DragonFly kernel List (threaded) for 2003-12
Re: SMP kernel on UP machines?
Matthew Dillon wrote:
I'm not entirely sure how to do this, because the IPI code depends on
the local APIC. If a cpu has HTT doesn't that mean that it must also
have a local APIC for each logical cpu?
The "logical" or "sibling" processor has its own local APIC. This
is necessary to send it the Startup IPI and soft IPIs while the system is
However, it is a full function APIC and can receive I/O interrupts. I have
seen this happen many times.
From Mobile Intel P4 with 533mhz system bus "specification update", Nov
Disabling a Local APIC Disables Both Logical Processor APICs on a
Hyper-Threading Technology Enabled Processor
Problem: Disabling a local APIC on one logical processor of a
Hyper-Threading Technology enabled processor by clearing bit 11 of the
IA32_APIC_BASE MSR will effectively disable the local APIC on the other
Implication: Disabling a local APIC on one logical processor prevents
the other logical processor from sending or receiving interrupts.
Multiprocessor Specification compliant BIOSs and multiprocessor
operating systems typically leave all local APICs enabled preventing any
end-user visible impact from this erratum.
Workaround: Do not disable the local APICs in a Hyper-Threading
Technology enabled processor.
Problem: When a system bus agent (processor or chipset) issues an
interrupt transaction without data onto the system bus and the
transaction receives a HardFailure response, a potential processor hang