core::arch::mips64 - Rust
Description: API documentation for the Rust `mips64` mod in crate `core`.
Keywords: rust, rustlang, rust-lang, mips64

# [−][src]Module core::arch::mips64

🔬 This is a nightly-only experimental API. (`stdsimd` #27731)
This is supported on MIPS-64 only.

Platform-specific intrinsics for the `mips64` platform.

See the module documentation for more details.

## Structs

v16i8 | ExperimentalMIPS-64
v16u8 | ExperimentalMIPS-64
v2f64 | ExperimentalMIPS-64
v2i64 | ExperimentalMIPS-64
v2u64 | ExperimentalMIPS-64
v4f32 | ExperimentalMIPS-64
v4i32 | ExperimentalMIPS-64
v4u32 | ExperimentalMIPS-64
v8i16 | ExperimentalMIPS-64
v8u16 | ExperimentalMIPS-64

## Functions

__msa_add_a_b⚠ | ExperimentalMIPS-64 and `msa` Vector Add Absolute Values.
__msa_add_a_d⚠ | ExperimentalMIPS-64 and `msa` Vector Add Absolute Values
__msa_add_a_h⚠ | ExperimentalMIPS-64 and `msa` Vector Add Absolute Values
__msa_add_a_w⚠ | ExperimentalMIPS-64 and `msa` Vector Add Absolute Values
__msa_adds_a_b⚠ | ExperimentalMIPS-64 and `msa` Signed Saturated Vector Saturated Add of Absolute Values
__msa_adds_a_d⚠ | ExperimentalMIPS-64 and `msa` Vector Saturated Add of Absolute Values
__msa_adds_a_h⚠ | ExperimentalMIPS-64 and `msa` Vector Saturated Add of Absolute Values
__msa_adds_a_w⚠ | ExperimentalMIPS-64 and `msa` Vector Saturated Add of Absolute Values
__msa_adds_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Add of Signed Values
__msa_adds_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Add of Signed Values
__msa_adds_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Add of Signed Values
__msa_adds_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Add of Signed Values
__msa_adds_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Add of Unsigned Values
__msa_adds_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Add of Unsigned Values
__msa_adds_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Add of Unsigned Values
__msa_adds_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Add of Unsigned Values
__msa_addv_b⚠ | ExperimentalMIPS-64 and `msa` Vector Add
__msa_addv_d⚠ | ExperimentalMIPS-64 and `msa` Vector Add
__msa_addv_h⚠ | ExperimentalMIPS-64 and `msa` Vector Add
__msa_addv_w⚠ | ExperimentalMIPS-64 and `msa` Vector Add
__msa_addvi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Add
__msa_addvi_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Add
__msa_addvi_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Add
__msa_addvi_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Add
__msa_and_v⚠ | ExperimentalMIPS-64 and `msa` Vector Logical And
__msa_andi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Logical And
__msa_asub_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Absolute Values of Signed Subtract
__msa_asub_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Absolute Values of Signed Subtract
__msa_asub_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Absolute Values of Signed Subtract
__msa_asub_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Absolute Values of Signed Subtract
__msa_asub_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Absolute Values of Unsigned Subtract
__msa_asub_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Absolute Values of Unsigned Subtract
__msa_asub_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Absolute Values of Unsigned Subtract
__msa_asub_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Absolute Values of Unsigned Subtract
__msa_ave_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Average
__msa_ave_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Average
__msa_ave_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Average
__msa_ave_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Average
__msa_ave_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Average
__msa_ave_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Average
__msa_ave_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Average
__msa_ave_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Average
__msa_aver_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Average Rounded
__msa_aver_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Average Rounded
__msa_aver_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Average Rounded
__msa_aver_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Average Rounded
__msa_aver_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Average Rounded
__msa_aver_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Average Rounded
__msa_aver_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Average Rounded
__msa_aver_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Average Rounded
__msa_bclr_b⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Clear
__msa_bclr_d⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Clear
__msa_bclr_h⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Clear
__msa_bclr_w⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Clear
__msa_bclri_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Clear
__msa_bclri_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Clear
__msa_bclri_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Clear
__msa_bclri_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Clear
__msa_binsl_b⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Insert Left
__msa_binsl_d⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Insert Left
__msa_binsl_h⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Insert Left
__msa_binsl_w⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Insert Left
__msa_binsli_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Insert Left
__msa_binsli_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Insert Left
__msa_binsli_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Insert Left
__msa_binsli_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Insert Left
__msa_binsr_b⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Insert Right
__msa_binsr_d⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Insert Right
__msa_binsr_h⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Insert Right
__msa_binsr_w⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Insert Right
__msa_binsri_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Insert Right
__msa_binsri_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Insert Right
__msa_binsri_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Insert Right
__msa_binsri_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Insert Right
__msa_bmnz_v⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Move If Not Zero
__msa_bmnzi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Move If Not Zero
__msa_bmz_v⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Move If Zero
__msa_bmzi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Move If Zero
__msa_bneg_b⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Negate
__msa_bneg_d⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Negate
__msa_bneg_h⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Negate
__msa_bneg_w⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Negate
__msa_bnegi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Negate
__msa_bnegi_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Negate
__msa_bnegi_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Negate
__msa_bnegi_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Negate
__msa_bnz_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If All Elements Are Not Zero
__msa_bnz_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If All Elements Are Not Zero
__msa_bnz_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If All Elements Are Not Zero
__msa_bnz_v⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If Not Zero (At Least One Element of Any Format Is Not Zero)
__msa_bnz_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If All Elements Are Not Zero
__msa_bsel_v⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Select
__msa_bseli_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Select
__msa_bset_b⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Set
__msa_bset_d⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Set
__msa_bset_h⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Set
__msa_bset_w⚠ | ExperimentalMIPS-64 and `msa` Vector Bit Set
__msa_bseti_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Set
__msa_bseti_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Set
__msa_bseti_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Set
__msa_bseti_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Bit Set
__msa_bz_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If At Least One Element Is Zero
__msa_bz_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If At Least One Element Is Zero
__msa_bz_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If At Least One Element Is Zero
__msa_bz_v⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If Zero (All Elements of Any Format Are Zero)
__msa_bz_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Branch If At Least One Element Is Zero
__msa_ceq_b⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Equal
__msa_ceq_d⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Equal
__msa_ceq_h⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Equal
__msa_ceq_w⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Equal
__msa_ceqi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Equal
__msa_ceqi_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Equal
__msa_ceqi_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Equal
__msa_ceqi_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Equal
__msa_cfcmsa⚠ | ExperimentalMIPS-64 and `msa` GPR Copy from MSA Control Register
__msa_cle_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Signed Less Than or Equal
__msa_cle_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Signed Less Than or Equal
__msa_cle_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Signed Less Than or Equal
__msa_cle_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Signed Less Than or Equal
__msa_cle_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Unsigned Less Than or Equal
__msa_cle_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Unsigned Less Than or Equal
__msa_cle_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Unsigned Less Than or Equal
__msa_cle_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Unsigned Less Than or Equal
__msa_clei_s_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Signed Less Than or Equal
__msa_clei_s_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Signed Less Than or Equal
__msa_clei_s_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Signed Less Than or Equal
__msa_clei_s_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Signed Less Than or Equal
__msa_clei_u_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Unsigned Less Than or Equal
__msa_clei_u_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Unsigned Less Than or Equal
__msa_clei_u_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Unsigned Less Than or Equal
__msa_clei_u_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Unsigned Less Than or Equal
__msa_clt_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Signed Less Than
__msa_clt_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Signed Less Than
__msa_clt_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Signed Less Than
__msa_clt_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Signed Less Than
__msa_clt_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Unsigned Less Than
__msa_clt_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Unsigned Less Than
__msa_clt_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Unsigned Less Than
__msa_clt_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Compare Unsigned Less Than
__msa_clti_s_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Signed Less Than
__msa_clti_s_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Signed Less Than
__msa_clti_s_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Signed Less Than
__msa_clti_s_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Signed Less Than
__msa_clti_u_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Unsigned Less Than
__msa_clti_u_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Unsigned Less Than
__msa_clti_u_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Unsigned Less Than
__msa_clti_u_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Compare Unsigned Less Than
__msa_copy_s_b⚠ | ExperimentalMIPS-64 and `msa` Element Copy to GPR Signed
__msa_copy_s_d⚠ | ExperimentalMIPS-64 and `msa` Element Copy to GPR Signed
__msa_copy_s_h⚠ | ExperimentalMIPS-64 and `msa` Element Copy to GPR Signed
__msa_copy_s_w⚠ | ExperimentalMIPS-64 and `msa` Element Copy to GPR Signed
__msa_copy_u_b⚠ | ExperimentalMIPS-64 and `msa` Element Copy to GPR Unsigned
__msa_copy_u_d⚠ | ExperimentalMIPS-64 and `msa` Element Copy to GPR Unsigned
__msa_copy_u_h⚠ | ExperimentalMIPS-64 and `msa` Element Copy to GPR Unsigned
__msa_copy_u_w⚠ | ExperimentalMIPS-64 and `msa` Element Copy to GPR Unsigned
__msa_ctcmsa⚠ | ExperimentalMIPS-64 and `msa` GPR Copy to MSA Control Register The content of the least significant 31 bits of GPR imm1 is copied to MSA control register cd Can not be tested in user mode
__msa_div_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Divide
__msa_div_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Divide
__msa_div_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Divide
__msa_div_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Divide
__msa_div_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Divide
__msa_div_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Divide
__msa_div_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Divide
__msa_div_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Divide
__msa_dotp_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product
__msa_dotp_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product
__msa_dotp_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product
__msa_dotp_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product
__msa_dotp_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product
__msa_dotp_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product
__msa_dpadd_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product and Add
__msa_dpadd_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product and Add
__msa_dpadd_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product and Add
__msa_dpadd_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product and Add
__msa_dpadd_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product and Add
__msa_dpadd_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product and Add
__msa_dpsub_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product and Add
__msa_dpsub_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product and Add
__msa_dpsub_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Dot Product and Add
__msa_dpsub_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product and Add
__msa_dpsub_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product and Add
__msa_dpsub_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Dot Product and Add
__msa_fadd_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Addition
__msa_fadd_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Addition
__msa_fcaf_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Always False
__msa_fcaf_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Always False
__msa_fceq_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Equal
__msa_fceq_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Equal
__msa_fclass_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Class Mask
__msa_fclass_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Class Mask
__msa_fcle_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Less or Equal
__msa_fcle_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Less or Equal
__msa_fclt_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Less Than
__msa_fclt_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Less Than
__msa_fcne_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Not Equal
__msa_fcne_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Not Equal
__msa_fcor_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Ordered
__msa_fcor_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Ordered
__msa_fcueq_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered or Equal
__msa_fcueq_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered or Equal
__msa_fcule_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered or Less or Equal
__msa_fcule_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered or Less or Equal
__msa_fcult_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered or Less Than
__msa_fcult_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered or Less Than
__msa_fcun_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered
__msa_fcun_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered
__msa_fcune_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered or Not Equal
__msa_fcune_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Quiet Compare Unordered or Not Equal
__msa_fdiv_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Division
__msa_fdiv_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Division
__msa_fexdo_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Down-Convert Interchange Format
__msa_fexp2_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Down-Convert Interchange Format
__msa_fexp2_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Down-Convert Interchange Format
__msa_fexupl_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Up-Convert Interchange Format Left
__msa_fexupr_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Up-Convert Interchange Format Left
__msa_ffint_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Round and Convert from Signed Integer
__msa_ffint_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Round and Convert from Signed Integer
__msa_ffint_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Round and Convert from Unsigned Integer
__msa_ffint_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Round and Convert from Unsigned Integer
__msa_ffql_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert from Fixed-Point Left
__msa_ffql_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert from Fixed-Point Left
__msa_ffqr_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert from Fixed-Point Left
__msa_ffqr_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert from Fixed-Point Left
__msa_fill_b⚠ | ExperimentalMIPS-64 and `msa` Vector Fill from GPR
__msa_fill_d⚠ | ExperimentalMIPS-64 and `msa` Vector Fill from GPR
__msa_fill_h⚠ | ExperimentalMIPS-64 and `msa` Vector Fill from GPR
__msa_fill_w⚠ | ExperimentalMIPS-64 and `msa` Vector Fill from GPR
__msa_flog2_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Base 2 Logarithm
__msa_flog2_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Base 2 Logarithm
__msa_fmadd_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Multiply-Add
__msa_fmadd_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Multiply-Add
__msa_fmax_a_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Maximum Based on Absolute Values
__msa_fmax_a_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Maximum Based on Absolute Values
__msa_fmax_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Maximum
__msa_fmax_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Maximum
__msa_fmin_a_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Minimum Based on Absolute Values
__msa_fmin_a_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Minimum Based on Absolute Values
__msa_fmin_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Minimum
__msa_fmin_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Minimum
__msa_fmsub_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Multiply-Sub
__msa_fmsub_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Multiply-Sub
__msa_fmul_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Multiplication
__msa_fmul_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Multiplication
__msa_frcp_d⚠ | ExperimentalMIPS-64 and `msa` Vector Approximate Floating-Point Reciprocal
__msa_frcp_w⚠ | ExperimentalMIPS-64 and `msa` Vector Approximate Floating-Point Reciprocal
__msa_frint_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Round to Integer
__msa_frint_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Round to Integer
__msa_frsqrt_d⚠ | ExperimentalMIPS-64 and `msa` Vector Approximate Floating-Point Reciprocal of Square Root
__msa_frsqrt_w⚠ | ExperimentalMIPS-64 and `msa` Vector Approximate Floating-Point Reciprocal of Square Root
__msa_fsaf_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Always False
__msa_fsaf_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Always False
__msa_fseq_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Equal
__msa_fseq_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Equal
__msa_fsle_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Less or Equal
__msa_fsle_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Less or Equal
__msa_fslt_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Less Than
__msa_fslt_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Less Than
__msa_fsne_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Not Equal
__msa_fsne_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Not Equal
__msa_fsor_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Ordered
__msa_fsor_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Ordered
__msa_fsqrt_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Square Root
__msa_fsqrt_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Square Root
__msa_fsub_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Subtraction
__msa_fsub_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Subtraction
__msa_fsueq_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Ordered
__msa_fsueq_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Ordered
__msa_fsule_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Unordered or Less or Equal
__msa_fsule_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Unordered or Less or Equal
__msa_fsult_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Unordered or Less Than
__msa_fsult_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Unordered or Less Than
__msa_fsun_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Unordered
__msa_fsun_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Unordered
__msa_fsune_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Unordered or Not Equal
__msa_fsune_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Signaling Compare Unordered or Not Equal
__msa_ftint_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert to Signed Integer
__msa_ftint_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert to Signed Integer
__msa_ftint_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert to Unsigned Integer
__msa_ftint_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert to Unsigned Integer
__msa_ftq_h⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert to Fixed-Point
__msa_ftq_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Convert to Fixed-Point
__msa_ftrunc_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Truncate and Convert to Signed Integer
__msa_ftrunc_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Truncate and Convert to Signed Integer
__msa_ftrunc_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Truncate and Convert to Unsigned Integer
__msa_ftrunc_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Floating-Point Truncate and Convert to Unsigned Integer
__msa_hadd_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Horizontal Add
__msa_hadd_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Horizontal Add
__msa_hadd_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Horizontal Add
__msa_hadd_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Horizontal Add
__msa_hadd_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Horizontal Add
__msa_hadd_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Horizontal Add
__msa_hsub_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Horizontal Subtract
__msa_hsub_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Horizontal Subtract
__msa_hsub_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Horizontal Subtract
__msa_hsub_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Horizontal Subtract
__msa_hsub_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Horizontal Subtract
__msa_hsub_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Horizontal Subtract
__msa_ilvev_b⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Even
__msa_ilvev_d⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Even
__msa_ilvev_h⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Even
__msa_ilvev_w⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Even
__msa_ilvl_b⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Left
__msa_ilvl_d⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Left
__msa_ilvl_h⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Left
__msa_ilvl_w⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Left
__msa_ilvod_b⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Odd
__msa_ilvod_d⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Odd
__msa_ilvod_h⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Odd
__msa_ilvod_w⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Odd
__msa_ilvr_b⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Right
__msa_ilvr_d⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Right
__msa_ilvr_h⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Right
__msa_ilvr_w⚠ | ExperimentalMIPS-64 and `msa` Vector Interleave Right
__msa_insert_b⚠ | ExperimentalMIPS-64 and `msa` GPR Insert Element
__msa_insert_d⚠ | ExperimentalMIPS-64 and `msa` GPR Insert Element
__msa_insert_h⚠ | ExperimentalMIPS-64 and `msa` GPR Insert Element
__msa_insert_w⚠ | ExperimentalMIPS-64 and `msa` GPR Insert Element
__msa_insve_b⚠ | ExperimentalMIPS-64 and `msa` Element Insert Element
__msa_insve_d⚠ | ExperimentalMIPS-64 and `msa` Element Insert Element
__msa_insve_h⚠ | ExperimentalMIPS-64 and `msa` Element Insert Element
__msa_insve_w⚠ | ExperimentalMIPS-64 and `msa` Element Insert Element
__msa_ld_b⚠ | ExperimentalMIPS-64 and `msa` Vector Load
__msa_ld_d⚠ | ExperimentalMIPS-64 and `msa` Vector Load
__msa_ld_h⚠ | ExperimentalMIPS-64 and `msa` Vector Load
__msa_ld_w⚠ | ExperimentalMIPS-64 and `msa` Vector Load
__msa_ldi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Load
__msa_ldi_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Load
__msa_ldi_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Load
__msa_ldi_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Load
__msa_madd_q_h⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply and Add
__msa_madd_q_w⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply and Add
__msa_maddr_q_h⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply and Add Rounded
__msa_maddr_q_w⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply and Add Rounded
__msa_maddv_b⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply and Add
__msa_maddv_d⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply and Add
__msa_maddv_h⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply and Add
__msa_maddv_w⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply and Add
__msa_max_a_b⚠ | ExperimentalMIPS-64 and `msa` Vector Maximum Based on Absolute Values
__msa_max_a_d⚠ | ExperimentalMIPS-64 and `msa` Vector Maximum Based on Absolute Values
__msa_max_a_h⚠ | ExperimentalMIPS-64 and `msa` Vector Maximum Based on Absolute Values
__msa_max_a_w⚠ | ExperimentalMIPS-64 and `msa` Vector Maximum Based on Absolute Values
__msa_max_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Maximum
__msa_max_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Maximum
__msa_max_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Maximum
__msa_max_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Maximum
__msa_max_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Maximum
__msa_max_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Maximum
__msa_max_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Maximum
__msa_max_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Maximum
__msa_maxi_s_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Maximum
__msa_maxi_s_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Maximum
__msa_maxi_s_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Maximum
__msa_maxi_s_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Maximum
__msa_maxi_u_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Maximum
__msa_maxi_u_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Maximum
__msa_maxi_u_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Maximum
__msa_maxi_u_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Maximum
__msa_min_a_b⚠ | ExperimentalMIPS-64 and `msa` Vector Minimum Based on Absolute Value
__msa_min_a_d⚠ | ExperimentalMIPS-64 and `msa` Vector Minimum Based on Absolute Value
__msa_min_a_h⚠ | ExperimentalMIPS-64 and `msa` Vector Minimum Based on Absolute Value
__msa_min_a_w⚠ | ExperimentalMIPS-64 and `msa` Vector Minimum Based on Absolute Value
__msa_min_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Minimum
__msa_min_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Minimum
__msa_min_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Minimum
__msa_min_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Minimum
__msa_min_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Minimum
__msa_min_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Minimum
__msa_min_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Minimum
__msa_min_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Minimum
__msa_mini_s_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Minimum
__msa_mini_s_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Minimum
__msa_mini_s_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Minimum
__msa_mini_s_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Minimum
__msa_mini_u_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Minimum
__msa_mini_u_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Minimum
__msa_mini_u_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Minimum
__msa_mini_u_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Minimum
__msa_mod_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Modulo
__msa_mod_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Modulo
__msa_mod_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Modulo
__msa_mod_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Modulo
__msa_mod_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Modulo
__msa_mod_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Modulo
__msa_mod_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Modulo
__msa_mod_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Modulo
__msa_move_v⚠ | ExperimentalMIPS-64 and `msa` Vector Move
__msa_msub_q_h⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply and Subtract
__msa_msub_q_w⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply and Subtract
__msa_msubr_q_h⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply and Subtract Rounded
__msa_msubr_q_w⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply and Subtract Rounded
__msa_msubv_b⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply and Subtract
__msa_msubv_d⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply and Subtract
__msa_msubv_h⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply and Subtract
__msa_msubv_w⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply and Subtract
__msa_mul_q_h⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply
__msa_mul_q_w⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply
__msa_mulr_q_h⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply Rounded
__msa_mulr_q_w⚠ | ExperimentalMIPS-64 and `msa` Vector Fixed-Point Multiply Rounded
__msa_mulv_b⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply
__msa_mulv_d⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply
__msa_mulv_h⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply
__msa_mulv_w⚠ | ExperimentalMIPS-64 and `msa` Vector Multiply
__msa_nloc_b⚠ | ExperimentalMIPS-64 and `msa` Vector Leading Ones Count
__msa_nloc_d⚠ | ExperimentalMIPS-64 and `msa` Vector Leading Ones Count
__msa_nloc_h⚠ | ExperimentalMIPS-64 and `msa` Vector Leading Ones Count
__msa_nloc_w⚠ | ExperimentalMIPS-64 and `msa` Vector Leading Ones Count
__msa_nlzc_b⚠ | ExperimentalMIPS-64 and `msa` Vector Leading Zeros Count
__msa_nlzc_d⚠ | ExperimentalMIPS-64 and `msa` Vector Leading Zeros Count
__msa_nlzc_h⚠ | ExperimentalMIPS-64 and `msa` Vector Leading Zeros Count
__msa_nlzc_w⚠ | ExperimentalMIPS-64 and `msa` Vector Leading Zeros Count
__msa_nor_v⚠ | ExperimentalMIPS-64 and `msa` Vector Logical Negated Or
__msa_nori_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Logical Negated Or
__msa_or_v⚠ | ExperimentalMIPS-64 and `msa` Vector Logical Or
__msa_ori_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Logical Or
__msa_pckev_b⚠ | ExperimentalMIPS-64 and `msa` Vector Pack Even
__msa_pckev_d⚠ | ExperimentalMIPS-64 and `msa` Vector Pack Even
__msa_pckev_h⚠ | ExperimentalMIPS-64 and `msa` Vector Pack Even
__msa_pckev_w⚠ | ExperimentalMIPS-64 and `msa` Vector Pack Even
__msa_pckod_b⚠ | ExperimentalMIPS-64 and `msa` Vector Pack Odd
__msa_pckod_d⚠ | ExperimentalMIPS-64 and `msa` Vector Pack Odd
__msa_pckod_h⚠ | ExperimentalMIPS-64 and `msa` Vector Pack Odd
__msa_pckod_w⚠ | ExperimentalMIPS-64 and `msa` Vector Pack Odd
__msa_pcnt_b⚠ | ExperimentalMIPS-64 and `msa` Vector Population Count
__msa_pcnt_d⚠ | ExperimentalMIPS-64 and `msa` Vector Population Count
__msa_pcnt_h⚠ | ExperimentalMIPS-64 and `msa` Vector Population Count
__msa_pcnt_w⚠ | ExperimentalMIPS-64 and `msa` Vector Population Count
__msa_sat_s_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Saturate
__msa_sat_s_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Saturate
__msa_sat_s_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Saturate
__msa_sat_s_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Signed Saturate
__msa_sat_u_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Saturate
__msa_sat_u_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Saturate
__msa_sat_u_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Saturate
__msa_sat_u_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Unsigned Saturate
__msa_shf_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Set Shuffle Elements
__msa_shf_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Set Shuffle Elements
__msa_shf_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Set Shuffle Elements
__msa_sld_b⚠ | ExperimentalMIPS-64 and `msa` GPR Columns Slide
__msa_sld_d⚠ | ExperimentalMIPS-64 and `msa` GPR Columns Slide
__msa_sld_h⚠ | ExperimentalMIPS-64 and `msa` GPR Columns Slide
__msa_sld_w⚠ | ExperimentalMIPS-64 and `msa` GPR Columns Slide
__msa_sldi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Columns Slide
__msa_sldi_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Columns Slide
__msa_sldi_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Columns Slide
__msa_sldi_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Columns Slide
__msa_sll_b⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Left
__msa_sll_d⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Left
__msa_sll_h⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Left
__msa_sll_w⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Left
__msa_slli_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Left
__msa_slli_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Left
__msa_slli_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Left
__msa_slli_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Left
__msa_splat_b⚠ | ExperimentalMIPS-64 and `msa` GPR Element Splat
__msa_splat_d⚠ | ExperimentalMIPS-64 and `msa` GPR Element Splat
__msa_splat_h⚠ | ExperimentalMIPS-64 and `msa` GPR Element Splat
__msa_splat_w⚠ | ExperimentalMIPS-64 and `msa` GPR Element Splat
__msa_splati_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Element Splat
__msa_splati_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Element Splat
__msa_splati_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Element Splat
__msa_splati_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Element Splat
__msa_sra_b⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Arithmetic
__msa_sra_d⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Arithmetic
__msa_sra_h⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Arithmetic
__msa_sra_w⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Arithmetic
__msa_srai_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Arithmetic
__msa_srai_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Arithmetic
__msa_srai_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Arithmetic
__msa_srai_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Arithmetic
__msa_srar_b⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Arithmetic Rounded
__msa_srar_d⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Arithmetic Rounded
__msa_srar_h⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Arithmetic Rounded
__msa_srar_w⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Arithmetic Rounded
__msa_srari_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Arithmetic Rounded
__msa_srari_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Arithmetic Rounded
__msa_srari_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Arithmetic Rounded
__msa_srari_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Arithmetic Rounded
__msa_srl_b⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Logical
__msa_srl_d⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Logical
__msa_srl_h⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Logical
__msa_srl_w⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Logical
__msa_srli_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Logical
__msa_srli_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Logical
__msa_srli_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Logical
__msa_srli_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Logical
__msa_srlr_b⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Logical Rounded
__msa_srlr_d⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Logical Rounded
__msa_srlr_h⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Logical Rounded
__msa_srlr_w⚠ | ExperimentalMIPS-64 and `msa` Vector Shift Right Logical Rounded
__msa_srlri_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Logical Rounded
__msa_srlri_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Logical Rounded
__msa_srlri_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Logical Rounded
__msa_srlri_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Shift Right Logical Rounded
__msa_st_b⚠ | ExperimentalMIPS-64 and `msa` Vector Store
__msa_st_d⚠ | ExperimentalMIPS-64 and `msa` Vector Store
__msa_st_h⚠ | ExperimentalMIPS-64 and `msa` Vector Store
__msa_st_w⚠ | ExperimentalMIPS-64 and `msa` Vector Store
__msa_subs_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Subtract of Signed Values
__msa_subs_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Subtract of Signed Values
__msa_subs_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Subtract of Signed Values
__msa_subs_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Subtract of Signed Values
__msa_subs_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Subtract of Unsigned Values
__msa_subs_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Subtract of Unsigned Values
__msa_subs_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Subtract of Unsigned Values
__msa_subs_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Subtract of Unsigned Values
__msa_subsus_u_b⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Subtract of Signed from Unsigned
__msa_subsus_u_d⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Subtract of Signed from Unsigned
__msa_subsus_u_h⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Subtract of Signed from Unsigned
__msa_subsus_u_w⚠ | ExperimentalMIPS-64 and `msa` Vector Unsigned Saturated Subtract of Signed from Unsigned
__msa_subsuu_s_b⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Subtract of Unsigned Values
__msa_subsuu_s_d⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Subtract of Unsigned Values
__msa_subsuu_s_h⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Subtract of Unsigned Values
__msa_subsuu_s_w⚠ | ExperimentalMIPS-64 and `msa` Vector Signed Saturated Subtract of Unsigned Values
__msa_subv_b⚠ | ExperimentalMIPS-64 and `msa` Vector Subtract
__msa_subv_d⚠ | ExperimentalMIPS-64 and `msa` Vector Subtract
__msa_subv_h⚠ | ExperimentalMIPS-64 and `msa` Vector Subtract
__msa_subv_w⚠ | ExperimentalMIPS-64 and `msa` Vector Subtract
__msa_subvi_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Subtract
__msa_subvi_d⚠ | ExperimentalMIPS-64 and `msa` Immediate Subtract
__msa_subvi_h⚠ | ExperimentalMIPS-64 and `msa` Immediate Subtract
__msa_subvi_w⚠ | ExperimentalMIPS-64 and `msa` Immediate Subtract
__msa_vshf_b⚠ | ExperimentalMIPS-64 and `msa` Vector Data Preserving Shuffle
__msa_vshf_d⚠ | ExperimentalMIPS-64 and `msa` Vector Data Preserving Shuffle
__msa_vshf_h⚠ | ExperimentalMIPS-64 and `msa` Vector Data Preserving Shuffle
__msa_vshf_w⚠ | ExperimentalMIPS-64 and `msa` Vector Data Preserving Shuffle
__msa_xor_v⚠ | ExperimentalMIPS-64 and `msa` Vector Logical Exclusive Or
__msa_xori_b⚠ | ExperimentalMIPS-64 and `msa` Immediate Logical Exclusive Or
break_⚠ | ExperimentalMIPS-64 Generates the trap instruction `BREAK`

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