Copyright (c) 2003-2023 The DragonFly Project. Copyright (c) 1992-2003 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. DragonFly 6.5-DEVELOPMENT #16: Mon Jan 15 06:24:31 UTC 2024 root@elitebook:/usr/obj/usr/src/sys/X86_64_GENERIC acpi_hpet: frequency 14318180 Using cputimer HPET for TSC calibration Timer latency (in TSC ticks): 2569 min=2289 max=2583 TSC invariant clock: 2099998615 Hz CPU: AMD Ryzen 5 PRO 3500U w/ Radeon Vega Mobile Gfx (2100.00-MHz K8-class CPU) Origin="AuthenticAMD" Id=0x810f81 Family=0x17 Model=0x18 Stepping=1 Features=0x178bfbff Features2=0x76d8320b XSAVE Features=0xf AMD Features=0x2e500800 AMD Features2=0x35c233ff Structured Extended Features=0x209c01a9 Thermal and PM Features=0x4 MONITOR/MWAIT Features=0x3 CPU Special Features Installed: SMAP SMEP real memory = 14962475008 (14269 MB) avail memory = 14370779136 (13705 MB) madt_lapic_probe: lapic_count=8 x2apic_count=0 ACPI CPUS = 8 LAPIC AMD elvt0: 0x00010000 LAPIC AMD elvt1: 0x00010000 LAPIC AMD elvt2: 0x00010000 LAPIC AMD elvt3: 0x00010000 LAPIC latency (in TSC ticks): 216 min: 210 max: 231 lapic: divisor index 0, frequency 12499993 Hz core_bits 4 logical_CPU_bits 0 2-way htt, 1 Nodes, 8 cores/node CPU Topology: cores_per_chip: 4; threads_per_core: 2; chips_per_package: 1; Compute unit iDS: 0-0; srat_probe: can't locate SRAT Initialize MI interrupts for 8 cpus TSC testing MP synchronization ... TSC testing MP: NOTE! CPU pwrsave will inflate latencies! TSC cpu-delta test complete, 2530nS to 5470nS SUCCESS TSC cpu-delta test complete, 1780nS to 3440nS SUCCESS TSC cpu-delta test complete, 1790nS to 3340nS SUCCESS TSC cpu-delta test complete, 1910nS to 3410nS SUCCESS TSC cpu concurrency test complete, worst=270ns, avg=104ns SUCCESS TSC is MP synchronized TSC: cputimer freq 2099998615 Spectre: support=( IBPB ) req=0000 operating=( none ) MDS: support=( MDS_NOT_REQUIRED ) req=0000 operating=( none ) interrupt uses mplock: swi_taskq wdog: In-kernel automatic watchdog reset enabled md0: Malloc disk evdev device loaded. kbd1 at kbdmux0 ACPI: RSDP 0x000000003974D014 000024 (v02 HPQOEM) ACPI: XSDT 0x000000003971F188 000124 (v01 HPQOEM SLIC-BPC 00000001 01000013) ACPI: FACP 0x000000003973D000 00010C (v05 HPQOEM SLIC-BPC 00000001 HP 00000001) ACPI: DSDT 0x0000000039725000 010DE9 (v02 HPQOEM 8589 00000000 INTL 20160527) ACPI: FACS 0x0000000039614000 000040 ACPI: SSDT 0x000000003974B000 0002D7 (v01 HP NVTEC 00000001 INTL 20160527) ACPI: SSDT 0x000000003974A000 00012A (v02 HP ShmTable 00000001 INTL 20160527) ACPI: SSDT 0x0000000039744000 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) ACPI: UEFI 0x000000003962F000 000042 (v01 HPQOEM EDK2 00000002 01000013) ACPI: RTMA 0x0000000039742000 00009E (v01 HP _HBMART_ 00001000 HP 00000001) ACPI: SSDT 0x0000000039740000 001575 (v02 HP UcsiAcpi 00000001 INTL 20160527) ACPI: SSDT 0x000000003973F000 0000FB (v02 HP UcsiCntr 00000001 INTL 20160527) ACPI: OEML 0x000000003973E000 000028 (v03 HPQOEM EDK2 00000002 01000013) ACPI: ASF! 0x000000003973C000 00006E (v32 HPQOEM 8589 00000001 HP 00000001) ACPI: MSDM 0x000000003973B000 000055 (v03 HPQOEM SLIC-BPC 00000000 HP 00000001) ACPI: SLIC 0x000000003973A000 000176 (v01 HPQOEM SLIC-BPC 00000001 HP 00000001) ACPI: WSMT 0x0000000039739000 000028 (v01 HPQOEM 8589 00000001 HP 00000001) ACPI: HPET 0x0000000039738000 000038 (v01 HPQOEM 8589 00000001 HP 00000001) ACPI: APIC 0x0000000039737000 000138 (v02 HPQOEM 8589 00000001 HP 00000001) ACPI: MCFG 0x0000000039736000 00003C (v01 HPQOEM 8589 00000001 HP 00000001) ACPI: SSDT 0x0000000039722000 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) ACPI: CRAT 0x0000000039721000 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) ACPI: CDIT 0x0000000039720000 000029 (v01 AMD AMD CDIT 00000001 AMD 00000001) ACPI: SSDT 0x000000003974C000 00013B (v01 HP HPNBCONV 00001000 INTL 20160527) ACPI: SSDT 0x000000003971E000 000245 (v01 HP AMDTPL 00001000 INTL 20160527) ACPI: SSDT 0x000000003971D000 00097D (v01 HP HPADNBWL 00001000 INTL 20160527) ACPI: SSDT 0x000000003971C000 000032 (v01 HP HPCONDEV 00001000 INTL 20160527) ACPI: SSDT 0x000000003971B000 000069 (v01 HP HPCAHWID 00001000 INTL 20160527) ACPI: VFCT 0x000000003970D000 00D484 (v01 HPQOEM SLIC-BPC 00000001 AMD 31504F47) ACPI: SSDT 0x0000000039724000 000949 (v01 AMD AmdTable 00000001 INTL 20160527) ACPI: FPDT 0x000000003970C000 000044 (v01 HPQOEM EDK2 00000002 01000013) ACPI: SSDT 0x0000000039709000 00255E (v01 AMD AmdTable 00000001 INTL 20160527) ACPI: BGRT 0x0000000039708000 000038 (v01 HPQOEM EDK2 00000002 01000013) ACPI: SSDT 0x0000000039707000 000668 (v01 AMD AmdTable 00000001 INTL 20160527) ACPI: SSDT 0x0000000039743000 0002F9 (v02 HP PwrCtlEv 00000001 INTL 20160527) ACPI: IVRS 0x0000000039706000 00013E (v02 AMD AMD IVRS 00000001 AMD 00000000) sc0: on motherboard sc0: EFI_FB <16 virtual consoles, flags=0x700> cryptosoft0: on motherboard acpi0: on motherboard Firmware Error (ACPI): Could not resolve symbol [\_SB.PCI0.LPC0.EC0], AE_NOT_FOUND (20211217/dswload2-315) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20211217/psobject-372) ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010) ACPI: 16 ACPI AML tables successfully acquired and loaded ACPI FADT: SCI testing interrupt mode ... ACPI FADT: SCI select level/low acpi0: Power Button (fixed) acpi_hpet0: iomem 0xfed00000-0xfed003ff on acpi0 acpi_timer0 on acpi0 cpu0: on acpi0 cpu_cst0: on cpu0 cpu_pst0: on cpu0 cpu1: on acpi0 cpu_cst1: on cpu1 cpu_pst1: on cpu1 cpu2: on acpi0 cpu_cst2: on cpu2 cpu_pst2: on cpu2 cpu3: on acpi0 cpu_cst3: on cpu3 cpu_pst3: on cpu3 cpu4: on acpi0 cpu_cst4: on cpu4 cpu_pst4: on cpu4 cpu5: on acpi0 cpu_cst5: on cpu5 cpu_pst5: on cpu5 cpu6: on acpi0 cpu_cst6: on cpu6 cpu_pst6: on cpu6 cpu7: on acpi0 cpu_cst7: on cpu7 cpu_pst7: on cpu7 acpi_ec0: port 0x66,0x62 on acpi0 acpi_button0: on acpi0 battery0: on acpi0 battery0: supports extended information acpi_acad0: on acpi0 acpi_button1: on acpi0 acpi_lid0: on acpi0 acpi_tz0: on acpi0 acpi_tz1: on acpi0 acpi_tz2: on acpi0 acpi_tz3: on acpi0 acpi_tz4: on acpi0 acpi_tz5: on acpi0 Firmware Error (ACPI): AE_AML_PACKAGE_LIMIT, Index (0x000000005) is beyond end of object (length 0x5) (20211217/exoparg2-571) ACPI Error: Aborting method \_TZ.GETP due to previous error (AE_AML_PACKAGE_LIMIT) (20211217/psparse-689) ACPI Error: Aborting method \_TZ.CHGZ._CRT due to previous error (AE_AML_PACKAGE_LIMIT) (20211217/psparse-689) acpi_tz6: on acpi0 pcib0: port 0xcf8-0xcff on acpi0 pci0: on pcib0 amdsmn0: on hostb0 amdtemp0: on hostb0 amdtemp0: sc_ccd_offset = 00000300 pci0: (vendor 0x1022, dev 0x15d1) at device 0.2 pcib1: at device 1.3 on pci0 pci1: on pcib1 re0: port 0x4300-0x43ff mem 0xf0900000-0xf0903fff,0xf0914000-0xf0914fff at device 0.0 on pci1 re0: MAC version 0x50200000, MACFG 67, support MSI re0: bus speed 125MHz re0: MAC address: 84:2a:fd:c8:9b:ee pci1: (vendor 0x10ec, dev 0x816a) at device 0.1 pci1: (vendor 0x10ec, dev 0x816b) at device 0.2 pci1: (vendor 0x10ec, dev 0x816c) at device 0.3 ehci0: mem 0xf0910000-0xf0913fff,0xf0918000-0xf0918fff at device 0.4 on pci1 ehci0: pre-2.0 USB revision (ignored) usbus0: EHCI version 1.0 usbus0 on ehci0 usbus0: 480Mbps High Speed USB v2.0 nvme0: mem 0xf0700000-0xf0703fff at device 0.0 on pci3 nvme0: mapped 9 MSIX IRQs ugen0.1: <0x10ec> at usbus0 uhub0: <0x10ec EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus0 nvme0: NVME Version 1.3 maxqe=16384 caps=000000303c033fff nvme0: Model SAMSUNG_MZVLQ256HAJD-000H1 BaseSerial S4UJNF2N788664 nscount=1 nvme0: Request 16/8 queues, Returns 12/8 queues, nominal map 1:1 cpu nvme0: Interrupt Coalesce: 100uS / 4 qentries nvme0: Disk nvme0 ns=1 blksize=512 lbacnt=500118192 cap=238GB serno=S4UJNF2N788664-1 pcib4: at device 8.1 on pci0 pci4: on pcib4 (PCIB_BCR_VGA_ENABLE) config = 0 vgapci0: port 0x2000-0x20ff mem 0xf0600000-0xf067ffff,0xf0000000-0xf01fffff,0xe0000000-0xefffffff at device 0.0 on pci4 (PCIB_BCR_VGA_ENABLE) config = 0 pci4: (vendor 0x1002, dev 0x15de) at device 0.1 pci4: (vendor 0x1022, dev 0x15df) at device 0.2 xhci0: mem 0xf0200000-0xf02fffff at device 0.3 on pci4 xhci0: 64 bytes context size, 64-bit DMA usbus1 on xhci0 usbus1: 5.0Gbps Super Speed USB v3.0 xhci1: 64 bytes context size, 64-bit DMA ugen1.1: <0x1022> at usbus1 uhub1: <0x1022 XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus1 usbus2 on xhci1 usbus2: 5.0Gbps Super Speed USB v3.0 atkbdc0: port 0x64,0x60 irq 1 on acpi0 atkbd0: irq 1 on atkbdc0 kbd0 at atkbd0 uhub0: 1 port with 1 removable, self powered uhub2: 3 ports with 3 removable, self powered uhub1: 8 ports with 8 removable, self powered ugen2.2: at usbus2 uhub3: on usbus2 uhub3: MTT enabled ugen1.2: at usbus1 uhub4: on usbus1 psm0: irq 12 on atkbdc0 interrupt uses mplock: psm0 psm0: model Generic PS/2 mouse, device ID 0 ACPI: Enabled 7 GPEs in block 00 to 1F aesni0: on motherboard padlock0: No ACE support. rdrand0: on motherboard uhub3: 4 ports with 0 removable, self powered sio0: can't drain, serial port might not exist, disabling sio1: can't drain, serial port might not exist, disabling Firmware Error (ACPI): AE_AML_PACKAGE_LIMIT, Index (0x000000005) is beyond end of object (length 0x5) (20211217/exoparg2-571) ACPI Error: Aborting method \_TZ.GTTP due to previous error (AE_AML_PACKAGE_LIMIT) (20211217/psparse-689) ACPI Error: Aborting method \_TZ.CHGZ._TMP due to previous error (AE_AML_PACKAGE_LIMIT) (20211217/psparse-689) hpt27xx: no controller detected. CAM: Configuring 0 busses CAM: finished configuring all busses uhub4: 5 ports with 1 removable, self powered ugen2.3: at usbus2 ugen2.4: at usbus2 ugen1.3: at usbus1 uhid0: on usbus1 ugen1.4: at usbus1 uhub5: on usbus1 uhub5: 4 ports with 4 removable, self powered ugen1.5: at usbus1 uhid1: on usbus1 ugen1.6: at usbus1 uhub6: on usbus1 uhub6: 4 ports with 1 removable, self powered ugen1.7: at usbus1 uhub7: on usbus1 uhub7: 4 ports with 4 removable, self powered ugen1.8: at usbus1 Mounting root from ufs:serno/S4UJNF2N788664-1.s2d DMA space used: 3292k, remaining available: 131072k Mounting devfs Firmware Error (ACPI): AE_AML_PACKAGE_LIMIT, Index (0x000000005) is beyond end of object (length 0x5) (20211217/exoparg2-571) ACPI Error: Aborting method \_TZ.GTTP due to previous error (AE_AML_PACKAGE_LIMIT) (20211217/psparse-689) ACPI Error: Aborting method \_TZ.CHGZ._TMP due to previous error (AE_AML_PACKAGE_LIMIT) (20211217/psparse-689) Firmware Error (ACPI): AE_AML_PACKAGE_LIMIT, Index (0x000000005) is beyond end of object (length 0x5) (20211217/exoparg2-571) ACPI Error: Aborting method \_TZ.GTTP due to previous error (AE_AML_PACKAGE_LIMIT) (20211217/psparse-689) ACPI Error: Aborting method \_TZ.CHGZ._TMP due to previous error (AE_AML_PACKAGE_LIMIT) (20211217/psparse-689) uaudio0: on usbus1 swap low/high-water marks set to 167769/251654 uaudio0: Play: 48000 Hz, 2 ch, 16-bit S-LE PCM format, 2x8ms buffer. uaudio0: Record: 48000 Hz, 2 ch, 16-bit S-LE PCM format, 2x8ms buffer. uaudio0: No MIDI sequencer. pcm0: on uaudio0 uaudio0: No HID volume keys found. cdce0: on usbus1 ue0: on cdce0 ue0: MAC address: 84:2a:fd:c8:9b:f0 [drm:pid867:drm_core_init] Initialized [drm] amdgpu kernel modesetting enabled. drm0 on vgapci0 [drm] pdev: vendor=0x1002 device=0x15d8 rev=0xd2 [drm] svendor=0x103c sdevice=0x8589 irq=17 vgapci0: child drm0 requested pci_enable_io v g<118>Jan 15 07:30:23 elitebook kernel: [drm] amdgpu kernel modesetting enabled. apci0: child drm0 requested pci_enable_io 7>[drm:pid867:drm_minor_regi ster] [drm:pid867:drm_minor_register] new minor registered 128 [drm:pid867:drm_minor_register] [drm:pid867:drm_minor_register] new minor egistered 0 amdgpu_driver_load_kms(): fl ags=131094 drm_device=0xfffff8013c302e00 adev=0xfffff8031e420000 amdgpu_device_init: start [drm] initializing kernel modesetting (RAVEN 0x1002:0x15D8 0x103C:0x8589 0xD2). amdgpu_device_init: 1 [drm] register mmio base: 0xF0600000 [drm] register mmio size: 524288 pci_resource_flags: pdev=0xfffff8012f4ec800 bar=2 type=MEM amdgpu_device_init: 2 amdgpu_device_init: for loop 0 amdgpu_device_init: for loop 1 amdgpu_device_init: for loop 2 amdgpu_device_init: for loop 3 amdgpu_device_init: for loop 4 amdgpu_device_init: rio_rid=32 amdgpu_device_init: mem_size=256 amdgpu_device_init: 3 [drm] add ip block number 0 [drm] add ip block number 1 [drm] add ip block number 2 [drm] add ip block number 3 [drm] add ip block number 4 [drm] add ip block number 5 [drm] add ip block number 6 [drm] add ip block number 7 [drm] add ip block number 8 7>[drm:pid867:amdgpu_ucode_print_gpu_info_hdr] GPU_INFO [drm:pid867:amdgpu_ucode_print_common_hdr] size_bytes: 316 [drm:pid867:am dgpu_ucode_print_common_hdr] header_size_bytes: 36 [drm:pid867:amdgpu_ucode_print_common_hdr] header_version_major: 1 [drm:pid867:amdgpu_ucode_print_common_hdr] hea der_version_minor: 0 [drm:pid867:amdgpu_ucode_print_common_hdr] ip_version_major: 9 [drm:pid867:amdgpu_ucode_print_common_hdr] ip_version_minor: 0 [drm:pid86 7:amdgpu_ucode_print_common_hdr] ucode_version: 0x00000001 [drm:pid867:amdgpu_ucode_print_common_hdr] ucode_size_bytes: 60 [drm:pid86 7:amdgpu_ucode_print_common_hdr] ucode_array_offset_bytes: 256 [drm:pid867:amdgpu_ucode_print_common_hdr] crc32: 0x09f31aee [drm:pid867:amdgpu_ucode_print_gpu_info_hdr] version_major: 1 [drm:pid867:amdgpu_ucode_print_gpu_info_hdr] version_minor: 0 6>[drm] VCN decode is enabled in VM mode [drm] VCN encode is enabled in VM mode [drm] VCN jpeg decode is enabled in VM mode amdgpu_device_init: 4 7>[drm:pid867:check_atom_bios] ATOMBIOS detected amdgpu_device_init: 5 ATOM BIOS: SWBRT48929.001 [drm:pid867:amdgpu_atomfirmware_allocate_fb_scratch] a tom firmware requested 00000000 0kb fw 0kb drv a mdgpu_device_init: 6 amdgpu_device_init: 6.1 amdgpu_device_init: 7 amdgpu_device_init: 8 6>[drm] vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is 9-bit amdgpu: No suitable DMA available. amdgpu: No coherent DMA available. d rm0: info: VRAM: 2048M 0x000000F400000000 - 0x000000F47FFFFFFF (2048M used) drm0: info: GART: 1024M 0x0000000000000 000 - 0x000000003FFFFFFF drm0: info: AGP: 267419648M 0x000000F800000000 - 0x0000FFFFFFFFFFFF 6>[drm] Detected VRAM RAM=2048M, BAR=256M [drm] RAM wi dth 128bits DDR4 6>[TTM] Zone kernel: Available graphics memory: 65536 kiB [TTM] Zone dma32: Available graphics memory: 65536 kiB [TTM] I nitializing pool allocator 6>[drm] amdgpu: 2048M of VRAM memory ready [drm] amdgpu: 3072M of GTT memory ready. 6>[drm] GART: num cpu pages 262144, num gpu pages 262144 [drm] PCIE GART of 1024M enabled (table at 0x000000F4007E9000). ttm_check_under_lowerlimit: stub [drm:pid867:drm_irq_install] irq=17 [drm:pid867:amdgpu_irq_init] amdgpu: irq initialized. [drm:pid867:psp_v10_0_init_microcode] [drm:pid867:gfx_v9_0_init_microcode] ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 0 use gpu addr 0x0000000000400040, cpu addr 0x0xffffb80000101040 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 1 use gpu addr 0x00000000004000c0, cpu addr 0x0xffffb800001010c0 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 2 use gpu addr 0x0000000000400140, cpu addr 0x0xffffb80000101140 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 3 use gpu addr 0x00000000004001c0, cpu addr 0x0xffffb800001011c0 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 4 use gpu addr 0x0000000000400240, cpu addr 0x0xffffb80000101240 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 5 use gpu addr 0x00000000004002c0, cpu addr 0x0xffffb800001012c0 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 6 use gpu addr 0x0000000000400340, cpu addr 0x0xffffb80000101340 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 7 use gpu addr 0x00000000004003c0, cpu addr 0x0xffffb800001013c0 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 8 use gpu addr 0x0000000000400440, cpu addr 0x0xffffb80000101440 ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 9 use gpu addr 0x00000000004004e0, cpu addr 0x0xffffb800001014e0 ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub [drm:pid867:sdma_v4_0_init_microcode] [drm:pid867:sdma_v4_0_init_microcode] psp_load == 'true' [drm] use_doorbell being set to: [true] drm0: debug: fence driver on ring 10 use gpu addr 0x0000000000400560, cpu addr 0x0xffffb80000101560 ttm_check_under_lowerlimit: stub amdgpu: [powerplay] powerplay sw init successfully [drm:pid867:load_dmcu_fw] PSP loading DMCU firmware [drm] Found VCN firmware Version ENC: 1.15 DEC: 3 VEP: 0 Revision: 0 [drm] PSP loading VCN firmware drm0: debug: fence driver on ring 11 use gpu addr 0x00000000004005e0, cpu addr 0x0xffffb800001015e0 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 12 use gpu addr 0x0000000000400660, cpu addr 0x0xffffb80000101660 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 13 use gpu addr 0x00000000004006e0, cpu addr 0x0xffffb800001016e0 ttm_check_under_lowerlimit: stub drm0: debug: fence driver on ring 14 use gpu addr 0x0000000000400760, cpu addr 0x0xffffb80000101760 ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub ttm_check_under_lowerlimit: stub [drm] reserve 0x400000 from 0xf400b00000 for PSP TMR SIZE [drm:pid867:gfx_v9_0_ring_test_ring] ring test on 9 succeeded in 75 usecs [drm:pid867:gfx_v9_0_ring_test_ring] ring test on 0 succeeded in 2 usecs [drm:pid867:gfx_v9_0_ring_test_ring] ring test on 1 succeeded in 6 usecs [drm:pid867:gfx_v9_0_ring_test_ring] ring test on 2 succeeded in 3 usecs [drm:pid867:gfx_v9_0_ring_test_ring] ring test o 3 succeeded in 3 usecs [drm:pid867:gfx_v9_0_ring_test_ring] ring test on 4 succeeded in 3 usecs 7>[drm:pid867:gfx_v9_0_ring_test_ring] ring test on 5 succeeded in 3 usecs 7>[drm:pid867:gfx_v9_0_ring_test_ring] ring test on 6 succeeded in 3 usecs 7>[drm:pid867:gfx_v9_0_ring_test_ring] ring test on 7 succeeded in 3 usecs 7>[drm:pid867:gfx_v9_0_ring_test_ring] ring test on 8 succeeded in 3 usecs [drm:pid867:sdma_v4_0_ring_set_wptr] Setting write pointer [drm:pid867:sdma_v4_0_ring_set_wptr] Using doorbell -- wptr_offs == 0x00000150 lower_32_bits(ring->wptr) << 2 == 0x00000040 upper_32_bits(ring->wptr) << 2 == 0x00000000 [drm:pid867:sdma_v4_0_ring_set_wptr] calling WDOORBELL64(0x000001c0, 0x0000000000000040) [drm:pid867:sdma_v4_0_ring_test_ring] ring test on 10 succeeded in 5 usecs [drm:pid-1:amdgpu_irq_dispatch] Unhandled interrupt src_id: 243 [drm:pid867:drm_dp_dump_access] dmdc: 0x00000 AUX -> (ret= 16) fffff8031a45a3e8h [drm:pid867:drm_dp_dump_access] dmdc: 0x02200 AUX -> (ret= 16) fffff8031a45a3e8h [drm:pid867:drm_dp_dump_access] dmdc: 0x00080 AUX -> (ret= 4) fffff8031a45a3dfh [drm:pid867:drm_dp_dump_access] dmdc: 0x00500 AUX -> (ret= 9) fffff8031a45a3dfh [drm:pid867:drm_dp_dump_access] dmdc: 0x00509 AUX -> (ret= 3) fffff8031a45a3dfh [drm:pid867:drm_dp_dump_access] dmdc: 0x00200 AUX -> (ret= 1) fffff80136bfdcdch [drm:pid867:drm_dp_dump_access] dmdc: 0x00400 AUX -> (ret= 9) fffff8031a45a3dfh [drm:pid867:drm_dp_dump_access] dmdc: 0x00409 AUX -> (ret= 3) fffff8031a45a3dch [drm:pid867:dc_conn_log_hex_linux] 14 <7>[drm:pid867:dc_conn_log_hex_linux] 1E <7>[drm:pid867:dc_conn_log_hex_linux] C2 <7>[drm:pid867:dc_conn_log_hex_linux] 81 <7>[drm:pid867:dc_conn_log_hex_linux] 01 <7>[drm:pid867:dc_conn_log_hex_linux] 15 <7>[drm:pid867:dc_conn_log_hex_linux] 01 <7>[drm:pid867:dc_conn_log_hex_linux] 83 <7>[drm:pid867:dc_conn_log_hex_linux] 2A <7>[drm:pid867:dc_conn_log_hex_linux] 3F <7>[drm:pid867:dc_conn_log_hex_linux] 04 <7>[drm:pid867:dc_conn_log_hex_linux] 00 <7>[drm:pid867:dc_conn_log_hex_linux] 00 <7>[drm:pid867:dc_conn_log_hex_linux] 00 <7>[drm:pid867:dc_conn_log_hex_linux] 84 <7>[drm:pid867:dc_conn_log_hex_linux] 00 <7>[drm:pid867:retrieve_link_cap] Rx Caps: <7>[drm:pid867:drm_dp_dump_access] dmdc: 0x00000 AUX -> (ret= 1) fffff8031a45a406h [drm:pid867:drm_dp_dump_access] dmdc: 0x00021 AUX -> (ret= 1) fffff8031a45a407h [drm] DM_MST: Differing MST start on aconnector: 0xfffff8013c20c700 [id: 57] [drm:pid867:dc_link_detect] link=3, mst branch is now Connected [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0a00 for: dal_src=78, irq context=1 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0a40 for: dal_src=79, irq context=1 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0a80 for: dal_src=80, irq context=1 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0ac0 for: dal_src=81, irq context=1 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0b40 for: dal_src=26, irq context=1 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0b80 for: dal_src=27, irq context=1 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0bc0 for: dal_src=28, irq context=1 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0c00 for: dal_src=29, irq context=1 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0c80 for: dal_src=7, irq context=0 [drm:pid867:amdgpu_dm_irq_re gister_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0cc0 for: dal_src=2, irq context=0 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0d00 for: dal_src= 8, irq context=0 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0d40 for: dal_src=3, irq context=0 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0d80 for: dal_src=9, irq context=0 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IR Q: added irq handler: 0xfffff8012f4b0dc0 for: dal_src=4, irq context=0 [drm:pid867:amdgpu_dm_irq_register_interrupt] DM_IRQ: added irq handler: 0xfffff8012f4b0e00 for: dal_src=10 , irq context=0 [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [drm] Driver supports precise vblank timestamp query. [drm:pid867:amdgpu_dm_init] KMS initialized. [drm:pid867:amdgpu_vcn_dec_ring_test_ring] ring test on 11 succeeded in 3 usecs [drm:pid867:amdgpu_vcn_enc_ring_test_ring] ring test on 12 succeeded in 33 usecs [drm:pid867:amdgpu_vcn_enc_ring_test_ring] ring test on 13 succeeded in 21 usecs [drm:pid867:amdgpu_vcn_jpeg_ring_test_ring] ring test on 14 succeeded in 7 usecs [drm] VCN decode and encode initialized successfully(under SPG Mode). amdgpu_device_init: 9 ttm_check_under_lowerlimit: stub [drm] amdgpu_device_init: Taking over the fictitious range 0xe0000000-0xf0000000 amdgpu_device_init: 10 [drm:pid867:drm_setup_crtcs] [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:50:eDP-1] [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:50:eDP-1] status updated from unknown to connected [drm:pid867:drm_edid_to_eld] ELD: no CEA Extension found [drm:pid867:drm_add_display_info] non_desktop set to 0 [drm:pid867:drm_add_display_info] eDP-1: Assigning EDID-1.4 digital sink color depth as 6 bpc. [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:640 height:480 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:800 height:600 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1024 height:768 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:720 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:800 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:1024 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1440 height:900 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1680 height:1050 [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:50:eDP-1] probed modes : [drm:pid867:drm_mode_debug_printmodeline] Modeline 58:"1920x1080" 60 152840 1920 1966 1996 2250 1080 1082 1086 1132 0x48 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 59:"1920x1080" 40 101880 1920 1966 1996 2250 1080 1082 1086 1132 0x40 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 67:"1680x1050" 60 152840 1680 1966 1996 2250 1050 1082 1086 1132 0x40 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 152840 1280 1966 1996 2250 1024 1082 1086 1132 0x40 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 66:"1440x900" 60 152840 1440 1966 1996 2250 900 1082 1086 1132 0x40 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 64:"1280x800" 60 152840 1280 1966 1996 2250 800 1082 1086 1132 0x40 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 152840 1280 1966 1996 2250 720 1082 1086 1132 0x4 0 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 62:"1024x768" 60 152840 1024 1966 1996 2250 768 1082 1086 1132 0x40 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 152840 800 1966 1996 2250 600 1082 1086 1132 0x40 0x9 [drm:pid867:drm_mode_debug_printmodeline] Modeline 60:"640x480" 60 152840 640 1966 1996 2250 480 1082 1086 1132 0x40 0x9 [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] [drm:pid8 67:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] status updated from unknown to disconnected [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP- 1] disconnected [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [drm:pid867:drm_helper_probe_single_connector_modes] [CO NNECTOR:55:DP-2] status updated from unknown to disconnected [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-3] [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-3] status updated from unknown to disconnected [drm:pid867:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-3] disconnected [drm:pid867 :drm_enable_connectors] connector 50 enabled? yes [drm:pid867:drm_enable_connectors] connector 53 enabled? no [drm:pid867:drm_enable_connectors] connector 55 enabled? no [drm:pid867:drm_enable_connectors] connector 57 enabled? no [drm:pid867:drm_target_preferred] looking for cmdline mode on connector 50 [drm:pid867:drm_target_preferred] looking for preferred mode on connector 50 0 [drm:pid867:drm_target_preferred] found mode 1920x1080 [drm:pid867: drm_setup_crtcs] picking CRTCs for 16384x16384 config [drm:pid867:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0) 7>[drm:pid-1:sdma_v4_0_ring_set_wptr] Setting write pointer [drm:pid-1:sdma_v4_0_ring_set_wptr] Using doorbell -- wptr_offs == 0x00000150 lower_32_bits(ring->wptr) << 2 == 0x000000c0 upper_32_bits(ring->wptr) << 2 == 0x00000000 [drm:pid-1:sdma_v4_0_ring_set_wptr] calling WDOORBELL64(0x000001c0, 0x00000000000000c0) [drm:pid-1:sdma_v4_0_process_trap_irq] IH: SDMA trap [drm:pid-1:amdgpu_irq_dispatch] Unhandled interrupt src_id: 243 ( PCIB_BCR_VGA_ENABLE) config = 0 [drm] fb mappable at 0xE0F00000 [drm] vram apper at 0xE0000000 [drm] size 8294400 [drm] fb depth is 24 [drm] pitch is 7680 7>[drm:pid867:__drm_fb_helper_initial_config_and_unlock] dfly: registering framebuffer kms console: xpixels 1920 ypixels 1080 [drm:pid867:drm_atomic_state_init] Allocated atomic state 0xfffff8012f4ef680 [drm:pid867:drm_atomic_get_plane_state] Added [PLANE:37:plane-0] 0xfffff8013b72b800 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_get_plane_state] Added [PLANE:38:plane-1] 0xfffff8013b72b900 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_get_plane_state] Added [PLANE:39:plane-2] 0xfffff8013b72ba00 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_get_plane_state] Added [PLANE:40:plane-3] 0xfffff8013b72bb00 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_get_plane_state] Added [PLANE:41:plane-4] 0xfffff8013b72bc00 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:41:plane-4] state 0xfffff8013b72bc00 [drm:pid867:drm_atomic_get_plane_state] Added [PLANE:43:plane-5] 0xfffff8013b72bd00 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:43:plane-5] state 0xfffff8013b72bd00 [drm:pid867:drm_atomic_get_plane_state] Added [PLANE:45:plane-6] 0xfffff8013b72be00 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:plane-6] state 0xfffff8013b72be00 [drm:pid867:drm_atomic_get_plane_state] Added [PLANE:47:plane-7] 0xfffff8013b72bf00 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:47:plane-7] state 0xfffff8013b72bf00 [drm:pid867:drm_atomic_get_crtc_state] Added [CRTC:42:crtc-0] 0xfffff8012f4c9bc0 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for [CRTC:42:crtc-0] state 0xfffff8012f4c9bc0 [drm:pid867:drm_atomic_set_crtc_for_plane] Link [PLANE:40:plane-3] state 0xfffff8013b72bb00 to [CRTC:42:crtc-0] [drm:pid867:drm_atomic_set_fb_for_plane] Set [FB:69] for [PLANE:40:plane-3] state 0xfffff8013b72bb00 [drm:pid867:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:crtc-0] to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_get_connector_state] Added [CONNECTOR:50:eDP-1] 0xfffff8013b72c200 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:50:eDP-1] state 0xfffff8013b72c200 to [CRTC:42:crtc-0] [drm:pid867:drm_atomic_get_crtc_state] Added [CRTC:44:crtc-1] 0xfffff8012f4c9e40 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_mode_for_crtc] Set [NOMODE] for [CRTC:44:crtc-1] state 0xfffff8012f4c9e40 [drm:pid867:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-2] state 0xfffff8013b72ba00 [drm:pid867:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:44:crtc-1] to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_get_crtc_state] Added [CRTC:46:crtc-2] 0xfffff8012f4ca0c0 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_mode_for_crtc] Set [NOMODE] for [CRTC:46:crtc-2] state 0xfffff8012f4ca0c0 [drm:pid867:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:38:plane-1] state 0xfffff8013b72b900 [drm:pid867:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:crtc-2] to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_get_crtc_state] Added [CRTC:48:crtc-3] 0xfffff8012f4ca340 state to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_set_mode_for_crtc] Set [NOMODE] for [CRTC:48:crtc-3] state 0xfffff8012f4ca340 [drm:pid867:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:37:plane-0] state 0xfffff8013b72b800 [drm:pid867:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:48:crtc-3] to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_check_only] checking 0xfffff8012f4ef680 [drm:pid867:drm_atomic_helper_check_modeset] [CRTC:42:crtc-0] mode changed [drm:pid867:drm_atomic_helper_check_modeset] [CRTC:42:crtc-0] enable changed [drm:pid867:drm_atomic_helper_check_modeset] [CRTC:42:crtc-0] active changed [drm:pid867:update_connector_routing] Updating routing for [CONNECTOR:50:eDP-1] [drm:pid867:update_connector_routing] [CONNECTOR:50:eDP-1] using [ENCODER:49:TMDS-49] on [CRTC:42:crtc-0] [drm:pid867:drm_atomic_helper_check_modeset] [CRTC:42:crtc-0] needs all connectors, enable: y, active: y [drm:pid867:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:crtc-0] to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_add_affected_planes] Adding all current planes for [CRTC:42:crtc-0] to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:crtc-0] to 0xfffff8012f4ef680 [drm:pid867:drm_atomic_add_affected_planes] Adding all current planes for [CRTC:42:crtc-0] to 0xfffff8012f4ef680 [drm:pid867:dm_update_crtcs_state] amdgpu_crtc id:0 crtc_state_flags: enable:1, active:1, planes_changed:0, mode_changed:1,active_changed:1,connectors_changed:1 [drm:pid867:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid867:dm_update_crtcs_state] amdgpu_crtc id:0 crtc_state_flags: enable:1, active:1, planes_changed:0, mode_changed:1,active_changed:1,connectors_changed:1 [drm:pid867:drm_atomic_get_private_obj_state] Added new private object 0xfffff8031e42ac40 state 0xfffff8012f4b1840 to 0xfffff8012f4ef680 [drm:pid867:dm_update_crtcs_state] Enabling DRM crtc: 42 [drm:pid867:dm_update_planes_state] Enabling DRM plane: 40 on DRM crtc 42 [drm:pid867:amdgpu_dm_atomic_check] dfly: update_type = 2, overall_update_type = 0<7>[drm:pid867:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:1920 x:0 y:0 dst_rect: height:1080 width:1920 x:0 y:0 [drm:pid867:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:960 x:0 y:0 dst_rect: height:1080 width:1920 x:0 y:0 [drm:pid867:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:960 x:960 y:0 dst_rect: height:1080 width:1920 x:0 y:0 [drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: surf_linear = 1<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: surf_vert = 0<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: blk256_width = 64<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: blk256_height = 1<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_blk_height = 64<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_blk_width = 4096<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_surface_bytes = 0<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_pte_req_per_frame_ub = 1<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_pte_bytes_per_frame_ub = 64<7>[drm:pid867:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: req128_l = 0<7>[drm:pid867:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: req128_c = 0<7>[drm:pid867:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: full_swath_bytes_packed_l = 4096<7>[drm:pid867:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0<7>[drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: *************************** [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: === [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_width_ub = 1024 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_height = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 16 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_row_height = 128 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 64 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 3 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_row_height = 8 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 192 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_width_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_height = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_row_height = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_row_height = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: full_swath_bytes = 4096 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 8192 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_width = 64 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_height = 1 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_width = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_height = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_width = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_height = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_width = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_height = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: *************************** [drm:pid867:extract_rq_sizing_regs] [DML]:DLG: extract_rq_sizing_regs: rq_sizing param<7>[drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cstate_en = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pstate_en = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_en = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: iflip_en = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: interlaced = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dcfclk_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_ttu_vblank = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_calc_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x11af<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: htotal = 2250<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 218<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_x_after_scaler = 1178<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_after_scaler = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.sr_enter_plus_exit_time_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.dram_clock_change_latency_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.urgent_latency_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: swath_height_l = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_srx_delay_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vupdate_offset = 563<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vupdate_width = 302<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vready_offset = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_wait = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_o = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_setup = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_calc = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch (before rnd) = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = %3.2f<7>[drm:pid867:get_swath_need] [DML]:DLG: get_swath_need: swath_height = 1<7>[drm:pid867:get_swath_need] [DML]:DLG: get_swath_need: vinit = %3.2f<7>[drm:pid867:get_swath_need] [DML]:DLG: get_swath_need: max_num_sw = 1<7>[drm:pid867:get_swath_need] [DML]:DLG: get_swath_need: max_partial_sw = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes_ub_l = 8192<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes_ub_c = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes = 8192<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_bytes = 64<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: meta_row_bytes = 192<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_row_bytes = 64<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_after_scaler = 0x0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->refcyc_x_after_scaler = 0x171<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_prefetch = 42<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw_l = 2<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw_c = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_l = 64<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_c = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: prefetch_bw = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: flip_bw = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_pre_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_vm_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_r0_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_per_row_vblank = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw = %3.2f<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: max_num_sw = 1<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: max_partial_sw = 1<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: swath_height = 1<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: vinit = %3.2f<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: vratio_pre = %3.2f<7>[drm:pid867:get_vratio_pre] [DML]:WARNING_DLG: get_vratio_pre: vratio_pre=%3.2f < 1.0, set to 1.0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vratio_pre_l=%3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vratio_pre_c=%3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 960<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 1<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 960<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 1<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: full_recout_width = 960<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: hscale_pixel_rate_l = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 960<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 16<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 960<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 16<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_req_width = 64<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_width_ub = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_req_per_width = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: hactive_cur0 = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_cur0 = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_cur0 = %3.2f<7>[drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0xb0a [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x4f7 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x4b5f [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x4b5f [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x5065 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x5065 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x59 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x32 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x11af [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0x2c29f [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x171 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0x2a [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x2832e [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x211 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x211 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x211 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x1614f [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x1614 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x12d [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x12d [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: surf_linear = 1<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: surf_vert = 0<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: blk256_width = 64<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: blk256_height = 1<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_blk_height = 64<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_blk_width = 4096<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_surface_bytes = 0<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_pte_req_per_frame_ub = 1<7>[drm:pid867:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_pte_bytes_per_frame_ub = 64<7>[drm:pid867:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: req128_l = 0<7>[drm:pid867:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: req128_c = 0<7>[drm:pid867:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: full_swath_bytes_packed_l = 4096<7>[drm:pid867:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0<7>[drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: *************************** [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: === [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_width_ub = 1024 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_height = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 16 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_row_height = 128 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 64 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 3 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_row_height = 8 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 192 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_width_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_height = 1 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_row_height = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_row_height = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0 [drm:pid867:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: full_swath_bytes = 4096 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 8192 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_width = 64 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_height = 1 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_width = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_height = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_width = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_height = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_width = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_height = 0 [drm:pid867:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: *************************** [drm:pid867:extract_rq_sizing_regs] [DML]:DLG: extract_rq_sizing_regs: rq_sizing param<7>[drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048 [drm:pid867:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cstate_en = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pstate_en = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_en = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: iflip_en = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: interlaced = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dcfclk_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_ttu_vblank = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_calc_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x11af<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: htotal = 2250<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 218<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_x_after_scaler = 1178<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_after_scaler = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.sr_enter_plus_exit_time_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.dram_clock_change_latency_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.urgent_latency_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: swath_height_l = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_srx_delay_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vupdate_offset = 563<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vupdate_width = 302<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vready_offset = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_wait = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_o = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_setup = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_calc = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch (before rnd) = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = %3.2f<7>[drm:pid867:get_swath_need] [DML]:DLG: get_swath_need: swath_height = 1<7>[drm:pid867:get_swath_need] [DML]:DLG: get_swath_need: vinit = %3.2f<7>[drm:pid867:get_swath_need] [DML]:DLG: get_swath_need: max_num_sw = 1<7>[drm:pid867:get_swath_need] [DML]:DLG: get_swath_need: max_partial_sw = 1<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes_ub_l = 8192<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes_ub_c = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes = 8192<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_bytes = 64<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: meta_row_bytes = 192<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_row_bytes = 64<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_after_scaler = 0x0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->refcyc_x_after_scaler = 0x171<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_prefetch = 42<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw_l = 2<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw_c = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_l = 64<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_c = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: prefetch_bw = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: flip_bw = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_pre_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_vm_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_r0_us = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_per_row_vblank = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw = %3.2f<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: max_num_sw = 1<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: max_partial_sw = 1<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: swath_height = 1<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: vinit = %3.2f<7>[drm:pid867:get_vratio_pre] [DML]:DLG: get_vratio_pre: vratio_pre = %3.2f<7>[drm:pid867:get_vratio_pre] [DML]:WARNING_DLG: get_vratio_pre: vratio_pre=%3.2f < 1.0, set to 1.0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vratio_pre_l=%3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vratio_pre_c=%3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 960<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 1<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 960<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 1<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: full_recout_width = 960<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: hscale_pixel_rate_l = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 960<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 16<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 960<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 16<7>[drm:pid867:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_req_width = 64<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_width_ub = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_req_per_width = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: hactive_cur0 = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_cur0 = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_cur0 = %3.2f<7>[drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0xb0a [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x4f7 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x4b5f [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x4b5f [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x5065 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x5065 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0 [drm:pid867:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x59 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x32 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x11af [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0x2c29f [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x171 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0x2a [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x2832e [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x211 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x211 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x211 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x1614f [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x1614 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x12d [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x12d [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0 [drm:pid867:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid867:drm_atomic_commit] committing 0xfffff8012f4ef680 [drm:pid867:dm_plane_helper_prepare_fb] No FB bound [drm:pid867:dm_plane_helper_prepare_fb] No FB bound [drm:pid867:dm_plane_helper_prepare_fb] No FB bound [drm:pid867:dm_plane_helper_prepare_fb] No FB bound [drm:pid867:dm_plane_helper_prepare_fb] No FB bound [drm:pid867:dm_plane_helper_prepare_fb] No FB bound [drm:pid867:dm_plane_helper_prepare_fb] No FB bound [drm:pid867:drm_calc_timestamping_constants] crtc 42: hwmode: htotal 2250, vtotal 1132, vdisplay 1080 [drm:pid867:drm_calc_timestamping_constants] crtc 42: clock 152840 kHz framedur 16664485 linedur 14721 [drm:pid867:amdgpu_dm_atomic_commit_tail] amdgpu_crtc id:0 crtc_state_flags: enable:1, active:1, planes_changed:1, mode_changed:1,active_changed:1,connectors_changed:1 [drm:pid867:amdgpu_dm_atomic_commit_tail] Atomic commit: SET crtc id 0: [0xfffff8013c309100] [drm:pid867:amdgpu_dm_atomic_commit_tail] amdgpu_crtc id:1 crtc_state_flags: enable:0, active:0, planes_changed:0, mode_changed:0,active_changed:0,connectors_changed:0 [drm:pid867:amdgpu_dm_atomic_commit_tail] amdgpu_crtc id:2 crtc_state_flags: enable:0, active:0, planes_changed:0, mode_changed:0,active_changed:0,connectors_changed:0 [drm:pid867:amdgpu_dm_atomic_commit_tail] amdgpu_crtc id:3 crtc_state_flags: enable:0, active:0, planes_changed:0, mode_changed:0,active_changed:0,connectors_changed:0 [drm:pid867:dc_commit_state] dc_commit_state: 1 streams [drm:pid867:dc_stream_log] core_stream 0x0xfffff8013b79a4c0: src: 0, 0, 1920, 1080; dst: 0, 0, 1920, 1080, colorSpace:1 [drm:pid867:dc_stream_log] pix_clk_khz: 152840, h_total: 2250, v_total: 1132, pixelencoder:1, displaycolorDepth:1 [drm:pid867:dc_stream_log] sink name: , serial: 0 [drm:pid867:dc_stream_log] link: 0 [drm:pid867:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid867:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 155140clock_type = 0 [drm:pid867:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f [drm:pid867:dc_commit_state_no_check] dfly: set_bandwidth#1 [drm:pid867:dc_commit_state_no_check] dfly: streams[0].mode_changed == false [drm:pid867:dc_commit_state_no_check] dfly: ready_shared_resources [drm:pid867:dce110_apply_ctx_to_hw] dfly: reset_hw_ctx_wrap [drm:pid867:set_pixel_clock_v7] [BIOS]:set_pixel_clock_v7:program display clock = 152840colorDepth = 0 [drm:pid867:dce110_apply_ctx_to_hw] dfly: apply_single_controller_ctx_to_hw status = 1, i = 0<7>[drm:pid867:dc_commit_state_no_check] dfly: apply_ctx_to_hw result: 1 [drm:pid867:power_on_plane] Un-gated front end for pipe 0 [drm:pid867:power_on_plane] Un-gated front end for pipe 3 [drm:pid867:dc_commit_state_no_check] {1920x1080, 2250x1132@152840Khz}<7>[drm:pid867:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 155140clock_type = 0 [drm:pid867:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 [drm:pid867:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f [drm:pid867:dc_commit_state_no_check] dfly: set_bandwidth#2 [drm:pid867:drm_vblank_enable] enabling vblank on crtc 0, ret: 0 [drm:pid867:prepare_flip_isr] crtc:0, pflip_stat:AMDGPU_FLIP_SUBMITTED [drm:pid867:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:960 x:0 y:0 dst_rect: height:1080 width:1920 x:0 y:0 [drm:pid867:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:960 x:960 y:0 dst_rect: height:1080 width:1920 x:0 y:0 [drm:pid867:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 155140clock_type = 0 [drm:pid867:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 [drm:pid867:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f [drm:pid867:context_clock_trace] [BANDWIDTH_CALCS]:Current: dispclk_khz:155140 max_dppclk_khz:77570 dcfclk_khz:300000 dcfclk_deep_sleep_khz:9552 fclk_khz:400000 socclk_khz:0 [drm:pid867:context_clock_trace] [BANDWIDTH_CALCS]:Calculated: dispclk_khz:155140 max_dppclk_khz:77570 dcfclk_khz:300000 dcfclk_deep_sleep_khz:9552 fclk_khz:400000 socclk_khz:0 [drm:pid867:power_on_plane] Un-gated front end for pipe 0 [drm:pid867:power_on_plane] Un-gated front end for pipe 3 [drm:pid867:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 155140clock_type = 0 [drm:pid867:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 [drm:pid867:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =21030 HW register value = 0x3f1 [drm:pid867:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f [drm:pid-1:dm_pflip_high_irq] dm_pflip_high _irq - crtc :0[0xfffff8013c309100], pflip_stat:AMDGPU_FLIP_NONE [drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: interlaced = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: m [drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pclk_freq_in_mhz = %3.2f<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: interlaced = 0<7>[drm:pid867:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: m 7>[drm:pid-1:dm_irq_work_func] DM_IRQ: work_func: for dal_src=10 [drm:pid-1:dm_irq_work_func] DM_IRQ: schedule_work: for d al_src=10 7>[drm:pid-1:dc_link_handle_hpd_rx_irq] d c_link_handle_hpd_rx_irq: Got short pulse HPD on link 3 7>[drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 14) fffff8031e37b960h 7>[drm:pid-1:drm_dp_dump_access] d mdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch 7>[drm:pid-1:dm_handle_hpd_rx_irq] E SI 01 10 00 7>[drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:d rm_dp_dump_access] d mdc: 0x01410 AUX -> (ret= 16) fffff8031e37b890h 7>[drm:pid-1:drm_dp_dump_access] d mdc: 0x01420 AUX -> (ret= 16) fffff8031e37b890h 7>[drm:pid-1:drm_dp_dump_access] dmdc: 0x02003 AUX <- (ret= 3) fffff8031e37ba1dh 7>[drm:pid-1:drm_dp_dump_access] d mdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch 7>[drm:pid-1:dm_handle_hpd_rx_irq] E SI 01 10 00 7>[drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h 7>[drm:pid-1:drm_dp_dump_access] d mdc: 0x01410 AUX -> (ret= 16) fffff8031e37b890h 7>[drm:pid-1:drm_dp_dump_access] d mdc: 0x01420 AUX -> (ret= 8) fffff8031e37b890h [drm:pid-1:drm_dp_send_link_address] link address reply: 4 [drm:pid-1:drm_dp_send_link_address] port 0: input 1, pdt: 1, pn: 0, dpcd_rev: 00, mcs: 1, ddps: 1, ldps 0, sdp 0/0 [drm:pid-1:drm_dp_send_link_address] port 1: input 0, pdt: 4, pn: 1, dpcd_rev: 00, mcs: 0, ddps: 1, ldps 1, sdp 1/1 [drm:pid-1:drm_dp_send_link_address] port 2: input 0, pdt: 0, pn: 2, dpcd_rev: 00, mcs: 0, ddps: 0, ldps 0, sdp 0/0 [drm:pid-1:drm_dp_send_link_address] port 3: input 0, pdt: 0, pn: 3, dpcd_rev: 00, mcs: 0, ddps: 0, ldps 0, sdp 0/0 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00030 AUX <- (ret= 16) fffff8012f4ef6cdh [drm:pid-1:drm_dp_dump_access] dmdc: 0x01000 AUX <- (ret= 6) fffff8031e3cf730h [drm:pid-1:dm_irq_work_func] DM_IRQ: work_func: for dal_src=10 [drm:pid-1:dm_irq_work_func] DM_IRQ: schedule_work: for dal_src=10 [drm:pid-1:dc_link_handle_hpd_rx_irq] dc_link_handle_hpd_rx_irq: Got short pulse HPD on link 3 [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 14) fffff8031e37b960h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 10 00 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_send_enum_path_resources] enum path resources 1: 2160 2160 tunable drm.video.DP-4 is not set [drm] DM_MST: added connector: 0xfffff8013c20d200 [id: 71] [master: 0 xfffff8013c20c700] [drm:pid-1:dm_dp_add_mst_connector] :71 [drm:pid-1:drm_sysfs_connector_add] adding "DP-4" to sysfs tunable drm.video.DP-5 is not set [drm] DM_MST: added co nnector: 0xfffff8013c20dd00 [id: 74] [master: 0xfffff8013c20c700] [drm:pid-1:dm_dp_add_mst_connector] :74 [drm:pid-1:drm_sysfs_connector_add] adding "DP-5" to sysfs tunable drm.video.DP-6 is not set 6>[drm] DM_MST: added connector: 0xfffff8013c20e800 [id: 77] [master: 0xfffff8013c20c700] [drm:pid-1:dm_dp_add_mst_connector] :77 [drm:pid-1:drm_sysfs_connector_add] adding "DP-6" to sysfs [drm:pid-1:drm_fb_helper_hotplug_event] [drm:pid-1:drm_setup_crtcs] [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:50:eDP-1] [drm:pid-1:drm_edid_to_eld] ELD: no CEA Extension found [drm:pid-1:d rm_add_display_info] non_desktop set to 0 [drm:pid-1:drm_add_display_info] eDP-1: Assigning EDID-1.4 digital sink color depth as 6 bpc. 7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:upda te_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1680 height:1050 7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:1024 7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1440 height:900 7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:800 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:720 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1024 height:768 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:800 height:600 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:640 height:480 [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:50:eDP-1] probed modes : [drm:pid-1:drm_mode_debug_printmodeline] Modeline 58:"1920x1080" 60 152840 1920 1966 1996 2250 1080 1082 1086 1132 0x48 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 59:"1920x1080" 40 101880 1920 1966 1996 2250 1080 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 67:"1680x1050" 60 152840 1680 1966 1996 2250 1050 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 65:"1280x1024" 60 152840 1280 1966 1996 2250 1024 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 66:"1440x900" 60 152840 1440 1966 1996 2250 900 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 64:"1280x800" 60 152840 1280 1966 1996 2250 800 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 60 152840 1280 1966 1996 2250 720 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 62:"1024x768" 60 152840 1024 1966 1996 2250 768 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 61:"800x600" 60 152840 800 1966 1996 2250 600 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 60:"640x480" 60 152840 640 1966 1996 2250 480 1082 1086 1132 0x40 0x9 [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-1] disconnected [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:55:DP-2] disconnected [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-3] [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:57:DP-3] disconnected [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:71:DP-4] [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:71:DP-4] status updated from unknown to connected [drm:pid-1:drm_dp_dump_access] dmdc: 0x01000 AUX <- (ret= 12) fffff8031e3cf3a0h [drm:pid-1:dm_irq_work_func] DM_IRQ: work_func: for dal_src=10 [drm:pid-1:dm_irq_work_func] DM_IRQ: schedule_work: for dal_src=10 [drm:pid-1:dc_link_handle_hpd_rx_irq] dc_link_handle_hpd_rx_irq: Got short pulse HPD on link 3 [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 14) fffff8031e37b960h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 10 00 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02003 AUX <- (ret= 3) fffff8031e37ba1dh [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 10 00 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01410 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01420 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02003 AUX <- (ret= 3) fffff8031e37ba1dh [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 10 00 [drm] amdgpu_dm_irq_schedule_work FAILED src 10 [drm] amdgpu_dm_irq_schedule_work FAILED src 10 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01410 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01420 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02003 AUX <- (ret= 3) fffff8031e37ba1dh [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 10 00 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01410 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01420 AUX -> (ret= 15) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02003 AUX <- (ret= 3) fffff8031e37ba1dh [drm] amdgpu_dm_irq_schedule_work FAILED src 10 [drm] amdgpu_dm_irq_schedule_work FAILED src 10 [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm] amdgpu_dm_irq_schedule_work FAILED src 10 [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 10 00 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01410 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01420 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02003 AUX <- (ret= 3) fffff8031e37ba1dh [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 10 00 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h 7>[drm:pid-1:drm_dp_dump_access] d mdc: 0x01410 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] <6>[drm] amdgpu_dm_irq_schedule_work FAILED src 10 [drm] amdgpu_dm_irq_schedule_work FAILED src 10 dmdc: 0x01420 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02003 AUX <- (ret= 3) fffff8031e37ba1dh [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 10 00 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01410 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:drm_dp_dump_access] dmdc: 0x01420 AUX -> (ret= 15) fffff8031e37b890h [drm:pid-1:drm_detect_monitor_audio] Monitor has basic audio support [drm:pid-1:drm_add_display_info] non_desktop set to 0 [drm:pid-1:drm_parse_hdmi_vsdb_video] HDMI: DVI dual 0, max TMDS clock 0 kHz [drm:pid-1:drm_edid_to_eld] ELD monitor DELL U2415 [drm:pid-1:drm_parse_hdmi_vsdb_audio] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0 [drm:pid-1:drm_edid_to_eld] ELD size 36, SAD count 1 [drm:pid-1:drm_add_display_info] non_desktop set to 0 [drm:pid-1:drm_parse_hdmi_vsdb_video] HDMI: DVI dual 0, max TMDS clock 0 kHz [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:720 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:720 height:480 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1152 height:864 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:1024 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:800 height:600 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:640 height:480 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:640 height:480 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:720 height:400 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:1024 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1024 height:768 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1024 height:768 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:800 height:600 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:720 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:720 height:480 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:720 height:480 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:640 height:480 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:720 height:576 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:720 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1280 height:720 [drm:pid-1:upda te_stream_scaling_settings] Destination Rectangle x:0 y:0 width:720 height :480 7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x: 0 y:0 width:640 height:480 7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:720 height:480 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 81:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5 [drm:pid-1:drm_mode_prune_invalid] Not using 1920x1200 mode: VIRTUAL_Y [drm:pid-1:drm_mode_debug_printmodeline] Modeline 83:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [drm:pid-1:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE [drm:pid-1:drm_mode_debug_printmodeline] Modeline 88:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [drm:pid-1:drm_mode_prune_invalid] Not using 1600x1200 mode: VIRTUAL_Y [drm:pid-1:drm_mode_debug_printmodeline] Modeline 97:"1920x1080i" 0 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [drm:pid-1:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE [drm:pid-1:drm_mode_debug_printmodeline] Modeline 101:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [drm:pid-1:drm_mode_prune_invalid] Not using 720x480i mode: NO_INTERLACE [drm:pid-1:drm_mode_debug_printmodeline] Modeline 102:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [drm:pid-1:drm_mode_prune_invalid] Not using 720x576i mode: NO_INTERLACE [drm:pid-1:drm_mode_debug_printmodeline] Modeline 104:"1920x1080i" 0 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [drm:pid-1:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE [drm:pid-1:drm_mode_debug_printmodeline] Modeline 112:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [drm:pid-1:drm_mode_prune_invalid] Not using 1920x1080i mode: NO_INTERLACE [drm:pid-1:drm_mode_debug_printmodeline] Modeline 120:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [drm:pid-1:drm_mode_prune_invalid] Not using 720x480i mode: NO_INTERLACE [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:71:DP-4] probed modes : [drm:pid-1:drm_mode_debug_printmodeline] Modeline 82:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 105:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 123:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 109:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [drm:pid-1:drm_mode_debug_printm deline] Modeline 108:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 122:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [drm:pid-1:drm_ mode_debug_printmodeline] Modeline 93:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 60 10800 0 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 86:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0 x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 84:"1280x720" 60 74250 1 280 1390 1430 1650 720 725 730 750 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74250 1280 1 390 1430 1650 720 725 730 750 0x40 0x5 [drm:pid-1:drm_mode_debug_print modeline] Modeline 113:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] M odeline 107:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 94:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0 x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 95:"1024x768" 60 65000 1 024 1048 1184 1344 768 771 777 806 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Modeline 96:"800x600" 75 49500 800 816 896 1056 60 0 601 604 625 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodelin e] Modeline 89:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [drm:pid-1:drm_mode_debug_printmodeline] Modeline 106:"720x576 " 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [drm: pid-1:drm_mode_debug_printmodeline] Modeline 114:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [drm:pid-1:drm_mode_debug _printmodeline] Modeline 118:"720x480" 60 27027 720 736 798 858 4 80 489 495 525 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Modeline 85:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27000 72 0 736 798 858 480 489 495 525 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Modeline 100:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Model ine 90:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Modeline 115:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Modeline 91:"640x480" 6 0 25175 640 656 752 800 480 490 492 525 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Modeline 103:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [drm:pid-1:drm_mode_debug_printmodeline] Modeline 92:"720x400" 70 28320 720 738 846 90 0 400 412 414 449 0x40 0x6 [drm:pid-1:drm_helper_probe_single_connector_modes] [CONNECTOR:74:DP-5] [drm:p id-1:drm_helper_probe_single_connector_modes] [CONNECTOR:74:DP-5] status updated from unknown to disconnected [drm:pid -1:drm_helper_probe_single_connector_modes] [CONNECTOR:74:DP-5] disconnected [drm:pid-1:drm_helper_probe_single_conne ctor_modes] [CONNECTOR:77:DP-6] [drm:pid-1:drm_helper_p robe_single_connector_modes] [CONNECTOR:77:DP-6] status updated from unknown to disconnected [drm:pid-1:drm_helper_probe_single_connector_ modes] [CONNECTOR:77:DP-6] disconnected [drm:pid-1:drm_en able_connectors] connector 50 enabled? yes [drm:pid-1:d rm_enable_connectors] connector 53 enabled? no [drm:pid-1:drm_enable_connectors] connector 55 enabled? no [drm:pid-1:drm_enable_connectors] c onnector 57 enabled? no [drm:pid-1:drm_enable_connectors] connector 71 enabled? yes [drm:pid-1:drm_enable_connectors] connector 74 enabled? no [drm:pi d-1:drm_enable_connectors] connector 77 enabled? no 7>[drm:pid-1:drm_target_preferred] looking for cmdline mode on connector 50 7>[drm:pid-1:drm_target_preferred] looking for preferred mode on connector 50 0 [drm:pid-1:drm_target_preferred] found mode 1920x1080 [drm:pid- 1:drm_target_preferred] looking for cmdline mode on connector 71 [d rm:pid-1:drm_target_preferred] looking for preferred mode on connector 71 0 [drm:pid-1:drm_target_preferred] found mode 1920x1080 7>[drm:pid-1:drm_setup_crtcs] picking CRTCs for 1920x1080 conf ig >[drm:pid-1:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0 ) [drm:pid-1:drm_setup_crtcs] desired mode 1920 x1080 set on crtc 44 (0,0) [drm:pid-1:drm_atomic_state_init] Allocated atomic state 0xfffff80 12f4ef980 [drm:pid-1:drm_atomic_get_plane_state] Added [PLANE:3 7:plane-0] 0xfffff8013b72d300 state to 0xfffff8012f4ef980 7>[drm:pid-1:drm_atomic_get_plane_state] Added [PLANE:38:plane-1] 0xfffff8013b72d200 state to 0xfffff8012f4ef980 [drm:pid-1:drm _atomic_get_plane_state] Added [PLANE:39:plane-2] 0xfffff8013b72ce00 state to 0 xfffff8012f4ef980 [drm:pid-1:drm_atomic_get_plan e_state] Added [PLANE:40:plane-3] 0xfffff8013b72c100 state to 0xfffff8012f4ef980 [drm:pid-1:drm_ atomic_get_crtc_state] Added [CRTC:42:crtc-0] 0xfffff8012f4c9440 st ate to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_get_plane_ state] Added [PLANE:41:plane-4] 0xfffff8013b729900 state to 0 xfffff8012f4ef980 [drm:pid-1:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:41:plane-4] state 0xfffff8013b729900 [drm: pid-1:drm_atomic_get_plane_state] Added [PLANE:43:plane-5] 0xfffff8013b729700 state to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_set_f b_for_plane] Set [NOFB] for [PLANE:43:plane-5] state 0xf ffff8013b729700 [drm:pid-1:drm_atomic_get_plane_state] Added [P LANE:45:plane-6] 0xfffff8013b72e600 state to 0xfffff8012f4ef980 >[drm:pid-1:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:45:pl ane-6] state 0xfffff8013b72e600 [drm:pid-1:drm_atomic_get_plane_s tate] Added [PLANE:47:plane-7] 0xfffff8013b72e400 s tate to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_set_fb_for_plane] Set [NOFB] f or [PLANE:47:plane-7] state 0xfffff8013b72e400 7>[drm:pid-1:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for [ CRTC:42:crtc-0] state 0xfffff8012f4c9440 [drm:pid-1:drm_atomi c_set_fb_for_plane] Set [FB:69] for [PLANE:40:plane-3] state 0xfff ff8013b72c100 [drm:pid-1:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:crtc-0] to 0xfffff8012f4ef980 7>[drm:pid-1:drm_atomic_get_connector_state] Added [CONNECTOR:50:eDP-1 ] 0xfffff8013b72e100 state to 0xfffff8012f4ef980 [drm:pid- 1:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:50:eDP- 1] state 0xfffff8013b72e100 to [NOCRTC] [drm:pid-1:drm_atomic_set_crtc_ for_connector] Link [CONNECTOR:50:eDP-1] state 0xfffff8013b72e100 to [CRTC:42:crtc-0] [drm:pid-1:drm_atom ic_get_crtc_state] Added [CRTC:44:crtc-1] 0xfffff8012f4c91c0 state to 0xfffff8 012f4ef980 [drm:pid-1:drm_atomic_set_mode_f or_crtc] Set [MODE:1920x1080] for [CRTC:44:crtc-1] state 0xfffff8012f4c91c0 7>[drm:pid-1:drm_atomic_set_crtc_for_plane] Link [PLANE:39:plane -2] state 0xfffff8013b72ce00 to [CRTC:44:crtc-1] [drm:pid-1:drm_atomic_se t_fb_for_plane] Set [FB:69] for [PLANE:39:plane-2] state 0xffff f8013b72ce00 [drm:pid-1:drm_atomic_add_affected_connectors] Adding al l current connectors for [CRTC:44:crtc-1] to 0xfffff8012f4ef980 7>[drm:pid-1:drm_atomic_get_connector_state] Added [CONNECTOR:71:DP- 4] 0xfffff8013b72ea00 state to 0xfffff8012f4ef980 [drm:pid-1:drm_ atomic_set_crtc_for_connector] Link [CONNECTOR:71:DP-4] state 0xf ffff8013b72ea00 to [CRTC:44:crtc-1] [drm:pid-1:drm_atomi c_get_crtc_state] Added [CRTC:46:crtc-2] 0xfffff8012f4c8f40 state to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_set_mode_for_crtc] Set [NOMODE] for [CRTC:46:crtc-2] state 0xfffff8012f4c8f40 [drm:pid-1:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:38:plane-1] state 0xfffff8013b72d200 [drm:pid-1:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:46:crtc-2] to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_get_crtc_state] Added [CRTC:48:crtc-3] 0xfffff8012f4c8cc0 state to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_set_mode_for_crtc] Set [NOMODE] for [CRTC:48:crtc-3] state 0xfffff8012 f4c8cc0 [drm:pid-1:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:37:plane-0] state 0xfffff8013b72d300 [drm:pid-1:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:48:c rtc-3] to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_check_only] checking 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_helper_check_modese t] [CRTC:44:crtc-1] mode changed [drm:pid-1:drm_atomic_helper_check_modeset] [CRTC:44:crtc-1] enable changed [drm:pid-1:drm_atomic_helper_c heck_modeset] [CRTC:44:crtc-1] active changed [drm:pid-1:update_connector_routing] Updating rout ing for [CONNECTOR:50:eDP-1] [drm:pid-1:update_connector_routing] [CONNECTOR:50:eDP-1] keeps [ENCODER:49:TMDS-49], now on [CRTC:4 2:crtc-0] [drm:pid-1:update_connector_routing] Updating routing for [CONNECTOR:71:DP-4] [drm:p id-1:update_connector_routing] [CONNECTOR:71:DP-4] using [ENCODER:72:DP MST-72] on [CRTC:44:crtc-1] [drm:pid-1:drm_atomic_helper_check_modeset] [ CRTC:44:crtc-1] needs all connectors, enable: y, active: y [drm:pid-1:drm_atomi c_add_affected_connectors] Adding all current connectors for [CRTC:4 4:crtc-1] to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_add_affec ted_planes] Adding all current planes for [CRTC:44:crtc-1] to 0xfffff8012f4ef980 [drm:pid-1:drm_atomic_add_affected_con nectors] Adding all current connectors for [CRTC:44:crtc-1] to 0xfffff8012f4ef980 7>[drm:pid-1:drm_atomic_add_affected_planes] Adding all current planes for [CRTC:44:crtc-1] to 0xfffff8012f4ef980 [drm:pid-1: dm_update_planes_state] Disabling DRM plane: 40 on DRM crtc 42 7>[drm:pid-1:drm_atomic_get_private_obj_state] Added new private object 0xfffff803 1e42ac40 state 0xfffff8012f4b1c40 to 0xfffff8012f4ef980 7>[drm:pid-1:dm_update_crtcs_state] amdgpu_crtc id:1 crtc_state_flags: enable:1, active:1, planes_changed:0, mode_changed:1,active_changed:1,connectors_changed:1 [drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:dm_update_crtcs_state] Mode change not required, setting mode_changed to 0<7>[drm:pid-1:update_stream_scaling_settings] Destination Rectangle x:0 y:0 width:1920 height:1080 [drm:pid-1:dm_update_crtcs_state] amdgpu_crtc id:1 crtc_state_flags: enable:1, active:1, planes_changed:0, mode_changed:1,active_changed:1,connectors_changed:1 [drm:pid-1:dm_update_crtcs_state] Enabling DRM crtc: 44 [drm:pid-1:dm_update_planes_state] Enabling DRM plane: 40 on DRM crtc 42 [drm:pid-1:dm_update_planes_state] Enabling DRM plane: 39 on DRM crtc 44 [drm:pid-1:amdgpu_dm_atomic_check] dfly: update_type = 2, overall_update_type = 0<7>[drm:pid-1:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:1920 x:0 y:0 dst_rect: height:1080 width:1920 x:0 y:0 [drm:pid-1:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:1920 x:0 y:0 dst_rect: height:1080 width:1920 x:0 y:0 [drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: surf_linear = 1<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: surf_vert = 0<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: blk256_width = 64<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: blk256_height = 1<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_blk_height = 64<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_blk_width = 4096<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_surface_bytes = 0<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_pte_req_per_frame_ub = 1<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_pte_bytes_per_frame_ub = 64<7>[drm:pid-1:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: req128_l = 0<7>[drm:pid-1:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: req128_c = 0<7>[drm:pid-1:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: full_swath_bytes_packed_l = 7936< 7>[drm:pid-1:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0<7>[drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: *************************** [drm:pid-1:p rint__rq_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid-1:p rint__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_byte s = 8192 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_ CALC: min_chunk_bytes = 1024 [drm:pid-1:print__data_rq_siz ing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048 [drm:pid-1:print__data_rq_sizing_pa rams_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: === [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 0 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0 [drm:pid-1:print__data_rq_siz ing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0 [drm:p id-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_ group_bytes = 0 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0 [drm:pid-1:print__data_rq _sizing_params_st] [DML]:DML_RQ_DLG_CALC: ========================== =========== [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid -1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: =========== ========================== [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [drm:pid-1:print__data_rq_ dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_width_ub = 1984 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC : swath_height = 1 [drm:pid-1:print__data_rq_dlg_p arams_st] [DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 31 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_pte_byte s_per_frame_ub = 64 [drm:pid-1:print__data_rq_dlg_params_st] [DM L]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 1 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ ub = 1 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_row_height = 128 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 64 7>[drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1 [drm:pid-1:print__data_rq_dlg_params _st] [DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 5 >[drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_row _height = 8 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML _RQ_DLG_CALC: meta_bytes_per_row_ub = 320 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ====================== =============== [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid-1:print__data_rq_dlg_params_st] [DML]: DML_RQ_DLG_CALC: ===================================== [drm:pi d-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_width_ub = 0 [drm:pid-1:print__data_rq_dlg _params_st] [DML]:DML_RQ_DLG_CALC: swath_height = 1 [drm:pi d-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_C ALC: meta_pte_bytes_per_frame_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [D ML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dp te_groups_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG _CALC: dpte_row_height = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_D LG_CALC: meta_chunks_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_para ms_st] [DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_r ow_height = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ _DLG_CALC: meta_bytes_per_row_ub = 0 [drm:pid-1:print__data _rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: =================================== == [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid-1:p rint__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ============ ========================= [drm:pid-1:print__data_rq_misc_params_st] [DML]: DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST [drm:pid-1:print__data_r q_misc_params_st] [DML]:DML_RQ_DLG_CALC: full_swath_bytes = 7936 [drm:pid- 1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: stored_swa th_bytes = 15872 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_R Q_DLG_CALC: blk256_width = 64 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_height = 1 [drm:pid-1:p rint__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_width = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC : req_height = 0 [drm:pid-1:print__data_rq_misc_params_st] [ DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__rq_par ams_st] [DML]:DML_RQ_DLG_CALC: [drm:pid-1:print__data_rq_misc_p arams_st] [DML]:DML_RQ_DLG_CALC: ===================================== 7>[drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_D ATA_RQ_MISC_PARAM_ST [drm:pid-1:print__data_rq_misc_params_st] [D ML]:DML_RQ_DLG_CALC: full_swath_bytes = 0 [drm:pid-1:print__data_r q_misc_params_st] [DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0 [drm:pid-1: print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_width = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_height = 0 [drm:pid-1:print__data_rq_misc_params_s t] [DML]:DML_RQ_DLG_CALC: req_width = 0 [drm :pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_height = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__rq_params_st] [D ML]:DML_RQ_DLG_CALC: *************************** [drm:pid-1:extract_rq_ sizing_regs] [DML]:DLG: extract_rq_sizing_regs: rq_sizing param<7> [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================== ================ [drm:pid-1:print__data_rq_sizing_params_st] [ DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024 [drm:pid-1:print__data_rq_sizing _params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048 [drm:pid-1: print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chun k_bytes = 256 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CAL C: mpte_group_bytes = 2048 [drm:pid-1:print__data_rq_sizin g_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: =============== ====================== [drm:pid-1:dml1_rq_dl g_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cstate_en = 1< 7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_para ms: pstate_en = 1<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_en = 1<7>[drm:pid-1:dml1_rq_dlg_get_dlg_p arams] [DML]:DLG: dml1_rq_dlg_get_dlg_params: iflip_en = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg _params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: interlaced = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dcfclk_mhz = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_ttu_vblank = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_calc_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x11af<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: htotal = 2250<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 130<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_x_after_scaler = 130<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_after_scaler = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.sr_enter_plus_exit_time_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.dram_clock_change_latency_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.urgent_latency_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: swath_height_l = 1<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_srx_delay_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vupdate_offset = 563<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vupdate_width = 254<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vready_offset = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_wait = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_o = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_setup = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_calc = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch (before rnd) = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = %3.2f<7>[drm:pid-1:get_swath_need] [DML]:DLG: get_swath_need: swath_height = 1<7>[drm:pid-1:get_swath_need] [DML]:DLG: get_swath_need: vinit = %3.2f<7>[drm:pid-1:get_swath_need] [DML]:DLG: get_swath_need: max_num_sw = 1<7>[drm:pid-1:get_swath_need] [DML]:DLG: get_swath_need: max_partial_sw = 1<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes_ub_l = 15872<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes_ub_c = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes = 15872<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_bytes = 64<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: meta_row_bytes = 320<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_row_bytes = 64<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_after_scaler = 0x0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->refcyc_x_after_scaler = 0x28<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_prefetch = 44<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw_l = 2<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw_c = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_l = 64<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_c = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: prefetch_bw = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: flip_bw = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_pre_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_vm_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_r0_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_per_row_vblank = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw = %3.2f<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: max_num_sw = 1<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: max_partial_sw = 1<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: swath_height = 1<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: vinit = %3.2f<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: vratio_pre = %3.2f<7>[drm:pid-1:get_vratio_pre] [DML]:WARNING_DLG: get_vratio_pre: vratio_pre=%3.2f < 1.0, set to 1.0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vratio_pre_l=%3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vratio_pre_c=%3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 1920<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 1<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 1920<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 1<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: full_recout_width = 1920<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: hscale_pixel_rate_l = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 1920<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 31<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 1920<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 31<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_req_width = 64<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_width_ub = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_req_per_width = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: hactive_cur0 = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_cur0 = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_cur0 = %3.2f<7>[drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0xb0a [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x4ec [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x4dcd [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x4dcd [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x5065 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x5065 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x59 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x32 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x11af [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0x2c29f [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x28 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0x2c [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x2832e [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x211 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x211 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x211 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_ y_per_pte_row_nom_l = 0x200 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x1614f [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_ nom_c = 0x20 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x1614 [drm:pid-1:print__dlg_regs _st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_deliv ery_pre_l = 0x25a [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0 [drm:pid-1:print__dlg_regs_ st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x25a [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_deli very_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3 [drm:pid-1:pr int__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: v ready_after_vcount0 = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x0 [drm:pid -1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC : xfc_reg_precharge_delay = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: surf_linear = 1<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: surf_vert = 0< 7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: blk256_width = 64<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: blk 256_height = 1<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_blk_height = 64<7> [drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_blk_width = 4096<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_ param: meta_surface_bytes = 0<7>[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_pte_req_per_frame_ub = 1<7 >[drm:pid-1:get_surf_rq_param] [DML]:DLG: get_surf_rq_param: meta_pte_bytes_per_frame_ub = 64<7>[drm:pid-1:handle_det_buf_ split] [DML]:DLG: handle_det_buf_split: req128_l = 0<7>[drm:pid-1:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: req128_c = 0<7>[drm:pi d-1:handle_det_buf_split] [DML]:DLG: handle_det_buf_split: full_swath_bytes_packed_l = 7936<7>[drm:pid-1:handle_det_buf_split] [DML] :DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0<7>[drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: *************************** [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST [drm:pi d-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================== ================ [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST [drm:pid-1:pr int__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DL G_CALC: min_chunk_bytes = 1024 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256 [drm:pid-1:print__data_rq_sizin g_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpt e_group_bytes = 2048 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: === [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM _ST [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: chunk_bytes = 0 [drm:pid-1:print__data_rq_sizing_par ams_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_byte s = 0 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_ DLG_CALC: min_meta_chunk_bytes = 0 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0 [drm:pid- 1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid-1:print __data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_C ALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_width_ub = 1984 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_height = 1 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 31 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_pte _bytes_per_frame_ub = 64 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 1 [drm:pid-1:print__da ta_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 1 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG _CALC: dpte_row_height = 128 [drm:pid-1:print__data_rq_dlg_pa rams_st] [DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 64 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunks_ per_row_ub = 1 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 5 [drm:pi d-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_row_height = 8 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_ RQ_DLG_CALC: meta_bytes_per_row_ub = 320 [drm:pid-1:prin t__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ====== =============================== [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST [drm:pid-1:print__data_rq_dlg_params_s t] [DML]:DML_RQ_DLG_CALC: swath_width_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: swath_heigh t = 1 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_C ALC: req_per_swath_ub = 0 [drm:pid-1:print__dat a_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_ req_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [ DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: dpte_row_h eight = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CAL C: dpte_bytes_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_req_per _row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st ] [DML]:DML_RQ_DLG_CALC: meta_row_height = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0 [drm:pid-1:print__data_rq_dlg_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__rq_params_st ] [DML]:DML_RQ_DLG_CALC: [drm:pid-1:print__data _rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: DISP LAY_DATA_RQ_MISC_PARAM_ST [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: full_swath_bytes = 7936 [drm:pid-1 :print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 15872 [drm:pid-1:print__data_rq_misc_params _st] [DML]:DML_RQ_DLG_CALC: blk256_width = 64 [drm:pid-1:prin t__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_height = 1 [drm:pid-1:p rint__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_width = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]: DML_RQ_DLG_CALC: req_height = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: ================================ ===== [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: < CHROMA> [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: =========== ========================== [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST [drm:pid-1:p rint__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: stored_sw ath_bytes = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_width = 0 [drm:pid-1:p rint__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: blk256_height = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: req_width = 0 [drm:pid-1:print__data_rq_misc_param s_st] [DML]:DML_RQ_DLG_CALC: req_height = 0 [drm:pid-1:print__data_rq_misc_params_st] [DML]:DML_RQ_DLG_CALC: =========================== ========== [drm:pid-1:print__rq_params_st] [DML]:DML_RQ_DLG_CALC: *************************** [drm:pid-1:extract_rq_sizing_regs] [DML]:DLG: extract_rq_sizing_regs: rq_sizing param<7>[drm:pid-1:print__data_r q_sizing_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== 7>[drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: DISPL AY_DATA_RQ_SIZING_PARAM_ST [drm:pid-1:print__data_rq_sizing_params_st] [DML]:D ML_RQ_DLG_CALC: chunk_bytes = 8192 [drm:pid-1:p rint__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024 7>[drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048 [drm:pid-1:print__data_rq_sizing_params_ st] [DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG_CALC: mpte_group_byt es = 2048 [drm:pid-1:print__data_rq_sizing_params_st] [DML]:DML_RQ_DLG _CALC: dpte_group_bytes = 2048 [drm:pid-1:print__data_rq_sizin g_params_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG : dml1_rq_dlg_get_dlg_params: cstate_en = 1<7>[drm:pid-1:dml1_rq_dlg_ get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pstate_en = 1<7>[drm:pid- 1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_en = 1<7>[ drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_d lg_params: iflip_en = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = %3.2f<7>[drm:pid-1:d ml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dispc lk_freq_in_mhz = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_r q_dlg_get_dlg_params: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:dml 1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: pclk_freq _in_mhz = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get _dlg_params: interlaced = 0<7>[drm:p id-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_dc fclk_mhz = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_ dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: min_ttu_vblank = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get _dlg_params: min_dst_y_ttu_vblank = %3.2f<7>[drm:pid-1:d ml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_calc_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [ DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x118b [drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = %3.2f<7 >[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: htotal = 2200<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DM L]:DLG: dml1_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 126<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params ] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_x_after_scaler = 126<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_ get_dlg_params: dst_y_after_scaler = 0<7>[drm:pid-1:d ml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: soc.sr_ent er_plus_exit_time_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]: DLG: dml1_rq_dlg_get_dlg_params: soc.dram_clock_change_latency_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DL G: dml1_rq_dlg_get_dlg_params: soc.urgent_latency_us = %3.2f<7>[drm:pid- 1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params : swath_height_l = 1<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1 _rq_dlg_get_dlg_params: t_srx_delay_us = %3.2f<7>[drm:pid-1:d ml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = % 3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vupdate_offset = 550<7>[drm:pid-1:dml1_rq_dlg_get_dl g_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vupdate_width = 24 7<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vrea dy_offset = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_time_in_us = %3.2f<7>[ drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_w ait = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dl g_get_dlg_params: line_o = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: line_setup = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1 _rq_dlg_get_dlg_params: line_calc = %3.2f<7>[drm:pid-1:dml1 _rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch (bef ore rnd) = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = %3.2f<7>[d rm:pid-1:get_swath_need] [DML]:DLG: get_swath_need: swath_height = 1< 7>[drm:pid-1:get_swath_need] [DML]:DLG: get_swath_need: vinit = %3.2f<7>[drm:pid-1:get_swath_need] [DML]:DLG: get_swath_need: max_num_sw = 1<7>[drm:pid-1:get_swath_need] [DML]:DLG: get_swath_n eed: max_partial_sw = 1<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG : dml1_rq_dlg_get_dlg_params: sw_bytes_ub_l = 15872<7>[d rm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes_ub_c = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML ]:DLG: dml1_rq_dlg_get_dlg_params: sw_bytes = 15872<7>[dr m:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vm_ bytes = 64<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq _dlg_get_dlg_params: meta_row_bytes = 320<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_row_bytes = 64<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_after_scaler = 0x0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->refcyc_x_after_scaler = 0x28<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: disp_dlg_regs->dst_y_prefetch = 44<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw_l = 2<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw_c = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_l = 64<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dpte_bytes_per_row_ub_c = 0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: prefetch_bw = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: flip_bw = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_pre_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_vm_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: t_r0_us = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_per_row_vblank = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: dst_y_prefetch = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: lsw = %3.2f<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: max_num_sw = 1<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: max_partial_sw = 1<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: swath_height = 1<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: vinit = %3.2f<7>[drm:pid-1:get_vratio_pre] [DML]:DLG: get_vratio_pre: vratio_pre = %3.2f<7>[drm:pid-1:get_vratio_pre] [DML]:WARNING_DLG: get_vratio_pre: vratio_pre=%3.2f < 1.0, set to 1.0<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vratio_pre_l=%3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: vratio_pre_c=%3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 1920<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 1<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 1920<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 1<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: full_recout_width = 1920<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: hscale_pixel_rate_l = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 1920<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 31<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: recout_width = 1920<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: vratio = %3.2f<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: req_per_swath_ub = 31<7>[drm:pid-1:get_refcyc_per_delivery] [DML]:DLG: get_refcyc_per_delivery: refcyc_per_delivery= %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_req_width = 64<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_width_ub = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: cur0_req_per_width = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: hactive_cur0 = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_cur0 = %3.2f<7>[drm:pid-1:dml1_rq_dlg_get_dlg_params] [DML]:DLG: dml1_rq_dlg_get_dlg_params: refcyc_per_req_delivery_cur0 = %3.2f<7>[drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0xb1c [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x4ec [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x5014 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x5014 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x52bf [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x52bf [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0 [drm:pid-1:print__ttu_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x3e [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x29 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x118b [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0x2c71c [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x28 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_prefet ch = 0x2c [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst _y_per_row_flip = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x295fa [dr m:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000 [drm:pid-1:print__dlg_regs_st] [DML]:D ML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x215 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML _RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x215 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_ chunk_vblank_c = 0x215 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0 [drm:pid-1:print_ _dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: r efcyc_per_meta_chunk_flip_l = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0 [dr m:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200 [drm:pid-1:print__dlg_regs_st] [DM L]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x1638e [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0 [drm:pid-1:print__d lg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_per_meta_ro w_nom_c = 0x20 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x1638 [drm:pid-1:print__dlg_reg s_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_d elivery_pre_l = 0x26c [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0 [drm:pid-1:print__dlg _regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x26c [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: refcyc_per_li ne_delivery_c = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3 [drm:pid-1:print__dlg_reg s_st] [DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: chunk_hdl_adj ust_cur1 = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x0 [drm:pid-1:print __dlg_regs_st] [DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CAL C: xfc_reg_transfer_delay = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_f lip_latency = 0x0 [drm:pid-1:print__dlg_regs_st] [DML]:DML_RQ_DLG_CALC: ===================================== 7>[drm:pid-1:drm_atomic_commit] committing 0xfffff8012f4ef980 7>[drm:pid-1:dm_plane_helper_prepare_fb] No FB bound [drm:pid-1:dm_plane_helper_prepare_fb] No FB bound 7>[drm:pid-1:dm_plane_helper_prepare_fb] No FB bound [drm:pid-1:dm_plane_helper_prepare_fb] No FB bound [drm:pid-1:dm_plane_helper_p repare_fb] No FB bound [drm:pid-1:dm_plane_helper_prepare_fb] No FB bound 7>[drm:pid-1:drm_calc_timestamping_constants] crtc 42: hwmod e: htotal 2250, vtotal 1132, vdisplay 1080 [drm:pid-1:drm_calc_timestamping_constants] crtc 42: clock 152840 kHz framedur 16664485 linedur 14721 [drm:pid-1:drm_calc_timestamping_constants] crtc 44: hwmode: htotal 2200, vtotal 1125, vdisplay 1080 [drm:pid-1:drm_calc_timestamping_constants] crtc 44: clock 148500 kHz framedur 1666666 6 linedur 14814 [drm:pid-1:amdgpu_dm_atomic_commit_tail] am dgpu_crtc id:0 crtc_state_flags: enable:1, active:1, planes_changed:1, mode_changed:0,active_changed:0,connectors_changed:0 [drm:pid-1:a mdgpu_dm_atomic_commit_tail] amdgpu_crtc id:1 crtc_state_flags: enable:1, active:1, pl anes_changed:1, mode_changed:1,active_changed:1,connectors_changed:1 7>[drm:pid-1:amdgpu_dm_atomic_commit_tail] Atomic commit: SET crtc id 1: [0xfffff8013c309a00] [drm:pid-1:amdgpu_dm_atomic_commit_tai l] amdgpu_crtc id:2 crtc_state_flags: enable:0, active:0, planes_changed:0, mode_changed:0,active_changed:0,connectors_changed:0 [drm :pid-1:amdgpu_dm_atomic_commit_tail] amdgpu_crtc id:3 crtc_state_flags: enable:0, acti ve:0, planes_changed:0, mode_changed:0,active_changed:0,connectors_changed:0 7>[drm:pid-1:dc_commit_state] dc_commit_state: 2 streams [drm:pid-1:dc_stream_log] core_stream 0x0xfffff8013b79a4c0: src : 0, 0, 1920, 1080; dst: 0, 0, 1920, 1080, colorSpace:1 [drm:pid-1: dc_stream_log] pix_clk_khz: 152840, h_total: 2250, v_total: 1132, pixelencoder:1, displaycolorDepth:1 [drm:pid-1:dc_stream_log] sink name: , serial: 0 [drm:pid-1:dc_stream_log] link: 0 [ drm:pid-1:dc_stream_log] core_stream 0x0xfffff8013b79a140: sr c: 0, 0, 1920, 1080; dst: 0, 0, 1920, 1080, colorSpace:1 [drm:pid-1 :dc_stream_log] pix_clk_khz: 148500, h_total: 2200, v_total: 1125, pixelencoder:1, displaycolorDepth:2 [drm:pid-1:dc_stream_lo g] sink name: DELL U2415, serial: 810172755 [drm:pid-1:dc_stream_log] link: 3 7>[drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_fre quency = 155140clock_type = 0 7>[drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0c lock_type = 1 [drm:pid-1:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =20935 HW register value = 0x3ec [drm:pid- 1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f 7>[drm:pid-1:dc_commit_state_no_check] dfly: set_bandwidth#1 7>[drm:pid-1:dcn10_apply_ctx_for_surface] Reset mpcc for pipe 3 7>[drm:pid-1:power_on_plane] Un-gated front end for pipe 0 [drm:pid-1:generic_reg_wait] REG_WAIT taking a while: 7ms in mpc1_assert_idle_mpcc line:103 [drm:pid-1:plane_atomic_power_down] Power gated front end 3 [drm:pid-1:dcn10_disable_plane] Power down front end 3 [drm:pid-1:dc_commit_state_no_check] dfly: streams[1].mode_changed == false [drm:pid-1:dc_commit_state_no_check] dfly: ready_shared_resources [drm:pid-1:dce110_apply_ctx_to_hw] dfly: reset_hw_ctx_wrap [drm:pid-1:read_indirect_azalia_reg] [HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 1 [drm:pid-1:read_indirect_azalia_reg] [HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 37 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 37 data: 131073 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 40 data: 117901057 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 41 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 42 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 43 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 44 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 45 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 46 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 47 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 49 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 50 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 51 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 53 data: 0 [drm:pid-1:read_indirect_azalia_reg] [HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 56 data: 1 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 56 data: 1 [drm:pid-1:read_indirect_azalia_reg] [HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 55 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 55 data: 0 [drm:pid-1:read_indirect_azalia_reg] [HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 55 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 55 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 58 data: 2696588304 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 59 data: 11 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 60 data: 1431864734 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 61 data: 228103241 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 62 data: 1280066884 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 63 data: 875713824 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 64 data: 13617 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 65 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 66 data: 0 [drm:pid-1:read_indirect_azalia_reg] [HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 17 [drm:pid-1:write_indirect_azal a_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 16 [drm:pid-1:set_pixel_clock_v7] [BIOS]:set_pixel_clock_v7:program display clock = 148500colorDepth = 0 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00111 AUX -> (ret= 1) fffff8031e3cf34fh [drm:pid-1 :drm_dp_dump_access] dmdc: 0x00111 AUX <- (ret= 1) fffff8031e3cf34fh [drm:pid-1:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltag e = 626000 [drm:pid-1:transmitter_control_v1_6] [BIOS]:transmitter_control_v1_6:ps.param.symclk_10khz = 81000 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00600 AUX <- (ret= 1) fffff8031e3cf2bfh [drm:pid-1:dpcd_configure_panel_mode] Link: 3 eDP panel mode supported: 0 eDP panel mode enabled: 0 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00100 AUX <- (ret= 2) fffff8031e3cf16eh [drm:pid-1:drm_dp_dump_access] dmdc: 0x00107 AUX <- (ret= 1) fffff8031e3cf16dh [drm:pid-1:dpcd_set_link_settings] [HW_LINK_TRAINING]:dpcd_set_link_settings 100 rate = 1e 101 lane = 2 107 spread = 10 [drm:pid-1:dpcd_set_lt_pattern_and_lane_settings] [HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings 102 pattern = 1 [drm:pid-1:dpcd_set_lt_pattern_and_lane_settings] [HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings: 103 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00102 AUX <- (ret= 3) fffff8031e3cf15bh [drm:pid-1:drm_dp_dump_access] dmdc: 0x0000e AUX -> (ret= 1) fffff8031e3cf16fh [drm:pid-1:wait_for_training_aux_rd_interval] [HW_LINK_TRAINING]:wait_for_training_aux_rd_interval: wait = 16000 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00202 AUX -> (ret= 6) fffff8031e3cf10ah [drm:pid-1:get_lane_status_and_drive_settings] [HW_LINK_TRAINING]:get_lane_status_and_drive_settings: 202 Lane01Status = 0 203 Lane23Status = 0 <7>[drm:pid-1:get_lane_status_and_drive_settings] [HW_LINK_TRAINING]:get_lane_status_and_drive_settings: 206 Lane01AdjustRequest = 22 207 Lane23AdjustRequest = 22 [drm:pid-1:dpcd_set_lt_pattern_and_lane_settings] [HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings 102 pattern = 1 [drm:pid-1:dpcd_set_lt_pattern_and_lane_settings] [HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings: 103 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00102 AUX <- (ret= 3) fffff8031e3cf15bh [drm:pid-1:drm_dp_dump_access] dmdc: 0x0000e AUX -> (ret= 1) fffff8031e3cf16fh [drm:pid-1:wait_for_training_aux_rd_interval] [HW_LINK_TRAINING]:wait_for_training_aux_rd_interval: wait = 16000 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00202 AUX -> (ret= 6) fffff8031e3cf10ah [drm:pid-1:get_lane_status_and_drive_settings] [HW_LINK_TRAINING]:get_lane_status_and_drive_settings: 202 Lane01Status = 11 203 Lane23Status = 0 <7>[drm:pid-1:get_lane_status_and_drive_settings] [HW_LINK_TRAINING] :get_lane_status_and_drive_settings: 206 Lane01AdjustRequest = 22 207 Lane23AdjustRequest = 22 7>[drm:pid-1:dpcd_set_lt_pattern_and_lane_settings] [HW_LINK_TRAINING]:dpcd_set_lt_pattern_and _lane_settings 102 pattern = 7 [drm:pid-1:dpcd_set_lt_pattern_a nd_lane_settings] [HW_LINK_TRAINING]:dpcd_set_lt_pattern_and_lane_settings: 103 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00102 AUX <- (ret= 3) fffff8031e3cf15bh [drm:pid-1:drm_dp_dump_access] dmdc: 0x0000e AUX -> (ret= 1) fffff8031e3cf16fh [drm:pid-1:wait_for_training_aux_rd_interval] [HW_LINK_TRAINING]:wait_for_training_aux_rd_interval: wait = 16000 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00202 AUX -> (ret= 6) fffff8031e3cf10ah [drm:pid-1:get_lane_status_and_drive_settings] [HW_LINK_TRAINING]:get_lane_status_and_drive_settings: 202 Lane01Status = 77 203 Lane23Status = 0 <7>[drm:pid-1:get_lane_status_and_drive_settings] [HW_LINK_TRAINING]:get_lane_status_and_drive_settings: 206 Lane01AdjustRequest = 22 207 Lane23AdjustRequest = 22 [drm:pid-1:drm_dp_dump_access] dmdc: 0x00102 AUX <- (ret= 1) fffff8031e3cf230h [drm:pid-1:dpcd_set_training_pattern] [HW_LINK_TRAINING]:dpcd_set_training_pattern 102 pattern = 0 [drm:pid-1:dc_link_dp_perform_link_training] HBR3x2 pass VS=2, PE=0<7>[drm:pid-1:drm_dp_dump_access] dmdc: 0x00107 AUX -> (ret= 1) fffff8031e3cf30fh [drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm:pid-1:gfx_v9_0_ring_test_ib] ib test on ring 0 succeeded drm: expand RCU cpu 0 to 16 [drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm:pid-1:gfx_v9_0_ring_test_ib] ib test on ring 1 succeeded [drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm:pid-1:gfx_v9_0_ring_test_ib] ib test on ring 2 succeeded [drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm:pid-1:gfx_v9_0_ring_test_ib] ib test on ring 3 succeeded [drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm:pid-1:gfx_v9_0_ring_test_ib] ib test on ring 4 succeeded [drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm:pid-1:gfx_v9_0_ring_test_ib] ib test on ring 5 succeeded [drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm:pid-1:gfx_v9_0_ring_test_ib] ib test on ring 6 succeeded [drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm:pid-1:gfx_v9_0_ring_test_ib] ib test on ring 7 succeeded 7>[drm:pid-1:gfx_v9_0_eop_irq] IH: CP EOP [drm :pid-1:gfx_v9_0_ring_test_ib] ib test on ring 8 succeeded 7>[drm:pid-1:sdma_v4_0_ring_set_wptr] Setting write pointer [drm:pid-1: sdma_v4_0_ring_set_wptr] Using doorbell -- wptr_offs == 0x00000150 lower_32_bits(ring->wptr) << 2 == 0x00000140 upper_32_bits(ring->wptr) << 2 == 0x0 0000000 [drm:pid-1:sdma_v4_0_ring_set_wptr] calling WD OORBELL64(0x000001c0, 0x0000000000000140) 7>[drm:pid-1:sdma_v4_0_process_trap_irq] IH: SDMA trap 7>[drm:pid-1:amdgpu_irq_dispatch] Unhandled interrupt src_id: 243 [drm:pid-1:vcn_v1_0_process_interrupt] IH: VCN TRAP [drm:pid-1:vcn_v1_0_process_interrupt] IH: VCN TRAP [drm:pid-1:vcn_v1_0_process_interrupt] IH: VCN TRAP [drm:pid-1:vcn_v1_0_process_interrupt] IH: VCN TRAP [drm:pid-1:vcn_v1_0_process_interrupt] IH: VCN TRAP [drm:pid-1:vcn_v1_0_process_interrupt] IH: VCN TRAP [drm:pid-1:vcn_v1_0_process_interrupt] IH: VCN TRAP [drm:pid-1:amdgpu_vcn_jpeg_ring_test_ib] ib test on ring 14 succeeded [drm:pid-1:read_indirect_azalia_reg] [HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 2147483649 [drm:pid-1:write_indirect_azalia_reg] [HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 2147483648 [drm:pid-1:dce_aud_az_enable] [HW_AUDIO]: ========= AUDIO:dce_aud_az_enable: index: 3 data: 0x80000000 [drm:pid-1:drm_dp_mst_allocate_vcpi] initing vcpi for pbn=532 slots=27 [drm:pid-1:drm_dp_dump_access] dmdc: 0x002c0 AUX <- (ret= 1) fffff8031e3cf26dh [drm:pid-1:drm_dp_dump_access] dmdc: 0x001c0 AUX <- (ret= 3) fffff8031e3cf26dh [drm:pid-1:drm_dp_dump_access] dmdc: 0x002c0 AUX -> (ret= 1) fffff8031e3cf26ch [drm:pid-1:allocate_mst_payload] allocate_mst_payload stream_count: 1: <7>[drm:pid-1:allocate_mst_payload] stream_enc[0]: 0xfffff8012f4af380 stream[0].vcp_id: 1 stream[0].slot_count: 27 [drm:pid-1:allocate_mst_payload] stream_enc[1]: 0 stream[1].vcp_id: 0 stream[1].slot_count: 0 [drm:pid-1:allocate_mst_payload] stream_enc[2]: 0 stream[2].vcp_id: 0 stream[2].slot_count: 0 [drm:pid-1:allocate_mst_payload] stream_enc[3]: 0 stream[3].vcp_id: 0 stream[3].slot_count: 0 [drm:pid-1:allocate_mst_payload] stream_enc[4]: 0 stream[4].vcp_id: 0 stream[4].slot_count: 0 [drm:pid-1:allocate_mst_payload] stream_enc[5]: 0 stream[5].vcp_id: 0 stream[5].slot_count: 0 [drm:pid-1:drm_dp_dump_access] dmdc: 0x002c0 AUX -> (ret= 1) fffff8031e3cf32fh [drm:pid-1:drm_dp_update_payload_part2] payload 0 1 7>[drm:pid-1:drm_dp_dump_access] dmdc: 0x01000 AUX <- (ret= 10) fffff8031e3cf150h [drm:pid-1:dm_irq_work_func] DM_IRQ: work_func: for dal_src=10 [drm:pid-1:dm_irq_work_func] DM_IRQ: schedule_work: for dal_src=10 [drm:pid-1:dc_link_handle_hpd_rx_irq] dc_link_handle_hpd_rx_irq: Got short pulse HPD on link 3 [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 14) fffff8031e37b960h [drm:pid-1:drm_dp_dump_access] dmdc: 0x02002 AUX -> (ret= 4) fffff8031e37ba1ch [drm:pid-1:dm_handle_hpd_rx_irq] ESI 01 14 00 [drm:pid-1:drm_dp_dump_access] dmdc: 0x01400 AUX -> (ret= 16) fffff8031e37b890h [drm:pid-1:dce110_apply_ctx_to_hw] dfly: apply_single_controller_ctx_to_hw status = 1, i = 1<7>[drm:pid-1:dc_commit_state_no_check] dfly: apply_ctx_to_hw result: 1 [drm:pid-1:dc_commit_state_no_check] dfly: streams[0].mode_changed == false [drm:pid-1:power_on_plane] Un-gated front end for pipe 1 [drm:pid-1:dc_commit_state_no_check] {1920x1080, 2200x1125@148500Khz}<7>[drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 155140clock_type = 0 [drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 [drm:pid-1:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_prog ram_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf >[drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EX IT_WATERMARK_C calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_w atermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDT H_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [ drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf 7>[drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_progra m_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CAL CS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f 7>[drm:pid-1:dc_commit_state_no_check] dfly: set_bandwidth#2 7>[drm:pid-1:drm_vblank_enable] enabling vblank on crtc 0, ret: 0 7>[drm:pid-1:prepare_flip_isr] crtc:0, pflip_stat:AMDGPU_FLIP_SUBMITTED 7>[drm:pid-1:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:1920 x:0 y:0 dst_rec t: height:1080 width:1920 x:0 y:0 [drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_freq uency = 155140clock_type = 0 7>[drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 7>[drm:pid-1:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BA NDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_C ALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWID TH_CALCS]:SR_EXIT_WATERMARK_A calculated =20935 HW register value = 0x3ec 7>[drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calcula ted =23983 HW register value = 0x47f [drm:pid-1 :hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_wa termarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW registe r value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [B ANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f 7>[drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_ program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_wat ermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register valu e = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWID TH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf 7>[drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C c alculated =21983 HW register value = 0x41f [drm:pid-1: hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =2 0935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid-1:hu bbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f 7>[drm:pid-1:context_clock_trace] [BANDWIDTH_CALCS]:Current: dispclk_khz:155140 max_dppcl k_khz:155140 dcfclk_khz:300000 dcfclk_deep_sleep_khz:10507 fclk_khz:400000 socclk_khz:0 [drm:pid-1:context_clock_trace] [BANDWIDTH_CALCS]: Calculated: dispclk_khz:155140 max_dppclk_khz:155140 dcfclk_khz:300000 dcfclk_deep_sleep_khz:10507 fclk_khz:400000 socclk_khz:0 7>[drm:pid-1:power_on_plane] Un-gated front end for pipe 0 [drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 155140clock_type = 0 [drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 [drm:pid-1:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_C LK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f 7>[drm:pid-1:drm_vblank_enable] enabling vblank on crtc 1, ret: 0 7>[drm:pid-1:prepare_flip_isr] crtc:1, pflip_stat:AMDGPU_FLIP_SUBMITTED 7>[drm:pid-1:resource_build_scaling_params] [SCALER]:resource_build_scaling_params: Viewport: height:1080 width:1920 x:0 y:0 dst_r ect: height:1080 width:1920 x:0 y:0 [drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_ clock_frequency = 155140clock_type = 0 [drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 [drm:pid-1:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CH ANGE_WATERMARK_D calculated =23983 HW register value = 0x47f [drm:pid-1:context_clock_trace] [BANDWIDTH_C ALCS]:Current: dispclk_khz:155140 max_dppclk_khz:155140 dcfclk_khz:300000 dcfclk_deep_sleep_khz:10507 fclk_khz:400000 socclk_khz:0 [drm:pid-1:c ontext_clock_trace] [BANDWIDTH_CALCS]:Calculated: dispclk_khz:155140 max_dppclk_khz:155140 dcfclk_khz:300000 dcfclk_deep_sleep_khz:10507 fcl k_khz:400000 socclk_khz:0 7>[drm:pid-1:power_on_plane] Un-gated front end for pipe 1 [drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock _frequency = 155140clock_type = 0 [drm:pid-1:set_dce_clock_v2_1] [BIOS]:set_dce_clock_v2_1:target_clock_frequency = 0clock_type = 1 [drm:pid-1:dcn_find_dcfclk_suits_all] [BANDWIDTH_CALCS]: dcf_clk for voltage = 300000 [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =23983 HW register value = 0x47f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =6983 HW register value = 0x14f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =14983 HW register value = 0x2cf [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =21983 HW register value = 0x41f [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =20935 HW register value = 0x3ec [drm:pid-1:hubbub1_program_watermarks] [BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =23983 HW register value = 0x47f 7>[drm:pid-1:drm_atomic_state_default_clear] Clearing atomic state 0xfffff8012f4ef980 7>[drm:pid-1:__drm_atomic_state_free] Freeing atomic state 0xfffff8012f4ef980 [drm:pid-1:vblank_disable_fn] disabling vblank on crtc 0 [drm:pid-1:vblank_disable_fn] disabling vblank on crtc 1