git: acpi/pstate: Fix the long standing P-State detection problem on Intel CPUs

[Sepherosa Ziehau <sephe@xxxxxxxxxxxxxxxxxxxxxxx>]

commit 47cf4819ea1fbf8eb9d0da5cd92623dcac44298b
Author: Sepherosa Ziehau <sephe@dragonflybsd.org>
Date:   Thu Dec 29 16:33:11 2011 +0800

    acpi/pstate: Fix the long standing P-State detection problem on Intel CPUs
    
    - Rename the ACPI_CAP to ACPI_PDC according to Intel's document.
      While I'm here, update the document revision.
    - Remove unapplied comment about _OSC and _PDC's revision; Intel's
      document states clearly that it should be 1
    - Fix the 'Count' argument for _OSC evaluation; the intergers in
      'Capabilities buffer' argument is 2
    - Fix the buffer length of _OSC's 'Capabilities buffer'; we only
      pass 2 intergers.
    - Perfer _OSC evaluation, fall back to _PDC evaluation only if _OSC
      evaluation fails.
    - Add MD cpu features, so MD code could deliver proper settings.
      For AMD CPUs, the old configuration just works (AMD actually has
      no documents about _PDC and _OSC).
      For Intel CPUs w/ EST, it looks like P-State's _PCT will appear
      only when bit0 (P-State MSR), bit5 (P-State software coordination)
      and bit11 (P-State hardware coordination) are turned on.

Summary of changes:
 sys/dev/acpica5/Makefile                     |    2 +
 sys/dev/acpica5/acpi_cpu.c                   |   59 ++++++++++++++++++++++-
 sys/dev/acpica5/acpi_cpu.h                   |    2 +
 sys/dev/acpica5/acpi_cpu_cstate.c            |   68 +-------------------------
 sys/dev/acpica5/acpivar.h                    |   22 +++++----
 sys/platform/pc32/acpica5/acpi_cpu_machdep.c |   26 ++++++++++
 sys/platform/pc64/acpica5/acpi_cpu_machdep.c |   26 ++++++++++
 7 files changed, 128 insertions(+), 77 deletions(-)
 create mode 100644 sys/platform/pc32/acpica5/acpi_cpu_machdep.c
 create mode 100644 sys/platform/pc64/acpica5/acpi_cpu_machdep.c

http://gitweb.dragonflybsd.org/dragonfly.git/commitdiff/47cf4819ea1fbf8eb9d0da5cd92623dcac44298b


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