cvs commit: src/sys/dev/acpica5 src/sys/i386/i386 src/sys/i386/include

[Matthew Dillon <dillon@xxxxxxxxxxxxxxxxxxxxxxx>]

dillon      2004/11/20 12:50:36 PST

DragonFly src repository

  Modified files:
    sys/dev/acpica5      acpi_cpu.c 
    sys/i386/i386        machdep.c mplock.s 
    sys/i386/include     lock.h 
  Log:
  Fix a number of SMP issues.
  
  * Add required pause instructions in code paths that skip running "HLT".  This
    occurs when e.g. cpu #1 is running code with the BGL while cpu #2's only
    runnable thread requires the BGL.  cpu #2's LWKT scheduler spins in that
    case.  Similar situations can occur when the only runnable threads on a
    cpu are waiting for a token.
  
  * Add required pause instructions to spin loops.  DragonFly has very few spin
    locks (e.g. things like com_lock()) but its a good idea anyway to avoid
    known livelock issues on Intel cpus.
  
  * Fix a pending interrupt / HLT race.  We were not atomically retiring
    pending interrupts prior to potentially HLTing the cpu.  This could
    result in an SMP machine's network locking up until a key is hit on
    the console, then magically resuming.
  
  Lockups-reported-by: Peter Avalos <pavalos@xxxxxxxxxxxx>
  
  Revision  Changes    Path
  1.7       +12 -1     src/sys/dev/acpica5/acpi_cpu.c
  1.68      +10 -1     src/sys/i386/i386/machdep.c
  1.15      +1 -0      src/sys/i386/i386/mplock.s
  1.10      +1 -0      src/sys/i386/include/lock.h


http://www.dragonflybsd.org/cvsweb/src/sys/dev/acpica5/acpi_cpu.c.diff?r1=1.6&r2=1.7&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/i386/machdep.c.diff?r1=1.67&r2=1.68&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/i386/mplock.s.diff?r1=1.14&r2=1.15&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/i386/include/lock.h.diff?r1=1.9&r2=1.10&f=u