Re: missing CFCR flag in sioreg.h

[Robert Garrett <rg70@xxxxxxxxxxxxx>]

This patch i believe cleanly fixes the problem, and IMHO is prlly
the way it should of been dealt with.

Index: sio.c
===================================================================
RCS file: /usr/home/dcvs/src/sys/dev/serial/sio/sio.c,v
retrieving revision 1.11
diff -u -r1.11 sio.c
--- sio.c	11 Jan 2004 16:45:17 -0000	1.11
+++ sio.c	22 Jan 2004 04:32:59 -0000
@@ -101,7 +101,6 @@
 #ifdef COM_ESP
 #include "../ic_layer/esp.h"
 #endif
-#include "../ic_layer/ns16550.h"
 
 #define	LOTS_OF_EVENTS	64	/* helps separate urgent events from input */
 
Index: sioreg.h
===================================================================
RCS file: /usr/home/dcvs/src/sys/dev/serial/sio/sioreg.h,v
retrieving revision 1.5
diff -u -r1.5 sioreg.h
--- sioreg.h	22 Jan 2004 04:19:29 -0000	1.5
+++ sioreg.h	22 Jan 2004 04:37:43 -0000
@@ -32,97 +32,20 @@
  *
  *	from: @(#)comreg.h	7.2 (Berkeley) 5/9/91
  * $FreeBSD: src/sys/isa/sioreg.h,v 1.15.2.3 2003/04/04 08:42:17 sobomax Exp $
- * $DragonFly$
+ * $DragonFly: src/sys/dev/serial/sio/sioreg.h,v 1.4 2004/01/21 21:33:19 rob Exp $
  */
+#ifndef _SIOREG_H
+#define _SIOREG_H
+
+#include "../ic_layer/ns16550.h"
 
 /* Receiver clock frequency for "standard" pc serial ports. */
 #define	DEFAULT_RCLK	1843200
-
-/* interrupt enable register */
-#define	IER_ERXRDY	0x1
-#define	IER_ETXRDY	0x2
-#define	IER_ERLS	0x4
-#define	IER_EMSC	0x8
-
-/* interrupt identification register */
-#define	IIR_IMASK	0xf
-#define	IIR_RXTOUT	0xc
-#define	IIR_RLS		0x6
-#define	IIR_RXRDY	0x4
-#define	IIR_TXRDY	0x2
-#define	IIR_NOPEND	0x1
-#define	IIR_MLSC	0x0
-#define	IIR_FIFO_MASK	0xc0	/* set if FIFOs are enabled */
-
-/* fifo control register */
-#define	FIFO_ENABLE	0x01
-#define	FIFO_RCV_RST	0x02
-#define	FIFO_XMT_RST	0x04
-#define	FIFO_DMA_MODE	0x08
-#define	FIFO_RX_LOW	0x00
-#define	FIFO_RX_MEDL	0x40
-#define	FIFO_RX_MEDH	0x80
-#define	FIFO_RX_HIGH	0xc0
-
-/* character format control register (aka line control register) */
-#define	CFCR_SBREAK	0x40
-#define	CFCR_PZERO	0x30
-#define	CFCR_PONE	0x20
-#define	CFCR_PEVEN	0x10
-#define	CFCR_PODD	0x00
-#define	CFCR_PENAB	0x08
-#define	CFCR_STOPB	0x04
-#define	CFCR_8BITS	0x03
-#define	CFCR_7BITS	0x02
-#define	CFCR_6BITS	0x01
-#define	CFCR_5BITS	0x00
-
-/* modem control register */
-#define	MCR_PRESCALE	0x80		/* only available on 16650 up */
-#define	MCR_LOOPBACK	0x10
-#define	MCR_IENABLE	0x08
-#define	MCR_DRS		0x04
-#define	MCR_RTS		0x02
-#define	MCR_DTR		0x01
-
-/* line status register */
-#define	LSR_RCV_FIFO	0x80
-#define	LSR_TSRE	0x40
-#define	LSR_TXRDY	0x20
-#define	LSR_BI		0x10
-#define	LSR_FE		0x08
-#define	LSR_PE		0x04
-#define	LSR_OE		0x02
-#define	LSR_RXRDY	0x01
-#define	LSR_RCV_MASK	0x1f
-
-/* modem status register */
-#define	MSR_DCD		0x80
-#define	MSR_RI		0x40
-#define	MSR_DSR		0x20
-#define	MSR_CTS		0x10
-#define	MSR_DDCD	0x08
-#define	MSR_TERI	0x04
-#define	MSR_DDSR	0x02
-#define	MSR_DCTS	0x01
-
-/* enhanced feature register (only available on 16650 up) */
-#define	EFR_EFE		0x10		/* enhanced functions enable */
-
-#ifdef PC98
-/* Hardware extension mode register for RSB-2000/3000. */
-#define	EMR_EXBUFF	0x04
-#define	EMR_CTSFLW	0x08
-#define	EMR_DSRFLW	0x10
-#define	EMR_RTSFLW	0x20
-#define	EMR_DTRFLW	0x40
-#define	EMR_EFMODE	0x80
-#endif
-
 /* speed to initialize to during chip tests */
 #define SIO_TEST_SPEED	9600
-
 /* default serial console speed if not set with sysctl or probed from boot */
 #ifndef CONSPEED
 #define CONSPEED 9600
 #endif
+
+#endif