From b549eadbf113c16f3886019c126bfc10174a44ab Mon Sep 17 00:00:00 2001
From: Sascha Wildner <saw@online.de>
Date: Mon, 24 Feb 2014 08:45:22 +0100
Subject: [PATCH] WIP arcmsr(4): Sync with FreeBSD (1.20.00.25 -> 1.20.00.29).

---
 share/man/man4/arcmsr.4      |   10 +-
 sys/dev/raid/arcmsr/arcmsr.c | 2191 +++++++++++++++++++++------------
 sys/dev/raid/arcmsr/arcmsr.h | 2785 ++++++++++++++++++++++--------------------
 3 files changed, 2897 insertions(+), 2089 deletions(-)

diff --git a/share/man/man4/arcmsr.4 b/share/man/man4/arcmsr.4
index 8935339..9cfac5d 100644
--- a/share/man/man4/arcmsr.4
+++ b/share/man/man4/arcmsr.4
@@ -22,9 +22,9 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: src/share/man/man4/arcmsr.4,v 1.8 2012/09/04 05:15:54 delphij Exp $
+.\" $FreeBSD: head/share/man/man4/arcmsr.4 259564 2013-12-18 19:23:05Z delphij $
 .\"
-.Dd September 25, 2012
+.Dd February 23, 2014
 .Dt ARCMSR 4
 .Os
 .Sh NAME
@@ -106,12 +106,16 @@ ARC-1212
 .It
 ARC-1213
 .It
+ARC-1214
+.It
 ARC-1220
 .It
 ARC-1222
 .It
 ARC-1223
 .It
+ARC-1224
+.It
 ARC-1230
 .It
 ARC-1231
@@ -159,6 +163,8 @@ ARC-1880ix
 ARC-1880ixl
 .It
 ARC-1882
+.It
+ARC-1883
 .El
 .Sh FILES
 .Bl -tag -width ".Pa /dev/arcmsr?" -compact
diff --git a/sys/dev/raid/arcmsr/arcmsr.c b/sys/dev/raid/arcmsr/arcmsr.c
index f08380d..f0467c8 100644
--- a/sys/dev/raid/arcmsr/arcmsr.c
+++ b/sys/dev/raid/arcmsr/arcmsr.c
@@ -1,17 +1,15 @@
 /*
-*****************************************************************************************
-**        O.S   : FreeBSD
+********************************************************************************
+**        OS    : FreeBSD
 **   FILE NAME  : arcmsr.c
 **        BY    : Erich Chen, Ching Huang
 **   Description: SCSI RAID Device Driver for
-**                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) SATA/SAS RAID HOST Adapter
-**                ARCMSR RAID Host adapter
-**                [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set]
-******************************************************************************************
-************************************************************************
+**                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
+**                SATA/SAS RAID HOST Adapter
+********************************************************************************
+********************************************************************************
 **
-** Copyright (c) 2004-2010 ARECA Co. Ltd.
-**        Erich Chen, Taipei Taiwan All rights reserved.
+** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
 **
 ** Redistribution and use in source and binary forms, with or without
 ** modification, are permitted provided that the following conditions
@@ -34,46 +32,50 @@
 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**************************************************************************
+********************************************************************************
 ** History
 **
-**        REV#         DATE             NAME             DESCRIPTION
-**     1.00.00.00   03/31/2004      Erich Chen           First release
-**     1.20.00.02   11/29/2004      Erich Chen           bug fix with arcmsr_bus_reset when PHY error
-**     1.20.00.03   04/19/2005      Erich Chen           add SATA 24 Ports adapter type support
-**                                                       clean unused function
-**     1.20.00.12   09/12/2005      Erich Chen           bug fix with abort command handling,
-**                                                       firmware version check
-**                                                       and firmware update notify for hardware bug fix
-**                                                       handling if none zero high part physical address
-**                                                       of srb resource
-**     1.20.00.13   08/18/2006      Erich Chen           remove pending srb and report busy
-**                                                       add iop message xfer
-**                                                       with scsi pass-through command
-**                                                       add new device id of sas raid adapters
-**                                                       code fit for SPARC64 & PPC
-**     1.20.00.14   02/05/2007      Erich Chen           bug fix for incorrect ccb_h.status report
-**                                                       and cause g_vfs_done() read write error
-**     1.20.00.15   10/10/2007      Erich Chen           support new RAID adapter type ARC120x
-**     1.20.00.16   10/10/2009      Erich Chen           Bug fix for RAID adapter type ARC120x
-**                                                       bus_dmamem_alloc() with BUS_DMA_ZERO
-**     1.20.00.17   07/15/2010      Ching Huang          Added support ARC1880
-**                                                       report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
-**                                                       prevent cam_periph_error removing all LUN devices of one Target id
-**                                                       for any one LUN device failed
-**     1.20.00.18   10/14/2010      Ching Huang          Fixed "inquiry data fails comparion at DV1 step"
-**                  10/25/2010      Ching Huang          Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
-**     1.20.00.19   11/11/2010      Ching Huang          Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
-**     1.20.00.20   12/08/2010      Ching Huang          Avoid calling atomic_set_int function
-**     1.20.00.21   02/08/2011      Ching Huang          Implement I/O request timeout
-**                  02/14/2011      Ching Huang          Modified pktRequestCount
-**     1.20.00.21   03/03/2011      Ching Huang          if a command timeout, then wait its ccb back before free it
-**     1.20.00.22   07/04/2011      Ching Huang          Fixed multiple MTX panic
-**     1.20.00.23   10/28/2011      Ching Huang          Added TIMEOUT_DELAY in case of too many HDDs need to start
-**     1.20.00.23   11/08/2011      Ching Huang          Added report device transfer speed
-**     1.20.00.23   01/30/2012      Ching Huang          Fixed Request requeued and Retrying command
-**     1.20.00.24   06/11/2012      Ching Huang          Fixed return sense data condition
-**     1.20.00.25   08/17/2012      Ching Huang          Fixed hotplug device no function on type A adapter
+**    REV#         DATE         NAME        DESCRIPTION
+** 1.00.00.00   03/31/2004  Erich Chen      First release
+** 1.20.00.02   11/29/2004  Erich Chen      bug fix with arcmsr_bus_reset when PHY error
+** 1.20.00.03   04/19/2005  Erich Chen      add SATA 24 Ports adapter type support
+**                                          clean unused function
+** 1.20.00.12   09/12/2005  Erich Chen      bug fix with abort command handling, 
+**                                          firmware version check 
+**                                          and firmware update notify for hardware bug fix
+**                                          handling if none zero high part physical address 
+**                                          of srb resource 
+** 1.20.00.13   08/18/2006  Erich Chen      remove pending srb and report busy
+**                                          add iop message xfer 
+**                                          with scsi pass-through command
+**                                          add new device id of sas raid adapters 
+**                                          code fit for SPARC64 & PPC 
+** 1.20.00.14   02/05/2007  Erich Chen      bug fix for incorrect ccb_h.status report
+**                                          and cause g_vfs_done() read write error
+** 1.20.00.15   10/10/2007  Erich Chen      support new RAID adapter type ARC120x
+** 1.20.00.16   10/10/2009  Erich Chen      Bug fix for RAID adapter type ARC120x
+**                                          bus_dmamem_alloc() with BUS_DMA_ZERO
+** 1.20.00.17   07/15/2010  Ching Huang     Added support ARC1880
+**                                          report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
+**                                          prevent cam_periph_error removing all LUN devices of one Target id
+**                                          for any one LUN device failed
+** 1.20.00.18   10/14/2010  Ching Huang     Fixed "inquiry data fails comparion at DV1 step"
+**              10/25/2010  Ching Huang     Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
+** 1.20.00.19   11/11/2010  Ching Huang     Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
+** 1.20.00.20   12/08/2010  Ching Huang     Avoid calling atomic_set_int function
+** 1.20.00.21   02/08/2011  Ching Huang     Implement I/O request timeout
+**              02/14/2011  Ching Huang     Modified pktRequestCount
+** 1.20.00.21   03/03/2011  Ching Huang     if a command timeout, then wait its ccb back before free it
+** 1.20.00.22   07/04/2011  Ching Huang     Fixed multiple MTX panic
+** 1.20.00.23   10/28/2011  Ching Huang     Added TIMEOUT_DELAY in case of too many HDDs need to start 
+** 1.20.00.23   11/08/2011  Ching Huang     Added report device transfer speed 
+** 1.20.00.23   01/30/2012  Ching Huang     Fixed Request requeued and Retrying command
+** 1.20.00.24   06/11/2012  Ching Huang     Fixed return sense data condition
+** 1.20.00.25   08/17/2012  Ching Huang     Fixed hotplug device no function on type A adapter
+** 1.20.00.26   12/14/2012  Ching Huang     Added support ARC1214,1224,1264,1284
+** 1.20.00.27   05/06/2013  Ching Huang     Fixed out standing cmd full on ARC-12x4
+** 1.20.00.28   09/13/2013  Ching Huang     Removed recursive mutex in arcmsr_abort_dr_ccbs
+** 1.20.00.29   12/18/2013  Ching Huang     Change simq allocation number, support ARC1883
 ******************************************************************************************
 * $FreeBSD: src/sys/dev/arcmsr/arcmsr.c,v 1.43 2012/09/04 05:15:54 delphij Exp $
 */
@@ -119,33 +121,18 @@
 #include <sys/endian.h>
 #include <bus/pci/pcivar.h>
 #include <bus/pci/pcireg.h>
-#define ARCMSR_LOCK_INIT(l, s)	lockinit(l, s, 0, LK_CANRECURSE)
-#define ARCMSR_LOCK_DESTROY(l)	lockuninit(l)
-#define ARCMSR_LOCK_ACQUIRE(l)	lockmgr(l, LK_EXCLUSIVE)
-#define ARCMSR_LOCK_RELEASE(l)	lockmgr(l, LK_RELEASE)
-#define ARCMSR_LOCK_TRY(l)	lockmgr(&l, LK_EXCLUSIVE|LK_NOWAIT);
-#define arcmsr_htole32(x)	htole32(x)
-typedef struct lock		arcmsr_lock_t;
 
 #define arcmsr_callout_init(a)	callout_init_mp(a);
 
-#define ARCMSR_DRIVER_VERSION			"Driver Version 1.20.00.25 2012-08-17"
+#define ARCMSR_DRIVER_VERSION	"arcmsr version 1.20.00.29 2013-12-18"
 #include <dev/raid/arcmsr/arcmsr.h>
-#define	SRB_SIZE						((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
-#define ARCMSR_SRBS_POOL_SIZE           (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM)
-/*
-**************************************************************************
-**************************************************************************
-*/
-#define CHIP_REG_READ32(s, b, r)	bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r))
-#define CHIP_REG_WRITE32(s, b, r, d)	bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d)
 /*
 **************************************************************************
 **************************************************************************
 */
 static void arcmsr_free_srb(struct CommandControlBlock *srb);
-static struct CommandControlBlock * arcmsr_get_freesrb(struct AdapterControlBlock *acb);
-static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb);
+static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
+static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
 static int arcmsr_probe(device_t dev);
 static int arcmsr_attach(device_t dev);
 static int arcmsr_detach(device_t dev);
@@ -160,18 +147,20 @@ static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
-static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb);
+static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
+static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
-static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t * dm_segs, u_int32_t nseg);
-static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb * pccb);
+static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
+static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
 static int arcmsr_resume(device_t dev);
 static int arcmsr_suspend(device_t dev);
 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
-static void	arcmsr_polling_devmap(void* arg);
-static void	arcmsr_srb_timeout(void* arg);
+static void	arcmsr_polling_devmap(void *arg);
+static void	arcmsr_srb_timeout(void *arg);
+static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
 #ifdef ARCMSR_DEBUG1
 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
 #endif
@@ -201,8 +190,6 @@ static device_method_t arcmsr_methods[]={
 	DEVMETHOD(device_shutdown,	arcmsr_shutdown),
 	DEVMETHOD(device_suspend,	arcmsr_suspend),
 	DEVMETHOD(device_resume,	arcmsr_resume),
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
 	DEVMETHOD_END
 };
 
@@ -239,9 +226,9 @@ static int
 arcmsr_open(struct dev_open_args *ap)
 {
 	cdev_t dev = ap->a_head.a_dev;
-	struct AdapterControlBlock *acb=dev->si_drv1;
+	struct AdapterControlBlock *acb = dev->si_drv1;
 
-	if(acb==NULL) {
+	if(acb == NULL) {
 		return ENXIO;
 	}
 	return (0);
@@ -256,9 +243,9 @@ static int
 arcmsr_close(struct dev_close_args *ap)
 {
 	cdev_t dev = ap->a_head.a_dev;
-	struct AdapterControlBlock *acb=dev->si_drv1;
+	struct AdapterControlBlock *acb = dev->si_drv1;
 
-	if(acb==NULL) {
+	if(acb == NULL) {
 		return ENXIO;
 	}
 	return 0;
@@ -275,9 +262,9 @@ arcmsr_ioctl(struct dev_ioctl_args *ap)
 	cdev_t dev = ap->a_head.a_dev;
 	u_long ioctl_cmd = ap->a_cmd;
 	caddr_t arg = ap->a_data;
-	struct AdapterControlBlock *acb=dev->si_drv1;
+	struct AdapterControlBlock *acb = dev->si_drv1;
 
-	if(acb==NULL) {
+	if(acb == NULL) {
 		return ENXIO;
 	}
 	return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
@@ -289,28 +276,34 @@ arcmsr_ioctl(struct dev_ioctl_args *ap)
 */
 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 {
-	u_int32_t intmask_org=0;
+	u_int32_t intmask_org = 0;
 
 	switch (acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_A: {
 			/* disable all outbound interrupt */
-			intmask_org=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
+			intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 		}
 		break;
 	case ACB_ADAPTER_TYPE_B: {
 			/* disable all outbound interrupt */
-			intmask_org=CHIP_REG_READ32(HBB_DOORBELL,
+			intmask_org = CHIP_REG_READ32(HBB_DOORBELL, 
 			0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */
 		}
 		break;
 	case ACB_ADAPTER_TYPE_C: {
 			/* disable all outbound interrupt */
-			intmask_org=CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)	; /* disable outbound message0 int */
+			intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)	; /* disable outbound message0 int */
 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			/* disable all outbound interrupt */
+			intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)	; /* disable outbound message0 int */
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
+		}
+		break;
 	}
 	return (intmask_org);
 }
@@ -325,23 +318,31 @@ static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t in
 	switch (acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_A: {
 			/* enable outbound Post Queue, outbound doorbell Interrupt */
-			mask=~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
+			mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 			acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 		}
 		break;
 	case ACB_ADAPTER_TYPE_B: {
 			/* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
-			mask=(ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
+			mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 			acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 		}
 		break;
 	case ACB_ADAPTER_TYPE_C: {
 			/* enable outbound Post Queue, outbound doorbell Interrupt */
-			mask=~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
+			mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
-			acb->outbound_int_enable= ~(intmask_org & mask) & 0x0000000f;
+			acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
+		}
+		break;
+	case ACB_ADAPTER_TYPE_D: {
+			/* enable outbound Post Queue, outbound doorbell Interrupt */
+			mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
+			CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
+			acb->outbound_int_enable = mask;
 		}
 		break;
 	}
@@ -353,7 +354,7 @@ static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t in
 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 {
 	u_int32_t Index;
-	u_int8_t Retries=0x00;
+	u_int8_t Retries = 0x00;
 
 	do {
 		for(Index=0; Index < 100; Index++) {
@@ -373,7 +374,7 @@ static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 {
 	u_int32_t Index;
-	u_int8_t Retries=0x00;
+	u_int8_t Retries = 0x00;
 
 	do {
 		for(Index=0; Index < 100; Index++) {
@@ -394,7 +395,7 @@ static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 {
 	u_int32_t Index;
-	u_int8_t Retries=0x00;
+	u_int8_t Retries = 0x00;
 
 	do {
 		for(Index=0; Index < 100; Index++) {
@@ -408,12 +409,32 @@ static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 	return (FALSE);
 }
 /*
+**********************************************************************
+**********************************************************************
+*/
+static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
+{
+	u_int32_t Index;
+	u_int8_t Retries = 0x00;
+	
+	do {
+		for(Index=0; Index < 100; Index++) {
+			if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
+				CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
+				return TRUE;
+			}
+			UDELAY(10000);
+		}/*max 1 seconds*/
+	}while(Retries++ < 20);/*max 20 sec*/
+	return (FALSE);
+}
+/*
 ************************************************************************
 ************************************************************************
 */
 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 {
-	int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */
+	int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 
 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 	do {
@@ -422,7 +443,7 @@ static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 		} else {
 			retry_count--;
 		}
-	}while(retry_count!=0);
+	}while(retry_count != 0);
 }
 /*
 ************************************************************************
@@ -430,7 +451,7 @@ static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 */
 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 {
-	int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */
+	int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 
 	CHIP_REG_WRITE32(HBB_DOORBELL,
 	0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
@@ -440,7 +461,7 @@ static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 		} else {
 			retry_count--;
 		}
-	}while(retry_count!=0);
+	}while(retry_count != 0);
 }
 /*
 ************************************************************************
@@ -448,7 +469,7 @@ static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 */
 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 {
-	int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */
+	int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 
 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
@@ -458,7 +479,24 @@ static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 		} else {
 			retry_count--;
 		}
-	}while(retry_count!=0);
+	}while(retry_count != 0);
+}
+/*
+************************************************************************
+************************************************************************
+*/
+static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
+{
+	int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
+	
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
+	do {
+		if(arcmsr_hbd_wait_msgint_ready(acb)) {
+			break;
+		} else {
+			retry_count--;
+		}
+	}while(retry_count != 0);
 }
 /*
 ************************************************************************
@@ -479,6 +517,10 @@ static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 			arcmsr_flush_hbc_cache(acb);
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			arcmsr_flush_hbd_cache(acb);
+		}
+		break;
 	}
 }
 /*
@@ -512,44 +554,24 @@ static int arcmsr_resume(device_t dev)
 */
 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 {
-}
-/*
-**********************************************************************
-**********************************************************************
-*/
-static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
-{
-	struct AdapterControlBlock *acb=srb->acb;
-	union ccb * pccb=srb->pccb;
-
-	if(srb->srb_flags & SRB_FLAG_TIMER_START)
-		callout_stop(&srb->ccb_callout);
-	if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
-		bus_dmasync_op_t op;
-
-		if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
-			op = BUS_DMASYNC_POSTREAD;
-		} else {
-			op = BUS_DMASYNC_POSTWRITE;
-		}
-		bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
-		bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
-	}
-	if(stand_flag==1) {
-		atomic_subtract_int(&acb->srboutstandingcount, 1);
-		if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
-		acb->srboutstandingcount < ARCMSR_RELEASE_SIMQ_LEVEL)) {
-			acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
-			pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
+	struct AdapterControlBlock *acb;
+	u_int8_t target_id, target_lun;
+	struct cam_sim *sim;
+	
+	sim = (struct cam_sim *) cb_arg;
+	acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
+	switch (code) {
+	case AC_LOST_DEVICE:
+		target_id = xpt_path_target_id(path);
+		target_lun = xpt_path_lun_id(path);
+		if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
+			break;
 		}
+	//	printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
+		break;
+	default:
+		break;
 	}
-	if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
-		arcmsr_free_srb(srb);
-#ifdef ARCMSR_DEBUG1
-	acb->pktReturnCount++;
-#endif
-	xpt_done(pccb);
-	return;
 }
 /*
 **********************************************************************
@@ -557,7 +579,7 @@ static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 */
 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 {
-	union ccb * pccb=srb->pccb;
+	union ccb *pccb = srb->pccb;
 
 	pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 	pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
@@ -607,6 +629,17 @@ static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 *********************************************************************
 *********************************************************************
 */
+static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
+{
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
+	if(!arcmsr_hbd_wait_msgint_ready(acb)) {
+		kprintf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
+	}
+}
+/*
+*********************************************************************
+*********************************************************************
+*/
 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 {
 	switch (acb->adapter_type) {
@@ -622,7 +655,46 @@ static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 			arcmsr_abort_hbc_allcmd(acb);
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			arcmsr_abort_hbd_allcmd(acb);
+		}
+		break;
+	}
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
+static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
+{
+	struct AdapterControlBlock *acb = srb->acb;
+	union ccb *pccb = srb->pccb;
+
+	if(srb->srb_flags & SRB_FLAG_TIMER_START)
+		callout_stop(&srb->ccb_callout);
+	if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
+		bus_dmasync_op_t op;
+
+		if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
+			op = BUS_DMASYNC_POSTREAD;
+		} else {
+			op = BUS_DMASYNC_POSTWRITE;
+		}
+		bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
+		bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 	}
+	if(stand_flag == 1) {
+		atomic_subtract_int(&acb->srboutstandingcount, 1);
+		if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
+		acb->srboutstandingcount < (acb->maxOutstanding -10))) {
+			acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
+			pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
+		}
+	}
+	if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
+		arcmsr_free_srb(srb);
+	acb->pktReturnCount++;
+	xpt_done(pccb);
 }
 /*
 **************************************************************************
@@ -632,42 +704,42 @@ static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct Comm
 {
 	int target, lun;
 
-	target=srb->pccb->ccb_h.target_id;
-	lun=srb->pccb->ccb_h.target_lun;
+	target = srb->pccb->ccb_h.target_id;
+	lun = srb->pccb->ccb_h.target_lun;
 	if(error == FALSE) {
-		if(acb->devstate[target][lun]==ARECA_RAID_GONE) {
-			acb->devstate[target][lun]=ARECA_RAID_GOOD;
+		if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
+			acb->devstate[target][lun] = ARECA_RAID_GOOD;
 		}
 		srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 		arcmsr_srb_complete(srb, 1);
 	} else {
 		switch(srb->arcmsr_cdb.DeviceStatus) {
 		case ARCMSR_DEV_SELECT_TIMEOUT: {
-				if(acb->devstate[target][lun]==ARECA_RAID_GOOD) {
+				if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
 					kprintf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 				}
-				acb->devstate[target][lun]=ARECA_RAID_GONE;
+				acb->devstate[target][lun] = ARECA_RAID_GONE;
 				srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 				arcmsr_srb_complete(srb, 1);
 			}
 			break;
 		case ARCMSR_DEV_ABORTED:
 		case ARCMSR_DEV_INIT_FAIL: {
-				acb->devstate[target][lun]=ARECA_RAID_GONE;
+				acb->devstate[target][lun] = ARECA_RAID_GONE;
 				srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 				arcmsr_srb_complete(srb, 1);
 			}
 			break;
 		case SCSISTAT_CHECK_CONDITION: {
-				acb->devstate[target][lun]=ARECA_RAID_GOOD;
+				acb->devstate[target][lun] = ARECA_RAID_GOOD;
 				arcmsr_report_sense_info(srb);
 				arcmsr_srb_complete(srb, 1);
 			}
 			break;
 		default:
-			kprintf("arcmsr%d: scsi id=%d lun=%d isr got command error done, but got unknown DeviceStatus=0x%x\n"
+			kprintf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
 					, acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
-			acb->devstate[target][lun]=ARECA_RAID_GONE;
+			acb->devstate[target][lun] = ARECA_RAID_GONE;
 			srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 			/*unknown error or crc error just for retry*/
 			arcmsr_srb_complete(srb, 1);
@@ -686,7 +758,8 @@ static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t fl
 	/* check if command done with no error*/
 	switch (acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_C:
-		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
+	case ACB_ADAPTER_TYPE_D:
+		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
 		break;
 	case ACB_ADAPTER_TYPE_A:
 	case ACB_ADAPTER_TYPE_B:
@@ -694,7 +767,7 @@ static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t fl
 		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 		break;
 	}
-	if((srb->acb!=acb) || (srb->srb_state!=ARCMSR_SRB_START)) {
+	if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
 		if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
 			arcmsr_free_srb(srb);
 			kprintf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
@@ -711,17 +784,17 @@ static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t fl
 **************************************************************************
 **************************************************************************
 */
-static void	arcmsr_srb_timeout(void* arg)
+static void	arcmsr_srb_timeout(void *arg)
 {
 	struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
 	struct AdapterControlBlock *acb;
 	int target, lun;
 	u_int8_t cmd;
 
-	target=srb->pccb->ccb_h.target_id;
-	lun=srb->pccb->ccb_h.target_lun;
+	target = srb->pccb->ccb_h.target_id;
+	lun = srb->pccb->ccb_h.target_lun;
 	acb = srb->acb;
-	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 	if(srb->srb_state == ARCMSR_SRB_START)
 	{
 		cmd = srb->pccb->csio.cdb_io.cdb_bytes[0];
@@ -731,7 +804,7 @@ static void	arcmsr_srb_timeout(void* arg)
 		kprintf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
 				 acb->pci_unit, target, lun, cmd, srb);
 	}
-	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 #ifdef ARCMSR_DEBUG1
 	arcmsr_dump_data(acb);
 #endif
@@ -752,10 +825,10 @@ static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 			u_int32_t outbound_intstatus;
 
 			/*clear and abort all outbound posted Q*/
-			outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
+			outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 			while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
-                error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+                error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 				arcmsr_drain_donequeue(acb, flag_srb, error);
 			}
 		}
@@ -766,26 +839,30 @@ static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 			/*clear all outbound posted Q*/
 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 			for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
-				if((flag_srb=phbbmu->done_qbuffer[i])!=0) {
-					phbbmu->done_qbuffer[i]=0;
-			error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+				if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
+					phbbmu->done_qbuffer[i] = 0;
+                	error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 					arcmsr_drain_donequeue(acb, flag_srb, error);
 				}
-				phbbmu->post_qbuffer[i]=0;
+				phbbmu->post_qbuffer[i] = 0;
 			}/*drain reply FIFO*/
-			phbbmu->doneq_index=0;
-			phbbmu->postq_index=0;
+			phbbmu->doneq_index = 0;
+			phbbmu->postq_index = 0;
 		}
 		break;
 	case ACB_ADAPTER_TYPE_C: {
 
 			while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
-				flag_srb=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
-                error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
+				flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
+                error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
 				arcmsr_drain_donequeue(acb, flag_srb, error);
 			}
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			arcmsr_hbd_postqueue_isr(acb);
+		}
+		break;
 	}
 }
 /*
@@ -800,32 +877,30 @@ static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 
 	if(acb->srboutstandingcount>0) {
 		/* disable all outbound interrupt */
-		intmask_org=arcmsr_disable_allintr(acb);
+		intmask_org = arcmsr_disable_allintr(acb);
 		/*clear and abort all outbound posted Q*/
 		arcmsr_done4abort_postqueue(acb);
 		/* talk to iop 331 outstanding command aborted*/
 		arcmsr_abort_allcmd(acb);
-		for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) {
-			srb=acb->psrb_pool[i];
-			if(srb->srb_state==ARCMSR_SRB_START) {
-				srb->srb_state=ARCMSR_SRB_ABORTED;
+		for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
+			srb = acb->psrb_pool[i];
+			if(srb->srb_state == ARCMSR_SRB_START) {
+				srb->srb_state = ARCMSR_SRB_ABORTED;
 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 				arcmsr_srb_complete(srb, 1);
-				kprintf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n"
+				kprintf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n"
 						, acb->pci_unit, srb->pccb->ccb_h.target_id
-						, srb->pccb->ccb_h.target_lun, srb);
+						, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
 			}
 		}
 		/* enable all outbound interrupt */
 		arcmsr_enable_allintr(acb, intmask_org);
 	}
-	acb->srboutstandingcount=0;
-	acb->workingsrb_doneindex=0;
-	acb->workingsrb_startindex=0;
-#ifdef ARCMSR_DEBUG1
+	acb->srboutstandingcount = 0;
+	acb->workingsrb_doneindex = 0;
+	acb->workingsrb_startindex = 0;
 	acb->pktRequestCount = 0;
 	acb->pktReturnCount = 0;
-#endif
 }
 /*
 **********************************************************************
@@ -834,67 +909,66 @@ static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 static void arcmsr_build_srb(struct CommandControlBlock *srb,
 		bus_dma_segment_t *dm_segs, u_int32_t nseg)
 {
-	struct ARCMSR_CDB * arcmsr_cdb= &srb->arcmsr_cdb;
-	u_int8_t * psge=(u_int8_t *)&arcmsr_cdb->u;
+	struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
+	u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
 	u_int32_t address_lo, address_hi;
-	union ccb * pccb=srb->pccb;
-	struct ccb_scsiio * pcsio= &pccb->csio;
-	u_int32_t arccdbsize=0x30;
+	union ccb *pccb = srb->pccb;
+	struct ccb_scsiio *pcsio = &pccb->csio;
+	u_int32_t arccdbsize = 0x30;
 
 	memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
-	arcmsr_cdb->Bus=0;
-	arcmsr_cdb->TargetID=pccb->ccb_h.target_id;
-	arcmsr_cdb->LUN=pccb->ccb_h.target_lun;
-	arcmsr_cdb->Function=1;
-	arcmsr_cdb->CdbLength=(u_int8_t)pcsio->cdb_len;
-	arcmsr_cdb->Context=0;
+	arcmsr_cdb->Bus = 0;
+	arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
+	arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
+	arcmsr_cdb->Function = 1;
+	arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
 	bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len);
 	if(nseg != 0) {
-		struct AdapterControlBlock *acb=srb->acb;
+		struct AdapterControlBlock *acb = srb->acb;
 		bus_dmasync_op_t op;
-		u_int32_t length, i, cdb_sgcount=0;
+		u_int32_t length, i, cdb_sgcount = 0;
 
 		if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
-			op=BUS_DMASYNC_PREREAD;
+			op = BUS_DMASYNC_PREREAD;
 		} else {
-			op=BUS_DMASYNC_PREWRITE;
-			arcmsr_cdb->Flags|=ARCMSR_CDB_FLAG_WRITE;
-			srb->srb_flags|=SRB_FLAG_WRITE;
+			op = BUS_DMASYNC_PREWRITE;
+			arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
+			srb->srb_flags |= SRB_FLAG_WRITE;
 		}
 		bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
-		for(i=0;i<nseg;i++) {
+		for(i=0; i < nseg; i++) {
 			/* Get the physical address of the current data pointer */
-			length=arcmsr_htole32(dm_segs[i].ds_len);
-			address_lo=arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
-			address_hi=arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
-			if(address_hi==0) {
-				struct SG32ENTRY * pdma_sg=(struct SG32ENTRY *)psge;
-				pdma_sg->address=address_lo;
-				pdma_sg->length=length;
+			length = arcmsr_htole32(dm_segs[i].ds_len);
+			address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
+			address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
+			if(address_hi == 0) {
+				struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
+				pdma_sg->address = address_lo;
+				pdma_sg->length = length;
 				psge += sizeof(struct SG32ENTRY);
 				arccdbsize += sizeof(struct SG32ENTRY);
 			} else {
-				u_int32_t sg64s_size=0, tmplength=length;
+				u_int32_t sg64s_size = 0, tmplength = length;
 
 				while(1) {
 					u_int64_t span4G, length0;
-					struct SG64ENTRY * pdma_sg=(struct SG64ENTRY *)psge;
+					struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
 
-					span4G=(u_int64_t)address_lo + tmplength;
-					pdma_sg->addresshigh=address_hi;
-					pdma_sg->address=address_lo;
+					span4G = (u_int64_t)address_lo + tmplength;
+					pdma_sg->addresshigh = address_hi;
+					pdma_sg->address = address_lo;
 					if(span4G > 0x100000000) {
 						/*see if cross 4G boundary*/
-						length0=0x100000000-address_lo;
-						pdma_sg->length=(u_int32_t)length0|IS_SG64_ADDR;
-						address_hi=address_hi+1;
-						address_lo=0;
-						tmplength=tmplength-(u_int32_t)length0;
+						length0 = 0x100000000-address_lo;
+						pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
+						address_hi = address_hi+1;
+						address_lo = 0;
+						tmplength = tmplength - (u_int32_t)length0;
 						sg64s_size += sizeof(struct SG64ENTRY);
 						psge += sizeof(struct SG64ENTRY);
 						cdb_sgcount++;
 					} else {
-						pdma_sg->length=tmplength|IS_SG64_ADDR;
+						pdma_sg->length = tmplength | IS_SG64_ADDR;
 						sg64s_size += sizeof(struct SG64ENTRY);
 						psge += sizeof(struct SG64ENTRY);
 						break;
@@ -904,15 +978,16 @@ static void arcmsr_build_srb(struct CommandControlBlock *srb,
 			}
 			cdb_sgcount++;
 		}
-		arcmsr_cdb->sgcount=(u_int8_t)cdb_sgcount;
-		arcmsr_cdb->DataLength=pcsio->dxfer_len;
+		arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
+		arcmsr_cdb->DataLength = pcsio->dxfer_len;
 		if( arccdbsize > 256) {
-			arcmsr_cdb->Flags|=ARCMSR_CDB_FLAG_SGL_BSIZE;
+			arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
 		}
 	} else {
 		arcmsr_cdb->DataLength = 0;
 	}
-	srb->arc_cdb_size=arccdbsize;
+    srb->arc_cdb_size = arccdbsize;
+    arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
 }
 /*
 **************************************************************************
@@ -920,46 +995,45 @@ static void arcmsr_build_srb(struct CommandControlBlock *srb,
 */
 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
 {
-	u_int32_t cdb_shifted_phyaddr=(u_int32_t) srb->cdb_shifted_phyaddr;
-	struct ARCMSR_CDB * arcmsr_cdb=(struct ARCMSR_CDB *)&srb->arcmsr_cdb;
+	u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
+	struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
 
 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
 	atomic_add_int(&acb->srboutstandingcount, 1);
-	srb->srb_state=ARCMSR_SRB_START;
+	srb->srb_state = ARCMSR_SRB_START;
 
 	switch (acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_A: {
 			if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
-				CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_shifted_phyaddr|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
+				CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
 			} else {
-				CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_shifted_phyaddr);
+				CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
 			}
 		}
 		break;
 	case ACB_ADAPTER_TYPE_B: {
-			struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
+			struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 			int ending_index, index;
 
-			index=phbbmu->postq_index;
-			ending_index=((index+1)%ARCMSR_MAX_HBB_POSTQUEUE);
-			phbbmu->post_qbuffer[ending_index]=0;
+			index = phbbmu->postq_index;
+			ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
+			phbbmu->post_qbuffer[ending_index] = 0;
 			if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
-				phbbmu->post_qbuffer[index]= cdb_shifted_phyaddr|ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
+				phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
 			} else {
-				phbbmu->post_qbuffer[index]= cdb_shifted_phyaddr;
+				phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
 			}
 			index++;
 			index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
-			phbbmu->postq_index=index;
+			phbbmu->postq_index = index;
 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
 		}
 		break;
-    case ACB_ADAPTER_TYPE_C:
-        {
+    case ACB_ADAPTER_TYPE_C: {
             u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
 
-            arc_cdb_size=(srb->arc_cdb_size>0x300)?0x300:srb->arc_cdb_size;
-            ccb_post_stamp=(cdb_shifted_phyaddr | ((arc_cdb_size-1) >> 6) | 1);
+            arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
+            ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
 			cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
             if(cdb_phyaddr_hi32)
             {
@@ -972,33 +1046,67 @@ static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandContr
             }
         }
         break;
+	case ACB_ADAPTER_TYPE_D: {
+			struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
+			u_int16_t index_stripped;
+			u_int16_t postq_index;
+			struct InBound_SRB *pinbound_srb;
+
+			ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
+			postq_index = phbdmu->postq_index;
+			pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
+			pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
+			pinbound_srb->addressLow = srb->cdb_phyaddr_low;
+			pinbound_srb->length = srb->arc_cdb_size >> 2;
+			arcmsr_cdb->Context = srb->cdb_phyaddr_low;
+			if (postq_index & 0x4000) {
+				index_stripped = postq_index & 0xFF;
+				index_stripped += 1;
+				index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
+				phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
+			} else {
+				index_stripped = postq_index;
+				index_stripped += 1;
+				index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
+				phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
+			}
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
+			ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
+		}
+		break;
 	}
 }
 /*
 ************************************************************************
 ************************************************************************
 */
-static struct QBUFFER * arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
+static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
 {
 	struct QBUFFER *qbuffer=NULL;
 
 	switch (acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_A: {
-			struct HBA_MessageUnit *phbamu=(struct HBA_MessageUnit *)acb->pmu;
+			struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
 
-			qbuffer=(struct QBUFFER *)&phbamu->message_rbuffer;
+			qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
 		}
 		break;
 	case ACB_ADAPTER_TYPE_B: {
-			struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
+			struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 
-			qbuffer=(struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
+			qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
 		}
 		break;
 	case ACB_ADAPTER_TYPE_C: {
-			struct HBC_MessageUnit *phbcmu=(struct HBC_MessageUnit *)acb->pmu;
+			struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
 
-			qbuffer=(struct QBUFFER *)&phbcmu->message_rbuffer;
+			qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
+		}
+		break;
+	case ACB_ADAPTER_TYPE_D: {
+			struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
+	
+			qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
 		}
 		break;
 	}
@@ -1008,27 +1116,33 @@ static struct QBUFFER * arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb
 ************************************************************************
 ************************************************************************
 */
-static struct QBUFFER * arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
+static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
 {
-	struct QBUFFER *qbuffer=NULL;
+	struct QBUFFER *qbuffer = NULL;
 
 	switch (acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_A: {
-			struct HBA_MessageUnit *phbamu=(struct HBA_MessageUnit *)acb->pmu;
+			struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
 
-			qbuffer=(struct QBUFFER *)&phbamu->message_wbuffer;
+			qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
 		}
 		break;
 	case ACB_ADAPTER_TYPE_B: {
-			struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
+			struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 
-			qbuffer=(struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
+			qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
 		}
 		break;
 	case ACB_ADAPTER_TYPE_C: {
-			struct HBC_MessageUnit *phbcmu=(struct HBC_MessageUnit *)acb->pmu;
+			struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
 
-			qbuffer=(struct QBUFFER *)&phbcmu->message_wbuffer;
+			qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
+		}
+		break;
+	case ACB_ADAPTER_TYPE_D: {
+			struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
+	
+			qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
 		}
 		break;
 	}
@@ -1055,6 +1169,12 @@ static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
 			/* let IOP know data has been read */
 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
 		}
+		break;
+	case ACB_ADAPTER_TYPE_D: {
+			/* let IOP know data has been read */
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
+		}
+		break;
 	}
 }
 /*
@@ -1088,37 +1208,14 @@ static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
 		}
 		break;
-	}
-}
-/*
-**********************************************************************
-**********************************************************************
-*/
-static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
-{
-	u_int8_t *pQbuffer;
-	struct QBUFFER *pwbuffer;
-	u_int8_t * iop_data;
-	int32_t allxfer_len=0;
-
-	pwbuffer=arcmsr_get_iop_wqbuffer(acb);
-	iop_data=(u_int8_t *)pwbuffer->data;
-	if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
-		acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
-		while((acb->wqbuf_firstindex!=acb->wqbuf_lastindex)
-			&& (allxfer_len<124)) {
-			pQbuffer=&acb->wqbuffer[acb->wqbuf_firstindex];
-			memcpy(iop_data, pQbuffer, 1);
-			acb->wqbuf_firstindex++;
-			acb->wqbuf_firstindex %=ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */
-			iop_data++;
-			allxfer_len++;
+	case ACB_ADAPTER_TYPE_D: {
+			/*
+			** push inbound doorbell tell iop, driver data write ok 
+			** and wait reply on next hwinterrupt for next Qbuffer post
+			*/
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
 		}
-		pwbuffer->data_len=allxfer_len;
-		/*
-		** push inbound doorbell and wait reply at hwinterrupt routine for next Qbuffer post
-		*/
-		arcmsr_iop_message_wrote(acb);
+		break;
 	}
 }
 /*
@@ -1127,14 +1224,13 @@ static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
 */
 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
 {
-	acb->acb_flags &=~ACB_F_MSG_START_BGRB;
+	acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
 	CHIP_REG_WRITE32(HBA_MessageUnit,
 	0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
 	if(!arcmsr_hba_wait_msgint_ready(acb)) {
 		kprintf("arcmsr%d: wait 'stop adapter background rebuild' timeout \n"
 			, acb->pci_unit);
 	}
-	return;
 }
 /*
 ************************************************************************
@@ -1156,7 +1252,7 @@ static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
 */
 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
 {
-	acb->acb_flags &=~ACB_F_MSG_START_BGRB;
+	acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 	if(!arcmsr_hbc_wait_msgint_ready(acb)) {
@@ -1167,6 +1263,18 @@ static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
 ************************************************************************
 ************************************************************************
 */
+static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
+{
+	acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
+	if(!arcmsr_hbd_wait_msgint_ready(acb)) {
+		kprintf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
+	}
+}
+/*
+************************************************************************
+************************************************************************
+*/
 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
 {
 	switch (acb->adapter_type) {
@@ -1182,24 +1290,102 @@ static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
 			arcmsr_stop_hbc_bgrb(acb);
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			arcmsr_stop_hbd_bgrb(acb);
+		}
+		break;
 	}
 }
 /*
 ************************************************************************
 ************************************************************************
 */
-static void arcmsr_poll(struct cam_sim * psim)
+static void arcmsr_poll(struct cam_sim *psim)
 {
 	struct AdapterControlBlock *acb;
 	int	mutex;
 
 	acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
-	mutex = lockstatus(&acb->qbuffer_lock, curthread);
+	mutex = lockstatus(&acb->isr_lock, curthread);
 	if( mutex == 0 )
-		ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
+		ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 	arcmsr_interrupt(acb);
 	if( mutex == 0 )
-		ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
+		ARCMSR_LOCK_RELEASE(&acb->isr_lock);
+}
+/*
+**************************************************************************
+**************************************************************************
+*/
+static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
+    struct QBUFFER *prbuffer) {
+
+	u_int8_t *pQbuffer;
+	u_int8_t *buf1 = 0;
+	u_int32_t *iop_data, *buf2 = 0;
+	u_int32_t iop_len, data_len;
+
+	iop_data = (u_int32_t *)prbuffer->data;
+	iop_len = (u_int32_t)prbuffer->data_len;
+	if ( iop_len > 0 )
+	{
+		buf1 = kmalloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
+		buf2 = (u_int32_t *)buf1;
+		if( buf1 == NULL)
+			return (0);
+		data_len = iop_len;
+		while(data_len >= 4)
+		{
+			*buf2++ = *iop_data++;
+			data_len -= 4;
+		}
+		if(data_len)
+			*buf2 = *iop_data;
+		buf2 = (u_int32_t *)buf1;
+	}
+	while (iop_len > 0) {
+		pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
+		*pQbuffer = *buf1;
+		acb->rqbuf_lastindex++;
+		/* if last, index number set it to 0 */
+		acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
+		buf1++;
+		iop_len--;
+	}
+	if(buf2)
+		kfree( (u_int8_t *)buf2, M_DEVBUF);
+	/* let IOP know data has been read */
+	arcmsr_iop_message_read(acb);
+	return (1);
+}
+/*
+**************************************************************************
+**************************************************************************
+*/
+static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
+    struct QBUFFER *prbuffer) {
+
+	u_int8_t *pQbuffer;
+	u_int8_t *iop_data;
+	u_int32_t iop_len;
+
+	if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
+		return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
+	}
+	iop_data = (u_int8_t *)prbuffer->data;
+	iop_len = (u_int32_t)prbuffer->data_len;
+	while (iop_len > 0) {
+		pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
+		*pQbuffer = *iop_data;
+		acb->rqbuf_lastindex++;
+		/* if last, index number set it to 0 */
+		acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
+		iop_data++;
+		iop_len--;
+	}
+	/* let IOP know data has been read */
+	arcmsr_iop_message_read(acb);
+	return (1);
 }
 /*
 **************************************************************************
@@ -1208,31 +1394,95 @@ static void arcmsr_poll(struct cam_sim * psim)
 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
 {
 	struct QBUFFER *prbuffer;
+	int my_empty_len;
+	
+	/*check this iop data if overflow my rqbuffer*/
+	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
+	prbuffer = arcmsr_get_iop_rqbuffer(acb);
+	my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
+	    (ARCMSR_MAX_QBUFFER-1);
+	if(my_empty_len >= prbuffer->data_len) {
+		if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
+			acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
+	} else {
+		acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
+	}
+	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
+static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
+{
 	u_int8_t *pQbuffer;
+	struct QBUFFER *pwbuffer;
+	u_int8_t *buf1 = 0;
+	u_int32_t *iop_data, *buf2 = 0;
+	u_int32_t allxfer_len = 0, data_len;
+	
+	if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
+		buf1 = kmalloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
+		buf2 = (u_int32_t *)buf1;
+		if( buf1 == NULL)
+			return;
+
+		acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
+		pwbuffer = arcmsr_get_iop_wqbuffer(acb);
+		iop_data = (u_int32_t *)pwbuffer->data;
+		while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 
+			&& (allxfer_len < 124)) {
+			pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
+			*buf1 = *pQbuffer;
+			acb->wqbuf_firstindex++;
+			acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
+			buf1++;
+			allxfer_len++;
+		}
+		pwbuffer->data_len = allxfer_len;
+		data_len = allxfer_len;
+		buf1 = (u_int8_t *)buf2;
+		while(data_len >= 4)
+		{
+			*iop_data++ = *buf2++;
+			data_len -= 4;
+		}
+		if(data_len)
+			*iop_data = *buf2;
+		kfree( buf1, M_DEVBUF);
+		arcmsr_iop_message_wrote(acb);
+	}
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
+static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
+{
+	u_int8_t *pQbuffer;
+	struct QBUFFER *pwbuffer;
 	u_int8_t *iop_data;
-	int my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
+	int32_t allxfer_len=0;
 
-	/*check this iop data if overflow my rqbuffer*/
-	rqbuf_lastindex=acb->rqbuf_lastindex;
-	rqbuf_firstindex=acb->rqbuf_firstindex;
-	prbuffer=arcmsr_get_iop_rqbuffer(acb);
-	iop_data=(u_int8_t *)prbuffer->data;
-	iop_len=prbuffer->data_len;
-	my_empty_len=(rqbuf_firstindex-rqbuf_lastindex-1)&(ARCMSR_MAX_QBUFFER-1);
-	if(my_empty_len>=iop_len) {
-		while(iop_len > 0) {
-			pQbuffer=&acb->rqbuffer[rqbuf_lastindex];
-			memcpy(pQbuffer, iop_data, 1);
-			rqbuf_lastindex++;
-			rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;/*if last index number set it to 0 */
+	if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
+		arcmsr_Write_data_2iop_wqbuffer_D(acb);
+		return;
+	}
+	if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
+		acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
+		pwbuffer = arcmsr_get_iop_wqbuffer(acb);
+		iop_data = (u_int8_t *)pwbuffer->data;
+		while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 
+			&& (allxfer_len < 124)) {
+			pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
+			*iop_data = *pQbuffer;
+			acb->wqbuf_firstindex++;
+			acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
 			iop_data++;
-			iop_len--;
+			allxfer_len++;
 		}
-		acb->rqbuf_lastindex=rqbuf_lastindex;
-		arcmsr_iop_message_read(acb);
-		/*signature, let IOP know data has been read */
-	} else {
-		acb->acb_flags|=ACB_F_IOPDATA_OVERFLOW;
+		pwbuffer->data_len = allxfer_len;
+		arcmsr_iop_message_wrote(acb);
 	}
 }
 /*
@@ -1241,6 +1491,7 @@ static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
 */
 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
 {
+	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
 	acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
 	/*
 	*****************************************************************
@@ -1248,61 +1499,51 @@ static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
 	**   in my post bag, now is the time to send them into Areca's firmware
 	*****************************************************************
 	*/
-	if(acb->wqbuf_firstindex!=acb->wqbuf_lastindex) {
-		u_int8_t *pQbuffer;
-		struct QBUFFER *pwbuffer;
-		u_int8_t *iop_data;
-		int allxfer_len=0;
-
-		acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
-		pwbuffer=arcmsr_get_iop_wqbuffer(acb);
-		iop_data=(u_int8_t *)pwbuffer->data;
-		while((acb->wqbuf_firstindex!=acb->wqbuf_lastindex)
-			&& (allxfer_len<124)) {
-			pQbuffer=&acb->wqbuffer[acb->wqbuf_firstindex];
-			memcpy(iop_data, pQbuffer, 1);
-			acb->wqbuf_firstindex++;
-			acb->wqbuf_firstindex %=ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */
-			iop_data++;
-			allxfer_len++;
-		}
-		pwbuffer->data_len=allxfer_len;
-		/*
-		** push inbound doorbell tell iop driver data write ok
-		** and wait reply on next hwinterrupt for next Qbuffer post
-		*/
-		arcmsr_iop_message_wrote(acb);
+	if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
+		arcmsr_Write_data_2iop_wqbuffer(acb);
 	}
-	if(acb->wqbuf_firstindex==acb->wqbuf_lastindex) {
+	if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
 		acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
 	}
+	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
 }
-
+/*
+**************************************************************************
+**************************************************************************
+*/
 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
 {
 /*
 	if (ccb->ccb_h.status != CAM_REQ_CMP)
-		kprintf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x, failure status=%x\n",ccb->ccb_h.target_id,ccb->ccb_h.target_lun,ccb->ccb_h.status);
+		kprintf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
+		    "failure status=%x\n", ccb->ccb_h.target_id,
+		    ccb->ccb_h.target_lun, ccb->ccb_h.status);
 	else
 		kprintf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
 */
 	xpt_free_path(ccb->ccb_h.path);
+	xpt_free_ccb(ccb);
 }
 
 static void	arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
 {
 	struct cam_path     *path;
-	union ccb            ccb;
+	union ccb           *ccb;
 
-	if (xpt_create_path(&path, xpt_periph, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
+	if ((ccb = (union ccb *)xpt_alloc_ccb()) == NULL)
+ 		return;
+	if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
+	{
+		xpt_free_ccb(ccb);
 		return;
+	}
 /*	kprintf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
-	bzero(&ccb, sizeof(union ccb));
-	xpt_setup_ccb(&ccb.ccb_h, path, 5);
-	ccb.ccb_h.func_code = XPT_SCAN_LUN;
-	ccb.ccb_h.cbfcnp = arcmsr_rescanLun_cb;
-	ccb.crcn.flags = CAM_FLAG_NONE;
-	xpt_action(&ccb);
+	bzero(ccb, sizeof(union ccb));
+	xpt_setup_ccb(&ccb->ccb_h, path, 5);
+	ccb->ccb_h.func_code = XPT_SCAN_LUN;
+	ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
+	ccb->crcn.flags = CAM_FLAG_NONE;
+	xpt_action(ccb);
 }
 
 
@@ -1312,7 +1553,6 @@ static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, in
 	u_int32_t intmask_org;
 	int i;
 
-	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
 	/* disable all outbound interrupts */
 	intmask_org = arcmsr_disable_allintr(acb);
 	for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
@@ -1331,10 +1571,7 @@ static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, in
 	}
 	/* enable outbound Post Queue, outbound doorbell Interrupt */
 	arcmsr_enable_allintr(acb, intmask_org);
-	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
 }
-
-
 /*
 **************************************************************************
 **************************************************************************
@@ -1348,7 +1585,7 @@ static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
 	switch (acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_A:
 			devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
-			for (target= 0; target < 4; target++)
+			for (target = 0; target < 4; target++) 
 			{
 		deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
 		devicemap += 4;
@@ -1357,7 +1594,7 @@ static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
 
 	case ACB_ADAPTER_TYPE_B:
 			devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
-			for (target= 0; target < 4; target++)
+			for (target = 0; target < 4; target++) 
 			{
 		deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
 		devicemap += 4;
@@ -1366,12 +1603,20 @@ static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
 
 	case ACB_ADAPTER_TYPE_C:
 			devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
-			for (target= 0; target < 4; target++)
+			for (target = 0; target < 4; target++) 
 			{
 		deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
 		devicemap += 4;
 			}
 			break;
+	case ACB_ADAPTER_TYPE_D:
+			devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
+			for (target = 0; target < 4; target++) 
+			{
+            	deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
+            	devicemap += 4;
+			}
+			break;
 	}
 
 		if(acb->acb_flags & ACB_F_BUS_HANG_ON)
@@ -1383,16 +1628,16 @@ static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
 		** copy the new map, note if there are differences with the current map
 		*/
 		pDevMap = (u_int8_t	*)&deviceMapCurrent[0];
-		for (target= 0; target < ARCMSR_MAX_TARGETID - 1; target++)
+		for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 
 		{
 			if (*pDevMap != acb->device_map[target])
 			{
                 u_int8_t difference, bit_check;
 
-                difference= *pDevMap ^ acb->device_map[target];
+                difference = *pDevMap ^ acb->device_map[target];
                 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
                 {
-                    bit_check=(1 << lun);						/*check bit from 0....31*/
+                    bit_check = (1 << lun);						/*check bit from 0....31*/
                     if(difference & bit_check)
                     {
                         if(acb->device_map[target] & bit_check)
@@ -1411,7 +1656,7 @@ static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
                     }
                 }
 /*				kprintf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
-				acb->device_map[target]= *pDevMap;
+				acb->device_map[target] = *pDevMap;
 			}
 			pDevMap++;
 		}
@@ -1457,9 +1702,21 @@ static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
 **************************************************************************
 **************************************************************************
 */
+static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
+	u_int32_t outbound_message;
+
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
+	outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
+	if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
+		arcmsr_dr_handle( acb );
+}
+/*
+**************************************************************************
+**************************************************************************
+*/
 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
 {
-	u_int32_t outbound_doorbell;
+	u_int32_t doorbell_status;
 
 	/*
 	*******************************************************************
@@ -1468,14 +1725,12 @@ static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
 	**  check if there are any mail need to pack from firmware
 	*******************************************************************
 	*/
-	outbound_doorbell=CHIP_REG_READ32(HBA_MessageUnit,
-	0, outbound_doorbell);
-	CHIP_REG_WRITE32(HBA_MessageUnit,
-	0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */
-	if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
+	doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
+	CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
+	if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
 		arcmsr_iop2drv_data_wrote_handle(acb);
 	}
-	if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
+	if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
 		arcmsr_iop2drv_data_read_handle(acb);
 	}
 }
@@ -1485,7 +1740,7 @@ static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
 */
 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
 {
-	u_int32_t outbound_doorbell;
+	u_int32_t doorbell_status;
 
 	/*
 	*******************************************************************
@@ -1494,15 +1749,15 @@ static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
 	**  check if there are any mail need to pack from firmware
 	*******************************************************************
 	*/
-	outbound_doorbell=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
-	CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */
-	if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
+	doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
+	CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */
+	if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
 		arcmsr_iop2drv_data_wrote_handle(acb);
 	}
-	if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
+	if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
 		arcmsr_iop2drv_data_read_handle(acb);
 	}
-	if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
+	if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 		arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
 	}
 }
@@ -1510,6 +1765,39 @@ static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
 **************************************************************************
 **************************************************************************
 */
+static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
+{
+	u_int32_t doorbell_status;
+	
+	/*
+	*******************************************************************
+	**  Maybe here we need to check wrqbuffer_lock is lock or not
+	**  DOORBELL: din! don! 
+	**  check if there are any mail need to pack from firmware
+	*******************************************************************
+	*/
+	doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
+	if(doorbell_status)
+		CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
+	while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
+		if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
+			arcmsr_iop2drv_data_wrote_handle(acb);
+		}
+		if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
+			arcmsr_iop2drv_data_read_handle(acb);
+		}
+		if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
+			arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
+		}
+		doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
+		if(doorbell_status)
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */
+	}
+}
+/*
+**************************************************************************
+**************************************************************************
+*/
 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
 {
 	u_int32_t flag_srb;
@@ -1522,10 +1810,10 @@ static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
 	*/
 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
 		BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
-	while((flag_srb=CHIP_REG_READ32(HBA_MessageUnit,
+	while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 
 		0, outbound_queueport)) != 0xFFFFFFFF) {
 		/* check if command done with no error*/
-        error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+        error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
 		arcmsr_drain_donequeue(acb, flag_srb, error);
 	}	/*drain reply FIFO*/
 }
@@ -1535,7 +1823,7 @@ static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
 */
 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
 {
-	struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
+	struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 	u_int32_t flag_srb;
 	int index;
 	u_int16_t error;
@@ -1547,14 +1835,14 @@ static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
 	*/
 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
 		BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
-	index=phbbmu->doneq_index;
-	while((flag_srb=phbbmu->done_qbuffer[index]) != 0) {
-		phbbmu->done_qbuffer[index]=0;
+	index = phbbmu->doneq_index;
+	while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
+		phbbmu->done_qbuffer[index] = 0;
 		index++;
 		index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
-		phbbmu->doneq_index=index;
+		phbbmu->doneq_index = index;
 		/* check if command done with no error*/
-        error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+        error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 		arcmsr_drain_donequeue(acb, flag_srb, error);
 	}	/*drain reply FIFO*/
 }
@@ -1564,7 +1852,7 @@ static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
 */
 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
 {
-	u_int32_t flag_srb,throttling=0;
+	u_int32_t flag_srb,throttling = 0;
 	u_int16_t error;
 
 	/*
@@ -1573,19 +1861,76 @@ static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
 	*****************************************************************************
 	*/
 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
-
-	while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
-
-		flag_srb=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
+	do {
+		flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 		/* check if command done with no error*/
-        error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
+        	error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
 		arcmsr_drain_donequeue(acb, flag_srb, error);
-        if(throttling==ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
-            CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
-            break;
-        }
-        throttling++;
-	}	/*drain reply FIFO*/
+        	throttling++;
+		if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
+			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
+			throttling = 0;
+        	}
+	} while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
+}
+/*
+**********************************************************************
+** 
+**********************************************************************
+*/
+static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
+{
+	uint16_t doneq_index, index_stripped;
+
+	doneq_index = phbdmu->doneq_index;
+	if (doneq_index & 0x4000) {
+		index_stripped = doneq_index & 0xFF;
+		index_stripped += 1;
+		index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
+		phbdmu->doneq_index = index_stripped ?
+		    (index_stripped | 0x4000) : index_stripped;
+	} else {
+		index_stripped = doneq_index;
+		index_stripped += 1;
+		index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
+		phbdmu->doneq_index = index_stripped ?
+		    index_stripped : (index_stripped | 0x4000);
+	}
+	return (phbdmu->doneq_index);
+}
+/*
+**************************************************************************
+**************************************************************************
+*/
+static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
+{
+	struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
+	u_int32_t outbound_write_pointer;
+	u_int32_t addressLow;
+	uint16_t doneq_index;
+	u_int16_t error;
+	/*
+	*****************************************************************************
+	**               areca cdb command done
+	*****************************************************************************
+	*/
+	if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
+	    ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
+	    return;
+	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 
+		BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+	outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
+	doneq_index = phbdmu->doneq_index;
+	while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
+		doneq_index = arcmsr_get_doneq_index(phbdmu);
+		addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
+		error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
+		arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
+		CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
+		outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
+	}
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
+	CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
 }
 /*
 **********************************************************************
@@ -1599,12 +1944,12 @@ static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
 	**   check outbound intstatus
 	*********************************************
 	*/
-	outbound_intStatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
+	outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 	if(!outbound_intStatus) {
 		/*it must be share irq*/
 		return;
 	}
-	CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus);/*clear interrupt*/
+	CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
 	/* MU doorbell interrupts*/
 	if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
 		arcmsr_hba_doorbell_isr(acb);
@@ -1629,7 +1974,7 @@ static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
 	**   check outbound intstatus
 	*********************************************
 	*/
-	outbound_doorbell=CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable;
+	outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable;
 	if(!outbound_doorbell) {
 		/*it must be share irq*/
 		return;
@@ -1664,19 +2009,57 @@ static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
 	**   check outbound intstatus
 	*********************************************
 	*/
-	host_interrupt_status=CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
+	host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) &
+		(ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
+		ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
 	if(!host_interrupt_status) {
 		/*it must be share irq*/
 		return;
 	}
+	do {
+		/* MU doorbell interrupts*/
+		if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
+			arcmsr_hbc_doorbell_isr(acb);
+		}
+		/* MU post queue interrupts*/
+		if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
+			arcmsr_hbc_postqueue_isr(acb);
+		}
+		host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
+	} while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
+static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
+{
+	u_int32_t host_interrupt_status;
+	u_int32_t intmask_org;
+	/*
+	*********************************************
+	**   check outbound intstatus 
+	*********************************************
+	*/
+	host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
+	if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
+		/*it must be share irq*/
+		return;
+	}
+	/* disable outbound interrupt */
+	intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)	; /* disable outbound message0 int */
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
 	/* MU doorbell interrupts*/
-	if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
-		arcmsr_hbc_doorbell_isr(acb);
+	if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
+		arcmsr_hbd_doorbell_isr(acb);
 	}
 	/* MU post queue interrupts*/
-	if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
-		arcmsr_hbc_postqueue_isr(acb);
+	if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
+		arcmsr_hbd_postqueue_isr(acb);
 	}
+	/* enable all outbound interrupt */
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
+//	CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
 }
 /*
 ******************************************************************************
@@ -1694,6 +2077,9 @@ static void arcmsr_interrupt(struct AdapterControlBlock *acb)
 	case ACB_ADAPTER_TYPE_C:
 		arcmsr_handle_hbc_isr(acb);
 		break;
+	case ACB_ADAPTER_TYPE_D:
+		arcmsr_handle_hbd_isr(acb);
+		break;
 	default:
 		kprintf("arcmsr%d: interrupt service,"
 		" unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
@@ -1706,17 +2092,17 @@ static void arcmsr_interrupt(struct AdapterControlBlock *acb)
 */
 static void arcmsr_intr_handler(void *arg)
 {
-	struct AdapterControlBlock *acb=(struct AdapterControlBlock *)arg;
+	struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
 
-	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 	arcmsr_interrupt(acb);
-	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 }
 /*
 ******************************************************************************
 ******************************************************************************
 */
-static void	arcmsr_polling_devmap(void* arg)
+static void	arcmsr_polling_devmap(void *arg)
 {
 	struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
 	switch (acb->adapter_type) {
@@ -1732,6 +2118,10 @@ static void	arcmsr_polling_devmap(void* arg)
 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 		break;
+
+    	case ACB_ADAPTER_TYPE_D:
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
+	    	break;
 	}
 
 	if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
@@ -1749,7 +2139,7 @@ static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
 {
 	u_int32_t intmask_org;
 
-	if(acb!=NULL) {
+	if(acb != NULL) {
 		/* stop adapter background rebuild */
 		if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
 			intmask_org = arcmsr_disable_allintr(acb);
@@ -1766,25 +2156,25 @@ static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
 */
 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
 {
-	struct CMD_MESSAGE_FIELD * pcmdmessagefld;
-	u_int32_t retvalue=EINVAL;
+	struct CMD_MESSAGE_FIELD *pcmdmessagefld;
+	u_int32_t retvalue = EINVAL;
 
-	pcmdmessagefld=(struct CMD_MESSAGE_FIELD *) arg;
+	pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
 	if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
 		return retvalue;
 	}
 	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
 	switch(ioctl_cmd) {
 	case ARCMSR_MESSAGE_READ_RQBUFFER: {
-			u_int8_t * pQbuffer;
-			u_int8_t * ptmpQbuffer=pcmdmessagefld->messagedatabuffer;
+			u_int8_t *pQbuffer;
+			u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;			
 			u_int32_t allxfer_len=0;
 
-			while((acb->rqbuf_firstindex!=acb->rqbuf_lastindex)
-				&& (allxfer_len<1031)) {
+			while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 
+				&& (allxfer_len < 1031)) {
 				/*copy READ QBUFFER to srb*/
-				pQbuffer= &acb->rqbuffer[acb->rqbuf_firstindex];
-				memcpy(ptmpQbuffer, pQbuffer, 1);
+				pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
+				*ptmpQbuffer = *pQbuffer;
 				acb->rqbuf_firstindex++;
 				acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
 				/*if last index number set it to 0 */
@@ -1792,51 +2182,38 @@ u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_c
 				allxfer_len++;
 			}
 			if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
-				struct QBUFFER * prbuffer;
-				u_int8_t * iop_data;
-				u_int32_t iop_len;
+				struct QBUFFER *prbuffer;
 
 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
-				prbuffer=arcmsr_get_iop_rqbuffer(acb);
-				iop_data=(u_int8_t *)prbuffer->data;
-				iop_len=(u_int32_t)prbuffer->data_len;
-				/*this iop data does no chance to make me overflow again here, so just do it*/
-				while(iop_len>0) {
-					pQbuffer= &acb->rqbuffer[acb->rqbuf_lastindex];
-					memcpy(pQbuffer, iop_data, 1);
-					acb->rqbuf_lastindex++;
-					acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
-					/*if last index number set it to 0 */
-					iop_data++;
-					iop_len--;
-				}
-				arcmsr_iop_message_read(acb);
-				/*signature, let IOP know data has been readed */
+				prbuffer = arcmsr_get_iop_rqbuffer(acb);
+				if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
+					acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
 			}
-			pcmdmessagefld->cmdmessage.Length=allxfer_len;
-			pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			pcmdmessagefld->cmdmessage.Length = allxfer_len;
+			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
 			u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
-			u_int8_t * pQbuffer;
-			u_int8_t * ptmpuserbuffer=pcmdmessagefld->messagedatabuffer;
+			u_int8_t *pQbuffer;
+			u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
 
-			user_len=pcmdmessagefld->cmdmessage.Length;
+			user_len = pcmdmessagefld->cmdmessage.Length;
 			/*check if data xfer length of this request will overflow my array qbuffer */
-			wqbuf_lastindex=acb->wqbuf_lastindex;
-			wqbuf_firstindex=acb->wqbuf_firstindex;
-			if(wqbuf_lastindex!=wqbuf_firstindex) {
-				arcmsr_post_ioctldata2iop(acb);
-				pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR;
+			wqbuf_lastindex = acb->wqbuf_lastindex;
+			wqbuf_firstindex = acb->wqbuf_firstindex;
+			if(wqbuf_lastindex != wqbuf_firstindex) {
+				arcmsr_Write_data_2iop_wqbuffer(acb);
+				pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
 			} else {
-				my_empty_len=(wqbuf_firstindex-wqbuf_lastindex-1)&(ARCMSR_MAX_QBUFFER-1);
-				if(my_empty_len>=user_len) {
-					while(user_len>0) {
+				my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
+				    (ARCMSR_MAX_QBUFFER - 1);
+				if(my_empty_len >= user_len) {
+					while(user_len > 0) {
 						/*copy srb data to wqbuffer*/
-						pQbuffer= &acb->wqbuffer[acb->wqbuf_lastindex];
-						memcpy(pQbuffer, ptmpuserbuffer, 1);
+						pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
+						*pQbuffer = *ptmpuserbuffer;
 						acb->wqbuf_lastindex++;
 						acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
 						/*if last index number set it to 0 */
@@ -1845,19 +2222,19 @@ u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_c
 					}
 					/*post fist Qbuffer*/
 					if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
-						acb->acb_flags &=~ACB_F_MESSAGE_WQBUFFER_CLEARED;
-						arcmsr_post_ioctldata2iop(acb);
+						acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
+						arcmsr_Write_data_2iop_wqbuffer(acb);
 					}
-					pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
+					pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
 				} else {
-					pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR;
+					pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
 				}
 			}
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
-			u_int8_t * pQbuffer=acb->rqbuffer;
+			u_int8_t *pQbuffer = acb->rqbuffer;
 
 			if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
@@ -1865,16 +2242,16 @@ u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_c
 				/*signature, let IOP know data has been readed */
 			}
 			acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
-			acb->rqbuf_firstindex=0;
-			acb->rqbuf_lastindex=0;
+			acb->rqbuf_firstindex = 0;
+			acb->rqbuf_lastindex = 0;
 			memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
-			pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
 		{
-			u_int8_t * pQbuffer=acb->wqbuffer;
+			u_int8_t *pQbuffer = acb->wqbuffer;
 
 			if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
@@ -1882,15 +2259,15 @@ u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_c
 				/*signature, let IOP know data has been readed */
 			}
 			acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
-			acb->wqbuf_firstindex=0;
-			acb->wqbuf_lastindex=0;
+			acb->wqbuf_firstindex = 0;
+			acb->wqbuf_lastindex = 0;
 			memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
-			pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
-			u_int8_t * pQbuffer;
+			u_int8_t *pQbuffer;
 
 			if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
@@ -1900,44 +2277,44 @@ u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_c
 			acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
 					|ACB_F_MESSAGE_RQBUFFER_CLEARED
 					|ACB_F_MESSAGE_WQBUFFER_READ);
-			acb->rqbuf_firstindex=0;
-			acb->rqbuf_lastindex=0;
-			acb->wqbuf_firstindex=0;
-			acb->wqbuf_lastindex=0;
-			pQbuffer=acb->rqbuffer;
+			acb->rqbuf_firstindex = 0;
+			acb->rqbuf_lastindex = 0;
+			acb->wqbuf_firstindex = 0;
+			acb->wqbuf_lastindex = 0;
+			pQbuffer = acb->rqbuffer;
 			memset(pQbuffer, 0, sizeof(struct QBUFFER));
-			pQbuffer=acb->wqbuffer;
+			pQbuffer = acb->wqbuffer;
 			memset(pQbuffer, 0, sizeof(struct QBUFFER));
-			pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
-			pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_3F;
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	case ARCMSR_MESSAGE_SAY_HELLO: {
-			u_int8_t * hello_string="Hello! I am ARCMSR";
-			u_int8_t * puserbuffer=(u_int8_t *)pcmdmessagefld->messagedatabuffer;
+			u_int8_t *hello_string = "Hello! I am ARCMSR";
+			u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
 
 			if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
-				pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR;
+				pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
 				ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
 				return ENOIOCTL;
 			}
-			pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK;
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	case ARCMSR_MESSAGE_SAY_GOODBYE: {
 			arcmsr_iop_parking(acb);
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
 			arcmsr_flush_adapter_cache(acb);
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
 		}
 		break;
 	}
@@ -1951,54 +2328,46 @@ u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_c
 static void arcmsr_free_srb(struct CommandControlBlock *srb)
 {
 	struct AdapterControlBlock	*acb;
-	int	mutex;
 
 	acb = srb->acb;
-	mutex = lockstatus(&acb->qbuffer_lock, curthread);
-	if( mutex == 0 )
-		ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
-	srb->srb_state=ARCMSR_SRB_DONE;
-	srb->srb_flags=0;
-	acb->srbworkingQ[acb->workingsrb_doneindex]=srb;
+	ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
+	srb->srb_state = ARCMSR_SRB_DONE;
+	srb->srb_flags = 0;
+	acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
 	acb->workingsrb_doneindex++;
 	acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
-	if( mutex == 0 )
-		ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_RELEASE(&acb->srb_lock);
 }
 /*
 **************************************************************************
 **************************************************************************
 */
-struct CommandControlBlock * arcmsr_get_freesrb(struct AdapterControlBlock *acb)
+struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
 {
-	struct CommandControlBlock *srb=NULL;
+	struct CommandControlBlock *srb = NULL;
 	u_int32_t workingsrb_startindex, workingsrb_doneindex;
-	int	mutex;
 
-	mutex = lockstatus(&acb->qbuffer_lock, curthread);
-	if( mutex == 0 )
-		ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
-	workingsrb_doneindex=acb->workingsrb_doneindex;
-	workingsrb_startindex=acb->workingsrb_startindex;
-	srb=acb->srbworkingQ[workingsrb_startindex];
+	ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
+	workingsrb_doneindex = acb->workingsrb_doneindex;
+	workingsrb_startindex = acb->workingsrb_startindex;
+	srb = acb->srbworkingQ[workingsrb_startindex];
 	workingsrb_startindex++;
 	workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
-	if(workingsrb_doneindex!=workingsrb_startindex) {
-		acb->workingsrb_startindex=workingsrb_startindex;
+	if(workingsrb_doneindex != workingsrb_startindex) {
+		acb->workingsrb_startindex = workingsrb_startindex;
 	} else {
-		srb=NULL;
+		srb = NULL;
 	}
-	if( mutex == 0 )
-		ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_RELEASE(&acb->srb_lock);
 	return(srb);
 }
 /*
 **************************************************************************
 **************************************************************************
 */
-static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb * pccb)
+static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
 {
-	struct CMD_MESSAGE_FIELD * pcmdmessagefld;
+	struct CMD_MESSAGE_FIELD *pcmdmessagefld;
 	int retvalue = 0, transfer_len = 0;
 	char *buffer;
 	u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 |
@@ -2021,13 +2390,14 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 	switch(controlcode) {
 	case ARCMSR_MESSAGE_READ_RQBUFFER: {
 			u_int8_t *pQbuffer;
-			u_int8_t *ptmpQbuffer=pcmdmessagefld->messagedatabuffer;
+			u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
 			int32_t allxfer_len = 0;
 
+			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
 			while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
 				&& (allxfer_len < 1031)) {
 				pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
-				memcpy(ptmpQbuffer, pQbuffer, 1);
+				*ptmpQbuffer = *pQbuffer;
 				acb->rqbuf_firstindex++;
 				acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
 				ptmpQbuffer++;
@@ -2035,38 +2405,29 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 			}
 			if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
 				struct QBUFFER  *prbuffer;
-				u_int8_t  *iop_data;
-				int32_t iop_len;
 
 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
-				prbuffer=arcmsr_get_iop_rqbuffer(acb);
-				iop_data = (u_int8_t *)prbuffer->data;
-				iop_len =(u_int32_t)prbuffer->data_len;
-				while (iop_len > 0) {
-			        pQbuffer= &acb->rqbuffer[acb->rqbuf_lastindex];
-					memcpy(pQbuffer, iop_data, 1);
-					acb->rqbuf_lastindex++;
-					acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
-					iop_data++;
-					iop_len--;
-				}
-				arcmsr_iop_message_read(acb);
+				prbuffer = arcmsr_get_iop_rqbuffer(acb);
+				if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
+					acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
 			}
 			pcmdmessagefld->cmdmessage.Length = allxfer_len;
 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
-			retvalue=ARCMSR_MESSAGE_SUCCESS;
+			retvalue = ARCMSR_MESSAGE_SUCCESS;
+			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
 		}
 		break;
 	case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
 			int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
 			u_int8_t *pQbuffer;
-			u_int8_t *ptmpuserbuffer=pcmdmessagefld->messagedatabuffer;
+			u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
 
 			user_len = pcmdmessagefld->cmdmessage.Length;
+			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
 			wqbuf_lastindex = acb->wqbuf_lastindex;
 			wqbuf_firstindex = acb->wqbuf_firstindex;
 			if (wqbuf_lastindex != wqbuf_firstindex) {
-				arcmsr_post_ioctldata2iop(acb);
+				arcmsr_Write_data_2iop_wqbuffer(acb);
 				/* has error report sensedata */
 			    if(pccb->csio.sense_len) {
 				((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
@@ -2085,7 +2446,7 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 				if (my_empty_len >= user_len) {
 					while (user_len > 0) {
 						pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
-						memcpy(pQbuffer, ptmpuserbuffer, 1);
+						*pQbuffer = *ptmpuserbuffer;
 						acb->wqbuf_lastindex++;
 						acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
 						ptmpuserbuffer++;
@@ -2093,8 +2454,8 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 					}
 					if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
 						acb->acb_flags &=
-						~ACB_F_MESSAGE_WQBUFFER_CLEARED;
-						arcmsr_post_ioctldata2iop(acb);
+						    ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
+						arcmsr_Write_data_2iop_wqbuffer(acb);
 					}
 				} else {
 					/* has error report sensedata */
@@ -2111,11 +2472,13 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 					retvalue = ARCMSR_MESSAGE_FAIL;
 				}
 			}
+			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
 		}
 		break;
 	case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
 			u_int8_t *pQbuffer = acb->rqbuffer;
 
+			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
 			if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
 				arcmsr_iop_message_read(acb);
@@ -2125,12 +2488,14 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 			acb->rqbuf_lastindex = 0;
 			memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
 			pcmdmessagefld->cmdmessage.ReturnCode =
-			ARCMSR_MESSAGE_RETURNCODE_OK;
+			    ARCMSR_MESSAGE_RETURNCODE_OK;
+			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
 		}
 		break;
 	case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
 			u_int8_t *pQbuffer = acb->wqbuffer;
 
+			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
 			if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
 				arcmsr_iop_message_read(acb);
@@ -2143,11 +2508,13 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 			memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
 			pcmdmessagefld->cmdmessage.ReturnCode =
 				ARCMSR_MESSAGE_RETURNCODE_OK;
+			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
 		}
 		break;
 	case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
 			u_int8_t *pQbuffer;
 
+			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
 			if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
 				arcmsr_iop_message_read(acb);
@@ -2165,6 +2532,7 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 			pQbuffer = acb->wqbuffer;
 			memset(pQbuffer, 0, sizeof (struct QBUFFER));
 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
+			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
 		}
 		break;
 	case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
@@ -2172,7 +2540,7 @@ static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *
 		}
 		break;
 	case ARCMSR_MESSAGE_SAY_HELLO: {
-			int8_t * hello_string = "Hello! I am ARCMSR";
+			int8_t *hello_string = "Hello! I am ARCMSR";
 
 			memcpy(pcmdmessagefld->messagedatabuffer, hello_string
 				, (int16_t)strlen(hello_string));
@@ -2197,17 +2565,15 @@ message_out:
 */
 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
 {
-	struct CommandControlBlock *srb=(struct CommandControlBlock *)arg;
-	struct AdapterControlBlock *acb=(struct AdapterControlBlock *)srb->acb;
-	union ccb * pccb;
+	struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
+	struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
+	union ccb *pccb;
 	int target, lun;
 
-	pccb=srb->pccb;
-	target=pccb->ccb_h.target_id;
-	lun=pccb->ccb_h.target_lun;
-#ifdef ARCMSR_DEBUG1
+	pccb = srb->pccb;
+	target = pccb->ccb_h.target_id;
+	lun = pccb->ccb_h.target_lun;
 	acb->pktRequestCount++;
-#endif
 	if(error != 0) {
 		if(error != EFBIG) {
 			kprintf("arcmsr%d: unexpected error %x"
@@ -2231,12 +2597,12 @@ static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg,
 		arcmsr_srb_complete(srb, 0);
 		return;
 	}
-	if(acb->devstate[target][lun]==ARECA_RAID_GONE) {
+	if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
 		u_int8_t block_cmd, cmd;
 
 		cmd = pccb->csio.cdb_io.cdb_bytes[0];
-		block_cmd= cmd & 0x0f;
-		if(block_cmd==0x08 || block_cmd==0x0a) {
+		block_cmd = cmd & 0x0f;
+		if(block_cmd == 0x08 || block_cmd == 0x0a) {
 			kprintf("arcmsr%d:block 'read/write' command "
 				"with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
 				, acb->pci_unit, cmd, target, lun);
@@ -2252,10 +2618,14 @@ static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg,
 		arcmsr_srb_complete(srb, 0);
 		return;
 	}
-	if(acb->srboutstandingcount > ARCMSR_MAX_OUTSTANDING_CMD) {
-		xpt_freeze_simq(acb->psim, 1);
-		pccb->ccb_h.status = CAM_REQUEUE_REQ;
-		acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
+	if(acb->srboutstandingcount >= acb->maxOutstanding) {
+		if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
+		{
+			xpt_freeze_simq(acb->psim, 1);
+			acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
+		}
+		pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
+		pccb->ccb_h.status |= CAM_REQUEUE_REQ;
 		arcmsr_srb_complete(srb, 0);
 		return;
 	}
@@ -2273,12 +2643,12 @@ static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg,
 *****************************************************************************************
 *****************************************************************************************
 */
-static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb)
+static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
 {
 	struct CommandControlBlock *srb;
-	struct AdapterControlBlock *acb=(struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
+	struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
 	u_int32_t intmask_org;
-	int i=0;
+	int i = 0;
 
 	acb->num_aborts++;
 	/*
@@ -2290,18 +2660,18 @@ static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb)
 	** command return success.
 	***************************************************************************
 	*/
-	if(acb->srboutstandingcount!=0) {
+	if(acb->srboutstandingcount != 0) {
 		/* disable all outbound interrupt */
-		intmask_org=arcmsr_disable_allintr(acb);
-		for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) {
-			srb=acb->psrb_pool[i];
-			if(srb->srb_state==ARCMSR_SRB_START) {
-				if(srb->pccb==abortccb) {
-					srb->srb_state=ARCMSR_SRB_ABORTED;
-					kprintf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'"
+		intmask_org = arcmsr_disable_allintr(acb);
+		for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
+			srb = acb->psrb_pool[i];
+			if(srb->srb_state == ARCMSR_SRB_START) {
+				if(srb->pccb == abortccb) {
+					srb->srb_state = ARCMSR_SRB_ABORTED;
+					kprintf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'"
 						"outstanding command \n"
 						, acb->pci_unit, abortccb->ccb_h.target_id
-						, abortccb->ccb_h.target_lun, srb);
+						, (uintmax_t)abortccb->ccb_h.target_lun, srb);
 					arcmsr_polling_srbdone(acb, srb);
 					/* enable outbound Post Queue, outbound doorbell Interrupt */
 					arcmsr_enable_allintr(acb, intmask_org);
@@ -2320,11 +2690,11 @@ static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb)
 */
 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
 {
-	int retry=0;
+	int retry = 0;
 
 	acb->num_resets++;
-	acb->acb_flags |=ACB_F_BUS_RESET;
-	while(acb->srboutstandingcount!=0 && retry < 400) {
+	acb->acb_flags |= ACB_F_BUS_RESET;
+	while(acb->srboutstandingcount != 0 && retry < 400) {
 		arcmsr_interrupt(acb);
 		UDELAY(25000);
 		retry++;
@@ -2337,19 +2707,19 @@ static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
 **************************************************************************
 */
 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
-		union ccb * pccb)
+		union ccb *pccb)
 {
+	if (pccb->ccb_h.target_lun) {
+		pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
+		xpt_done(pccb);
+		return;
+	}
 	pccb->ccb_h.status |= CAM_REQ_CMP;
 	switch (pccb->csio.cdb_io.cdb_bytes[0]) {
 	case INQUIRY: {
 		unsigned char inqdata[36];
-		char *buffer=pccb->csio.data_ptr;
+		char *buffer = pccb->csio.data_ptr;
 
-		if (pccb->ccb_h.target_lun) {
-			pccb->ccb_h.status |= CAM_SEL_TIMEOUT;
-			xpt_done(pccb);
-			return;
-		}
 		inqdata[0] = T_PROCESSOR;	/* Periph Qualifier & Periph Dev Type */
 		inqdata[1] = 0;				/* rem media bit & Dev Type Modifier */
 		inqdata[2] = 0;				/* ISO, ECMA, & ANSI versions */
@@ -2382,12 +2752,12 @@ static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
 *********************************************************************
 *********************************************************************
 */
-static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
+static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
 {
-	struct AdapterControlBlock *  acb;
+	struct AdapterControlBlock *acb;
 
-	acb=(struct AdapterControlBlock *) cam_sim_softc(psim);
-	if(acb==NULL) {
+	acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
+	if(acb == NULL) {
 		pccb->ccb_h.status |= CAM_REQ_INVALID;
 		xpt_done(pccb);
 		return;
@@ -2395,14 +2765,14 @@ static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
 	switch (pccb->ccb_h.func_code) {
 	case XPT_SCSI_IO: {
 			struct CommandControlBlock *srb;
-			int target=pccb->ccb_h.target_id;
+			int target = pccb->ccb_h.target_id;
 
 			if(target == 16) {
 				/* virtual device for iop message transfer */
 				arcmsr_handle_virtual_command(acb, pccb);
 				return;
 			}
-			if((srb=arcmsr_get_freesrb(acb)) == NULL) {
+			if((srb = arcmsr_get_freesrb(acb)) == NULL) {
 				pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
 				xpt_done(pccb);
 				return;
@@ -2462,27 +2832,30 @@ static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
 			break;
 		}
 	case XPT_PATH_INQ: {
-			struct ccb_pathinq *cpi= &pccb->cpi;
-
-			cpi->version_num=1;
-			cpi->hba_inquiry=PI_SDTR_ABLE | PI_TAG_ABLE;
-			cpi->target_sprt=0;
-			cpi->hba_misc=0;
-			cpi->hba_eng_cnt=0;
-			cpi->max_target=ARCMSR_MAX_TARGETID;        /* 0-16 */
-			cpi->max_lun=ARCMSR_MAX_TARGETLUN;	    /* 0-7 */
-			cpi->initiator_id=ARCMSR_SCSI_INITIATOR_ID; /* 255 */
-			cpi->bus_id=cam_sim_bus(psim);
+			struct ccb_pathinq *cpi = &pccb->cpi;
+
+			cpi->version_num = 1;
+			cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
+			cpi->target_sprt = 0;
+			cpi->hba_misc = 0;
+			cpi->hba_eng_cnt = 0;
+			cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
+			cpi->max_lun = ARCMSR_MAX_TARGETLUN;	    /* 0-7 */
+			cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
+			cpi->bus_id = cam_sim_bus(psim);
 			strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
 			strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
 			strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
-			cpi->unit_number=cam_sim_unit(psim);
-			if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
+			cpi->unit_number = cam_sim_unit(psim);
+			if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G)
+				cpi->base_transfer_speed = 1200000;
+			else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
 				cpi->base_transfer_speed = 600000;
 			else
 				cpi->base_transfer_speed = 300000;
 			if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
-			   (acb->vendor_device_id == PCIDevVenIDARC1680))
+			   (acb->vendor_device_id == PCIDevVenIDARC1680) ||
+			   (acb->vendor_device_id == PCIDevVenIDARC1214))
 			{
 				cpi->transport = XPORT_SAS;
 				cpi->transport_version = 0;
@@ -2502,7 +2875,7 @@ static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
 	case XPT_ABORT: {
 			union ccb *pabort_ccb;
 
-			pabort_ccb=pccb->cab.abort_ccb;
+			pabort_ccb = pccb->cab.abort_ccb;
 			switch (pabort_ccb->ccb_h.func_code) {
 			case XPT_ACCEPT_TARGET_IO:
 			case XPT_IMMED_NOTIFY:
@@ -2552,7 +2925,7 @@ static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
 				xpt_done(pccb);
 				break;
 			}
-			cts= &pccb->cts;
+			cts = &pccb->cts;
 			{
 				struct ccb_trans_settings_scsi *scsi;
 				struct ccb_trans_settings_spi *spi;
@@ -2564,14 +2937,18 @@ static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
 				cts->protocol = PROTO_SCSI;
 
 				if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
-				   (acb->vendor_device_id == PCIDevVenIDARC1680))
+				   (acb->vendor_device_id == PCIDevVenIDARC1680) ||
+				   (acb->vendor_device_id == PCIDevVenIDARC1214))
 				{
 					cts->protocol_version = SCSI_REV_SPC2;
 					cts->transport_version = 0;
 					cts->transport = XPORT_SAS;
 					sas = &cts->xport_specific.sas;
 					sas->valid = CTS_SAS_VALID_SPEED;
-					if(acb->vendor_device_id == PCIDevVenIDARC1880)
+					if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883)
+						sas->bitrate = 1200000;
+					else if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
+					   (acb->vendor_device_id == PCIDevVenIDARC1214))
 						sas->bitrate = 600000;
 					else if(acb->vendor_device_id == PCIDevVenIDARC1680)
 						sas->bitrate = 300000;
@@ -2583,9 +2960,9 @@ static void arcmsr_action(struct cam_sim * psim, union ccb * pccb)
 					cts->transport = XPORT_SPI;
 					spi = &cts->xport_specific.spi;
 					spi->flags = CTS_SPI_FLAGS_DISC_ENB;
-					spi->sync_period=2;
-					spi->sync_offset=32;
-					spi->bus_width=MSG_EXT_WDTR_BUS_16_BIT;
+					spi->sync_period = 2;
+					spi->sync_offset = 32;
+					spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
 					spi->valid = CTS_SPI_VALID_DISC
 						| CTS_SPI_VALID_SYNC_RATE
 						| CTS_SPI_VALID_SYNC_OFFSET
@@ -2657,6 +3034,18 @@ static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
 **********************************************************************
 **********************************************************************
 */
+static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
+{
+	acb->acb_flags |= ACB_F_MSG_START_BGRB;
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
+	if(!arcmsr_hbd_wait_msgint_ready(acb)) {
+		kprintf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
+	}
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
 {
 	switch (acb->adapter_type) {
@@ -2669,6 +3058,9 @@ static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
 	case ACB_ADAPTER_TYPE_C:
 		arcmsr_start_hbc_bgrb(acb);
 		break;
+	case ACB_ADAPTER_TYPE_D:
+		arcmsr_start_hbd_bgrb(acb);
+		break;
 	}
 }
 /*
@@ -2688,8 +3080,8 @@ polling_ccb_retry:
 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);	/*clear interrupt*/
 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 	while(1) {
-		if((flag_srb=CHIP_REG_READ32(HBA_MessageUnit,
-			0, outbound_queueport))==0xFFFFFFFF) {
+		if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 
+			0, outbound_queueport)) == 0xFFFFFFFF) {
 			if(poll_srb_done) {
 				break;/*chip FIFO no ccb for completion already*/
 			} else {
@@ -2701,17 +3093,17 @@ polling_ccb_retry:
 			}
 		}
 		/* check if command done with no error*/
-		srb=(struct CommandControlBlock *)
+		srb = (struct CommandControlBlock *)
 			(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
-        error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
-		poll_srb_done = (srb==poll_srb) ? 1:0;
-		if((srb->acb!=acb) || (srb->srb_state!=ARCMSR_SRB_START)) {
-			if(srb->srb_state==ARCMSR_SRB_ABORTED) {
-				kprintf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
+        error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+		poll_srb_done = (srb == poll_srb) ? 1:0;
+		if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
+			if(srb->srb_state == ARCMSR_SRB_ABORTED) {
+				kprintf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
 					"poll command abort successfully \n"
 					, acb->pci_unit
 					, srb->pccb->ccb_h.target_id
-					, srb->pccb->ccb_h.target_lun, srb);
+					, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 				arcmsr_srb_complete(srb, 1);
 				continue;
@@ -2732,7 +3124,7 @@ polling_ccb_retry:
 */
 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
 {
-	struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
+	struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
 	struct CommandControlBlock *srb;
 	u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
 	int index;
@@ -2744,8 +3136,8 @@ polling_ccb_retry:
 	0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 	while(1) {
-		index=phbbmu->doneq_index;
-		if((flag_srb=phbbmu->done_qbuffer[index]) == 0) {
+		index = phbbmu->doneq_index;
+		if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
 			if(poll_srb_done) {
 				break;/*chip FIFO no ccb for completion already*/
 			} else {
@@ -2756,22 +3148,22 @@ polling_ccb_retry:
 				goto polling_ccb_retry;
 			}
 		}
-		phbbmu->done_qbuffer[index]=0;
+		phbbmu->done_qbuffer[index] = 0;
 		index++;
 		index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
-		phbbmu->doneq_index=index;
+		phbbmu->doneq_index = index;
 		/* check if command done with no error*/
-		srb=(struct CommandControlBlock *)
+		srb = (struct CommandControlBlock *)
 			(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
-        error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
-		poll_srb_done = (srb==poll_srb) ? 1:0;
-		if((srb->acb!=acb) || (srb->srb_state!=ARCMSR_SRB_START)) {
-			if(srb->srb_state==ARCMSR_SRB_ABORTED) {
-				kprintf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
+        error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
+		poll_srb_done = (srb == poll_srb) ? 1:0;
+		if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
+			if(srb->srb_state == ARCMSR_SRB_ABORTED) {
+				kprintf("arcmsr%d: scsi id=%d lun=%jx srb='%p'"
 					"poll command abort successfully \n"
 					, acb->pci_unit
 					, srb->pccb->ccb_h.target_id
-					, srb->pccb->ccb_h.target_lun, srb);
+					, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 				arcmsr_srb_complete(srb, 1);
 				continue;
@@ -2816,14 +3208,70 @@ polling_ccb_retry:
 		}
 		flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 		/* check if command done with no error*/
-		srb=(struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
-        error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
+		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
+        error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
+		if (poll_srb != NULL)
+			poll_srb_done = (srb == poll_srb) ? 1:0;
+		if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
+			if(srb->srb_state == ARCMSR_SRB_ABORTED) {
+				kprintf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
+						, acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
+				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
+				arcmsr_srb_complete(srb, 1);
+				continue;
+			}
+			kprintf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
+					, acb->pci_unit, srb, acb->srboutstandingcount);
+			continue;
+		}
+		arcmsr_report_srb_state(acb, srb, error);
+	}	/*drain reply FIFO*/
+}
+/*
+**********************************************************************
+** 
+**********************************************************************
+*/
+static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
+{
+	struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
+	struct CommandControlBlock *srb;
+	u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
+	u_int32_t outbound_write_pointer;
+	u_int16_t	error, doneq_index;
+	
+polling_ccb_retry:
+	poll_count++;
+	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+	while(1) {
+		outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
+		doneq_index = phbdmu->doneq_index;
+		if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
+			if(poll_srb_done) {
+				break;/*chip FIFO no ccb for completion already*/
+			} else {
+				UDELAY(25000);
+			    if ((poll_count > 100) && (poll_srb != NULL)) {
+					break;
+				}
+			    if (acb->srboutstandingcount == 0) {
+				    break;
+			    }
+				goto polling_ccb_retry;
+			}
+		}
+		doneq_index = arcmsr_get_doneq_index(phbdmu);
+		flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
+		/* check if command done with no error*/
+		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
+        error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
+		CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
 		if (poll_srb != NULL)
-			poll_srb_done = (srb==poll_srb) ? 1:0;
-		if((srb->acb!=acb) || (srb->srb_state!=ARCMSR_SRB_START)) {
-			if(srb->srb_state==ARCMSR_SRB_ABORTED) {
-				kprintf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
-						, acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
+			poll_srb_done = (srb == poll_srb) ? 1:0;
+		if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
+			if(srb->srb_state == ARCMSR_SRB_ABORTED) {
+				kprintf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n"
+						, acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb);
 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 				arcmsr_srb_complete(srb, 1);
 				continue;
@@ -2854,6 +3302,10 @@ static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct Comma
 			arcmsr_polling_hbc_srbdone(acb, poll_srb);
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			arcmsr_polling_hbd_srbdone(acb, poll_srb);
+		}
+		break;
 	}
 }
 /*
@@ -2862,11 +3314,11 @@ static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct Comma
 */
 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
 {
-	char *acb_firm_model=acb->firm_model;
-	char *acb_firm_version=acb->firm_version;
+	char *acb_firm_model = acb->firm_model;
+	char *acb_firm_version = acb->firm_version;
 	char *acb_device_map = acb->device_map;
-	size_t iop_firm_model=offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);	/*firm_model,15,60-67*/
-	size_t iop_firm_version=offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);	/*firm_version,17,68-83*/
+	size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);	/*firm_model,15,60-67*/
+	size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);	/*firm_version,17,68-83*/
 	size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
 	int i;
 
@@ -2874,33 +3326,36 @@ static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
 	if(!arcmsr_hba_wait_msgint_ready(acb)) {
 		kprintf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
 	}
-	i=0;
-	while(i<8) {
-		*acb_firm_model=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
+	i = 0;
+	while(i < 8) {
+		*acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 
 		/* 8 bytes firm_model, 15, 60-67*/
 		acb_firm_model++;
 		i++;
 	}
 	i=0;
-	while(i<16) {
-		*acb_firm_version=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
+	while(i < 16) {
+		*acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);  
 		/* 16 bytes firm_version, 17, 68-83*/
 		acb_firm_version++;
 		i++;
 	}
 	i=0;
-	while(i<16) {
-		*acb_device_map=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
+	while(i < 16) {
+		*acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);  
 		acb_device_map++;
 		i++;
 	}
-	kprintf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
-	kprintf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
-	acb->firm_request_len=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
-	acb->firm_numbers_queue=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
-	acb->firm_sdram_size=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
-	acb->firm_ide_channels=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
-	acb->firm_cfg_version=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25,	  */
+	kprintf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
+	acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
+	acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
+	acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
+	acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
+	acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25, 	  */
+	if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
+		acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
+	else
+		acb->maxOutstanding = acb->firm_numbers_queue - 1;
 }
 /*
 **********************************************************************
@@ -2908,11 +3363,11 @@ static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
 */
 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
 {
-	char *acb_firm_model=acb->firm_model;
-	char *acb_firm_version=acb->firm_version;
+	char *acb_firm_model = acb->firm_model;
+	char *acb_firm_version = acb->firm_version;
 	char *acb_device_map = acb->device_map;
-	size_t iop_firm_model=offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);	/*firm_model,15,60-67*/
-	size_t iop_firm_version=offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);	/*firm_version,17,68-83*/
+	size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);	/*firm_model,15,60-67*/
+	size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);	/*firm_version,17,68-83*/
 	size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
 	int i;
 
@@ -2920,33 +3375,36 @@ static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
 	if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 		kprintf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
 	}
-	i=0;
-	while(i<8) {
-		*acb_firm_model=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
+	i = 0;
+	while(i < 8) {
+		*acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
 		/* 8 bytes firm_model, 15, 60-67*/
 		acb_firm_model++;
 		i++;
 	}
-	i=0;
-	while(i<16) {
-		*acb_firm_version=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
+	i = 0;
+	while(i < 16) {
+		*acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
 		/* 16 bytes firm_version, 17, 68-83*/
 		acb_firm_version++;
 		i++;
 	}
-	i=0;
-	while(i<16) {
-		*acb_device_map=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
+	i = 0;
+	while(i < 16) {
+		*acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);  
 		acb_device_map++;
 		i++;
 	}
-	kprintf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
-	kprintf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
-	acb->firm_request_len=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
-	acb->firm_numbers_queue=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
-	acb->firm_sdram_size=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
-	acb->firm_ide_channels=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
-	acb->firm_cfg_version=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25,	  */
+	kprintf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
+	acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
+	acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
+	acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
+	acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
+	acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25, 	  */
+	if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
+		acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
+	else
+		acb->maxOutstanding = acb->firm_numbers_queue - 1;
 }
 /*
 **********************************************************************
@@ -2954,11 +3412,11 @@ static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
 */
 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
 {
-	char *acb_firm_model=acb->firm_model;
-	char *acb_firm_version=acb->firm_version;
+	char *acb_firm_model = acb->firm_model;
+	char *acb_firm_version = acb->firm_version;
 	char *acb_device_map = acb->device_map;
-	size_t iop_firm_model=offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
-	size_t iop_firm_version=offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
+	size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
+	size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
 	size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
 	int i;
 
@@ -2967,33 +3425,87 @@ static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
 	if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 		kprintf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
 	}
-	i=0;
-	while(i<8) {
-		*acb_firm_model=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
+	i = 0;
+	while(i < 8) {
+		*acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 
 		/* 8 bytes firm_model, 15, 60-67*/
 		acb_firm_model++;
 		i++;
 	}
-	i=0;
-	while(i<16) {
-		*acb_firm_version=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
+	i = 0;
+	while(i < 16) {
+		*acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);  
 		/* 16 bytes firm_version, 17, 68-83*/
 		acb_firm_version++;
 		i++;
 	}
-	i=0;
-	while(i<16) {
-		*acb_device_map=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
+	i = 0;
+	while(i < 16) {
+		*acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);  
+		acb_device_map++;
+		i++;
+	}
+	kprintf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
+	acb->firm_request_len	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);	/*firm_request_len,   1, 04-07*/
+	acb->firm_numbers_queue	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);	/*firm_numbers_queue, 2, 08-11*/
+	acb->firm_sdram_size	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);	/*firm_sdram_size,    3, 12-15*/
+	acb->firm_ide_channels	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);	/*firm_ide_channels,  4, 16-19*/
+	acb->firm_cfg_version	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25, 	  */
+	if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
+		acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
+	else
+		acb->maxOutstanding = acb->firm_numbers_queue - 1;
+}
+/*
+**********************************************************************
+**********************************************************************
+*/
+static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
+{
+	char *acb_firm_model = acb->firm_model;
+	char *acb_firm_version = acb->firm_version;
+	char *acb_device_map = acb->device_map;
+	size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
+	size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
+	size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
+	int i;
+	
+	if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
+		CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
+	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
+	if(!arcmsr_hbd_wait_msgint_ready(acb)) {
+		kprintf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
+	}
+	i = 0;
+	while(i < 8) {
+		*acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 
+		/* 8 bytes firm_model, 15, 60-67*/
+		acb_firm_model++;
+		i++;
+	}
+	i = 0;
+	while(i < 16) {
+		*acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);  
+		/* 16 bytes firm_version, 17, 68-83*/
+		acb_firm_version++;
+		i++;
+	}
+	i = 0;
+	while(i < 16) {
+		*acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);  
 		acb_device_map++;
 		i++;
 	}
-	kprintf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
-	kprintf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
-	acb->firm_request_len	=CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);	/*firm_request_len,   1, 04-07*/
-	acb->firm_numbers_queue	=CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);	/*firm_numbers_queue, 2, 08-11*/
-	acb->firm_sdram_size	=CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);	/*firm_sdram_size,    3, 12-15*/
-	acb->firm_ide_channels	=CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);	/*firm_ide_channels,  4, 16-19*/
-	acb->firm_cfg_version	=CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25,	  */
+	kprintf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
+	acb->firm_request_len	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);	/*firm_request_len,   1, 04-07*/
+	acb->firm_numbers_queue	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);	/*firm_numbers_queue, 2, 08-11*/
+	acb->firm_sdram_size	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);	/*firm_sdram_size,    3, 12-15*/
+	acb->firm_ide_channels	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]);	/*firm_ide_channels,  4, 16-19*/
+	acb->firm_cfg_version	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25, 	  */
+	if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
+		acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
+	else
+		acb->maxOutstanding = acb->firm_numbers_queue - 1;
 }
 /*
 **********************************************************************
@@ -3014,6 +3526,10 @@ static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
 			arcmsr_get_hbc_config(acb);
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			arcmsr_get_hbd_config(acb);
+		}
+		break;
 	}
 }
 /*
@@ -3062,6 +3578,18 @@ static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
 			}
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
+			{
+				if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
+				{
+					kprintf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
+					return;
+				}
+				UDELAY(15000); /* wait 15 milli-seconds */
+			}
+		}
+		break;
 	}
 }
 /*
@@ -3092,6 +3620,15 @@ static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
 			outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);	/*clear doorbell interrupt */
 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
+			CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
+			CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
+		}
+		break;
+	case ACB_ADAPTER_TYPE_D: {
+			/* empty doorbell Qbuffer if door bell ringed */
+			outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);	/*clear doorbell interrupt */
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
 
 		}
 		break;
@@ -3105,6 +3642,7 @@ static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
 {
 	unsigned long srb_phyaddr;
 	u_int32_t srb_phyaddr_hi32;
+	u_int32_t srb_phyaddr_lo32;
 
 	/*
 	********************************************************************
@@ -3112,12 +3650,12 @@ static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
 	** if freesrb.HighPart is not zero
 	********************************************************************
 	*/
-	srb_phyaddr= (unsigned long) acb->srb_phyaddr.phyaddr;
-//	srb_phyaddr_hi32=(u_int32_t) ((srb_phyaddr>>16)>>16);
-	srb_phyaddr_hi32=acb->srb_phyaddr.B.phyadd_high;
+	srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
+	srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
+	srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
 	switch (acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_A: {
-			if(srb_phyaddr_hi32!=0) {
+			if(srb_phyaddr_hi32 != 0) {
 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
@@ -3137,9 +3675,9 @@ static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
 			u_int32_t post_queue_phyaddr;
 			struct HBB_MessageUnit *phbbmu;
 
-			phbbmu=(struct HBB_MessageUnit *)acb->pmu;
-			phbbmu->postq_index=0;
-			phbbmu->doneq_index=0;
+			phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+			phbbmu->postq_index = 0;
+			phbbmu->doneq_index = 0;
 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
 			if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 				kprintf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
@@ -3165,7 +3703,7 @@ static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
 		}
 		break;
 	case ACB_ADAPTER_TYPE_C: {
-			if(srb_phyaddr_hi32!=0) {
+			if(srb_phyaddr_hi32 != 0) {
 				CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
 				CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
 				CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
@@ -3177,6 +3715,29 @@ static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
 			}
 		}
 		break;
+	case ACB_ADAPTER_TYPE_D: {
+			u_int32_t post_queue_phyaddr, done_queue_phyaddr;
+			struct HBD_MessageUnit0 *phbdmu;
+	
+			phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
+			phbdmu->postq_index = 0;
+			phbdmu->doneq_index = 0x40FF;
+			post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 
+								+ offsetof(struct HBD_MessageUnit0, post_qbuffer);
+			done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 
+								+ offsetof(struct HBD_MessageUnit0, done_qbuffer);
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
+			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
+			if(!arcmsr_hbd_wait_msgint_ready(acb)) {
+				kprintf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
+				return FALSE;
+			}
+		}
+		break;
 	}
 	return (TRUE);
 }
@@ -3190,12 +3751,12 @@ static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
 	{
 	case ACB_ADAPTER_TYPE_A:
 	case ACB_ADAPTER_TYPE_C:
+	case ACB_ADAPTER_TYPE_D:
 		break;
 	case ACB_ADAPTER_TYPE_B: {
 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
 			if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 				kprintf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
-
 				return;
 			}
 		}
@@ -3211,7 +3772,7 @@ static void arcmsr_iop_init(struct AdapterControlBlock *acb)
 	u_int32_t intmask_org;
 
 	/* disable all outbound interrupt */
-	intmask_org=arcmsr_disable_allintr(acb);
+	intmask_org = arcmsr_disable_allintr(acb);
 	arcmsr_wait_firmware_ready(acb);
 	arcmsr_iop_confirm(acb);
 	arcmsr_get_firmware_spec(acb);
@@ -3222,7 +3783,7 @@ static void arcmsr_iop_init(struct AdapterControlBlock *acb)
 	arcmsr_enable_eoi_mode(acb);
 	/* enable outbound Post Queue, outbound doorbell Interrupt */
 	arcmsr_enable_allintr(acb, intmask_org);
-	acb->acb_flags |=ACB_F_IOP_INITED;
+	acb->acb_flags |= ACB_F_IOP_INITED;
 }
 /*
 **********************************************************************
@@ -3230,35 +3791,37 @@ static void arcmsr_iop_init(struct AdapterControlBlock *acb)
 */
 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 {
-	struct AdapterControlBlock *acb=arg;
+	struct AdapterControlBlock *acb = arg;
 	struct CommandControlBlock *srb_tmp;
-	u_int8_t * dma_memptr;
 	u_int32_t i;
-	unsigned long srb_phyaddr=(unsigned long)segs->ds_addr;
+	unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
 
-	dma_memptr=acb->uncacheptr;
-	acb->srb_phyaddr.phyaddr=srb_phyaddr;
-	srb_tmp=(struct CommandControlBlock *)dma_memptr;
-	for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) {
+	acb->srb_phyaddr.phyaddr = srb_phyaddr; 
+	srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
+	for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
 		if(bus_dmamap_create(acb->dm_segs_dmat,
-			 /*flags*/0, &srb_tmp->dm_segs_dmamap)!=0) {
+			 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
 			acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
 			kprintf("arcmsr%d:"
 			" srb dmamap bus_dmamap_create error\n", acb->pci_unit);
 			return;
 		}
-		srb_tmp->cdb_shifted_phyaddr=(acb->adapter_type==ACB_ADAPTER_TYPE_C)?srb_phyaddr:(srb_phyaddr >> 5);
-		srb_tmp->acb=acb;
-		acb->srbworkingQ[i]=acb->psrb_pool[i]=srb_tmp;
-		srb_phyaddr=srb_phyaddr+SRB_SIZE;
-		srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp+SRB_SIZE);
+		if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D))
+		{
+			srb_tmp->cdb_phyaddr_low = srb_phyaddr;
+			srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
+		}
+		else
+			srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
+		srb_tmp->acb = acb;
+		acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
+		srb_phyaddr = srb_phyaddr + SRB_SIZE;
+		srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
 	}
-	acb->vir2phy_offset=(unsigned long)srb_tmp-srb_phyaddr;
+	acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
 }
 /*
 ************************************************************************
-**
-**
 ************************************************************************
 */
 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
@@ -3277,30 +3840,62 @@ static void arcmsr_free_resource(struct AdapterControlBlock *acb)
 ************************************************************************
 ************************************************************************
 */
+static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
+{
+	ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
+	ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
+	ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
+	ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
+}
+/*
+************************************************************************
+************************************************************************
+*/
+static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
+{
+	ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
+	ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
+	ARCMSR_LOCK_DESTROY(&acb->srb_lock);
+	ARCMSR_LOCK_DESTROY(&acb->isr_lock);
+}
+/*
+************************************************************************
+************************************************************************
+*/
 static u_int32_t arcmsr_initialize(device_t dev)
 {
-	struct AdapterControlBlock *acb=device_get_softc(dev);
+	struct AdapterControlBlock *acb = device_get_softc(dev);
 	u_int16_t pci_command;
 	int i, j,max_coherent_size;
 	u_int32_t vendor_dev_id;
 
 	vendor_dev_id = pci_get_devid(dev);
 	acb->vendor_device_id = vendor_dev_id;
+	acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 	switch (vendor_dev_id) {
 	case PCIDevVenIDARC1880:
 	case PCIDevVenIDARC1882:
 	case PCIDevVenIDARC1213:
 	case PCIDevVenIDARC1223: {
-			acb->adapter_type=ACB_ADAPTER_TYPE_C;
+			acb->adapter_type = ACB_ADAPTER_TYPE_C;
+			if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883)
+				acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
+			else
+				acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
+			max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
+		}
+		break;
+	case PCIDevVenIDARC1214: {
+			acb->adapter_type = ACB_ADAPTER_TYPE_D;
 			acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
-			max_coherent_size=ARCMSR_SRBS_POOL_SIZE;
+			max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
 		}
 		break;
 	case PCIDevVenIDARC1200:
 	case PCIDevVenIDARC1201: {
-			acb->adapter_type=ACB_ADAPTER_TYPE_B;
+			acb->adapter_type = ACB_ADAPTER_TYPE_B;
 			acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
-			max_coherent_size=ARCMSR_SRBS_POOL_SIZE+(sizeof(struct HBB_MessageUnit));
+			max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
 		}
 		break;
 	case PCIDevVenIDARC1110:
@@ -3322,9 +3917,9 @@ static u_int32_t arcmsr_initialize(device_t dev)
 	case PCIDevVenIDARC1381:
 	case PCIDevVenIDARC1680:
 	case PCIDevVenIDARC1681: {
-			acb->adapter_type=ACB_ADAPTER_TYPE_A;
+			acb->adapter_type = ACB_ADAPTER_TYPE_A;
 			acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
-			max_coherent_size=ARCMSR_SRBS_POOL_SIZE;
+			max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
 		}
 		break;
 	default: {
@@ -3333,7 +3928,7 @@ static u_int32_t arcmsr_initialize(device_t dev)
 			return ENOMEM;
 		}
 	}
-	if(bus_dma_tag_create(  /*parent*/	NULL,
+	if(bus_dma_tag_create(  /*PCI parent*/		bus_get_dma_tag(dev),
 				/*alignemnt*/	1,
 				/*boundary*/	0,
 				/*lowaddr*/	BUS_SPACE_MAXADDR,
@@ -3367,6 +3962,7 @@ static u_int32_t arcmsr_initialize(device_t dev)
 		kprintf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
 		return ENOMEM;
 	}
+
 	/* DMA tag for our srb structures.... Allocate the freesrb memory */
 	if(bus_dma_tag_create(  /*parent_dmat*/	acb->parent_dmat,
 				/*alignment*/	0x20,
@@ -3402,19 +3998,18 @@ static u_int32_t arcmsr_initialize(device_t dev)
 		kprintf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
 		return ENXIO;
 	}
-	pci_command=pci_read_config(dev, PCIR_COMMAND, 2);
+	pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
 	pci_command |= PCIM_CMD_BUSMASTEREN;
 	pci_command |= PCIM_CMD_PERRESPEN;
 	pci_command |= PCIM_CMD_MWRICEN;
-	/* Enable Busmaster/Mem */
-	pci_command |= PCIM_CMD_MEMEN;
+	/* Enable Busmaster */
 	pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
 	switch(acb->adapter_type) {
 	case ACB_ADAPTER_TYPE_A: {
-			u_int32_t rid0=PCIR_BAR(0);
+			u_int32_t rid0 = PCIR_BAR(0);
 			vm_offset_t	mem_base0;
 
-			acb->sys_res_arcmsr[0]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
+			acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
 			if(acb->sys_res_arcmsr[0] == NULL) {
 				arcmsr_free_resource(acb);
 				kprintf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
@@ -3425,15 +4020,15 @@ static u_int32_t arcmsr_initialize(device_t dev)
 				kprintf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
 				return ENXIO;
 			}
-			mem_base0=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
-			if(mem_base0==0) {
+			mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
+			if(mem_base0 == 0) {
 				arcmsr_free_resource(acb);
 				kprintf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
 				return ENXIO;
 			}
-			acb->btag[0]=rman_get_bustag(acb->sys_res_arcmsr[0]);
-			acb->bhandle[0]=rman_get_bushandle(acb->sys_res_arcmsr[0]);
-			acb->pmu=(struct MessageUnit_UNION *)mem_base0;
+			acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
+			acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
+			acb->pmu = (struct MessageUnit_UNION *)mem_base0;
 		}
 		break;
 	case ACB_ADAPTER_TYPE_B: {
@@ -3441,12 +4036,12 @@ static u_int32_t arcmsr_initialize(device_t dev)
 			struct CommandControlBlock *freesrb;
 			u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
 			vm_offset_t	mem_base[]={0,0};
-			for(i=0; i<2; i++) {
-				if(i==0) {
-					acb->sys_res_arcmsr[i]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
+			for(i=0; i < 2; i++) {
+				if(i == 0) {
+					acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
 											0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE);
 				} else {
-					acb->sys_res_arcmsr[i]=bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
+					acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
 											0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE);
 				}
 				if(acb->sys_res_arcmsr[i] == NULL) {
@@ -3459,28 +4054,54 @@ static u_int32_t arcmsr_initialize(device_t dev)
 					kprintf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
 					return ENXIO;
 				}
-				mem_base[i]=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
-				if(mem_base[i]==0) {
+				mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
+				if(mem_base[i] == 0) {
 					arcmsr_free_resource(acb);
 					kprintf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
 					return ENXIO;
 				}
-				acb->btag[i]=rman_get_bustag(acb->sys_res_arcmsr[i]);
-				acb->bhandle[i]=rman_get_bushandle(acb->sys_res_arcmsr[i]);
+				acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
+				acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
 			}
-			freesrb=(struct CommandControlBlock *)acb->uncacheptr;
-//			acb->pmu=(struct MessageUnit_UNION *)&freesrb[ARCMSR_MAX_FREESRB_NUM];
-			acb->pmu=(struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
-			phbbmu=(struct HBB_MessageUnit *)acb->pmu;
-			phbbmu->hbb_doorbell=(struct HBB_DOORBELL *)mem_base[0];
-			phbbmu->hbb_rwbuffer=(struct HBB_RWBUFFER *)mem_base[1];
+			freesrb = (struct CommandControlBlock *)acb->uncacheptr;
+			acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
+			phbbmu = (struct HBB_MessageUnit *)acb->pmu;
+			phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
+			phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
 		}
 		break;
 	case ACB_ADAPTER_TYPE_C: {
-			u_int32_t rid0=PCIR_BAR(1);
+			u_int32_t rid0 = PCIR_BAR(1);
+			vm_offset_t	mem_base0;
+
+			acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
+			if(acb->sys_res_arcmsr[0] == NULL) {
+				arcmsr_free_resource(acb);
+				kprintf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
+				return ENOMEM;
+			}
+			if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
+				arcmsr_free_resource(acb);
+				kprintf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
+				return ENXIO;
+			}
+			mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
+			if(mem_base0 == 0) {
+				arcmsr_free_resource(acb);
+				kprintf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
+				return ENXIO;
+			}
+			acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
+			acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
+			acb->pmu = (struct MessageUnit_UNION *)mem_base0;
+		}
+		break;
+	case ACB_ADAPTER_TYPE_D: {
+			struct HBD_MessageUnit0 *phbdmu;
+			u_int32_t rid0 = PCIR_BAR(0);
 			vm_offset_t	mem_base0;
 
-			acb->sys_res_arcmsr[0]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
+			acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE);
 			if(acb->sys_res_arcmsr[0] == NULL) {
 				arcmsr_free_resource(acb);
 				kprintf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
@@ -3491,15 +4112,17 @@ static u_int32_t arcmsr_initialize(device_t dev)
 				kprintf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
 				return ENXIO;
 			}
-			mem_base0=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
-			if(mem_base0==0) {
+			mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
+			if(mem_base0 == 0) {
 				arcmsr_free_resource(acb);
 				kprintf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
 				return ENXIO;
 			}
-			acb->btag[0]=rman_get_bustag(acb->sys_res_arcmsr[0]);
-			acb->bhandle[0]=rman_get_bushandle(acb->sys_res_arcmsr[0]);
-			acb->pmu=(struct MessageUnit_UNION *)mem_base0;
+			acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
+			acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
+			acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
+			phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
+			phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
 		}
 		break;
 	}
@@ -3515,9 +4138,9 @@ static u_int32_t arcmsr_initialize(device_t dev)
 	** init raid volume state
 	********************************************************************
 	*/
-	for(i=0;i<ARCMSR_MAX_TARGETID;i++) {
-		for(j=0;j<ARCMSR_MAX_TARGETLUN;j++) {
-			acb->devstate[i][j]=ARECA_RAID_GONE;
+	for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
+		for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
+			acb->devstate[i][j] = ARECA_RAID_GONE;
 		}
 	}
 	arcmsr_iop_init(acb);
@@ -3541,63 +4164,63 @@ static int arcmsr_attach(device_t dev)
 		kprintf("arcmsr%d: cannot allocate softc\n", unit);
 		return (ENOMEM);
 	}
-	ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr Q buffer lock");
+	arcmsr_mutex_init(acb);
+	acb->pci_dev = dev;
+	acb->pci_unit = unit;
 	if(arcmsr_initialize(dev)) {
 		kprintf("arcmsr%d: initialize failure!\n", unit);
-		ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
+		arcmsr_mutex_destroy(acb);
 		return ENXIO;
 	}
 	/* After setting up the adapter, map our interrupt */
 	rid=0;
 	acb->irq_type = pci_alloc_1intr(dev, arcmsr_msi_enable, &rid,
 	    &irq_flags);
-	irqres=bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
+	irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
 	    irq_flags);
 	if(irqres == NULL ||
 		bus_setup_intr(dev, irqres, INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih, NULL)) {
 		arcmsr_free_resource(acb);
-		ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
+		arcmsr_mutex_destroy(acb);
 		kprintf("arcmsr%d: unable to register interrupt handler!\n", unit);
 		return ENXIO;
 	}
-	acb->irqres=irqres;
-	acb->pci_dev=dev;
-	acb->pci_unit=unit;
+	acb->irqres = irqres;
 	/*
 	 * Now let the CAM generic SCSI layer find the SCSI devices on
 	 * the bus *  start queue to reset to the idle loop. *
 	 * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
 	 * max_sim_transactions
 	*/
-	devq=cam_simq_alloc(ARCMSR_MAX_START_JOB);
+	devq = cam_simq_alloc(acb->maxOutstanding);
 	if(devq == NULL) {
 	    arcmsr_free_resource(acb);
 		bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
 		if (acb->irq_type == PCI_INTR_TYPE_MSI)
 			pci_release_msi(dev);
-		ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
+		arcmsr_mutex_destroy(acb);
 		kprintf("arcmsr%d: cam_simq_alloc failure!\n", unit);
 		return ENXIO;
 	}
-	acb->psim=cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->qbuffer_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
+	acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
 	cam_simq_release(devq);
 	if(acb->psim == NULL) {
 		arcmsr_free_resource(acb);
 		bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
 		if (acb->irq_type == PCI_INTR_TYPE_MSI)
 			pci_release_msi(dev);
-		ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
+		arcmsr_mutex_destroy(acb);
 		kprintf("arcmsr%d: cam_sim_alloc failure!\n", unit);
 		return ENXIO;
 	}
-	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 	if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
 		arcmsr_free_resource(acb);
 		bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
 		if (acb->irq_type == PCI_INTR_TYPE_MSI)
 			pci_release_msi(dev);
 		cam_sim_free(acb->psim);
-		ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
+		arcmsr_mutex_destroy(acb);
 		kprintf("arcmsr%d: xpt_bus_register failure!\n", unit);
 		return ENXIO;
 	}
@@ -3608,7 +4231,7 @@ static int arcmsr_attach(device_t dev)
 			pci_release_msi(dev);
 		xpt_bus_deregister(cam_sim_path(acb->psim));
 		cam_sim_free(acb->psim);
-		ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
+		arcmsr_mutex_destroy(acb);
 		kprintf("arcmsr%d: xpt_create_path failure!\n", unit);
 		return ENXIO;
 	}
@@ -3616,16 +4239,16 @@ static int arcmsr_attach(device_t dev)
 	****************************************************
 	*/
 	xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
-	csa.ccb_h.func_code=XPT_SASYNC_CB;
-	csa.event_enable=AC_FOUND_DEVICE|AC_LOST_DEVICE;
-	csa.callback=arcmsr_async;
-	csa.callback_arg=acb->psim;
+	csa.ccb_h.func_code = XPT_SASYNC_CB;
+	csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
+	csa.callback = arcmsr_async;
+	csa.callback_arg = acb->psim;
 	xpt_action((union ccb *)&csa);
-	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 	/* Create the control device.  */
-	acb->ioctl_dev=make_dev(&arcmsr_ops, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
+	acb->ioctl_dev = make_dev(&arcmsr_ops, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
 
-	acb->ioctl_dev->si_drv1=acb;
+	acb->ioctl_dev->si_drv1 = acb;
 	(void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
 	arcmsr_callout_init(&acb->devmap_callout);
 	callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
@@ -3639,15 +4262,17 @@ static int arcmsr_attach(device_t dev)
 static int arcmsr_probe(device_t dev)
 {
 	u_int32_t id;
+	u_int16_t sub_device_id;
 	static char buf[256];
-	char x_type[]={"X-TYPE"};
+	char x_type[]={"unknown"};
 	char *type;
 	int raid6 = 1;
 
 	if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
 		return (ENXIO);
 	}
-	switch(id=pci_get_devid(dev)) {
+	sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
+	switch(id = pci_get_devid(dev)) {
 	case PCIDevVenIDARC1110:
 	case PCIDevVenIDARC1200:
 	case PCIDevVenIDARC1201:
@@ -3665,7 +4290,7 @@ static int arcmsr_probe(device_t dev)
 	case PCIDevVenIDARC1261:
 	case PCIDevVenIDARC1270:
 	case PCIDevVenIDARC1280:
-		type = "SATA";
+		type = "SATA 3G";
 		break;
 	case PCIDevVenIDARC1212:
 	case PCIDevVenIDARC1222:
@@ -3679,16 +4304,24 @@ static int arcmsr_probe(device_t dev)
 	case PCIDevVenIDARC1882:
 	case PCIDevVenIDARC1213:
 	case PCIDevVenIDARC1223:
-		type = "SAS 6G";
+		if (sub_device_id == ARECA_SUB_DEV_ID_1883)
+			type = "SAS 12G";
+		else
+			type = "SAS 6G";
 		arcmsr_msi_enable = 0;
 		break;
+	case PCIDevVenIDARC1214:
+		type = "SATA 6G";
+		break;
 	default:
 		type = x_type;
+		raid6 = 0;
 		break;
 	}
 	if(type == x_type)
 		return(ENXIO);
-	ksprintf(buf, "Areca %s Host Adapter RAID Controller%s", type, raid6 ? " (RAID6 capable)" : "");
+	ksprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
+		type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
 	device_set_desc_copy(dev, buf);
 	return (BUS_PROBE_DEFAULT);
 }
@@ -3703,7 +4336,7 @@ static int arcmsr_shutdown(device_t dev)
 	struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
 
 	/* stop adapter background rebuild */
-	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 	/* disable all outbound interrupt */
 	arcmsr_disable_allintr(acb);
 	arcmsr_stop_adapter_bgrb(acb);
@@ -3711,28 +4344,26 @@ static int arcmsr_shutdown(device_t dev)
 	/* abort all outstanding command */
 	acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
 	acb->acb_flags &= ~ACB_F_IOP_INITED;
-	if(acb->srboutstandingcount!=0) {
+	if(acb->srboutstandingcount != 0) {
 		/*clear and abort all outbound posted Q*/
 		arcmsr_done4abort_postqueue(acb);
 		/* talk to iop 331 outstanding command aborted*/
 		arcmsr_abort_allcmd(acb);
-		for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) {
-			srb=acb->psrb_pool[i];
-			if(srb->srb_state==ARCMSR_SRB_START) {
-				srb->srb_state=ARCMSR_SRB_ABORTED;
+		for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
+			srb = acb->psrb_pool[i];
+			if(srb->srb_state == ARCMSR_SRB_START) {
+				srb->srb_state = ARCMSR_SRB_ABORTED;
 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 				arcmsr_srb_complete(srb, 1);
 			}
 		}
 	}
-	acb->srboutstandingcount=0;
-	acb->workingsrb_doneindex=0;
-	acb->workingsrb_startindex=0;
-#ifdef ARCMSR_DEBUG1
+	acb->srboutstandingcount = 0;
+	acb->workingsrb_doneindex = 0;
+	acb->workingsrb_startindex = 0;
 	acb->pktRequestCount = 0;
 	acb->pktReturnCount = 0;
-#endif
-	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 	return (0);
 }
 /*
@@ -3754,13 +4385,13 @@ static int arcmsr_detach(device_t dev)
 	bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
 	if (acb->irq_type == PCI_INTR_TYPE_MSI)
 		pci_release_msi(dev);
-	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
+	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 	xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
 	xpt_free_path(acb->ppath);
 	xpt_bus_deregister(cam_sim_path(acb->psim));
 	cam_sim_free(acb->psim);
-	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
-	ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
+	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
+	arcmsr_mutex_destroy(acb);
 	return (0);
 }
 
@@ -3769,9 +4400,9 @@ static void arcmsr_dump_data(struct AdapterControlBlock *acb)
 {
 	if((acb->pktRequestCount - acb->pktReturnCount) == 0)
 		return;
-	printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
-	printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
-	printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
-	printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
+	kprintf("Command Request Count   =0x%x\n",acb->pktRequestCount);
+	kprintf("Command Return Count    =0x%x\n",acb->pktReturnCount);
+	kprintf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
+	kprintf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
 }
 #endif
diff --git a/sys/dev/raid/arcmsr/arcmsr.h b/sys/dev/raid/arcmsr/arcmsr.h
index ed91264..45edfff 100644
--- a/sys/dev/raid/arcmsr/arcmsr.h
+++ b/sys/dev/raid/arcmsr/arcmsr.h
@@ -1,17 +1,14 @@
 /*
-***********************************************************************************************
-**        O.S   : FreeBSD
+********************************************************************************
+**        OS    : FreeBSD
 **   FILE NAME  : arcmsr.h
 **        BY    : Erich Chen, Ching Huang
-**   Description: SCSI RAID Device Driver for
-**                ARECA SATA/SAS RAID HOST Adapter
-**                [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set]
-***********************************************************************************************
-************************************************************************
-** Copyright (C) 2002 - 2010, Areca Technology Corporation All rights reserved.
-**
-**     Web site: www.areca.com.tw
-**       E-mail: erich@areca.com.tw; ching2048@areca.com.tw
+**   Description: SCSI RAID Device Driver for 
+**                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
+**                SATA/SAS RAID HOST Adapter
+********************************************************************************
+********************************************************************************
+** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
 **
 ** Redistribution and use in source and binary forms,with or without
 ** modification,are permitted provided that the following conditions
@@ -35,27 +32,28 @@
 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **************************************************************************
-* $FreeBSD: src/sys/dev/arcmsr/arcmsr.h,v 1.10 2012/09/04 05:15:54 delphij Exp $
+* $FreeBSD: head/sys/dev/arcmsr/arcmsr.h 259565 2013-12-18 19:25:40Z delphij $
 */
 
 #include <sys/ioccom.h>
 
-#define ARCMSR_SCSI_INITIATOR_ID                                              255
-#define ARCMSR_DEV_SECTOR_SIZE                                                512
-#define ARCMSR_MAX_XFER_SECTORS                                              4096
-#define ARCMSR_MAX_TARGETID                                                    17 /*16 max target id + 1*/
-#define ARCMSR_MAX_TARGETLUN                                                    8 /*8*/
-#define ARCMSR_MAX_CHIPTYPE_NUM                                                 4
-#define ARCMSR_MAX_OUTSTANDING_CMD                                            256
-#define ARCMSR_MAX_START_JOB                                                  257
-#define ARCMSR_MAX_CMD_PERLUN                          ARCMSR_MAX_OUTSTANDING_CMD
-#define ARCMSR_MAX_FREESRB_NUM				384
-#define ARCMSR_MAX_QBUFFER                                                   4096 /* ioctl QBUFFER */
-#define ARCMSR_MAX_SG_ENTRIES                                                  38 /* max 38*/
-#define ARCMSR_MAX_ADAPTER                                                      4
-#define ARCMSR_RELEASE_SIMQ_LEVEL                                             230
-#define ARCMSR_MAX_HBB_POSTQUEUE                                              264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
-#define	ARCMSR_TIMEOUT_DELAY				60 /* in sec */
+#define ARCMSR_SCSI_INITIATOR_ID	255
+#define ARCMSR_DEV_SECTOR_SIZE		512
+#define ARCMSR_MAX_XFER_SECTORS		4096
+#define ARCMSR_MAX_TARGETID		17	/*16 max target id + 1*/
+#define ARCMSR_MAX_TARGETLUN		8	/*8*/
+#define ARCMSR_MAX_CHIPTYPE_NUM		4
+#define ARCMSR_MAX_OUTSTANDING_CMD	256
+#define ARCMSR_MAX_START_JOB		256
+#define ARCMSR_MAX_CMD_PERLUN		ARCMSR_MAX_OUTSTANDING_CMD
+#define ARCMSR_MAX_FREESRB_NUM		384
+#define ARCMSR_MAX_QBUFFER		4096	/* ioctl QBUFFER */
+#define ARCMSR_MAX_SG_ENTRIES		38	/* max 38*/
+#define ARCMSR_MAX_ADAPTER		4
+#define ARCMSR_RELEASE_SIMQ_LEVEL	230
+#define ARCMSR_MAX_HBB_POSTQUEUE	264	/* (ARCMSR_MAX_OUTSTANDING_CMD+8) */
+#define ARCMSR_MAX_HBD_POSTQUEUE	256
+#define	ARCMSR_TIMEOUT_DELAY		60	/* in sec */
 /*
 *********************************************************************
 */
@@ -72,37 +70,48 @@
 #ifndef offsetof
 	#define offsetof(type, member)  ((size_t)(&((type *)0)->member))
 #endif
+
+#define ARCMSR_LOCK_INIT(l, s)	lockinit(l, s, 0, LK_CANRECURSE)
+#define ARCMSR_LOCK_DESTROY(l)	lockuninit(l)
+#define ARCMSR_LOCK_ACQUIRE(l)	lockmgr(l, LK_EXCLUSIVE)
+#define ARCMSR_LOCK_RELEASE(l)	lockmgr(l, LK_RELEASE)
+#define ARCMSR_LOCK_TRY(l)	lockmgr(&l, LK_EXCLUSIVE|LK_NOWAIT)
+#define arcmsr_htole32(x)	htole32(x)
+typedef struct lock		arcmsr_lock_t;
+
 /*
 **********************************************************************************
 **
 **********************************************************************************
 */
-#define PCI_VENDOR_ID_ARECA                                                0x17D3 /* Vendor ID	*/
-#define PCI_DEVICE_ID_ARECA_1110                                           0x1110 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1120                                           0x1120 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1130                                           0x1130 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1160                                           0x1160 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1170                                           0x1170 /* Device ID	*/
+#define PCI_VENDOR_ID_ARECA		0x17D3 /* Vendor ID	*/
+#define PCI_DEVICE_ID_ARECA_1110        0x1110 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1120        0x1120 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1130        0x1130 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1160        0x1160 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1170        0x1170 /* Device ID	*/
 #define PCI_DEVICE_ID_ARECA_1200        0x1200 /* Device ID	*/
 #define PCI_DEVICE_ID_ARECA_1201        0x1201 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1210                                           0x1210 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1210        0x1210 /* Device ID	*/
 #define PCI_DEVICE_ID_ARECA_1212        0x1212 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1220                                           0x1220 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1214        0x1214 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1220        0x1220 /* Device ID	*/
 #define PCI_DEVICE_ID_ARECA_1222        0x1222 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1230                                           0x1230 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1230        0x1230 /* Device ID	*/
 #define PCI_DEVICE_ID_ARECA_1231        0x1231 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1260                                           0x1260 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1260        0x1260 /* Device ID	*/
 #define PCI_DEVICE_ID_ARECA_1261        0x1261 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1270                                           0x1270 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1280                                           0x1280 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1380                                           0x1380 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1381                                           0x1381 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1680                                           0x1680 /* Device ID	*/
-#define PCI_DEVICE_ID_ARECA_1681                                           0x1681 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1270        0x1270 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1280        0x1280 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1380        0x1380 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1381        0x1381 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1680        0x1680 /* Device ID	*/
+#define PCI_DEVICE_ID_ARECA_1681        0x1681 /* Device ID	*/
 #define PCI_DEVICE_ID_ARECA_1880        0x1880 /* Device ID	*/
 
 #define ARECA_SUB_DEV_ID_1880	0x1880 /* Subsystem Device ID	*/
 #define ARECA_SUB_DEV_ID_1882	0x1882 /* Subsystem Device ID	*/
+#define ARECA_SUB_DEV_ID_1883	0x1883 /* Subsystem Device ID	*/
 #define ARECA_SUB_DEV_ID_1212	0x1212 /* Subsystem Device ID	*/
 #define ARECA_SUB_DEV_ID_1213	0x1213 /* Subsystem Device ID	*/
 #define ARECA_SUB_DEV_ID_1222	0x1222 /* Subsystem Device ID	*/
@@ -118,6 +127,7 @@
 #define PCIDevVenIDARC1210              0x121017D3 /* Vendor Device ID	*/
 #define PCIDevVenIDARC1212              0x121217D3 /* Vendor Device ID	*/
 #define PCIDevVenIDARC1213              0x121317D3 /* Vendor Device ID	*/
+#define PCIDevVenIDARC1214              0x121417D3 /* Vendor Device ID	*/
 #define PCIDevVenIDARC1220              0x122017D3 /* Vendor Device ID	*/
 #define PCIDevVenIDARC1222              0x122217D3 /* Vendor Device ID	*/
 #define PCIDevVenIDARC1223              0x122317D3 /* Vendor Device ID	*/
@@ -139,35 +149,41 @@
 	#define	PCIR_BAR(x)	(PCIR_BARS + (x) * 4)
 #endif
 
-#define PCI_BASE_ADDR0                                               0x10
-#define PCI_BASE_ADDR1                                               0x14
-#define PCI_BASE_ADDR2                                               0x18
-#define PCI_BASE_ADDR3                                               0x1C
-#define PCI_BASE_ADDR4                                               0x20
-#define PCI_BASE_ADDR5                                               0x24
+#define PCI_BASE_ADDR0                  0x10
+#define PCI_BASE_ADDR1                  0x14
+#define PCI_BASE_ADDR2                  0x18
+#define PCI_BASE_ADDR3                  0x1C
+#define PCI_BASE_ADDR4                  0x20
+#define PCI_BASE_ADDR5                  0x24
 /*
 **********************************************************************************
 **
 **********************************************************************************
 */
-#define ARCMSR_SCSICMD_IOCTL                                         0x77
-#define ARCMSR_CDEVSW_IOCTL                                          0x88
-#define ARCMSR_MESSAGE_FAIL                                          0x0001
-#define	ARCMSR_MESSAGE_SUCCESS                                       0x0000
+#define ARCMSR_SCSICMD_IOCTL            0x77
+#define ARCMSR_CDEVSW_IOCTL             0x88
+#define ARCMSR_MESSAGE_FAIL             0x0001
+#define	ARCMSR_MESSAGE_SUCCESS          0x0000
 /*
 **********************************************************************************
 **
 **********************************************************************************
 */
-#define arcmsr_ccbsrb_ptr                  							spriv_ptr0
-#define arcmsr_ccbacb_ptr                  							spriv_ptr1
-#define dma_addr_hi32(addr)                							(u_int32_t) ((addr>>16)>>16)
-#define dma_addr_lo32(addr)                							(u_int32_t) (addr & 0xffffffff)
-#define get_min(x,y)            ((x) < (y) ? (x) : (y))
-#define get_max(x,y)            ((x) < (y) ? (y) : (x))
+#define arcmsr_ccbsrb_ptr	spriv_ptr0
+#define arcmsr_ccbacb_ptr	spriv_ptr1
+#define dma_addr_hi32(addr)	(u_int32_t) ((addr>>16)>>16)
+#define dma_addr_lo32(addr)	(u_int32_t) (addr & 0xffffffff)
+#define get_min(x,y)		((x) < (y) ? (x) : (y))
+#define get_max(x,y)		((x) < (y) ? (y) : (x))
+/*
+**************************************************************************
+**************************************************************************
+*/
+#define CHIP_REG_READ32(s, b, r)	bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r))
+#define CHIP_REG_WRITE32(s, b, r, d)	bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d)
 /*
 **********************************************************************************
-**
+**    IOCTL CONTROL Mail Box
 **********************************************************************************
 */
 struct CMD_MESSAGE {
@@ -187,17 +203,17 @@ struct CMD_MESSAGE_FIELD {
 /************************************************************************/
 /************************************************************************/
 
-#define ARCMSR_IOP_ERROR_ILLEGALPCI            	0x0001
-#define ARCMSR_IOP_ERROR_VENDORID              	0x0002
-#define ARCMSR_IOP_ERROR_DEVICEID              	0x0002
-#define ARCMSR_IOP_ERROR_ILLEGALCDB           	0x0003
-#define ARCMSR_IOP_ERROR_UNKNOW_CDBERR        	0x0004
-#define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE    	0x0005
-#define ARCMSR_SYS_ERROR_MEMORY_CROSS4G     	0x0006
-#define ARCMSR_SYS_ERROR_MEMORY_LACK        	0x0007
-#define ARCMSR_SYS_ERROR_MEMORY_RANGE           0x0008
-#define ARCMSR_SYS_ERROR_DEVICE_BASE            0x0009
-#define ARCMSR_SYS_ERROR_PORT_VALIDATE          0x000A
+#define ARCMSR_IOP_ERROR_ILLEGALPCI		0x0001
+#define ARCMSR_IOP_ERROR_VENDORID		0x0002
+#define ARCMSR_IOP_ERROR_DEVICEID		0x0002
+#define ARCMSR_IOP_ERROR_ILLEGALCDB		0x0003
+#define ARCMSR_IOP_ERROR_UNKNOW_CDBERR		0x0004
+#define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE	0x0005
+#define ARCMSR_SYS_ERROR_MEMORY_CROSS4G		0x0006
+#define ARCMSR_SYS_ERROR_MEMORY_LACK		0x0007
+#define ARCMSR_SYS_ERROR_MEMORY_RANGE		0x0008
+#define ARCMSR_SYS_ERROR_DEVICE_BASE		0x0009
+#define ARCMSR_SYS_ERROR_PORT_VALIDATE		0x000A
 
 /*DeviceType*/
 #define ARECA_SATA_RAID                      	0x90000000
@@ -214,7 +230,7 @@ struct CMD_MESSAGE_FIELD {
 #define FUNCTION_FLUSH_ADAPTER_CACHE           	0x0809
 /*
 ************************************************************************
-**        IOCTL CONTROL CODE
+**      IOCTL CONTROL CODE
 ************************************************************************
 */
 /* ARECA IO CONTROL CODE*/
@@ -224,16 +240,50 @@ struct CMD_MESSAGE_FIELD {
 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER          	_IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD)
 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER        	_IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD)
 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F   	_IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD)
-#define ARCMSR_MESSAGE_SAY_HELLO               	_IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD)
+#define ARCMSR_MESSAGE_SAY_HELLO               	_IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 
 #define ARCMSR_MESSAGE_SAY_GOODBYE              _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD)
 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE      _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD)
 
 /* ARECA IOCTL ReturnCode */
-#define ARCMSR_MESSAGE_RETURNCODE_OK              0x00000001
-#define ARCMSR_MESSAGE_RETURNCODE_ERROR           0x00000006
-#define ARCMSR_MESSAGE_RETURNCODE_3F              0x0000003F
-#define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON		0x00000088
-/*
+#define ARCMSR_MESSAGE_RETURNCODE_OK		0x00000001
+#define ARCMSR_MESSAGE_RETURNCODE_ERROR		0x00000006
+#define ARCMSR_MESSAGE_RETURNCODE_3F		0x0000003F
+#define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON	0x00000088
+/* 
+************************************************************************
+**                SPEC. for Areca HBA adapter
+************************************************************************
+*/
+/* signature of set and get firmware config */
+#define ARCMSR_SIGNATURE_GET_CONFIG		0x87974060
+#define ARCMSR_SIGNATURE_SET_CONFIG		0x87974063
+/* message code of inbound message register */
+#define ARCMSR_INBOUND_MESG0_NOP		0x00000000
+#define ARCMSR_INBOUND_MESG0_GET_CONFIG		0x00000001
+#define ARCMSR_INBOUND_MESG0_SET_CONFIG		0x00000002
+#define ARCMSR_INBOUND_MESG0_ABORT_CMD		0x00000003
+#define ARCMSR_INBOUND_MESG0_STOP_BGRB		0x00000004
+#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE	0x00000005
+#define ARCMSR_INBOUND_MESG0_START_BGRB		0x00000006
+#define ARCMSR_INBOUND_MESG0_CHK331PENDING	0x00000007
+#define ARCMSR_INBOUND_MESG0_SYNC_TIMER		0x00000008
+/* doorbell interrupt generator */
+#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK	0x00000001
+#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK	0x00000002
+#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK	0x00000001
+#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK	0x00000002
+/* srb areca cdb flag */
+#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE		0x80000000
+#define ARCMSR_SRBPOST_FLAG_IAM_BIOS		0x40000000
+#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS		0x40000000
+#define ARCMSR_SRBREPLY_FLAG_ERROR		0x10000000
+#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0        0x10000000
+#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1	0x00000001
+/* outbound firmware ok */
+#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK	0x80000000
+
+#define ARCMSR_ARC1680_BUS_RESET		0x00000003
+/* 
 ************************************************************************
 **                SPEC. for Areca HBB adapter
 ************************************************************************
@@ -250,20 +300,20 @@ struct CMD_MESSAGE_FIELD {
 #define ARCMSR_IOP2DRV_CDB_DONE                 0x00000004
 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE         0x00000008
 
-#define ARCMSR_DOORBELL_HANDLE_INT		        0x0000000F
+#define ARCMSR_DOORBELL_HANDLE_INT		0x0000000F
 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN       0xFF00FFF0
 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN        0xFF00FFF7
 
-#define ARCMSR_MESSAGE_GET_CONFIG				0x00010008	/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_SET_CONFIG				0x00020008	/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_ABORT_CMD				0x00030008	/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_STOP_BGRB				0x00040008	/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_GET_CONFIG		0x00010008	/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_SET_CONFIG		0x00020008	/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_ABORT_CMD		0x00030008	/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_STOP_BGRB		0x00040008	/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
 #define ARCMSR_MESSAGE_FLUSH_CACHE              0x00050008	/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_START_BGRB				0x00060008	/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
-#define ARCMSR_MESSAGE_START_DRIVER_MODE		0x000E0008
-#define ARCMSR_MESSAGE_SET_POST_WINDOW		    0x000F0008
-#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE		    0x00100008
-#define ARCMSR_MESSAGE_FIRMWARE_OK				0x80000000	/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
+#define ARCMSR_MESSAGE_START_BGRB		0x00060008	/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
+#define ARCMSR_MESSAGE_START_DRIVER_MODE	0x000E0008	
+#define ARCMSR_MESSAGE_SET_POST_WINDOW		0x000F0008	
+#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE		0x00100008
+#define ARCMSR_MESSAGE_FIRMWARE_OK		0x80000000	/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
 
 #define ARCMSR_DRV2IOP_DATA_WRITE_OK            0x00000001	/* ioctl transfer */
 #define ARCMSR_DRV2IOP_DATA_READ_OK             0x00000002	/* ioctl transfer */
@@ -272,14 +322,14 @@ struct CMD_MESSAGE_FIELD {
 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT         0x00000010  /*  */
 
 /* data tunnel buffer between user space program and its firmware */
-#define ARCMSR_MSGCODE_RWBUFFER					0x0000fa00    /* iop msgcode_rwbuffer for message command */
-#define ARCMSR_IOCTL_WBUFFER					0x0000fe00    /* user space data to iop 128bytes */
-#define ARCMSR_IOCTL_RBUFFER					0x0000ff00    /* iop data to user space 128bytes */
-#define ARCMSR_HBB_BASE0_OFFSET					0x00000010
-#define ARCMSR_HBB_BASE1_OFFSET					0x00000018
-#define ARCMSR_HBB_BASE0_LEN					0x00021000
-#define ARCMSR_HBB_BASE1_LEN					0x00010000
-/*
+#define ARCMSR_MSGCODE_RWBUFFER			0x0000fa00    /* iop msgcode_rwbuffer for message command */
+#define ARCMSR_IOCTL_WBUFFER			0x0000fe00    /* user space data to iop 128bytes */
+#define ARCMSR_IOCTL_RBUFFER			0x0000ff00    /* iop data to user space 128bytes */
+#define ARCMSR_HBB_BASE0_OFFSET			0x00000010
+#define ARCMSR_HBB_BASE1_OFFSET			0x00000018
+#define ARCMSR_HBB_BASE0_LEN			0x00021000
+#define ARCMSR_HBB_BASE1_LEN			0x00010000
+/* 
 ************************************************************************
 **                SPEC. for Areca HBC adapter
 ************************************************************************
@@ -294,7 +344,7 @@ struct CMD_MESSAGE_FIELD {
 /* Host Interrupt Status */
 #define ARCMSR_HBCMU_UTILITY_A_ISR                      0x00000001
         /*
-        ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
+        ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 
         ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
         */
 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR              0x00000004
@@ -326,14 +376,310 @@ struct CMD_MESSAGE_FIELD {
 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR           0x00000004/*outbound DATA READ isr door bell clear*/
 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE                   0x00000008/*outbound message 0 ready*/
 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR    0x00000008/*outbound message cmd isr door bell clear*/
-#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK		                0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
+#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK		        0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/
+#define ARCMSR_HBCMU_RESET_ADAPTER				0x00000024
+#define ARCMSR_HBCMU_DiagWrite_ENABLE				0x00000080
+
+/* 
+************************************************************************
+**                SPEC. for Areca HBD adapter
+************************************************************************
+*/
+#define ARCMSR_HBDMU_CHIP_ID				0x00004
+#define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION		0x00008
+#define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK		0x00034
+#define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS		0x00200
+#define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE		0x0020C
+#define ARCMSR_HBDMU_INBOUND_MESSAGE0			0x00400
+#define ARCMSR_HBDMU_INBOUND_MESSAGE1			0x00404
+#define ARCMSR_HBDMU_OUTBOUND_MESSAGE0			0x00420
+#define ARCMSR_HBDMU_OUTBOUND_MESSAGE1			0x00424
+#define ARCMSR_HBDMU_INBOUND_DOORBELL			0x00460
+#define ARCMSR_HBDMU_OUTBOUND_DOORBELL			0x00480
+#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE		0x00484
+#define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW		0x01000
+#define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH		0x01004
+#define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER		0x01018
+#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW		0x01060
+#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH		0x01064
+#define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER		0x0106C
+#define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER		0x01070
+#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE		0x01088
+#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE		0x0108C
+
+#define ARCMSR_HBDMU_MESSAGE_WBUFFER			0x02000
+#define ARCMSR_HBDMU_MESSAGE_RBUFFER			0x02100
+#define ARCMSR_HBDMU_MESSAGE_RWBUFFER			0x02200
+
+#define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL		16
+#define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE			20
+
+/* Host Interrupt Mask */
+#define ARCMSR_HBDMU_ALL_INT_ENABLE			0x00001010	/* enable all ISR */
+#define ARCMSR_HBDMU_ALL_INT_DISABLE			0x00000000	/* disable all ISR */
+
+/* Host Interrupt Status */
+#define ARCMSR_HBDMU_OUTBOUND_INT			0x00001010
+#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT		0x00001000
+#define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT		0x00000010
+
+/* DoorBell*/
+#define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY		0x00000001
+#define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ		0x00000002
+
+#define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK		0x00000001
+#define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK		0x00000002
+
+/*outbound message 0 ready*/
+#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE		0x02000000
+
+#define ARCMSR_HBDMU_F0_DOORBELL_CAUSE			0x02000003
+
+/*outbound message cmd isr door bell clear*/
+#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR	0x02000000
+
+/*outbound list */
+#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT		0x00000001
+#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR	0x00000001
+
+/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
+#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK		0x80000000
+/*
+*********************************************************************
+** Message Unit structure
+*********************************************************************
+*/
+struct HBA_MessageUnit
+{
+	u_int32_t	resrved0[4];		/*0000 000F*/
+	u_int32_t	inbound_msgaddr0;	/*0010 0013*/
+	u_int32_t	inbound_msgaddr1;	/*0014 0017*/
+	u_int32_t	outbound_msgaddr0;	/*0018 001B*/
+	u_int32_t	outbound_msgaddr1;	/*001C 001F*/
+	u_int32_t	inbound_doorbell;	/*0020 0023*/
+	u_int32_t	inbound_intstatus;	/*0024 0027*/
+	u_int32_t	inbound_intmask;	/*0028 002B*/
+	u_int32_t	outbound_doorbell;	/*002C 002F*/
+	u_int32_t	outbound_intstatus;	/*0030 0033*/
+	u_int32_t	outbound_intmask;	/*0034 0037*/
+	u_int32_t	reserved1[2];		/*0038 003F*/
+	u_int32_t	inbound_queueport;	/*0040 0043*/
+	u_int32_t	outbound_queueport;	/*0044 0047*/
+	u_int32_t	reserved2[2];		/*0048 004F*/
+	u_int32_t	reserved3[492];		/*0050 07FF ......local_buffer 492*/
+	u_int32_t	reserved4[128];		/*0800 09FF                    128*/
+	u_int32_t	msgcode_rwbuffer[256];	/*0a00 0DFF                    256*/
+	u_int32_t	message_wbuffer[32];	/*0E00 0E7F                     32*/
+	u_int32_t	reserved5[32];		/*0E80 0EFF                     32*/
+	u_int32_t	message_rbuffer[32];	/*0F00 0F7F                     32*/
+	u_int32_t	reserved6[32];		/*0F80 0FFF                     32*/
+};
+/*
+*********************************************************************
+** 
+*********************************************************************
+*/
+struct HBB_DOORBELL
+{
+	u_int8_t	doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */
+	u_int32_t	drv2iop_doorbell;          /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
+	u_int32_t	drv2iop_doorbell_mask;     /*                  04,05,06,07: doorbell mask */
+	u_int32_t	iop2drv_doorbell;          /*                  08,09,10,11: window of "instruction flags" from iop to driver */
+	u_int32_t	iop2drv_doorbell_mask;     /*                  12,13,14,15: doorbell mask */
+};
+/*
+*********************************************************************
+** 
+*********************************************************************
+*/
+struct HBB_RWBUFFER
+{
+	u_int8_t	message_reserved0[ARCMSR_MSGCODE_RWBUFFER];   /*reserved */
+	u_int32_t	msgcode_rwbuffer[256];      /*offset 0x0000fa00:   0,   1,   2,   3,...,1023: message code read write 1024bytes */
+	u_int32_t	message_wbuffer[32];        /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
+	u_int32_t	message_reserved1[32];      /*                  1152,1153,1154,1155,...,1279: message reserved*/
+	u_int32_t	message_rbuffer[32];        /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 
+};
+/*
+*********************************************************************
+** 
+*********************************************************************
+*/
+struct HBB_MessageUnit
+{
+	u_int32_t		post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];       /* post queue buffer for iop */
+	u_int32_t		done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];       /* done queue buffer for iop */
+	int32_t			postq_index;                                  /* post queue index */
+	int32_t			doneq_index;								   /* done queue index */
+	struct HBB_DOORBELL    *hbb_doorbell;
+	struct HBB_RWBUFFER    *hbb_rwbuffer;
+};
 
 /*
+*********************************************************************
+** 
+*********************************************************************
+*/
+struct HBC_MessageUnit {
+	u_int32_t	message_unit_status;                        /*0000 0003*/
+	u_int32_t	slave_error_attribute;	                    /*0004 0007*/
+	u_int32_t	slave_error_address;	                    /*0008 000B*/
+	u_int32_t	posted_outbound_doorbell;	            /*000C 000F*/
+	u_int32_t	master_error_attribute;	                    /*0010 0013*/
+	u_int32_t	master_error_address_low;	            /*0014 0017*/
+	u_int32_t	master_error_address_high;	            /*0018 001B*/
+	u_int32_t	hcb_size;                                   /*001C 001F size of the PCIe window used for HCB_Mode accesses*/
+	u_int32_t	inbound_doorbell;	                    /*0020 0023*/
+	u_int32_t	diagnostic_rw_data;	                    /*0024 0027*/
+	u_int32_t	diagnostic_rw_address_low;	            /*0028 002B*/
+	u_int32_t	diagnostic_rw_address_high;	            /*002C 002F*/
+	u_int32_t	host_int_status;	                    /*0030 0033 host interrupt status*/
+	u_int32_t	host_int_mask;     	                    /*0034 0037 host interrupt mask*/
+	u_int32_t	dcr_data;	                            /*0038 003B*/
+	u_int32_t	dcr_address;                                /*003C 003F*/
+	u_int32_t	inbound_queueport;                          /*0040 0043 port32 host inbound queue port*/
+	u_int32_t	outbound_queueport;                         /*0044 0047 port32 host outbound queue port*/
+	u_int32_t	hcb_pci_address_low;                        /*0048 004B*/
+	u_int32_t	hcb_pci_address_high;                       /*004C 004F*/
+	u_int32_t	iop_int_status;                             /*0050 0053*/
+	u_int32_t	iop_int_mask;                               /*0054 0057*/
+	u_int32_t	iop_inbound_queue_port;                     /*0058 005B*/
+	u_int32_t	iop_outbound_queue_port;                    /*005C 005F*/
+	u_int32_t	inbound_free_list_index;                    /*0060 0063 inbound free list producer consumer index*/
+	u_int32_t	inbound_post_list_index;                    /*0064 0067 inbound post list producer consumer index*/
+	u_int32_t	outbound_free_list_index;                   /*0068 006B outbound free list producer consumer index*/
+	u_int32_t	outbound_post_list_index;                   /*006C 006F outbound post list producer consumer index*/
+	u_int32_t	inbound_doorbell_clear;                     /*0070 0073*/
+	u_int32_t	i2o_message_unit_control;                   /*0074 0077*/
+	u_int32_t	last_used_message_source_address_low;       /*0078 007B*/
+	u_int32_t	last_used_message_source_address_high;	    /*007C 007F*/
+	u_int32_t	pull_mode_data_byte_count[4];               /*0080 008F pull mode data byte count0..count7*/
+	u_int32_t	message_dest_address_index;                 /*0090 0093*/
+	u_int32_t	done_queue_not_empty_int_counter_timer;     /*0094 0097*/
+	u_int32_t	utility_A_int_counter_timer;                /*0098 009B*/
+	u_int32_t	outbound_doorbell;                          /*009C 009F*/
+	u_int32_t	outbound_doorbell_clear;                    /*00A0 00A3*/
+	u_int32_t	message_source_address_index;               /*00A4 00A7 message accelerator source address consumer producer index*/
+	u_int32_t	message_done_queue_index;                   /*00A8 00AB message accelerator completion queue consumer producer index*/
+	u_int32_t	reserved0;                                  /*00AC 00AF*/
+	u_int32_t	inbound_msgaddr0;                           /*00B0 00B3 scratchpad0*/
+	u_int32_t	inbound_msgaddr1;                           /*00B4 00B7 scratchpad1*/
+	u_int32_t	outbound_msgaddr0;                          /*00B8 00BB scratchpad2*/
+	u_int32_t	outbound_msgaddr1;                          /*00BC 00BF scratchpad3*/
+	u_int32_t	inbound_queueport_low;                      /*00C0 00C3 port64 host inbound queue port low*/
+	u_int32_t	inbound_queueport_high;                     /*00C4 00C7 port64 host inbound queue port high*/
+	u_int32_t	outbound_queueport_low;                     /*00C8 00CB port64 host outbound queue port low*/
+	u_int32_t	outbound_queueport_high;                    /*00CC 00CF port64 host outbound queue port high*/
+	u_int32_t	iop_inbound_queue_port_low;                 /*00D0 00D3*/
+	u_int32_t	iop_inbound_queue_port_high;                /*00D4 00D7*/
+	u_int32_t	iop_outbound_queue_port_low;                /*00D8 00DB*/
+	u_int32_t	iop_outbound_queue_port_high;               /*00DC 00DF*/
+	u_int32_t	message_dest_queue_port_low;                /*00E0 00E3 message accelerator destination queue port low*/
+	u_int32_t	message_dest_queue_port_high;               /*00E4 00E7 message accelerator destination queue port high*/
+	u_int32_t	last_used_message_dest_address_low;         /*00E8 00EB last used message accelerator destination address low*/
+	u_int32_t	last_used_message_dest_address_high;        /*00EC 00EF last used message accelerator destination address high*/
+	u_int32_t	message_done_queue_base_address_low;        /*00F0 00F3 message accelerator completion queue base address low*/
+	u_int32_t	message_done_queue_base_address_high;       /*00F4 00F7 message accelerator completion queue base address high*/
+	u_int32_t	host_diagnostic;                            /*00F8 00FB*/
+	u_int32_t	write_sequence;                             /*00FC 00FF*/
+	u_int32_t	reserved1[34];                              /*0100 0187*/
+	u_int32_t	reserved2[1950];                            /*0188 1FFF*/
+	u_int32_t	message_wbuffer[32];                        /*2000 207F*/
+	u_int32_t	reserved3[32];                              /*2080 20FF*/
+	u_int32_t	message_rbuffer[32];                        /*2100 217F*/
+	u_int32_t	reserved4[32];                              /*2180 21FF*/
+	u_int32_t	msgcode_rwbuffer[256];                      /*2200 23FF*/
+};
+/*
+*********************************************************************
+** 
+*********************************************************************
+*/
+struct InBound_SRB {
+	uint32_t addressLow; //pointer to SRB block
+	uint32_t addressHigh;
+	uint32_t length; // in DWORDs
+	uint32_t reserved0;
+};
+
+struct OutBound_SRB {
+	uint32_t addressLow; //pointer to SRB block
+	uint32_t addressHigh;
+};
+
+struct HBD_MessageUnit {
+	uint32_t reserved0;
+	uint32_t chip_id;			//0x0004
+	uint32_t cpu_mem_config;		//0x0008
+	uint32_t reserved1[10];			//0x000C
+	uint32_t i2o_host_interrupt_mask;	//0x0034
+	uint32_t reserved2[114];		//0x0038
+	uint32_t host_int_status;		//0x0200
+	uint32_t host_int_enable;		//0x0204
+	uint32_t reserved3[1];			//0x0208
+	uint32_t pcief0_int_enable;		//0x020C
+	uint32_t reserved4[124];		//0x0210
+	uint32_t inbound_msgaddr0;		//0x0400
+	uint32_t inbound_msgaddr1;		//0x0404
+	uint32_t reserved5[6];			//0x0408
+	uint32_t outbound_msgaddr0;		//0x0420
+	uint32_t outbound_msgaddr1;		//0x0424
+	uint32_t reserved6[14];			//0x0428
+	uint32_t inbound_doorbell;		//0x0460
+	uint32_t reserved7[7];			//0x0464
+	uint32_t outbound_doorbell;		//0x0480
+	uint32_t outbound_doorbell_enable;	//0x0484
+	uint32_t reserved8[734];		//0x0488
+	uint32_t inboundlist_base_low;		//0x1000
+	uint32_t inboundlist_base_high;		//0x1004
+	uint32_t reserved9[4];			//0x1008
+	uint32_t inboundlist_write_pointer;	//0x1018
+	uint32_t inboundlist_read_pointer;	//0x101C
+	uint32_t reserved10[16];		//0x1020
+	uint32_t outboundlist_base_low;		//0x1060
+	uint32_t outboundlist_base_high;	//0x1064
+	uint32_t reserved11;			//0x1068
+	uint32_t outboundlist_copy_pointer;	//0x106C
+	uint32_t outboundlist_read_pointer;	//0x1070 0x1072
+	uint32_t reserved12[5];			//0x1074
+	uint32_t outboundlist_interrupt_cause;	//0x1088
+	uint32_t outboundlist_interrupt_enable;	//0x108C
+	uint32_t reserved13[988];		//0x1090
+	uint32_t message_wbuffer[32];		//0x2000
+	uint32_t reserved14[32];		//0x2080
+	uint32_t message_rbuffer[32];		//0x2100
+	uint32_t reserved15[32];		//0x2180
+	uint32_t msgcode_rwbuffer[256];		//0x2200
+};
+
+struct HBD_MessageUnit0 {
+ 	struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE];
+   	struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1];
+	uint16_t postq_index;
+	uint16_t doneq_index;
+	struct HBD_MessageUnit	*phbdmu;
+};
+
+/*
+*********************************************************************
+** 
+*********************************************************************
+*/
+struct MessageUnit_UNION
+{
+	union	{
+		struct HBA_MessageUnit		hbamu;
+		struct HBB_MessageUnit		hbbmu;
+        	struct HBC_MessageUnit		hbcmu;
+        	struct HBD_MessageUnit0		hbdmu;
+	} muu;
+};
+/* 
 *************************************************************
-**   structure for holding DMA address data
+**   structure for holding DMA address data 
 *************************************************************
 */
-#define IS_SG64_ADDR                0x01000000 /* bit24 */
+#define IS_SG64_ADDR	0x01000000 /* bit24 */
 /*
 ************************************************************************************************
 **                            ARECA FIRMWARE SPEC
@@ -342,10 +688,10 @@ struct CMD_MESSAGE_FIELD {
 **		(All In/Out is in IOP331's view)
 **		1. Message 0 --> InitThread message and retrun code
 **		2. Doorbell is used for RS-232 emulation
-**				inDoorBell :    bit0 -- data in ready            (DRIVER DATA WRITE OK)
-**								bit1 -- data out has been read   (DRIVER DATA READ OK)
-**				outDooeBell:    bit0 -- data out ready           (IOP331 DATA WRITE OK)
-**								bit1 -- data in has been read    (IOP331 DATA READ OK)
+**			inDoorBell :    bit0 -- data in ready            (DRIVER DATA WRITE OK)
+**					bit1 -- data out has been read   (DRIVER DATA READ OK)
+**			outDooeBell:    bit0 -- data out ready           (IOP331 DATA WRITE OK)
+**					bit1 -- data in has been read    (IOP331 DATA READ OK)
 **		3. Index Memory Usage
 **			offset 0xf00 : for RS232 out (request buffer)
 **			offset 0xe00 : for RS232 in  (scratch buffer)
@@ -357,74 +703,74 @@ struct CMD_MESSAGE_FIELD {
 **			        Byte 4--127 : Max 124 bytes of data
 **		5. PostQ
 **		All SCSI Command must be sent through postQ:
-**		(inbound queue port)	Request frame must be 32 bytes aligned
-**            #   bit27--bit31 => flag for post ccb
-**			  #   bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
-**													bit31 : 0 : 256 bytes frame
-**															1 : 512 bytes frame
-**													bit30 : 0 : normal request
-**															1 : BIOS request
-**                                                  bit29 : reserved
-**                                                  bit28 : reserved
-**                                                  bit27 : reserved
+**		(inbound queue port)	Request frame must be 32 bytes aligned 
+**              	#   bit27--bit31 => flag for post ccb 
+**			#   bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb  
+**					bit31 : 0 : 256 bytes frame
+**						1 : 512 bytes frame
+**					bit30 : 0 : normal request
+**						1 : BIOS request
+**                                      bit29 : reserved
+**                                      bit28 : reserved
+**                                      bit27 : reserved
 **  -------------------------------------------------------------------------------
-**		(outbount queue port)	Request reply
-**            #   bit27--bit31 => flag for reply
-**			  #   bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
-**													bit31 : must be 0 (for this type of reply)
-**													bit30 : reserved for BIOS handshake
-**													bit29 : reserved
-**													bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
-**															1 : Error, error code in AdapStatus/DevStatus/SenseData
-**													bit27 : reserved
+**		(outbount queue port)	Request reply                          
+**              	#   bit27--bit31 => flag for reply
+**			#   bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 
+**			bit31 : must be 0 (for this type of reply)
+**			bit30 : reserved for BIOS handshake
+**			bit29 : reserved
+**			bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
+**				1 : Error, error code in AdapStatus/DevStatus/SenseData
+**			bit27 : reserved
 **		6. BIOS request
 **			All BIOS request is the same with request from PostQ
 **			Except :
 **				Request frame is sent from configuration space
-**								offset: 0x78 : Request Frame (bit30 == 1)
-**								offset: 0x18 : writeonly to generate IRQ to IOP331
+**					offset: 0x78 : Request Frame (bit30 == 1)
+**					offset: 0x18 : writeonly to generate IRQ to IOP331
 **				Completion of request:
-**				                      (bit30 == 0, bit28==err flag)
+**				        (bit30 == 0, bit28==err flag)
 **		7. Definition of SGL entry (structure)
 **		8. Message1 Out - Diag Status Code (????)
 **		9. Message0 message code :
 **			0x00 : NOP
 **			0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver)
-**												Signature             0x87974060(4)
-**												Request len           0x00000200(4)
-**												numbers of queue      0x00000100(4)
-**												SDRAM Size            0x00000100(4)-->256 MB
-**												IDE Channels          0x00000008(4)
-**												vendor                40 bytes char
-**												model                  8 bytes char
-**												FirmVer               16 bytes char
-**												Device Map            16 bytes char
-**
+**					Signature             0x87974060(4)
+**					Request len           0x00000200(4)
+**					numbers of queue      0x00000100(4)
+**					SDRAM Size            0x00000100(4)-->256 MB
+**					IDE Channels          0x00000008(4)
+**					vendor                40 bytes char
+**					model                  8 bytes char
+**					FirmVer               16 bytes char
+**					Device Map            16 bytes char
+**	
 **					FirmwareVersion DWORD <== Added for checking of new firmware capability
 **			0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
-**												Signature             0x87974063(4)
-**												UPPER32 of Request Frame  (4)-->Driver Only
+**					Signature             0x87974063(4)
+**					UPPER32 of Request Frame  (4)-->Driver Only
 **			0x03 : Reset (Abort all queued Command)
 **			0x04 : Stop Background Activity
 **			0x05 : Flush Cache
 **			0x06 : Start Background Activity (re-start if background is halted)
 **			0x07 : Check If Host Command Pending (Novell May Need This Function)
 **			0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331)
-**											byte 0 : 0xaa <-- signature
-**											byte 1 : 0x55 <-- signature
-**											byte 2 : year (04)
-**											byte 3 : month (1..12)
-**											byte 4 : date (1..31)
-**											byte 5 : hour (0..23)
-**											byte 6 : minute (0..59)
-**											byte 7 : second (0..59)
+**					byte 0 : 0xaa <-- signature
+**					byte 1 : 0x55 <-- signature
+**					byte 2 : year (04)
+**					byte 3 : month (1..12)
+**					byte 4 : date (1..31)
+**					byte 5 : hour (0..23)
+**					byte 6 : minute (0..59)
+**					byte 7 : second (0..59)
 **      *********************************************************************************
 **      Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter
 **      ==> Difference from IOP348
 **      <1> Message Register 0,1 (the same usage) Init Thread message and retrun code
 **           Inbound Message 0  (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP)
-**           Inbound Message 1  (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code
-**           Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code
+**           Inbound Message 1  (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 
+**           Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 
 **           Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver)
 **           <A> use doorbell to generate interrupt
 **
@@ -433,36 +779,36 @@ struct CMD_MESSAGE_FIELD {
 **
 **		        a. Message1: Out - Diag Status Code (????)
 **
-**		        b. Message0: message code
+**		        b. Message0: message code 
 **		        	    0x00 : NOP
 **		        	    0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver)
-**		        	    									Signature             0x87974060(4)
-**		        	    									Request len           0x00000200(4)
-**		        	    									numbers of queue      0x00000100(4)
-**		        	    									SDRAM Size            0x00000100(4)-->256 MB
-**		        	    									IDE Channels          0x00000008(4)
-**		        	    									vendor                40 bytes char
-**		        	    									model                  8 bytes char
-**		        	    									FirmVer               16 bytes char
-**                                      					Device Map            16 bytes char
-**                                      	                cfgVersion    ULONG <== Added for checking of new firmware capability
+**		        	    			Signature             0x87974060(4)
+**		        	    			Request len           0x00000200(4)
+**		        	    			numbers of queue      0x00000100(4)
+**		        	    			SDRAM Size            0x00000100(4)-->256 MB
+**		        	    			IDE Channels          0x00000008(4)
+**		        	    			vendor                40 bytes char
+**		        	    			model                  8 bytes char
+**		        	    			FirmVer               16 bytes char
+**                                         Device Map            16 bytes char
+**                                         cfgVersion    ULONG <== Added for checking of new firmware capability
 **		        	    0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP)
-**		        	    									Signature             0x87974063(4)
-**		        	    									UPPER32 of Request Frame  (4)-->Driver Only
+**		        	    			Signature             0x87974063(4)
+**		        	    			UPPER32 of Request Frame  (4)-->Driver Only
 **		        	    0x03 : Reset (Abort all queued Command)
 **		        	    0x04 : Stop Background Activity
 **		        	    0x05 : Flush Cache
 **		        	    0x06 : Start Background Activity (re-start if background is halted)
 **		        	    0x07 : Check If Host Command Pending (Novell May Need This Function)
 **		        	    0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP)
-**		        	            							byte 0 : 0xaa <-- signature
-**                                      					byte 1 : 0x55 <-- signature
-**		        	            							byte 2 : year (04)
-**		        	            							byte 3 : month (1..12)
-**		        	            							byte 4 : date (1..31)
-**		        	            							byte 5 : hour (0..23)
-**		        	            							byte 6 : minute (0..59)
-**		        	            							byte 7 : second (0..59)
+**		        	            		byte 0 : 0xaa <-- signature
+**                                      		byte 1 : 0x55 <-- signature
+**		        	            		byte 2 : year (04)
+**		        	            		byte 3 : month (1..12)
+**		        	            		byte 4 : date (1..31)
+**		        	            		byte 5 : hour (0..23)
+**		        	            		byte 6 : minute (0..59)
+**		        	            		byte 7 : second (0..59)
 **
 **      <2> Doorbell Register is used for RS-232 emulation
 **           <A> different clear register
@@ -527,13 +873,13 @@ struct CMD_MESSAGE_FIELD {
 **                      111: <= 0x0300 (reserved)
 **                  -----------------------------
 **                  if len > 0x300 the len always set as 0x300
-**                  -----------------------------
+**                  -----------------------------   
 **                  post addr = addr | ((len-1) >> 6) | 1
 **                  -----------------------------
-**                  page length in command buffer still required,
+**                  page length in command buffer still required, 
 **
-**                  if page length > 3,
-**                     firmware will assume more request data need to be retrieved
+**                  if page length > 3, 
+**                     firmware will assume more request data need to be retrieved 
 **
 **              <D> Outbound Posting
 **                  bit0:0 , no error, 1 with error, refer to status buffer
@@ -542,42 +888,12 @@ struct CMD_MESSAGE_FIELD {
 **                  bit3:0 , reserved (will be 0)
 **                  bit63-4: Completed command address
 **
-**              <E> BIOS support, no special support is required.
+**              <E> BIOS support, no special support is required. 
 **                  LSI2108 support I/O register
 **                  All driver functionality is supported through I/O address
 **
-**           For further spec, refer to
-**       \spec\lsi\2108 for Areca\2108\LSISAS2108_PG_NoEncryption.pdf : Chapter 8 (8-11/8-28)
-**       \spec\lsi\2108 for Areca\2108\SAS2108_RM_20.pdf              : for configuration space
 ************************************************************************************************
 */
-/* signature of set and get firmware config */
-#define ARCMSR_SIGNATURE_GET_CONFIG                   0x87974060
-#define ARCMSR_SIGNATURE_SET_CONFIG                   0x87974063
-/* message code of inbound message register */
-#define ARCMSR_INBOUND_MESG0_NOP                      0x00000000
-#define ARCMSR_INBOUND_MESG0_GET_CONFIG               0x00000001
-#define ARCMSR_INBOUND_MESG0_SET_CONFIG               0x00000002
-#define ARCMSR_INBOUND_MESG0_ABORT_CMD                0x00000003
-#define ARCMSR_INBOUND_MESG0_STOP_BGRB                0x00000004
-#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE              0x00000005
-#define ARCMSR_INBOUND_MESG0_START_BGRB               0x00000006
-#define ARCMSR_INBOUND_MESG0_CHK331PENDING            0x00000007
-#define ARCMSR_INBOUND_MESG0_SYNC_TIMER               0x00000008
-/* doorbell interrupt generator */
-#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK           0x00000001
-#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK            0x00000002
-#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK          0x00000001
-#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK           0x00000002
-/* srb areca cdb flag */
-#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE                 0x80000000
-#define ARCMSR_SRBPOST_FLAG_IAM_BIOS                  0x40000000
-#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS                 0x40000000
-#define ARCMSR_SRBREPLY_FLAG_ERROR                    0x10000000
-#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0        	0x10000000
-#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1			0x00000001
-/* outbound firmware ok */
-#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK             0x80000000
 /*
 **********************************
 **
@@ -585,21 +901,21 @@ struct CMD_MESSAGE_FIELD {
 */
 /* size 8 bytes */
 /* 32bit Scatter-Gather list */
-struct SG32ENTRY {                             /* length bit 24 == 0                      */
-    u_int32_t						length;    /* high 8 bit == flag,low 24 bit == length */
-    u_int32_t						address;
+struct SG32ENTRY {                 /* length bit 24 == 0 */
+	u_int32_t	length;    /* high 8 bit == flag,low 24 bit == length */
+	u_int32_t	address;
 };
 /* size 12 bytes */
 /* 64bit Scatter-Gather list */
-struct SG64ENTRY {                             /* length bit 24 == 1                      */
-	u_int32_t       				length;    /* high 8 bit == flag,low 24 bit == length */
-	u_int32_t       				address;
-	u_int32_t       				addresshigh;
+struct SG64ENTRY {                 /* length bit 24 == 1 */
+  	u_int32_t       length;    /* high 8 bit == flag,low 24 bit == length */
+   	u_int32_t       address; 
+   	u_int32_t       addresshigh;
 };
 struct SGENTRY_UNION {
 	union {
-		struct SG32ENTRY            sg32entry;   /* 30h   Scatter gather address  */
-		struct SG64ENTRY            sg64entry;   /* 30h                           */
+  		struct SG32ENTRY	sg32entry;   /* 30h   Scatter gather address  */
+  		struct SG64ENTRY	sg64entry;   /* 30h */
 	}u;
 };
 /*
@@ -609,9 +925,16 @@ struct SGENTRY_UNION {
 */
 struct QBUFFER {
 	u_int32_t     data_len;
-    u_int8_t      data[124];
+	u_int8_t      data[124];
 };
 /*
+**********************************
+*/
+typedef struct PHYS_ADDR64 {
+	u_int32_t	phyadd_low;
+	u_int32_t	phyadd_high;
+}PHYSADDR64;
+/*
 ************************************************************************************************
 **      FIRMWARE INFO
 ************************************************************************************************
@@ -622,23 +945,23 @@ struct QBUFFER {
 #define	ARCMSR_FW_CFGVER_OFFSET		25
 
 struct FIRMWARE_INFO {
-	u_int32_t      signature;                /*0,00-03*/
-	u_int32_t      request_len;              /*1,04-07*/
-	u_int32_t      numbers_queue;            /*2,08-11*/
-	u_int32_t      sdram_size;               /*3,12-15*/
-	u_int32_t      ide_channels;             /*4,16-19*/
-	char           vendor[40];               /*5,20-59*/
-	char           model[8];                 /*15,60-67*/
-	char           firmware_ver[16];         /*17,68-83*/
-	char           device_map[16];           /*21,84-99*/
-    u_int32_t      cfgVersion;          /*25,100-103 Added for checking of new firmware capability*/
-    char           cfgSerial[16];       /*26,104-119*/
-    u_int32_t      cfgPicStatus;        /*30,120-123*/
+	u_int32_t      signature;           /*0,00-03*/
+	u_int32_t      request_len;         /*1,04-07*/
+	u_int32_t      numbers_queue;       /*2,08-11*/
+	u_int32_t      sdram_size;          /*3,12-15*/
+	u_int32_t      ide_channels;        /*4,16-19*/
+	char           vendor[40];          /*5,20-59*/
+	char           model[8];            /*15,60-67*/
+	char           firmware_ver[16];    /*17,68-83*/
+	char           device_map[16];      /*21,84-99*/
+	u_int32_t      cfgVersion;          /*25,100-103 Added for checking of new firmware capability*/
+	char           cfgSerial[16];       /*26,104-119*/
+	u_int32_t      cfgPicStatus;        /*30,120-123*/
 };
 /*   (A) For cfgVersion in FIRMWARE_INFO
 **        if low BYTE (byte#0) >= 3 (version 3)
 **        then byte#1 report the capability of the firmware can xfer in a single request
-**
+**        
 **        byte#1
 **        0         256K
 **        1         512K
@@ -668,33 +991,43 @@ struct FIRMWARE_INFO {
 ************************************************************************************************
 */
 struct ARCMSR_CDB {
-	u_int8_t     						Bus;              /* 00h   should be 0            */
-	u_int8_t     						TargetID;         /* 01h   should be 0--15        */
-	u_int8_t     						LUN;              /* 02h   should be 0--7         */
-	u_int8_t     						Function;         /* 03h   should be 1            */
-
-	u_int8_t     						CdbLength;        /* 04h   not used now           */
-	u_int8_t     						sgcount;          /* 05h                          */
-	u_int8_t     						Flags;            /* 06h                          */
-#define ARCMSR_CDB_FLAG_SGL_BSIZE          0x01   /* bit 0: 0(256) / 1(512) bytes         */
-#define ARCMSR_CDB_FLAG_BIOS               0x02   /* bit 1: 0(from driver) / 1(from BIOS) */
-#define ARCMSR_CDB_FLAG_WRITE              0x04	  /* bit 2: 0(Data in) / 1(Data out)      */
-#define ARCMSR_CDB_FLAG_SIMPLEQ            0x00	  /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
-#define ARCMSR_CDB_FLAG_HEADQ              0x08
-#define ARCMSR_CDB_FLAG_ORDEREDQ           0x10
+	u_int8_t     	Bus;              /* 00h   should be 0            */
+	u_int8_t     	TargetID;         /* 01h   should be 0--15        */
+	u_int8_t     	LUN;              /* 02h   should be 0--7         */
+	u_int8_t     	Function;         /* 03h   should be 1            */
+	
+	u_int8_t     	CdbLength;        /* 04h   not used now           */
+	u_int8_t     	sgcount;          /* 05h                          */
+	u_int8_t     	Flags;            /* 06h                          */
 	u_int8_t     	msgPages;         /* 07h                          */
-
-	u_int32_t    						Context;          /* 08h   Address of this request */
-	u_int32_t    						DataLength;       /* 0ch   not used now            */
-
-	u_int8_t     						Cdb[16];          /* 10h   SCSI CDB                */
+	
+	u_int32_t    	Context;          /* 08h   Address of this request */
+	u_int32_t    	DataLength;       /* 0ch   not used now           */
+	
+	u_int8_t     	Cdb[16];          /* 10h   SCSI CDB               */
 	/*
 	********************************************************
-	**Device Status : the same from SCSI bus if error occur
+	** Device Status : the same from SCSI bus if error occur 
 	** SCSI bus status codes.
 	********************************************************
 	*/
-	u_int8_t     						DeviceStatus;     /* 20h   if error                */
+	u_int8_t     	DeviceStatus;     /* 20h   if error                */
+	
+	u_int8_t     	SenseData[15];    /* 21h   output                  */        
+	
+	union {
+		struct SG32ENTRY	sg32entry[ARCMSR_MAX_SG_ENTRIES];        /* 30h   Scatter gather address  */
+		struct SG64ENTRY	sg64entry[ARCMSR_MAX_SG_ENTRIES];        /* 30h                           */
+	} u;
+};
+/* CDB flag */
+#define ARCMSR_CDB_FLAG_SGL_BSIZE		0x01	/* bit 0: 0(256) / 1(512) bytes         */
+#define ARCMSR_CDB_FLAG_BIOS			0x02	/* bit 1: 0(from driver) / 1(from BIOS) */
+#define ARCMSR_CDB_FLAG_WRITE			0x04	/* bit 2: 0(Data in) / 1(Data out)      */
+#define ARCMSR_CDB_FLAG_SIMPLEQ			0x00	/* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
+#define ARCMSR_CDB_FLAG_HEADQ			0x08
+#define ARCMSR_CDB_FLAG_ORDEREDQ		0x10
+/* scsi status */
 #define SCSISTAT_GOOD                  		0x00
 #define SCSISTAT_CHECK_CONDITION       		0x02
 #define SCSISTAT_CONDITION_MET         		0x04
@@ -704,17 +1037,10 @@ struct ARCMSR_CDB {
 #define SCSISTAT_RESERVATION_CONFLICT  		0x18
 #define SCSISTAT_COMMAND_TERMINATED    		0x22
 #define SCSISTAT_QUEUE_FULL            		0x28
-#define ARCMSR_DEV_SELECT_TIMEOUT               0xF0
-#define ARCMSR_DEV_ABORTED                      0xF1
-#define ARCMSR_DEV_INIT_FAIL                    0xF2
-
-	u_int8_t     						SenseData[15];    /* 21h   output                  */
-
-	union {
-		struct SG32ENTRY                sg32entry[ARCMSR_MAX_SG_ENTRIES];        /* 30h   Scatter gather address  */
-		struct SG64ENTRY                sg64entry[ARCMSR_MAX_SG_ENTRIES];        /* 30h                           */
-	} u;
-};
+/* DeviceStatus */
+#define ARCMSR_DEV_SELECT_TIMEOUT		0xF0
+#define ARCMSR_DEV_ABORTED			0xF1
+#define ARCMSR_DEV_INIT_FAIL			0xF2
 /*
 *********************************************************************
 **                   Command Control Block (SrbExtension)
@@ -724,351 +1050,196 @@ struct ARCMSR_CDB {
 *********************************************************************
 */
 struct CommandControlBlock {
-	struct ARCMSR_CDB			arcmsr_cdb;				/* 0  -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
-	u_int32_t					cdb_shifted_phyaddr;     /* 504-507 */
-	u_int32_t					arc_cdb_size;			/* 508-511 */
+	struct ARCMSR_CDB	arcmsr_cdb;		/* 0  -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */
+	u_int32_t		cdb_phyaddr_low;	/* 504-507 */
+	u_int32_t		arc_cdb_size;		/* 508-511 */
 	/*  ======================512+32 bytes============================  */
-	union ccb					*pccb;					/* 512-515 516-519 pointer of freebsd scsi command */
-	struct AdapterControlBlock	*acb;					/* 520-523 524-527 */
-		bus_dmamap_t				dm_segs_dmamap;          /* 528-531 532-535 */
-		u_int16_t   				srb_flags;               /* 536-537 */
-	u_int16_t					srb_state;                /* 538-539 */
-	struct	callout				ccb_callout;
+	union ccb		*pccb;			/* 512-515 516-519 pointer of freebsd scsi command */
+	struct AdapterControlBlock	*acb;		/* 520-523 524-527 */
+	bus_dmamap_t		dm_segs_dmamap;		/* 528-531 532-535 */
+	u_int16_t   		srb_flags;		/* 536-537 */
+	u_int16_t		srb_state;              /* 538-539 */
+	u_int32_t		cdb_phyaddr_high;	/* 540-543 */
+	struct	callout		ccb_callout;
     /*  ==========================================================  */
 };
 /*	srb_flags */
-#define		SRB_FLAG_READ				0x0000
-#define		SRB_FLAG_WRITE				0x0001
-#define		SRB_FLAG_ERROR				0x0002
-#define		SRB_FLAG_FLUSHCACHE			0x0004
+#define		SRB_FLAG_READ			0x0000
+#define		SRB_FLAG_WRITE			0x0001
+#define		SRB_FLAG_ERROR			0x0002
+#define		SRB_FLAG_FLUSHCACHE		0x0004
 #define		SRB_FLAG_MASTER_ABORTED 	0x0008
-#define		SRB_FLAG_DMAVALID			0x0010
+#define		SRB_FLAG_DMAVALID		0x0010
 #define		SRB_FLAG_DMACONSISTENT  	0x0020
-#define		SRB_FLAG_DMAWRITE			0x0040
-#define		SRB_FLAG_PKTBIND			0x0080
+#define		SRB_FLAG_DMAWRITE		0x0040
+#define		SRB_FLAG_PKTBIND		0x0080
 #define		SRB_FLAG_TIMER_START		0x0080
 /*	srb_state */
-#define		ARCMSR_SRB_DONE   			0x0000
-#define		ARCMSR_SRB_UNBUILD 			0x0000
-#define		ARCMSR_SRB_TIMEOUT 			0x1111
-#define		ARCMSR_SRB_RETRY 			0x2222
-#define		ARCMSR_SRB_START   			0x55AA
-#define		ARCMSR_SRB_PENDING			0xAA55
-#define		ARCMSR_SRB_RESET			0xA5A5
-#define		ARCMSR_SRB_ABORTED			0x5A5A
-#define		ARCMSR_SRB_ILLEGAL			0xFFFF
+#define		ARCMSR_SRB_DONE   		0x0000
+#define		ARCMSR_SRB_UNBUILD 		0x0000
+#define		ARCMSR_SRB_TIMEOUT 		0x1111
+#define		ARCMSR_SRB_RETRY 		0x2222
+#define		ARCMSR_SRB_START   		0x55AA
+#define		ARCMSR_SRB_PENDING		0xAA55
+#define		ARCMSR_SRB_RESET		0xA5A5
+#define		ARCMSR_SRB_ABORTED		0x5A5A
+#define		ARCMSR_SRB_ILLEGAL		0xFFFF
+
+#define		SRB_SIZE	((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0)
+#define 	ARCMSR_SRBS_POOL_SIZE   (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM)
+
 /*
 *********************************************************************
 **                 Adapter Control Block
 *********************************************************************
 */
-#define ACB_ADAPTER_TYPE_A            0x00000001                /* hba I IOP */
-#define ACB_ADAPTER_TYPE_B            0x00000002                /* hbb M IOP */
-#define ACB_ADAPTER_TYPE_C            0x00000004			/* hbc L IOP */
-#define ACB_ADAPTER_TYPE_D            0x00000008                /* hbd A IOP */
+#define ACB_ADAPTER_TYPE_A	0x00000001	/* hba I IOP */
+#define ACB_ADAPTER_TYPE_B	0x00000002	/* hbb M IOP */
+#define ACB_ADAPTER_TYPE_C	0x00000004	/* hbc L IOP */
+#define ACB_ADAPTER_TYPE_D	0x00000008	/* hbd M IOP */
 
 struct AdapterControlBlock {
-	u_int32_t					adapter_type;               /* adapter A,B..... */
-
-	bus_space_tag_t					btag[2];
-	bus_space_handle_t				bhandle[2];
-	bus_dma_tag_t					parent_dmat;
-	bus_dma_tag_t					dm_segs_dmat;                         /* dmat for buffer I/O */
-	bus_dma_tag_t					srb_dmat;                             /* dmat for freesrb */
-	bus_dmamap_t					srb_dmamap;
-	device_t					pci_dev;
-	struct cdev					*ioctl_dev;
-	int						pci_unit;
-
-	struct resource				*sys_res_arcmsr[2];
-	struct resource				*irqres;
-	void						*ih;                         /* interrupt handle */
-	int						irq_type;
-
+	u_int32_t		adapter_type;		/* adapter A,B..... */
+	
+	bus_space_tag_t		btag[2];
+	bus_space_handle_t	bhandle[2];
+	bus_dma_tag_t		parent_dmat;
+	bus_dma_tag_t		dm_segs_dmat;		/* dmat for buffer I/O */  
+	bus_dma_tag_t		srb_dmat;		/* dmat for freesrb */
+	bus_dmamap_t		srb_dmamap;
+	device_t		pci_dev;
+	struct cdev		*ioctl_dev;
+	int			pci_unit;
+	
+	struct resource		*sys_res_arcmsr[2];
+	struct resource		*irqres;
+	void			*ih;			/* interrupt handle */
+	int			irq_type;
+	
 	/* Hooks into the CAM XPT */
-	struct						cam_sim *psim;
-	struct						cam_path *ppath;
-	u_int8_t					*uncacheptr;
-	unsigned long					vir2phy_offset;
+	struct			cam_sim *psim;
+	struct			cam_path *ppath;
+	u_int8_t		*uncacheptr;
+	unsigned long		vir2phy_offset;
 	union	{
-		unsigned long			phyaddr;
+		unsigned long	phyaddr;
 		struct {
-				u_int32_t		phyadd_low;
-				u_int32_t		phyadd_high;
+			u_int32_t	phyadd_low;
+			u_int32_t	phyadd_high;
 		}B;
-	} 							srb_phyaddr;
+	}srb_phyaddr;
 //	unsigned long				srb_phyaddr;
 	/* Offset is used in making arc cdb physical to virtual calculations */
-	u_int32_t					outbound_int_enable;
-
-	struct MessageUnit_UNION	*pmu;                        /* message unit ATU inbound base address0 */
-
-	u_int8_t					adapter_index;                         /*  */
-	u_int8_t					irq;
-	u_int16_t					acb_flags;                             /*  */
-
+	u_int32_t		outbound_int_enable;
+	
+	struct MessageUnit_UNION	*pmu;		/* message unit ATU inbound base address0 */
+	
+	u_int8_t		adapter_index;
+	u_int8_t		irq;
+	u_int16_t		acb_flags;
+	
 	struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM];     /* serial srb pointer array */
 	struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM];   /* working srb pointer array */
-	int32_t						workingsrb_doneindex;                  /* done srb array index */
-	int32_t						workingsrb_startindex;                 /* start srb array index  */
-	int32_t						srboutstandingcount;
-
-	u_int8_t					rqbuffer[ARCMSR_MAX_QBUFFER];          /* data collection buffer for read from 80331 */
-	u_int32_t					rqbuf_firstindex;                      /* first of read buffer  */
-	u_int32_t					rqbuf_lastindex;                       /* last of read buffer   */
-
-	u_int8_t					wqbuffer[ARCMSR_MAX_QBUFFER];          /* data collection buffer for write to 80331  */
-	u_int32_t					wqbuf_firstindex;                      /* first of write buffer */
-	u_int32_t					wqbuf_lastindex;                       /* last of write buffer  */
-
-	arcmsr_lock_t					workingQ_done_lock;
-	arcmsr_lock_t					workingQ_start_lock;
-	arcmsr_lock_t					qbuffer_lock;
-
-	u_int8_t					devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
-	u_int32_t					num_resets;
-	u_int32_t					num_aborts;
-	u_int32_t					firm_request_len;                      /*1,04-07*/
-	u_int32_t					firm_numbers_queue;                    /*2,08-11*/
-	u_int32_t					firm_sdram_size;                       /*3,12-15*/
-	u_int32_t					firm_ide_channels;                     /*4,16-19*/
-	u_int32_t					firm_cfg_version;
-	char						firm_model[12];	                       /*15,60-67*/
-	char						firm_version[20];                      /*17,68-83*/
-	char						device_map[20];				/*21,84-99 */
-	struct	callout				devmap_callout;
-#ifdef ARCMSR_DEBUG1
-	u_int32_t					pktRequestCount;
-	u_int32_t					pktReturnCount;
-#endif
-	u_int32_t					vendor_device_id;
-	u_int32_t					adapter_bus_speed;
+	int32_t			workingsrb_doneindex;		/* done srb array index */
+	int32_t			workingsrb_startindex;		/* start srb array index  */
+	int32_t			srboutstandingcount;
+	
+	u_int8_t		rqbuffer[ARCMSR_MAX_QBUFFER];	/* data collection buffer for read from 80331 */
+	u_int32_t		rqbuf_firstindex;		/* first of read buffer  */
+	u_int32_t		rqbuf_lastindex;		/* last of read buffer   */
+	
+	u_int8_t		wqbuffer[ARCMSR_MAX_QBUFFER];	/* data collection buffer for write to 80331  */
+	u_int32_t		wqbuf_firstindex;		/* first of write buffer */
+	u_int32_t		wqbuf_lastindex;		/* last of write buffer  */
+	
+	arcmsr_lock_t		isr_lock;
+	arcmsr_lock_t		srb_lock;
+	arcmsr_lock_t		postDone_lock;
+	arcmsr_lock_t		qbuffer_lock;
+	
+	u_int8_t		devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */
+	u_int32_t		num_resets;
+	u_int32_t		num_aborts;
+	u_int32_t		firm_request_len;	/*1,04-07*/
+	u_int32_t		firm_numbers_queue;	/*2,08-11*/
+	u_int32_t		firm_sdram_size;	/*3,12-15*/
+	u_int32_t		firm_ide_channels;	/*4,16-19*/
+	u_int32_t		firm_cfg_version;
+	char			firm_model[12];		/*15,60-67*/
+	char			firm_version[20];	/*17,68-83*/
+	char			device_map[20];		/*21,84-99 */
+	struct	callout		devmap_callout;
+	u_int32_t		pktRequestCount;
+	u_int32_t		pktReturnCount;
+	u_int32_t		vendor_device_id;
+	u_int32_t		adapter_bus_speed;
+	u_int32_t		maxOutstanding;
+	u_int16_t		sub_device_id;
 };/* HW_DEVICE_EXTENSION */
 /* acb_flags */
 #define ACB_F_SCSISTOPADAPTER           0x0001
-#define ACB_F_MSG_STOP_BGRB             0x0002              /* stop RAID background rebuild */
-#define ACB_F_MSG_START_BGRB            0x0004              /* stop RAID background rebuild */
-#define ACB_F_IOPDATA_OVERFLOW          0x0008              /* iop ioctl data rqbuffer overflow */
-#define ACB_F_MESSAGE_WQBUFFER_CLEARED  0x0010              /* ioctl clear wqbuffer */
-#define ACB_F_MESSAGE_RQBUFFER_CLEARED  0x0020              /* ioctl clear rqbuffer */
+#define ACB_F_MSG_STOP_BGRB             0x0002		/* stop RAID background rebuild */
+#define ACB_F_MSG_START_BGRB            0x0004		/* stop RAID background rebuild */
+#define ACB_F_IOPDATA_OVERFLOW          0x0008		/* iop ioctl data rqbuffer overflow */
+#define ACB_F_MESSAGE_WQBUFFER_CLEARED  0x0010		/* ioctl clear wqbuffer */
+#define ACB_F_MESSAGE_RQBUFFER_CLEARED  0x0020		/* ioctl clear rqbuffer */
 #define ACB_F_MESSAGE_WQBUFFER_READ     0x0040
 #define ACB_F_BUS_RESET                 0x0080
-#define ACB_F_IOP_INITED                0x0100              /* iop init */
-#define ACB_F_MAPFREESRB_FAILD		    0x0200              /* arcmsr_map_freesrb faild */
+#define ACB_F_IOP_INITED                0x0100		/* iop init */
+#define ACB_F_MAPFREESRB_FAILD		0x0200		/* arcmsr_map_freesrb faild */
 #define ACB_F_CAM_DEV_QFRZN             0x0400
-#define ACB_F_BUS_HANG_ON               0x0800              /* need hardware reset bus */
+#define ACB_F_BUS_HANG_ON               0x0800		/* need hardware reset bus */
 #define ACB_F_SRB_FUNCTION_POWER        0x1000
 /* devstate */
-#define ARECA_RAID_GONE         		0x55
-#define ARECA_RAID_GOOD         		0xaa
+#define ARECA_RAID_GONE         	0x55
+#define ARECA_RAID_GOOD         	0xaa
 /* adapter_bus_speed */
 #define	ACB_BUS_SPEED_3G	0
 #define	ACB_BUS_SPEED_6G	1
 #define	ACB_BUS_SPEED_12G	2
 /*
-*********************************************************************
-** Message Unit structure
-*********************************************************************
-*/
-struct HBA_MessageUnit
-{
-	u_int32_t				resrved0[4];	        /*0000 000F*/
-	u_int32_t				inbound_msgaddr0;	    /*0010 0013*/
-	u_int32_t				inbound_msgaddr1;	    /*0014 0017*/
-	u_int32_t				outbound_msgaddr0;	    /*0018 001B*/
-	u_int32_t				outbound_msgaddr1;	    /*001C 001F*/
-	u_int32_t				inbound_doorbell;	    /*0020 0023*/
-	u_int32_t				inbound_intstatus;	    /*0024 0027*/
-	u_int32_t				inbound_intmask;	    /*0028 002B*/
-	u_int32_t				outbound_doorbell;	    /*002C 002F*/
-	u_int32_t				outbound_intstatus;	    /*0030 0033*/
-	u_int32_t				outbound_intmask;	    /*0034 0037*/
-	u_int32_t				reserved1[2];	        /*0038 003F*/
-	u_int32_t				inbound_queueport;	    /*0040 0043*/
-	u_int32_t				outbound_queueport;     /*0044 0047*/
-	u_int32_t				reserved2[2];	        /*0048 004F*/
-	u_int32_t				reserved3[492];         /*0050 07FF ......local_buffer 492*/
-	u_int32_t				reserved4[128];         /*0800 09FF                    128*/
-	u_int32_t				msgcode_rwbuffer[256];  /*0a00 0DFF                    256*/
-	u_int32_t				message_wbuffer[32];    /*0E00 0E7F                     32*/
-	u_int32_t				reserved5[32];          /*0E80 0EFF                     32*/
-	u_int32_t				message_rbuffer[32];    /*0F00 0F7F                     32*/
-	u_int32_t				reserved6[32];          /*0F80 0FFF                     32*/
-};
-/*
-*********************************************************************
-**
-*********************************************************************
-*/
-struct HBB_DOORBELL
-{
-	u_int8_t				doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */
-	u_int32_t				drv2iop_doorbell;          /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */
-	u_int32_t				drv2iop_doorbell_mask;     /*                  04,05,06,07: doorbell mask */
-	u_int32_t				iop2drv_doorbell;          /*                  08,09,10,11: window of "instruction flags" from iop to driver */
-	u_int32_t				iop2drv_doorbell_mask;     /*                  12,13,14,15: doorbell mask */
-};
-/*
-*********************************************************************
-**
-*********************************************************************
-*/
-struct HBB_RWBUFFER
-{
-	u_int8_t				message_reserved0[ARCMSR_MSGCODE_RWBUFFER];   /*reserved */
-	u_int32_t				msgcode_rwbuffer[256];      /*offset 0x0000fa00:   0,   1,   2,   3,...,1023: message code read write 1024bytes */
-	u_int32_t				message_wbuffer[32];        /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */
-	u_int32_t				message_reserved1[32];      /*                  1152,1153,1154,1155,...,1279: message reserved*/
-	u_int32_t				message_rbuffer[32];        /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */
-};
-/*
-*********************************************************************
-**
-*********************************************************************
-*/
-struct HBB_MessageUnit
-{
-	u_int32_t				post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];       /* post queue buffer for iop */
-	u_int32_t				done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];       /* done queue buffer for iop */
-	int32_t					postq_index;                                  /* post queue index */
-	int32_t					doneq_index;								   /* done queue index */
-	struct HBB_DOORBELL    *hbb_doorbell;
-	struct HBB_RWBUFFER    *hbb_rwbuffer;
-};
-
-/*
-*********************************************************************
-**
-*********************************************************************
-*/
-struct HBC_MessageUnit {
-	u_int32_t	message_unit_status;                        /*0000 0003*/
-	u_int32_t	slave_error_attribute;	                    /*0004 0007*/
-	u_int32_t	slave_error_address;	                    /*0008 000B*/
-	u_int32_t	posted_outbound_doorbell;	                /*000C 000F*/
-	u_int32_t	master_error_attribute;	                    /*0010 0013*/
-	u_int32_t	master_error_address_low;	                /*0014 0017*/
-	u_int32_t	master_error_address_high;	                /*0018 001B*/
-	u_int32_t	hcb_size;                                   /*001C 001F size of the PCIe window used for HCB_Mode accesses*/
-	u_int32_t	inbound_doorbell;	                        /*0020 0023*/
-	u_int32_t	diagnostic_rw_data;	                        /*0024 0027*/
-	u_int32_t	diagnostic_rw_address_low;	                /*0028 002B*/
-	u_int32_t	diagnostic_rw_address_high;	                /*002C 002F*/
-	u_int32_t	host_int_status;	                        /*0030 0033 host interrupt status*/
-	u_int32_t	host_int_mask;     	                        /*0034 0037 host interrupt mask*/
-	u_int32_t	dcr_data;	                                /*0038 003B*/
-	u_int32_t   dcr_address;                                /*003C 003F*/
-	u_int32_t   inbound_queueport;                          /*0040 0043 port32 host inbound queue port*/
-	u_int32_t   outbound_queueport;                         /*0044 0047 port32 host outbound queue port*/
-	u_int32_t   hcb_pci_address_low;                        /*0048 004B*/
-    u_int32_t   hcb_pci_address_high;                       /*004C 004F*/
-	u_int32_t   iop_int_status;                             /*0050 0053*/
-	u_int32_t   iop_int_mask;                               /*0054 0057*/
-    u_int32_t   iop_inbound_queue_port;                     /*0058 005B*/
-    u_int32_t   iop_outbound_queue_port;                    /*005C 005F*/
-    u_int32_t   inbound_free_list_index;                    /*0060 0063 inbound free list producer consumer index*/
-    u_int32_t   inbound_post_list_index;                    /*0064 0067 inbound post list producer consumer index*/
-    u_int32_t   outbound_free_list_index;                   /*0068 006B outbound free list producer consumer index*/
-    u_int32_t   outbound_post_list_index;                   /*006C 006F outbound post list producer consumer index*/
-    u_int32_t   inbound_doorbell_clear;                     /*0070 0073*/
-    u_int32_t   i2o_message_unit_control;                   /*0074 0077*/
-    u_int32_t   last_used_message_source_address_low;       /*0078 007B*/
-    u_int32_t   last_used_message_source_address_high;		/*007C 007F*/
-    u_int32_t   pull_mode_data_byte_count[4];               /*0080 008F pull mode data byte count0..count7*/
-    u_int32_t   message_dest_address_index;                 /*0090 0093*/
-    u_int32_t   done_queue_not_empty_int_counter_timer;     /*0094 0097*/
-    u_int32_t   utility_A_int_counter_timer;                /*0098 009B*/
-    u_int32_t   outbound_doorbell;                          /*009C 009F*/
-    u_int32_t   outbound_doorbell_clear;                    /*00A0 00A3*/
-    u_int32_t   message_source_address_index;               /*00A4 00A7 message accelerator source address consumer producer index*/
-    u_int32_t   message_done_queue_index;                   /*00A8 00AB message accelerator completion queue consumer producer index*/
-    u_int32_t   reserved0;                                  /*00AC 00AF*/
-    u_int32_t   inbound_msgaddr0;                           /*00B0 00B3 scratchpad0*/
-    u_int32_t   inbound_msgaddr1;                           /*00B4 00B7 scratchpad1*/
-    u_int32_t   outbound_msgaddr0;                          /*00B8 00BB scratchpad2*/
-    u_int32_t   outbound_msgaddr1;                          /*00BC 00BF scratchpad3*/
-    u_int32_t   inbound_queueport_low;                      /*00C0 00C3 port64 host inbound queue port low*/
-    u_int32_t   inbound_queueport_high;                     /*00C4 00C7 port64 host inbound queue port high*/
-    u_int32_t   outbound_queueport_low;                     /*00C8 00CB port64 host outbound queue port low*/
-    u_int32_t   outbound_queueport_high;                    /*00CC 00CF port64 host outbound queue port high*/
-    u_int32_t   iop_inbound_queue_port_low;                 /*00D0 00D3*/
-    u_int32_t   iop_inbound_queue_port_high;                /*00D4 00D7*/
-    u_int32_t   iop_outbound_queue_port_low;                /*00D8 00DB*/
-    u_int32_t   iop_outbound_queue_port_high;               /*00DC 00DF*/
-    u_int32_t   message_dest_queue_port_low;                /*00E0 00E3 message accelerator destination queue port low*/
-    u_int32_t   message_dest_queue_port_high;               /*00E4 00E7 message accelerator destination queue port high*/
-    u_int32_t   last_used_message_dest_address_low;         /*00E8 00EB last used message accelerator destination address low*/
-    u_int32_t   last_used_message_dest_address_high;        /*00EC 00EF last used message accelerator destination address high*/
-    u_int32_t   message_done_queue_base_address_low;        /*00F0 00F3 message accelerator completion queue base address low*/
-    u_int32_t   message_done_queue_base_address_high;       /*00F4 00F7 message accelerator completion queue base address high*/
-    u_int32_t   host_diagnostic;                            /*00F8 00FB*/
-    u_int32_t   write_sequence;                             /*00FC 00FF*/
-    u_int32_t   reserved1[34];                              /*0100 0187*/
-    u_int32_t   reserved2[1950];                            /*0188 1FFF*/
-    u_int32_t   message_wbuffer[32];                        /*2000 207F*/
-    u_int32_t   reserved3[32];                              /*2080 20FF*/
-    u_int32_t   message_rbuffer[32];                        /*2100 217F*/
-    u_int32_t   reserved4[32];                              /*2180 21FF*/
-    u_int32_t   msgcode_rwbuffer[256];                      /*2200 23FF*/
-};
-
-/*
-*********************************************************************
-**
-*********************************************************************
-*/
-struct MessageUnit_UNION
-{
-	union	{
-		struct HBA_MessageUnit				hbamu;
-		struct HBB_MessageUnit				hbbmu;
-        struct HBC_MessageUnit          	hbcmu;
-	} muu;
-};
-
-/*
 *************************************************************
 *************************************************************
 */
 struct SENSE_DATA {
-    u_int8_t 						ErrorCode:7;
-    u_int8_t 						Valid:1;
-    u_int8_t 						SegmentNumber;
-    u_int8_t 						SenseKey:4;
-    u_int8_t 						Reserved:1;
-    u_int8_t 						IncorrectLength:1;
-    u_int8_t 						EndOfMedia:1;
-    u_int8_t 						FileMark:1;
-    u_int8_t 						Information[4];
-    u_int8_t 						AdditionalSenseLength;
-    u_int8_t 						CommandSpecificInformation[4];
-    u_int8_t 						AdditionalSenseCode;
-    u_int8_t 						AdditionalSenseCodeQualifier;
-    u_int8_t 						FieldReplaceableUnitCode;
-    u_int8_t 						SenseKeySpecific[3];
+    u_int8_t 	ErrorCode:7;
+    u_int8_t 	Valid:1;
+    u_int8_t 	SegmentNumber;
+    u_int8_t 	SenseKey:4;
+    u_int8_t 	Reserved:1;
+    u_int8_t 	IncorrectLength:1;
+    u_int8_t 	EndOfMedia:1;
+    u_int8_t 	FileMark:1;
+    u_int8_t 	Information[4];
+    u_int8_t 	AdditionalSenseLength;
+    u_int8_t 	CommandSpecificInformation[4];
+    u_int8_t 	AdditionalSenseCode;
+    u_int8_t 	AdditionalSenseCodeQualifier;
+    u_int8_t 	FieldReplaceableUnitCode;
+    u_int8_t 	SenseKeySpecific[3];
 };
-/*
+/* 
 **********************************
-**  Peripheral Device Type definitions
+**  Peripheral Device Type definitions 
 **********************************
 */
-#define SCSI_DASD		      0x00	   /* Direct-access Device	   */
-#define SCSI_SEQACESS		      0x01	   /* Sequential-access device     */
-#define SCSI_PRINTER		      0x02	   /* Printer device		   */
-#define SCSI_PROCESSOR		      0x03	   /* Processor device		   */
-#define SCSI_WRITEONCE		      0x04	   /* Write-once device 	   */
-#define SCSI_CDROM		      0x05	   /* CD-ROM device		   */
-#define SCSI_SCANNER		      0x06	   /* Scanner device		   */
-#define SCSI_OPTICAL		      0x07	   /* Optical memory device	   */
-#define SCSI_MEDCHGR		      0x08	   /* Medium changer device	   */
-#define SCSI_COMM		      0x09	   /* Communications device	   */
-#define SCSI_NODEV		      0x1F	   /* Unknown or no device type    */
+#define SCSI_DASD		0x00	   /* Direct-access Device	   */
+#define SCSI_SEQACESS		0x01	   /* Sequential-access device     */
+#define SCSI_PRINTER		0x02	   /* Printer device		   */
+#define SCSI_PROCESSOR		0x03	   /* Processor device		   */
+#define SCSI_WRITEONCE		0x04	   /* Write-once device 	   */
+#define SCSI_CDROM		0x05	   /* CD-ROM device		   */
+#define SCSI_SCANNER		0x06	   /* Scanner device		   */
+#define SCSI_OPTICAL		0x07	   /* Optical memory device	   */
+#define SCSI_MEDCHGR		0x08	   /* Medium changer device	   */
+#define SCSI_COMM		0x09	   /* Communications device	   */
+#define SCSI_NODEV		0x1F	   /* Unknown or no device type    */
 /*
 ************************************************************************************************************
 **				         @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 **				                          80331 PCI-to-PCI Bridge
-**				                          PCI Configuration Space
-**
+**				                          PCI Configuration Space 
+**				
 **				         @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 **				                            Programming Interface
 **				                          ========================
@@ -1123,7 +1294,7 @@ struct SENSE_DATA {
 */
 /*
 **=============================================================================================================
-**  0x03-0x00 :
+**  0x03-0x00 : 
 ** Bit       Default             Description
 **31:16       0335h            Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG.
 **                             ID is unique per product speed as indicated.
@@ -1134,44 +1305,44 @@ struct SENSE_DATA {
 #define     ARCMSR_PCI2PCI_DEVICEID_REG		         0x02    /*word*/
 /*
 **==============================================================================
-**  0x05-0x04 : command register
+**  0x05-0x04 : command register 
 ** Bit       Default 		               Description
 **15:11        00h		   		             Reserved
-** 10          0		   		           Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus.
+** 10          0		   		           Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 
 **                		   		                              The bridge does not support interrupts.
-** 09          0		   		                 FB2B Enable: Enables/Disables the generation of fast back to back
-**										transactions on the primary bus.
-**                		   		                              The bridge does not generate fast back to back
+** 09          0		   		                 FB2B Enable: Enables/Disables the generation of fast back to back 
+**										transactions on the primary bus. 
+**                		   		                              The bridge does not generate fast back to back 
 **										transactions on the primary bus.
 ** 08          0		   		          SERR# Enable (SEE): Enables primary bus SERR# assertions.
 **                		   		                              0=The bridge does not assert P_SERR#.
 **                		   		                              1=The bridge may assert P_SERR#, subject to other programmable criteria.
-** 07          0		   		    Wait Cycle Control (WCC): Always returns 0bzero indicating
+** 07          0		   		    Wait Cycle Control (WCC): Always returns 0bzero indicating 
 **										that bridge does not perform address or data stepping,
 ** 06          0		   		 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error.
-**                		   		                              0=When a data parity error is detected bridge does not assert S_PERR#.
-**                		   		                                  Also bridge does not assert P_SERR# in response to
+**                		   		                              0=When a data parity error is detected bridge does not assert S_PERR#. 
+**                		   		                                  Also bridge does not assert P_SERR# in response to 
 **											a detected address or attribute parity error.
-**                		   		                              1=When a data parity error is detected bridge asserts S_PERR#.
-**                		   		                                  The bridge also asserts P_SERR#
-**											(when enabled globally via bit(8) of this register)
+**                		   		                              1=When a data parity error is detected bridge asserts S_PERR#. 
+**                		   		                                  The bridge also asserts P_SERR# 
+**											(when enabled globally via bit(8) of this register) 
 **											in response to a detected address or attribute parity error.
-** 05          0		  VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions.
+** 05          0		  VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 
 **                		                                      VGA palette write transactions are I/O transactions
 **										 whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h
-**                		                                      P_AD[15:10] are not decoded (i.e. aliases are claimed),
-**										or are fully decoding
-**										(i.e., must be all 0's depending upon the VGA
+**                		                                      P_AD[15:10] are not decoded (i.e. aliases are claimed), 
+**										or are fully decoding 
+**										(i.e., must be all 0's depending upon the VGA 
 **										aliasing bit in the Bridge Control Register, offset 3Eh.
 **                		                                      P_AD[31:16] equal to 0000h
-**                		                                      0=The bridge ignores VGA palette write transactions,
+**                		                                      0=The bridge ignores VGA palette write transactions, 
 **										unless decoded by the standard I/O address range window.
-**                		                                      1=The bridge responds to VGA palette write transactions
+**                		                                      1=The bridge responds to VGA palette write transactions 
 **										with medium DEVSEL# timing and forwards them to the secondary bus.
-** 04          0   Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions.
-**                                                            MWI transactions targeting resources on the opposite side of the bridge,
+** 04          0   Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 
+**                                                            MWI transactions targeting resources on the opposite side of the bridge, 
 **										however, are forwarded as MWI transactions.
-** 03          0                  Special Cycle Enable (SCE): The bridge ignores special cycle transactions.
+** 03          0                  Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 
 **                                                            This bit is read only and always returns 0 when read
 ** 02          0                     Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface.
 **                                                            Initiation of configuration transactions is not affected by the state of this bit.
@@ -1185,40 +1356,40 @@ struct SENSE_DATA {
 **                                                            1=The bridge target response to I/O transactions on the primary interface is enabled.
 **==============================================================================
 */
-#define     ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG		 0x04    /*word*/
-#define     PCI_DISABLE_INTERRUPT                        0x0400
+#define     ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG		0x04    /*word*/
+#define     PCI_DISABLE_INTERRUPT					0x0400
 /*
 **==============================================================================
-**  0x07-0x06 : status register
+**  0x07-0x06 : status register 
 ** Bit       Default                       Description
-** 15          0                       Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
-**									attribute or data parity error.
+** 15          0                       Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 
+**									attribute or data parity error. 
 **                                                            This bit is set regardless of the state of the PER bit in the command register.
 ** 14          0                       Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus.
-** 13          0                       Received Master Abort: The bridge sets this bit to a 1b when,
-**									acting as the initiator on the primary bus,
-**									its transaction (with the exception of special cycles)
+** 13          0                       Received Master Abort: The bridge sets this bit to a 1b when, 
+**									acting as the initiator on the primary bus, 
+**									its transaction (with the exception of special cycles) 
 **									has been terminated with a Master Abort.
-** 12          0                       Received Target Abort: The bridge sets this bit to a 1b when,
-**									acting as the initiator on the primary bus,
+** 12          0                       Received Target Abort: The bridge sets this bit to a 1b when, 
+**									acting as the initiator on the primary bus, 
 **									its transaction has been terminated with a Target Abort.
-** 11          0                       Signaled Target Abort: The bridge sets this bit to a 1b when it,
-**									as the target of a transaction, terminates it with a Target Abort.
+** 11          0                       Signaled Target Abort: The bridge sets this bit to a 1b when it, 
+**									as the target of a transaction, terminates it with a Target Abort. 
 **                                                            In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
-** 10:09       01                             DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface.
+** 10:09       01                             DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 
 **                                                            Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
-** 08          0                    Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
+** 08          0                    Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 
 **									The bridge is the current master on the primary bus
 **                                                            S_PERR# is detected asserted or is asserted by bridge
 **                                                            The Parity Error Response bit is set in the Command register
-** 07          1                   Fast Back to Back Capable: Returns a 1b when read indicating that bridge
+** 07          1                   Fast Back to Back Capable: Returns a 1b when read indicating that bridge 
 **									is able to respond to fast back to back transactions on its primary interface.
 ** 06          0                             Reserved
 ** 05          1                   66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable.
 **                                                            1 =
-** 04          1                    Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities.
-**                                                            Offset 34h (Capability Pointer register)
-**										provides the offset for the first entry
+** 04          1                    Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 
+**                                                            Offset 34h (Capability Pointer register) 
+**										provides the offset for the first entry 
 **										in the linked list of enhanced capabilities.
 ** 03          0                            Interrupt Status: Reflects the state of the interrupt in the device/function.
 **                                                            The bridge does not support interrupts.
@@ -1229,7 +1400,7 @@ struct SENSE_DATA {
 #define          ARCMSR_ADAP_66MHZ                   0x20
 /*
 **==============================================================================
-**  0x08 : revision ID
+**  0x08 : revision ID 
 ** Bit       Default                       Description
 ** 07:00       00000000                  Revision ID (RID): '00h' indicating bridge A-0 stepping.
 **==============================================================================
@@ -1237,7 +1408,7 @@ struct SENSE_DATA {
 #define     ARCMSR_PCI2PCI_REVISIONID_REG		     0x08    /*byte*/
 /*
 **==============================================================================
-**  0x0b-0x09 : 0180_00 (class code 1,native pci mode )
+**  0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 
 ** Bit       Default                       Description
 ** 23:16       06h                     Base Class Code (BCC): Indicates that this is a bridge device.
 ** 15:08       04h                      Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge.
@@ -1247,108 +1418,108 @@ struct SENSE_DATA {
 #define     ARCMSR_PCI2PCI_CLASSCODE_REG	         0x09    /*3bytes*/
 /*
 **==============================================================================
-**  0x0c : cache line size
+**  0x0c : cache line size 
 ** Bit       Default                       Description
 ** 07:00       00h                     Cache Line Size (CLS): Designates the cache line size in 32-bit dword units.
-**                                                            The contents of this register are factored into
-**									internal policy decisions associated with memory read prefetching,
+**                                                            The contents of this register are factored into 
+**									internal policy decisions associated with memory read prefetching, 
 **									and the promotion of Memory Write transactions to MWI transactions.
-**                                                            Valid cache line sizes are 8 and 16 dwords.
-**                                                            When the cache line size is set to an invalid value,
+**                                                            Valid cache line sizes are 8 and 16 dwords. 
+**                                                            When the cache line size is set to an invalid value, 
 **									bridge behaves as though the cache line size was set to 00h.
 **==============================================================================
 */
 #define     ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C    /*byte*/
 /*
 **==============================================================================
-**  0x0d : latency timer (number of pci clock 00-ff )
+**  0x0d : latency timer (number of pci clock 00-ff ) 
 ** Bit       Default                       Description
 **                                   Primary Latency Timer (PTV):
 ** 07:00      00h (Conventional PCI)   Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles,
-**                                                            referenced from the assertion of FRAME# to the expiration of the timer,
-**                                                            when bridge may continue as master of the current transaction. All bits are writable,
-**                                                            resulting in a granularity of 1 PCI clock cycle.
-**                                                            When the timer expires (i.e., equals 00h)
-**									bridge relinquishes the bus after the first data transfer
+**                                                            referenced from the assertion of FRAME# to the expiration of the timer, 
+**                                                            when bridge may continue as master of the current transaction. All bits are writable, 
+**                                                            resulting in a granularity of 1 PCI clock cycle. 
+**                                                            When the timer expires (i.e., equals 00h) 
+**									bridge relinquishes the bus after the first data transfer 
 **									when its PCI bus grant has been deasserted.
-**         or 40h (PCI-X)                         PCI-X Mode: Primary bus Master latency timer.
+**         or 40h (PCI-X)                         PCI-X Mode: Primary bus Master latency timer. 
 **                                                            Indicates the number of PCI clock cycles,
-**                                                            referenced from the assertion of FRAME# to the expiration of the timer,
-**                                                            when bridge may continue as master of the current transaction.
-**                                                            All bits are writable, resulting in a granularity of 1 PCI clock cycle.
-**                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
-**                                                            (Except in the case where MLT expires within 3 data phases
-**								of an ADB.In this case bridge continues on
+**                                                            referenced from the assertion of FRAME# to the expiration of the timer, 
+**                                                            when bridge may continue as master of the current transaction. 
+**                                                            All bits are writable, resulting in a granularity of 1 PCI clock cycle. 
+**                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 
+**                                                            (Except in the case where MLT expires within 3 data phases 
+**								of an ADB.In this case bridge continues on 
 **								until it reaches the next ADB before relinquishing the bus.)
 **==============================================================================
 */
 #define     ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG	 0x0D    /*byte*/
 /*
 **==============================================================================
-**  0x0e : (header type,single function )
+**  0x0e : (header type,single function ) 
 ** Bit       Default                       Description
 ** 07           0                Multi-function device (MVD): 80331 is a single-function device.
-** 06:00       01h                       Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space.
-**                                                            Returns ¡§01h¡¨ when read indicating
+** 06:00       01h                       Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 
+**                                                            Returns ¡§01h¡¨ when read indicating 
 **								that the register layout conforms to the standard PCI-to-PCI bridge layout.
 **==============================================================================
 */
 #define     ARCMSR_PCI2PCI_HEADERTYPE_REG	         0x0E    /*byte*/
 /*
 **==============================================================================
-**     0x0f   :
+**     0x0f   : 
 **==============================================================================
 */
 /*
 **==============================================================================
-**  0x13-0x10 :
-**  PCI CFG Base Address #0 (0x10)
+**  0x13-0x10 : 
+**  PCI CFG Base Address #0 (0x10) 
 **==============================================================================
 */
 /*
 **==============================================================================
-**  0x17-0x14 :
-**  PCI CFG Base Address #1 (0x14)
+**  0x17-0x14 : 
+**  PCI CFG Base Address #1 (0x14) 
 **==============================================================================
 */
 /*
 **==============================================================================
-**  0x1b-0x18 :
-**  PCI CFG Base Address #2 (0x18)
+**  0x1b-0x18 : 
+**  PCI CFG Base Address #2 (0x18) 
 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
 ** Bit       Default                       Description
-** 23:16       00h             Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge.
-**                                                            Any Type 1 configuration cycle
+** 23:16       00h             Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 
+**                                                            Any Type 1 configuration cycle 
 **									on the primary bus whose bus number is greater than the secondary bus number,
-**                                                            and less than or equal to the subordinate bus number
+**                                                            and less than or equal to the subordinate bus number 
 **									is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus.
-** 15:08       00h               Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected.
-**                                                            Any Type 1 configuration cycle matching this bus number
-**									is translated to a Type 0 configuration cycle (or a Special Cycle)
+** 15:08       00h               Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 
+**                                                            Any Type 1 configuration cycle matching this bus number 
+**									is translated to a Type 0 configuration cycle (or a Special Cycle) 
 **									before being executed on bridge's secondary PCI bus.
-** 07:00       00h                  Primary Bus Number (PBN): Indicates bridge primary bus number.
-**                                                            Any Type 1 configuration cycle on the primary interface
-**									with a bus number that is less than the contents
+** 07:00       00h                  Primary Bus Number (PBN): Indicates bridge primary bus number. 
+**                                                            Any Type 1 configuration cycle on the primary interface 
+**									with a bus number that is less than the contents 
 **									of this register field does not be claimed by bridge.
 **-----------------0x1B--Secondary Latency Timer Register - SLTR
 ** Bit       Default                       Description
 **                             Secondary Latency Timer (STV):
-** 07:00       00h (Conventional PCI)  Conventional PCI Mode: Secondary bus Master latency timer.
+** 07:00       00h (Conventional PCI)  Conventional PCI Mode: Secondary bus Master latency timer. 
 **                                                            Indicates the number of PCI clock cycles,
-**									referenced from the assertion of FRAME# to the expiration of the timer,
-**                                                            when bridge may continue as master of the current transaction. All bits are writable,
+**									referenced from the assertion of FRAME# to the expiration of the timer, 
+**                                                            when bridge may continue as master of the current transaction. All bits are writable, 
 **                                                            resulting in a granularity of 1 PCI clock cycle.
-**                                                            When the timer expires (i.e., equals 00h)
-**								bridge relinquishes the bus after the first data transfer
+**                                                            When the timer expires (i.e., equals 00h) 
+**								bridge relinquishes the bus after the first data transfer 
 **								when its PCI bus grant has been deasserted.
-**          or 40h (PCI-X)                        PCI-X Mode: Secondary bus Master latency timer.
-**                                                            Indicates the number of PCI clock cycles,referenced from the assertion of FRAME#
-**								to the expiration of the timer,
-**                                                            when bridge may continue as master of the current transaction. All bits are writable,
+**          or 40h (PCI-X)                        PCI-X Mode: Secondary bus Master latency timer. 
+**                                                            Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 
+**								to the expiration of the timer, 
+**                                                            when bridge may continue as master of the current transaction. All bits are writable, 
 **                                                            resulting in a granularity of 1 PCI clock cycle.
-**                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB.
-**                                                            (Except in the case where MLT expires within 3 data phases of an ADB.
-**								In this case bridge continues on until it reaches the next ADB
+**                                                            When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 
+**                                                            (Except in the case where MLT expires within 3 data phases of an ADB. 
+**								In this case bridge continues on until it reaches the next ADB 
 **								before relinquishing the bus)
 **==============================================================================
 */
@@ -1358,42 +1529,42 @@ struct SENSE_DATA {
 #define     ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG	         0x1B    /*byte*/
 /*
 **==============================================================================
-**  0x1f-0x1c :
-**  PCI CFG Base Address #3 (0x1C)
+**  0x1f-0x1c : 
+**  PCI CFG Base Address #3 (0x1C) 
 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
 ** Bit       Default                       Description
-** 15:12        0h            I/O Limit Address Bits [15:12]: Defines the top address of an address range to
-**								determine when to forward I/O transactions from one interface to the other.
-**                                                            These bits correspond to address lines 15:12 for 4KB alignment.
+** 15:12        0h            I/O Limit Address Bits [15:12]: Defines the top address of an address range to 
+**								determine when to forward I/O transactions from one interface to the other. 
+**                                                            These bits correspond to address lines 15:12 for 4KB alignment. 
 **                                                            Bits 11:0 are assumed to be FFFh.
 ** 11:08        1h           I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing.
-** 07:04        0h             I/O Base Address Bits [15:12]: Defines the bottom address of
-**								an address range to determine when to forward I/O transactions
-**								from one interface to the other.
-**                                                            These bits correspond to address lines 15:12 for 4KB alignment.
+** 07:04        0h             I/O Base Address Bits [15:12]: Defines the bottom address of 
+**								an address range to determine when to forward I/O transactions 
+**								from one interface to the other. 
+**                                                            These bits correspond to address lines 15:12 for 4KB alignment. 
 **								Bits 11:0 are assumed to be 000h.
 ** 03:00        1h            I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing.
 **-----------------0x1F,0x1E--Secondary Status Register - SSR
 ** Bit       Default                       Description
-** 15           0b                     Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address,
+** 15           0b                     Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 
 **								attribute or data parity error on its secondary interface.
 ** 14           0b                     Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface.
-** 13           0b                     Received Master Abort: The bridge sets this bit to a 1b when,
-**								acting as the initiator on the secondary bus,
-**								it's transaction (with the exception of special cycles)
+** 13           0b                     Received Master Abort: The bridge sets this bit to a 1b when, 
+**								acting as the initiator on the secondary bus, 
+**								it's transaction (with the exception of special cycles) 
 **								has been terminated with a Master Abort.
-** 12           0b                     Received Target Abort: The bridge sets this bit to a 1b when,
-**								acting as the initiator on the secondary bus,
+** 12           0b                     Received Target Abort: The bridge sets this bit to a 1b when, 
+**								acting as the initiator on the secondary bus, 
 **								it's transaction has been terminated with a Target Abort.
-** 11           0b                     Signaled Target Abort: The bridge sets this bit to a 1b when it,
-**								as the target of a transaction, terminates it with a Target Abort.
+** 11           0b                     Signaled Target Abort: The bridge sets this bit to a 1b when it, 
+**								as the target of a transaction, terminates it with a Target Abort. 
 **                                                            In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code.
-** 10:09       01b                            DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface.
+** 10:09       01b                            DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 
 **                                                            Returns ¡§01b¡¨ when read, indicating that bridge responds no slower than with medium timing.
 ** 08           0b                  Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true:
 **                                                            The bridge is the current master on the secondary bus
 **                                                            S_PERR# is detected asserted or is asserted by bridge
-**                                                            The Parity Error Response bit is set in the Command register
+**                                                            The Parity Error Response bit is set in the Command register 
 ** 07           1b           Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles.
 ** 06           0b                           Reserved
 ** 05           1b                      66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable.
@@ -1406,21 +1577,21 @@ struct SENSE_DATA {
 #define     ARCMSR_PCI2PCI_SECONDARY_STATUS_REG	             0x1E    /*word: 0x1F,0x1E */
 /*
 **==============================================================================
-**  0x23-0x20 :
+**  0x23-0x20 : 
 **  PCI CFG Base Address #4 (0x20)
 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
 ** Bit       Default                       Description
 ** 31:20      000h                              Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
-**                                                            the upper 1MB aligned value (exclusive) of the range.
-**                                                            The incoming address must be less than or equal to this value.
-**                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
+**                                                            the upper 1MB aligned value (exclusive) of the range. 
+**                                                            The incoming address must be less than or equal to this value. 
+**                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 
 **									are assumed to be F FFFFh.
 ** 19:16        0h                            Reserved.
-** 15:04      000h                               Memory Base: These 12 bits are compared with bits P_AD[31:20]
-**								of the incoming address to determine the lower 1MB
-**								aligned value (inclusive) of the range.
+** 15:04      000h                               Memory Base: These 12 bits are compared with bits P_AD[31:20] 
+**								of the incoming address to determine the lower 1MB 
+**								aligned value (inclusive) of the range. 
 **                                                            The incoming address must be greater than or equal to this value.
-**                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
+**                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 
 **								are assumed to be 0 0000h.
 ** 03:00        0h                            Reserved.
 **==============================================================================
@@ -1429,20 +1600,20 @@ struct SENSE_DATA {
 #define     ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG  0x22    /*word: 0x23,0x22 */
 /*
 **==============================================================================
-**  0x27-0x24 :
-**  PCI CFG Base Address #5 (0x24)
+**  0x27-0x24 : 
+**  PCI CFG Base Address #5 (0x24) 
 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
 ** Bit       Default                       Description
 ** 31:20      000h                 Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine
-**                                                            the upper 1MB aligned value (exclusive) of the range.
-**                                                            The incoming address must be less than or equal to this value.
-**                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0]
+**                                                            the upper 1MB aligned value (exclusive) of the range. 
+**                                                            The incoming address must be less than or equal to this value. 
+**                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 
 **									are assumed to be F FFFFh.
 ** 19:16        1h                          64-bit Indicator: Indicates that 64-bit addressing is supported.
-** 15:04      000h                  Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20]
-**								of the incoming address to determine the lower 1MB aligned value (inclusive)
-**								of the range.
-**                                                            The incoming address must be greater than or equal to this value.
+** 15:04      000h                  Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 
+**								of the incoming address to determine the lower 1MB aligned value (inclusive) 
+**								of the range. 
+**                                                            The incoming address must be greater than or equal to this value. 
 **                                                            For the purposes of address decoding the lower 20 address bits (P_AD[19:0])
 **								 are assumed to be 0 0000h.
 ** 03:00        1h                          64-bit Indicator: Indicates that 64-bit addressing is supported.
@@ -1452,31 +1623,31 @@ struct SENSE_DATA {
 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG     0x26    /*word: 0x27,0x26 */
 /*
 **==============================================================================
-**  0x2b-0x28 :
+**  0x2b-0x28 : 
 ** Bit       Default                       Description
-** 31:00    00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable
+** 31:00    00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable  
 **                                                            bridge supports full 64-bit addressing.
 **==============================================================================
 */
 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG     0x28    /*dword: 0x2b,0x2a,0x29,0x28 */
 /*
 **==============================================================================
-**  0x2f-0x2c :
+**  0x2f-0x2c : 
 ** Bit       Default                       Description
-** 31:00    00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable
+** 31:00    00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 
 **                                                             bridge supports full 64-bit addressing.
 **==============================================================================
 */
 #define     ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG    0x2C    /*dword: 0x2f,0x2e,0x2d,0x2c */
 /*
 **==============================================================================
-**  0x33-0x30 :
+**  0x33-0x30 : 
 ** Bit       Default                       Description
 ** 07:00       DCh                      Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration
 **                                                            space. (Power Management Capability Registers)
 **==============================================================================
 */
-#define     ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG	                 0x34    /*byte*/
+#define     ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG	                 0x34    /*byte*/ 
 /*
 **==============================================================================
 **  0x3b-0x35 : reserved
@@ -1484,18 +1655,18 @@ struct SENSE_DATA {
 */
 /*
 **==============================================================================
-**  0x3d-0x3c :
+**  0x3d-0x3c : 
 **
 ** Bit       Default                       Description
 ** 15:08       00h                       Interrupt Pin (PIN): Bridges do not support the generation of interrupts.
 ** 07:00       00h                     Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'.
 **==============================================================================
 */
-#define     ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG                0x3C    /*byte*/
-#define     ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG                 0x3D    /*byte*/
+#define     ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG                0x3C    /*byte*/ 
+#define     ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG                 0x3D    /*byte*/ 
 /*
 **==============================================================================
-**  0x3f-0x3e :
+**  0x3f-0x3e : 
 ** Bit       Default                       Description
 ** 15:12        0h                          Reserved
 ** 11           0b                Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response
@@ -1504,90 +1675,90 @@ struct SENSE_DATA {
 **                                                            1b=SERR# is asserted.
 ** 10           0b                Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires.
 **                                                            The delayed completion is then discarded.
-** 09           0b             Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles
-**									that bridge waits for an initiator on the secondary bus
-**									to repeat a delayed transaction request.
-**                                                            The counter starts when the delayed transaction completion is ready
-**									to be returned to the initiator.
-**                                                            When the initiator has not repeated the transaction
-**									at least once before the counter expires,bridge
+** 09           0b             Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 
+**									that bridge waits for an initiator on the secondary bus 
+**									to repeat a delayed transaction request. 
+**                                                            The counter starts when the delayed transaction completion is ready 
+**									to be returned to the initiator. 
+**                                                            When the initiator has not repeated the transaction 
+**									at least once before the counter expires,bridge 
 **										discards the delayed transaction from its queues.
 **                                                            0b=The secondary master time-out counter is 2 15 PCI clock cycles.
 **                                                            1b=The secondary master time-out counter is 2 10 PCI clock cycles.
-** 08           0b               Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles
-**									that bridge waits for an initiator on the primary bus
-**									to repeat a delayed transaction request.
-**                                                            The counter starts when the delayed transaction completion
-**									is ready to be returned to the initiator.
-**                                                            When the initiator has not repeated the transaction
-**									at least once before the counter expires,
+** 08           0b               Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 
+**									that bridge waits for an initiator on the primary bus 
+**									to repeat a delayed transaction request. 
+**                                                            The counter starts when the delayed transaction completion 
+**									is ready to be returned to the initiator. 
+**                                                            When the initiator has not repeated the transaction 
+**									at least once before the counter expires, 
 **									bridge discards the delayed transaction from its queues.
 **                                                            0b=The primary master time-out counter is 2 15 PCI clock cycles.
 **                                                            1b=The primary master time-out counter is 2 10 PCI clock cycles.
 ** 07           0b            Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions.
-** 06           0b                 Secondary Bus Reset (SBR):
-**                                                            When cleared to 0b: The bridge deasserts S_RST#,
+** 06           0b                 Secondary Bus Reset (SBR): 
+**                                                            When cleared to 0b: The bridge deasserts S_RST#, 
 **									when it had been asserted by writing this bit to a 1b.
 **                                                                When set to 1b: The bridge asserts S_RST#.
-** 05           0b                   Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus
-**									when a master abort termination occurs in response to
+** 05           0b                   Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 
+**									when a master abort termination occurs in response to 
 **										a delayed transaction initiated by bridge on the target bus.
 **                                                            0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,
 **										and returns FFFF FFFFh when a read.
-**                                                            1b=When the transaction had not yet been completed on the initiator bus
-**										(e.g.,delayed reads, or non-posted writes),
-**                                                                 then bridge returns a Target Abort in response to the original requester
-**                                                                 when it returns looking for its delayed completion on the initiator bus.
-**                                                                 When the transaction had completed on the initiator bus (e.g., a PMW),
+**                                                            1b=When the transaction had not yet been completed on the initiator bus 
+**										(e.g.,delayed reads, or non-posted writes), 
+**                                                                 then bridge returns a Target Abort in response to the original requester 
+**                                                                 when it returns looking for its delayed completion on the initiator bus. 
+**                                                                 When the transaction had completed on the initiator bus (e.g., a PMW), 
 **										then bridge asserts P_SERR# (when enabled).
-**                                   For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort
+**                                   For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 
 **								while attempting to deliver a posted memory write on the destination bus.
-** 04           0b                   VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit
-**								(also of this register),
-**                                                            and the VGA Palette Snoop Enable bit (Command Register).
-**                                                            When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b)
+** 04           0b                   VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 
+**								(also of this register), 
+**                                                            and the VGA Palette Snoop Enable bit (Command Register). 
+**                                                            When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 
 **									the VGA Aliasing bit for the corresponding enabled functionality,:
 **                                                            0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses.
 **                                                            1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses.
-**                                   When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b),
+**                                   When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 
 **									then this bit has no impact on bridge behavior.
 ** 03           0b                                VGA Enable: Setting this bit enables address decoding
-**								 and transaction forwarding of the following VGA transactions from the primary bus
+**								 and transaction forwarding of the following VGA transactions from the primary bus 
 **									to the secondary bus:
-**                                                            frame buffer memory addresses 000A0000h:000BFFFFh,
+**                                                            frame buffer memory addresses 000A0000h:000BFFFFh, 
 **									VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=¡§0000h?**									?and AD[15:10] are either not decoded (i.e., don't cares),
 **										 or must be ¡§000000b¡¨
 **                                                            depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register)
-**                                                            I/O and Memory Enable bits must be set in the Command register
+**                                                            I/O and Memory Enable bits must be set in the Command register 
 **										to enable forwarding of VGA cycles.
-** 02           0b                                ISA Enable: Setting this bit enables special handling
-**								for the forwarding of ISA I/O transactions that fall within the address range
-**									specified by the I/O Base and Limit registers,
-**										and are within the lowest 64Kbyte of the I/O address map
+** 02           0b                                ISA Enable: Setting this bit enables special handling 
+**								for the forwarding of ISA I/O transactions that fall within the address range 
+**									specified by the I/O Base and Limit registers, 
+**										and are within the lowest 64Kbyte of the I/O address map 
 **											(i.e., 0000 0000h - 0000 FFFFh).
-**                                                            0b=All I/O transactions that fall within the I/O Base
-**										and Limit registers' specified range are forwarded
+**                                                            0b=All I/O transactions that fall within the I/O Base 
+**										and Limit registers' specified range are forwarded 
 **											from primary to secondary unfiltered.
-**                                                            1b=Blocks the forwarding from primary to secondary
-**											of the top 768 bytes of each 1Kbyte alias.
-**												On the secondary the top 768 bytes of each 1K alias
-**													are inversely decoded and forwarded
+**                                                            1b=Blocks the forwarding from primary to secondary 
+**											of the top 768 bytes of each 1Kbyte alias. 
+**												On the secondary the top 768 bytes of each 1K alias 
+**													are inversely decoded and forwarded 
 **														from secondary to primary.
 ** 01           0b                      SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion.
-**                                                            1b=The bridge asserts P_SERR# whenever S_SERR# is detected
+**                                                            1b=The bridge asserts P_SERR# whenever S_SERR# is detected 
 **									asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
-** 00           0b                     Parity Error Response: This bit controls bridge response to a parity error
+** 00           0b                     Parity Error Response: This bit controls bridge response to a parity error 
 **										that is detected on its secondary interface.
-**                                                            0b=When a data parity error is detected bridge does not assert S_PERR#.
-**                                                            Also bridge does not assert P_SERR# in response to a detected address
+**                                                            0b=When a data parity error is detected bridge does not assert S_PERR#. 
+**                                                            Also bridge does not assert P_SERR# in response to a detected address 
 **										or attribute parity error.
-**                                                            1b=When a data parity error is detected bridge asserts S_PERR#.
-**										The bridge also asserts P_SERR# (when enabled globally via bit(8)
+**                                                            1b=When a data parity error is detected bridge asserts S_PERR#. 
+**										The bridge also asserts P_SERR# (when enabled globally via bit(8) 
 **											of the Command register)
 **                                                            in response to a detected address or attribute parity error.
 **==============================================================================
 */
-#define     ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG	                     0x3E    /*word*/
+#define     ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG	                     0x3E    /*word*/ 
 /*
 **************************************************************************
 **                  Device Specific Registers 40-A7h
@@ -1619,11 +1790,11 @@ struct SENSE_DATA {
 **==============================================================================
 **  0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
 ** Bit       Default                       Description
-** 15:12      1111b                  Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule
-**							(PCI=16 clocks,PCI-X=6 clocks).
+** 15:12      1111b                  Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 
+**							(PCI=16 clocks,PCI-X=6 clocks). 
 **                                   Note that this field is only meaningful when:
-**                                                              # Bit[11] of this register is set to 1b,
-**									indicating that a Grant Time-out violation had occurred.
+**                                                              # Bit[11] of this register is set to 1b, 
+**									indicating that a Grant Time-out violation had occurred. 
 **                                                              # bridge internal arbiter is enabled.
 **                                           Bits[15:12] Violating Agent (REQ#/GNT# pair number)
 **                                                 0000b REQ#/GNT#[0]
@@ -1633,55 +1804,55 @@ struct SENSE_DATA {
 **                                                 1111b Default Value (no violation detected)
 **                                   When bit[11] is cleared by software, this field reverts back to its default value.
 **                                   All other values are Reserved
-** 11            0b                  Grant Time-out Occurred: When set to 1b,
+** 11            0b                  Grant Time-out Occurred: When set to 1b, 
 **                                   this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents.
 **                                   Software clears this bit by writing a 1b to it.
 ** 10            0b                      Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus.
-**                                                            1=During bus idle, bridge parks the bus on itself.
+**                                                            1=During bus idle, bridge parks the bus on itself. 
 **									The bus grant is removed from the last master and internally asserted to bridge.
 ** 09:08        00b                          Reserved
-** 07:00      0000 0000b  Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority.
-**                                                                      Each bit of this field assigns its corresponding secondary
-**										bus master to either the high priority arbiter ring (1b)
-**											or to the low priority arbiter ring (0b).
-**                                                                      Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively.
-**                                                                      Bit [6] corresponds to the bridge internal secondary bus request
-**										while Bit [7] corresponds to the SATU secondary bus request.
+** 07:00      0000 0000b  Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 
+**                                                                      Each bit of this field assigns its corresponding secondary 
+**										bus master to either the high priority arbiter ring (1b) 
+**											or to the low priority arbiter ring (0b). 
+**                                                                      Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 
+**                                                                      Bit [6] corresponds to the bridge internal secondary bus request 
+**										while Bit [7] corresponds to the SATU secondary bus request. 
 **                                                                      Bits [5:4] are unused.
 **                                                                      0b=Indicates that the master belongs to the low priority group.
 **                                                                      1b=Indicates that the master belongs to the high priority group
 **=================================================================================
 **  0x43: Bridge Control Register 0 - BCR0
 ** Bit       Default                       Description
-** 07           0b                  Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight
+** 07           0b                  Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 
 **									and the Posted Write data is limited to 4KB.
-**                                                            1=Operation in fully dynamic queue mode. The bridge enqueues up to
+**                                                            1=Operation in fully dynamic queue mode. The bridge enqueues up to 
 **									14 Posted Memory Write transactions and 8KB of posted write data.
 ** 06:03        0H                          Reserved.
-** 02           0b                 Upstream Prefetch Disable: This bit disables bridge ability
-**									to perform upstream prefetch operations for Memory
-**										Read requests received on its secondary interface.
-**                                 This bit also controls the bridge's ability to generate advanced read commands
-**								when forwarding a Memory Read Block transaction request upstream from a PCI-X bus
+** 02           0b                 Upstream Prefetch Disable: This bit disables bridge ability 
+**									to perform upstream prefetch operations for Memory 
+**										Read requests received on its secondary interface. 
+**                                 This bit also controls the bridge's ability to generate advanced read commands 
+**								when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 
 **										to a Conventional PCI bus.
 **                                 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory.
 **										The use of Memory Read Line and Memory Read
-**                                      Multiple is enabled when forwarding a PCI-X Memory Read Block request
+**                                      Multiple is enabled when forwarding a PCI-X Memory Read Block request 
 **										to an upstream bus operating in Conventional PCI mode.
-**                                 1b=bridge treats upstream PCI Memory Read requests as though
-**									they target non-prefetchable memory and forwards upstream PCI-X Memory
-**											Read Block commands as Memory Read
-**												when the primary bus is operating
+**                                 1b=bridge treats upstream PCI Memory Read requests as though 
+**									they target non-prefetchable memory and forwards upstream PCI-X Memory 
+**											Read Block commands as Memory Read 
+**												when the primary bus is operating 
 **													in Conventional PCI mode.
-**                                 NOTE: This bit does not affect bridge ability to perform read prefetching
+**                                 NOTE: This bit does not affect bridge ability to perform read prefetching 
 **									when the received command is Memory Read Line or Memory Read Multiple.
 **=================================================================================
 **  0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
 ** Bit       Default                       Description
 ** 15:08    0000000b                         Reserved
-** 07:06         00b                   Alias Command Mapping: This two bit field determines how bridge handles PCI-X ¡§Alias¡¨ commands,
-**								specifically the Alias to Memory Read Block and Alias to Memory Write Block commands.
-**                                                            The three options for handling these alias commands are to either pass it as is,
+** 07:06         00b                   Alias Command Mapping: This two bit field determines how bridge handles PCI-X ¡§Alias¡¨ commands, 
+**								specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 
+**                                                            The three options for handling these alias commands are to either pass it as is, 
 **									re-map to the actual block memory read/write command encoding, or ignore
 **                                                            			the transaction forcing a Master Abort to occur on the Origination Bus.
 **                                                   Bit (7:6) Handling of command
@@ -1689,54 +1860,54 @@ struct SENSE_DATA {
 **                                                        0 1 Enqueue and forward the alias command code unaltered
 **                                                        1 0 Ignore the transaction, forcing Master Abort
 **                                                        1 1 Reserved
-** 05            1b                  Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions.
-**                                                            The watchdog timers are used to detect prohibitively long latencies in the system.
-**                                                            The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request,
-**                                                            or Split Requests (PCI-X mode) is not completed within 2 24 events
-**                                                            (¡§events¡¨ are defined as PCI Clocks when operating in PCI-X mode,
+** 05            1b                  Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 
+**                                                            The watchdog timers are used to detect prohibitively long latencies in the system. 
+**                                                            The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 
+**                                                            or Split Requests (PCI-X mode) is not completed within 2 24 events 
+**                                                            (¡§events¡¨ are defined as PCI Clocks when operating in PCI-X mode, 
 **								and as the number of times being retried when operating in Conventional PCI mode)
 **                                                            0b=All 2 24 watchdog timers are enabled.
-**                                                            1b=All 2 24 watchdog timers are disabled and there is no limits to
-**									the number of attempts bridge makes when initiating a PMW,
-**                                                                 transacting a Delayed Transaction, or how long it waits for
+**                                                            1b=All 2 24 watchdog timers are disabled and there is no limits to 
+**									the number of attempts bridge makes when initiating a PMW, 
+**                                                                 transacting a Delayed Transaction, or how long it waits for 
 **									a split completion corresponding to one of its requests.
-** 04            0b                  GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism.
+** 04            0b                  GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 
 **                                                            Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X.
-**                                                            0b=The Secondary bus arbiter times out an agent
-**									that does not assert FRAME# within 16/6 clocks of receiving its grant,
-**										once the bus has gone idle.
-**                                                                 The time-out counter begins as soon as the bus goes idle with the new GNT# asserted.
-**                                                                 An infringing agent does not receive a subsequent GNT#
+**                                                            0b=The Secondary bus arbiter times out an agent 
+**									that does not assert FRAME# within 16/6 clocks of receiving its grant, 
+**										once the bus has gone idle. 
+**                                                                 The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 
+**                                                                 An infringing agent does not receive a subsequent GNT# 
 **									until it de-asserts its REQ# for at least one clock cycle.
 **                                                            1b=GNT# time-out mechanism is disabled.
 ** 03           00b                           Reserved.
 ** 02            0b          Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism.
-**                                                            The time out mechanism is used to ensure that initiators
-**									of delayed transactions return for their delayed completion data/status
+**                                                            The time out mechanism is used to ensure that initiators 
+**									of delayed transactions return for their delayed completion data/status 
 **										within a reasonable amount of time after it is available from bridge.
-**                                                            0b=The secondary master time-out counter is enabled
-**										and uses the value specified by the Secondary Discard Timer bit
+**                                                            0b=The secondary master time-out counter is enabled 
+**										and uses the value specified by the Secondary Discard Timer bit 
 **											(see Bridge Control Register).
-**                                                            1b=The secondary master time-out counter is disabled.
-**											The bridge waits indefinitely for a secondary bus master
+**                                                            1b=The secondary master time-out counter is disabled. 
+**											The bridge waits indefinitely for a secondary bus master 
 **												to repeat a delayed transaction.
-** 01            0b            Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism.
-**								The time out mechanism is used to ensure that initiators
-**									of delayed transactions return for their delayed completion data/status
+** 01            0b            Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 
+**								The time out mechanism is used to ensure that initiators 
+**									of delayed transactions return for their delayed completion data/status 
 **										within a reasonable amount of time after it is available from bridge.
-**                                                            0b=The primary master time-out counter is enabled and uses the value specified
+**                                                            0b=The primary master time-out counter is enabled and uses the value specified 
 **									by the Primary Discard Timer bit (see Bridge Control Register).
-**                                                            1b=The secondary master time-out counter is disabled.
-**									The bridge waits indefinitely for a secondary bus master
+**                                                            1b=The secondary master time-out counter is disabled. 
+**									The bridge waits indefinitely for a secondary bus master 
 **										to repeat a delayed transaction.
 ** 00            0b                           Reserved
 **=================================================================================
 **  0x47-0x46: Bridge Control Register 2 - BCR2
 ** Bit       Default                       Description
 ** 15:07      0000b                          Reserved.
-** 06            0b Global Clock Out Disable (External Secondary Bus Clock Source Enable):
-**									This bit disables all of the secondary PCI clock outputs including
-**										the feedback clock S_CLKOUT.
+** 06            0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 
+**									This bit disables all of the secondary PCI clock outputs including 
+**										the feedback clock S_CLKOUT. 
 **                                                            This means that the user is required to provide an S_CLKIN input source.
 ** 05:04        11 (66 MHz)                  Preserved.
 **              01 (100 MHz)
@@ -1747,83 +1918,83 @@ struct SENSE_DATA {
 **                                        secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0])
 **                                        default to being enabled following the rising edge of P_RST#, depending on the
 **                                        frequency of the secondary bus clock:
-**                                               ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with
+**                                               ¡E Designs with 100 MHz (or lower) Secondary PCI clock power up with 
 **								all four S_CLKOs enabled by default. (SCLKO[3:0])¡P
-**                                               ¡E Designs with 133 MHz Secondary PCI clock power up
-**								with the lower order 3 S_CLKOs enabled by default.
-**								(S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected
+**                                               ¡E Designs with 133 MHz Secondary PCI clock power up 
+**								with the lower order 3 S_CLKOs enabled by default. 
+**								(S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 
 **								to downstream device clock inputs.
 **=================================================================================
 **  0x49-0x48: Bridge Status Register - BSR
 ** Bit       Default                       Description
-** 15           0b  Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
+** 15           0b  Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 
 **									is conditionally asserted when the secondary discard timer expires.
-** 14           0b  Upstream Delayed/Split Read Watchdog Timer Expired:
+** 14           0b  Upstream Delayed/Split Read Watchdog Timer Expired: 
 **                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR#
 **									is conditionally asserted when bridge discards an upstream delayed read **	**									transaction request after 2 24 retries following the initial retry.
-**                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
-**									when bridge discards an upstream split read request
-**									after waiting in excess of 2 24 clocks for the corresponding
+**                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 
+**									when bridge discards an upstream split read request 
+**									after waiting in excess of 2 24 clocks for the corresponding 
 **									Split Completion to arrive.
-** 13           0b Upstream Delayed/Split Write Watchdog Timer Expired:
-**                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR#
+** 13           0b Upstream Delayed/Split Write Watchdog Timer Expired: 
+**                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# 
 **									is conditionally asserted when bridge discards an upstream delayed write **	**									transaction request after 2 24 retries following the initial retry.
-**                                                                PCI-X Mode: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when bridge discards an upstream split write request **									after waiting in excess of 2 24 clocks for the corresponding
+**                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# 
+**									is conditionally asserted when bridge discards an upstream split write request **									after waiting in excess of 2 24 clocks for the corresponding 
 **									Split Completion to arrive.
-** 12           0b           Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when a Master Abort occurs as a result of an attempt,
+** 12           0b           Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 
+**									is conditionally asserted when a Master Abort occurs as a result of an attempt, 
 **									by bridge, to retire a PMW upstream.
-** 11           0b           Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR#
+** 11           0b           Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 
 **									is conditionally asserted when a Target Abort occurs as a result of an attempt,
 **									by bridge, to retire a PMW upstream.
-** 10           0b                Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when bridge discards an upstream PMW transaction
+** 10           0b                Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 
+**									is conditionally asserted when bridge discards an upstream PMW transaction 
 **									after receiving 2 24 target retries from the primary bus target
-** 09           0b             Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when a data parity error is detected by bridge
+** 09           0b             Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 
+**									is conditionally asserted when a data parity error is detected by bridge 
 **									while attempting to retire a PMW upstream
-** 08           0b                  Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when bridge detects an address parity error on
+** 08           0b                  Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 
+**									is conditionally asserted when bridge detects an address parity error on 
 **									the secondary bus.
-** 07           0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR#
+** 07           0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 
 **									is conditionally asserted when the primary bus discard timer expires.
 ** 06           0b Downstream Delayed/Split Read Watchdog Timer Expired:
-**                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR#
+**                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# 
 **									is conditionally asserted when bridge discards a downstream delayed read **	**										transaction request after receiving 2 24 target retries
 **											 from the secondary bus target.
-**                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
-**										when bridge discards a downstream split read request
-**											after waiting in excess of 2 24 clocks for the corresponding
+**                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 
+**										when bridge discards a downstream split read request 
+**											after waiting in excess of 2 24 clocks for the corresponding 
 **												Split Completion to arrive.
 ** 05           0b Downstream Delayed Write/Split Watchdog Timer Expired:
-**                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted
-**									when bridge discards a downstream delayed write transaction request
+**                                                     Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 
+**									when bridge discards a downstream delayed write transaction request 
 **										after receiving 2 24 target retries from the secondary bus target.
-**                                                                PCI-X Mode: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when bridge discards a downstream
-**										split write request after waiting in excess of 2 24 clocks
+**                                                                PCI-X Mode: This bit is set to a 1b and P_SERR# 
+**									is conditionally asserted when bridge discards a downstream 
+**										split write request after waiting in excess of 2 24 clocks 
 **											for the corresponding Split Completion to arrive.
-** 04           0b          Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when a Master Abort occurs as a result of an attempt,
+** 04           0b          Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 
+**									is conditionally asserted when a Master Abort occurs as a result of an attempt, 
 **										by bridge, to retire a PMW downstream.
-** 03           0b          Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted
-**										when a Target Abort occurs as a result of an attempt, by bridge,
+** 03           0b          Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 
+**										when a Target Abort occurs as a result of an attempt, by bridge, 
 **											to retire a PMW downstream.
 ** 02           0b               Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when bridge discards a downstream PMW transaction
+**									is conditionally asserted when bridge discards a downstream PMW transaction 
 **										after receiving 2 24 target retries from the secondary bus target
-** 01           0b            Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR#
-**									is conditionally asserted when a data parity error is detected by bridge
+** 01           0b            Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 
+**									is conditionally asserted when a data parity error is detected by bridge 
 **										while attempting to retire a PMW downstream.
-** 00           0b                     Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted
+** 00           0b                     Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 
 **										when bridge detects an address parity error on the primary bus.
 **==================================================================================
 **  0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
 ** Bit       Default                       Description
 ** 15:13       000b                          Reserved
-** 12:10       000b                          GRANT# Duration: This field specifies the count (PCI clocks)
-**							that a secondary bus master has its grant maintained in order to enable
+** 12:10       000b                          GRANT# Duration: This field specifies the count (PCI clocks) 
+**							that a secondary bus master has its grant maintained in order to enable 
 **								multiple transactions to execute within the same arbitration cycle.
 **                                                    Bit[02:00] GNT# Extended Duration
 **                                                               000 MTT Disabled (Default=no GNT# extension)
@@ -1835,62 +2006,62 @@ struct SENSE_DATA {
 **                                                               110 Invalid (treated as 000)
 **                                                               111 Invalid (treated as 000)
 ** 09:08        00b                          Reserved
-** 07:00        FFh                                 MTT Mask: This field enables/disables MTT usage for each REQ#/GNT#
-**								pair supported by bridge secondary arbiter.
+** 07:00        FFh                                 MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 
+**								pair supported by bridge secondary arbiter. 
 **                                                            Bit(7) corresponds to SATU internal REQ#/GNT# pair,
-**                                                            bit(6) corresponds to bridge internal REQ#/GNT# pair,
+**                                                            bit(6) corresponds to bridge internal REQ#/GNT# pair, 
 **                                                            bit(5) corresponds to REQ#/GNT#(5) pair, etc.
-**                                                  When a given bit is set to 1b, its corresponding REQ#/GNT#
+**                                                  When a given bit is set to 1b, its corresponding REQ#/GNT# 
 **								pair is enabled for MTT functionality as determined by bits(12:10) of this register.
 **                                                  When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT.
 **==================================================================================
 **  0x53-0x52: Read Prefetch Policy Register - RPPR
 ** Bit       Default                       Description
-** 15:13       000b                    ReRead_Primary Bus: 3-bit field indicating the multiplication factor
-**							to be used in calculating the number of bytes to prefetch from the secondary bus interface on **								subsequent PreFetch operations given that the read demands were not satisfied
+** 15:13       000b                    ReRead_Primary Bus: 3-bit field indicating the multiplication factor 
+**							to be used in calculating the number of bytes to prefetch from the secondary bus interface on **								subsequent PreFetch operations given that the read demands were not satisfied 
 **									using the FirstRead parameter.
-**                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
+**                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 
 **							Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines
-** 12:10       000b                 FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating
-**							the number of bytes to prefetch from the secondary bus interface
+** 12:10       000b                 FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 
+**							the number of bytes to prefetch from the secondary bus interface 
 **								on the initial PreFetch operation.
-**                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs
+**                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 
 **								Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
-** 09:07       010b                  ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
-**								in calculating the number of bytes to prefetch from the primary
-**									bus interface on subsequent PreFetch operations given
-**										that the read demands were not satisfied using
+** 09:07       010b                  ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 
+**								in calculating the number of bytes to prefetch from the primary 
+**									bus interface on subsequent PreFetch operations given 
+**										that the read demands were not satisfied using 
 **											the FirstRead parameter.
 **                                           The default value of 010b correlates to: Command Type Hardwired pre-fetch a
-**							mount Memory Read 3 cache lines Memory Read Line 3 cache lines
+**							mount Memory Read 3 cache lines Memory Read Line 3 cache lines 
 **								Memory Read Multiple 6 cache lines
-** 06:04       000b               FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used
-**							in calculating the number of bytes to prefetch from
+** 06:04       000b               FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 
+**							in calculating the number of bytes to prefetch from 
 **								the primary bus interface on the initial PreFetch operation.
-**                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount
+**                                           The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 
 **							Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines
-** 03:00      1111b                Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch
+** 03:00      1111b                Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 
 **							algorithm for the secondary and the primary bus interfaces.
 **                                                         Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual
-**                                                                            enable bits for REQ#/GNT#[2:0].
+**                                                                            enable bits for REQ#/GNT#[2:0]. 
 **							  (bit(2) is the enable bit for REQ#/GNT#[2], etc...)
 **                                                                            1b: enables the staged pre-fetch feature
 **                                                                            0b: disables staged pre-fetch,
-**                                                         and hardwires read pre-fetch policy to the following for
-**                                                         Memory Read,
-**                                                         Memory Read Line,
-**                                                     and Memory Read Multiple commands:
+**                                                         and hardwires read pre-fetch policy to the following for 
+**                                                         Memory Read, 
+**                                                         Memory Read Line, 
+**                                                     and Memory Read Multiple commands: 
 **                                                     Command Type Hardwired Pre-Fetch Amount...
 **                                                                                      Memory Read 4 DWORDs
 **                                                                                      Memory Read Line 1 cache line
 **                                                                                      Memory Read Multiple 2 cache lines
-** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands
-** only to the next higher cache line boundary.For non-cache line aligned Memory Read
+** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 
+** only to the next higher cache line boundary.For non-cache line aligned Memory Read 
 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
 **==================================================================================
 **  0x55-0x54: P_SERR# Assertion Control - SERR_CTL
 ** Bit       Default                       Description
-**  15          0b   Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior
+**  15          0b   Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 
 ** 						in response to its discarding of a delayed transaction that was initiated from the primary bus.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
@@ -1900,27 +2071,27 @@ struct SENSE_DATA {
 **  13          0b   Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  12          0b             Master Abort during Upstream Posted Write: Dictates bridge behavior following
+**  12          0b             Master Abort during Upstream Posted Write: Dictates bridge behavior following 
 **						its having detected a Master Abort while attempting to retire one of its PMWs upstream.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  11          0b             Target Abort during Upstream Posted Write: Dictates bridge behavior following
+**  11          0b             Target Abort during Upstream Posted Write: Dictates bridge behavior following 
 **						its having been terminated with Target Abort while attempting to retire one of its PMWs upstream.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  10          0b                  Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that
+**  10          0b                  Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 
 **						it discards an upstream posted write transaction.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  09          0b               Upstream Posted Write Data Parity Error: Dictates bridge behavior
+**  09          0b               Upstream Posted Write Data Parity Error: Dictates bridge behavior 
 **						when a data parity error is detected while attempting to retire on of its PMWs upstream.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  08          0b                    Secondary Bus Address Parity Error: This bit dictates bridge behavior
+**  08          0b                    Secondary Bus Address Parity Error: This bit dictates bridge behavior 
 **						when it detects an address parity error on the secondary bus.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  07          0b  Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to
+**  07          0b  Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 
 **						its discarding of a delayed transaction that was initiated on the secondary bus.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
@@ -1930,23 +2101,23 @@ struct SENSE_DATA {
 **  05          0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  04          0b           Master Abort during Downstream Posted Write: Dictates bridge behavior following
+**  04          0b           Master Abort during Downstream Posted Write: Dictates bridge behavior following 
 **						its having detected a Master Abort while attempting to retire one of its PMWs downstream.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  03          0b           Target Abort during Downstream Posted Write: Dictates bridge behavior following
+**  03          0b           Target Abort during Downstream Posted Write: Dictates bridge behavior following 
 **						its having been terminated with Target Abort while attempting to retire one of its PMWs downstream.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  02          0b                Downstream Posted Write Data Discarded: Dictates bridge behavior in the event
+**  02          0b                Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 
 **						that it discards a downstream posted write transaction.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  01          0b             Downstream Posted Write Data Parity Error: Dictates bridge behavior
+**  01          0b             Downstream Posted Write Data Parity Error: Dictates bridge behavior 
 **						when a data parity error is detected while attempting to retire on of its PMWs downstream.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
-**  00          0b                      Primary Bus Address Parity Error: This bit dictates bridge behavior
+**  00          0b                      Primary Bus Address Parity Error: This bit dictates bridge behavior 
 **						when it detects an address parity error on the primary bus.
 **                                                                       0b=bridge asserts P_SERR#.
 **                                                                       1b=bridge does not assert P_SERR#
@@ -1957,7 +2128,7 @@ struct SENSE_DATA {
 ** 06           -                          							 Reserved - value indeterminate
 ** 05:02        0                          							 Reserved
 ** 01      Varies with External State of S_133EN at PCI Bus Reset    Secondary Bus Max Frequency Setting:
-**									 This bit reflect captured S_133EN strap,
+**									 This bit reflect captured S_133EN strap, 
 **										indicating the maximum secondary bus clock frequency when in PCI-X mode.
 **                                                                   Max Allowable Secondary Bus Frequency
 **																			**						S_133EN PCI-X Mode
@@ -1968,61 +2139,61 @@ struct SENSE_DATA {
 **  0x59-0x58: Secondary Decode Enable Register - SDER
 ** Bit       Default                       							Description
 ** 15:03      FFF1h                        							 Preserved.
-** 02     Varies with External State of PRIVMEM at PCI Bus Reset   Private Memory Space Enable - when set,
+** 02     Varies with External State of PRIVMEM at PCI Bus Reset   Private Memory Space Enable - when set, 
 **									bridge overrides its secondary inverse decode logic and not
 **                                                                 forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b.
-**                                                                 This creates a private memory space on the Secondary PCI bus
+**                                                                 This creates a private memory space on the Secondary PCI bus 
 **									that allows peer-to-peer transactions.
 ** 01:00      10 2                                                   Preserved.
 **===============================================================================
 **  0x5D-0x5C: Secondary IDSEL Select Register - SISR
 ** Bit       Default                       							Description
 ** 15:10     000000 2                      							 Reserved.
-** 09    Varies with External State of PRIVDEV at PCI Bus Reset     AD25- IDSEL Disable - When this bit is set,
+** 09    Varies with External State of PRIVDEV at PCI Bus Reset     AD25- IDSEL Disable - When this bit is set, 
 **							AD25 is deasserted for any possible Type 1 to Type 0 conversion.
-**                                                                                        When this bit is clear,
+**                                                                                        When this bit is clear, 
 **							AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion.
-** 08    Varies with External State of PRIVDEV at PCI Bus Reset     AD24- IDSEL Disable - When this bit is set,
+** 08    Varies with External State of PRIVDEV at PCI Bus Reset     AD24- IDSEL Disable - When this bit is set, 
 **							AD24 is deasserted for any possible Type 1 to Type 0 conversion.
-**                                                                                        When this bit is clear,
+**                                                                                        When this bit is clear, 
 **							AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion.
-** 07    Varies with External State of PRIVDEV at PCI Bus Reset     AD23- IDSEL Disable - When this bit is set,
-**							AD23 is deasserted for any possible Type 1 to Type 0 conversion.
-**                                                                                        When this bit is clear,
+** 07    Varies with External State of PRIVDEV at PCI Bus Reset     AD23- IDSEL Disable - When this bit is set, 
+**							AD23 is deasserted for any possible Type 1 to Type 0 conversion. 
+**                                                                                        When this bit is clear, 
 **							AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion.
-** 06    Varies with External State of PRIVDEV at PCI Bus Reset     AD22- IDSEL Disable - When this bit is set,
+** 06    Varies with External State of PRIVDEV at PCI Bus Reset     AD22- IDSEL Disable - When this bit is set, 
 **							AD22 is deasserted for any possible Type 1 to Type 0 conversion.
-**                                                                                        When this bit is clear,
+**                                                                                        When this bit is clear, 
 **							AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion.
-** 05    Varies with External State of PRIVDEV at PCI Bus Reset     AD21- IDSEL Disable - When this bit is set,
+** 05    Varies with External State of PRIVDEV at PCI Bus Reset     AD21- IDSEL Disable - When this bit is set, 
 **							AD21 is deasserted for any possible Type 1 to Type 0 conversion.
-**                                                                                        When this bit is clear,
+**                                                                                        When this bit is clear, 
 **							AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion.
-** 04    Varies with External State of PRIVDEV at PCI Bus Reset     AD20- IDSEL Disable - When this bit is set,
+** 04    Varies with External State of PRIVDEV at PCI Bus Reset     AD20- IDSEL Disable - When this bit is set, 
 **							AD20 is deasserted for any possible Type 1 to Type 0 conversion.
-**                                                                                        When this bit is clear,
+**                                                                                        When this bit is clear, 
 **							AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion.
-** 03    Varies with External State of PRIVDEV at PCI Bus Reset     AD19- IDSEL Disable - When this bit is set,
+** 03    Varies with External State of PRIVDEV at PCI Bus Reset     AD19- IDSEL Disable - When this bit is set, 
 **							AD19 is deasserted for any possible Type 1 to Type 0 conversion.
 **                                                                                        When this bit is clear,
 **							AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion.
-** 02    Varies with External State of PRIVDEV at PCI Bus Reset     AD18- IDSEL Disable - When this bit is set,
+** 02    Varies with External State of PRIVDEV at PCI Bus Reset     AD18- IDSEL Disable - When this bit is set, 
 **							AD18 is deasserted for any possible Type 1 to Type 0 conversion.
 **                                                                                        When this bit is clear,
 **							AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion.
-** 01    Varies with External State of PRIVDEV at PCI Bus Reset     AD17- IDSEL Disable - When this bit is set,
+** 01    Varies with External State of PRIVDEV at PCI Bus Reset     AD17- IDSEL Disable - When this bit is set, 
 **							AD17 is deasserted for any possible Type 1 to Type 0 conversion.
-**                                                                                        When this bit is clear,
+**                                                                                        When this bit is clear, 
 **							AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion.
-** 00    Varies with External State of PRIVDEV at PCI Bus Reset     AD16- IDSEL Disable - When this bit is set,
+** 00    Varies with External State of PRIVDEV at PCI Bus Reset     AD16- IDSEL Disable - When this bit is set, 
 **							AD16 is deasserted for any possible Type 1 to Type 0 conversion.
-**                                                                                        When this bit is clear,
+**                                                                                        When this bit is clear, 
 **							AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion.
 **************************************************************************
 */
 /*
 **************************************************************************
-**                 Reserved      A8-CBh
+**                 Reserved      A8-CBh           
 **************************************************************************
 */
 /*
@@ -2064,7 +2235,7 @@ struct SENSE_DATA {
 ** 15:11       00h                     PME Supported (PME): PME# cannot be asserted by bridge.
 ** 10           0h                 State D2 Supported (D2): Indicates no support for state D2. No power management action in this state.
 ** 09           1h                 State D1 Supported (D1): Indicates support for state D1. No power management action in this state.
-** 08:06        0h                Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.
+** 08:06        0h                Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 
 **                                                          This returns 000b as PME# wake-up for bridge is not implemented.
 ** 05           0   Special Initialization Required (SINT): Special initialization is not required for bridge.
 ** 04:03       00                            Reserved
@@ -2073,10 +2244,10 @@ struct SENSE_DATA {
 **  0xE1-0xE0: Power Management Control / Status - Register - PMCSR
 ** Bit       Default                       Description
 ** 15:09       00h                          Reserved
-** 08          0b                          PME_Enable: This bit, when set to 1b enables bridge to assert PME#.
+** 08          0b                          PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 
 **	Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
 ** 07:02       00h                          Reserved
-** 01:00       00                Power State (PSTATE): This 2-bit field is used both to determine the current power state of
+** 01:00       00                Power State (PSTATE): This 2-bit field is used both to determine the current power state of 
 **									a function and to set the Function into a new power state.
 **  													00 - D0 state
 **  													01 - D1 state
@@ -2086,7 +2257,7 @@ struct SENSE_DATA {
 **  0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
 ** Bit       Default                       Description
 ** 07          0         Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled.
-** 06          0                B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that
+** 06          0                B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 
 **									is to occur as a direct result of programming the function to D3 hot.
 **                                                                 This bit is only meaningful when bit 7 (BPCC_En) is a ¡§1¡¨.
 ** 05:00     00h                            Reserved
@@ -2107,7 +2278,7 @@ struct SENSE_DATA {
 **  0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
 ** Bit       Default                       Description
 ** 15:09       00h                          Reserved
-** 08:06       Xxx                Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus.
+** 08:06       Xxx                Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 
 **                                                                 The values are:
 ** 																			**		BitsMax FrequencyClock Period
 ** 																			**		000PCI ModeN/A
@@ -2120,14 +2291,14 @@ struct SENSE_DATA {
 ** 						secondary bus to the primary bus because there is not enough room within the limit
 ** 						specified in the Split Transaction Commitment Limit field in the Downstream Split
 ** 						Transaction Control register. The bridge does not set this bit.
-** 04           0b                 Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the **	**						secondary bus with retry or Disconnect at next ADB because its buffers are full.
+** 04           0b                 Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the **	**						secondary bus with retry or Disconnect at next ADB because its buffers are full. 
 **						The bridge does not set this bit.
-** 03           0b              Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID
+** 03           0b              Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 
 **						equal to bridge secondary bus number, device number 00h,
-**						and function number 0 is received on the secondary interface.
+**						and function number 0 is received on the secondary interface. 
 **						This bit is cleared by software writing a '1'.
-** 02           0b               Split Completion Discarded (SCD): This bit is set
-**						when bridge discards a split completion moving toward the secondary bus
+** 02           0b               Split Completion Discarded (SCD): This bit is set 
+**						when bridge discards a split completion moving toward the secondary bus 
 **						because the requester would not accept it. This bit cleared by software writing a '1'.
 ** 01           1b                                133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz
 ** 00           1b                            64-bit Device (D64): Indicates the width of the secondary bus as 64-bits.
@@ -2138,10 +2309,10 @@ struct SENSE_DATA {
 ** 21           0         							Split Request Delayed (SRD): This bit does not be set by bridge.
 ** 20           0         							Split Completion Overrun (SCO): This bit does not be set by bridge
 **										because bridge throttles traffic on the completion side.
-** 19           0         							Unexpected Split Completion (USC): The bridge sets this bit to 1b
-**										when it encounters a corrupted Split Completion, possibly with an **	**										inconsistent remaining byte count.Software clears
+** 19           0         							Unexpected Split Completion (USC): The bridge sets this bit to 1b 
+**										when it encounters a corrupted Split Completion, possibly with an **	**										inconsistent remaining byte count.Software clears 
 **										this bit by writing a 1b to it.
-** 18           0         							Split Completion Discarded (SCD): The bridge sets this bit to 1b
+** 18           0         							Split Completion Discarded (SCD): The bridge sets this bit to 1b 
 **										when it has discarded a Split Completion.Software clears this bit by **	**										writing a 1b to it.
 ** 17           1         							133 MHz Capable: This bit indicates that the bridge primary interface is **										capable of 133 MHz operation in PCI-X mode.
 **										0=The maximum operating frequency is 66 MHz.
@@ -2149,10 +2320,10 @@ struct SENSE_DATA {
 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset    64-bit Device (D64): Indicates bus width of the Primary PCI bus interface.
 **										 0=Primary Interface is connected as a 32-bit PCI bus.
 **										 1=Primary Interface is connected as a 64-bit PCI bus.
-** 15:08       00h 								Bus Number (BNUM): This field is simply an alias to the PBN field
+** 15:08       00h 								Bus Number (BNUM): This field is simply an alias to the PBN field 
 **											of the BNUM register at offset 18h.
 **								Apparently it was deemed necessary reflect it here for diagnostic purposes.
-** 07:03       1fh						Device Number (DNUM): Indicates which IDSEL bridge consumes.
+** 07:03       1fh						Device Number (DNUM): Indicates which IDSEL bridge consumes. 
 **								May be updated whenever a PCI-X
 **								 configuration write cycle that targets bridge scores a hit.
 ** 02:00        0h                                                   Function Number (FNUM): The bridge Function #
@@ -2181,7 +2352,7 @@ struct SENSE_DATA {
 ** 15:00      003Eh              Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing
 **                                                                 split completions. This register controls behavior of the bridge buffers for forwarding
 **                                                                 Split Transactions from a primary bus requester to a secondary bus completer.
-**                                                                 The default value of 003Eh indicates there is available buffer space for 62 ADQs
+**                                                                 The default value of 003Eh indicates there is available buffer space for 62 ADQs 
 **									(7936 bytes).
 **************************************************************************
 */
@@ -2217,7 +2388,7 @@ struct SENSE_DATA {
 ** ----------------------------------------------------------------------------------------------------------
 ** |                               Inbound ATU Upper Base Address 2                                       | 24H
 ** ----------------------------------------------------------------------------------------------------------
-** |                                             Reserved                                                 | 28H
+** |                                             Reserved                                                 | 28H   
 ** ----------------------------------------------------------------------------------------------------------
 ** |                ATU Subsystem ID                 |                ATU Subsystem Vendor ID             | 2CH
 ** ----------------------------------------------------------------------------------------------------------
@@ -2236,9 +2407,9 @@ struct SENSE_DATA {
 **  ATU Vendor ID Register - ATUVID
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  15:00      8086H (0x17D3)               ATU Vendor ID - This is a 16-bit value assigned to Intel.
-**						This register, combined with the DID, uniquely identify the PCI device.
-**      Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID
+**  15:00      8086H (0x17D3)               ATU Vendor ID - This is a 16-bit value assigned to Intel. 
+**						This register, combined with the DID, uniquely identify the PCI device. 
+**      Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 
 **	to simulate the interface of a standard mechanism currently used by existing application software.
 ***********************************************************************************
 */
@@ -2248,7 +2419,7 @@ struct SENSE_DATA {
 **  ATU Device ID Register - ATUDID
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  15:00      0336H (0x1110)               ATU Device ID - This is a 16-bit value assigned to the ATU.
+**  15:00      0336H (0x1110)               ATU Device ID - This is a 16-bit value assigned to the ATU. 
 **	This ID, combined with the VID, uniquely identify any PCI device.
 ***********************************************************************************
 */
@@ -2262,29 +2433,29 @@ struct SENSE_DATA {
 **  10           0                          Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal.
 **                                                              0=enables the assertion of interrupt signal.
 **                                                              1=disables the assertion of its interrupt signal.
-**  09          0 2                         Fast Back to Back Enable - When cleared,
+**  09          0 2                         Fast Back to Back Enable - When cleared, 
 **						the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
 **						Ignored when operating in the PCI-X mode.
 **  08          0 2                         SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface.
 **  07          1 2                         Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The
-**                                          ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles
+**                                          ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 
 **						of address stepping for PCI-X mode.
-**  06          0 2                         Parity Error Response - When set, the ATU takes normal action when a parity error
+**  06          0 2                         Parity Error Response - When set, the ATU takes normal action when a parity error 
 **						is detected. When cleared, parity checking is disabled.
-**  05          0 2                         VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore,
+**  05          0 2                         VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 
 **						does not perform VGA palette snooping.
-**  04          0 2                         Memory Write and Invalidate Enable - When set, ATU may generate MWI commands.
+**  04          0 2                         Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 
 **						When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
-**  03          0 2                         Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way.
+**  03          0 2                         Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 
 **						Not implemented and a reserved bit field.
-**  02          0 2                         Bus Master Enable - The ATU interface can act as a master on the PCI bus.
-**						When cleared, disables the device from generating PCI accesses.
+**  02          0 2                         Bus Master Enable - The ATU interface can act as a master on the PCI bus. 
+**						When cleared, disables the device from generating PCI accesses. 
 **						When set, allows the device to behave as a PCI bus master.
-**                                          When operating in the PCI-X mode, ATU initiates a split completion transaction regardless
+**                                          When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 
 **						of the state of this bit.
-**  01          0 2                         Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses.
+**  01          0 2                         Memory Enable - Controls the ATU interface¡¦s response to PCI memory addresses. 
 **						When cleared, the ATU interface does not respond to any memory access on the PCI bus.
-**  00          0 2                         I/O Space Enable - Controls the ATU interface response to I/O transactions.
+**  00          0 2                         I/O Space Enable - Controls the ATU interface response to I/O transactions. 
 **						Not implemented and a reserved bit field.
 ***********************************************************************************
 */
@@ -2304,10 +2475,10 @@ struct SENSE_DATA {
 **                                          or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
 **  12          0 2                         Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target
 **                                          abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
-**  11          0 2                         Target Abort (target) - set when the ATU interface, acting as a target,
+**  11          0 2                         Target Abort (target) - set when the ATU interface, acting as a target, 
 **						terminates the transaction on the PCI bus with a target abort.
-**  10:09       01 2                        DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL#
-**						timing for a target device in Conventional PCI Mode regardless of the operating mode
+**  10:09       01 2                        DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 
+**						timing for a target device in Conventional PCI Mode regardless of the operating mode 
 **							(except configuration accesses).
 **  										00 2=Fast
 **  										01 2=Medium
@@ -2316,7 +2487,7 @@ struct SENSE_DATA {
 **                                          The ATU interface uses Medium timing.
 **  08           0 2                        Master Parity Error - The ATU interface sets this bit under the following conditions:
 **  										¡E The ATU asserted PERR# itself or the ATU observed PERR# asserted.
-**  										¡E And the ATU acted as the requester
+**  										¡E And the ATU acted as the requester 
 **											for the operation in which the error occurred.
 **  										¡E And the ATUCMD register¡¦s Parity Error Response bit is set
 **  										¡E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
@@ -2329,7 +2500,7 @@ struct SENSE_DATA {
 **  06           0 2                        UDF Supported - User Definable Features are not supported
 **  05           1 2                        66 MHz. Capable - 66 MHz operation is supported.
 **  04           1 2                        Capabilities - When set, this function implements extended capabilities.
-**  03             0                        Interrupt Status - reflects the state of the ATU interrupt
+**  03             0                        Interrupt Status - reflects the state of the ATU interrupt 
 **						when the Interrupt Disable bit in the command register is a 0.
 **  										0=ATU interrupt signal deasserted.
 **  										1=ATU interrupt signal asserted.
@@ -2402,24 +2573,24 @@ struct SENSE_DATA {
 **  the 80331 replying with the results from the software implementation of the BIST functionality.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  07           0 2                        BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit.
+**  07           0 2                        BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 
 **  06           0 2                        Start BIST - When the ATUCR BIST Interrupt Enable bit is set:
 **  				 Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function.
 **  				 The Intel XScale core clears this bit when the BIST software has completed with the BIST results
 **  				 found in ATUBISTR register bits [3:0].
 **  				 When the ATUCR BIST Interrupt Enable bit is clear:
-**  				 Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed.
+**  				 Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 
 **                                                       The Intel XScale core does not clear this bit.
 **  05:04       00 2             Reserved
 **  03:00     0000 2             BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6):
-**                               The Intel XScale  core places the results of the software BIST in these bits.
+**                               The Intel XScale  core places the results of the software BIST in these bits. 
 **				 A nonzero value indicates a device-specific error.
 ***********************************************************************************
 */
 #define     ARCMSR_ATU_BIST_REG		         0x0F    /*byte*/
 
 /*
-***************************************************************************************
+***************************************************************************************  
 **            ATU Base Registers and Associated Limit Registers
 ***************************************************************************************
 **           Base Address                         Register Limit                          Register Description
@@ -2434,10 +2605,10 @@ struct SENSE_DATA {
 **     NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH).
 **  Expansion ROM Base Address Register           Expansion ROM Limit Register            Defines the window of addresses used by a bus master for reading **  from an Expansion ROM.
 **--------------------------------------------------------------------------------------
-**  ATU Inbound Window 1 is not a translate window.
-**  The ATU does not claim any PCI accesses that fall within this range.
-**  This window is used to allocate host memory for use by Private Devices.
-**  When enabled, the ATU interrupts the Intel  XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus.
+**  ATU Inbound Window 1 is not a translate window. 
+**  The ATU does not claim any PCI accesses that fall within this range. 
+**  This window is used to allocate host memory for use by Private Devices. 
+**  When enabled, the ATU interrupts the Intel  XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 
 ***********************************************************************************
 */
 
@@ -2445,37 +2616,37 @@ struct SENSE_DATA {
 ***********************************************************************************
 **  Inbound ATU Base Address Register 0 - IABAR0
 **
-**  . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0)
-**    defines the block of memory addresses where the inbound translation window 0 begins.
-**  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
+**  . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 
+**    defines the block of memory addresses where the inbound translation window 0 begins. 
+**  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 **  . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size.
-**  . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0
-**    depending on the value located within the IALR0.
+**  . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 
+**    depending on the value located within the IALR0. 
 **    This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification.
 **    The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit.
-**    The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
-**  Warning:
+**    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
+**  Warning: 
 **    When IALR0 is cleared prior to host configuration:
-**                          the user should also clear the Prefetchable Indicator and the Type Indicator.
+**                          the user should also clear the Prefetchable Indicator and the Type Indicator. 
 **    Assuming IALR0 is not cleared:
 **                          a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
-**                             when the Prefetchable Indicator is cleared prior to host configuration,
+**                             when the Prefetchable Indicator is cleared prior to host configuration, 
 **                             the user should also set the Type Indicator for 32 bit addressability.
 **                          b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification,
 **                             when the Prefetchable Indicator is set prior to host configuration, the user
-**                             should also set the Type Indicator for 64 bit addressability.
+**                             should also set the Type Indicator for 64 bit addressability. 
 **                             This is the default for IABAR0.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Translation Base Address 0 - These bits define the actual location
+**  31:12     00000H                        Translation Base Address 0 - These bits define the actual location 
 **						the translation function is to respond to when addressed from the PCI bus.
 **  11:04        00H                        Reserved.
 **  03           1 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 **  02:01       10 2                        Type Indicator - Defines the width of the addressability for this memory window:
 **  						00 - Memory Window is locatable anywhere in 32 bit address space
 **  						10 - Memory Window is locatable anywhere in 64 bit address space
-**  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address.
-**                                                                   The ATU does not occupy I/O space,
+**  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
+**                                                                   The ATU does not occupy I/O space, 
 **                                                                   thus this bit must be zero.
 ***********************************************************************************
 */
@@ -2489,9 +2660,9 @@ struct SENSE_DATA {
 **  This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
 **  Together with the Translation Base Address this register defines the actual location the translation
 **  function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
-**  The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
-**  Note:
-**      When the Type indicator of IABAR0 is set to indicate 32 bit addressability,
+**  The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
+**  Note: 
+**      When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 
 **      the IAUBAR0 register attributes are read-only.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
@@ -2504,23 +2675,23 @@ struct SENSE_DATA {
 ***********************************************************************************
 **  Inbound ATU Base Address Register 1 - IABAR1
 **
-**  . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1)
-**    defines the block of memory addresses where the inbound translation window 1 begins.
+**  . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 
+**    defines the block of memory addresses where the inbound translation window 1 begins. 
 **  . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
-**  . The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
-**  . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus.
-**    Warning:
-**    When a non-zero value is not written to IALR1 prior to host configuration,
-**                          the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability.
+**  . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
+**  . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 
+**    Warning: 
+**    When a non-zero value is not written to IALR1 prior to host configuration, 
+**                          the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 
 **                          This is the default for IABAR1.
-**    Assuming a non-zero value is written to IALR1,
-**               			the user may set the Prefetchable Indicator
+**    Assuming a non-zero value is written to IALR1, 
+**               			the user may set the Prefetchable Indicator 
 **               			              or the Type         Indicator:
 **  						a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address
-**  						   boundary, when the Prefetchable Indicator is not set prior to host configuration,
-**                             the user should also leave the Type Indicator set for 32 bit addressability.
+**  						   boundary, when the Prefetchable Indicator is not set prior to host configuration, 
+**                             the user should also leave the Type Indicator set for 32 bit addressability. 
 **                             This is the default for IABAR1.
-**  						b. when the Prefetchable Indicator is set prior to host configuration,
+**  						b. when the Prefetchable Indicator is set prior to host configuration, 
 **                             the user should also set the Type Indicator for 64 bit addressability.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
@@ -2530,8 +2701,8 @@ struct SENSE_DATA {
 **  02:01       00 2                        Type Indicator - Defines the width of the addressability for this memory window:
 **  			00 - Memory Window is locatable anywhere in 32 bit address space
 **  			10 - Memory Window is locatable anywhere in 64 bit address space
-**  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address.
-**                                                                   The ATU does not occupy I/O space,
+**  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
+**                                                                   The ATU does not occupy I/O space, 
 **                                                                   thus this bit must be zero.
 ***********************************************************************************
 */
@@ -2540,20 +2711,20 @@ struct SENSE_DATA {
 ***********************************************************************************
 **  Inbound ATU Upper Base Address Register 1 - IAUBAR1
 **
-**  This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes.
-**  Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs).
+**  This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 
+**  Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 
 **  This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range.
 **  The programmed value within the base address register must comply with the PCI programming
-**  requirements for address alignment.
+**  requirements for address alignment. 
 **  When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written
-**  from the PCI bus.
-**  Note:
-**      When the Type indicator of IABAR1 is set to indicate 32 bit addressability,
-**      the IAUBAR1 register attributes are read-only.
+**  from the PCI bus. 
+**  Note: 
+**      When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 
+**      the IAUBAR1 register attributes are read-only. 
 **      This is the default for IABAR1.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:0      00000H                        Translation Upper Base Address 1 - Together with the Translation Base Address 1
+**  31:0      00000H                        Translation Upper Base Address 1 - Together with the Translation Base Address 1 
 **						these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes.
 ***********************************************************************************
 */
@@ -2562,37 +2733,37 @@ struct SENSE_DATA {
 ***********************************************************************************
 **  Inbound ATU Base Address Register 2 - IABAR2
 **
-**  . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2)
-**           defines the block of memory addresses where the inbound translation window 2 begins.
-**  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
+**  . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 
+**           defines the block of memory addresses where the inbound translation window 2 begins. 
+**  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 **  . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size
 **  . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2.
-**    The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
-**  Warning:
-**    When a non-zero value is not written to IALR2 prior to host configuration,
-**                          the user should not set either the Prefetchable Indicator
-**                                                      or the Type         Indicator for 64 bit addressability.
+**    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
+**  Warning: 
+**    When a non-zero value is not written to IALR2 prior to host configuration, 
+**                          the user should not set either the Prefetchable Indicator 
+**                                                      or the Type         Indicator for 64 bit addressability. 
 **                          This is the default for IABAR2.
-**  Assuming a non-zero value is written to IALR2,
-**                          the user may set the Prefetchable Indicator
+**  Assuming a non-zero value is written to IALR2, 
+**                          the user may set the Prefetchable Indicator 
 **                                        or the Type         Indicator:
-**  						a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
-**                             when the Prefetchable Indicator is not set prior to host configuration,
-**                             the user should also leave the Type Indicator set for 32 bit addressability.
+**  						a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 
+**                             when the Prefetchable Indicator is not set prior to host configuration, 
+**                             the user should also leave the Type Indicator set for 32 bit addressability. 
 **                             This is the default for IABAR2.
-**  						b. when the Prefetchable Indicator is set prior to host configuration,
+**  						b. when the Prefetchable Indicator is set prior to host configuration, 
 **                             the user should also set the Type Indicator for 64 bit addressability.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Translation Base Address 2 - These bits define the actual location
+**  31:12     00000H                        Translation Base Address 2 - These bits define the actual location 
 **						the translation function is to respond to when addressed from the PCI bus.
 **  11:04        00H                        Reserved.
 **  03           0 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
 **  02:01       00 2                        Type Indicator - Defines the width of the addressability for this memory window:
 **  			00 - Memory Window is locatable anywhere in 32 bit address space
 **  			10 - Memory Window is locatable anywhere in 64 bit address space
-**  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address.
-**                                                                   The ATU does not occupy I/O space,
+**  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address. 
+**                                                                   The ATU does not occupy I/O space, 
 **                                                                   thus this bit must be zero.
 ***********************************************************************************
 */
@@ -2602,18 +2773,18 @@ struct SENSE_DATA {
 **  Inbound ATU Upper Base Address Register 2 - IAUBAR2
 **
 **  This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
-**  Together with the Translation Base Address this register defines the actual location
+**  Together with the Translation Base Address this register defines the actual location 
 **  the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
 **  The programmed value within the base address register must comply with the PCI programming
 **  requirements for address alignment.
-**  Note:
+**  Note: 
 **      When the Type indicator of IABAR2 is set to indicate 32 bit addressability,
-**      the IAUBAR2 register attributes are read-only.
+**      the IAUBAR2 register attributes are read-only. 
 **      This is the default for IABAR2.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:0      00000H                        Translation Upper Base Address 2 - Together with the Translation Base Address 2
-**                                          these bits define the actual location the translation function is to respond to
+**  31:0      00000H                        Translation Upper Base Address 2 - Together with the Translation Base Address 2 
+**                                          these bits define the actual location the translation function is to respond to 
 **                                          when addressed from the PCI bus for addresses > 4GBytes.
 ***********************************************************************************
 */
@@ -2641,27 +2812,27 @@ struct SENSE_DATA {
 **  Expansion ROM Base Address Register -ERBAR
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Expansion ROM Base Address - These bits define the actual location
+**  31:12     00000H                        Expansion ROM Base Address - These bits define the actual location 
 **						where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary.
 **  11:01     000H                          Reserved
-**  00        0 2                           Address Decode Enable - This bit field shows the ROM address
+**  00        0 2                           Address Decode Enable - This bit field shows the ROM address 
 **						decoder is enabled or disabled. When cleared, indicates the address decoder is disabled.
 ***********************************************************************************
 */
 #define     ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG		         0x30    /*dword 0x33,0x32,0v31,0x30*/
-#define     ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE   		     0x01
+#define     ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE   		     0x01    
 /*
 ***********************************************************************************
 **  ATU Capabilities Pointer Register - ATU_CAP_PTR
 **  -----------------------------------------------------------------
 **  Bit Default Description
-**  07:00     C0H                           Capability List Pointer - This provides an offset in this function¡¦s configuration space
+**  07:00     C0H                           Capability List Pointer - This provides an offset in this function¡¦s configuration space 
 **						that points to the 80331 PCl Bus Power Management extended capability.
 ***********************************************************************************
 */
 #define     ARCMSR_ATU_CAPABILITY_PTR_REG		     0x34    /*byte*/
 /*
-***********************************************************************************
+***********************************************************************************  
 **  Determining Block Sizes for Base Address Registers
 **  The required address size and type can be determined by writing ones to a base address register and
 **  reading from the registers. By scanning the returned value from the least-significant bit of the base
@@ -2711,7 +2882,7 @@ struct SENSE_DATA {
 **  FFFC0000H 256K
 **  FFF80000H 512K
 **
-***************************************************************************************
+***************************************************************************************  
 */
 
 
@@ -2722,7 +2893,7 @@ struct SENSE_DATA {
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
 **  07:00       FFH                         Interrupt Assigned - system-assigned value identifies which system interrupt controller¡¦s interrupt
-**                                                               request line connects to the device's PCI interrupt request lines
+**                                                               request line connects to the device's PCI interrupt request lines 
 **								(as specified in the interrupt pin register).
 **                                                               A value of FFH signifies ¡§no connection¡¨ or ¡§unknown¡¨.
 ***********************************************************************************
@@ -2751,7 +2922,7 @@ struct SENSE_DATA {
 **  ATU Maximum Latency Register - ATUMLAT
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  07:00       00H                         Specifies frequency (how often) the device needs to access the PCI bus
+**  07:00       00H                         Specifies frequency (how often) the device needs to access the PCI bus 
 **						in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement.
 ***********************************************************************************
 */
@@ -2759,9 +2930,9 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  Inbound Address Translation
-**
-**  The ATU allows external PCI bus initiators to directly access the internal bus.
-**  These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space.
+**  
+**  The ATU allows external PCI bus initiators to directly access the internal bus. 
+**  These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 
 **  The process of inbound address translation involves two steps:
 **  1. Address Detection.
 **             ¡E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
@@ -2782,42 +2953,42 @@ struct SENSE_DATA {
 **  				¡E Inbound ATU Base Address Register 3
 **  				¡E Inbound ATU Limit Register 3
 **  				¡E Inbound ATU Translate Value Register 3
-**    Note: Inbound Address window 1 is not a translate window.
+**    Note: Inbound Address window 1 is not a translate window. 
 **          Instead, window 1 may be used to allocate host memory for Private Devices.
-**          Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH),
+**          Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 
 **          thus the host BIOS does not configure window 3.
 **          Window 3 is intended to be used as a special window into local memory for private PCI
 **          agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge.
 **          PCI-to-PCI Bridge in 80331 or
-**          Inbound address detection is determined from the 32-bit PCI address,
-**          (64-bit PCI address during DACs) the base address register and the limit register.
-**          In the case of DACs none of the upper 32-bits of the address is masked during address comparison.
-**
+**          Inbound address detection is determined from the 32-bit PCI address, 
+**          (64-bit PCI address during DACs) the base address register and the limit register. 
+**          In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 
+**  
 **  The algorithm for detection is:
-**
+**  
 **  Equation 1. Inbound Address Detection
-**              When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only)
+**              When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 
 **              the PCI Address is claimed by the Inbound ATU.
-**
+**  
 **  			The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed
-**  			with the associated inbound limit register.
-**              When the result matches the base register (and upper base address matches upper PCI address in case of DACs),
+**  			with the associated inbound limit register. 
+**              When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 
 **              the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU.
 **
-**  			Note:   The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit.
+**  			Note:   The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 
 **  					Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit
 **  					internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the
-**  					lower 32-bits are used during address translation.
+**  					lower 32-bits are used during address translation. 
 **              		The algorithm is:
-**
-**
+**  
+**  
 **  Equation 2. Inbound Translation
 **              Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0].
-**
+**  
 **  			The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the
 **  			bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and
 **  			the result is the internal bus address. This translation mechanism is used for all inbound memory
-**  			read and write commands excluding inbound configuration read and writes.
+**  			read and write commands excluding inbound configuration read and writes. 
 **  			In the PCI mode for inbound memory transactions, the only burst order supported is Linear
 **  			Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase.
 **  			The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode.
@@ -2827,7 +2998,7 @@ struct SENSE_DATA {
 **  		        Limit_Register=FF80 0000H (8 Mbyte limit value)
 **  		        Value_Register=B100 0000H
 **  		        Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes)
-**
+**  		
 **  		Address Detection (32-bit address)
 **
 **  						PCI_Address & Limit_Register == Base_Register
@@ -2879,8 +3050,8 @@ struct SENSE_DATA {
 **  inbound ATU address translation.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     FF000H                        Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses.
-**                                          This value must be 64-bit aligned on the internal bus.
+**  31:12     FF000H                        Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 
+**                                          This value must be 64-bit aligned on the internal bus. 
 **						The default address allows the ATU to access the internal 80331 memory-mapped registers.
 **  11:00       000H                        Reserved
 ***********************************************************************************
@@ -2936,7 +3107,7 @@ struct SENSE_DATA {
 **  IAUBAR1, and IALR1.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Inbound Translation Limit 1 - This readback value determines the memory block size
+**  31:12     00000H                        Inbound Translation Limit 1 - This readback value determines the memory block size 
 **						required for the ATUs memory window 1.
 **  11:00 000H Reserved
 ***********************************************************************************
@@ -2945,7 +3116,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  Inbound ATU Limit Register 2 - IALR2
-**
+**  
 **  Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI
 **  bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts
 **  PCI addresses to internal bus addresses.
@@ -2966,7 +3137,7 @@ struct SENSE_DATA {
 **  register.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Inbound Translation Limit 2 - This readback value determines the memory block size
+**  31:12     00000H                        Inbound Translation Limit 2 - This readback value determines the memory block size 
 **						required for the ATUs memory window 2.
 **  11:00       000H                        Reserved
 ***********************************************************************************
@@ -2981,8 +3152,8 @@ struct SENSE_DATA {
 **  inbound ATU address translation.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses.
-**                                                                            This value must be 64-bit aligned on the internal bus.
+**  31:12     00000H                        Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 
+**                                                                            This value must be 64-bit aligned on the internal bus. 
 **										The default address allows the ATU to access the internal 80331 **	**										memory-mapped registers.
 **  11:00       000H                        Reserved
 ***********************************************************************************
@@ -2994,7 +3165,7 @@ struct SENSE_DATA {
 **
 **  The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address
 **  used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a
-**  result of the outbound ATU address translation.
+**  result of the outbound ATU address translation. 
 **  The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed
 **  length of 64 Kbytes.
 **  -----------------------------------------------------------------
@@ -3010,14 +3181,14 @@ struct SENSE_DATA {
 **
 **  The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
 **  address used to convert 80331 internal bus addresses for outbound transactions. This address is
-**  driven on the PCI bus as a result of the outbound ATU address translation.
+**  driven on the PCI bus as a result of the outbound ATU address translation. 
 **  The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length
 **  of 64 Mbytes.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
 **  31:26       00H                         Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
 **  25:02     00 0000H                      Reserved
-**  01:00      00 2                         Burst Order - This bit field shows the address sequence during a memory burst.
+**  01:00      00 2                         Burst Order - This bit field shows the address sequence during a memory burst. 
 **								Only linear incrementing mode is supported.
 ***********************************************************************************
 */
@@ -3044,14 +3215,14 @@ struct SENSE_DATA {
 **
 **  The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI
 **  address used to convert 80331 internal bus addresses for outbound transactions. This address is
-**  driven on the PCI bus as a result of the outbound ATU address translation.
+**  driven on the PCI bus as a result of the outbound ATU address translation. 
 **  The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length
 **  of 64 Mbytes.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
 **  31:26       00H                         Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses.
 **  25:02     00 0000H                      Reserved
-**  01:00       00 2                        Burst Order - This bit field shows the address sequence during a memory burst.
+**  01:00       00 2                        Burst Order - This bit field shows the address sequence during a memory burst. 
 **						Only linear incrementing mode is supported.
 ***********************************************************************************
 */
@@ -3101,8 +3272,8 @@ struct SENSE_DATA {
 **  			current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read
 **  			transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not
 **  			applicable in the PCI-X mode.
-**  18          0 2                         Direct Addressing Upper 2Gbytes Translation Enable - When set,
-**						with Direct Addressing enabled (bit 7 of the ATUCR set),
+**  18          0 2                         Direct Addressing Upper 2Gbytes Translation Enable - When set, 
+**						with Direct Addressing enabled (bit 7 of the ATUCR set), 
 **							the ATU forwards internal bus cycles with an address between 0000.0040H and
 **								7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH).
 **									 When clear, no translation occurs.
@@ -3113,15 +3284,15 @@ struct SENSE_DATA {
 ** 						discarded the delayed completion transaction within the queue. When clear, no timer has expired.
 **  14:10    00000 2                        Reserved
 **  09          0 2                         SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt
-**						when the ATU detects that SERR# was asserted. When clear,
+**						when the ATU detects that SERR# was asserted. When clear, 
 **							the Intel XScale core is not interrupted when SERR# is detected.
 **  08          0 2                         Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU.
 **  						Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to
-**  						the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of
+**  						the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 
 **							the ATUCR.
 **  07:04    0000 2                         Reserved
 **  03          0 2                         ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start
-**						BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7
+**						BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 
 **							in the ATUBISTR register.
 **  02          0 2                         Reserved
 **  01          0 2                         Outbound ATU Enable - When set, enables the outbound address translation unit.
@@ -3133,7 +3304,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  PCI Configuration and Status Register - PCSR
-**
+**  
 **  The PCI Configuration and Status Register has additional bits for controlling and monitoring
 **  various features of the PCI bus interface.
 **  -----------------------------------------------------------------
@@ -3150,7 +3321,7 @@ struct SENSE_DATA {
 **  										TRDY#,
 **  										during
 **  										P_RST#
-**  										PCI-X capability - These two bits define the mode of
+**  										PCI-X capability - These two bits define the mode of 
 **  										the PCI bus (conventional or PCI-X) as well as the
 **  										operating frequency in the case of PCI-X mode.
 **  										00 - Conventional PCI mode
@@ -3176,9 +3347,9 @@ struct SENSE_DATA {
 **  										    0=Inbound Transaction Queue Empty
 **  										    1=Inbound Transaction Queue Busy
 **  13          0 2                         Reserved.
-**  12          0 2								Discard Timer Value - This bit controls the time-out value
-**  										for the four discard timers attached to the queues holding read data.
-**                                                         A value of 0 indicates the time-out value is 2 15 clocks.
+**  12          0 2								Discard Timer Value - This bit controls the time-out value 
+**  										for the four discard timers attached to the queues holding read data. 
+**                                                         A value of 0 indicates the time-out value is 2 15 clocks. 
 **                                                         A value of 1 indicates the time-out value is 2 10 clocks.
 **  11          0 2                         Reserved.
 **  10      Varies with
@@ -3199,38 +3370,38 @@ struct SENSE_DATA {
 **  										P_RST#
 **  										PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been
 **  										configured as 64-bit capable by
-**  										the assertion of REQ64# on the rising edge of P_RST#. When set,
+**  										the assertion of REQ64# on the rising edge of P_RST#. When set, 
 **  										the PCI interface is configured as
 **  										32-bit only.
 **  07:06      00 2                         Reserved.
-**  05         0 2   						Reset Internal Bus - This bit controls the reset of the Intel XScale core
+**  05         0 2   						Reset Internal Bus - This bit controls the reset of the Intel XScale core 
 **  								and all units on the internal
-**  								bus. In addition to the internal bus initialization,
+**  								bus. In addition to the internal bus initialization, 
 **  								this bit triggers the assertion of the M_RST# pin for
 **  								initialization of registered DIMMs. When set:
 **  								When operating in the conventional PCI mode:
-**  								¡E All current PCI transactions being mastered by the ATU completes,
+**  								¡E All current PCI transactions being mastered by the ATU completes, 
 **  								and the ATU master interfaces
 **  								proceeds to an idle state. No additional transactions is mastered by these units
 **  								until the internal bus reset is complete.
-**  								¡E All current transactions being slaved by the ATU on either the PCI bus
+**  								¡E All current transactions being slaved by the ATU on either the PCI bus 
 **  								or the internal bus
-**  								completes, and the ATU target interfaces proceeds to an idle state.
-**  								All future slave transactions master aborts,
+**  								completes, and the ATU target interfaces proceeds to an idle state. 
+**  								All future slave transactions master aborts, 
 **  								with the exception of the completion cycle for the transaction that set the Reset
 **  								Internal Bus bit in the PCSR.
-**  								¡E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion)
+**  								¡E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 
 **  								is set, the Intel XScale core is held in reset when the internal bus reset is complete.
-**  								¡E The ATU ignores configuration cycles, and they appears as master aborts for: 32
+**  								¡E The ATU ignores configuration cycles, and they appears as master aborts for: 32 
 **  								Internal Bus clocks.
 **  								¡E The 80331 hardware clears this bit after the reset operation completes.
 **  								When operating in the PCI-X mode:
-**  								The ATU hardware responds the same as in Conventional PCI-X mode.
-**  								However, this may create a problem in PCI-X mode for split requests in
+**  								The ATU hardware responds the same as in Conventional PCI-X mode. 
+**  								However, this may create a problem in PCI-X mode for split requests in 
 **  								that there may still be an outstanding split completion that the
-**  								ATU is either waiting to receive (Outbound Request) or initiate
+**  								ATU is either waiting to receive (Outbound Request) or initiate 
 **  								(Inbound Read Request). For a cleaner
-**  								internal bus reset, host software can take the following steps prior
+**  								internal bus reset, host software can take the following steps prior 
 **  								to asserting Reset Internal bus:
 **  					1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in
 **  						the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued.
@@ -3264,7 +3435,7 @@ struct SENSE_DATA {
 **  01		Varies with external state of CORE_RST# during P_RST#
 **  			Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is
 **  			asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is
-**  			being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel
+**  			being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 
 **  			XScale  core reset.
 **  			The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge
 **  			of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is
@@ -3280,7 +3451,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  ATU Interrupt Status Register - ATUISR
-**
+**  
 **  The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU
 **  interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit
 **  of the 80331. All bits in this register are Read/Clear.
@@ -3410,45 +3581,45 @@ struct SENSE_DATA {
 **  					error) from the memory controller on the internal bus. In conventional mode, this action only occurs
 **  					during an inbound read transaction where the data phase that was target aborted on the internal bus is
 **  					actually requested from the inbound read queue.
-**  														0=Disconnect with data
+**  														0=Disconnect with data 
 **  														(the data being up to 64 bits of 1¡¦s)
 **  														1=Target Abort
 **  		NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h -
 **  			completer error and message index=81h - 80331 internal bus target abort) on the PCI bus,
 **  			independent of the setting of this bit.
-***********************************************************************************
+*********************************************************************************** 
 */
 #define     ARCMSR_ATU_INTERRUPT_MASK_REG		          0x8C    /*dword 0x8F,0x8E,0x8D,0x8C*/
 /*
 ***********************************************************************************
 **  Inbound ATU Base Address Register 3 - IABAR3
 **
-**  . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block
-**    of memory addresses where the inbound translation window 3 begins.
-**  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory.
+**  . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 
+**    of memory addresses where the inbound translation window 3 begins. 
+**  . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 
 **  . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size.
-**  . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3.
-**    The programmed value within the base address register must comply with the PCI programming requirements for address alignment.
-**  Note:
-**      Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH),
+**  . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 
+**    The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 
+**  Note: 
+**      Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 
 **      IABAR3 is not configured by the host during normal system initialization.
-**  Warning:
-**    When a non-zero value is not written to IALR3,
-**                          the user should not set either the Prefetchable Indicator
+**  Warning: 
+**    When a non-zero value is not written to IALR3, 
+**                          the user should not set either the Prefetchable Indicator 
 **                                                      or the Type         Indicator for 64 bit addressability.
-**                          This is the default for IABAR3.
+**                          This is the default for IABAR3. 
 **  Assuming a non-zero value is written to IALR3,
-**                          the user may set the Prefetchable Indicator
+**                          the user may set the Prefetchable Indicator 
 **                                        or the Type         Indicator:
 **  						a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary,
-**                             when the Prefetchable Indicator is not set,
+**                             when the Prefetchable Indicator is not set, 
 **                             the user should also leave the Type Indicator set for 32 bit addressability.
 **                             This is the default for IABAR3.
-**  						b. when the Prefetchable Indicator is set,
+**  						b. when the Prefetchable Indicator is set, 
 **                             the user should also set the Type Indicator for 64 bit addressability.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Translation Base Address 3 - These bits define the actual location
+**  31:12     00000H                        Translation Base Address 3 - These bits define the actual location 
 **                                          the translation function is to respond to when addressed from the PCI bus.
 **  11:04        00H                        Reserved.
 **  03           0 2                        Prefetchable Indicator - When set, defines the memory space as prefetchable.
@@ -3456,7 +3627,7 @@ struct SENSE_DATA {
 **  						00 - Memory Window is locatable anywhere in 32 bit address space
 **  						10 - Memory Window is locatable anywhere in 64 bit address space
 **  00           0 2                        Memory Space Indicator - This bit field describes memory or I/O space base address.
-**                                                                   The ATU does not occupy I/O space,
+**                                                                   The ATU does not occupy I/O space, 
 **                                                                   thus this bit must be zero.
 ***********************************************************************************
 */
@@ -3470,13 +3641,13 @@ struct SENSE_DATA {
 **  the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
 **  The programmed value within the base address register must comply with the PCI programming
 **  requirements for address alignment.
-**  Note:
-**      When the Type indicator of IABAR3 is set to indicate 32 bit addressability,
-**      the IAUBAR3 register attributes are read-only.
+**  Note: 
+**      When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 
+**      the IAUBAR3 register attributes are read-only. 
 **      This is the default for IABAR3.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:0      00000H                        Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define
+**  31:0      00000H                        Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 
 **                        the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes.
 ***********************************************************************************
 */
@@ -3505,7 +3676,7 @@ struct SENSE_DATA {
 **  register.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Inbound Translation Limit 3 - This readback value determines the memory block size required
+**  31:12     00000H                        Inbound Translation Limit 3 - This readback value determines the memory block size required 
 **                                          for the ATUs memory window 3.
 **  11:00       000H                        Reserved
 ***********************************************************************************
@@ -3520,7 +3691,7 @@ struct SENSE_DATA {
 **  inbound ATU address translation.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:12     00000H                        Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses.
+**  31:12     00000H                        Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 
 **                                                          This value must be 64-bit aligned on the internal bus. The default address allows the ATU to
 **                                                          access the internal 80331 memory-mapped registers.
 **  11:00       000H                        Reserved
@@ -3530,7 +3701,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  Outbound Configuration Cycle Address Register - OCCAR
-**
+**  
 **  The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
 **  cycle address. The Intel XScale core writes the PCI configuration cycles address which then
 **  enables the outbound configuration read or write. The Intel XScale core then performs a read or
@@ -3544,7 +3715,7 @@ struct SENSE_DATA {
 **  Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:00    0000 0000H                     Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound
+**  31:00    0000 0000H                     Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 
 **                                          configuration read or write cycle.
 ***********************************************************************************
 */
@@ -3564,7 +3735,7 @@ struct SENSE_DATA {
 **  within the ATU configuration space.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:00    0000 0000H                     Configuration Cycle Data - These bits define the data used during an outbound configuration read
+**  31:00    0000 0000H                     Configuration Cycle Data - These bits define the data used during an outbound configuration read 
 **                                          or write cycle.
 ***********************************************************************************
 */
@@ -3572,7 +3743,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  VPD Capability Identifier Register - VPD_CAPID
-**
+**  
 **  The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
 **  Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
 **  Capability contained in that header. In the case of the 80331, this is the VPD extended capability
@@ -3587,7 +3758,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  VPD Next Item Pointer Register - VPD_NXTP
-**
+**  
 **  The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
 **  Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
 **  For the 80331, this the final capability list, and hence, this register is set to 00H.
@@ -3662,13 +3833,13 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  Power Management Capabilities Register - PM_CAP
-**
+**  
 **  Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management
 **  Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides
 **  information on the capabilities of the ATU function related to power management.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  15:11   00000 2                         PME_Support - This function is not capable of asserting the PME# signal in any state, since PME#
+**  15:11   00000 2                         PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 
 **                                          is not supported by the 80331.
 **  10          0 2                         D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State
 **  9           1 2                         D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State
@@ -3678,7 +3849,7 @@ struct SENSE_DATA {
 **                                                          following the transition to the D0 uninitialized state.
 **  4           0 2                         Reserved.
 **  3           0 2                         PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 .
-**  2:0       010 2                         Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management
+**  2:0       010 2                         Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 
 **                                          Interface Specification, Revision 1.1
 ***********************************************************************************
 */
@@ -3695,10 +3866,10 @@ struct SENSE_DATA {
 **  15          0 2                         PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not
 **                                          supported by the 80331.
 **  14:9        00H                         Reserved
-**  8           0 2                         PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME#
+**  8           0 2                         PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 
 **                                          generation from any power state.
 **  7:2    000000 2                         Reserved
-**  1:0        00 2                         Power State - This 2-bit field is used both to determine the current power state
+**  1:0        00 2                         Power State - This 2-bit field is used both to determine the current power state 
 **                                          of a function and to set the function into a new power state. The definition of the values is:
 **  							00 2 - D0
 **  							01 2 - D1
@@ -3712,7 +3883,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  PCI-X Capability Identifier Register - PX_CAPID
-**
+**  
 **  The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification,
 **  Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended
 **  Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with
@@ -3727,7 +3898,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  PCI-X Next Item Pointer Register - PX_NXTP
-**
+**  
 **  The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification,
 **  Revision 2.3. This register describes the location of the next item in the function¡¦s capability list.
 **  By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults
@@ -3754,7 +3925,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  PCI-X Command Register - PX_CMD
-**
+**  
 **  This register controls various modes and features of ATU and Message Unit when operating in the
 **  PCI-X mode.
 **  -----------------------------------------------------------------
@@ -3790,7 +3961,7 @@ struct SENSE_DATA {
 /*
 ***********************************************************************************
 **  PCI-X Status Register - PX_SR
-**
+**  
 **  This register identifies the capabilities and current operating mode of ATU, DMAs and Message
 **  Unit when operating in the PCI-X mode.
 **  -----------------------------------------------------------------
@@ -3809,7 +3980,7 @@ struct SENSE_DATA {
 **  					2 32 2048
 **  					2 32 4096
 **  25:23      011 2                        Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions.
-**  22:21       01 2                        Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up
+**  22:21       01 2                        Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 
 **                                          to 1024 bytes.
 **  20           1 2                        80331 is a complex device.
 **  19           0 2                        Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device¡¦s
@@ -3825,11 +3996,11 @@ struct SENSE_DATA {
 **  		NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read
 **  			Requests with Split Responses (Memory or Register) that has ¡§read side effects.¡¨
 **  17           1 2                        80331 is a 133 MHz capable device.
-**  16           1 2 or P_32BITPCI#	80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus,
+**  16           1 2 or P_32BITPCI#	80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 
 **  					therefore this bit is always set.
-**  			80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0),
-**  			use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#).
-**  			This strap, by default, identifies the add in card based on 80331 with bridge disabled
+**  			80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 
+**  			use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 
+**  			This strap, by default, identifies the add in card based on 80331 with bridge disabled 
 **  			as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.
 **  			0=The bus is 32 bits wide.
 **  			1=The bus is 64 bits wide.
@@ -4174,7 +4345,7 @@ struct SENSE_DATA {
 **  actions is taken:
 **  ¡X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the
 **  Detected Parity Error bit in the ATUISR. When set, no action.
-**  ===================================================
+**  =================================================== 
 **                       PCI-X Mode
 **  ===================================================
 **  Data parity errors occurring during configuration write operations received by the ATU may cause
@@ -4244,24 +4415,24 @@ struct SENSE_DATA {
 ******************************************************************************************************
 **                 Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
 **  ==================================================================================================
-**	The Messaging Unit (MU) transfers data between the PCI system and the 80331
+**	The Messaging Unit (MU) transfers data between the PCI system and the 80331 
 **  notifies the respective system when new data arrives.
 **	The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation.
-**	window defined by:
-**                    1.Inbound ATU Base Address Register 0 (IABAR0)
+**	window defined by: 
+**                    1.Inbound ATU Base Address Register 0 (IABAR0) 
 **                    2.Inbound ATU Limit Register 0 (IALR0)
-**	All of the Messaging Unit errors are reported in the same manner as ATU errors.
+**	All of the Messaging Unit errors are reported in the same manner as ATU errors. 
 **  Error conditions and status can be found in :
-**                                               1.ATUSR
+**                                               1.ATUSR 
 **                                               2.ATUISR
 **====================================================================================================
 **     Mechanism        Quantity               Assert PCI Interrupt Signals      Generate I/O Processor Interrupt
 **----------------------------------------------------------------------------------------------------
 **  Message Registers      2 Inbound                   Optional                              Optional
-**                         2 Outbound
+**                         2 Outbound                
 **----------------------------------------------------------------------------------------------------
 **  Doorbell Registers     1 Inbound                   Optional                              Optional
-**                         1 Outbound
+**                         1 Outbound  
 **----------------------------------------------------------------------------------------------------
 **  Circular Queues        4 Circular Queues           Under certain conditions              Under certain conditions
 **----------------------------------------------------------------------------------------------------
@@ -4312,38 +4483,38 @@ struct SENSE_DATA {
 **  outbound_msgaddr0:
 **  outbound_msgaddr1:
 **  .  The MU has four independent messaging mechanisms.
-**     There are four Message Registers that are similar to a combination of mailbox and doorbell registers.
+**     There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 
 **     Each holds a 32-bit value and generates an interrupt when written.
 **--------------------
 **   inbound_doorbell:
 **  outbound_doorbell:
-**  .  The two Doorbell Registers support software interrupts.
+**  .  The two Doorbell Registers support software interrupts. 
 **     When a bit is set in a Doorbell Register, an interrupt is generated.
 **--------------------
 **  inbound_queueport:
 ** outbound_queueport:
 **
 **
-**  .  The Circular Queues support a message passing scheme that uses 4 circular queues.
-**     The 4 circular queues are implemented in 80331 local memory.
-**     Two queues are used for inbound messages and two are used for outbound messages.
+**  .  The Circular Queues support a message passing scheme that uses 4 circular queues. 
+**     The 4 circular queues are implemented in 80331 local memory. 
+**     Two queues are used for inbound messages and two are used for outbound messages. 
 **     Interrupts may be generated when the queue is written.
 **--------------------
 ** local_buffer 0x0050 ....0x0FFF
-**  .  The Index Registers use a portion of the 80331 local memory to implement a large set of message registers.
+**  .  The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 
 **     When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured.
-**     Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register.
+**     Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 
 **     Each interrupt generated by the Messaging Unit can be masked.
 **--------------------
-**  .  Multi-DWORD PCI burst accesses are not supported by the Messaging Unit,
-**     with the exception of Multi-DWORD reads to the index registers.
-**     In Conventional mode: the MU terminates   Multi-DWORD PCI transactions
-**     (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports.
-**     In PCI-X mode       : the MU terminates a Multi-DWORD PCI read transaction with a Split Response
+**  .  Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 
+**     with the exception of Multi-DWORD reads to the index registers. 
+**     In Conventional mode: the MU terminates   Multi-DWORD PCI transactions 
+**     (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 
+**     In PCI-X mode       : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 
 **     and the data is returned through split completion transaction(s).
-**     however, when the burst request crosses into or through the range of  offsets 40h to 4Ch
-**     (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus.
-**     In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect
+**     however, when the burst request crosses into or through the range of  offsets 40h to 4Ch 
+**     (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 
+**     In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 
 **     which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written.
 **--------------------
 **  .  All registers needed to configure and control the Messaging Unit are memory-mapped registers.
@@ -4356,10 +4527,10 @@ struct SENSE_DATA {
 **     The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register.
 **     The Messaging Unit reports all PCI errors in the ATU Status Register.
 **--------------------
-**  .  Parts of the Messaging Unit can be accessed as a 64-bit PCI device.
-**     The register interface, message registers, doorbell registers,
-**     and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface.
-**     Up to 1 Qword of data can be read or written per transaction (except Index Register reads).
+**  .  Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 
+**     The register interface, message registers, doorbell registers, 
+**     and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 
+**     Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 
 **     The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H.
 **************************************************************************
 */
@@ -4367,7 +4538,7 @@ struct SENSE_DATA {
 **************************************************************************
 **  Message Registers
 **  ==============================
-**  . Messages can be sent and received by the 80331 through the use of the Message Registers.
+**  . Messages can be sent and received by the 80331 through the use of the Message Registers. 
 **  . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor.
 **  . Inbound messages are sent by the host processor and received by the 80331.
 **    Outbound messages are sent by the 80331 and received by the host processor.
@@ -4376,23 +4547,23 @@ struct SENSE_DATA {
 **
 **  Inbound Messages:
 **  -----------------
-**  . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core.
+**  . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 
 **  . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register.
-**  . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register.
-**    The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register.
+**  . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 
+**    The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 
 **    This is a Read/Clear bit that is set by the MU hardware and cleared by software.
-**    The interrupt is cleared when the Intel XScale core writes a value of
+**    The interrupt is cleared when the Intel XScale core writes a value of 
 **    1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register.
 **  ------------------------------------------------------------------------
 **  Inbound Message Register - IMRx
 **
-**  . There are two Inbound Message Registers: IMR0 and IMR1.
+**  . There are two Inbound Message Registers: IMR0 and IMR1. 
 **  . When the IMR register is written, an interrupt to the Intel XScale core may be generated.
-**    The interrupt is recorded in the Inbound Interrupt Status Register and may be masked
+**    The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 
 **    by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register.
 **  -----------------------------------------------------------------
 **  Bit       Default                       Description
-**  31:00    0000 0000H                     Inbound Message - This is a 32-bit message written by an external PCI agent.
+**  31:00    0000 0000H                     Inbound Message - This is a 32-bit message written by an external PCI agent. 
 **                                                            When written, an interrupt to the Intel XScale core may be generated.
 **************************************************************************
 */
@@ -4418,40 +4589,40 @@ struct SENSE_DATA {
 **************************************************************************
 **        Doorbell Registers
 **  ==============================
-**  There are two Doorbell Registers:
-**                                  Inbound Doorbell Register
+**  There are two Doorbell Registers: 
+**                                  Inbound Doorbell Register 
 **                                  Outbound Doorbell Register
-**  The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core.
-**  The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt.
+**  The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 
+**  The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 
 **  Both Doorbell Registers may generate interrupts whenever a bit in the register is set.
 **
 **  Inbound Doorbells:
 **  ------------------
 **  . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale  core.
 **    An interrupt is generated when any of the bits in the doorbell register is written to a value of 1.
-**    Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated.
-**  . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent.
+**    Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 
+**  . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 
 **    The interrupt is recorded in the Inbound Interrupt Status Register.
 **  . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register.
 **    When the mask bit is set for a particular bit, no interrupt is generated for that bit.
 **    The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt
-**    and not the values written to the Inbound Doorbell Register.
+**    and not the values written to the Inbound Doorbell Register. 
 **    One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt.
-**  . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set.
+**  . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 
 **    Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt.
 **  ------------------------------------------------------------------------
 **  Inbound Doorbell Register - IDR
 **
-**  . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core.
-**  . Bit 31 is reserved for generating an Error Doorbell interrupt.
-**    When bit 31 is set, an Error interrupt may be generated to the Intel XScale core.
-**    All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted,
+**  . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 
+**  . Bit 31 is reserved for generating an Error Doorbell interrupt. 
+**    When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 
+**    All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 
 **    when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register.
 **    The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale  core.
 **  ------------------------------------------------------------------------
 **  Bit       Default                       Description
 **  31          0 2                         Error Interrupt - Generate an Error Interrupt to the Intel XScale core.
-**  30:00    00000000H                      Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core.
+**  30:00    00000000H                      Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 
 **                                                             When all bits are clear, do not generate a Normal Interrupt.
 **************************************************************************
 */
@@ -4460,32 +4631,32 @@ struct SENSE_DATA {
 **************************************************************************
 **  Inbound Interrupt Status Register - IISR
 **
-**  . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status.
-**    It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues.
-**    All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core,
-**    except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt;
-**    these two are routed to the Messaging Unit Error interrupt input.
-**    The generation of interrupts recorded in the Inbound Interrupt Status Register
-**    may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register.
-**    Some of the bits in this register are Read Only.
+**  . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 
+**    It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 
+**    All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 
+**    except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 
+**    these two are routed to the Messaging Unit Error interrupt input. 
+**    The generation of interrupts recorded in the Inbound Interrupt Status Register 
+**    may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 
+**    Some of the bits in this register are Read Only. 
 **    For those bits, the interrupt must be cleared through another register.
 **
 **  Bit       Default                       Description
 **  31:07    0000000H 0 2                   Reserved
-**  06          0 2              Index Register Interrupt - This bit is set by the MU hardware
+**  06          0 2              Index Register Interrupt - This bit is set by the MU hardware 
 **                               when an Index Register has been written after a PCI transaction.
-**  05          0 2              Outbound Free Queue Full Interrupt - This bit is set
-**                               when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
+**  05          0 2              Outbound Free Queue Full Interrupt - This bit is set 
+**                               when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 
 **                               An Error interrupt is generated for this condition.
-**  04          0 2              Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written.
-**                               Once cleared, an interrupt does NOT be generated
+**  04          0 2              Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 
+**                               Once cleared, an interrupt does NOT be generated 
 **                               when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
-**                               Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared,
+**                               Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 
 **                               software must retain the information that the Inbound Post queue status is not empty.
 **          NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller.
 **  03          0 2              Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set.
 **                               To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear.
-**  02          0 2              Inbound Doorbell Interrupt - This bit is set when at least one
+**  02          0 2              Inbound Doorbell Interrupt - This bit is set when at least one 
 **                               Normal Interrupt bit in the Inbound Doorbell Register is set.
 **                               To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear.
 **  01          0 2              Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written.
@@ -4495,7 +4666,7 @@ struct SENSE_DATA {
 #define     ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG	      0x24    /*dword 0x27,0x26,0x25,0x24*/
 #define     ARCMSR_MU_INBOUND_INDEX_INT                      0x40
 #define     ARCMSR_MU_INBOUND_QUEUEFULL_INT                  0x20
-#define     ARCMSR_MU_INBOUND_POSTQUEUE_INT                  0x10
+#define     ARCMSR_MU_INBOUND_POSTQUEUE_INT                  0x10         
 #define     ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT             0x08
 #define     ARCMSR_MU_INBOUND_DOORBELL_INT                   0x04
 #define     ARCMSR_MU_INBOUND_MESSAGE1_INT                   0x02
@@ -4504,33 +4675,33 @@ struct SENSE_DATA {
 **************************************************************************
 **  Inbound Interrupt Mask Register - IIMR
 **
-**  . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit.
+**  . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 
 **    Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register.
-**    Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register.
+**    Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 
 **    They only affect the generation of the Intel XScale core interrupt.
 **  ------------------------------------------------------------------------
 **  Bit       Default                       Description
 **  31:07     000000H 0 2                   Reserved
-**  06        0 2               Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware
+**  06        0 2               Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 
 **				when an Index Register has been written after a PCI transaction.
-**  05        0 2               Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated
+**  05        0 2               Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 
 **				when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
-**  04        0 2               Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated
+**  04        0 2               Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 
 **				by the MU hardware when the Inbound Post Queue has been written.
-**  03        0 2               Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt
+**  03        0 2               Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 
 **				when the Error Interrupt bit of the Inbound Doorbell Register is set.
-**  02        0 2               Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated
+**  02        0 2               Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 
 **				when at least one Normal Interrupt bit in the Inbound Doorbell Register is set.
-**  01        0 2               Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1
+**  01        0 2               Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 
 **				Interrupt generated by a write to the Inbound Message 1 Register.
-**  00        0 2               Inbound Message 0 Interrupt Mask - When set,
+**  00        0 2               Inbound Message 0 Interrupt Mask - When set, 
 **                              this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register.
 **************************************************************************
 */
 #define     ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG	      0x28    /*dword 0x2B,0x2A,0x29,0x28*/
 #define     ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE               0x40
 #define     ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE           0x20
-#define     ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE           0x10
+#define     ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE           0x10         
 #define     ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE      0x08
 #define     ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE            0x04
 #define     ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE            0x02
@@ -4539,7 +4710,7 @@ struct SENSE_DATA {
 **************************************************************************
 **  Outbound Doorbell Register - ODR
 **
-**  The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel
+**  The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 
 **  XScale  core to generate PCI interrupts to the host processor by writing to this register. The
 **  generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the
 **  Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register.
@@ -4550,14 +4721,14 @@ struct SENSE_DATA {
 **  31          0 2                          Reserved
 **  30          0 2                          Reserved.
 **  29          0 2                          Reserved
-**  28       0000 0000H                      PCI Interrupt - When set, this bit causes the P_INTC# interrupt output
-**                                                           (P_INTA# with BRG_EN and ARB_EN straps low)
-**                                                           signal to be asserted or a Message-signaled Interrupt is generated (when enabled).
-**                                                           When this bit is cleared, the P_INTC# interrupt output
+**  28       0000 0000H                      PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 
 **                                                           (P_INTA# with BRG_EN and ARB_EN straps low)
+**                                                           signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 
+**                                                           When this bit is cleared, the P_INTC# interrupt output 
+**                                                           (P_INTA# with BRG_EN and ARB_EN straps low) 
 **                                                           signal is deasserted.
-**  27:00     000 0000H                      Software Interrupts - When any bit is set the P_INTC# interrupt output
-**                                           (P_INTA# with BRG_EN and ARB_EN straps low)
+**  27:00     000 0000H                      Software Interrupts - When any bit is set the P_INTC# interrupt output 
+**                                           (P_INTA# with BRG_EN and ARB_EN straps low) 
 **                                           signal is asserted or a Message-signaled Interrupt is generated (when enabled).
 **                                           When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low)
 **                                           signal is deasserted.
@@ -4592,10 +4763,10 @@ struct SENSE_DATA {
 */
 #define     ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG	      0x30    /*dword 0x33,0x32,0x31,0x30*/
 #define     ARCMSR_MU_OUTBOUND_PCI_INT       	              0x10
-#define     ARCMSR_MU_OUTBOUND_POSTQUEUE_INT    	          0x08
-#define     ARCMSR_MU_OUTBOUND_DOORBELL_INT 		          0x04
-#define     ARCMSR_MU_OUTBOUND_MESSAGE1_INT 		          0x02
-#define     ARCMSR_MU_OUTBOUND_MESSAGE0_INT 		          0x01
+#define     ARCMSR_MU_OUTBOUND_POSTQUEUE_INT    	          0x08 
+#define     ARCMSR_MU_OUTBOUND_DOORBELL_INT 		          0x04 
+#define     ARCMSR_MU_OUTBOUND_MESSAGE1_INT 		          0x02 
+#define     ARCMSR_MU_OUTBOUND_MESSAGE0_INT 		          0x01 
 /*
 **************************************************************************
 **  Outbound Interrupt Mask Register - OIMR
@@ -4622,11 +4793,11 @@ struct SENSE_DATA {
 */
 #define     ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG		  0x34    /*dword 0x37,0x36,0x35,0x34*/
 #define     ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE   	          0x10
-#define     ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE	      0x08
-#define     ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE		  0x04
-#define     ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE		  0x02
-#define     ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE		  0x01
-#define     ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE		      0x1F
+#define     ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE	      0x08 
+#define     ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE		  0x04 
+#define     ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE		  0x02 
+#define     ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE		  0x01 
+#define     ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE		      0x1F 
 /*
 **************************************************************************
 **
@@ -4647,12 +4818,12 @@ struct SENSE_DATA {
 ** 							¡E posted messages by the Intel XScale core for other processors to process or
 ** 							¡E free (or empty) messages that can be reused by the Intel XScale core.
 **  Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331.
-**  The four Circular Queues are used to pass messages in the following manner.
-**  	. The two inbound queues are used to handle inbound messages
-**  	  and the two outbound queues are used to handle  outbound messages.
-**  	. One of the inbound queues is designated the Free queue and it contains inbound free messages.
+**  The four Circular Queues are used to pass messages in the following manner. 
+**  	. The two inbound queues are used to handle inbound messages 
+**  	  and the two outbound queues are used to handle  outbound messages. 
+**  	. One of the inbound queues is designated the Free queue and it contains inbound free messages. 
 **  	  The other inbound queue is designated the Post queue and it contains inbound posted messages.
-**  	  Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue.
+**  	  Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 
 **
 **  =============================================================================================================
 **  Circular Queue Summary
@@ -4670,36 +4841,36 @@ struct SENSE_DATA {
 **  |______________________|____________________________________________________________|_________________________|
 **
 **  . The two inbound queues allow the host processor to post inbound messages for the 80331 in one
-**    queue and to receive free messages returning from the 80331.
-**    The host processor posts inbound messages,
+**    queue and to receive free messages returning from the 80331. 
+**    The host processor posts inbound messages, 
 **    the Intel XScale core receives the posted message and when it is finished with the message,
 **    places it back on the inbound free queue for reuse by the host processor.
 **
 **  The circular queues are accessed by external PCI agents through two port locations in the PCI
-**  address space:
-**              Inbound Queue Port
-**          and Outbound Queue Port.
-**  The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue.
+**  address space: 
+**              Inbound Queue Port 
+**          and Outbound Queue Port. 
+**  The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 
 **  The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue.
-**  Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 )
-**  does not cause the MU hardware to increment the queue pointers.
-**  This is treated as when the PCI transaction did not occur.
+**  Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 
+**  does not cause the MU hardware to increment the queue pointers. 
+**  This is treated as when the PCI transaction did not occur. 
 **  The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
 **  ======================================================================================
 **  Overview of Circular Queue Operation
 **  ======================================================================================
 **  . The data storage for the circular queues must be provided by the 80331 local memory.
 **  . The base address of the circular queues is contained in the Queue Base Address Register.
-**    Each entry in the queue is a 32-bit data value.
-**  . Each read from or write to the queue may access only one queue entry.
-**  . Multi-DWORD accesses to the circular queues are not allowed.
+**    Each entry in the queue is a 32-bit data value. 
+**  . Each read from or write to the queue may access only one queue entry. 
+**  . Multi-DWORD accesses to the circular queues are not allowed. 
 **    Sub-DWORD accesses are promoted to DWORD accesses.
-**  . Each circular queue has a head pointer and a tail pointer.
+**  . Each circular queue has a head pointer and a tail pointer. 
 **    The pointers are offsets from the Queue Base Address.
-**  . Writes to a queue occur at the head of the queue and reads occur from the tail.
+**  . Writes to a queue occur at the head of the queue and reads occur from the tail. 
 **    The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware.
-**    Which unit maintains the pointer is determined by the writer of the queue.
-**    More details about the pointers are given in the queue descriptions below.
+**    Which unit maintains the pointer is determined by the writer of the queue. 
+**    More details about the pointers are given in the queue descriptions below. 
 **    The pointers are incremented after the queue access.
 **    Both pointers wrap around to the first address of the circular queue when they reach the circular queue size.
 **
@@ -4708,14 +4879,14 @@ struct SENSE_DATA {
 **  The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions.
 **  . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted.
 **    The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes).
-**  . All four queues must be the same size and may be contiguous.
-**    Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes.
+**  . All four queues must be the same size and may be contiguous. 
+**    Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 
 **    The Queue size is determined by the Queue Size field in the MU Configuration Register.
-**  . There is one base address for all four queues.
+**  . There is one base address for all four queues. 
 **    It is stored in the Queue Base Address Register (QBAR).
-**    The starting addresses of each queue is based on the Queue Base Address and the Queue Size field.
+**    The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 
 **    here shows an example of how the circular queues should be set up based on the
-**    Intelligent I/O (I 2 O) Architecture Specification.
+**    Intelligent I/O (I 2 O) Architecture Specification. 
 **    Other ordering of the circular queues is possible.
 **
 **  				Queue                           Starting Address
@@ -4727,66 +4898,66 @@ struct SENSE_DATA {
 **  Inbound Post Queue
 **  ------------------
 **  The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process.
-**  This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents.
+**  This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 
 **  The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware.
-**  For a PCI write transaction that accesses the Inbound Queue Port,
+**  For a PCI write transaction that accesses the Inbound Queue Port, 
 **  the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register.
 **  When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register.
-**  An Intel XScale core interrupt may be generated when the Inbound Post Queue is written.
+**  An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 
 **  The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status.
-**  The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared.
-**  The interrupt can be masked by the Inbound Interrupt Mask Register.
-**  Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee
+**  The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 
+**  The interrupt can be masked by the Inbound Interrupt Mask Register. 
+**  Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 
 **  that the full condition is recognized by the core processor.
-**  In addition, to guarantee that the queue does not get overwritten,
+**  In addition, to guarantee that the queue does not get overwritten, 
 **  software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt.
-**  Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty).
-**  Only a new message posting the in the inbound queue generates a new interrupt.
-**  Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared,
+**  Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 
+**  Only a new message posting the in the inbound queue generates a new interrupt. 
+**  Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 
 **  software must retain the information that the Inbound Post queue status.
-**  From the time that the PCI write transaction is received until the data is written
-**  in local memory and the Inbound Post Head Pointer Register is incremented,
+**  From the time that the PCI write transaction is received until the data is written 
+**  in local memory and the Inbound Post Head Pointer Register is incremented, 
 **  any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry.
-**  The Intel XScale core may read messages from the Inbound Post Queue
-**  by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register.
-**  The Intel XScale core must then increment the Inbound Post Tail Pointer Register.
-**  When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware),
-**  the hardware retries any PCI writes until a slot in the queue becomes available.
+**  The Intel XScale core may read messages from the Inbound Post Queue 
+**  by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 
+**  The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 
+**  When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 
+**  the hardware retries any PCI writes until a slot in the queue becomes available. 
 **  A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer.
 **  ===================================================================================
 **  Inbound Free Queue
 **  ------------------
 **  The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use.
-**  This queue is read from the queue tail by external PCI agents.
-**  It is written to the queue head by the Intel XScale core.
+**  This queue is read from the queue tail by external PCI agents. 
+**  It is written to the queue head by the Intel XScale core. 
 **  The tail pointer is maintained by the MU hardware.
 **  The head pointer is maintained by the Intel XScale core.
 **  For a PCI read transaction that accesses the Inbound Queue Port,
-**  the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer.
-**  When the queue is not empty (head and tail pointers are not equal)
+**  the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 
+**  When the queue is not empty (head and tail pointers are not equal) 
 **  or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned.
-**  When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware),
+**  When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 
 **  the value of -1 (FFFF.FFFFH) is  returned.
-**  When the queue was not empty and the MU succeeded in returning the data at the tail,
+**  When the queue was not empty and the MU succeeded in returning the data at the tail, 
 **  the MU hardware must increment the value in the Inbound Free Tail Pointer Register.
-**  To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue.
-**  The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register.
+**  To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 
+**  The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 
 **  When the PCI read access occurs, the data is read directly from the prefetch register.
-**  The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register
-**  when the head and tail pointers are equal and the queue is empty.
-**  In order to update the prefetch register when messages are added to the queue and it becomes non-empty,
-**  the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH
+**  The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 
+**  when the head and tail pointers are equal and the queue is empty. 
+**  In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 
+**  the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 
 **  and the Inbound Free Head Pointer Register is written.
 **  The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue.
 **  A prefetch must appear atomic from the perspective of the external PCI agent.
 **  When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed.
 **  The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the
-**  local memory location pointed to by the Inbound Free Head Pointer Register.
+**  local memory location pointed to by the Inbound Free Head Pointer Register. 
 **  The processor must then increment the Inbound Free Head Pointer Register.
 **  ==================================================================================
 **  Outbound Post Queue
 **  -------------------
-**  The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale
+**  The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 
 **  core for other processors to process. This queue is read from the queue tail by external PCI agents.
 **  It is written to the queue head by the Intel XScale  core. The tail pointer is maintained by the
 **  MU hardware. The head pointer is maintained by the Intel XScale  core.
@@ -4874,20 +5045,20 @@ struct SENSE_DATA {
 **************************************************************************
 **       Index Registers
 **  ========================
-**  . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core.
+**  . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 
 **    These registers are for inbound messages only.
 **    The interrupt is recorded in the Inbound Interrupt Status Register.
-**    The storage for the Index Registers is allocated from the 80331 local memory.
-**    PCI write accesses to the Index Registers write the data to local memory.
-**    PCI read accesses to the Index Registers read the data from local memory.
-**  . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H
+**    The storage for the Index Registers is allocated from the 80331 local memory. 
+**    PCI write accesses to the Index Registers write the data to local memory. 
+**    PCI read accesses to the Index Registers read the data from local memory. 
+**  . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 
 **                                                           to Inbound ATU Translate Value Register + FFFH.
-**  . The address of the first write access is stored in the Index Address Register.
-**    This register is written during the earliest write access and provides a means to determine which Index Register was written.
-**    Once updated by the MU, the Index Address Register is not updated until the Index Register
-**    Interrupt bit in the Inbound Interrupt Status Register is cleared.
+**  . The address of the first write access is stored in the Index Address Register. 
+**    This register is written during the earliest write access and provides a means to determine which Index Register was written. 
+**    Once updated by the MU, the Index Address Register is not updated until the Index Register 
+**    Interrupt bit in the Inbound Interrupt Status Register is cleared. 
 **  . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access.
-**    Writes by the Intel XScale core to the local memory used by the Index Registers
+**    Writes by the Intel XScale core to the local memory used by the Index Registers 
 **    does not cause an interrupt and does not update the Index Address Register.
 **  . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes.
 **************************************************************************
@@ -4941,14 +5112,14 @@ struct SENSE_DATA {
 **  MU Configuration Register - MUCR  FFFF.E350H
 **
 **  . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue.
-**  . The Circular Queue Enable bit enables or disables the Circular Queues.
-**    The Circular Queues are disabled at reset to allow the software to initialize the head
-**    and tail pointer registers before any PCI accesses to the Queue Ports.
+**  . The Circular Queue Enable bit enables or disables the Circular Queues. 
+**    The Circular Queues are disabled at reset to allow the software to initialize the head 
+**    and tail pointer registers before any PCI accesses to the Queue Ports. 
 **  . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues.
 **  ------------------------------------------------------------------------
 **  Bit       Default                       Description
 **  31:06     000000H 00 2                  Reserved
-**  05:01     00001 2                       Circular Queue Size - This field determines the size of each Circular Queue.
+**  05:01     00001 2                       Circular Queue Size - This field determines the size of each Circular Queue. 
 **  					All four queues are the same size.
 **  					¡E 00001 2 - 4K Entries (16 Kbytes)
 **  					¡E 00010 2 - 8K Entries (32 Kbytes)
@@ -4961,12 +5132,12 @@ struct SENSE_DATA {
 ** 					disabled. When set, the Circular Queues are fully enabled.
 **************************************************************************
 */
-#define     ARCMSR_MU_CONFIGURATION_REG  	          0xFFFFE350
-#define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K  	          0x0020
+#define     ARCMSR_MU_CONFIGURATION_REG  	          0xFFFFE350        
+#define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K  	          0x0020    
 #define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K  	          0x0010
-#define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K  	          0x0008
-#define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K  	          0x0004
-#define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K  	          0x0002
+#define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K  	          0x0008   
+#define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K  	          0x0004   
+#define     ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K  	          0x0002    
 #define     ARCMSR_MU_CIRCULAR_QUEUE_ENABLE  	          0x0001        /*0:disable 1:enable*/
 /*
 **************************************************************************
@@ -4974,27 +5145,27 @@ struct SENSE_DATA {
 **
 **  . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues.
 **    The base address is required to be located on a 1 Mbyte address boundary.
-**  . All Circular Queue head and tail pointers are based on the QBAR.
-**    When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits.
+**  . All Circular Queue head and tail pointers are based on the QBAR. 
+**    When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 
 **    Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register.
-**  Warning:
-**         The QBAR must designate a range allocated to the 80331 DDR SDRAM interface
+**  Warning: 
+**         The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 
 **  ------------------------------------------------------------------------
 **  Bit       Default                       Description
 **  31:20     000H                          Queue Base Address - Local memory address of the circular queues.
 **  19:00     00000H                        Reserved
 **************************************************************************
 */
-#define     ARCMSR_MU_QUEUE_BASE_ADDRESS_REG  	      0xFFFFE354
+#define     ARCMSR_MU_QUEUE_BASE_ADDRESS_REG  	      0xFFFFE354   
 /*
 **************************************************************************
 **  Inbound Free Head Pointer Register - IFHPR
 **
-**  . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from
-**    the Queue Base Address of the head pointer for the Inbound Free Queue.
+**  . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 
+**    the Queue Base Address of the head pointer for the Inbound Free Queue. 
 **    The Head Pointer must be aligned on a DWORD address boundary.
-**    When read, the Queue Base Address is provided in the upper 12 bits of the register.
-**    Writes to the upper 12 bits of the register are ignored.
+**    When read, the Queue Base Address is provided in the upper 12 bits of the register. 
+**    Writes to the upper 12 bits of the register are ignored. 
 **    This register is maintained by software.
 **  ------------------------------------------------------------------------
 **  Bit       Default                       Description
@@ -5003,7 +5174,7 @@ struct SENSE_DATA {
 **  01:00     00 2                          Reserved
 **************************************************************************
 */
-#define     ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG       0xFFFFE360
+#define     ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG       0xFFFFE360   
 /*
 **************************************************************************
 **  Inbound Free Tail Pointer Register - IFTPR
@@ -5019,7 +5190,7 @@ struct SENSE_DATA {
 **  01:00     00 2                          Reserved
 **************************************************************************
 */
-#define     ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG       0xFFFFE364
+#define     ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG       0xFFFFE364  
 /*
 **************************************************************************
 **  Inbound Post Head Pointer Register - IPHPR
@@ -5059,7 +5230,7 @@ struct SENSE_DATA {
 **  . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register.
 **    It is written by the MU when the Index Registers are written by a PCI agent.
 **    The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared.
-**  . The local memory address of the Index Register least recently accessed is computed
+**  . The local memory address of the Index Register least recently accessed is computed 
 **    by adding the Index Address Register to the Inbound ATU Translate Value Register.
 **  ------------------------------------------------------------------------
 **  Bit       Default                       Description
@@ -5079,7 +5250,7 @@ struct SENSE_DATA {
 **    	(A) Header : 3 bytes sequence (0x5E, 0x01, 0x61)
 **    	(B) Command block : variable length of data including length, command code, data and checksum byte
 **    	(C) Return data : variable length of data
-**  --------------------------------------------------------------------
+**  --------------------------------------------------------------------  
 **    2. Command block
 **  --------------------------------------------------------------------
 **    	(A) 1st byte : command block length (low byte)
@@ -5088,7 +5259,7 @@ struct SENSE_DATA {
 **    	(C) 3rd byte : command code
 **    	(D) 4th and following bytes : variable length data bytes depends on command code
 **    	(E) last byte : checksum byte (sum of 1st byte until last data byte)
-**  --------------------------------------------------------------------
+**  --------------------------------------------------------------------  
 **    3. Command code and associated data
 **  --------------------------------------------------------------------
 **    	The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management,
@@ -5226,8 +5397,8 @@ struct SENSE_DATA {
 **    	    byte 7 			: raid level
 **    	    byte 8 			: stripe size
 **    	    byte 9 			: spare
-**    	    byte 10/11/12/13: device mask (the devices to create raid/volume)
-**    		                  This function is removed, application like to implement quick create function
+**    	    byte 10/11/12/13: device mask (the devices to create raid/volume) 
+**    		                  This function is removed, application like to implement quick create function 
 **    		                  need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function.
 **      GUI_GET_INFO_R : Get Raid Set Information
 **    		byte 0,1        : length
@@ -5271,7 +5442,7 @@ struct SENSE_DATA {
 **    		DWORD gvsNewStripeSize;
 **    		DWORD gvsVolumeStatus;
 **    		DWORD gvsProgress; //     32
-**    		sSCSI_ATTR gvsScsi;
+**    		sSCSI_ATTR gvsScsi; 
 **    		BYTE gvsMemberDisks;
 **    		BYTE gvsRaidLevel; //     8
 **
@@ -5460,7 +5631,7 @@ struct SENSE_DATA {
 **    		byte 2          : command code 0x51
 **    		byte 3          : raidset#
 **
-**    	GUI_EXPAND_RAIDSET : Expand Raid Set
+**    	GUI_EXPAND_RAIDSET : Expand Raid Set 
 **    		byte 0,1        : length
 **    		byte 2          : command code 0x52
 **    		byte 3          : raidset#
@@ -5468,22 +5639,22 @@ struct SENSE_DATA {
 **    		byte 8/9/10     : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K )
 **    		byte 11/12/13   : repeat for each volume in the raidset ....
 **
-**      GUI_ACTIVATE_RAIDSET : Activate incomplete raid set
+**      GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 
 **    		byte 0,1        : length
 **    		byte 2          : command code 0x53
 **    		byte 3          : raidset#
 **
-**      GUI_CREATE_HOT_SPARE : Create hot spare disk
+**      GUI_CREATE_HOT_SPARE : Create hot spare disk 
 **    		byte 0,1        : length
 **    		byte 2          : command code 0x54
 **    		byte 3/4/5/6    : device mask for hot spare creation
 **
-**    	GUI_DELETE_HOT_SPARE : Delete hot spare disk
+**    	GUI_DELETE_HOT_SPARE : Delete hot spare disk 
 **    		byte 0,1        : length
 **    		byte 2          : command code 0x55
 **    		byte 3/4/5/6    : device mask for hot spare deletion
 **
-**    	GUI_CREATE_VOLUME : Create volume set
+**    	GUI_CREATE_VOLUME : Create volume set 
 **    		byte 0,1        : length
 **    		byte 2          : command code 0x60
 **    		byte 3          : raidset#
@@ -5529,9 +5700,9 @@ struct SENSE_DATA {
 **    	GUI_STOP_CHECK_VOLUME : Stop volume consistency check
 **    		byte 0,1        : length
 **    		byte 2          : command code 0x64
-** ---------------------------------------------------------------------
+** ---------------------------------------------------------------------   
 **    4. Returned data
-** ---------------------------------------------------------------------
+** ---------------------------------------------------------------------   
 **    	(A) Header          : 3 bytes sequence (0x5E, 0x01, 0x61)
 **    	(B) Length          : 2 bytes (low byte 1st, excludes length and checksum byte)
 **    	(C) status or data  :
-- 
1.8.2.2

