diff --git a/sys/dev/netif/re/if_re.c b/sys/dev/netif/re/if_re.c
index 34d7b9a..dc1a1a3 100644
--- a/sys/dev/netif/re/if_re.c
+++ b/sys/dev/netif/re/if_re.c
@@ -2621,10 +2621,36 @@ re_init(void *xsc)
 		CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
 
 	framelen = RE_FRAMELEN(ifp->if_mtu);
-	if (framelen < MCLBYTES)
+	if (framelen < MCLBYTES) {
 		CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
-	else
-		CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
+		if (sc->re_macver == RE_MACVER_2E ||
+		    sc->re_macver == RE_MACVER_2F) {
+			uint8_t val;
+
+			val = CSR_READ_1(sc, RE_CFG3);
+			CSR_WRITE_1(sc, RE_CFG3, val & ~(1 << 2));
+
+			val = CSR_READ_1(sc, RE_CFG4);
+			CSR_WRITE_1(sc, RE_CFG4, val & ~0x1);
+		}
+	} else {
+		if (sc->re_macver == RE_MACVER_2E ||
+		    sc->re_macver == RE_MACVER_2F) {
+			uint8_t val;
+
+			CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 0x2c);
+
+			val = CSR_READ_1(sc, RE_CFG3);
+			CSR_WRITE_1(sc, RE_CFG3, val | (1 << 2));
+
+			val = CSR_READ_1(sc, RE_CFG4);
+			CSR_WRITE_1(sc, RE_CFG4, val | 0x1);
+
+			ifp->if_hwassist = 0;
+		} else {
+			CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
+		}
+	}
 
 	CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
 
diff --git a/sys/dev/netif/re/if_rereg.h b/sys/dev/netif/re/if_rereg.h
index 11756eb..258a82d 100644
--- a/sys/dev/netif/re/if_rereg.h
+++ b/sys/dev/netif/re/if_rereg.h
@@ -71,7 +71,9 @@
 #define RE_CFG0		0x0051		/* config register #0 */
 #define RE_CFG1		0x0052		/* config register #1 */
 #define RE_CFG2		0x0053		/* config register #2 */
-                                        /* 0054-0057 reserved */   
+#define RE_CFG3		0x0054		/* config register #3 */
+#define RE_CFG4		0x0055		/* config register #4 */
+                                        /* 0056-0057 reserved */   
 #define RE_MEDIASTAT	0x0058		/* media status register (8139) */
 					/* 0059-005A reserved */
 #define RE_MII		0x005A		/* 8129 chip only */
@@ -105,7 +107,6 @@
 #define RE_TXLIST_ADDR_HI	0x0024	/* 64 bits, 256 byte alignment */
 #define RE_TXLIST_ADDR_HPRIO_LO	0x0028	/* 64 bits, 256 byte alignment */
 #define RE_TXLIST_ADDR_HPRIO_HI	0x002C	/* 64 bits, 256 byte alignment */
-#define RE_CFG2			0x0053
 #define RE_TIMERINT		0x0054	/* interrupt on timer expire */
 #define RE_TXSTART		0x00D9	/* 8 bits */
 #define RE_CPLUS_CMD		0x00E0	/* 16 bits */