commit 884344674cfe03597bb8d89a8a1ccf69e53af36b
Author: Hasso Tepper <hasso@estpak.ee>
Date:   Tue May 12 22:48:59 2009 +0300

    ath(4) HAL update to the open source version 081128.
    
    Submitted-by: Alexander Polakov <polachok@gmail.com>

diff --git a/sys/contrib/dev/ath/COPYRIGHT b/sys/contrib/dev/ath/COPYRIGHT
deleted file mode 100644
index 3e2752f..0000000
--- a/sys/contrib/dev/ath/COPYRIGHT
+++ /dev/null
@@ -1,42 +0,0 @@
-All files contained in this distribution are covered by the following
-copyright unless explicitly identified otherwise.  Note that this
-copyright does _NOT_ contain a "or GPL" clause and does _NOT_ permit
-redistribution with changes.
-
-/*-
- * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
- * Communications, Inc.  All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. The materials contained herein are unmodified and are used
- *    unmodified.
- * 2. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following NO
- *    ''WARRANTY'' disclaimer below (''Disclaimer''), without
- *    modification.
- * 3. Redistributions in binary form must reproduce at minimum a
- *    disclaimer similar to the Disclaimer below and any redistribution
- *    must be conditioned upon including a substantially similar
- *    Disclaimer requirement for further binary redistribution.
- * 4. Neither the names of the above-listed copyright holders nor the
- *    names of any contributors may be used to endorse or promote
- *    product derived from this software without specific prior written
- *    permission.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
- * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
- * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/sam_hal/COPYRIGHT#1 $
- */
diff --git a/sys/contrib/dev/ath/README b/sys/contrib/dev/ath/README
deleted file mode 100644
index 5d3b7f5..0000000
--- a/sys/contrib/dev/ath/README
+++ /dev/null
@@ -1,73 +0,0 @@
-$Id: //depot/sw/branches/sam_hal/README#2 $
-
-
-Atheros Hardware Access Layer (HAL)
-===================================
-
-* Copyright (c) 2002-2006 Sam Leffler.
-* Copyright (c) 2002-2006 Atheros Communications, Inc.
-* All rights reserved.
-
-Read the file COPYRIGHT for the complete copyright.
-
-This code manages much of the chip-specific operation of the Atheros
-driver.  The HAL is provided in a binary-only form in order to
-comply with local regulatory agency rules.  In the United States
-the FCC requires that a radio transmitter only be operated at power
-levels and on frequency channels for which it is approved.  The FCC
-requires that a software-defined radio cannot be configured by a
-user to operate outside the approved power levels and frequency
-channels.  This makes it difficult to open-source code that enforces
-limits on the power levels, frequency channels and other parameters
-of the radio transmitter.  See
-
-http://ftp.fcc.gov/Bureaus/Engineering_Technology/Orders/2001/fcc01264.pdf
-
-for the specific FCC regulation.  Because the module is provided
-in a binary-only form it is marked "Proprietary" on Linux; this
-means when you load it you will see messages that your system is
-now "tainted".
-
-If you wish to use this driver on a platform for which an ath_hal
-module is not already provided please contact the author.  Note that
-this is only necessary for new _architectures_; the HAL is not tied to
-any specific version of your operating system.
-
-
-Atheros Hardware
-================
-There are many generations of Atheros 802.11 wireless devices that
-are typically referred to by their programming model:
-
-5210	supports 11a only
-5211	supports both 11a and 11b
-5212	supports 11a, 11b, and 11g
-
-These parts have been incorporated in a variety of retail products
-including cardbus cards and mini-pci cards.  In addition many laptop
-vendors use Atheros mini-pci cards for their builtin wireless
-support.
-
-The Atheors PCI vendor id is 0x168c.  The file ah_devid.h lists most
-known PCI device id's but is not exhaustive.  Some vendors program
-their own vendor and/or device id's to aid in BIOS-locking mini-pci
-cards in laptops.
-
-Atheros SoC Hardware
-====================
-In addition to the cardbus/pci devices Atheros makes System on Chip
-(SoC) parts that integrate a MIPS cpu core and one or more MAC and
-radio parts.  Binary support for these parts is necessarily built
-for the embedded MIPS processor where the code is to be run.
-
-Caveats
-=======
-The binary hal builds provided here include no floating point and
-are operating system-independent.  However due to toolchain
-peculiarities the .o files may be wrongly rejected by development
-tools.  If that happens it may be possible to patch the file header
-so that the native toolchain will accept the files.  In particular
-this has been observed for various Linux MIPS installations for the
-SoC parts.  If you have issues consult the associated .inc file in
-the public directory; it explains exactly how the binary file was
-created (e.g. toolchain and compilation options).
diff --git a/sys/contrib/dev/ath/ah.h b/sys/contrib/dev/ath/ah.h
deleted file mode 100644
index 411acbe..0000000
--- a/sys/contrib/dev/ath/ah.h
+++ /dev/null
@@ -1,879 +0,0 @@
-/*-
- * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
- * Communications, Inc.  All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. The materials contained herein are unmodified and are used
- *    unmodified.
- * 2. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following NO
- *    ''WARRANTY'' disclaimer below (''Disclaimer''), without
- *    modification.
- * 3. Redistributions in binary form must reproduce at minimum a
- *    disclaimer similar to the Disclaimer below and any redistribution
- *    must be conditioned upon including a substantially similar
- *    Disclaimer requirement for further binary redistribution.
- * 4. Neither the names of the above-listed copyright holders nor the
- *    names of any contributors may be used to endorse or promote
- *    product derived from this software without specific prior written
- *    permission.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
- * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
- * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/sam_hal/ah.h#19 $
- */
-
-#ifndef _ATH_AH_H_
-#define _ATH_AH_H_
-/*
- * Atheros Hardware Access Layer
- *
- * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
- * structure for use with the device.  Hardware-related operations that
- * follow must call back into the HAL through interface, supplying the
- * reference as the first parameter.
- */
-
-/*
- * Bus i/o type definitions.  We define a platform-independent
- * set of types that are mapped to platform-dependent data for
- * register read/write operations.  We use types that are large
- * enough to hold a pointer; smaller data should fit and only
- * require type coercion to work.  Larger data can be stored
- * elsewhere and a reference passed for the bus tag and/or handle.
- */
-typedef void* HAL_SOFTC;		/* pointer to driver/OS state */
-typedef void* HAL_BUS_TAG;		/* opaque bus i/o id tag */
-typedef void* HAL_BUS_HANDLE;		/* opaque bus i/o handle */
-
-#include "ah_osdep.h"
-
-/*
- * __ahdecl is analogous to _cdecl; it defines the calling
- * convention used within the HAL.  For most systems this
- * can just default to be empty and the compiler will (should)
- * use _cdecl.  For systems where _cdecl is not compatible this
- * must be defined.  See linux/ah_osdep.h for an example.
- */
-#ifndef __ahdecl
-#define __ahdecl
-#endif
-
-/*
- * Status codes that may be returned by the HAL.  Note that
- * interfaces that return a status code set it only when an
- * error occurs--i.e. you cannot check it for success.
- */
-typedef enum {
-	HAL_OK		= 0,	/* No error */
-	HAL_ENXIO	= 1,	/* No hardware present */
-	HAL_ENOMEM	= 2,	/* Memory allocation failed */
-	HAL_EIO		= 3,	/* Hardware didn't respond as expected */
-	HAL_EEMAGIC	= 4,	/* EEPROM magic number invalid */
-	HAL_EEVERSION	= 5,	/* EEPROM version invalid */
-	HAL_EELOCKED	= 6,	/* EEPROM unreadable */
-	HAL_EEBADSUM	= 7,	/* EEPROM checksum invalid */
-	HAL_EEREAD	= 8,	/* EEPROM read problem */
-	HAL_EEBADMAC	= 9,	/* EEPROM mac address invalid */
-	HAL_EESIZE	= 10,	/* EEPROM size not supported */
-	HAL_EEWRITE	= 11,	/* Attempt to change write-locked EEPROM */
-	HAL_EINVAL	= 12,	/* Invalid parameter to function */
-	HAL_ENOTSUPP	= 13,	/* Hardware revision not supported */
-	HAL_ESELFTEST	= 14,	/* Hardware self-test failed */
-	HAL_EINPROGRESS	= 15,	/* Operation incomplete */
-} HAL_STATUS;
-
-typedef enum {
-	AH_FALSE = 0,		/* NB: lots of code assumes false is zero */
-	AH_TRUE  = 1,
-} HAL_BOOL;
-
-typedef enum {
-	HAL_CAP_REG_DMN		= 0,	/* current regulatory domain */
-	HAL_CAP_CIPHER		= 1,	/* hardware supports cipher */
-	HAL_CAP_TKIP_MIC	= 2,	/* handle TKIP MIC in hardware */
-	HAL_CAP_TKIP_SPLIT	= 3,	/* hardware TKIP uses split keys */
-	HAL_CAP_PHYCOUNTERS	= 4,	/* hardware PHY error counters */
-	HAL_CAP_DIVERSITY	= 5,	/* hardware supports fast diversity */
-	HAL_CAP_KEYCACHE_SIZE	= 6,	/* number of entries in key cache */
-	HAL_CAP_NUM_TXQUEUES	= 7,	/* number of hardware xmit queues */
-	HAL_CAP_VEOL		= 9,	/* hardware supports virtual EOL */
-	HAL_CAP_PSPOLL		= 10,	/* hardware has working PS-Poll support */
-	HAL_CAP_DIAG		= 11,	/* hardware diagnostic support */
-	HAL_CAP_COMPRESSION	= 12,	/* hardware supports compression */
-	HAL_CAP_BURST		= 13,	/* hardware supports packet bursting */
-	HAL_CAP_FASTFRAME	= 14,	/* hardware supoprts fast frames */
-	HAL_CAP_TXPOW		= 15,	/* global tx power limit  */
-	HAL_CAP_TPC		= 16,	/* per-packet tx power control  */
-	HAL_CAP_PHYDIAG		= 17,	/* hardware phy error diagnostic */
-	HAL_CAP_BSSIDMASK	= 18,	/* hardware supports bssid mask */
-	HAL_CAP_MCAST_KEYSRCH	= 19,	/* hardware has multicast key search */
-	HAL_CAP_TSF_ADJUST	= 20,	/* hardware has beacon tsf adjust */
-	HAL_CAP_XR		= 21,	/* hardware has XR support  */
-	HAL_CAP_WME_TKIPMIC 	= 22,   /* hardware can support TKIP MIC when WMM is turned on */
-	HAL_CAP_CHAN_HALFRATE 	= 23,	/* hardware can support half rate channels */
-	HAL_CAP_CHAN_QUARTERRATE = 24,	/* hardware can support quarter rate channels */
-	HAL_CAP_RFSILENT	= 25,	/* hardware has rfsilent support  */
-	HAL_CAP_TPC_ACK		= 26,	/* ack txpower with per-packet tpc */
-	HAL_CAP_TPC_CTS		= 27,	/* cts txpower with per-packet tpc */
-	HAL_CAP_11D		= 28,   /* 11d beacon support for changing cc */
-	HAL_CAP_INTMIT		= 29,	/* interference mitigation */
-	HAL_CAP_RXORN_FATAL	= 30,	/* HAL_INT_RXORN treated as fatal */
-	HAL_CAP_RXTSTAMP_PREC	= 34,	/* rx desc tstamp precision (bits) */
-} HAL_CAPABILITY_TYPE;
-
-/* 
- * "States" for setting the LED.  These correspond to
- * the possible 802.11 operational states and there may
- * be a many-to-one mapping between these states and the
- * actual hardware state for the LED's (i.e. the hardware
- * may have fewer states).
- */
-typedef enum {
-	HAL_LED_INIT	= 0,
-	HAL_LED_SCAN	= 1,
-	HAL_LED_AUTH	= 2,
-	HAL_LED_ASSOC	= 3,
-	HAL_LED_RUN	= 4
-} HAL_LED_STATE;
-
-/*
- * Transmit queue types/numbers.  These are used to tag
- * each transmit queue in the hardware and to identify a set
- * of transmit queues for operations such as start/stop dma.
- */
-typedef enum {
-	HAL_TX_QUEUE_INACTIVE	= 0,		/* queue is inactive/unused */
-	HAL_TX_QUEUE_DATA	= 1,		/* data xmit q's */
-	HAL_TX_QUEUE_BEACON	= 2,		/* beacon xmit q */
-	HAL_TX_QUEUE_CAB	= 3,		/* "crap after beacon" xmit q */
-	HAL_TX_QUEUE_UAPSD	= 4,		/* u-apsd power save xmit q */
-} HAL_TX_QUEUE;
-
-#define	HAL_NUM_TX_QUEUES	10		/* max possible # of queues */
-
-/*
- * Transmit queue subtype.  These map directly to
- * WME Access Categories (except for UPSD).  Refer
- * to Table 5 of the WME spec.
- */
-typedef enum {
-	HAL_WME_AC_BK	= 0,			/* background access category */
-	HAL_WME_AC_BE	= 1, 			/* best effort access category*/
-	HAL_WME_AC_VI	= 2,			/* video access category */
-	HAL_WME_AC_VO	= 3,			/* voice access category */
-	HAL_WME_UPSD	= 4,			/* uplink power save */
-	HAL_XR_DATA	= 5,			/* uplink power save */
-} HAL_TX_QUEUE_SUBTYPE;
-
-/*
- * Transmit queue flags that control various
- * operational parameters.
- */
-typedef enum {
-	/*
-	 * Per queue interrupt enables.  When set the associated
-	 * interrupt may be delivered for packets sent through
-	 * the queue.  Without these enabled no interrupts will
-	 * be delivered for transmits through the queue.
-	 */
-	HAL_TXQ_TXOKINT_ENABLE	   = 0x0001,	/* enable TXOK interrupt */
-	HAL_TXQ_TXERRINT_ENABLE	   = 0x0001,	/* enable TXERR interrupt */
-	HAL_TXQ_TXDESCINT_ENABLE   = 0x0002,	/* enable TXDESC interrupt */
-	HAL_TXQ_TXEOLINT_ENABLE	   = 0x0004,	/* enable TXEOL interrupt */
-	HAL_TXQ_TXURNINT_ENABLE	   = 0x0008,	/* enable TXURN interrupt */
-	/*
-	 * Enable hardware compression for packets sent through
-	 * the queue.  The compression buffer must be setup and
-	 * packets must have a key entry marked in the tx descriptor.
-	 */
-	HAL_TXQ_COMPRESSION_ENABLE  = 0x0010,	/* enable h/w compression */
-	/*
-	 * Disable queue when veol is hit or ready time expires.
-	 * By default the queue is disabled only on reaching the
-	 * physical end of queue (i.e. a null link ptr in the
-	 * descriptor chain).
-	 */
-	HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
-	/*
-	 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
-	 * event.  Frames will be transmitted only when this timer
-	 * fires, e.g to transmit a beacon in ap or adhoc modes.
-	 */
-	HAL_TXQ_DBA_GATED	    = 0x0040,	/* schedule based on DBA */
-	/*
-	 * Each transmit queue has a counter that is incremented
-	 * each time the queue is enabled and decremented when
-	 * the list of frames to transmit is traversed (or when
-	 * the ready time for the queue expires).  This counter
-	 * must be non-zero for frames to be scheduled for
-	 * transmission.  The following controls disable bumping
-	 * this counter under certain conditions.  Typically this
-	 * is used to gate frames based on the contents of another
-	 * queue (e.g. CAB traffic may only follow a beacon frame).
-	 * These are meaningful only when frames are scheduled
-	 * with a non-ASAP policy (e.g. DBA-gated).
-	 */
-	HAL_TXQ_CBR_DIS_QEMPTY	    = 0x0080,	/* disable on this q empty */
-	HAL_TXQ_CBR_DIS_BEMPTY	    = 0x0100,	/* disable on beacon q empty */
-
-	/*
-	 * Fragment burst backoff policy.  Normally the no backoff
-	 * is done after a successful transmission, the next fragment
-	 * is sent at SIFS.  If this flag is set backoff is done
-	 * after each fragment, regardless whether it was ack'd or
-	 * not, after the backoff count reaches zero a normal channel
-	 * access procedure is done before the next transmit (i.e.
-	 * wait AIFS instead of SIFS).
-	 */
-	HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
-	/*
-	 * Disable post-tx backoff following each frame.
-	 */
-	HAL_TXQ_BACKOFF_DISABLE	    = 0x00010000, /* disable post backoff  */
-	/*
-	 * DCU arbiter lockout control.  This controls how
-	 * lower priority tx queues are handled with respect to
-	 * to a specific queue when multiple queues have frames
-	 * to send.  No lockout means lower priority queues arbitrate
-	 * concurrently with this queue.  Intra-frame lockout
-	 * means lower priority queues are locked out until the
-	 * current frame transmits (e.g. including backoffs and bursting).
-	 * Global lockout means nothing lower can arbitrary so
-	 * long as there is traffic activity on this queue (frames,
-	 * backoff, etc).
-	 */
-	HAL_TXQ_ARB_LOCKOUT_INTRA   = 0x00020000, /* intra-frame lockout */
-	HAL_TXQ_ARB_LOCKOUT_GLOBAL  = 0x00040000, /* full lockout s */
-
-	HAL_TXQ_IGNORE_VIRTCOL	    = 0x00080000, /* ignore virt collisions */
-	HAL_TXQ_SEQNUM_INC_DIS	    = 0x00100000, /* disable seqnum increment */
-} HAL_TX_QUEUE_FLAGS;
-
-typedef struct {
-	u_int32_t	tqi_ver;		/* hal TXQ version */
-	HAL_TX_QUEUE_SUBTYPE tqi_subtype;	/* subtype if applicable */
-	HAL_TX_QUEUE_FLAGS tqi_qflags;		/* flags (see above) */
-	u_int32_t	tqi_priority;		/* (not used) */
-	u_int32_t	tqi_aifs;		/* aifs */
-	u_int32_t	tqi_cwmin;		/* cwMin */
-	u_int32_t	tqi_cwmax;		/* cwMax */
-	u_int16_t	tqi_shretry;		/* rts retry limit */
-	u_int16_t	tqi_lgretry;		/* long retry limit (not used)*/
-	u_int32_t	tqi_cbrPeriod;		/* CBR period (us) */
-	u_int32_t	tqi_cbrOverflowLimit;	/* threshold for CBROVF int */
-	u_int32_t	tqi_burstTime;		/* max burst duration (us) */
-	u_int32_t	tqi_readyTime;		/* frame schedule time (us) */
-	u_int32_t	tqi_compBuf;		/* comp buffer phys addr */
-} HAL_TXQ_INFO;
-
-#define HAL_TQI_NONVAL 0xffff
-
-/* token to use for aifs, cwmin, cwmax */
-#define	HAL_TXQ_USEDEFAULT	((u_int32_t) -1)
-
-/* compression definitions */
-#define HAL_COMP_BUF_MAX_SIZE           9216            /* 9K */
-#define HAL_COMP_BUF_ALIGN_SIZE         512
-
-/*
- * Transmit packet types.  This belongs in ah_desc.h, but
- * is here so we can give a proper type to various parameters
- * (and not require everyone include the file).
- *
- * NB: These values are intentionally assigned for
- *     direct use when setting up h/w descriptors.
- */
-typedef enum {
-	HAL_PKT_TYPE_NORMAL	= 0,
-	HAL_PKT_TYPE_ATIM	= 1,
-	HAL_PKT_TYPE_PSPOLL	= 2,
-	HAL_PKT_TYPE_BEACON	= 3,
-	HAL_PKT_TYPE_PROBE_RESP	= 4,
-	HAL_PKT_TYPE_CHIRP	= 5,
-	HAL_PKT_TYPE_GRP_POLL = 6,
-} HAL_PKT_TYPE;
-
-/* Rx Filter Frame Types */
-typedef enum {
-	HAL_RX_FILTER_UCAST	= 0x00000001,	/* Allow unicast frames */
-	HAL_RX_FILTER_MCAST	= 0x00000002,	/* Allow multicast frames */
-	HAL_RX_FILTER_BCAST	= 0x00000004,	/* Allow broadcast frames */
-	HAL_RX_FILTER_CONTROL	= 0x00000008,	/* Allow control frames */
-	HAL_RX_FILTER_BEACON	= 0x00000010,	/* Allow beacon frames */
-	HAL_RX_FILTER_PROM	= 0x00000020,	/* Promiscuous mode */
-	HAL_RX_FILTER_XRPOLL	= 0x00000040,	/* Allow XR poll frmae */
-	HAL_RX_FILTER_PROBEREQ	= 0x00000080,	/* Allow probe request frames */
-	HAL_RX_FILTER_PHYERR	= 0x00000100,	/* Allow phy errors */
-	HAL_RX_FILTER_PHYRADAR	= 0x00000200,	/* Allow phy radar errors*/
-} HAL_RX_FILTER;
-
-typedef enum {
-	HAL_PM_AWAKE		= 0,
-	HAL_PM_FULL_SLEEP	= 1,
-	HAL_PM_NETWORK_SLEEP	= 2,
-	HAL_PM_UNDEFINED	= 3
-} HAL_POWER_MODE;
-
-/*
- * NOTE WELL:
- * These are mapped to take advantage of the common locations for many of
- * the bits on all of the currently supported MAC chips. This is to make
- * the ISR as efficient as possible, while still abstracting HW differences.
- * When new hardware breaks this commonality this enumerated type, as well
- * as the HAL functions using it, must be modified. All values are directly
- * mapped unless commented otherwise.
- */
-typedef enum {
-	HAL_INT_RX	= 0x00000001,	/* Non-common mapping */
-	HAL_INT_RXDESC	= 0x00000002,
-	HAL_INT_RXNOFRM	= 0x00000008,
-	HAL_INT_RXEOL	= 0x00000010,
-	HAL_INT_RXORN	= 0x00000020,
-	HAL_INT_TX	= 0x00000040,	/* Non-common mapping */
-	HAL_INT_TXDESC	= 0x00000080,
-	HAL_INT_TXURN	= 0x00000800,
-	HAL_INT_MIB	= 0x00001000,
-	HAL_INT_RXPHY	= 0x00004000,
-	HAL_INT_RXKCM	= 0x00008000,
-	HAL_INT_SWBA	= 0x00010000,
-	HAL_INT_BMISS	= 0x00040000,
-	HAL_INT_BNR	= 0x00100000,	/* Non-common mapping */
-	HAL_INT_TIM	= 0x00200000,	/* Non-common mapping */
-	HAL_INT_DTIM	= 0x00400000,	/* Non-common mapping */
-	HAL_INT_DTIMSYNC= 0x00800000,	/* Non-common mapping */
-	HAL_INT_GPIO	= 0x01000000,
-	HAL_INT_CABEND	= 0x02000000,	/* Non-common mapping */
-	HAL_INT_FATAL	= 0x40000000,	/* Non-common mapping */
-#define	HAL_INT_GLOBAL	0x80000000	/* Set/clear IER */
-	HAL_INT_BMISC	= HAL_INT_TIM
-			| HAL_INT_DTIM
-			| HAL_INT_DTIMSYNC
-			| HAL_INT_CABEND,
-
-	/* Interrupt bits that map directly to ISR/IMR bits */
-	HAL_INT_COMMON  = HAL_INT_RXNOFRM
-			| HAL_INT_RXDESC
-			| HAL_INT_RXEOL
-			| HAL_INT_RXORN
-			| HAL_INT_TXURN
-			| HAL_INT_TXDESC
-			| HAL_INT_MIB
-			| HAL_INT_RXPHY
-			| HAL_INT_RXKCM
-			| HAL_INT_SWBA
-			| HAL_INT_BMISS
-			| HAL_INT_GPIO,
-} HAL_INT;
-
-typedef enum {
-	HAL_RFGAIN_INACTIVE		= 0,
-	HAL_RFGAIN_READ_REQUESTED	= 1,
-	HAL_RFGAIN_NEED_CHANGE		= 2
-} HAL_RFGAIN;
-
-/*
- * Channels are specified by frequency.
- */
-typedef struct {
-	u_int16_t	channel;	/* setting in Mhz */
-	u_int16_t	channelFlags;	/* see below */
-	u_int8_t	privFlags;
-	int8_t		maxRegTxPower;	/* max regulatory tx power in dBm */
-	int8_t		maxTxPower;	/* max true tx power in 0.5 dBm */
-	int8_t		minTxPower;	/* min true tx power in 0.5 dBm */
-} HAL_CHANNEL;
-
-/* channelFlags */
-#define	CHANNEL_CW_INT	0x0002	/* CW interference detected on channel */
-#define	CHANNEL_TURBO	0x0010	/* Turbo Channel */
-#define	CHANNEL_CCK	0x0020	/* CCK channel */
-#define	CHANNEL_OFDM	0x0040	/* OFDM channel */
-#define	CHANNEL_2GHZ	0x0080	/* 2 GHz spectrum channel. */
-#define	CHANNEL_5GHZ	0x0100	/* 5 GHz spectrum channel */
-#define	CHANNEL_PASSIVE	0x0200	/* Only passive scan allowed in the channel */
-#define	CHANNEL_DYN	0x0400	/* dynamic CCK-OFDM channel */
-#define	CHANNEL_XR	0x0800	/* XR channel */
-#define	CHANNEL_STURBO	0x2000	/* Static turbo, no 11a-only usage */
-#define CHANNEL_HALF    0x4000 	/* Half rate channel */
-#define CHANNEL_QUARTER 0x8000 	/* Quarter rate channel */
-
-/* privFlags */
-#define CHANNEL_INTERFERENCE   	0x01 /* Software use: channel interference 
-				        used for as AR as well as RADAR 
-				        interference detection */
-#define CHANNEL_DFS		0x02 /* DFS required on channel */
-#define CHANNEL_4MS_LIMIT	0x04 /* 4msec packet limit on this channel */
-#define CHANNEL_DFS_CLEAR	0x08 /* if channel has been checked for DFS */
-
-#define	CHANNEL_A	(CHANNEL_5GHZ|CHANNEL_OFDM)
-#define	CHANNEL_B	(CHANNEL_2GHZ|CHANNEL_CCK)
-#define	CHANNEL_PUREG	(CHANNEL_2GHZ|CHANNEL_OFDM)
-#ifdef notdef
-#define	CHANNEL_G	(CHANNEL_2GHZ|CHANNEL_DYN)
-#else
-#define	CHANNEL_G	(CHANNEL_2GHZ|CHANNEL_OFDM)
-#endif
-#define	CHANNEL_T	(CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
-#define CHANNEL_ST	(CHANNEL_T|CHANNEL_STURBO)
-#define	CHANNEL_108G	(CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
-#define	CHANNEL_108A	CHANNEL_T
-#define	CHANNEL_X	(CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
-#define	CHANNEL_ALL \
-	(CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | CHANNEL_TURBO)
-#define	CHANNEL_ALL_NOTURBO 	(CHANNEL_ALL &~ CHANNEL_TURBO)
-
-#define HAL_ANTENNA_MIN_MODE  0
-#define HAL_ANTENNA_FIXED_A   1
-#define HAL_ANTENNA_FIXED_B   2
-#define HAL_ANTENNA_MAX_MODE  3
-
-typedef struct {
-	u_int32_t	ackrcv_bad;
-	u_int32_t	rts_bad;
-	u_int32_t	rts_good;
-	u_int32_t	fcs_bad;
-	u_int32_t	beacons;
-} HAL_MIB_STATS;
-
-typedef u_int16_t HAL_CTRY_CODE;		/* country code */
-typedef u_int16_t HAL_REG_DOMAIN;		/* regulatory domain code */
-
-enum {
-	CTRY_DEBUG	= 0x1ff,		/* debug country code */
-	CTRY_DEFAULT	= 0			/* default country code */
-};
-
-enum {
-	HAL_MODE_11A	= 0x001,		/* 11a channels */
-	HAL_MODE_TURBO	= 0x002,		/* 11a turbo-only channels */
-	HAL_MODE_11B	= 0x004,		/* 11b channels */
-	HAL_MODE_PUREG	= 0x008,		/* 11g channels (OFDM only) */
-#ifdef notdef
-	HAL_MODE_11G	= 0x010,		/* 11g channels (OFDM/CCK) */
-#else
-	HAL_MODE_11G	= 0x008,		/* XXX historical */
-#endif
-	HAL_MODE_108G	= 0x020,		/* 11a+Turbo channels */
-	HAL_MODE_108A	= 0x040,		/* 11g+Turbo channels */
-	HAL_MODE_XR     = 0x100,		/* XR channels */
-	HAL_MODE_11A_HALF_RATE = 0x200,		/* 11A half rate channels */
-	HAL_MODE_11A_QUARTER_RATE = 0x400,	/* 11A quarter rate channels */
-	HAL_MODE_ALL	= 0xfff
-};
-
-typedef struct {
-	int		rateCount;		/* NB: for proper padding */
-	u_int8_t	rateCodeToIndex[32];	/* back mapping */
-	struct {
-		u_int8_t	valid;		/* valid for rate control use */
-		u_int8_t	phy;		/* CCK/OFDM/XR */
-		u_int16_t	rateKbps;	/* transfer rate in kbs */
-		u_int8_t	rateCode;	/* rate for h/w descriptors */
-		u_int8_t	shortPreamble;	/* mask for enabling short
-						 * preamble in CCK rate code */
-		u_int8_t	dot11Rate;	/* value for supported rates
-						 * info element of MLME */
-		u_int8_t	controlRate;	/* index of next lower basic
-						 * rate; used for dur. calcs */
-		u_int16_t	lpAckDuration;	/* long preamble ACK duration */
-		u_int16_t	spAckDuration;	/* short preamble ACK duration*/
-	} info[32];
-} HAL_RATE_TABLE;
-
-typedef struct {
-	u_int		rs_count;		/* number of valid entries */
-	u_int8_t	rs_rates[32];		/* rates */
-} HAL_RATE_SET;
-
-/*
- * Antenna switch control.  By default antenna selection
- * enables multiple (2) antenna use.  To force use of the
- * A or B antenna only specify a fixed setting.  Fixing
- * the antenna will also disable any diversity support.
- */
-typedef enum {
-	HAL_ANT_VARIABLE = 0,			/* variable by programming */
-	HAL_ANT_FIXED_A	 = 1,			/* fixed antenna A */
-	HAL_ANT_FIXED_B	 = 2,			/* fixed antenna B */
-} HAL_ANT_SETTING;
-
-typedef enum {
-	HAL_M_STA	= 1,			/* infrastructure station */
-	HAL_M_IBSS	= 0,			/* IBSS (adhoc) station */
-	HAL_M_HOSTAP	= 6,			/* Software Access Point */
-	HAL_M_MONITOR	= 8			/* Monitor mode */
-} HAL_OPMODE;
-
-typedef struct {
-	u_int8_t	kv_type;		/* one of HAL_CIPHER */
-	u_int8_t	kv_pad;
-	u_int16_t	kv_len;			/* length in bits */
-	u_int8_t	kv_val[16];		/* enough for 128-bit keys */
-	u_int8_t	kv_mic[8];		/* TKIP MIC key */
-	u_int8_t	kv_txmic[8];		/* TKIP TX MIC key (optional) */
-} HAL_KEYVAL;
-
-typedef enum {
-	HAL_CIPHER_WEP		= 0,
-	HAL_CIPHER_AES_OCB	= 1,
-	HAL_CIPHER_AES_CCM	= 2,
-	HAL_CIPHER_CKIP		= 3,
-	HAL_CIPHER_TKIP		= 4,
-	HAL_CIPHER_CLR		= 5,		/* no encryption */
-
-	HAL_CIPHER_MIC		= 127		/* TKIP-MIC, not a cipher */
-} HAL_CIPHER;
-
-enum {
-	HAL_SLOT_TIME_6	 = 6,			/* NB: for turbo mode */
-	HAL_SLOT_TIME_9	 = 9,
-	HAL_SLOT_TIME_20 = 20,
-};
-
-/*
- * Per-station beacon timer state.  Note that the specified
- * beacon interval (given in TU's) can also include flags
- * to force a TSF reset and to enable the beacon xmit logic.
- * If bs_cfpmaxduration is non-zero the hardware is setup to
- * coexist with a PCF-capable AP.
- */
-typedef struct {
-	u_int32_t	bs_nexttbtt;		/* next beacon in TU */
-	u_int32_t	bs_nextdtim;		/* next DTIM in TU */
-	u_int32_t	bs_intval;		/* beacon interval+flags */
-#define	HAL_BEACON_PERIOD	0x0000ffff	/* beacon interval period */
-#define	HAL_BEACON_ENA		0x00800000	/* beacon xmit enable */
-#define	HAL_BEACON_RESET_TSF	0x01000000	/* clear TSF */
-	u_int32_t	bs_dtimperiod;
-	u_int16_t	bs_cfpperiod;		/* CFP period in TU */
-	u_int16_t	bs_cfpmaxduration;	/* max CFP duration in TU */
-	u_int32_t	bs_cfpnext;		/* next CFP in TU */
-	u_int16_t	bs_timoffset;		/* byte offset to TIM bitmap */
-	u_int16_t	bs_bmissthreshold;	/* beacon miss threshold */
-	u_int32_t	bs_sleepduration;	/* max sleep duration */
-} HAL_BEACON_STATE;
-
-/*
- * Like HAL_BEACON_STATE but for non-station mode setup.
- * NB: see above flag definitions 
- */
-typedef struct {
-	u_int32_t	bt_intval;		/* beacon interval+flags */
-	u_int32_t	bt_nexttbtt;		/* next beacon in TU */
-	u_int32_t	bt_nextatim;		/* next ATIM in TU */
-	u_int32_t	bt_nextdba;		/* next DBA in 1/8th TU */
-	u_int32_t	bt_nextswba;		/* next SWBA in 1/8th TU */
-} HAL_BEACON_TIMERS;
-
-/*
- * Per-node statistics maintained by the driver for use in
- * optimizing signal quality and other operational aspects.
- */
-typedef struct {
-	u_int32_t	ns_avgbrssi;	/* average beacon rssi */
-	u_int32_t	ns_avgrssi;	/* average data rssi */
-	u_int32_t	ns_avgtxrssi;	/* average tx rssi */
-} HAL_NODE_STATS;
-
-#define	HAL_RSSI_EP_MULTIPLIER	(1<<7)	/* pow2 to optimize out * and / */
-
-struct ath_desc;
-struct ath_tx_status;
-struct ath_rx_status;
-
-/*
- * Hardware Access Layer (HAL) API.
- *
- * Clients of the HAL call ath_hal_attach to obtain a reference to an
- * ath_hal structure for use with the device.  Hardware-related operations
- * that follow must call back into the HAL through interface, supplying
- * the reference as the first parameter.  Note that before using the
- * reference returned by ath_hal_attach the caller should verify the
- * ABI version number.
- */
-struct ath_hal {
-	u_int32_t	ah_magic;	/* consistency check magic number */
-	u_int32_t	ah_abi;		/* HAL ABI version */
-#define	HAL_ABI_VERSION	0x06102600	/* YYMMDDnn */
-	u_int16_t	ah_devid;	/* PCI device ID */
-	u_int16_t	ah_subvendorid;	/* PCI subvendor ID */
-	HAL_SOFTC	ah_sc;		/* back pointer to driver/os state */
-	HAL_BUS_TAG	ah_st;		/* params for register r+w */
-	HAL_BUS_HANDLE	ah_sh;
-	HAL_CTRY_CODE	ah_countryCode;
-
-	u_int32_t	ah_macVersion;	/* MAC version id */
-	u_int16_t	ah_macRev;	/* MAC revision */
-	u_int16_t	ah_phyRev;	/* PHY revision */
-	/* NB: when only one radio is present the rev is in 5Ghz */
-	u_int16_t	ah_analog5GhzRev;/* 5GHz radio revision */
-	u_int16_t	ah_analog2GhzRev;/* 2GHz radio revision */
-
-	const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
-				u_int mode);
-	void	  __ahdecl(*ah_detach)(struct ath_hal*);
-
-	/* Reset functions */
-	HAL_BOOL  __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
-				HAL_CHANNEL *, HAL_BOOL bChannelChange,
-				HAL_STATUS *status);
-	HAL_BOOL  __ahdecl(*ah_phyDisable)(struct ath_hal *);
-	HAL_BOOL  __ahdecl(*ah_disable)(struct ath_hal *);
-	void	  __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
-	HAL_BOOL  __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, HAL_BOOL *);
-	HAL_BOOL  __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, u_int32_t);
-
-	/* DFS support */
-	HAL_BOOL  __ahdecl(*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *);
-
-	/* Transmit functions */
-	HAL_BOOL  __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
-				HAL_BOOL incTrigLevel);
-	int	  __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
-				const HAL_TXQ_INFO *qInfo);
-	HAL_BOOL  __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 
-				const HAL_TXQ_INFO *qInfo);
-	HAL_BOOL  __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 
-				HAL_TXQ_INFO *qInfo);
-	HAL_BOOL  __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
-	HAL_BOOL  __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
-	u_int32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
-	HAL_BOOL  __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, u_int32_t txdp);
-	u_int32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
-	HAL_BOOL  __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
-	HAL_BOOL  __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
-	HAL_BOOL  __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
-				u_int pktLen, u_int hdrLen,
-				HAL_PKT_TYPE type, u_int txPower,
-				u_int txRate0, u_int txTries0,
-				u_int keyIx, u_int antMode, u_int flags,
-				u_int rtsctsRate, u_int rtsctsDuration,
-				u_int compicvLen, u_int compivLen,
-				u_int comp);
-	HAL_BOOL  __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
-				u_int txRate1, u_int txTries1,
-				u_int txRate2, u_int txTries2,
-				u_int txRate3, u_int txTries3);
-	HAL_BOOL  __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
-				u_int segLen, HAL_BOOL firstSeg,
-				HAL_BOOL lastSeg, const struct ath_desc *);
-	HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
-				struct ath_desc *, struct ath_tx_status *);
-	void	   __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, u_int32_t *);
-	void	   __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
-
-	/* Receive Functions */
-	u_int32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
-	void	  __ahdecl(*ah_setRxDP)(struct ath_hal*, u_int32_t rxdp);
-	void	  __ahdecl(*ah_enableReceive)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
-	void	  __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
-	void	  __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
-	void	  __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
-				u_int32_t filter0, u_int32_t filter1);
-	HAL_BOOL  __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
-				u_int32_t index);
-	HAL_BOOL  __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
-				u_int32_t index);
-	u_int32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
-	void	  __ahdecl(*ah_setRxFilter)(struct ath_hal*, u_int32_t);
-	HAL_BOOL  __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
-				u_int32_t size, u_int flags);
-	HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
-				struct ath_desc *, u_int32_t phyAddr,
-				struct ath_desc *next, u_int64_t tsf,
-				struct ath_rx_status *);
-	void	  __ahdecl(*ah_rxMonitor)(struct ath_hal *,
-				const HAL_NODE_STATS *, HAL_CHANNEL *);
-	void	  __ahdecl(*ah_procMibEvent)(struct ath_hal *,
-				const HAL_NODE_STATS *);
-
-	/* Misc Functions */
-	HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
-				HAL_CAPABILITY_TYPE, u_int32_t capability,
-				u_int32_t *result);
-	HAL_BOOL   __ahdecl(*ah_setCapability)(struct ath_hal *,
-				HAL_CAPABILITY_TYPE, u_int32_t capability,
-				u_int32_t setting, HAL_STATUS *);
-	HAL_BOOL   __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
-				const void *args, u_int32_t argsize,
-				void **result, u_int32_t *resultsize);
-	void	  __ahdecl(*ah_getMacAddress)(struct ath_hal *, u_int8_t *);
-	HAL_BOOL  __ahdecl(*ah_setMacAddress)(struct ath_hal *, const u_int8_t*);
-	void	  __ahdecl(*ah_getBssIdMask)(struct ath_hal *, u_int8_t *);
-	HAL_BOOL  __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const u_int8_t*);
-	HAL_BOOL  __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
-				u_int16_t, HAL_STATUS *);
-	void	  __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
-	void	  __ahdecl(*ah_writeAssocid)(struct ath_hal*,
-				const u_int8_t *bssid, u_int16_t assocId);
-	HAL_BOOL  __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, u_int32_t gpio);
-	HAL_BOOL  __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, u_int32_t gpio);
-	u_int32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, u_int32_t gpio);
-	HAL_BOOL  __ahdecl(*ah_gpioSet)(struct ath_hal *,
-				u_int32_t gpio, u_int32_t val);
-	void	  __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t);
-	u_int32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
-	u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
-	void	  __ahdecl(*ah_resetTsf)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
-	void	  __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
-				HAL_MIB_STATS*);
-	HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
-	u_int	  __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
-	void	  __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
-	HAL_ANT_SETTING	 __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
-				HAL_ANT_SETTING);
-	HAL_BOOL  __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
-	u_int	  __ahdecl(*ah_getSlotTime)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
-	u_int	  __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
-	u_int	  __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
-	u_int	  __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_setDecompMask)(struct ath_hal*, u_int16_t, int);
-	void	  __ahdecl(*ah_setCoverageClass)(struct ath_hal*, u_int8_t, int);
-
-	/* Key Cache Functions */
-	u_int32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, u_int16_t);
-	HAL_BOOL  __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
-				u_int16_t);
-	HAL_BOOL  __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
-				u_int16_t, const HAL_KEYVAL *,
-				const u_int8_t *, int);
-	HAL_BOOL  __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
-				u_int16_t, const u_int8_t *);
-
-	/* Power Management Functions */
-	HAL_BOOL  __ahdecl(*ah_setPowerMode)(struct ath_hal*,
-				HAL_POWER_MODE mode, int setChip);
-	HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
-	int16_t   __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
-
-
-	/* Beacon Management Functions */
-	void	  __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
-				const HAL_BEACON_TIMERS *);
-	/* NB: deprecated, use ah_setBeaconTimers instead */
-	void	  __ahdecl(*ah_beaconInit)(struct ath_hal *,
-				u_int32_t nexttbtt, u_int32_t intval);
-	void	  __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
-				const HAL_BEACON_STATE *);
-	void	  __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
-
-	/* Interrupt functions */
-	HAL_BOOL  __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
-	HAL_BOOL  __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
-	HAL_INT	  __ahdecl(*ah_getInterrupts)(struct ath_hal*);
-	HAL_INT	  __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
-};
-
-/* 
- * Check the PCI vendor ID and device ID against Atheros' values
- * and return a printable description for any Atheros hardware.
- * AH_NULL is returned if the ID's do not describe Atheros hardware.
- */
-extern	const char *__ahdecl ath_hal_probe(u_int16_t vendorid, u_int16_t devid);
-
-/*
- * Attach the HAL for use with the specified device.  The device is
- * defined by the PCI device ID.  The caller provides an opaque pointer
- * to an upper-layer data structure (HAL_SOFTC) that is stored in the
- * HAL state block for later use.  Hardware register accesses are done
- * using the specified bus tag and handle.  On successful return a
- * reference to a state block is returned that must be supplied in all
- * subsequent HAL calls.  Storage associated with this reference is
- * dynamically allocated and must be freed by calling the ah_detach
- * method when the client is done.  If the attach operation fails a
- * null (AH_NULL) reference will be returned and a status code will
- * be returned if the status parameter is non-zero.
- */
-extern	struct ath_hal * __ahdecl ath_hal_attach(u_int16_t devid, HAL_SOFTC,
-		HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);
-
-/*
- * Set the Vendor ID for Vendor SKU's which can modify the
- * channel properties returned by ath_hal_init_channels.
- * Return AH_TRUE if set succeeds
- */
-
-extern  HAL_BOOL __ahdecl ath_hal_setvendor(struct ath_hal *, u_int32_t );
-
-/*
- * Return a list of channels available for use with the hardware.
- * The list is based on what the hardware is capable of, the specified
- * country code, the modeSelect mask, and whether or not outdoor
- * channels are to be permitted.
- *
- * The channel list is returned in the supplied array.  maxchans
- * defines the maximum size of this array.  nchans contains the actual
- * number of channels returned.  If a problem occurred or there were
- * no channels that met the criteria then AH_FALSE is returned.
- */
-extern	HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *,
-		HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
-		u_int8_t *regclassids, u_int maxregids, u_int *nregids,
-		HAL_CTRY_CODE cc, u_int16_t modeSelect,
-		HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
-
-/*
- * Calibrate noise floor data following a channel scan or similar.
- * This must be called prior retrieving noise floor data.
- */
-extern	void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
-
-/*
- * Return bit mask of wireless modes supported by the hardware.
- */
-extern	u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
-
-/*
- * Return rate table for specified mode (11a, 11b, 11g, etc).
- */
-extern	const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *,
-		u_int mode);
-
-/*
- * Calculate the transmit duration of a frame.
- */
-extern u_int16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
-		const HAL_RATE_TABLE *rates, u_int32_t frameLen,
-		u_int16_t rateix, HAL_BOOL shortPreamble);
-
-/*
- * Return if device is public safety.
- */
-extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *);
-
-/*
- * Convert between IEEE channel number and channel frequency
- * using the specified channel flags; e.g. CHANNEL_2GHZ.
- */
-extern	int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags);
-
-/*
- * Return a version string for the HAL release.
- */
-extern	char ath_hal_version[];
-/*
- * Return a NULL-terminated array of build/configuration options.
- */
-extern	const char* ath_hal_buildopts[];
-#endif /* _ATH_AH_H_ */
diff --git a/sys/contrib/dev/ath/ah_desc.h b/sys/contrib/dev/ath/ah_desc.h
deleted file mode 100644
index 36e097c..0000000
--- a/sys/contrib/dev/ath/ah_desc.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*-
- * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
- * Communications, Inc.  All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. The materials contained herein are unmodified and are used
- *    unmodified.
- * 2. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following NO
- *    ''WARRANTY'' disclaimer below (''Disclaimer''), without
- *    modification.
- * 3. Redistributions in binary form must reproduce at minimum a
- *    disclaimer similar to the Disclaimer below and any redistribution
- *    must be conditioned upon including a substantially similar
- *    Disclaimer requirement for further binary redistribution.
- * 4. Neither the names of the above-listed copyright holders nor the
- *    names of any contributors may be used to endorse or promote
- *    product derived from this software without specific prior written
- *    permission.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
- * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
- * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/sam_hal/ah_desc.h#5 $
- */
-
-#ifndef _DEV_ATH_DESC_H
-#define _DEV_ATH_DESC_H
-
-/*
- * Transmit descriptor status.  This structure is filled
- * in only after the tx descriptor process method finds a
- * ``done'' descriptor; at which point it returns something
- * other than HAL_EINPROGRESS.
- *
- * Note that ts_antenna may not be valid for all h/w.  It
- * should be used only if non-zero.
- */
-struct ath_tx_status {
-	u_int16_t	ts_seqnum;	/* h/w assigned sequence number */
-	u_int16_t	ts_tstamp;	/* h/w assigned timestamp */
-	u_int8_t	ts_status;	/* frame status, 0 => xmit ok */
-	u_int8_t	ts_rate;	/* h/w transmit rate index */
-#define	HAL_TXSTAT_ALTRATE	0x80	/* alternate xmit rate used */
-	int8_t		ts_rssi;	/* tx ack RSSI */
-	u_int8_t	ts_shortretry;	/* # short retries */
-	u_int8_t	ts_longretry;	/* # long retries */
-	u_int8_t	ts_virtcol;	/* virtual collision count */
-	u_int8_t	ts_antenna;	/* antenna information */
-	u_int8_t	ts_finaltsi;	/* final transmit series index */
-};
-
-#define	HAL_TXERR_XRETRY	0x01	/* excessive retries */
-#define	HAL_TXERR_FILT		0x02	/* blocked by tx filtering */
-#define	HAL_TXERR_FIFO		0x04	/* fifo underrun */
-
-/*
- * Receive descriptor status.  This structure is filled
- * in only after the rx descriptor process method finds a
- * ``done'' descriptor; at which point it returns something
- * other than HAL_EINPROGRESS.
- *
- * If rx_status is zero, then the frame was received ok;
- * otherwise the error information is indicated and rs_phyerr
- * contains a phy error code if HAL_RXERR_PHY is set.  In general
- * the frame contents is undefined when an error occurred thought
- * for some errors (e.g. a decryption error), it may be meaningful.
- *
- * Note that the receive timestamp is expanded using the TSF to
- * 15 bits (regardless of what the h/w provides directly).
- *
- * rx_rssi is in units of dbm above the noise floor.  This value
- * is measured during the preamble and PLCP; i.e. with the initial
- * 4us of detection.  The noise floor is typically a consistent
- * -96dBm absolute power in a 20MHz channel.
- */
-struct ath_rx_status {
-	u_int16_t	rs_datalen;	/* rx frame length */
-	u_int16_t	rs_tstamp;	/* h/w assigned timestamp */
-	u_int8_t	rs_status;	/* rx status, 0 => recv ok */
-	u_int8_t	rs_phyerr;	/* phy error code */
-	int8_t		rs_rssi;	/* rx frame RSSI */
-	u_int8_t	rs_keyix;	/* key cache index */
-	u_int8_t	rs_rate;	/* h/w receive rate index */
-	u_int8_t	rs_antenna;	/* antenna information */
-	u_int8_t	rs_more;	/* more descriptors follow */
-};
-
-#define	HAL_RXERR_CRC		0x01	/* CRC error on frame */
-#define	HAL_RXERR_PHY		0x02	/* PHY error, rs_phyerr is valid */
-#define	HAL_RXERR_FIFO		0x04	/* fifo overrun */
-#define	HAL_RXERR_DECRYPT	0x08	/* non-Michael decrypt error */
-#define	HAL_RXERR_MIC		0x10	/* Michael MIC decrypt error */
-
-enum {
-	HAL_PHYERR_UNDERRUN		= 0,	/* Transmit underrun */
-	HAL_PHYERR_TIMING		= 1,	/* Timing error */
-	HAL_PHYERR_PARITY		= 2,	/* Illegal parity */
-	HAL_PHYERR_RATE			= 3,	/* Illegal rate */
-	HAL_PHYERR_LENGTH		= 4,	/* Illegal length */
-	HAL_PHYERR_RADAR		= 5,	/* Radar detect */
-	HAL_PHYERR_SERVICE		= 6,	/* Illegal service */
-	HAL_PHYERR_TOR			= 7,	/* Transmit override receive */
-	/* NB: these are specific to the 5212 */
-	HAL_PHYERR_OFDM_TIMING		= 17,	/* */
-	HAL_PHYERR_OFDM_SIGNAL_PARITY	= 18,	/* */
-	HAL_PHYERR_OFDM_RATE_ILLEGAL	= 19,	/* */
-	HAL_PHYERR_OFDM_LENGTH_ILLEGAL	= 20,	/* */
-	HAL_PHYERR_OFDM_POWER_DROP	= 21,	/* */
-	HAL_PHYERR_OFDM_SERVICE		= 22,	/* */
-	HAL_PHYERR_OFDM_RESTART		= 23,	/* */
-	HAL_PHYERR_CCK_TIMING		= 25,	/* */
-	HAL_PHYERR_CCK_HEADER_CRC	= 26,	/* */
-	HAL_PHYERR_CCK_RATE_ILLEGAL	= 27,	/* */
-	HAL_PHYERR_CCK_SERVICE		= 30,	/* */
-	HAL_PHYERR_CCK_RESTART		= 31,	/* */
-};
-
-/* value found in rs_keyix to mark invalid entries */
-#define	HAL_RXKEYIX_INVALID	((u_int8_t) -1)
-/* value used to specify no encryption key for xmit */
-#define	HAL_TXKEYIX_INVALID	((u_int) -1)
-
-/* XXX rs_antenna definitions */
-
-/*
- * Definitions for the software frame/packet descriptors used by
- * the Atheros HAL.  This definition obscures hardware-specific
- * details from the driver.  Drivers are expected to fillin the
- * portions of a descriptor that are not opaque then use HAL calls
- * to complete the work.  Status for completed frames is returned
- * in a device-independent format.
- */
-struct ath_desc {
-	/*
-	 * The following definitions are passed directly
-	 * the hardware and managed by the HAL.  Drivers
-	 * should not touch those elements marked opaque.
-	 */
-	u_int32_t	ds_link;	/* phys address of next descriptor */
-	u_int32_t	ds_data;	/* phys address of data buffer */
-	u_int32_t	ds_ctl0;	/* opaque DMA control 0 */
-	u_int32_t	ds_ctl1;	/* opaque DMA control 1 */
-	u_int32_t	ds_hw[4];	/* opaque h/w region */
-};
-
-struct ath_desc_status {
-	union {
-		struct ath_tx_status tx;/* xmit status */
-		struct ath_rx_status rx;/* recv status */
-	} ds_us;
-};
-
-#define	ds_txstat	ds_us.tx
-#define	ds_rxstat	ds_us.rx
-
-/* flags passed to tx descriptor setup methods */
-#define	HAL_TXDESC_CLRDMASK	0x0001	/* clear destination filter mask */
-#define	HAL_TXDESC_NOACK	0x0002	/* don't wait for ACK */
-#define	HAL_TXDESC_RTSENA	0x0004	/* enable RTS */
-#define	HAL_TXDESC_CTSENA	0x0008	/* enable CTS */
-#define	HAL_TXDESC_INTREQ	0x0010	/* enable per-descriptor interrupt */
-#define	HAL_TXDESC_VEOL		0x0020	/* mark virtual EOL */
-/* NB: this only affects frame, not any RTS/CTS */
-#define	HAL_TXDESC_DURENA	0x0040	/* enable h/w write of duration field */
-
-/* flags passed to rx descriptor setup methods */
-#define	HAL_RXDESC_INTREQ	0x0020	/* enable per-descriptor interrupt */
-#endif /* _DEV_ATH_DESC_H */
diff --git a/sys/contrib/dev/ath/ah_devid.h b/sys/contrib/dev/ath/ah_devid.h
deleted file mode 100644
index c4bd28c..0000000
--- a/sys/contrib/dev/ath/ah_devid.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*-
- * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
- * Communications, Inc.  All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. The materials contained herein are unmodified and are used
- *    unmodified.
- * 2. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following NO
- *    ''WARRANTY'' disclaimer below (''Disclaimer''), without
- *    modification.
- * 3. Redistributions in binary form must reproduce at minimum a
- *    disclaimer similar to the Disclaimer below and any redistribution
- *    must be conditioned upon including a substantially similar
- *    Disclaimer requirement for further binary redistribution.
- * 4. Neither the names of the above-listed copyright holders nor the
- *    names of any contributors may be used to endorse or promote
- *    product derived from this software without specific prior written
- *    permission.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
- * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
- * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/sam_hal/ah_devid.h#2 $
- */
-
-#ifndef _DEV_ATH_DEVID_H_
-#define _DEV_ATH_DEVID_H_
-
-#define ATHEROS_VENDOR_ID	0x168c		/* Atheros PCI vendor ID */
-/*
- * NB: all Atheros-based devices should have a PCI vendor ID
- *     of 0x168c, but some vendors, in their infinite wisdom
- *     do not follow this so we must handle them specially.
- */
-#define	ATHEROS_3COM_VENDOR_ID	0xa727		/* 3Com 3CRPAG175 vendor ID */
-#define	ATHEROS_3COM2_VENDOR_ID	0x10b7		/* 3Com 3CRDAG675 vendor ID */
-
-/* AR5210 (for reference) */
-#define AR5210_DEFAULT          0x1107          /* No eeprom HW default */
-#define AR5210_PROD             0x0007          /* Final device ID */
-#define AR5210_AP               0x0207          /* Early AP11s */
-
-/* AR5211 */
-#define AR5211_DEFAULT          0x1112          /* No eeprom HW default */
-#define AR5311_DEVID            0x0011          /* Final ar5311 devid */
-#define AR5211_DEVID            0x0012          /* Final ar5211 devid */
-#define AR5211_LEGACY           0xff12          /* Original emulation board */
-#define AR5211_FPGA11B          0xf11b          /* 11b emulation board */
-
-/* AR5212 */
-#define AR5212_DEFAULT          0x1113          /* No eeprom HW default */
-#define AR5212_DEVID            0x0013          /* Final ar5212 devid */
-#define AR5212_FPGA             0xf013          /* Emulation board */
-#define	AR5212_DEVID_IBM	0x1014          /* IBM minipci ID */
-#define AR5212_AR5312_REV2      0x0052          /* AR5312 WMAC (AP31) */
-#define AR5212_AR5312_REV7      0x0057          /* AR5312 WMAC (AP30-040) */
-#define AR5212_AR2313_REV8      0x0058          /* AR2313 WMAC (AP43-030) */
-#define AR5212_AR2315_REV6      0x0086          /* AR2315 WMAC (AP51-Light) */
-#define AR5212_AR2315_REV7      0x0087          /* AR2315 WMAC (AP51-Full) */
-#define AR5212_AR2317_REV1      0x0091          /* AR2317 WMAC (AP61) */
-
-/* AR5212 compatible devid's also attach to 5212 */
-#define	AR5212_DEVID_0014	0x0014
-#define	AR5212_DEVID_0015	0x0015
-#define	AR5212_DEVID_0016	0x0016
-#define	AR5212_DEVID_0017	0x0017
-#define	AR5212_DEVID_0018	0x0018
-#define	AR5212_DEVID_0019	0x0019
-#define AR5212_AR2413      	0x001a          /* AR2413 aka Griffin-lite */
-#define AR5212_AR5413		0x001b          /* Eagle */
-#define AR5212_AR5424		0x001c          /* Condor (PCI express) */
-#define AR5212_DEVID_FF19	0xff19          /* XXX PCI express */
-
-/* AR5213 */
-#define	AR5213_SREV_1_0		0x0055
-#define	AR5213_SREV_REG		0x4020
-
-/* AR5416  */
-#define AR5416_DEVID_EMU_PCI	0xff1d		/* PCI Owl Emulation*/
-#define AR5416_DEVID_EMU_PCIE	0xff1c		/* PCIe Owl Emulation*/
-#define AR5416_DEVID		0x0023          /* PCI (MB/CB) */
-#define AR5418_DEVID		0x0024          /* PCI Express (XB) */
-
-#define	AR_SUBVENDOR_ID_NOG	0x0e11		/* No 11G subvendor ID */
-#define AR_SUBVENDOR_ID_NEW_A	0x7065		/* Update device to new RD */
-#endif /* _DEV_ATH_DEVID_H */
diff --git a/sys/contrib/dev/ath/ah_soc.h b/sys/contrib/dev/ath/ah_soc.h
deleted file mode 100644
index 0852bd3..0000000
--- a/sys/contrib/dev/ath/ah_soc.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*-
- * Copyright (c) 2006 Sam Leffler, Errno Consulting, Atheros
- * Communications, Inc.  All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. The materials contained herein are unmodified and are used
- *    unmodified.
- * 2. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following NO
- *    ''WARRANTY'' disclaimer below (''Disclaimer''), without
- *    modification.
- * 3. Redistributions in binary form must reproduce at minimum a
- *    disclaimer similar to the Disclaimer below and any redistribution
- *    must be conditioned upon including a substantially similar
- *    Disclaimer requirement for further binary redistribution.
- * 4. Neither the names of the above-listed copyright holders nor the
- *    names of any contributors may be used to endorse or promote
- *    product derived from this software without specific prior written
- *    permission.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
- * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
- * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/sam_hal/ah_soc.h#3 $
- */
-#ifndef _ATH_AH_SOC_H_
-#define _ATH_AH_SOC_H_
-/*
- * Atheros System on Chip (SoC) public definitions.
- */
-
-/*
- * This is board-specific data that is stored in a "known"
- * location in flash.  To find the start of this data search
- * back from the (aliased) end of flash by 0x1000 bytes at a
- * time until you find the string "5311", which marks the
- * start of Board Configuration.  Typically one gives up if
- * more than 500KB is searched.
- */
-struct ar531x_boarddata {
-	u_int32_t magic;             /* board data is valid */
-#define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
-	u_int16_t cksum;             /* checksum (starting with BD_REV 2) */
-	u_int16_t rev;               /* revision of this struct */
-#define BD_REV  4
-	char   boardName[64];        /* Name of board */
-	u_int16_t major;             /* Board major number */
-	u_int16_t minor;             /* Board minor number */
-	u_int32_t config;            /* Board configuration */
-#define BD_ENET0        0x00000001   /* ENET0 is stuffed */
-#define BD_ENET1        0x00000002   /* ENET1 is stuffed */
-#define BD_UART1        0x00000004   /* UART1 is stuffed */
-#define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
-#define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
-#define BD_SYSLED       0x00000020   /* System LED stuffed */
-#define BD_EXTUARTCLK   0x00000040   /* External UART clock */
-#define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
-#define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
-#define BD_WLAN0        0x00000200   /* Enable WLAN0 */
-#define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
-#define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
-#define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
-#define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
-#define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
-#define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
-#define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
-#define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
-	u_int16_t resetConfigGpio;   /* Reset factory GPIO pin */
-	u_int16_t sysLedGpio;        /* System LED GPIO pin */
-	
-	u_int32_t cpuFreq;           /* CPU core frequency in Hz */
-	u_int32_t sysFreq;           /* System frequency in Hz */
-	u_int32_t cntFreq;           /* Calculated C0_COUNT frequency */
-	
-	u_int8_t  wlan0Mac[6];
-	u_int8_t  enet0Mac[6];
-	u_int8_t  enet1Mac[6];
-	
-	u_int16_t pciId;             /* Pseudo PCIID for common code */
-	u_int16_t memCap;            /* cap bank1 in MB */
-	
-	/* version 3 */
-	u_int8_t  wlan1Mac[6];       /* (ar5212) */
-};
-
-/*
- * Board support data.  The driver is required to locate
- * and fill-in this information before passing a reference to
- * this structure as the HAL_BUS_TAG parameter supplied to
- * ath_hal_attach.
- */
-struct ar531x_config {
-	const struct ar531x_boarddata *board;	/* board config data */
-	const char	*radio;			/* radio config data */
-	int		unit;			/* unit number [0, 1] */
-	void		*tag;			/* bus space tag */
-};
-#endif	/* _ATH_AH_SOC_H_ */
diff --git a/sys/contrib/dev/ath/public/amd64-elf.hal.o.uu b/sys/contrib/dev/ath/public/amd64-elf.hal.o.uu
deleted file mode 100644
index 597aa76..0000000
--- a/sys/contrib/dev/ath/public/amd64-elf.hal.o.uu
+++ /dev/null
@@ -1,5533 +0,0 @@
-/*-
- * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
- * Communications, Inc.  All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. The materials contained herein are unmodified and are used
- *    unmodified.
- * 2. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following NO
- *    ''WARRANTY'' disclaimer below (''Disclaimer''), without
- *    modification.
- * 3. Redistributions in binary form must reproduce at minimum a
- *    disclaimer similar to the Disclaimer below and any redistribution
- *    must be conditioned upon including a substantially similar
- *    Disclaimer requirement for further binary redistribution.
- * 4. Neither the names of the above-listed copyright holders nor the
- *    names of any contributors may be used to endorse or promote
- *    product derived from this software without specific prior written
- *    permission.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
- * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
- * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/sam_hal/public/x86_64-elf.hal.o.uu#6 $
- */
-#define	ATH_HAL_VERSION	"0.9.20.3"
-begin 644 hal.o
-M?T5,1@(!`0````````````$`/@`!`````````````````````````,C>`@``
-M`````````$```````$``$``-``^WQTC'P@````"#^%@/A/\```"#^%A_5X/X
-M&W\J@_@:#XW>````@_@2?Q>#^!$/C;4```"#^`</A*,```#IRP```(/X$^M@
-M@_A2#X2B````@_A2?PQ(Q\(`````@_@<ZWN#^%</A(@```#IG@```#T'$0``
-M=&H]!Q$``'\N2,?"`````#V1````#X2#````/9$```!_#"V&````@_@!=VWK
-M63T4$```=%OK8CT3$0``=%(]$Q$``'\)/1(1``!T*>M+2,?"`````#T3\```
-M=$)(Q\(`````/1OQ``!T-.LM2,?"`````.LI2,?"`````.L@2,?"`````.L7
-M2,?"`````.L.2,?"`````.L%N@````!(B=##2(/L"(GQ9H'_C!9T$V:!_R>G
-M=`RX`````&:!_[<0=0@/M_GHPO[__TB#Q`C#2(/L"`^WQST'`@``#X2*````
-M/0<"``!_((/X$G\,@_@1?6^#^`=T=.M_@_@3=%F#Z!J#^`)W<NM*/1,1``!T
-M2#T3$0``?QX]!Q$``'1./0<1``!_!ST4$```ZR4]$A$``'0OZT0]&_$``'0F
-M/1OQ``!_"3T3\```=`[K+3T9_P``=2:_$P````^W_^@`````ZQ(/M__H````
-M`.L(#[?_Z`````!(B<+K#+H`````0<<``0```$B%TG1+#[>">`,``&:)0@@/
-MMX)Z`P``9HE""HN"?`,``(E"+`^W@H`#``!FB4(P#[>"@@,``&:)0C(/MX*$
-M`P``9HE"-`^W@H8#``!FB4(V2(G02(/$",.)MX@#``"X`0```,-!5D%50515
-M4TF)_D&)U4&)S+L`````B?5)BT8@BT0%`$0AZ+H!````1#G@=!F_"@```.@`
-M````_\.!^^<#``!^U[H`````B=!;74%<05U!7L.Y`````+@`````.?!S$HT4
-M`(GX@^`!"=#1[__!.?%R[L-!B=(/M\%(C01`1`^W3(8FN`````!%A<D/A+8!
-M```/M\%(C01`#[9$AB6#^`)T88/X`G\)A<!T'.F/`0``@_@##X05`0``@_@$
-M#X0]`0``Z7@!``"_P````$6%P'03#[?!2(T$0(!\ABD`=`6_8````$*-!-4`
-M````:<#H`P``N@````!!]_&-1#@*Z4$!``!(@[_H$P````^$C````$B+A^@3
-M``!F@W@"`'DS1(G(P>`$B<!(:<#336(02,'H((G"P>H&0HU$TA6)T;H`````
-M]_'!X`0%D````.GR````2(._Z!,```!T04B+A^@3``#V0`-`=#1"C03-````
-M`(G`2&G`TTUB$$C!Z"")PL'J!D*-1-(5B=&Z`````/?QC03%2````.FG````
-M0HT$C0````")P$AIP---8A!(P>@@B<+!Z@9"C432%8G1N@````#W\8T$A20`
-M``#K=D*-!,T`````B<!(:<#336(02,'H((G"P>H&0HU$TA6)T;H`````]_&-
-M!(46````ZT5"C02-`````(G`2&G`TTUB$$C!Z"")PL'J!D*-1-(5B=&Z````
-M`/?QP>`"C9"]````@\!<08'YYP,```]&PNL%N``````/M\##]D8"('0'N@(`
-M``#K1`^W1@(ET````+H#````/<````!T+P^W1@(ET````+H$````/=````!T
-M&O9&`A!T![H!````ZPWV1@,(#Y7`#[;0C122B=##2(/L&$B)7"0(2(EL)!")
-M]8G3A-)Y'K@.````@?ZT"0``#X0.`0``@?ZS"0``=E3IT````/;&`70QZ```
-M``"%P'0+C86S[/__@_@P=G+WPT`!```/A,8```"!_8@3```/AI<```#IM0``
-M`+@.````@?ZT"0``#X2Z````@?ZS"0``=R"-E9GV__](8\)(:<!G9F9F2,'H
-M(-'XP?H?*=#ID@```('^AQ,``'=TZ`````"%P'1`C86S[/__@_@P=S6-1*T`
-MC10`B>BYS<S,S$@/K\%(P>@@P>@"C02`*<6-@@@___^#_0)U/8V"#3___T@/
-MK\'K.H'])!,``'8(C85@\/__ZR&-A3#V__^ZS<S,S$@/K\)(P>@@P>@$@\`/
-MZQ:-A7CL__^ZS<S,S$@/K\)(P>@@P>@"2(M<)`A(BVPD$$B#Q!C#4XGS2(NW
-MZ!,``$B%]G03Z`````")P`^V@``````/K\/K`VO#%EO#4XGS2(NWZ!,``$B%
-M]G0=Z`````")P`^VD`````")V(G6N@````#W]HG!ZQ2)V+JCBRZZ2`^OPDC!
-MZ"")P<'I!(G(6\-!5D%505154TF)_DB)]8!^!``/A9$```!!O`````!)8\3&
-M1"@$_T'_Q$&#_!]^[T&\`````$0[90!];DECW$B-'%M(C5R=(`^V0P@/MDL+
-M#[;01(AD*@0*0PD/ML!$B&0H!$0/MNE!N`````!$B>FZ#@```$B)[DR)]^@`
-M````9HE##$&X`0```$2)Z;H.````2(GN3(GWZ`````!FB4,.0?_$1#ME`'R2
-M6UU!7$%=05[#3(V'D`,``(/^(@^'+P$``(GP_R3%``````^WA[@#``#K$4'V
-M0`,!#Y3`#[;`PT$/MT`*B0&X`````,-!#[=`".OQ0?9``@+K%T'V0`(!N@``
-M``"X#0````]$PL-!]@`$N@````"X#0````]%PL-!]@`(Z^Q!]@`0Z^:+AZ@#
-M``#KL8/Z`70=N`````"#^@$/@J\```"#^@)T$X/Z`W0:Z8P````/OX>L`P``
-MZX8/MX>N`P``Z7K___^+A[`#``#I;____T'V0`($ZY5!]D`"".N.0?9``0'K
-MAT'V0`(@ZX!!]D`"0.EV____@_H!=!^#^@%R!X/Z`G0>ZS5!@'@"`+H`````
-MN`T````/2,+#@[\$%````.L3#[>'`!0``.D0____@[\@%`````^%!?___[@-
-M````PT&+0!3I]/[__[@,````PTR)P(/^&70E@_X9=P>#_@]T">M*@_X>=#WK
-M0X/Z`W4^@_D$=SF)C[`#``#K&H/Z`70'@_H"=!;K)87)#Y7`#[;`B8<$%```
-MN`$```##9HF/`!0``.OQB8\@%```Z^E(A<!T!L<`#````+@`````PU-(B=-)
-MB=%!NP````"#^0=V2TECPT0/MP2&1`^W5(8"1(G`P>`01`G008D!28/!!(/I
-M!$2)P$B+5R"+!!!!B0%)@\$$08/`!(/I!$4YT'<%@_D#=]Y!_\.#^0=WM42)
-MR"G86\-328G23(G+@_X-="J#_@U_!H7V=`[K=H/^'70L@_X>=#KK:DB-AW@#
-M``!)B0!!QP$0````ZU!!BPE)BQ!,B=;H6/___XD#ZSY(C8<(%```28D`0<<!
-M&````.LKA<EU%$''`00```!)BQ"+A[0#``")`NL3N`````"#^01U%4&+`HF'
-MM`,``+@!````ZP6X`````%O#2(G1@WX$`'4&N`````##BP*)!HM"!(E&"(M"
-M"(E&#(M"#(E&$(-Z$/]T%8M"$#T``0``NO\````/0\*)1A3K!\=&%`(```"#
-M>13_="V+412!^@$$``"X``0```]#T,=&&`$````Y5AAS%K@!`````<"#R`$Y
-MT'+WZP.+012)1AB#>1C_=#"+41B!^@$$``"X``0```]#T,=&'`$````Y5AQS
-M&K@!`````<"#R`$YT'+WB48<ZP?'1AS_`P``9H-Y'`!T%@^W01QF@_@0N@\`
-M```/0\)FB48@ZP9FQT8@"@!F@WD>`'06#[=!'F:#^!"Z#P````]#PF:)1B+K
-M!F;'1B(*`(M!((E&)(M!)(E&*(M!*(E&+(M!+(E&,(-Y!`1U#8-^!`%U!\=&
-M.`$```"X`0```,.#>@0`=0:X`````,.+0@R)1@B+`HD&BT((B48$BT(,B48(
-MBT(0B48,BT(4B480BT(8B484BT(<B488#[="(&:)1AP/MT(B9HE&'HM")(E&
-M((M"*(E&)(M"+(E&*(M",(E&++@!````PTB#[!A(B1PD2(EL)`A,B60D$$F)
-M_$B)\^@`````2(G%N`````!(A>UT-6:#?18`=25(B=Y,B>?H`````(G#2(GN
-M3(GG0?^4)&@#``!F`X0;`````.L(#[=%%F8#11B82(L<)$B+;"0(3(MD)!!(
-M@\08PT%7059!54%455-(@^P(28G]9L=$)`(``&;'1"0&``!FQP0D``!FQT0D
-M!```0;P`````1#NGX!,```^#MP```$ECQ$C!X`9*C:PHX`,``&:#?18`#XF-
-M````2(GN3(GOZ`````!!B<:)P$0/M[P```````^W719$`?M(B>Y,B>]!_Y5H
-M`P``C008]D4#`70G9CL$)'U19HD$)$B)[DR)[T'_E6@#``!F`T469D$IQV9$
-MB7PD!.LP9CM$)`)]*6:)1"0"1(GS2(GN3(GO0?^5:`,``&8#118/MY0;````
-M`&8IPF:)5"0&0?_$13NEX!,```^"2?___T&\`````$0/OW0D!`^_7"0&26/$
-M2,'@!DJ-K"C@`P``9H-]%@!Y'TB)[DR)[T'_E6@#``"8]D4#`70%1`'PZP(!
-MV&:)11A!_\1!@_P_?L)(@\0(6UU!7$%=05Y!7\.0D%.)T&:!/P$P=PE)Q\(`
-M````ZP=)Q\(`````OP````!$#[?`0;ED````#[?V2&/'00^W!$*)PD$/K]!$
-MB<LIPXG8#Z_&`<)(8\)(:<`?A>M12,'H(,'X!<'Z'RG09HD!2(/!`O_'@_\*
-M?L);PP^WUF:!_O\`=#=F@3\",'<A9H/^/G8,#[?&C02`9@4B%>L9#[?&C02`
-MC80`[!,``.L*#[?&C02`9@7`$@^WP(G"B=##B?`/M]9F@?[_`'069H$_`C!W
-M!F8%8`GK!&8%_`@/M\")PHG0PT%505154TB#[`A(B?M)B?1F@3[_/W829H-^
-M+@!T"V:#?A8`#X1C`@``9D&!/"0",'9S0;U0`0``O0````!F08.\)'8!````
-M#X0_`@``00^W]4'_Q4B-5"0&2(G?_Y,H`P``N@````"%P`^$(@(``$ACU68/
-MMD0D!V9!B8148@$``&8/MD0D!F9!B8149`$``(/%`D$/MX0D=@$``#G%?*WI
-MJ0$``$&]`0$``$B-5"0&O@`!``!(B=__DR@#``"Z`````(7`#X3&`0``#[=$
-M)`:)PF;!Z@EF08F4)&(!``!FP>@"@^!_9D&)A"1D`0``#[=$)`;!X`6#X']F
-M08F$)&8!``!!#[?U0?_%2(U4)`9(B=__DR@#``"Z`````(7`#X1L`0``#[=$
-M)`:)PF;!Z@MF00F4)&8!``!FP>@$@^!_9D&)A"1H`0``#[=$)`;!X`.#X']F
-M08F$)&H!``!!#[?U0?_%2(U4)`9(B=__DR@#``"Z`````(7`#X02`0``#[=$
-M)`:)PF;!Z@UF00F4)&H!``!FP>@&@^!_9D&)A"1L`0``#[=$)`8!P(/@?V9!
-MB80D;@$``$$/M_5!_\5(C50D!DB)W_^3*`,``+H`````A<`/A+D````/MU0D
-M!HG09L'H#V9!"80D;@$``(G09L'H"(/@?V9!B80D<`$``&;1ZH/B?V9!B90D
-M<@$```^W1"0&P>`&@^!_9D&)A"1T`0``00^W]4B-5"0&2(G?_Y,H`P``N@``
-M``"%P'15#[=$)`9FP>@*9D$)A"1T`0``O0````!F08.\)'8!````="U%#[>L
-M)'8!``!(8]U!#[>T7&(!``!,B>?H&_W__V9!B81<8@$``/_%1#GM?-RZ`0``
-M`(G02(/$"%M=05Q!7<-!5%532(G3#[=N%$F)]`^WQ4B-/(!(C3RX2(U$``-(
-MP>@"2`''2,'G`N@`````2(G"N`````!(A=(/A*````!(B1,/M\5(C40``R7\
-M_P<`2(T$$$B)0Q!FB6L(0;@`````9H7M='1$#[?-26/02(L[2(MS$$AKRE1!
-M#[<$5&:)!`YFB017N0````!(:_)42&/!2(T$@$B-!(9(B<)(`U,09HE*!$@#
-M0Q!FQT`&``#_P8/Y`W[926/`2(M3$$AKP%1FQT0"!@0`2(M3$&;'1`)"`P!!
-M_\!%.<A\D+@!````6UU!7,-(@^P(2(G7#[=&%F:)0@IFQT0D!*W>9L=$)`:M
-MWKH`````N0````!$#[='"DR-3"0$1(G`T_BH`708N`````"#^@$/CQ8"``!(
-M8\)F08D,0?_"_\&#^0-^V`^W1A1FB4<(9H7`=0JX`````.GN`0``0;D`````
-M9H-_"``/A-@!``!,C50D!$ECT4AKPAI(C00P3(U`&$B+3Q!(:])4#[=`&&:)
-M!!%(BT\000^W0!)FB401`KD`````2&/!2(T$@$B-!()(`T<09L=`!@``_\&#
-M^0-^Y&9!@7H"K=YU<$ECT4AKTE1(#[=$)`1(C02`2(T$@D@#1Q!(C5`$9L="
-M`@0`00^W0`)FB4($9D$#0`9FB4(&9D$#0`IFB4((9D$#0`YFB4(*00^W0`1F
-MB4(,00^W0`AFB4(.00^W0`QFB4(000^W0!!FB4(2Z?P```!)8\E(:\E42`^W
-M1"0$2(T$@$B-!(%(`T<000^W4`)FB5`(20^W0@)(C02`2(T$@4@#1Q!FQT`(
-M%`!)#[="`DB-!(!(C02!2`-'$&;'0`HC`$D/MT("2(T$@$B-!(%(`T<09L=`
-M##\`2`^W1"0$2(T$@$B-%(%(`U<02(/"!&;'0@($``^W0@1F00-`!F:)0@9F
-M00-`"F:)0@AF00-`#F:)0@I!#[=`!&:)0@Q!#[=`"&:)0@Y!#[=`#&:)0A!!
-M#[=`$&:)0A))#[="`DB-!(!(C12!2`-7$$B#P@1FQT("`P!!#[=`%&:)0@Q!
-M#[=`%F:)0@Y!#[=`&&:)0A!!_\$/MT<(03G!#XPM_O__N`$```!(@\0(PT%7
-M059!54%455-(@>Q8`0``2(G]28GU0;Q0`0``0;\`````0;X`````08/_`0^$
-MK@```$&#_P%_"D6%_W04Z2`!``!!@_\"#X35````Z1$!``!F08-]%@`/A`0$
-M``!!@_X)#X\%`0``1(GF0?_$2(U4)`Y(B>__E2@#``"Z`````(7`#X3K`P``
-M@'PD#@`/A-D```!)8]X/MG0D#D'_QDR)[^@+^?__9HF$7#`!``!F#[9$)`^$
-MP`^$L````$ECW@^V\$'_QDR)[^CD^/__9HF$7#`!``!!@_X)?HSIC````&9!
-M@WT:``^$=0,``+L`````2&/#9D&!O$54`0``_P!T%TECUD$/MX1%5`$``&:)
-MA%0P`0``0?_&_\.#^P)^TNM+9D&#?1P`#X0T`P``NP````!(8\-F08&\14X!
-M``#_`'0726/600^WA$5.`0``9HF$5#`!``!!_\;_PX/[`G[2ZPJZ`````.D'
-M`P``OAP!``!(C7PD$.@`````9D2)="0DNP````!$.?,/C7T"``!(8\,/MY1$
-M,`$``&:)5$002&O`&F:)5`0H1(GF0?_$2(U4)`Y(B>__E2@#``"Z`````(7`
-M#X2J`@``2&/+2&O)&DB-A"10`0``2`'!#[=$)`X/MM!FP>@'@^`!P>`(9BG"
-M9HF1W/[__P^W1"0.B<)FP>H(9L'H#\'@"&8IPF:)D>#^__]$B>9!_\1(C50D
-M#DB)[_^5*`,``+H`````A<`/A#\"``!(8\M(:\D:2(V4)%`!``!(`=$/MT0D
-M#@^VT&;!Z`>#X`'!X`AF*<)FB9'D_O__#[=$)`Z)PF;!Z@AFP>@/P>`(9BG"
-M9HF1Z/[__T2)YD'_Q$B-5"0.2(GO_Y4H`P``N@````"%P`^$U`$``$ACTTAK
-MTAI(C80D4`$``$@!P@^W1"0.@^`?9HF"WO[__P^W1"0.9L'H!8/@'V:)@N+^
-M__\/MT0D#F;!Z`J#X!]FB8+F_O__1(GF0?_$2(U4)`Y(B>__E2@#``"Z````
-M`(7`#X1L`0``2&/+2&O)&DB-E"10`0``2`'1#[=$)`X/MM!FP>@'@^`!P>`(
-M9BG"9HF1[/[__P^W1"0.B<)FP>H(9L'H#\'@"&8IPF:)D>[^__]$B>9!_\1(
-MC50D#DB)[_^5*`,``+H`````A<`/A`$!``!(8\-(:\`:2(V4)%`!``!(C0P"
-M#[=$)`X/MM!FP>@'@^`!P>`(9BG"9HF1\/[__V9!@7T``D!V(`^W@>C^__]F
-MB8'J_O__9@^V1"0/@^`_9HF!VO[__^LW2&/#2&O`&DB-E"10`0``2`'0#[=4
-M)`Z)T6;!Z0AFP>H/P>((9BG19HF(ZO[__V;'@-K^__\!`/_#1#GS#XR#_?__
-M26/700^W1%5H9HE$)"9(C11228V4U6@-``!(C70D$$B)[^B%^/__N@````"%
-MP'0W26/72(T44DF-E-5H#0``2(UT)!!(B>_H1/G__[H`````A<!T$D'_QT&#
-M_P(/CK3[__^Z`0```(G02('$6`$``%M=05Q!74%>05_#55-(@^P(2(GUNP``
-M``!(8\-(C01`2(U$Q0!(B[AH#0``2(7_=!!(QX!H#0```````.@`````_\.#
-M^P)^T4B#Q`A;7<-)B=%!B?!FB7<4#[=7%KX`````]L(!N`$````/1?"-1@'V
-MP@(/1?"-1@'VP@0/1?"-1@'VP@@/1?"Y`````&9$.<%S(P^WP4$/MQ1!9HD4
-M1TAKP&9(`?AFB5`89HEP&O_!9D0YP7+=D,-!5T%6055!5%532(/L2$F)_4F)
-M]DB)5"00B4PD#$6)QT2(3"0+BVPD#$&\`````$6%P`^$K0````^W]?_%2(U4
-M)!Y,B>]!_Y4H`P``N@````"%P`^$M@4``(!\)!X`#X2!````@'PD"P!U%D$/
-MM]P/MG0D'D'_Q$R)]^C^\___ZQ1!#[?<#[9T)!Y!_\1,B??H+/3__V:)1%P@
-M9@^V1"0?A,!T08!\)`L`=11!#[?<#[;P0?_$3(GWZ,#S___K%$$/M]P/MG0D
-M'T'_Q$R)]^CN\___9HE$7"!!#[?$1#GX#X)3____2(U4)"!!#[?T2(M\)!#H
-MG_[__T2)^-'HBVPD#`'%0;P`````2(M$)!!F1#M@%`^#\00``$$/M\1(:\!F
-M2(M4)!!(C5P0&&:#>P(`#X31````#[?U_\5(C50D'DR)[T'_E2@#``"Z````
-M`(7`#X2X!```#[=$)!Z#X!]FB4,,#[=$)!YFP>@%@^!_9HE#!`^W1"0>9L'H
-M#&:)0SP/M_7_Q4B-5"0>3(GO0?^5*`,``+H`````A<`/A&X$```/MT0D'H/@
-M/V:)0Q0/MT0D'F;!Z`:#X`]FB4-$#[=$)!YFP>@*9HE#'`^W]?_%2(U4)!Y,
-MB>]!_Y4H`P``N@````"%P`^$)`0```^W1"0>@^`/9HE#3`^W1"0>9L'H!(/@
-M/V:)0R1F@WL"`0^&]0````^W1"0>9L'H"H/@'V:)0PX/MT0D'F;!Z`]FB4,&
-M#[?U_\5(C50D'DR)[T'_E2@#``"Z`````(7`#X2_`P``#[=$)!Z#X#\!P&8)
-M0P8/MT0D'F;!Z`:#X`]FB4,^#[=$)!YFP>@*9HE#%@^W]?_%2(U4)!Y,B>]!
-M_Y4H`P``N@````"%P`^$<P,```^W1"0>@^`/9HE#1@^W1"0>9L'H!(/@/V:)
-M0QX/MT0D'F;!Z`J#X`]FB4-.#[=$)!YFP>@.9HE#)@^W]?_%2(U4)!Y,B>]!
-M_Y4H`P``N@````"%P`^$&0,```^W1"0>@^`/P>`"9@E#)NM49H-[`@%U30^W
-M1"0>9L'H"H/@#V:)0U0/MT0D'F;!Z`YFB4,L#[?U_\5(C50D'DR)[T'_E2@#
-M``"Z`````(7`#X3#`@``#[=$)!Z#X`_!X`)F"4,L9H-[`@(/AL8````/MT0D
-M'F;!Z`2#X!]FB4,0#[=$)!YFP>@)9HE#"`^W]?_%2(U4)!Y,B>]!_Y4H`P``
-MN@````"%P`^$:P(```^W1"0>@^`/9HE#0`^W1"0>9L'H!(/@/V:)0Q@/MT0D
-M'F;!Z`J#X`]FB4-(#[=$)!YFP>@.9HE#(`^W]?_%2(U4)!Y,B>]!_Y4H`P``
-MN@````"%P`^$$0(```^W1"0>@^`/P>`"9@E#(`^W1"0>9L'H!(/@#V:)0U!F
-M#[9$)!^#X#]FB4,HZR1F@WL"`G4=#[=$)!YFP>@$@^`/9HE#5F8/MD0D'X/@
-M/V:)0RYF@WL"`P^&3`$```^W1"0>9L'H#F:)0Q(/M_7_Q4B-5"0>3(GO0?^5
-M*`,``+H`````A<`/A(8!```/MT0D'H/@!\'@`F8)0Q(/MT0D'F;!Z`.#X']F
-MB4,*#[=$)!YFP>@*@^`/9HE#0@^W1"0>9L'H#F:)0QH/M_7_Q4B-5"0>3(GO
-M0?^5*`,``+H`````A<`/A"D!```/MT0D'H/@#\'@`F8)0QH/MT0D'F;!Z`2#
-MX`]FB4-*9@^V1"0?@^`_9HE#(@^W1"0>9L'H#F:)0U(/M_7_Q4B-5"0>3(GO
-M0?^5*`,``+H`````A<`/A,\````/MT0D'H/@`\'@`F8)0U(/MT0D'F;!Z`*#
-MX#]FB4,J9@^V1"0?@^`/9HE#6@^W1"0>9L'H#&:)0S(/M_7_Q4B-5"0>3(GO
-M0?^5*`,``+H`````A<!T>0^W1"0>@^`#P>`$9@E#,NM09H-[`@-U20^W1"0>
-M9L'H#F:)0U@/M_7_Q4B-5"0>3(GO0?^5*`,``+H`````A<!T-P^W1"0>@^`#
-MP>`"9@E#6`^W1"0>9L'H`H/@/V:)0S!!_\1(BT0D$&9$.V`4#X(/^___N@$`
-M``")T$B#Q$A;74%<05U!7D%?PU-(B?,/MT849HE'%`^W5Q:^`````/;"`;@!
-M````#T7PC48!]L("#T7PC48!]L($#T7PC48!]L((#T7P0;L`````9D0[6Q0/
-M@XX```!$#[?200^WPP^W%$-FB11'2&O`9D@!^&:)4!AFB7`<0;D`````N0``
-M``!!#[?#3&O`9@^WP4B-!$!)C03`2(T4!V:)2AY$B=#3^*@!=!AFQT(@!`!!
-M_\%F08/Y`74:9L="(`4`ZQ(/M\%(C01`28T$P&;'1`<@``#_P6:#^0-VLD'_
-MPV9$.UL4#X)V____6\-!5T%6055!5%532(/L$$B)-"1(B=5FQT0D"*W>2(U$
-M)`AFQT`"K=YFQT`$K=YFQT`&K=Y!O0````"[``````^W<A:_`P```$F)P`^W
-MPXGY*<&)\-/XJ`%T$$2)ZHGX9BG89D&)!%!!_\7_PV:#^P-VV4B+%"0/MT(4
-M9HE%%$&^`````&9!.<8/@\D```!!#[?&2&O`9DB+%"1(`<),C4H8#[=2&&:)
-M5`48NP````"X`````$0YZ`^#C````$R-?"0(00^WQDQKX&8/M]-)#[<$5TB-
-M!$!)C03$2(U\!1Y!#[]$40S!X`)FB4<.00^W1%$$9HE'!$&X`0```&9$.T<"
-M<SQ)B=-$#[=7`D$/M\A)C32+00^_1'$T#[=43PR-!$)FB41/#@^W1$\"9D$#
-M1'$,9HE$3P1!_\!F13G0<LS_PP^WPT0YZ'*!0?_&9D0[=10/@C?___^X`0``
-M`$B#Q!!;74%<05U!7D%?PT%7059!54%455-(@^P(28G^2(GSQP0D!``&`,=$
-M)`0)``P`0;\`````OQ0$``#H`````$B)Q4B%P`^$H`$``$0/MZO0````9H-[
-M%@`/A((```"^%`0``$B)Q^@`````#[=#:&:)119!N0````!!N`H```!$B>E(
-MB>I(B=Y,B??H%O?__X7`#X1&`0``3(VC:`T```^W0VAF08E$)!9(B>Y,B>?H
-M$OW__TR)XDB)[DR)]^C@_?__A<`/A!0!``!(#[=%&@^W5$3^#[=%%`^OPD:-
-M;"@%9H-[&@`/A((```"^%`0``$B)[^@`````#[=#:F:)119!N0$```!!N`0`
-M``!$B>E(B>I(B=Y,B??HB?;__X7`#X2Y````3(VC?!$```^W0VIF08E$)!9(
-MB>Y,B>?HA?S__TR)XDB)[DR)]^A3_?__A<`/A(<```!(#[=%&@^W5$3^#[=%
-M%`^OPD:-;"@"9H-['`!T9+X4!```2(GOZ``````/MT-L9HE%%D&Y`@```$&X
-M!````$2)Z4B)ZDB)WDR)]^@`]O__A<!T-$R-HY`5```/MT-L9D&)1"062(GN
-M3(GGZ`#\__],B>)(B>Y,B??HSOS__X7`=`9!OP$```!(A>UT"$B)[^@`````
-M1(GX2(/$"%M=05Q!74%>05_#05=!5D%505154TB#[!A)B?Q)B?5F@3[_/W8.
-M9H-^+@%U!^A-\/__ZQQF08%]`/]/=AIF08-]+@)U$DR)[DR)Y^C*_?__B<+I
-MR@(``$&^`````&9!@7T``C!V![U0`0``ZP6]``$``$&#_@%T.$&#_@%_"D6%
-M]G0-Z8````!!@_X"=$[K>(/%!4$/MX5V`0``9HE$)!1)C9UX`0``28V58@$`
-M`.MB9D&#?1H`#X13`@``@\4W00^WA8`#``!FB40D%$F-G3X$``!)C96(`P``
-MZS9F08-]'``/A"<"``"#Q49!#[>%@`,``&:)1"0428V=H@,``$F-E8(#``#K
-M"KH`````Z0\"``!(B50D"$&_`````&:#?"04``^$Y@$``$ECQTB+5"0(#[<$
-M0F:)`XGN_\5(C50D%DR)YT'_E"0H`P``N@````"%P`^$R`$```^W1"069L'H
-M"F:)0P0/MT0D%F;!Z`2#X#]FB4,"#[=$)!;!X`*#X#]FB4,>B>[_Q4B-5"06
-M3(GG0?^4)"@#``"Z`````(7`#X1[`0``#[=$)!9FP>@.9@E#'F8/MD0D%X/@
-M/V:)0R`/MT0D%F;!Z`*#X#]FB4,B#[=$)!;!X`2#X#]FB4,DB>[_Q4B-5"06
-M3(GG0?^4)"@#``"Z`````(7`#X0A`0``#[=$)!9FP>@,9@E#)`^W1"069L'H
-M!H/@/V:)0R8/MT0D%H/@/V:)0RB)[O_%2(U4)!9,B>=!_Y0D*`,``+H`````
-MA<`/A-<````/MT0D%F;!Z`IFB4,J#[=$)!9FP>@$@^`_9HE#+`^W1"06P>`"
-M@^`_9HE#+HGN_\5(C50D%DR)YT'_E"0H`P``N@````"%P`^$B@````^W1"06
-M9L'H#F8)0RYF#[9$)!>#X#]FB4,P#[=$)!9FP>@"@^`_9HE#,DB-2P@/MU,$
-M#[=S`DR)[^CPYO__N0`````/MT,&B<8YP7T62&/1#[]$4QYKP#)FB413'O_!
-M.?%\ZDB#PS1!_\</MT0D%$$YQP^,&O[__T'_QD&#_@(/CD']__^Z`0```(G0
-M2(/$&%M=05Q!74%>05_#05=!5D%505154TB#[!A)B?Y(B?5!O0````!F@7T`
-M_S]V"@^W121$C6"KZQ9F@7T``C!V"$&\4`$``.L&0;P``0``08/]`70Q08/]
-M`7\'187M=`KK<D&#_0)T1>MJ08/$5<=$)!`(````2(V=W`0``$B-A=H$``#K
-M6&:#?1H`#X2N`0``08/$9<=$)!`"````2(V=3@4``$B-A4P%``#K,6:#?1P`
-M#X2'`0``08/$:<=$)!`#````2(V=+@4``$B-A2P%``#K"KH`````Z7,!``!(
-MB40D"$B+1"0(9L<```!!OP````!$.WPD$`^-00$``$2)YD'_Q$B-5"063(GW
-M0?^6*`,``+H`````A<`/A#$!``!F@7T``C!V"&8/MD0D%^L)#[=$)!9FP>@)
-M9HE#"&:#>P@`#X3E````187M=0X/MW,(2(GOZ+/E___K#`^W<PA(B>_HZ>7_
-M_V:)0PAF@7T``C!V&@^W1"069L'H`H/@/V:)0P8/MT0D%L'@!.L8#[=$)!9F
-MP>@#@^`_9HE#!@^W1"06P>`#@^`_9HE#!$2)YD'_Q$B-5"063(GW0?^6*`,`
-M`+H`````A<`/A(,```!F@7T``C!V)`^W1"069L'H#&8)0P0/MT0D%F;!Z`:#
-MX#]FB4,"#[=$)!;K)0^W1"069L'H#68)0P0/MT0D%F;!Z`>#X#]FB4,"#[=$
-M)!9FT>B#X#]FB0-(BT0D"&;_`$B#PPI!_\=$.WPD$`^,O_[__T'_Q4&#_0(/
-MCMO]__^Z`0```(G02(/$&%M=05Q!74%>05_#05=!5D%505154TB#[!A)B?Y)
-MB?=,C:9D!0``9H$^_S]V"T0/MVXD08/%&NL59H$^`C!V"$&]OP$``.L&0;UO
-M`0``QT0D$`````!F08._!`$````/A*`#``!(8T0D$&9!@[Q'!@$```!U&F9!
-M@3\",'8)08/%".ED`P``08/%!^E;`P``9D&!/P(P#X;#````O0````!$B>Y!
-M_\5(C50D%DR)]T'_EB@#``"Z`````(7`#X1'`P``2&/%#[=4)!:)T6;!Z0AF
-M08D,Q&:!XO\`9D&)5,0(@\4"@_T'?KB]`````$2)[D'_Q4B-5"063(GW0?^6
-M*`,``+H`````A<`/A/H"``!(8]5F#[9$)!>#X#]F08E$U`(/MT0D%F;!Z`Z#
-MX`%!B434!`^W1"06@^`_9D&)1-0*#[=$)!9FP>@&@^`!08E$U`R#Q0*#_0=^
-ME.DM`@``1(GN0?_%2(U4)!9,B?=!_Y8H`P``N@````"%P`^$B0(```^W1"06
-MB<)FP>H)9D&)%"1FP>@"@^!_9D&)1"0(#[=$)!;!X`6#X']F08E$)!!$B>Y!
-M_\5(C50D%DR)]T'_EB@#``"Z`````(7`#X0Y`@``#[=$)!:)PF;!Z@MF00E4
-M)!!FP>@$@^!_9D&)1"08#[=$)!;!X`.#X']F08E$)"!$B>Y!_\5(C50D%DR)
-M]T'_EB@#``"Z`````(7`#X3H`0``#[=$)!:)PF;!Z@UF00E4)"!FP>@&@^!_
-M9D&)1"0H#[=$)!8!P(/@?V9!B40D,$2)[D'_Q4B-5"063(GW0?^6*`,``+H`
-M````A<`/A)@!```/MU0D%HG09L'H#V9!"40D,(G09L'H"(/@?V9!B40D.&;!
-MZ@*#XC]F08E4)`(/MT0D%L'@!(/@/V9!B40D"D2)[D'_Q4B-5"063(GW0?^6
-M*`,``+H`````A<`/A#@!```/MU0D%HG09L'H#&9!"40D"HG09L'H!H/@/V9!
-MB40D$H/B/V9!B50D&D2)[D'_Q4B-5"063(GW0?^6*`,``+H`````A<`/A.T`
-M```/MT0D%HG"9L'J"F9!B50D(F;!Z`2#X#]F08E$)"H/MT0D%L'@`H/@/V9!
-MB40D,D2)[D'_Q4B-5"063(GW0?^6*`,``+H`````A<`/A)P````/MT0D%HG"
-M9L'J#F9!"50D,F;!Z`B#X#]F08E$)#J]`````$AC1"002(E$)`A(8\5!@SS$
-M`'0_2(M4)`A!#[>$5P8!``"#X`=T!8/X`W422&/=00^W--Q,B?_HZ>#__^L0
-M2&/=00^W--Q,B?_H&^'__V9!B03<_\6#_0=^L$F#Q$#_1"0000^WAP0!```Y
-M1"00#XQ@_/__N@$```")T$B#Q!A;74%<05U!7D%?PT%6055!5%532(/L$$F)
-M_$B)\V;'1BH/`&;'1BP/`&:!/@(P=A))Q\8`````9L>&!`$``"``ZQ!)Q\8`
-M````9L>&!`$``!``2(U4)`Y!BS9,B>=!_Y0D*`,``,=$)`@`````A<`/A+0-
-M```/MU0D#HG09L'H#V:)0P:)T&;!Z`Z#X`%FB4,*B=!FP>@+@^`'9HE##(G0
-M9L'H!(/@?V:)0PYF@3O_/W8/B=!FP>@#@^`!9HE#".L&9L=#"`$`#[=4)`Z)
-MT&;!Z`*#X`%FB4,<B=!FT>B#X`%FB4,:@^(!9HE3%D&+;@2)[O_%2(U4)`Y,
-MB>=!_Y0D*`,``,=$)`@`````A<`/A!4-``!F#[9$)`^(0QX/MD0D#HA#'V:!
-M._\_#X;4````B>[_Q4B-5"0.3(GG0?^4)"@#``#'1"0(`````(7`#X35#```
-M#[=4)`Z)T&;!Z`YFB4,NB=!FP>@-@^`!B8/(````B=!FP>@,@^`!B8/,````
-M9H'B_P]FB5,PB>[_Q4B-5"0.3(GG0?^4)"@#``#'1"0(`````(7`#X1[#```
-M#[=$)`Z)PF:!XO\/9HE3)&;!Z`Z#X`&(0R-F@3O_3W8U@\4"2(U4)`Z)[DR)
-MYT'_E"0H`P``QT0D"`````"%P`^$-0P```^W1"0.9L'H!&:)@]````!!O0``
-M``!)8\5!BVR&"(GN_\5(C50D#DR)YT'_E"0H`P``QT0D"`````"%P`^$\PL`
-M`$ECU68/MD0D#X/@?V:)1%,R#[=$)`YFP>@"@^`_9HE$4S@/MT0D#L'@!(/@
-M/V:)1%-TB>[_Q4B-5"0.3(GG0?^4)"@#``#'1"0(`````(7`#X2="P``26/5
-M#[=$)`YFP>@,9@E$4W0/MT0D#F;!Z`:#X#]FB413>@^W1"0.@^`_9HF$4X``
-M``")[O_%2(U4)`Y,B>=!_Y0D*`,``,=$)`@`````A<`/A$<+``!)8]4/MT0D
-M#F;!Z`IFB813A@````^W1"0.9L'H!(/@/V:)A%.,````#[=$)`[!X`*#X#]F
-MB813D@```(GN_\5(C50D#DR)YT'_E"0H`P``QT0D"`````"%P`^$Z`H``$EC
-MU0^W1"0.9L'H#F8)A%.2````9@^V1"0/@^`_9HF$4Y@````/MT0D#F;!Z`*#
-MX#]FB813G@````^W1"0.P>`$@^`_9HF$4Z0```")[O_%2(U4)`Y,B>=!_Y0D
-M*`,``,=$)`@`````A<`/A'@*``!)8]4/MT0D#F;!Z`QF"813I`````^W1"0.
-M9L'H!H/@/V:)A%.J````#[=$)`Z#X#]FB813L````(GN_\5(C50D#DR)YT'_
-ME"0H`P``QT0D"`````"%P`^$'`H``$ECU68/MD0D#XA$$U9!@_T!=$Y!@_T!
-M?PI%A>UT#>D'`0``08/]`G19ZW8/MT0D#HG"9L'J!8/B!V:)D_````!FP>@"
-M@^`'9HF#\@````^W1"0.`<"#X`=FB8/L````ZT`/MU0D#HG09L'H!(/@!V:)
-M@_0```"#X@=FB9/V````ZQ\/MU0D#HG09L'H!(/@!V:)@_@```"#X@=FB9/Z
-M````187M#X6`````B>[_Q4B-5"0.3(GG0?^4)"@#``#'1"0(`````(7`#X1.
-M"0``#[=4)`Z)T&;!Z`]F"8/L````B=!FP>@,@^`'9HF#[@```(G09L'H"8/@
-M!V:)@^@```")T&;!Z`:#X`=FB8/J````B=!FP>@#@^`'9HF#Y````(/B!V:)
-MD^8```")[O_%2(U4)`Y,B>=!_Y0D*`,``,=$)`@`````A<`/A,X(``!)8]5F
-M#[9$)`]FB413/F8/MD0D#F:)1%-$B>[_Q4B-5"0.3(GG0?^4)"@#``#'1"0(
-M`````(7`#X21"```26/59@^V1"0/9HE$4TIF#[9$)`YFB4134(GN_\5(C50D
-M#DR)YT'_E"0H`P``QT0D"`````"%P`^$5`@``$ECU68/MD0D#XA$$UEF#[9$
-M)`YFB4137(!\4UP`>0EF#0#_9HE$4UR)[O_%2(U4)`Y,B>=!_Y0D*`,``,=$
-M)`@`````A<`/A`@(``!)8]4/MT0D#F;!Z`5F)?\`9HE$4V(/MT0D#F;1Z(/@
-M#V:)1%-H#[=$)`Z#X`%FB413;F:!._\_=B]%A>UT"$&#_0)T%.LB#[=$)`YF
-MP>@-@^`!9HE#)NL0#[=$)`YFP>@-@^`!9HE#*&:!.P(P#X:D````B>[_Q4B-
-M5"0.3(GG0?^4)"@#``#'1"0(`````(7`#X1Q!P``26/5#[=$)`YFP>@&@^!_
-M9HF$4[8```!!@_T!=!5!@_T!?P=%A>UT3.M608/]`G0CZTX/MT0D#HG"@^('
-M9HF3_````&;!Z`.#X`=FB8,``0``ZRT/MT0D#HG"@^('9HF3_@```&;!Z`.#
-MX`=FB8,"`0``ZPP/MT0D#H/@/V:)0Q)F@3L#,`^&J````$ECU0^W1"0.9L'H
-M#6:)A%.\````B>[_Q4B-5"0.3(GG0?^4)"@#``#'1"0(`````(7`#X2N!@``
-M26/5#[=$)`[!X`.#X#AF"813O````$&#_0)U'P^W5"0.B=!FP>@#B$,B9H$[
-M!4!V"HG09L'H"V:)0RQ%A>UU06:!._\_#X8D!```#[=4)`Z)T&;!Z`B#X#]F
-MB8-&`0``9L'J`X/B'V:)DTH!``#K$4ECQ6;'A$.\````"@#&0R(/9H$[_S\/
-MAN,#``!!@_T!="-!@_T!?PY%A>T/A-`"``#IR0,``$&#_0(/A*<```#IN@,`
-M`(GN_\5(C50D#DR)YT'_E"0H`P``QT0D"`````"%P`^$U04```^V="0.2(G?
-MZ(G8__]FB8-4`0``#[9T)`](B=_H==C__V:)@U8!``")[DB-5"0.3(GG0?^4
-M)"@#``#'1"0(`````(7`#X2+!0``#[9T)`Y(B=_H/]C__V:)@U@!``!F@3L`
-M0`^&+0,``&8/MD0D#X/@/V:)@\0```#I&`,``(GN_\5(C50D#DR)YT'_E"0H
-M`P``QT0D"`````"%P`^$,P4```^V="0.2(G?Z.?7__]FB8-.`0``#[9T)`](
-MB=_HT]?__V:)@U`!``")[O_%2(U4)`Y,B>=!_Y0D*`,``,=$)`@`````A<`/
-MA.<$```/MT0D#HG"@^)_9HE3$&;!Z`>#X#]FB4,4B>[_Q4B-5"0.3(GG0?^4
-M)"@#``#'1"0(`````(7`#X2J!```#[9T)`Y(B=_H7M?__V:)@U(!``!F@3L`
-M0'809@^V1"0/@^`_9HF#Q@```(GN_\5(C50D#DR)YT'_E"0H`P``QT0D"```
-M``"%P`^$6P0```^W5"0.B=!FP>@%@^`_9HF#2`$``(/B'V:)DTP!``!F@3L!
-M0`^&\@$``(GN_\5(C50D#DR)YT'_E"0H`P``QT0D"`````"%P`^$#00``&8/
-MMD0D#F:)0RIF@3O_3P^&N0$```^W5"0.B=!FP>@(@^!_9HF#U@```&;!Z@]F
-MB9/:````B>[_Q4B-5"0.3(GG0?^4)"@#``#'1"0(`````(7`#X2T`P``#[=$
-M)`Z#X!\!P&8)@]H````/MU0D#HG09L'H!8/@/V:)@^(```!FP>H+B)/=````
-MB>Y(C50D#DR)YT'_E"0H`P``QT0D"`````"%P`^$8@,```^W1"0.@^`'P>`%
-M"(/=````#[=$)`YFP>@#B(/?````Z?X```!F@3L`0`^&\P```(GN_\5(C50D
-M#DR)YT'_E"0H`P``QT0D"`````"%P`^$#@,```^W5"0.B="#X#]FB8/"````
-M9H$[_T\/AK,```")T&;!Z`:#X']FB8/4````B=!FP>@-9HF#V````(GN_\5(
-MC50D#DR)YT'_E"0H`P``QT0D"`````"%P`^$L0(```^W1"0.@^`'P>`#9@F#
-MV`````^W5"0.B=!FP>@#@^`_9HF#X````&;!Z@F(D]P```")[DB-5"0.3(GG
-M0?^4)"@#``#'1"0(`````(7`#X1>`@``#[=$)`Z#X`'!X`<(@]P````/MT0D
-M#F;1Z(B#W@```$'_Q4&#_0(/CA/V__]F@3L",`^'B````$B-5"0.ONP```!,
-MB>=!_Y0D*`,``,=$)`@`````A<`/A`("```/MT0D#HG"@^('9HF3_````&;!
-MZ`.#X`=FB8,``0``2(U4)`Z^[0```$R)YT'_E"0H`P``QT0D"`````"%P`^$
-MO@$```^W1"0.B<*#X@=FB9/^````9L'H`X/@!V:)@P(!``!FQX-@`0``!`!F
-MQX->`0```0!FQX-<`0```0!FQX-:`0````!!BVX40;T`````9H.[!`$```!T
-M4XGN_\5(C50D#DR)YT'_E"0H`P``QT0D"`````"%P`^$0P$``$ECU68/MD0D
-M#V:)A%,&`0``9@^V1"0.9HF$4P@!``!!@\4"#[>#!`$``$$YQ7RM9H$[`E!V
-M=D&]`````$B-5"0.B>Y,B>=!_Y0D*`,``,=$)`@`````A<`/A.4```!)8]4/
-MMT0D#F:)A)..`P``C74%2(U4)`Y,B>=!_Y0D*`,``,=$)`@`````A<`/A+(`
-M``!)8]4/MT0D#F:)A).0`P``_\5!_\5!@_T$?I!F@3L",'<F9L=#7,K_9L=#
-M7O__9L=#8/__=Q)FQT-$#P!FQT-&'`!FQT-('`!F@3O_/W8,2(U4)`Z^R@``
-M`.L*2(U4)`Z^SP```$R)YT'_E"0H`P``QT0D"`````"%P'0V#[=$)`YFB4,8
-M9H-[%@!U'F:!._\_=@L/M\#!Z`N#X`'K"`^W0QAFP>@/9HE#%L=$)`@!````
-MBT0D"$B#Q!!;74%<05U!7L-(@^P82(E<)`A(B6PD$$B)_4B)\^BX\?__N@``
-M``"%P'1)2(G>2(GOZ*C2__^Z`````(7`=#5(B=Y(B>_H!>C__[H`````A<!T
-M(4B)WDB)[^@8Z___N@````"%P'0-2(G>2(GOZ%GM__^)PHG02(M<)`A(BVPD
-M$$B#Q!C#2(/L"&:!/O\_=@QF@WXN`74%Z*_<__](@\0(PP^W!V8[!G45#[=7
-M`H'B\,$```^W1@(E\,$``.L&#[<7#[<&*<*)T,,/MX>X`P``)?^_``##N@``
-M``!(8\)(@SS'`'0&N`````##_\*#^@%^Z;@!````PTB#[`CHR/___XG!9H7`
-M>3%F@>'_?[H`````2,?&`````$ACPDB-!(!F.0R&=`S_PH'Z@@```';IZR>X
-M`0```.LEN@````!(Q\8`````2&/"2,'@!68Y#`9TX/_"@_I*=NRX`````$B#
-MQ`C#4XGSN`$```!FA?9T9NA4____B<%FA<!Y%0^WPXG*@>+_?P``.=`/E,`/
-MML#K168]_P%T!6:%P'4'N`$```#K,[H`````2,?&`````$ACPDB-!(!(P>`"
-M9CL<!G4'9CE,!@)TU?_"@?J"````=MZX`````%O#2(/L&$B)'"1(B6PD"$R)
-M9"002(GU28G4_Y<@`P``B<.H0G0)@WT(`'4#@^.]]L,@=`F#?0P`=0.#X]_V
-MPPAT"8-]!`!U`X/C]_;#`70428U\)"#HIO[__XG:@^+^A<`/1=J)V$B+'"1(
-MBVPD"$R+9"002(/$&,-(@>RH````2(F<)(@```!(B:PDD````$R)I"28````
-M3(FL)*````!(B?U!O0`````/M_[HG@```$B)PTB%P'0H2(GANG__``!(B<9(
-MB>_HM@$``(7`=!%(B>)(B=Y(B>_H)/___T&)Q42)Z$B+G"2(````2(NL))``
-M``!,BZ0DF````$R+K"2@````2('$J````,-32(G[Z-[]__\/M\"#^!)T)(/X
-M$G\&A<!T$.L@/?\!``!T!SU*@P``ZPEF@;NZ`P``2@-U![@!````ZP6X````
-M`%O#B?FZ`````$C'Q@````!(8\)(C02`2,'@`F8Y#`9U!T@%`````,/_PH'Z
-M@@```';>N`````##55-(@^P(Z&/]__^)Q6:%P'D?B>N!X_]_``")W^BI____
-MB=I(A<!U0NL'#[=4`@CK.;H`````2,?!`````$ACPDC!X`5F.2P!=11(Q\(`
-M````9H-\`@@`==&Z2P```/_"@_I*=MBZ`````(G02(/$"%M=PTB#[`A)B?"Z
-M`````$ACPDB)P4C!X0</MX$`````.?AU($V%P'042(VQ`````+J`````3(G'
-MZ`````"X`0```.L,_\*#^C!VQ+@`````2(/$",.Y`````(7_="RZ`````$C'
-MQ@````!(8\)(P>`%#[<$!KD!````.?AT#/_"@_I*=N6Y`````(G(PT%7059!
-M54%455-(@^P82(E\)!!)B?5)B<]!B=1!O@````!(QT0D"`````!(QP0D````
-M`&:#/@!U+^@S_/__B<-FA<!X(P^WZ+X`````B>_H(O___X7`=0N)[^AI____
-MA<!T!0^W^^L%00^W?0)F]\<`_P^%^0```+D`````O@````!)Q\``````2&/!
-M2(G"2,'B!4$/MP00.?AU$4B!P@````!(B50D"+X!````_\&#^4IW!H7V=-'K
-M#;@`````A?8/A.4```!%A.1X#4B+1"0(#[=X`D2+<`A%A.1Y#4B+5"0(#[=Z
-M!$2+<@RY`````+X`````2<?``````$ACP4B-!,!(C12%`````$$/MP00.?AU
-M(DB+7"00BX.(`P``03M$$`1U$$B!P@````!(B10DO@$```#_P8/Y`7<&A?9T
-MN^L$A?9T*D6$Y'@02(L4)(M""$DAQHM"#$D)QD6$Y'D02(L<)(M#$$DAQHM#
-M%$D)QDR)_NC]_?__B<:X`````(7V="A)BT<02(M4)`A((T(028E'$&9!]T4"
-M`/]U"4V%]G0$18EW&+@!````2(/$&%M=05Q!74%>05_#C4<_@___#T_'P?@&
-MB<+!X@:)^2G1N@$```!(T^)(F$@C%,9(A=(/E<`/ML##A,ET*K@`````.?!S
-M%DQCP$$X##AT&$&`/#@`=`;_P#GP<NHY\'0'2)B(##C_`I##2('LZ`$``$B)
-MG"2X`0``2(FL),`!``!,B:0DR`$``$R)K"30`0``3(FT)-@!``!,B;PDX`$`
-M`$B)^TF)]D&)UTB)3"1@3(E$)%A$B4PD5(NL)/@!``"+A"0``@``9HE$)%)F
-MQT0D2E@;3(VGX`,``$&]`````.@-^O__N@````"%P`^$9P8``$B)W^A;_/__
-M9HF#N@,``&:%P'4E#[?U2(G?Z$SZ__^Z`````(7`#X0[!@``B>AF)?\_9HF#
-MN@,``$B)W^CW"@``#[>[N@,``.C@^___2(G%N@````!(A<`/A`D&``!(C8PD
-M,`$``+I__P``2(G&2(G?Z.K\__^Z`````(7`#X3D!0``2(V,)+````"Z@```
-M`$B)[DB)W^C%_/__N@````"%P`^$OP4``/:$)#@!```%N`$```!$#T7H]H0D
-M.`$```*X`@```$0/1>A$.ZN\`P``=`=$B:N\`P``2(V4)#`!``!(B>Y(B=_H
-M\_G__XE$)$R#O"0(`@```'4)#[=M$&:);"1*QT0D1`````!!@_]!N$````!$
-M#T/X#[:#D@,``(G"P.H%B=&#X0&)3"0TP.@&B<*#X@&)5"0X2,?%`````$B!
-M_0`````/@S,$```/MT0D4F8C10!FA<`/A!`$```/MT4`A40D3`^$`@0```^W
-M=0)(C4PD;DB-5"1L2(G?_Y,8`P``A<`/A.,#```/MT4`@_@$#X29````@_@$
-M?P^#^`%T8X/X`G0OZ<(#``"#^"`/A-L```"#^"!_#H/X"`^$G0```.FF`P``
-M@_A`#X3O````Z9@#``!(C8PD,`$``$B)3"0@2(/!,$B)3"0H2,=$)!``````
-M#[:$)#(!``"#R`/IA0```$B-E"0P`0``2(E4)"!(@\(@2(E4)"A(QT0D$```
-M```/MHPD,@$``.F)````2(V$)+````!(B40D($B#P%!(B40D*$C'1"00````
-M``^VE"2R````@\H!Z8H```!(C8PDL````$B)3"0@2(/!8$B)3"0H2,=$)!``
-M````#[:$)+(```"#R`*(1"0_ZUY(C90DL````$B)5"0@2(/"<$B)5"0H2,=$
-M)!``````#[:,)+(```"#R02(3"0_ZRY(C80D,`$``$B)1"0@2(/`0$B)1"0H
-M2,=$)!``````#[:4)#(!``"#R@2(5"0_2(M\)"CHY/;__X7`#X5N`@``QT0D
-M0`````!(BW0D*(M\)$#H`_S__X7`#X1!`@``2&-$)$!(P>`%2`-$)!!(B40D
-M&`^V2!A(BY0D\`$``(MT)%1(BWPD6.C[^___2(M,)!A$#[<I9D0[:0(/AP`"
-M```/MT0D2H/`"HE$)`QF1#EL)&P/A]`!``!F1#ML)&X/A\0!``!(BT0D&(!X
-M!@IU"X-\)#0`#X2N`0``2(M4)!B`>@8%=0N#?"0X``^$F`$``$$/M\5(BTPD
-M&`^V40<!T-'X.T0D#`^/?0$``$0Y?"1$#X.J`0``2(-Y$`!Y#H.\)!`"````
-M#X1=`0``2(M$)""`>!@`>0V#NXP#```&#X1%`0``OD````!(C7PD<.@`````
-M9D2);"1P#[=%`F:)1"1R2(M,)!@/ME$&@_H%=`^#^@IU$8#,0&:)1"1RZP=F
-M@4PD<@"`2(M4)!@/MD($B$0D=0^V0@6(A"2*````2(M,)""+01B)A"2,````
-M#[9$)#^)A"20````2(M"$$@C01`/MTPD<H#-`@^W5"1R@.;]2(7`#T719HE4
-M)')(BU0D&$B+0@A(BTPD($@C00A(A<`/E<`!P(A$)'1(BT((2"-!"*@"=`6`
-M3"1T"$B+1"0@]D`80'0%@$PD=`1(8U0D1$C!X@9(BT0D<$F)!!1(BT0D>$F)
-M1!0(2(N$)(````!)B404$$B+A"2(````28E$%!A(BX0DD````$F)1!0@2(N$
-M))@```!)B404*$B+A"2@````28E$%#!(BX0DJ````$F)1!0X_T0D1$B+5"08
-M9@^V0@=!`<5F1#MJ`@^&#/[___]$)$"#?"1`?P^.FOW__TB#Q01(@?T`````
-M#X+-^___@WPD1``/A+T```"#?"1$0;A`````#T)$)$2)1"1$2,?!`````+I`
-M````B<9,B>?HZ0(``(M,)$2)B^`3``"^`````#G.?3Y(8\Y(B<I(P>(&00^W
-M!!1F08D$SD$/MT04`F9!B43.`D$/MD04!$&(1,X$00^V1!0%08A$S@7_QCMT
-M)$1\PHM4)$1,B?9(B=__DV`#``"^`````#MT)$1]*$ACQDB)P4C!X09!#[94
-MQ@9!B%0,!D$/MD3&!T&(1`P'_\8[="1$?-B+5"1$2(M$)&")$`^W@[H#``!F
-MB4,HA=(/E<`/MM")T$B+G"2X`0``2(NL),`!``!,BZ0DR`$``$R+K"30`0``
-M3(NT)-@!``!,B[PDX`$``$B!Q.@!``##4T0/MT8"08'@\,$``$B+C^@3``!(
-MA<ET*`^W`68[!G4@#[=1`HG0)?#!``!$.<!U$/9!!`%T6+@`````]L("ZTQ,
-MC8_@`P``BY?@$P``A=)T8`^W-HG0T?A(F$C!X`9*C0P(#[<!B?,IPXG8=38/
-MMWD"B?@E\,$``$0YP'46]D$$`70+N`````!`]L<"=2A(B<CK(P^W00(E\,$`
-M`$2)PRG#B=B%P'X&3(U)0/_*T?IUH[@`````6\-3B=/H`````+H`````2(7`
-M=!4/OD`:`<`HPP^^TX3;N``````/2-")T%O#2(/L&$B)'"1(B6PD"$R)9"00
-M2(G[2(GU0;S_````9H._N@,```!U?^@?\O__B<*)T"7P````@_A@=`=F@?J9
-M`75E#[=%`B6@````0;SA````/:`````/A((````/MT4")=````!!O.(````]
-MP````'1L#[=%`B70````0;SD````/=````!T5@^W10(E4`$``#U0`0``#Y3`
-M1`^VX$>-I&3@````ZS=(B>Y(B=_H`````$B%P'0G1(M@(`^W10(EP````#W`
-M````=1-$B>"#X`^#^`%U"$&#Y/!!@\P"1(G@2(L<)$B+;"0(3(MD)!!(@\08
-MPTB#[`CH`````+H`````2(7`=`N+0!S!Z`*)PH/B`8G02(/$",-!5T%6055!
-M5%532(/L&(ET)!1!B=9(B4PD"$F)_8G03(T\./],)!1T3TB)!"1,B?U-.>]V
-M.46)]$B)ZTPIXTB)[DB)W_]4)`B%P'XB2(GI1(GV#[83#[8!B`-(_\.($4C_
-MP?_.=>Q,*>5,.>UWRDP#/"3_3"04=;5(@\086UU!7$%=05Y!7\-(@^P82(E<
-M)`A(B6PD$$B)^TB)_4B-5"0&OL$```#_ER@#``"Z`````(7`=%9F@7PD!O\_
-M=@>^R@```.L%OL\```!(C50D!$B)[_^5*`,``+H`````A<!T*F:!?"0&_S]V
-M#0^W1"0$P>@+@^`!ZP@/OT0D!,'H'XF#]!,``(N3]!,``(G02(M<)`A(BVPD
-M$$B#Q!C#4TB)^^@/\/__#[?`@_A(=%6#^$A_%8/X07\+@_A`?4:%P'0FZTJ#
-M^$/K.3V-@0``?Q$]B($``'TM@^A*@_@"=R_K(SV/@0``ZQH/MX.Z`P``/8@!
-M``!\&#V-`0``?@<]CP$``'4*2(G?Z/[^___K!;@`````6\-!5%532(/L$$F)
-M_(GS2(G]2(U4)`Z^P0```/^7*`,``(7`=%>Z`````$C'P0````!(8\)(C01`
-M2`'`9CD<`74T9H%\)`X"4'<'#[=$`0+K#$ACPDB-!$`/MT1!!&:)A;@#``!,
-MB>?HR/'__V:)A;H#``#K!__"@_H-=K5(@\006UU!7,-!5%532(/L$$F)_(GS
-M2(G]2(U4)`Z^P0```/^7*`,``(7`=%>Z`````$C'P0````!(8\)(C01`2`'`
-M9CD<`74T9H%\)`X"4'<'#[=$`0+K#$ACPDB-!$`/MT1!!&:)A;@#``!,B>?H
-M1/'__V:)A;H#``#K!__"@_H&=K5(@\006UU!7,-(@^P82(E<)`A(B6PD$$B)
-M^^AK_O__A<!T,_:#E`,```%T*F:#N[@#````=!$/M[.X`P``2(G?Z+S^___K
-M#P^WL[H#``!(B=_H+____TB+7"0(2(ML)!!(@\08PY!!5T%6055!5%532('L
-MJ````$F)]DF)UTB)3"003(E$)`B)_;_`%0``Z`````!(B<-!O0(```!(A<`/
-MA+P%``!)B<2Z*!0``$C'Q@````!(B<?H`````$R)<Q!,B7L82(M$)!!(B4,@
-M9HFK>`,``&;'@WH#`````&;'@ZP#```\`,>#L`,```````#'@^P4```#````
-MQX.L%0```````,>#L!4````'``#'@[05``#_____QX.X%0``_____\>#O!4`
-M`/____^^`````$B)W^@`````0;T#````A<`/A!H%``#'@WP#```!````2(M#
-M((N0($```&8/MM)FB9.``P``BY`8F```9HF3@@,``&;'@X8#`````,>`T)@`
-M`!8<``"]`````$F+1"0@QX"`F``````!`/_%@_T#=NI)BT0D((NX`)P``,'O
-M'+X$````Z`````#_P&9!B80DA`,``$F+5"0@1(NR$$```$2)\(/(`8F"$$``
-M`$B-5"0>OCT```!,B>?H`````$&]"````(7`#X19!```9H%\)!ZE6G0+0;T$
-M````Z44$``!(C50D'KX_````3(GGZ`````!!O0@```"%P`^$)00```^W1"0>
-M9HF#*A0``$B-5"0>OL$```!,B>?H`````$&]"````(7`#X3Y`P``#[=$)!YF
-MP>@,9HF#*!0``$&]!0```&:#^`$/A=D#``!!OP````"]`````$R-;"0@B>I)
-MC515`(VUP````$R)Y^@`````A<`/A*8#``")Z`^W1$0@03''_\6#_3]VTD&]
-M!P```$&!____```/A8@#``!(C50D'KZ_````3(GGZ`````!!O0@```"%P`^$
-M:`,``&8/MD0D'F9!B80DN`,``(M$)"1FB8,L%```#[=$)"9FB8,N%```#[9$
-M)"B(@S`4``!F#[9$)"F(@S$4```/MD0D*HB#,Q0``&8/MD0D*XB#,A0``&8/
-MMD0D+8B#-A0```^V1"0LB(,W%```9@^V1"0OB(,X%```#[9$)"Z(@SD4```/
-MMD0D,(/@`8B#-!0``(M$)#!FT>B#X`>(@S44``!)QX0D:`,```````"]````
-M`+\)````B>A(C13%`````$@IPDB-%)!(C10:2(VR.A0``(GY#[=$3"!FP>@*
-MB((Z%```#[=$3"!FP>@$@^`_B$8+#[=43"#!X@*#XCR-3P$/MT1,(&;!Z`X)
-MPHA6`0^V1$PA@^`_B$8,#[=$3"!FP>@"@^`_B$8"#[=43"#!X@2#XC"-3P(/
-MMT1,(&;!Z`P)PHA6#0^W1$P@9L'H!H/@/XA&`P^V1$P@@^`_B$8.C5<##[=$
-M5"!FP>@*B$8$#[=$5"!FP>@$@^`_B$8/#[=45"#!X@*#XCR-3P0/MT1,(&;!
-MZ`X)PHA6!0^V1$PA@^`_B$80#[=$3"!FP>@"@^`_B$8&#[=43"#!X@2#XC"-
-M3P4/MT1,(&;!Z`P)PHA6$0^W1$P@9L'H!H/@/XA&!P^V1$P@@^`_B$82C5<&
-M#[=$5"!FP>@*B$8(#[=$5"!FP>@$@^`_B$83#[=45"#!X@*#XCR-3P</MT1,
-M(&;!Z`X)PHA6"0^V1$PA@^`_B$84#[=$3"!FP>@"@^`_B$8*#[=43"#!X@2#
-MXC"-3P@/MT1,(&;!Z`P)PHA6%0^W1$P@9L'H!H/@/XA&%@^V1$P@@^`_B$87
-MC5<)#[=$5"!FP>@*B$88#[=$5"!FP>@$@^`_B$89#[=45"#!X@*#XCR-3PH/
-MMT1,(&;!Z`X)PHA6&@^V1$PA@^`_B$8;#[=$3"!FP>@"@^`_B$8<_\6#QPN#
-M_00/AN+]__],B>?H_0```$&_`````+T`````0;T?````1(GN*>Y(C50D'DR)
-MY^@`````A<!T5P^W1"0>00''C50M`(G19@^V1"0?B(0+RQ0``/_"#[9$)!Z(
-MA!/+%```_\6#_0)VND6%_W0)08'__?\"`'4(0;T)````ZQ])BT0D($2)L!!`
-M``!,B>#K/$&]"````.L20;T(````28M$)"!$B;`00```2(7;=`A(B=_H````
-M`$B#?"0(`'0(2(M$)`A$B2BX`````$B!Q*@```!;74%<05U!7D%?PTB#[`CH
-M`````$B#Q`C#N`````#WQ@`!``!T#V;'`@`49L<!-A6X`0```,.X`0```,-(
-MC9>0`P``@TH$`6;'0@P`%&;'0@XV%8"/D`,```(/MD("9L=""`,`9L=""D``
-M@^">B$("@+\T%````'079L>'`!0`````QX<$%````0```(!*`H#'0A0/````
-MQX<@%````0```+@!````PY!(BU<@BT8$B8(L@```2(M7((M&#(F",(```$B+
-M5R"+1A")@C2```!(BU<@BT8(B8(X@```2(M7((L&B8(D@```PTB#["B)="0$
-M@[^,`P```70DB?`K!0````#!X`.)1"0,B?`K!0````#!X`.)1"00B70D".L8
-MQT0D#/_____'1"00_____\=$)`@!````B=`E__^``8D$)$B)YN@`````2(/$
-M*,-(BT<@QX`L@````````$B+5R"+@@2````-```0`"7__U__B8($@```2(M'
-M(,>`)(```/__``##28GX9H-^$@!T2$B+5R"+@@2````E__]__PT``"``B8($
-M@```2(M7(`^W1A")@BB```!(BU<@#[=&$HF"2(```$B+5R"+1A3!X`.)@C2`
-M``#K%4B+5R"+@@2````E__]?_XF"!(```$B+5R"+!HF"+(```$B+3R"+@22`
-M```E``"`_P^W5@@)PF:#?A@`=!$/MT88@\`$P>`0)0``?P`)PHF1)(```&:#
-MOX`#```#=CD/MT8:J`=T,4&+D+`5``"`YOAF@WX:!W<,P>`()0`'```)PNL#
-M@,X'08F0L!4``$B+1R")D!B```"0PY!(BT<@BX`(0```A<`/E<`/ML##2(M'
-M((M0'(/Z_W4,QP8`````N`````##B=`CA]04```ENM@%`8D&]\(@`'``=`<-
-M````0(D&]L(%=`.##@'WPL`%``!T`X,.0/9&`T!T!HF7"!0``+@!````PXN'
-MU!0``,-(B?E$BX?4%```187`>0M(BT<@QT`D`````(GR@>*ZV`4!B="#R`5`
-M]L8!#T700/;&0'0P@[G8%````'0#@\I`@[G<%````'0#@,X!@[G@%````'0#
-M@,J`@[GD%````'0#@,X$2(M'((E0((FQU!0``(7V>0M(BT<@QT`D`0```$2)
-MP,.0D)"X0````,.)\&:#_C]W'DC!X`4EX/\?`$B+5R"+A!`<D```N@$```!F
-MA<!X!;H`````B=##B?*X`````&:#_C\/AX<```!(P>(%@>+@_Q\`2(M'(,>$
-M`@"0````````2(M'(,>$`@20````````2(M'(,>$`@B0````````2(M'(,>$
-M`@R0````````2(M'(,>$`A"0````````2(M'(,>$`A20````````2(M'(,>$
-M`AB0````````2(M'(,>$`AR0````````N`$```##N`````!F@_X_=WM(A=)T
-M/40/MD(%0<'@"`^V0@1!"<`/MDH#P>$8#[9"`L'@$`G!#[9"`<'@"`G!#[8"
-M"<'1Z42)P,'@'PG!0='HZPM!N`````"Y`````$B)\DC!X@6!XN#_'P!(BT<@
-MB8P"&)```$B+3R!$B<"`S(")A`H<D```N`$```##2(/L*$B)7"0(2(EL)!!,
-MB60D&$R);"0@28G128G,187`N@````"XJJJJJHG!#T3*N`````!F@_X_#X=2
-M`0``08`Y`'4(9D&#>0($=PJX`````.DZ`0``9D&#>0(%=PA!O0````#K%F9!
-M@WD"#7<(0;T!````ZP9!O0,```!%#[99!$$/MD$%P>`(00G#00^V00;!X!!!
-M"<-!#[9!!\'@&$$)PT$QRT$/MD$)P>`(00^V40B)U0G%,<V!Y?__``!%#[91
-M"D$/MD$+P>`(00G"00^V00S!X!!!"<)!#[9!#<'@&$$)PD$QRD$/MD$/P>`(
-M00^V40Z)TPG#,<N!X___``!%#[9!$$$/MD$1P>`(00G`00^V01+!X!!!"<!!
-M#[9!$\'@&$$)P$$QR&9!@WD"#7<'08'@_P````^W]HGPP>`%2)A(BU<@1(F<
-M$`"0``!(BU<@B:P0!)```$B+5R!$B900")```$B+5R")G!`,D```2(M7($2)
-MA!`0D```2(M7($2)K!`4D```3(GBZ`````!(BUPD"$B+;"003(MD)!A,BVPD
-M($B#Q"C#D)!(@^P(2(GP2(VWRQ0``+H&````2(G'Z`````!(@\0(PTB#[`A(
-M@<?+%```N@8```#H`````+@!````2(/$",-(@^P(2(GWN@8```!(Q\8`````
-MZ`````!(@\0(P[@`````PTB#[!A(B5PD"$B);"002(G[2(G5C32U`&```$B+
-M1R"+!`:Y`@```+H#````O@!L``#H`````+H`````A<!T$TB+0R"+@`!H``!F
-MB44`N@$```")T$B+7"0(2(ML)!!(@\08PV8YM[@#``!U![@,````ZQ2`ORH4
-M````#YC`#[;`C03%`P```$B%TG0"B0*X`````,.X`0```,-(@^P82(D<)$R)
-M9"0(3(EL)!!)B?T/MY\`%```08G<08/D'$'!_`*#XP+1^T2)YN@`````.=@/
-ME,(/MM)$B>9,B>_H`````$B+'"1,BV0D"$R+;"002(/$&,-(BW\@C0PVN@,`
-M``#3XO?2BX<40```(<*X`@```-/@"<*)EQ1```"X`0```,-(BW\@C0PVN`,`
-M``#3X/?0BY<40```(=")AQ1```"X`0```,-(BW\@1(N'&$```+C^____B?'3
-MP$$AP(/B`=/B00G01(F'&$```+@!````PXGQN/____^#_@5W$DB+1R"+@!Q`
-M``"#X"_3Z(/@`<-(@^P(2(M'($2+B!1```!!B?!!P>`,`?:X`P```(GQT^!$
-M"<`-`(`!`/?002'!10G!08')`(```$2)R`T```$`A=)$#T7(2(M'($2)B!1`
-M``"+M]04``"!S@````'H`````$B#Q`C#2(M'((N0$$```(7V=`>#_@1T!^L-
-M@^*?ZPZ#XM^#RD#K!H/*((/BOTB+1R")D!!```##2(M'((N`!(```*D``(``
-M#Y7`#[;`_\##2(M'((N`!(```*D``(``=`>#_@)U!Y##@_X!=`](BU<@#0``
-M@`")@@2```"0P[@`````PX7V#Y3`#[;`PU532(/L"$B)^XG52(V_\!0``+H&
-M````Z`````!(BTL@#[:3\!0```^V@_$4``#!X`@)P@^V@_(4``#!X!`)P@^V
-M@_,4``#!X!@)PHF1"(```$B+2R`/MH/U%```P>`(#[:3]!0```G"B>@E_S\`
-M`,'@$`G"B9$,@```9H7M=1%(BU,@BX($@```#0``$`#K#TB+4R"+@@2````E
-M___O_XF"!(```$B#Q`A;7<-(BU<@B[)L@```BX)P@```BY)L@```C4@!.?(/
-M0L%(P>`@B=)("=##2(M'((N`;(```,-(BU<@BX(D@```#0````&)@B2```##
-M2(M'((N`9)@``(G!P>D3@>'_`0``]L4!=`:!\0#^__](BU<@BX)P@```BY)L
-M@```,=`QR,,/MY>``P``2(M'((N`($```"7_````.<(/E,`/MM")T,-(BT<@
-MBX"8@````09(BT<@BX"4@````48$2(M'((N`G(````%&#$B+1R"+@)"````!
-M1@A(BT<@BX"@@````480PTB#[!A(B1PD2(EL)`A,B60D$$B)_8GS28G\@_X(
-M=@Z^__\``.@`````.<-V$T''A"2T%0``_____[@`````ZQ^)WDB)[^@`````
-M2(M5((F"$(```(F=M!4``+@!````2(L<)$B+;"0(3(MD)!!(@\08PTB#[`A(
-MBT<@B[`0@```@>;__P``Z`````!(@\0(PTB#["A(B1PD2(EL)`A,B60D$$R)
-M;"083(ET)"!(B?U!B?:^_Q\``.@`````03G&=A''A;@5``#_____N`````#K
-M.$R+92!!BYPD%(```('C`.#__T2)]DB)[^@`````)?\?```)PT&)G"04@```
-M1(FUN!4``+@!````2(L<)$B+;"0(3(MD)!!,BVPD&$R+="0@2(/$*,-(@^P(
-M2(M'((NP%(```('F_Q\``.@`````2(/$",,/MH>O%0``@_`!@^`!PX7V="%(
-MBU<@BX($@```)?____Z)@@2```"!IZP5``#____^ZQ](BU<@BX($@```#0``
-M``&)@@2```"!CZP5```````!N`$```##2(/L*$B)'"1(B6PD"$R)9"003(EL
-M)!A,B70D($B)_4&)]K[_'P``Z`````!!.<9V$<>%O!4``/____^X`````.L[
-M3(ME($&+G"04@```@>/__P#@1(GV2(GOZ`````#!X!`E``#_'PG#08F<)!2`
-M``!$B;6\%0``N`$```!(BQPD2(ML)`A,BV0D$$R+;"083(MT)"!(@\0HPTB#
-M[`A(BT<@B[`4@```@>8``/\?P>X0Z`````!(@\0(P[@!````P\.X`````,/#
-MPTB#[`B#_@%U$872N@T```"X``````]%PNL%Z`````!(@\0(PTB#[`B#_@MT
-M#+@`````@_X>="/K'(G*@^(&B9>H`P``2(M'((F0:(```+@!````ZP7H````
-M`$B#Q`C#2(/L".@`````2(/$",.0D)!(BU<@BX($@```#0``!`")@@2```"%
-M]G052(M7((N"!$```"7___S_B8($0```PU532(/L"$B)^X7V=&5(BU<@BX($
-M0```)?___/^)@@1```"_T`<``.@`````O0H```!(BT,@BX`00```J0```0!T
-M);_(````Z`````!(BU,@BX($0```)?___/^)@@1```#_S77,ZP2%[74'N```
-M``#K&DB+4R"+@@2````E___[_XF"!(```+@!````2(/$"%M=PTB+5R"+@@2`
-M```-```$`(F"!(```(7V=!5(BU<@BX($0```)?___/^)@@1```##2(/L&$B)
-M'"1(B6PD"$R)9"00B?-(B?U!O`$```"#_@%T&(/^`7('@_X"=!?K'HG6Z`G_
-M__]!B<3K&8G6Z)#____K$(G6Z,7^___K![@`````ZPF)G>P4``!$B>!(BQPD
-M2(ML)`A,BV0D$$B#Q!C#2(M'((N`!$```"4```,`P>@0PY!3@_X!=`Y(Q\,`
-M````@_X"=!+K"4C'PP````#K![@`````ZPM(B=[H`````$B)V%O#D)"02(M'
-M((M`#,-(BT<@B7`,PTB+1R#'0`@$````PU532(/L"$B)_4B+1R#'0`@@````
-MNP````!(BT4@BT`(N@$```"H!'09OPH```#H`````/_#@?OG`P``?MRZ````
-M`(G02(/$"%M=PTB+5R"+@FB```"#X+^)@FB```##2(M7((N":(```(/(0(F"
-M:(```,-(BT<@B;!0@```2(M'((F05(```,.X`````(/^/W='@_X?=B!(BU<@
-M1(N"5(```(U.X+C^____T\!$(<")@E2```#K'4B+5R!$BX)0@```N/[___^)
-M\=/`1"'`B8)0@```N`$```##N`````"#_C]W1X/^'W8@2(M7($2+@E2```"-
-M3N"X`0```-/@1`G`B8)4@```ZQU(BT<@1(N`4(```+H!````B?'3XD0)PHF0
-M4(```+@!````PTB+1R"+@$R```##]\8``@``=`F!YO_]__^#SB!(BT<@B;!,
-M@```P\=&"`````")T"7_#P``B48,.=!T!K@`````P_;!('0'@4X,`"```,=&
-M%`````#'1A``````N`$```##]D84`74*N0\```#I"P$``/9!%`%U%$B+1R"+
-M0`RY#P```#G0#X3Q````#[=&$&8E_P]F08D!BTX4@>$`@/\/P>D/2(M'((N`
-M;(```(G"P>H*@>+__P``B=`E_Q\``#G(<P^-@@#@__\E__\```G!ZP()T8G(
-M9B7_?V9!B4$"0<9!!`"+1A2H`G4YJ`1T!T'&000!ZR[V1A00=`=!@$D$".LA
-M]D84"'0'08!)!`3K%$&`200"BT84)>````#!Z`5!B$$%BT80)0``^`?!Z!-!
-MB$$&BT84]L0!=`XE`'X``,'H"4&(00?K!4'&00?_BT80)0"`!P#!Z`]!B$$(
-MBT80P>@.@^`!08A!"8M&$,'H#(/@`4&(00JY`````(G(PT%7059!54%455-(
-M@^P(2(G[08GV28G5B4PD!$V)QTF)_/9"`P%T,TB)UN@`````2(G%N@P```!(
-MA<`/A)D%``!!@_X&=!Y!@_X&=PA!@_X!=PCK$$&#_@AT"KH,````Z74%``!(
-MBT,@BX`00```@^!@B00D3(GN2(G?Z`````"Z`P```(7`#X1-!0``2(M+($$/
-MMI0DRQ0``$$/MH0DS!0``,'@"`G"00^VA"3-%```P>`0"<)!#[:$),X4``#!
-MX!@)PHF1`(```$B+2R!!#[:4)-`4``#!X@A!#[:$),\4```)T(F!!(```$2)
-M]DB)W^@!!0``08/^`70A08/^`7(.08/^!G0P08/^"'0JZT%(BT,@QT`H`0``
-M`.L+2(M#(,=`*`````!(BT,@QX`00```)!```.L92(M#(,=`*`````!(BT,@
-MQX`00```0!```$B+4R"+@A!````+!"2)@A!```!(BTL@00^VE"3P%```00^V
-MA"3Q%```P>`("<)!#[:$)/(4``#!X!`)PD$/MH0D\Q0``,'@&`G"B9$(@```
-M2(M+($$/MI0D]10``,'B"$$/MH0D]!0```G0B8$,@```2(M#(,<``````$B+
-M0R#'0`0`````2(M#(,=`#`````!(BT,@BU`<QT`@`````$B+0R#'0"0`````
-M0<>$)-04````````2(M#((M0+,=`,`4```!(BT,@QT`T!0```$B+0R#'0$0(
-M````2(M#(,=`2`@```!(BT,@QT!0`````$B+0R#'0$P`````2(M#(,>`#$``
-M``````!(BT,@QT!``````$B+4R!!BX0DL!4``(F"&(```$B+0R#'@$B`````
-M````O@````!(B=_H`````$B+0R#'@%"`````````2(M#(,>`5(````````!(
-MBT,@QX!8@````````$B+0R#'@%R`````````2(M#(,>`8(````$```!(BT,@
-MQX!D@````0```$B+0R#'@&B`````````2(M#(,>`*(````````!(BT,@QX`L
-M@````````$B+0R#'@&R`````````2(M#(,>`,(```/____](BT,@QX`T@```
-M_____TB+0R#'@#B````!````O@````!(Q\<`````2&/&BQ3'@WPD!`!T#8V"
-M`(#__SW_#P``=A")T4B+4R!(8\:+1,<$B001_\:!_J8```!VS$R)[DB)W^@`
-M````N@,```"%P`^$.@(``$B+2R"+D2B8```P]D$/MH0D,10``,'@"`G"B9$H
-MF```2(MS($$/MI0D,A0``(G0P>`8P>(0"=!!#[:,)#,4``")RL'B"`G0"<B)
-MAC28``!(BTL@BY%$F```@>)_P/__00^WA"0L%```9M'H)8`_```)PHF11)@`
-M`$B+2R"+D4B8``"!XO\/_/]!#[>$)"P4``#!X`HE`/`#``G"B9%(F```2(M+
-M((N19)@``('B_P_X_T$/MH0D,!0``,'@#"4`\`<`"<*)D628``!(BTL@BY$0
-MF0``@^+\00^WA"0L%```@^`#"<*)D1"9``!(B>Y(B=_H-`T``+H#````A<`/
-MA#<!``"#?"0$`'0;]D4$`G4$@&4$_@^W10)F08E%`@^V101!B$4$2(M#(,>`
-M')@```$```"_Z`,``.@`````2(M3((N"8)@``(/(`8F"8)@``+D`````N@$`
-M``"^8)@``$B)W^@`````2(GN2(G?Z`````"]`````(7`=1!F08--`@*Z`P``
-M`.FO````B>Y(B=_H`````/_%@_T"?N^#NP04````=`A(B=_H`````$B+4R"+
-M@B2````E__]__HF")(```$&#O"2T%0``_W0008NT)+05``!(B=_H`````$&#
-MO"2X%0``_W0008NT)+@5``!(B=_H`````$&#O"2\%0``_W0008NT)+P5``!(
-MB=_H`````(.[J`,```!T$$B+4R"+@Z@#``")@FB```!$B;.,`P``N`$```#K
-M#D&#/P!T`T&)%[@`````2(/$"%M=05Q!74%>05_#2(M'((N`!(```"7__P``
-M@_X!=#Z#_@%_!H7V=!^0PX/^!G0'@_X(=#J0PTB+5R`+AZP5```-``!1`.L/
-M2(M7(`N'K!4```T``%(`B8($@```PTB+5R`+AZP5```-```4`.OH2(M7(`N'
-MK!4```T``!``Z]=(@^P(B[>,`P``Z'W___](@\0(PTB#[`BZ"@```+X(````
-MZ&@#``!(@\0(PU-(B?NZ`0```+X`````Z`````"Z`````(7`=$:Z($X``+X/
-M````2(G?Z#4#``"Z`````(7`="N_Z`,``.@`````NB!.``"^'P```$B)W^@0
-M`P``OS0(``#H`````+H!````B=!;PTB#[!A(B5PD"$B);"002(G]2(GSN@$`
-M``"^`````.@`````N@````"%P`^$F0```$B+32"Z`````$B%VW0,]D,"$+@!
-M````#T70B9$$F```NB!.``"^#P```$B)[^B;`@``N@````"%P'1>O^@#``#H
-M`````+H@3@``OA\```!(B>_H=@(``+H`````A<!T.;\T"```Z`````"Z`0``
-M`+X`````2(GOZ`````"Z`````(7`=!2Z"@```+X`````2(GOZ#8"``")PHG0
-M2(M<)`A(BVPD$$B#Q!C#05=!5D%505154TB#[!A(B?U)B?=(B50D$.@`````
-M28G&N@````!(A<`/A.,!``!(BU4@BX)H@```@\A@B8)H@```2(M5($2+JB2`
-M``!$B>@E__]__XF")(```+^@#P``Z`````!(BU4@BX((F```#0````B)@@B8
-M``"_"@```.@`````3(GV2(GOZ&0)``"Z`````(7`#X1V`0``O^@#``#H````
-M`$B+52"+@@B8```E____]XF"")@``$B+12"+F%B8``!$BZ!<F```BY!HF```
-MB50D#(G:@<H``/P#B9!8F```2(M5($2)X"5_`,#_#8#`/P")@ER8``!(BU4@
-MBT0D#"4?`/[_#8`1``")@FB8``"_%````.@`````2(M5((N"")@```T````(
-MB8((F```OPH```#H`````$B+12#'@-28```A````2(M5((N"")@``"7____W
-MB8((F```O^@#``#H`````$B+52"+@F"8``"#R`&)@F"8``"Y`````+H!````
-MOF"8``!(B>_H`````$B+12")F%B8``!(BT4@1(F@7)@``$B+12"+5"0,B9!H
-MF```3(GV2(GOZ`````"%P'4?OX@3``#H`````$R)]DB)[^@`````A<!U!F9!
-M@T\"`DB+12"+D&B```"#XI^)D&B```!(BT4@1(FH)(```$B+1"00QP`!````
-MN@$```")T$B#Q!A;74%<05U!7D%?PTB#[!A(B1PD2(EL)`A,B60D$$F)_(GS
-MB=>%]KC_____B<4/1>Y)BT0D((FP`$```.@`````@^,/B>J#X@^)V;X`0```
-M3(GGZ`````")PO;#!'4,28M$)"#'0!0`````B=!(BQPD2(ML)`A,BV0D$$B#
-MQ!C#OP````"Y"@````^VPD2-2`&-1`D#.,)U"TACP8`\,#]U>>M0C40)`P^V
-MP$$YP75+A<E^1TQCP4&`/#`_=#:-0?](8_B`/#<_="I!#[8$,`^V%#<IT&G`
-M7@$```7G`P``2&G`TTUB$$C!Z"#!Z`8!T`^VP,._`0```.L.@_\!=0E(8\&`
-M/#`_=1+_R7F$N0````!(8\&`/#`_=`4/M@0PP__!@_D*?NNX`0```,-328G*
-M0;G_____18G+OP````!(8\^`/#$_=#(Z%#%T73H4,78#08GY3&/'03H4,',<
-M08G[08/Y_W4<0XU$&P-!B`)!#[9$,`OIE@```/_'@_\*?K[K!8/_"GXPN#\`
-M``!!@_G_='V#_PI^($.-1`D#08@"26/!#[9$,`OK9HU$/P-!B`(/MD0Q"^M8
-M0XU$"P-!B`(/MOI)8\D/MA0Q*==I_^@#``!-8\M%#[8$,4$IT(GXF4'W^(G'
-M00^V1#$+#[94,0LIT`^O^(V'YP,``$AIP---8A!(P>@@P>@&`D0Q"P^VP%O#
-M@_X]N#P````/0_!FB;>L`P``N`$```##05=!5D%505154TB#[`A(B?M(B?=(
-MB=5(B=X/MX,N%```9L'H!(/@!XA"#P^V@RX4``"#X`>(0A`/MP=F+3(4N@``
-M``!F/98`#X>)`@``N0````")R&8/MH0&-A0``&8Y@[@#``!T!__!@_D#=N6Z
-M`````(/Y!`^$6P(```^W%X'J,A0``$ACPDAIP&=F9F9(P>@@P?@"P?H?*=")
-MPHU"_X/Z#`]#T(G2N*NJJJI(#Z_02,'J(4B-!-4`````2"G02(T$@DR-I#`Z
-M%```B<I"#[9$(AF(10Y!#[9$)!9".D0B&78&0@^V1"(9B$4)B<I!#[9$)!="
-M.D0B&78&0@^V1"(9B$4(B<I!#[9$)!A".D0B&78&0@^V1"(9B$4'B<A"#[94
-M(!E(C4PD!TR)YDB)W^C._?__08G%#[95"4B-3"0&3(GF2(G?Z+?]__]!B<</
-MME4(2(U,)`5,B>9(B=_HH/W__T&)Q@^V50=(C4PD!$R)YDB)W^B)_?__B<*#
-MN[`#````#X0!`0``BX.P`P``#[>,```````/ME0D!P^WP8/``SG"?0?&1"0'
-M`^L$*$PD!P^V5"0'3(GF2(G?Z)7\__^(10X/MM!(C4PD`TR)YDB)W^@L_?__
-M08G%#[9$)`<Z1"0&=@4/MD0D!HA$)`8/MM!,B>9(B=_H6OS__XA%"0^VT$B-
-M3"0#3(GF2(G?Z/'\__]!B<</MD0D!SI$)`5V!0^V1"0%B$0D!0^VT$R)YDB)
-MW^@?_/__B$4(#[;02(U,)`-,B>9(B=_HMOS__T&)Q@^V1"0'.D0D!'8%#[9$
-M)`2(1"0$#[;03(GF2(G?Z.3[__^(10</MM!(C4PD`TR)YDB)W^A[_/__B<(/
-MMD0D!P'`9HF#K@,```^V10Z(10J(10N(10R(10U$B>@HT(A%`$2)Z$0H\(A%
-M`42)Z$0H^(A%`L9%!@#&104`QD4$`,9%`P"Z`0```(G02(/$"%M=05Q!74%>
-M05_#05154TB#['!(B?U)B?1(B>>Z1````$C'Q@````#H`````$B-7"10NA$`
-M``!(Q\8`````2(G?Z`````!(B=I,B>9(B>_HS_S__[H`````A<`/A&D"```/
-MMD0D7__(N@`````\!`^'50(```^V1"1@_\BZ`````#P$#X=!`@``0;P`````
-M00^WW`^V?!Q0O@4```#H`````(A$'%!!_\1F08/\!G;?0;P'````00^WW`^V
-M?!Q0O@8```#H`````(A$'%!!_\1F08/\#G;?#[9$)%'!X`4EX`````^V5"10
-M@^(?"=`)!"0/ME0D4\'B!X'B@`````^V1"12P>`"@^!\"<(/MD0D4<#H`X/@
-M`PG""50D!`^V5"14P>($@>+P````#[9$)%/0Z(/@#PG""50D"`^V5"16P>(&
-M@>+`````#[9$)%4!P(/@/@G"#[9$)%3`Z`2#X`$)P@E4)`P/ME0D5\'B`X'B
-M^`````^V1"16P.@"@^`'"<()5"00#[94)%G!X@>!XH`````/MD0D6`'`@^!^
-M"<(/MD0D5\#H!8/@`0G""50D%`^V5"1:P>(%@>+@````#[9$)%G0Z(/@'PG"
-M"50D&`^V5"1;P>(#@>+X````#[9$)%K`Z`.#X`<)P@E4)!P/ME0D7`'2@^)^
-M#[9$)%O`Z`6#X`$)P@E4)"`/MD0D7<'@!27@````"40D)`^V5"1>P>(#@>+X
-M````#[9$)%W`Z`.#X`<)P@E4)"@/MD0D7L#H!8/@`0E$)"P/MGPD7[X#````
-MZ`````#!X`<E@`````E$)"`/MGPD7[X#````Z`````#1Z(/@`PE$)"0/MGPD
-M8+X#````Z`````#!X`*#X!P)1"0D0;P`````2(M%($$/M]2+%)2)D)R8``!!
-M_\1F08/\#W;E2(M%($$/M]2+%)2)D-28``"Z`0```(G02(/$<%M=05S#2(/L
-M&$B)7"0(3(ED)!!(B?M)B?0/MP8M`!0``$AC^$AI_V=F9F9(P>\@P?\"P?@?
-M*<>^!0```.@``````<"#R$%(BU,@B8*<F```2(M#(,>`P)@```````!,B:/H
-M$P``N`$```!(BUPD"$R+9"002(/$&,-(BT<@BX!DF```P>@39B7_`?;$`70$
-M9C4`_IC#05154TB)_4F)]$B+1R"+D&"8``"#R@*)D&"8``"Y`````+H"````
-MOF"8``#H`````+H`````A<!T1;L`````O^@#``#H`````$B)[^@`````F/_#
-M@_L4?P>#^+A_X>L4@_BX?@]F0<=$)!8``+H`````ZPMF08E$)!:Z`0```(G0
-M6UU!7,.X`````,.X`````,.02(/L"+@`````@_X"?QI(8\9(B<9(P>8$2"G&
-M2(VTM_@4``#H`````$B#Q`C#2(/L"$F)T+@`````@_X"?QU(8\9(B<)(P>($
-M2"G"2(V4E_@4``!,B<;H`````$B#Q`C#2(/L*$B)'"1(B6PD"$R)9"003(EL
-M)!A,B70D($F)_(GU28G52(GY@_X"=!.#_@)W!X/^`709ZSB#_@-T"NLQ0;X"
-M````ZPY!O@$```#K!D&^`````$ECUDB)T$C!X`1(*=!(C9R!^!0``(-[!`!T
-M![C_____ZTF^/````$B)W^@`````B6L$387M=2/'0PP+````QT,4`@```,=#
-M&/____]FQT,@"@!FQT,B"@#K#DR)ZD2)]DR)Y^@`````1(GP2(L<)$B+;"0(
-M3(MD)!!,BVPD&$R+="0@2(/$*,.X`````(/^`G=3B?)(B=!(P>`$2"G02(V$
-MA_@4``"#>`0`=0:X`````,/'0`0`````N/[___^)\=/`(8?8%```(8?<%```
-M(8?@%```(8?D%```(8?H%```N`$```##28GX2(N/Z!,``+@`````@_X"#X='
-M`@``B?)(B=!(P>`$2"G03(V,A_@4``!!@WD$`'4&N`````##08-Y!`%T!K@!
-M````P_9!`A`/A(````!(BT<@QX`0@```X`$``$B+1R#'@!2`````"``(2(M'
-M(,>`((```,^/W0%(BT\@08M1%(G0P>`$*=#!X!`%```/``W@`0``B8%`@```
-M2(M'(,>`1(```,`#K@5(BU<@BX)$F```@^"`@\@XB8)$F```2(M'(,>`!)@`
-M`",@`&_K?4B+1R#'@!"```!H`0``2(M'(,>`%(`````$``1(BT<@QX`@@```
-MIX_=`4B+5R!!BT$4:<!H`0``!3`"``#!X`L-,`(``(F"0(```$B+1R#'@$2`
-M``"8`]<$2(M7((N"1)@``(/@@(/('(F"1)@``$B+1R#'@`28```@$`!O08-Y
-M&/]U![@/````ZP1!BT$82(M/((G"P>(400^W02+!X`0E\`````G"00^W02"#
-MX`\)PH'*`"`(`(F1'(```$'V00P!=!*X`0```(GQT^!!"8#8%```ZQ"X_O__
-M_XGQT\!!(8#8%```0?9!#`%T$K@!````B?'3X$$)@-P4``#K$+C^____B?'3
-MP$$A@-P4``!!]D$,`G02N`$```")\=/@00F`X!0``.L0N/[___^)\=/`02&`
-MX!0``$'V00P$=!*X`0```(GQT^!!"8#D%```ZQ"X_O___XGQT\!!(8#D%```
-M0?9!#`AT$K@!````B?'3X$$)@.@4``#K$+C^____B?'3P$$A@.@4``"X`0``
-M`,.)]DB)\$C!X`1(*?"+A(?\%```A<!T#(/X`74'2(M'((L`P[C_____PXGV
-M2(GP2,'@!$@I\(N$A_P4``"#^`%T#(/X`7(8@_@#=Q/K"$B+1R")$.L/2(M'
-M((E0!.L&N`````##N`$```##2(/L&$B)'"1(B6PD"$R)9"002(G]B?/H````
-M`$&)Q(G&@>;___]_2(GOZ`````!(BT4@BY!D@```A=MT#;@E````*=#1Z`'"
-MZQN#^@%V!/_*ZQ)$B>9(B>_H`````+@`````ZQI(BT4@B9!D@```1(GF2(GO
-MZ`````"X`0```$B+'"1(BVPD"$R+9"002(/$&,.)]DB)\$C!X`1(*?"+A(?\
-M%```@_@!=!&#^`%R/H/X`G0L@_@#=`_K,DB+1R#'0`@!````ZRM(BT<@QT`(
-M`@```$B+1R#'0"@.````ZQ-(BT<@QT`H"@```.L&N`````##N`$```##B?9(
-MB?!(P>`$2"GPBX2'_!0``(7`=!6#^`%U$$B+1R"+0!0E`'@``,'H"\.X````
-M`,-54TB#[`A(B?V)]DB)\$C!X`1(*?"+A(?\%```@_@!=`R#^`%R9H/X`G1+
-MZU](BT<@QT`("````+L`````2(M%((M`%/;$>'04OPH```#H`````/_#@?OG
-M`P``?N!(BT4@QT`(`````('[YP,```^>P`^VP.L;N0````"Z!````+XL````
-MZ`````#K!;@`````2(/$"%M=PT2+3"08BWPD*$&-0/U!P>`:@_@!N`````Q$
-M#T;`@>+_#P``BT0D",'@$@G"P>$,@>$`\`,`"<I$"<*)T`T````!0/;'`0]$
-MPHG"@<H````@0/;'$`]$T(G0#0````*#?"0@``]%T(E6"$&#^?]T&D2)R,'@
-M#24`X`<`B48,B=`-````0(E&".L'QT8,`````$#VQP1T$X%."```0`"+1"0X
-M)0``^/\)1@RX`0```,.X`````,.!3@@````@PX7)=!*+1@P)T(G"@,X0187`
-M#T3"ZQU%A<!T#$&+00B)1@B)5@SK#\=&"`````")T(#,$(E&#,=&%`````#'
-M1A``````N`$```##2(GQ]D84`74&N`\```###[=&%&8E_A]FB0(/MT829HE"
-M`L9"!`"+1A"H`74<J`)T!,9"!`'V01`(=`2`2@0"]D$0!'0$@$H$!(M!""4`
-M`#P`P>@2B$(%BT$4)0#@'P#!Z`V(0@:+01`E``\``,'H"(A"!XM!$"7P````
-MP>@$B$((QD(*`,9""P"X`````,/#D(!.!`BX`````,.0D$B#[`A(BT<@QX#0
-MF```%AP``+H`````2(M'(,>`@)@``````0#_PH/Z!W[K2(M'((N``)P``(G'
-MP>\8B?K!Z@2)^(/@#\'@!(G7"<>^"````.@`````2(/$",-!5T%6055!5%53
-M2(/L&$F)]DF)UTB)3"0(3(D$)$&)_;^X,```Z`````!(B<-!O`(```!(A<`/
-MA#@$``!(B<6Z*!0``$C'Q@````!(B<?H`````$R)<Q!,B7L82(M$)`A(B4,@
-M9D2)JW@#``!FQX-Z`P````!FQX.L`P``/P#'@[`#````````QX-P,```````
-M`,>#C#````````#'@Y0P````!P``QX.8,```_____\>#G#```/_____'@Z`P
-M``#_____O@````!(B=_H`````$&\`P```(7`#X25`P``9H&[>`,``!OQ=29(
-MBT,@QX``H@```````$B+0R#'@'R8```9````O^@#``#H`````$B+12"+@"!`
-M```E_P```(G"P>H$B95\`P``@^`/9HF%@`,``(/J`D&\#0```(/Z`@^'+@,`
-M`$B+12"+@!B8``!FB86"`P``2(GOZ%X#``!!O`X```"%P`^$!P,``(.]?`,`
-M``-V$$B+12#'@`"8```'````ZPY(BT4@QX``F```1P```+_0!P``Z`````!(
-MB>_H__W__V:)A80#```/M\`E\````$&\#0```(/X$`^%L`(``$B-5"06OL$`
-M``!(B>_H`````$&\"````(7`#X20`@``9H%\)!;_+W<+0;P%````Z7P"```/
-MMT0D%F:)@R@4``!(BT4@BX`00```@^`8P>@#0;P*````@_@"#X51`@``2(U4
-M)!:^/P```$B)[^@`````0;P(````A<`/A#$"```/MT0D%F:)@RH4``!!O0``
-M``!!O`````!!C;0DP````$B-5"062(GOZ`````"%P`^$]@$```^W1"0603'%
-M0?_$08'\/P,``';/0;P'````08']__\```^%U0$``&;'@YX5```*`&;'@Z@7
-M```#`$&\`````$2)X$AKP#1FQX0#IA4```L`0?_$08/\"7;F0;P`````2,?!
-M`````$2)X`^W%$%FB91#L!<``&:)E$.J%P``2&O`-$@!V&;'@&P8```+`&;'
-M@-`7```+`$'_Q$&#_`)VQTB-LR@4``!(B>_H`````$&\"````(7`#X1``0``
-M@[U\`P```W9F9H.[0A0```!T7$B+12#'@`"8```'0```O]`'``#H`````$B)
-M[^@^_/__9HF%A@,``$B+12#'@`"8```'````O]`'``#H``````^WA88#```E
-M\````$&\#0```(/X(`^%TP```.L)9L>#0A0`````2(U4)!:^OP```$B)[^@`
-M````0;P(````A<`/A*@````/MT0D%F:)@RP4``!FB86X`P``2,>%:`,`````
-M``!(B>_H``(``$B)[^@`````0;T`````0;P`````0;X?````1(GV1"GF2(U4
-M)!9(B>_H`````(7`=$L/MT0D%D$!Q4.-%"2)T68/MD0D%XB$"_`M``#_P@^V
-M1"06B(03\"T``$'_Q$&#_`)VMT6%[70,2(GH08']_?\"`'4N0;P)````ZP9!
-MO`@```!(A=MT"$B)W^@`````2(,\)`!T!TB+!"1$B2"X`````$B#Q!A;74%<
-M05U!7D%?PU-(B?M(C;<H%```Z`````!(B=_H`````%O#4TB#["#'1"0(`(``
-M`,=$)`P@F```QT0D$%55557'1"04JJJJJL=$)!AF9F9FQT0D')F9F9E!N@``
-M``!(C5PD"$F)XTECTDC!X@)$BPP31(G)2(M'((L$`4&)!!-!N`````!$B<#!
-MX!")QD0)QDB+1R")-`%(BT<@BQ0!N``````Y\G5M0?_`08'X_P```'[20;@`
-M````1(G)26/`BW2$$$B+1R")-`%(BT<@BQ0!N``````YUG4Z0?_`08/X`W[9
-M26/"2,'@`HL,`TB+5R!!BP0#B0010?_"08/Z`0^.8?___[]D````Z`````"X
-M`0```$B#Q"!;PXGP]L0!=`QFQP(X$V;'`=07ZQE`A/9Y&F:#OT(4````=!!F
-MQP(("6;'`:P*N`$```##N`````##N`$```##055!5%532(/L"$F)_4B)_4F)
-M_$B-GY`#``!F@[^X`P```74/2(U4)`2^$````.@`````QT,$`````&:#O3X4
-M````=!C'0P0!````9H.]+A0```!U!\=#!`,```!F@[U"%````'0$@TL$!&;'
-M0Q`("6;'0Q*L"F;'0PPX$V;'0P[4%X`+`P^V0P*#R`-FQT,("@!FQT,*@`"#
-MX)^(0P)F@[TR%````'0I28V4)``4``"^#P```$R)[^@`````A<!T$$''A"0$
-M%````0```(!+`H#'0Q0-````0<>$)"`4```!````N`$```!(@\0(6UU!7$%=
-MPY"0D$B+5R"+1@2)@BB```!(BU<@BT8,B8(L@```2(M7((M&$(F",(```$B+
-M5R"+1@B)@C2```!(BU<@BP:)@B"```##2(/L*(ET)`2+AXP#``"#^`%T#X/X
-M`7(<@_@&=!>#^`AU,,=$)`S__P``QT0D$/__!P#K'HGP*P4`````P>`#B40D
-M#(GP*P4`````P>`#B40D$(U&`8E$)`B)T"7__X`!B00D2(GFZ`````!(@\0H
-MPTB+1R#'@"B`````````2(M7((N"!(````T```0`)?__S_^)@@2```!(BT<@
-MQX`@@```__\``,-)B?AF@WX2`'1#2(M7((N"!(````T``!``B8($@```2(M7
-M(`^W1A")@B2```!(BU<@#[=&$HF".(```$B+5R"+1A3!X`.)@C"```#K%4B+
-M5R"+@@2````E___O_XF"!(```$B+5R"+!HF"*(```$B+3R"+@2"````E``"`
-M_P^W5@@)PF:#?A@`=!$/MT88@\`$P>`0)0``?P`)PHF1((```$&+D)0P```P
-M]@^W1AK!X`@E`/\```G"08F0E#```$B+1R")D!B```!(BT\@BY$$0```9KH`
-M`(M&'(/H`\'@`R7__P``"<*)D01```##D)!(BT<@BX`(0```A<`/E<`/ML##
-M2(M'((N0P````(/Z_W4,QP8`````N`````##B=`ENM@%`8D&]\(```@`=`<-
-M````0(D&]L(%=`.##@'WPL`%``!T`X,.0/;"('0/@[\@%````'0&@0X```!`
-M]D8#0'1&B9<(%```2(M7((N"Q````(F'#!0``(N"R````(F'$!0``(N"S```
-M`(F'%!0``(N"T````(F'&!0``(N"U````(F''!0``+@!````PXN'_"T``,-(
-MB?E$BX?\+0``187`>1)(BT<@QT`D`````$B+1R"+0"2)\H'BNM@%`4#VQD!T
-M,(.Y`"X```!T`X/*0(.Y!"X```!T`X#.`8.Y""X```!T`X#*@(.Y#"X```!T
-M`X#.!(G0@\@'0/;&`0]%T(G0#0``"`#WQ@```$`/1=!(BT<@B9"@````B;'\
-M+0``A?9Y"TB+1R#'0"0!````1(G`P[B`````PXGP9H/^?W<>2,'@!27@_Q\`
-M2(M7((N$$!R(``"Z`0```&:%P'@%N@````")T,.)\K@`````9H/^?P^'AP``
-M`$C!X@6!XN#_'P!(BT<@QX0"`(@```````!(BT<@QX0"!(@```````!(BT<@
-MQX0""(@```````!(BT<@QX0"#(@```````!(BT<@QX0"$(@```````!(BT<@
-MQX0"%(@```````!(BT<@QX0"&(@```````!(BT<@QX0"'(@```````"X`0``
-M`,.X`````&:#_G]W>TB%TG0]1`^V0@5!P>`(#[9"!$$)P`^V2@/!X1@/MD("
-MP>`0"<$/MD(!P>`("<$/M@()P='I1(G`P>`?"<%!T>CK"T&X`````+D`````
-M2(GR2,'B!8'BX/\?`$B+1R")C`(8B```2(M/($2)P(#,@(F$"AR(``"X`0``
-M`,-!54%455-(@^P(28G128G,B?5%A<"Z`````+BJJJJJB<8/1/*X`````&:#
-M_7\/AWD!``!!#[8!@_@!=!*#^`%_!H7`=!'K1X/X!70ZZT!!O04```#K0F9!
-M@WD"!'8P9D&#>0(%=PA!O0````#K*F9!@WD"#7<(0;T!````ZQI!O0,```#K
-M$D&]!P```.L*N`````#I%`$``$4/MED$00^V007!X`A!"<-!#[9!!L'@$$$)
-MPT$/MD$'P>`800G#03'S00^V00G!X`A!#[91"(G3"<,Q\X'C__\``$4/ME$*
-M00^V00O!X`A!"<)!#[9!#,'@$$$)PD$/MD$-P>`800G"03'R00^V00_!X`A!
-M#[91#HG1"<$Q\8'A__\``$4/MD$000^V01'!X`A!"<!!#[9!$L'@$$$)P$$/
-MMD$3P>`800G`03'P9D&#>0(-=P=!@>#_````#[?UB?#!X`5(F$B+5R!$B9P0
-M`(@``$B+5R")G!`$B```2(M7($2)E!`(B```2(M7((F,$`R(``!(BU<@1(F$
-M$!"(``!(BU<@1(FL$!2(``!,B>+H`````$B#Q`A;74%<05W#D$B#[`A(B?!(
-MC;?P+0``N@8```!(B<?H`````$B#Q`C#2(/L"$B!Q_`M``"Z!@```.@`````
-MN`$```!(@\0(PTB#[`A(B?>Z!@```$C'Q@````#H`````$B#Q`C#N`````##
-M2(/L&$B)7"0(2(EL)!!(B?M(B=5(BT<@B;``8```2(M'(,>`"&````$```"Y
-M`@```+H#````O@Q@``#H`````+H`````A<!T$TB+0R"+@`1@``!FB44`N@$`
-M``")T$B+7"0(2(ML)!!(@\08PV8YM[@#``!U![@,````ZQ2`ORH4````#YC`
-M#[;`C03%`P```$B%TG0"B0*X`````,.X`````&:#OSX4````=!2X`0```&:#
-MORX4````=06X0P```&:#OT(4````=`.#R`3#2(/L&$B)'"1,B60D"$R);"00
-M28G]#[>?`!0``$&)W$&#Y!Q!P?P"@^,"T?M$B>;H`````$F+52"+@@"8``"`
-MS"")@@"8``!$B>9,B>_H`````#G8#Y7"#[;21(GF3(GOZ`````!(BQPD3(MD
-M)`A,BVPD$$B#Q!C#2(M_((N7%$```(T,-K@#````T^`)PHF7%$```+@!````
-MPTB+?R"+EQ1```"-##:X`P```-/@]]`APHF7%$```+@!````PTB+?R!$BX<8
-M0```N/[___^)\=/`02'`@^(!T^)!"=!$B8<80```N`$```##B?&X_____X/^
-M!7<22(M'((N`'$```(/@+]/H@^`!PTB#[`A(BT<@BX`40```)?Q__O^`S(")
-MP8')```!`(72#T7!2(M7((F"%$```(NW_"T``('.`````>@`````2(/$",-(
-MBU<@BX(00```)9__\?^#Y@<+!+4`````B8(00```PTB#[!A(B5PD"$B);"00
-M2(G[B=5(C;_V+0``N@8```#H`````$B+2R`/MI/V+0``#[:#]RT``,'@"`G"
-M#[:#^"T``,'@$`G"#[:#^2T``,'@&`G"B9$(@```2(M+(`^V@_LM``#!X`@/
-MMI/Z+0``"<*)Z"7_/P``P>`0"<*)D0R```!(BUPD"$B+;"002(/$&,-(BU<@
-MB[),@```BX)0@```BY),@```C4@!.?(/0L%(P>`@B=)("=##2(M'((N`3(``
-M`,-(BU<@BX(@@```#0````&)@B"```##2(M'((N`9)@``(G!P>D3@>'_`0``
-M]L4!=`:!\0#^__](BU<@BX)0@```BY),@```,=`QR,-(BT<@BX`@0```)?\`
-M``")PH/B#[D`````P>@$.8=\`P``=0YF.9>``P``=06Y`0```(G(PTB+1R"+
-M@)"````!!DB+1R"+@(R````!1@1(BT<@BX"4@````48,2(M'((N`B(````%&
-M"$B+1R"+@)B````!1A##2(/L&$B)'"1(B6PD"$R)9"002(G]B?-)B?R#_@AV
-M#K[__P``Z``````YPW8/08F<))@P``"X`````.L?B=Y(B>_H`````$B+52")
-M@G`0``")G9@P``"X`0```$B+'"1(BVPD"$R+9"002(/$&,-(@^P(2(M'((NP
-M<!```('F__\``.@`````2(/$",-(@^PH2(D<)$B);"0(3(ED)!!,B6PD&$R)
-M="0@2(G]08GVOO\?``#H`````$$YQG81QX6<,```_____[@`````ZSA,BV4@
-M08N<)!2```"!XP#@__]$B?9(B>_H`````"7_'P``"<-!B9PD%(```$2)M9PP
-M``"X`0```$B+'"1(BVPD"$R+9"003(ML)!A,BW0D($B#Q"C#2(/L"$B+1R"+
-ML!2```"!YO\?``#H`````$B#Q`C##[:'CS```(/P`8/@`<.%]G0A2(M7((N"
-M!(```"7____^B8($@```@:>,,```_____NL?2(M7((N"!(````T````!B8($
-M@```@8^,,````````;@!````PTB#["A(B1PD2(EL)`A,B60D$$R);"083(ET
-M)"!(B?U!B?:^_Q\``.@`````03G&=A''A:`P``#_____N`````#K.TR+92!!
-MBYPD%(```('C__\`X$2)]DB)[^@`````P>`0)0``_Q\)PT&)G"04@```1(FU
-MH#```+@!````2(L<)$B+;"0(3(MD)!!,BVPD&$R+="0@2(/$*,-(@^P(2(M'
-M((NP%(```('F``#_'\'N$.@`````2(/$",.X`0```,/#N`````##P\-(BT<@
-MBX`<G```)?\```##2(M'((N`6(```(/@!\-(BT<@@^8'B;!8@```PXN'<#``
-M`,-(@^P(2(N7Z!,``$B%TG4-B;=P,```N`$```#K!>@`````2(/$",-(@^P(
-M@_X!=1:#^@%V"K@-````@_H%=0RX`````.L%Z`````!(@\0(PTB#[`B#_@MU
-M'(G*@^(&B9>H`P``2(M'((F02(```+@!````ZP7H`````$B#Q`C#2(/L".@`
-M````A<`/E<`/ML!(@\0(PY"0D%532(/L"$B)^X7V=&5(BU<@BX($0```)?__
-M_/^)@@1```"_"@```.@`````O0H```!(BT,@BX`00```J0```0!T);_(````
-MZ`````!(BU,@BX($0```)?___/^)@@1```#_S77,ZP2%[74'N`````#K&DB+
-M4R"+@@2````E___[_XF"!(```+@!````2(/$"%M=PTB+5R"+@@2````-```$
-M`(F"!(```(7V=!5(BU<@BX($0```)?___/^)@@1```##2(M7((N"!(````T`
-M``0`B8($@```A?9T%4B+5R"+@@1````E___\_XF"!$```,-(@^P82(D<)$B)
-M;"0(3(ED)!")\TB)_4&\`0```(/^`708@_X!<@>#_@)T%^L>B=;HVO[__T&)
-MQ.L9B=;H8?___^L0B=;HA____^L'N`````#K"8F=;#```$2)X$B+'"1(BVPD
-M"$R+9"002(/$&,-(BT<@BX`$0```)0```P#!Z!##D%.#_@)T)8/^`G<'@_X!
-M=`GK(H/^!'0+ZQM(Q\,`````ZQE(Q\,`````ZQ!(Q\,`````ZP>X`````.L+
-M2(G>Z`````!(B=A;PTB+1R"+0`S#2(M'((EP#,-(BT<@QT`(!````,-(@^P(
-M2(M'(,=`""````"Y`````+H$````O@@```#H`````(7`#Y7`#[;`2(/$",-(
-MBU<@BX)(@```@^#?B8)(@```PTB+5R"+@DB```"#R"")@DB```##2(M'((FP
-M0(```$B+1R")D$2```##N`````"#_C]W1X/^'W8@2(M7($2+@D2```"-3N"X
-M_O___]/`1"'`B8)$@```ZQU(BU<@1(N"0(```+C^____B?'3P$0AP(F"0(``
-M`+@!````P[@`````@_X_=T>#_A]V($B+5R!$BX)$@```C4[@N`$```#3X$0)
-MP(F"1(```.L=2(M'($2+@$"```"Z`0```(GQT^)$"<*)D$"```"X`0```,-(
-MBT<@BX`\@```PTB+1R")L#R```##QT8(`````(G0)?\/``")1@PYT'0&N```
-M``##]L$@=`>!3@P`(```QT84`````,=&$`````"X`0```,/V1A0!=0JY#P``
-M`.G(````]D$4`7442(M'((M`#+D/````.=`/A*X````/MT809B7_#V9!B0&+
-M1A0E`(#_#\'H#V9!B4$"0<9!!`"+1A2H`G4LJ`1T!T'&000!ZR'V1A00=`=!
-M@$D$".L408!)!`*+1A0EX````,'H!4&(006+1A`E``#X!\'H$T&(00:+1A3V
-MQ`%T#B4`?@``P>@)08A!!^L%0<9!!_^+1A`E`(`'`,'H#T&(00B+1A`E````
-M.,'H&T&(00F+1A#!Z`R#X`%!B$$*N0````")R,.0D)!!5T%6055!5%532(/L
-M>$B)_4&)]DB)TT&)S4R)1"0X28G\9L=$)!X``$&_`````,=$)!@`````QT0D
-M%``````/MT("]L0!=`>I@````.L,#[="`L'H!X/P`:@!=5(/MT,"J"!T!*A`
-MZPP/MT,"P>@&@_`!J`%U.$B)WDB)[^@`````2(E$)"BZ#````$B%P`^$ZP<`
-M`$&#_@9T'D&#_@9W"$&#_@%W".L008/^"'0*N@P```#IQP<``$6%[71P2(M%
-M((N03(```(E4)!B+B%"```")3"04@[U\`P```W8,BX!`$0``B40D0.L@OP``
-M``!(BTT@B?B-%+U`$0``BQ0*B52$0/_'@_\)=NE(BT0D*/9`!`)U!(!@!/Y(
-MBU0D*`^W0@)FB4,"#[9"!(A#!$B+12"+@%B```")1"00A<"X`0````]%1"00
-MB40D$$B+52"+@@2````E`````HE$)""+@A!````E8`#^`(E$)"2+BA1```")
-M3"0TBY(80```B50D,`^W<P)(B>_H`````+H#````A<`/A.4&```/MT,")?`!
-M```]P````'1!/<````!_"3V@````="KK/CU``0``=`D]4`$``'0+ZRYFQT0D
-M'@$`ZP=FQT0D'@(`0;\!````ZQ9FQT0D'@,`ZP=FQT0D'@0`0;\"````@[U\
-M`P```W802(M%(,>``)@```<```#K#DB+12#'@`"8``!'````@[U\`P```P^&
-M\P```(![`@`/B;H```!F08&\)"@4````,`^&J0```/9#`B!T'$$/MX0D)!4`
-M`(E$)`Q!#[>4)"@5``")5"0(ZQI!#[>,)"85``")3"0,00^WA"0J%0``B40D
-M"+X#````BWPD#.@`````B40D#+X#````BWPD".@`````B40D"$$/M_=(Q\$`
-M````BQ2Q@.(_BT0D#,'@!B7`````"<*)%+%(Q\<`````BPRW@^'PBU0D#,'J
-M`H/B`8M$)`@!P(/@#@G""=&)#+>_`````$G'P`````!!#[?WB?A(C01`08L,
-M@$B+52!(`?!!BP2`B001_\>#_QMVX4B)WDB)[^C$#```OP````!)Q\``````
-M2`^W="0>B?A(C02`08L,@$B+52!(`?!!BP2`B001_\>#_R)VX;\`````2<?`
-M`````$$/M_>)^$B-!$!!BPR`2(M5($@!\$&+!(")!!'_QX/_/W;AOP````!(
-MQ\8`````2<?``````(GXBQ3&187M=`V-@@"`__\]_P\``'8/B=%(BU4@B?A!
-MBP3`B001_\>!_ZH```!VT(.]?`,```-W1DB+52"+@AR````E__\/``T``-`!
-MB8(<@```2(M%(,=`7`````!(BT4@QX!XF```"````$B+52"+@DB```"`S`2)
-M@DB```!%A>UT54B+12"+5"08B9!,@```2(M%((M,)!2)B%"```"#O7P#```#
-M=A!(BU4@BT0D0(F"0!$``.L@OP````"-#+U`$0``2(M5((GXBT2$0(D$$?_'
-M@_\)=N5(BTT@00^VE"3P+0``00^VA"3Q+0``P>`("<)!#[:$)/(M``#!X!`)
-MPD$/MH0D\RT``,'@&`G"B9$`@```2(M-($$/MI0D]2T``,'B"$$/MH0D]"T`
-M``G0"T0D((F!!(```$2)]DB)[^AJ(0``2(M5((N"$$````M$)"2)@A!```!(
-MBT4@BU0D-(F0%$```$B+12"+3"0PB8@80```2(M%((M4)!")D%B```!(BTT@
-M00^VE"3V+0``00^VA"3W+0``P>`("<)!#[:$)/@M``#!X!`)PD$/MH0D^2T`
-M`,'@&`G"B9$(@```2(M-($$/MI0D^RT``,'B"$$/MH0D^BT```G0B8$,@```
-M2(M5($&+A"24,```B8(8@```2(M%(,>`@````/____^#O7P#```$=1=F@[V`
-M`P```7<-2(M5((M"%(#,!(E"%$B)WDB)[^@`````N@,```"%P`^$J`(``$&#
-M_@9T*(N%M`,``*@#=!Y(BTT@BY%$F0``@>+____?@^`!P>`="<*)D429``!(
-MB=Y(B>_H,PX``$B+="0H2(GOZ%\&``"Z`P```(7`#X15`@``9H&]>`,``!OQ
-M=12`>P(`>0Y(BT4@QX`(V````@4``$B+12#'@!R8```!````2(M%((N`%)D`
-M`"7_/P``]D,"('07P>`"B<"ZHXLNND@/K\)(P>@@P>@$ZQ*)P+K-S,S,2`^O
-MPDC!Z"#!Z`.->&3H`````$B+52"+@F"8``"#R`&)@F"8``"Y`````+H!````
-MOF"8``!(B>_H`````$B+="0H2(GOZ`````"%P'45]D,"('4%9H-+`@*Z`P``
-M`.F2`0``08.\)'0P````=!I(BT4@QX`@F0```/`!`$''A"1X,````0```+L`
-M````O@$```"-!)T`````2)A(BWT@B?*)V=/BB90X`!```/_#@_L)?M^[````
-M`(G>2(GOZ`````#_PX/["7[O2(M%(,>`I`````$``0!(BT4@QX"H`````0``
-M`$B+12#'@*P````!````2(M5((N"L!```(F"L!```$B+12#'@*````!E"0@`
-M0<>$)/PM``!E"0@`2(M5((N"K`````T```<`B8*L````08/^!G4?2(M5((N"
-MH````(#,$(F"H````$&!C"3\+0```!```(.]!!0```!T"$B)[^@`````2(M5
-M((N"((```"7__W_^B8(@@```08.\))@P``#_=!!!B[0DF#```$B)[^@`````
-M08.\))PP``#_=!!!B[0DG#```$B)[^@`````08.\)*`P``#_=!!!B[0DH#``
-M`$B)[^@`````@[VH`P```'002(M5((N%J`,``(F"2(```$2)M8P#``"X`0``
-M`.L12(M$)#B#.`!T`HD0N`````!(@\1X6UU!7$%=05Y!7\-(@^P(O@(```#H
-M5@,``$B#Q`C#4TB)^[H!````O@````#H`````+H`````A<!T);X3````2(G?
-MZ"@#``"Z`````(7`=`^_-`@``.@`````N@$```")T%O#2(/L&$B)7"0(2(EL
-M)!!(B?N)];H!````O@````#H`````+H`````A<`/A&D!``")Z"7P`0``/<``
-M``!T?3W`````?Q,]H````'0V/;````!T+^GW````/4`!```/A)@````]0`$`
-M`'\,/=````!T2NG9````/5`!``!T?NG-````2(M#(,>`!)@```````!(BT,@
-MQX``H@```P```$B+0R#'@'R8```9````ORP!``#H`````.F4````2(M#(,>`
-M!)@```````!F@[MX`P``$G5\2(M#(,>`?)@``!@```"_+`$``.@`````2(M#
-M(,>``*(```(```#K5$#VQ1!T$$B+0R#'@`28```#````ZPY(BT,@QX`$F```
-M`````&:#NW@#```2=29(BT,@QX!\F```&````+\L`0``Z`````!(BT,@QX``
-MH@```````+X3````2(G?Z+$!``"Z`````(7`=#2_-`@``.@`````N@$```"^
-M`````$B)W^@`````N@````"%P'0/O@````!(B=_H=@$``(G"B=!(BUPD"$B+
-M;"002(/$&,-(@^PH2(D<)$B);"0(3(ED)!!,B6PD&$R)="0@2(G[28GU28G6
-M28G\Z`````!(B<6X`````$B%[0^$"`$``(.[>#`````/A(0```!(BT,@BX`@
-MF0``J0```0!U<\>#>#````````!(BW,@B[X0G```BX84G```1(N&&)P``(GZ
-MT>J)P='I`<J)P<'I!L'J!W0^A<ET.D6)P4'WV42)R$&)T)E!]_A!B<%!@^$_
-MB?B9]_F)P8/A'T2)R,'@!8N6()D```G0"<B`S`B)AB"9``!(B>Y(B=_H$P,`
-M`(7`=0UF08--`@)F@V4"_>LU2(GN2(G?Z`````"%P'4MOX@3``#H`````$B)
-M[DB)W^@`````A<!U%$'V10(@=09F08--`@*X`````.L?2(G?Z#\8``!!@[PD
-M>#`````/E,`/ML!!B0:X`0```$B+'"1(BVPD"$R+9"003(ML)!A,BW0D($B#
-MQ"C#2(/L&$B)'"1(B6PD"$R)9"0028G\B?.%]KC_____B<4/1>Y(BT<@BU`,
-MB;``0```OP\```#H`````(/C`XGJ@^(#B=F^`$```$R)Y^@`````B<+VPP%U
-M#$F+1"0@QT`4`````(G02(L<)$B+;"0(3(MD)!!(@\08PT%505154TB#[`A)
-MB?U)B?0/MU8"#[<VZ`````!!@'PD`@!Y-4@/O]A(C01;2(T<A0````"+>P2^
-M"````.@`````B<6!Y?\```#!Y06+`\'@!`G%#[=#".L%O0````!F/9``?P2H
-M`70?#[_X@^\8O@@```#H`````(G&@>;_````N`$```#K)@^_^(/O&(GXP>@?
-M`<?1_[X(````Z`````")QH'F_P```+@`````P>8"`<`)QH'.`00``$F+32!`
-M#[;%P>`(0`^VU@G0B8&<F```28M-((GH)0#_``!(B?,/MM<)T(F!T)@``$V)
-MI>@3``"X`0```$B#Q`A;74%<05W#2(M'((N`9)@``,'H$V8E_P'VQ`%T!&8U
-M`/Z8PT%455-(B?V)]TB+=2"+CF28``"!X0#P__^)^,'@"24`#@``"<&!XO\!
-M```)T8F.9)@``$B+52"+@F"8``"#R`*)@F"8``!!O#@```!`A/]T%D0/MN="
-MC03E`````$0IX$&)Q$'!Y`F[`````$B+12"+@&"8``"H`G011(GGZ`````#_
-MPX/[.W[CZP6#^SM^![@`````ZPE(B>_H1?___YA;74%<PP^W1@(EX`$``#W`
-M````="D]P````'\)/:````!T$NLI/4`!``!U(@^WAX04``#K$`^WAX84``#K
-M!P^WAX@4``!FB0*X`0```,.X`````,-(@^P82(E<)`A(B6PD$$B)^TB)]4B-
-M5"0&Z)/___^Z`````(7`="U(BT,@BX!@F```2(G?Z+?^__]F.T0D!GX%9H--
-M`@)FB4469CM$)`8/GL`/MM")T$B+7"0(2(ML)!!(@\08PTB#["A(B5PD$$B)
-M;"083(ED)"!(B?M(B?6#OWP#```#=V?H`````(7`=%Y(C50D#DB)[DB)W^@1
-M____N@````"%P'1=0;P`````26/$#[:P`````+H`````2(G?Z$;^__]F.T0D
-M#GX(9L=%%@``ZP1FB4460?_$08/\`G;-08/\`P^6P`^VT.L82(M3((N"8)@`
-M`(/(`HF"8)@``+H!````B=!(BUPD$$B+;"083(MD)"!(@\0HP[H`````2,?'
-M``````^W!HG!9CL%`````'<+_\)(8\)F.PR'=O5(8\(/MQ2%``````^_PFG`
-M5E4``,'H$&;!^@]F*="8PT%7059!54%455-(@^Q(2(E\)#A(B?V`?@(`N`$`
-M``"Z`@```(G1#TG(9HD,)`^W1@(EX`$``#W`````#X1\`0``/<````!_$#V@
-M````#X0T`0``Z:,!```]0`$```^%F`$```^W!F8MH0]F/>H$=Q4/MY\,%0``
-M9HE<)!X/MX<.%0``ZV@/MP9F+8P49CWO`'<:#[>/$!4``&:)3"0>#[>?$A4`
-M`&:)7"0<ZU8/MP9F+7P59CW@`'<:#[>'%!4``&:)1"0>#[>/%A4``&:)3"0<
-MZR]F@3Y<%G8:#[>?&!4``&:)7"0>#[>'&A4``&:)1"0<ZPYFQT0D'```9L=$
-M)!X``$0/M[60%```#[>-EA0``&:)3"0@9H.]EA0````/E,!F1`^V^$@/MPPD
-M2,?&`````(L4CH'B____[P^WA805``#!X!P)PHD4CDC'Q@````"+%(Z!XO__
-M__L/MX6&%0``P>`:"<*)%(Y(Q\8`````BQ2.@^+W#[>%@A4``,'@`PG"B12.
-MZWX/MY\<%0``9HE<)!X/MX<>%0``9HE$)!Q$#[>WDA0```^WCY@4``!FB4PD
-M(&:#OY@4````ZS0/MY\@%0``9HE<)!X/MX<B%0``9HE$)!Q$#[>WE!0```^W
-MCYH4``!FB4PD(&:#OYH4````#Y3`9D0/MOCK"K@`````Z3(!``!,#[<D)$G'
-MQ0````!#BURE`(#C/T4/M_:^!````$2)]^@`````P>`'00^WU\'B!@G0)<``
-M```)PT.)7*4`2<?%`````$.+7*4`@^/XO@0```!$B??H`````-'H@^`'"<-#
-MB5RE`(#C?T0/MW0D'KX#````1(GWZ`````#!X`<E@`````G#0XE<I0!)Q\4`
-M````0XM<I0"#X_R^`P```$2)]^@`````T>B#X`,)PT.)7*4`@^/C#[=\)!R^
-M`P```.@`````P>`"@^`<"<-#B5RE`$C'P0````!"BQ2A@^+WBT0D(,'@`X/@
-M"`G"0HD4H;X`````2,?'`````$P/MR0D2&/&2(T$0(L,ATB+7"0X2(M3($P!
-MX(L$AXD$$?_&@_X8=MW'A80P````````N`$```!(@\1(6UU!7$%=05Y!7\-)
-MB?D/MT(")>`!```]P````'0K/<````!_##V@````=!;IP0```+H`````/4`!
-M``!T$>FP````N@$```#K!;H"````2&/210^WA%&B%```00^WA%&H%```P>`&
-M00G`00^WA%&N%```P>`,00G`00^WA%&T%```P>`200G`00^WA%&Z%```P>`8
-M00G`00^WC%'`%```00^WA%'&%```P>`&"<%!#[>$4<P4``#!X`P)P4$/MX11
-MTA0``,'@$@G!00^WA%'8%```P>`8"<&#_@%T#(/^`7(7@_X"=`?K"D2)P>L+
-M08G(ZP:X`````,-!B;%P,```2(M'($2)@&"9``!(BT<@B8ADF0``N`$```##
-M059!54%455-(B?U)B?5)B?P/MT8")>`!```]P````'1)/<````!_"3V@````
-M=#/K03U``0``=3I!O@````!(BT\@BY%$F0``@^+'#[>'B!4``,'@`X/@.`G"
-MB9%$F0``ZQI!O@$```#K$D&^`@```.L*N`````#IYP$``(.]?`,```-W%4B+
-M52"+@A"9``"#R`.)@A"9``#K6$B+32"+D1"9``"!X@;\__])8]Y!#[>$7)P4
-M``#!X`0)PH/*`8F1$)D``$&+M"1P,```3(GJ2(GOZ`````!(BU4@00^_A%R$
-M%```)?\!``"`S`*)@FB9``!(BTT@BY%$F```@>)_P/__26/V00^WA'1:%```
-MP>`')8`_```)PHF11)@``$B+32"+D4B8``"!XO\/_/]!#[>$=&`4``#!X`PE
-M`/`#``G"B9%(F```2(M-((N14)@``&:Z``!!#[Z$-($4``#!X`@E`/\```G"
-M00^VA#1^%```"<*)D5"8``!(BWT@00^WE'1R%```B=#!X!C!XA`)T$$/MXQT
-M>!0``(G*P>(("=`)R(F'-)@``$B+32"+D2B8```P]D$/MX1T9A0``,'@"`G"
-MB9$HF```2(M-((N19)@``('B_P_X_T$/MX1T;!0``,'@#"4`\`<`"<*)D628
-M``"^`@```&9!@;PD*!0```(P=QEF@;UZ`P``(A!U,T'V10)`="R^"````.LE
-M00^W10"#X!\/M\"%P'06@^@*@_@,=@Y)8\9!#[>$1-X4```!QDB+32"+D229
-M``"`X@&-!#8E]P````G"B9$DF0``N`$```!;74%<05U!7L.#_D"X/P````]"
-MQF:)AZP#``!(BT<@B;`\F0``N`$```##05=!5D%505154TB#["A)B?Q(B?5(
-MB?L/MT8")>`!```]P````'15/<````!_##V@````='OIJ@```#U``0``#X6?
-M````#[>'GA4``&:)1"0(2(V'BA4``$B)!"1(C8>@%0``2(E$)!!$#[>W`AD`
-M`$R-KP09``#I@P````^WAZ@7``!FB40D"$B-AZH7``!(B00D2(V'RA<``$B)
-M1"001`^WMU09``!,C:]6&0``ZT\/MX>H%P``9HE$)`A(C8>P%P``2(D$)$B-
-MAV88``!(B40D$$0/M[=T&0``3(VO=AD``.L;N`````#I@P```$B)T$C!X`9,
-MC;P8C!D``.M8#[=5`$B)YDR)Y^AR````0;\`````2(GN3(GGZ`````")Q[D`
-M````9H.[+!4```!T)P^WLRP5``!(8]%F@[Q3+A4```!T#`^WA%,N%0``.?AT
-MG?_!.?%\X$$/M\Y)B>A,B>I,B?Y,B>?H9@,``+@!````2(/$*%M=05Q!74%>
-M05_#05=!5D%505154TB#[!A(B7PD$$F)]T&)U6;'1"0.``!FQT0D##\`O@@!
-M``!(Q\<`````Z`````"^@````$C'QP````#H`````$G'Q@````!)Q\0`````
-MNP$```"]``````^WQ69!B1Q&_\/_Q6:#^S]V[F:)+0````!FQP4``````0!F
-MQP4`````/P"]`````&8[+0````!S)`^WW4$/MS1>3(GZ00^W_>C_!@``9D&)
-M!%S_Q68[+0````!RW$$/MS0D2`^W!0````!!#[=\1/Z]`````&8[+0````!S
-M>0^WQ69!.S1$?`I!#[<T1&:);"0.B>CWT(G#9@,=`````'0F#[?300^W1%3^
-M9D$[!%1^"T$/MP149D&)1%3^_\5F.RT`````<K>]`````&8[+0````!S(@^W
-M#0`````/M\5F03L\1'T*00^W/$1FB6PD#/_%9CG-<N4/O]:#PAE(8\)(:<`?
-MA>M12,'H(,'X!,'Z'RG0:^@R0;T`````NP`````/O]6)UDACPDAIP!^%ZU%(
-MP>@@P?@$P?H?*=#_P(7`?CI(Q\$`````2&/&2&G`'X7K44C!Z"")Q\'_!(GX
-M*="-4`%!#[?%#[=T)`YFB31!0?_%_\,/M\,YT'SGNP````!(#[<%`````$B)
-MPF9!.VQ$_@^-R@```(/%,DB)UV9!.VQ4_GU1#[_-B<X/M]-!#[\$5$&)R$$I
-MP$2)P$$/OU14`BG1#Z_!A<!^+/_#9D$[;'S^?2(/M]-!#[\$5(GQ*<&)R$$/
-MOU14`D&)\$$IT$$/K\"%P'_4#[?#10^W1$8"10'`10^WP$$/MPQ&`<D/M\E!
-M#[=41`)!#[<T1`^W_4&Y`````.CT!@``_\!!#[?52,?!`````&;1Z&:)!%&+
-M="0,9CGP=@1FB3110?_%2`^W%0````!F03ML5/X/C#;___]F08/]/W<G2,?&
-M`````$BY``````````!!#[?5#[<$46:)!%9!_\5F08/]/W;JOH"A``"[````
-M`$G'P`````!(Q\<`````#[?#00^W%(#!XAB!R@``_P`/MP2'P>`(#/\E__\`
-M``G"B?%(BVPD$$B+12")%`&#Q@3_PV:#^Q]VQDB#Q!A;74%<05U!7D%?PT%7
-M059!54%455-(@^QH2(E\)$!)B?1)B=9,B<5!B<](B7PD.&;'1"0V``!FQT0D
-M-```9L=$)#(``&;'1"0P``!FQT0D+C\`9L=$)!```$G'Q0````!!#[Y`!0'`
-M9HE$)"I!]D`#`703#[:'1A0``.L69HE<)#+I,@$``$B+5"0X#[:"1Q0```^^
-MT$B)[DB+?"1`Z`````"(1"0/387D#X2/````NP`````/M]-F08,\U`!T$D$/
-MMP349HE$5%#_PV:#^P=VXV:)7"0L#[?32(UT)%`/MWT`3(U$)$Y(C4PD3.CL
-M!0``NP````!F.UPD+',7BU0D3`^WPV8[5$10=`G_PV8[7"0L<NV+1"1,9CM$
-M)$YU!F8[10!T"P^WPT&#?,0$`'0.#[?#00^W1,0"9HE$)"Z[`````&9$.?MS
-M&@^WPTB-%(!!#[=45@AFB51$4/_#9D0Y^W+F00^WUTB-="10#[=]`$R-1"1.
-M2(U,)$SH7@4``+L`````9D0Y^W,NBTPD3`^W5"1.#[?#9CM,1%!U!6:)7"0V
-M#[?#9CM41%`/A,S^____PV9$.?MRV[L`````]D4"0'0A9H/[!'8P9H/[!711
-M9H/[!G1R9H/[!P^%MP```.F*````#[?#@_@'#X>F````B<#_),4`````2`^W
-M1"0V2(T$@$$/MT1&!F:)1"0T2`^W1"0R2(T$@$$/MT1&!NMQ2`^W1"0V2(T$
-M@$$/MT1&!&:)1"0T2`^W1"0R2(T$@$$/MT1&!.M*2`^W1"0V2(T$@$$/MT1&
-M`F:)1"0T2`^W1"0R2(T$@$$/MT1&`NLC2`^W1"0V2(T$@$$/MP1&9HE$)#1(
-M#[=$)#)(C02`00^W!$9FB40D,$0/MT0D,`^W3"0T#[=4)$X/MW0D3`^W?0!!
-MN0````#H?@,``(G"#[=$)"YF.=`/1M#V10(0=!U(BTPD.&:!N2@4````,'8-
-M#[>!-A0``&8YT`]&T`^W\P^WR@^W1"0J#[Y4)`\IT#G(#T_!9D&)1'4`9H7;
-M=2U(BU0D0(N"L`,```^WA````````<!!#[=5`&8IPF:%TK@!````#T[09HE4
-M)!`/M\M!#[=430`/OT0D$#G0#T_"9D&)1$T`_\-F@_L'#X9?_O__00^W10!(
-MBTPD.(F!B#```$B+1"1`3(M((+X`````@^8!B?'!X1ZX/P```&9!(T4&P>`8
-MB<H)PD&)\$'!X!9$"<*X/P```&9!(T4$P>`0"<*)]\'G#@GZN#\```!F02-%
-M`@^WP,'@"`G"P>8&"?*X/P```&9!(T4`#[?`"<)!B9$TF0``2(M$)$!(BU`@
-MN#\```!F02-%#L'@&`G!1`G!N#\```!F02-%#,'@$`G!"?FX/P```&9!(T4*
-M#[?`P>`("<$)\;@_````9D$C10@/M\`)P8F*.)D``$$/MW4`2(M\)$#H````
-M`$$/MT4`2(M4)$!FB8*N`P``2(/$:%M=05Q!74%>05_#2(/L.$B)7"082(EL
-M)"!,B60D*$R);"0P2(G508G]B?,/M_8/M_](C4PD%NA"`0``A<!T"@^W1"06
-MZ1L!```/MU4(10^W[4R-1"042(U,)!)(BW4`1(GOZ!L"```/MW0D$@^WVTR-
-M1"002(U,)`Y(B>J)W^B<`@``#[=T)!1,C40D#$B-3"0*2(GJB=_H@P(```^W
-M="0.#[=\)!)(C4PD"$B)ZNC*````#[=T)!`/MWPD$DB-3"0&2(GJZ+,```!$
-M#[=$)`8/MTPD"`^W5"00#[=T)`Y!N0````")W^CQ````08G$#[=T)`H/MWPD
-M%$B-3"0(2(GJZ'<````/MW0D#`^W?"042(U,)`9(B>KH8````$0/MT0D!@^W
-M3"0(#[=4)`P/MW0D"D&Y`````(G?Z)X````/M\!!#[?,#[=4)!0/MW0D$D&Y
-M`````$&)P$2)[^A\````#[?`2(M<)!A(BVPD($R+9"0H3(ML)#!(@\0XPTR+
-M2A!!N@````!F1#M2"'-)9D$Y.74U38U!"+@`````9D$[009S)69!.3!U$@^W
-MP$$/MT1!'F:)`;@!````PTF#P`+_P&9!.T$&<MM)@\$T0?_"9D0[4@ARM[@`
-M````PU.)^T&)\D&)TXG.OV0````/M\%!#[?0#Z_"N@````"%P'1^187)N`$`
-M```/1?AF13G3=%\/M\-!#[?2*=!KR&1!#[?#*=")PHG(B=.9]_MFA<!Y!0^W
-MQNL*9H/X9'X/00^WP&O09$6%R0]$T.LP#[_(00^WP`^OP;ID````*<H/M\X/
-MK]$!T`^WUXG1F??YB<+K"XG*:\)D187)#T70#[?2B=!;PP^WPD0/MTQ&_@^W
-M_VO_9`^W!FO`9(/H"CG'<PL/MP9FB0$/MP;K)$$/M\%KP&2#P`HYQW8K9D2)
-M"69%B0C#0@^W!$YFB0%"#[<$3F9!B0##0@^W!$YFB0%"#[=$3@+KZT&Z````
-M`&:%TG0P#[?236/*0@^W!$YKP&0I^(/`"8/X$G:[0@^W1$X":\!D@^@*.<=R
-MO4'_PD$YTGS3D,-(@^P(08GR2(MR$$&Y``````^W0@B)PD$YP7T29D0Y%G0,
-M2(/&-$'_P4$YT7SN#[=6!DB#Q@@/M__H)?___TB#Q`C#2(V/T"T``(L%````
-M`(F'T"T``(G"2(T$U0````!(*=!(C02%`````$B)01C'010!````QT$,%```
-M`,=!$",```##2(N'Z!,``/9``B!T)D&Y`````+\<````N4````!!N'(```#'
-M1@P`````QT80=P```.LD0;D`````OS(```"Y`````$&X,@```,=&#!0```#'
-M1A`C````BU8$N`````!$.<IR!#GZ=@XYRG(%1#G"=@6X`0```,-(BU<@BX>(
-M,```P>`))0!^``"`S(")@C"9``#'AX0P```!````PTB#[!A(B1PD2(EL)`A,
-MB60D$$B)^TB-K]`M``"#?10`=0>X`````.MM@[^$,````75>2(M'((N`,)D`
-M`&:%P'A/P>@9B44$QX>$,````````$B)[N@*____A<!U,TB)[DB)W^A!````
-MA<!T)$B)[DB)W^A*````A<!^%4B)[DB)W^A1`0``QX.$,````@```(N#A#``
-M`$B+'"1(BVPD"$R+9"002(/$&,.X`````(M6!#M6#'8%.U80<@6X`0```,.#
-M?A0`=":+!DB-%,4`````2"G"2(T4E0````!(B588BT8$.T80<FF#/@!U!KC_
-M____PXM&!(E&"#M&$')-@SX`=$A)Q\``````2,?'`````/\.BP9(C13%````
-M`$@IPDC!X@)(BTX808M$$!`K00@!P(M.""G!B4X(2`'Z2(E6&#M.$'(%@SX`
-M=<:X`0```,.+1@0[1@QW>(L%`````/_(.09U!KC^____PXM&!(E&"#M&#'=5
-MBP4`````_\@Y!G-)2<?!`````$G'P`````")Q_\&BP9(C13%`````$@IPDC!
-MX@)(BTX808M$$1`K00@!P(M.""G!B4X(3`'"2(E6&#M.#'<$.3YRQ[@"````
-MP[@`````PX-^%`!T.TB+1A@/MP!FB8>(%0``2(M&&`^W0`)FB8>&%0``2(M&
-M&`^W0`1FB8>$%0``2(M&&`^W0`9FB8>"%0``PTB)^4B+1R"+@`2````E__\`
-M`(/^`70^@_X!?P:%]G0?D,.#_@9T!X/^"'0ID,-(BU<@"X>,,```#0``@0#K
-M#TB+5R`+AXPP```-``!"`(F"!(```,-(BU<@"X&,,```#0``(`#KZ$B#[`B+
-MMXP#``#HB____TB#Q`C#2(/L&$B)'"1(B6PD"$R)9"002(G]B?/H`````$&)
-MQ(G&@>;___]_2(GOZ`````!(BT4@BU`PB=:!YO`#``#![@2%VW0-N"4````I
-M\-'H`<;K&X/^`78$_\[K$D2)YDB)[^@`````N`````#K*4B+32"!X@_\__^)
-M\,'@!"7P`P``"<*)43!$B>9(B>_H`````+@!````2(L<)$B+;"0(3(MD)!!(
-M@\08PTB#[`BX`````(/^"7\:2&/&2(G&2,'F!$@IQDB-M+<4+@``Z`````!(
-M@\0(PTB#[`A)B="X`````(/^"7\=2&/&2(G"2,'B!$@IPDB-E)<4+@``3(G&
-MZ`````!(@\0(PTB#["A(B1PD2(EL)`A,B60D$$R);"083(ET)"!)B?R)]4F)
-MU4B)^8/^`G03@_X"=P>#_@%T&>M(@_X#=`KK04&^"0```.L>0;X(````ZQ9!
-MO@````"#OQ@N````=`>X`````.MR26/62(G02,'@!$@IT$B-G($4+@``@WL$
-M`'0'N/_____K4+X\````2(G?Z`````"):P1-A>UU*L=##`L```#'0Q0"````
-MQT,8_____\=#'/\#``!FQT,@"@!FQT,B"@#K#DR)ZD2)]DR)Y^@`````1(GP
-M2(L<)$B+;"0(3(MD)!!,BVPD&$R+="0@2(/$*,-(BT\@BY<`+@``@>+_`P``
-MBX<(+@``P>`0)0``_P,)PHF1I````$B+3R"+EP0N``"!XO\#``"+APPN``#!
-MX!`E``#_`PG"B9&H````2(M/((N!K````"4`_/__BY<0+@``@>+_`P``"=")
-M@:P```##2(/L"+@`````@_X)=UZ)\DB)T$C!X`1(*=!,C82'%"X``$&#>`0`
-M=0>X`````.L\0<=`!`````"X_O___XGQT\`AAP`N```AAP0N```AAP@N```A
-MAPPN```AAQ`N``!,B<;H*?___[@!````2(/$",-(@^P(28GY08GR28G[2(N/
-MZ!,``+@`````@_X)#X>>`P``B?)(B=!(P>`$2"G03(V$AQ0N``!!@W@$``^$
-M>@,``$&#>!C_=3-(A<ET%0^W00(EH````+H?````/:````!T!;H/````N`$`
-M```YT',/`<"#R`$YT'+WZP1!BT`80HT\E0````"-MT`0``!)BTD@B<*!XO\#
-M``!!BT`<P>`*)0#\#P`)PD&+0!3!X!0E``#P#PG"B10.C;>`$```28M)($$/
-MMT`BP>`$)?````!!#[=0((/B#PG0#0`@"`")!`Z-E\`)``!)BT$@QP0"``@`
-M`$&#N7P#```#=Q&-EP`1``!)BT$@QP0"`````4&#>"0`=$Q"C325`````(V^
-MP`@``$F+22!!BU`D@>+___\`08M`*,'@&`G"B10/@<;`"0``28M)((L$#HG"
-M@\H!08-X*`!T"(G"@<H!`0``B10.08-X,`!T'4*-#)4`"0``28M1($&+0#`E
-M____``T````!B00108-X+`!T/4*--)4`````C8[`$```28M1($&+0"PE__\/
-M``T``!``B0010?9`#"!T$XV.P`D``$F+42"+!!&`S`*)!!%!]D`.`7070HT,
-ME0`1``!)BU$@BP01#0``(`")!!%!]D`.@'050HT,E0`1``!)BU$@BP01@,P"
-MB00108M`!(/X`G0*@_@#=#?II@```$*-#)7`"0``28M1((L$$0RBB001N0``
-M)0!!@[E\`P```W<%N0``)0%"C125`!$``.MM0HTTE0````"-CL`)``!)BU$@
-MBP01#6("``")!!&+!0`````K!0````!!BY.0,```B=$IP2L-`````,'A"H'&
-M``D``$F+42")R`T````!B006N0``!`!!@[E\`P```W<%N0``!`%"C125P`D`
-M`$F+02")#`)!]D`X`7070HT,E0`1``!)BU$@BP01#0``)`")!!%!]D`,`703
-MN`$```!$B='3X$$)@P`N``#K$;C^____1(G1T\!!(8,`+@``0?9`#`%T$[@!
-M````1(G1T^!!"8,$+@``ZQ&X_O___T2)T=/`02&#!"X``$'V0`P"=!.X`0``
-M`$2)T=/@00F#""X``.L1N/[___]$B='3P$$A@P@N``!!]D`,!'03N`$```!$
-MB='3X$$)@PPN``#K$;C^____1(G1T\!!(8,,+@``0?9`#`AT$[@!````1(G1
-MT^!!"8,0+@``ZQ&X_O___T2)T=/`02&#$"X``$R)QDR)S^AD^___N`$```!(
-M@\0(PXTTM0`(``!(BT<@BP0&PXTTM0`(``!(BT<@B10&N`$```##B?%(BU<@
-MN`$```#3X(F"0`@``+@!````PXT$M0`*``!(BU<@BP00B<>#YP-U&;@!````
-MB?'3X(N20`@``(7"N`$````/1?B)^,-!5%532(G]08GT2(M7(+@!````B?'3
-MX(F"@`@``+L`````1(GF2(GOZ`````"%P'04OPH```#H`````/_#@?L/)P``
-M?MU(BT4@QX"`"````````('[#R<```^>P`^VP%M=05S#BWPD&(M,)"B!XO\/
-M``"+1"0(P>`2"<*+1"0@P>`9"<*)T`T````!]L$!#T3"B<*!R@```"#VP1`/
-M1-")T`T``$``]L$$#T3"B<*!R@``@`#VP2`/1<*)1@A$B<+!XAJ)T`T``(``
-M]L$"#T70B58,@___=!:)^,'@#24`X`\`"=")1@R!3@@```!`N`$```##N```
-M``##@4X(````(,.%R702BT8,"=")PH#.$$6%P`]$PNL=187`=`Q!BT$(B48(
-MB58,ZP_'1@@`````B="`S!")1@S'1A0`````QT80`````+@!````PTB)\?9&
-M%`%U!K@/````PXM&%"7^'P``T>AFB0(/MT829HE"`L9"!`"+1A"H`74<J`)T
-M!,9"!`'V01`(=`2`2@0"]D$0!'0$@$H$!(M!""4``#P`P>@2B$(%BT$4)0#@
-M'P#!Z`V(0@:+01`E``\``(G&P>X(0(AR!XM!$"7P````P>@$B$((BT$0)0#P
-M``#!Z`R(0@G&0@H`QD(+`$"$]G0&C48!B$('@'H(`'0#_D((N`````##PY"`
-MCX`P```(@$X$"`^WAWXP``!FB08/MH>`,```B$8$#[:'@3```(A&!;@`````
-MPY!(BT<@QX"`0````/Q(DDB+1R#'@(!````D29(D2(M'(,>`@$```#D``"A(
-MBT<@QX"`0```)`@64TB+1R#'@(!```!Y!9CE2(M'(,>`@$```/_O'0!(BT<@
-MQX"`0```0+ZJ&DB+1R#'@(!```!451"^2(M'(,>`@$````<P#@!(BT<@QX"$
-M0````````,-(@^P(2(M'(,>`T)@``!8<``"Z`````$B+1R#'@("8``````$`
-M_\*#^@=^ZTB+1R"+@`"<``")Q\'O&(GZP>H$B?B#X`_!X`2)UPG'O@@```#H
-M`````$B#Q`C#2('LB````$B)_L=$)&#)____QT0D9,G____'1"1HR?___\=$
-M)&S)____QT0D<,+____'1"1`\O___\=$)$3R____QT0D2/+____'1"1,\O__
-M_\=$)%#T____QT0D(,#____'1"0DP/___\=$)"C`____QT0D+,#____'1"0P
-MNO___\<$)++____'1"0$LO___\=$)`BR____QT0D#++____'1"00L/___[D`
-M````2&/!BU2$8(F4ABA(``"+5(1`B92&/$@``(M4A"")E(902```BQ2$B92&
-M9$@``/_!@_D$?LN^`0```.@`````2('$B````,-(8_:)TDB--'(/MX1WMA<`
-M`,-!5T%6055!5%-(B?M!B?=)B=1)B<U-B<:Z*!0``$C'Q@````#H`````$R)
-M8Q!,B6L83(ES(&9$B;MX`P``9L>#>@,`````9L>#K`,``#\`QX.P`P``````
-M`,>#K#$```````#'@[`Q````````QX.\,0``````",>#Q#$``($'``#'@\PQ
-M````````QX/0,0``/S\_`,>#U#$``&0```#'@]@Q```"````QX/P,0``____
-M_\>#]#$``/_____'@_@Q``#_____2(V[!"X``+H&````2,?&`````.@`````
-MQH/\,0```%M!7$%=05Y!7\.Y`````$G'P`````!)Q\$`````2<?"`````$AC
-MP4B-%$!!.#P0=1%!.#01=PNX`0```$$Z-!)V#/_!@_D#=MNX`````,-!5T%6
-M055!5%532(/L"$F)]4F)U$B)S4V)QXG[OZA(``#H`````$F)QDB%P'4,0<<'
-M`@```.E+!@``#[?S38GY28GH3(GA3(GJ2(G'Z`````!,B?.Z`0```+X`````
-M3(GWZ`````"%P'1428M&((N`($````^VT(G0P>@$08F&?`,``(G0@^`/9D&)
-MAH`#``!!#[:V@`,``$$/MKY\`P``Z!;___^%P`^$5P0``+X`````3(GWZ```
-M``"%P'4,QP0D`P```.FC!0``28M&((N`&)@``&9!B8:"`P``08.^?`,```ET
-M%4&#OGP#```*=1-F08.^@`,```-W"$B)W^C9^___2(G?Z`````"%P'4,QP0D
-M#@```.E2!0``@[M\`P``!'832(M3((N"$$```(#,$(F"$$```$B+0R#'@`"8
-M```'````2(G?Z`````!FB8.$`P``#[?`)?````"#^#`/A*(```"#^#!_#H/X
-M$`^$E````(/X(.L8@_A@#X2&````@_A@?P6#^%#K!3V@````='5F@[N$`P``
-M`'5K@[M\`P``!747@;N``P``"0!#`'4+9L>#A`,``$8`ZTN#NWP#```'=`F#
-MNWP#```+=0MFQX.$`P``40#K+H.[?`,```IT'(.[?`,```ET$X.[?`,```IU
-M'&:#NX`#```#=PEFQX.$`P``8@"#NWP#```*=$"#NWP#```)=#>#NWP#```*
-M=0IF@[N``P```W8D#[>3A`,``(G0)?````"#Z#"#^#]W#HG0@^`/@_@$#XZT
-M`@``2(U4)`:^P0```$B)W^@`````A<`/A/P#``!F@7PD!@$P=PS'!"0%````
-MZ>X#```/MT0D!F9!B88H%```2(M#((N0$$```(/B&,'J`X/Z`G0M@_H#=!R#
-MNWP#```)=!^#NWP#```*=0IF@[N``P```W8,QP0D"@```.F?`P``2(U4)`:^
-M/P```$B)W^@`````A<`/A'X#```/MT0D!F9!B88J%```2(U4)`:^'````$B)
-MW^@`````A<`/A%<#``!F@WPD!@!T/$0/MV0D!D&!Y/#_``!!P>0,2(U4)`:^
-M&P```$B)W^@`````A<`/A"0#```/MT0D!D$)Q$&![,````#K!D&\0`,``$&]
-M`````+T`````13GE<RJ-M<````!(C50D!DB)W^@`````A<`/A.("```/MT0D
-M!D$QQ?_%1#GE<M9!@?W__P``=`S'!"0'````Z<4"``!F0<>&GA4```H`9D''
-MAJ@7```#`+T`````B>A(:\`T9D''A`:F%0``"P#_Q8/]"7;HO0````!(Q\8`
-M````2,?!`````(GH#[<41F9!B91&L!<```^W%$%F08F41JH7``!(:\`T3`'P
-M9L>`;!@```L`9L>`T!<```L`_\6#_0)VQ$F-MB@4``!(B=_H`````(7`#X0G
-M`@``9D&!OB@4```"4'=-@[M\`P``"G0<@[M\`P``"703@[M\`P``"G4R9H.[
-M@`,```-W*&9!QX:X%P``:`9F0<>&O!<``+`$9D''AL`7````@&9!QX:V%P``
-M`(!F08.^0A0```!T;0^W@X0#```E\````(/X$'5<2(M#(,>``)@```=```"_
-MT`<``.@`````2(G?Z`````!FB8.&`P``2(M#(,>``)@```<```"_T`<``.@`
-M````#[>#A@,``"7P````@_@@=`S'!"0-````Z5T!``!(C50D!KZ_````2(G?
-MZ`````"%P`^$/`$```^W1"0&9D&)ABP4``!FB8.X`P``2(G?Z`````"%P`^$
-M&`$``(.[?`,```IT'(.[?`,```ET$X.[?`,```IU%V:#NX`#```#=PU(B>9(
-MB=_H`````.M+@[M\`P``!W0)@[M\`P``"W4-2(GF2(G?Z`````#K+`^W@X0#
-M```E\````(/H,(/X/W<-2(GF2(G?Z`````#K"TB)YDB)W^@`````A<`/A)H`
-M``!)BX:P+@``2(F#:`,``$B)W^@`````0;T`````O0````!!O!\```!$B>8I
-M[DB-5"0&2(G?Z`````"%P'16#[=$)`9!`<6-5"T`B=%F#[9$)`=!B(0.^"T`
-M`/_"#[9$)`9!B(06^"T``/_%@_T"=KA%A>UT"4&!_?W_`@!U"<<$)`D```#K
-M%$B)W^AC]___2(G8ZR3'!"0(````387V=`A,B??H`````$V%_W0&BP0D08D'
-MN`````!(@\0(6UU!7$%=05Y!7\-32(G[Z`````!(@[MX+@```'0)2(G?_Y-X
-M+@``2(G?Z`````"Z`0```+X!````2(G?Z`````!(C;,H%```2(G?Z`````!(
-MB=_H`````%O#4TB#["#'1"0(`(```,=$)`P@F```QT0D$%55557'1"04JJJJ
-MJL=$)!AF9F9FQT0D')F9F9E!N@````!(C5PD"$F)XTECTDC!X@)$BPP31(G)
-M2(M'((L$`4&)!!-!N`````!$B<#!X!")QD0)QDB+1R")-`%(BT<@BQ0!N```
-M```Y\G5M0?_`08'X_P```'[20;@`````1(G)26/`BW2$$$B+1R")-`%(BT<@
-MBQ0!N``````YUG4Z0?_`08/X`W[926/"2,'@`HL,`TB+5R!!BP0#B0010?_"
-M08/Z`0^.8?___[]D````Z`````"X`0```$B#Q"!;PXGP]L0!=`QFQP(S$V;'
-M`=07ZR)`A/9Y(TBX``#_____``!(A8=`%```=!!FQP(("6;'`:P*N`$```##
-MN`````##055!5%532(/L"$B)_4F)_4F)_$B-GY`#``!FQT0D!@``9H&_*!0`
-M``!0=AU(C50D!K[)````_Y<H`P``N@````"%P`^$J@,```^WA80#```E\```
-M`(/X0'4*9D''A3X4`````&:#?"0&`'4N@[U\`P``!W4E9H.]@`,```AU&V;'
-M1"0&!0!F0<>%+A0```$`9D''A3`4```!`$&#O"2,`P``!G1$9D&!O"1Z`P``
-M97!U-T$/MY0DN`,``(U"G&:#^`%W#HU"!69!B80DN`,``.L79D&#O"2X`P``
-M074+9D''A"2X`P``0P#'0P0`````9D&#O3X4````=!G'0P0!````9D&#O2X4
-M````=0?'0P0#````9D&#O4(4````=`2#2P0$9D&#O404````="MF08&\)'H#
-M```1#G0>BU,$B="#R`B)0P1F08.],!0```!U"(G0@\@HB4,$9L=#$`@)#[>%
-MA`,``"7P````@^@P@_@_=C>#O7P#```'="Z#O7P#```+="6#O7P#```*=!R#
-MO7P#```)=!.#O7P#```*=1)F@[V``P```W<(9L=#$L0)ZP9FQT,2K`IFQT,,
-M,Q-FQT,.U!</MD,!@^"_@\B`B$,!N`````#V1"0&`G4A@[U\`P``!7<3@[U\
-M`P``!74/9H.]@`,```-V!;@!````P>`%#[93`8/BVPG"@\H(#[=$)`;1Z(/P
-M`8/@`0'`@^+]"<*(4P&#O7P#```&=@J)T(/($(A#`>L$@&,![X`+`V9!@[PD
-M@`,```%W"8.]?`,```MU9+H`````]D0D!@%U#/9#!`FX`0````]%T(TTE0``
-M```/MA.#XO,/MTPD!HG(P>@#@_`!@^`!P>`#"?()PH@3N@````#VP01U#/9#
-M!`FX`0````]%T,'B!`^V`X/@[PG0@\B@B`.`([^Z`````$&#O?`4````=`I!
-M@[WT%````'4%N@$````/MD,!@^#^"="(0P&`2P(/08.\)'P#```%=0QF08.\
-M)(`#```(=`M!@[PD?`,```5V!(!+`A`/MT0D!B7P`0``=`G!^`1FB4,(ZP9F
-MQT,("@!F]T0D!@#P=!4/MTPD!L'I#+@!````T^!FB4,*ZP9FQT,*@``/MX6$
-M`P``)?````"#Z#"#^#]W!H!+`F#K!(!C`I]F08.],A0```!T*DF-E"0`%```
-MO@\```!(B>__E2@#``"%P'000<>$)`04```!````@$L"@(.]?`,```0/EL`/
-MML!!B80D(!0``+H`````@[U\`P``!74*9H.]@`,```ET"8.]?`,```5V!;H!
-M````#[9#`X/@_@G0B$,#QT,4#P```+H!````B=!(@\0(6UU!7$%=PTB#[`A(
-MB>;H`````+@!````2(/$",.#_@%(Q\``````2,?"`````$@/1,)(B8?(````
-MPY!(@^P82(E<)`A(B6PD$$B)^TB)]4B+5R"+1@2)@BB```!(BU<@BT8,B8(L
-M@```2(M7((M&$(F",(```$B+5R"+1@B)@C2```#V1@,!="5(B>;H`````$B+
-M@^@3``!(QT`H`````$B+0R#'@""````````!2(M3((M%`(F"((```$B+7"0(
-M2(ML)!!(@\08PTB#["B)="0$BX>,`P``@_@!=`^#^`%R'(/X!G07@_@(=3#'
-M1"0,__\``,=$)!#__P<`ZQZ)\"L%`````,'@`XE$)`R)\"L%`````,'@`XE$
-M)!"-1@&)1"0(B=`E__^``8D$)$B)YN@`````2(/$*,-(BT<@QX`H@```````
-M`$B+5R"+@@2````-```$`"7__\__B8($@```2(M'(,>`((```/__``##28GX
-M9H-^$@!T0TB+5R"+@@2````-```0`(F"!(```$B+5R`/MT80B8(D@```2(M7
-M(`^W1A*)@CB```!(BU<@BT84P>`#B8(P@```ZQ5(BU<@BX($@```)?__[_^)
-M@@2```!(BU<@BP:)@BB```!(BT\@BX$@@```)0``@/\/MU8("<)F@WX8`'01
-M#[=&&(/`!,'@$"4``'\`"<*)D2"```!!BX#$,0``,.0/MU8:P>((@>(`_P``
-M"=!!B8#$,0``2(M7((F"&(```$0/MTX(1#E.''8$1(M.'$2+1@Q$.48<=@1$
-MBT8<13G!=06+3@3K`HL.2(M7((M&!(/H`\'@`R7__P<`#0``&`J)@M2```!(
-MBU<@C03-Z/___R7__P<`#0````J)@MB```!(BT\@00^WP42)PL'B$`G0B8'<
-M@```PTB#[!A(B5PD"$B);"002(G[2(G52(M'((FP`&```$B+1R#'@`A@```!
-M````N0(```"Z`P```+X,8```Z`````"Z`````(7`=!-(BT,@BX`$8```9HE%
-M`+H!````B=!(BUPD"$B+;"002(/$&,.0D)!(BW\@C0PVN`,```#3X(N7%$``
-M``G0B8<40```N`$```##2(M_((T,-K@#````T^#WT(N7%$```"'0B8<40```
-MN`$```##2(M_($2+AQA```"X_O___XGQT\!!(<"#X@'3XD$)T$2)AQA```"X
-M`0```,.)\;C_____@_X%=Q)(BT<@BX`<0```@^`OT^B#X`'#2(/L"$B+1R!$
-MBX@40```1(T$-K@#````1(G!T^`-`/`!`/?002'!P>8,00GQ08')`(```$2)
-MR`T```$`A=)$#T7(2(M'($2)B!1```"+MPPN``"!S@````'H`````$B#Q`C#
-M2(M'((N`"$```(/X`0^4P`^VP,-!N0````!)B?I(BT<@1(N`@````$'WP```
-M@`!T2XN0C````/?"`````;@``"``1`]%R$2)R`T``$``]\(````@1`]%R$2)
-MR`T``(``]\(````$1`]%R$2)R`T````"]\(````"1`]%R$B+1R!$BX#`````
-M08/X_W4,QP8`````N`````##1(G`);K8!0&)!D'WP```"`!T!PT```!`B09!
-M]L`%=`.##@%!]\#`!0``=%*##D!(BT<@BY#$````B=`E_P,``$$+@J1(``"!
-MX@``_P/!ZA`)PD&)DJ1(``!(BT<@BX#(````B<&!X?\#```)T24``/\#P>@0
-M"<A!B8*D2```0?;`('0/@[\@%````'0&@0X```!`1(G("P:)!JD```!`=$=$
-MB8<(%```2(M7((N"Q````(F'#!0``(N"R````(F'$!0``(N"S````(F'%!0`
-M`(N"T````(F'&!0``(N"U````(F''!0``+@!````PXN'#"X``,-)B?A$BX\,
-M+@``187)>1)(BT<@QT`D`````$B+1R"+0"2)\H'BNM@%`;D`````0/;&0'0T
-M08.XO"X```!T`X/*0$&#N,`N````=`.`S@%!@[C$+@```'0#@,J`08.XR"X`
-M``!T`X#.!(G0@\@'0/;&`0]%T/?&``#@`G1&@<H``(``B<@-`````??&```@
-M``]%R(G(#0```"#WQ@``0``/1<B)R`T````$]\8``(``#T7(B<@-`````O?&
-M`````@]%R(G0#0``"`#WQ@```$`/1=!(BT<@B9"@````2(M7((N"K````"7_
-M__]("<B)@JP```!!B;`,+@``A?9Y"TB+1R#'0"0!````1(G(PY`/MX>:`P``
-MPXGP9CNWF@,``',>2,'@!27@_Q\`2(M7((N$$!R(``"Z`0```&:%P'@%N@``
-M``")T,-F.[>:`P``<@:X`````,-(B?!(P>`%)>#_'P!(BU<@BXP0%(@``,>$
-M$`"(````````2(M7(,>$$`2(````````2(M7(,>$$`B(````````2(M7(,>$
-M$`R(````````2(M7(,>$$!"(````````2(M7(,>$$!2(```'````2(M7(,>$
-M$!B(````````2(M7(,>$$!R(````````@_D$=5'VA[\Q```(=$B-1D!(P>`%
-M)>#_'P!(BU<@QX00`(@```````!(BU<@QX00!(@```````!(BU<@QX00"(@`
-M``````!(BU<@QX00#(@```````"X`0```,-F.[>:`P``<@:X`````,-(A=)T
-M/40/MD(%0<'@"`^V0@1!"<`/MDH#P>$8#[9"`L'@$`G!#[9"`<'@"`G!#[8"
-M"<'1Z42)P,'@'PG!0='HZPM!N`````"Y`````$B)\DC!X@6!XN#_'P!(BT<@
-MB8P"&(@``$B+3R!$B<"`S(")A`H<B```N`$```##05=!5D%505154TB#[!A(
-MB?U(B=-)B<I!B?5)B?](C8^0`P``187`N@````"XJJJJJHG&#T3R9D0[:0H/
-M@X4````/M@.#^`5W?8G`_R3%`````$&[!0```.MV]D$!('1F0;L&````ZVA!
-MNP0```#VA[\Q```(=%E!#[?%@\!`#[=1"KD`````.=`/C1`#``#K/V:#>P($
-M=BYF@WL"!7<(0;L`````ZREF@WL"#7<(0;L!````ZQI!NP,```#K$D&[!P``
-M`.L*N0````#ISP(``$0/MF,$#[9#!<'@"$$)Q`^V0P;!X!!!"<0/MD,'P>`8
-M00G$03'T#[9#"<'@"`^V4PA!B=9!"<9!,?9!@>;__P``1`^V0PH/MD,+P>`(
-M00G`#[9##,'@$$$)P`^V0PW!X!A!"<!!,?`/MD,/P>`(#[93#D&)T4$)P4$Q
-M\4&!X?__```/MGL0#[9#$<'@"`G'#[9#$L'@$`G'#[9#$\'@&`G',?=F@WL"
-M#7<&@>?_````08/[!`^%LP$``/:%OS$```@/A*8!``!!C45`9HD$)$$/M_6)
-M\L'B!4ACTDB+32!$B>#WT(F$"@"(``!(BTT@1(GP]]")A`H$B```2(M%($2)
-MA`((B```2(M%($2)C`(,B```2(M%((F\`A"(``!(BT4@QX0"%(@```0```!,
-MB=)(B>_H``````^V<Q0/MD,5P>`("<8/MD,6P>`0"<8/MD,7P>`8"<8/MDL8
-M#[9#&<'@"`G!#[9#&L'@$`G!#[9#&\'@&`G!0?:'P#$```1T0P^V0Q_!X`@/
-MME,>08G000G`#[9#'<'@"`^V4QQ!B=%!"<$/MGL@#[9#(<'@"`G'#[9#(L'@
-M$`G'#[9#(\'@&`G'ZQ&_`````$&Y`````$&X`````(L4)$C!X@6!XN#_'P!(
-MBT4@B;0"`(@``$B+12!$B80"!(@``$B+12")C`((B```2(M%($2)C`(,B```
-M2(M%((F\`A"(``!(BT4@QX0"%(@```<```!(BT4@QX0"&(@```````!(BT4@
-MQX0"'(@```````!,B>A(P>`%)>#_'P!(BU4@1(FD$`"(``!(BU4@1(FT$`2(
-M``#K74$/M_6)\,'@!4B82(M5($2)I!``B```2(M5($2)M!`$B```2(M5($2)
-MA!`(B```2(M5($2)C!`,B```2(M5((F\$!"(``!(BU4@1(F<$!2(``!,B=)(
-MB>_H`````+D!````B<A(@\086UU!7$%=05Y!7\.0D$B#[`A(B?!(C;?X+0``
-MN@8```!(B<?H`````$B#Q`C#2(/L"$B!Q_@M``"Z!@```.@`````N`$```!(
-M@\0(PTB#[`A(B?!(C;<$+@``N@8```!(B<?H`````$B#Q`C#4TB)^TB-OP0N
-M``"Z!@```.@`````2(M+(`^VDP0N```/MH,%+@``P>`("<(/MH,&+@``P>`0
-M"<(/MH,'+@``P>`8"<*)D>"```!(BTL@#[:3"2X``,'B"`^V@P@N```)T(F!
-MY(```+@!````6\-F.;>X`P``=0>X#````.L4@+\J%`````^8P`^VP(T$Q0,`
-M``!(A=)T`HD"N`````##2(GZN`````!F@[\^%````'04N`$```!F@[\N%```
-M`'4%N$,```!F@[]"%````'0#@\@$9H._1!0```!T&V:!NGH#```1#G00@\@(
-M9H._,!0```!U`X/((,-(@^P82(D<)$B);"0(3(ED)!!(B?L/MX<`%```08G$
-M08/D'$'!_`*)Q8/E`M']1(GF_Y=``P``2(M3((N"`)@``(#,((F"`)@``$2)
-MYDB)W_^32`,``(GJ.>AU"(7M#Y3`#[;01(GF2(G?_Y-8`P``2(L<)$B+;"0(
-M3(MD)!!(@\08PTB+5R"+@A!````EG__Q_X/F!PL$M0````")@A!```##2(/L
-M&$B)7"0(2(EL)!!(B?N)U4B-O_XM``"Z!@```.@`````2(M+(`^VD_XM```/
-MMH/_+0``P>`("<(/MH,`+@``P>`0"<(/MH,!+@``P>`8"<*)D0B```!(BTL@
-M#[:#`RX``,'@"`^VDP(N```)PHGH)?\_``#!X!`)PHF1#(```$B+7"0(2(ML
-M)!!(@\08PTB+5R"+LDR```"+@E"```"+DDR```"-2`$Y\@]"P4C!X"")TD@)
-MT,-(BT<@BX!,@```PTB+5R"+@B"````-`````8F"((```$B+5R")@B"```##
-M2(N'Z!,``$B%P'1I]D`"('1C0;@`````N@`````[%G,=2&/"#[9$,`2$P'D+
-M@^!_1#C`<@-!B<#_PCL6<N-(BU<@BXH$@```183`=!=$B<#0Z#P"=PZ)R`T`
-M```"B8($@```PTB+5R")R"7____]B8($@```D,-(BT<@BX!DF```B<'!Z1.!
-MX?\!``#VQ0%T!H'Q`/[__TB+5R"+@E"```"+DDR````QT#'(PTB+1R"+@"!`
-M```E_P```(G"@^(/N0````#!Z`0YAWP#``!U#F8YEX`#``!U!;D!````B<C#
-M2(M'((N`D(````$&2(M'((N`C(````%&!$B+1R"+@)2````!1@Q(BT<@BX"(
-M@````48(2(M'((N`F(````%&$,.X`0```,-(BT<@BX`<G```)?\```##2(M'
-M((N`6(```(/@!\-(BT<@@^8'B;!8@```PXN'K#$``,-(@^P(2(N7Z!,``$B%
-MTG4-B;>L,0``N`$```#K!>@`````2(/$",.X`0```,-(@^P82(D<)$B);"0(
-M3(ED)!!(B?V)\TF)_(/^!78.OO__``#H`````#G#=A-!QX0D\#$``/____^X
-M`````.L?B=Y(B>_H`````$B+52")@G`0``")G?`Q``"X`0```$B+'"1(BVPD
-M"$R+9"002(/$&,-(@^P(2(M'((NP<!```('F__\``.@`````2(/$",-(@^PH
-M2(D<)$B);"0(3(ED)!!,B6PD&$R)="0@2(G]08GVOO\_``#H`````$$YQG81
-MQX7T,0``_____[@`````ZSA,BV4@08N<)!2```"!XP#`__]$B?9(B>_H````
-M`"7_/P``"<-!B9PD%(```$2)M?0Q``"X`0```$B+'"1(BVPD"$R+9"003(ML
-M)!A,BW0D($B#Q"C#2(/L"$B+1R"+L!2```"!YO\_``#H`````$B#Q`C##[:'
-MOS$``(/P`8/@`<.%]G0A2(M7((N"!(```"7____^B8($@```@:>\,0``____
-M_NL?2(M7((N"!(````T````!B8($@```@8^\,0```````;@!````PTB#["A(
-MB1PD2(EL)`A,B60D$$R);"083(ET)"!(B?U!B?:^_S\``.@`````03G&=A''
-MA?@Q``#_____N`````#K.TR+92!!BYPD%(```('C__\`P$2)]DB)[^@`````
-MP>`0)0``_S\)PT&)G"04@```1(FU^#$``+@!````2(L<)$B+;"0(3(MD)!!,
-MBVPD&$R+="0@2(/$*,-(@^P(2(M'((NP%(```('F``#_/\'N$.@`````2(/$
-M",-!B=")\;@,````9H/Y?W<P2(M7(`^WP8F"``0``$B+5R!%A<`/E<`/ML")
-M@@0$```/M\%$B(0'*#$``+@`````PTB#[!A(B5PD"$B);"002(G[B?5`B+?P
-M$P``A=(/A/8```!`A/8/A.T```!(BX?H$P``#[=``B5``0``/4`!```/A=(`
-M``"^`0```.@`````B<=(BX/H$P``]D`#0'0G0`^V]8GXT>@/K_"--':!Q@0!
-M``!`#[;-#Z_(C01)C8P`K`T``.M72(N#Z!,``&:#>`(`>2A`#[;UB?C!Z`(/
-MK_"--':!QM(```!`#[;-#Z_(C01)C8P`2`T``.LA0`^V]0^O]XTT=H'&:`$`
-M`$`/MLT/K\^-!$F-C`!@#@``0`^VU0^OUXT44H'"Z`,``('B_S\``$B+0R")
-ML'`0``!(BT,@B8BP$```2(M+((G0P>`0"=")@12```!(BUPD"$B+;"002(/$
-M&,-(@^P(B[>,`P``Z`````!(@\0(P[@`````@_X&=!>`OTL4````=`Z#O]@Q
-M```!=P6X`0```,-32(G[Z`````"%P`^$00$``$B+0R#'@'"8```?````2(M3
-M(`^W@X0#```E\````(/H,(/X0!G`@^#\@\`8B8+XF0``2(M3((N"'(```"5_
-MP/__#(")@AR```!(BT,@QX`$@0``/0```$B+4R"+@A!```"#R`*)@A!```"#
-MNWP#```'="Z#NWP#```+="6#NWP#```*=!R#NWP#```)=!.#NWP#```*=5AF
-M@[N``P```W=.2(M#(,>`=)@``"8```!(BT,@QX!XF```#0```$B+0R#'@/"9
-M```'````2(M#(,>`])D``#\```!(BU,@BX(00```)?____P-`````NM'2(M#
-M(,>`=)@```H```!(BT,@QX!XF```#````$B+0R#'@/"9```#````2(M#(,>`
-M])D``"````!(BU,@BX(00```#0````.)@A!```#IR@```$B+4R"+@A!````E
-M_____(F"$$```$B+4R"+@A!```"#X/V)@A!```!(BT,@QX!PF```'P```$B+
-M0R#'@'28``!_````2(M#(,>`>)@```X```!(BT,@QX#PF0``#````$B+0R#'
-M@/29``#_````2(M3(`^W@X0#```E\````(/H,(/X0!G`@^#\@\`2B8+XF0``
-M2(MS((N&'(```"5_P/__#[>3A`,``('B\````(/J,(G!@<F`$P``#8`/``"#
-M^C\/1L&)AAR```!;PU-(B?OH`````(7`#X38````2(M3((N"$$```"7____\
-MB8(00```2(M3((N"$$```(/@_8F"$$```$B+0R#'@`2!```!````2(MS((N&
-M'(```"5_P/__#[>3A`,``('B\````(/J,(G!@<F`$P``#8`/``"#^C\/1L&)
-MAAR```!(BT,@QX!PF```'P```$B+0R#'@'28``!_````2(M#(,>`>)@```X`
-M``!(BT,@QX#PF0``#````$B+0R#'@/29``#_````2(M3(`^W@X0#```E\```
-M`(/H,(/X0!G`@^#\@\`8B8+XF0``6\.Z`````$C'QP`````/MP:)P68[!0``
-M``!W"__"2&/"9CL,AW;U2&/"#[\$A0````##2(/L&$B)7"0(2(EL)!")TTB)
-MS4B)^4B-EY`#``"#_AT/AR("``")\/\DQ0````"#^P)T)H/[`@^"!`(``(/[
-M!`^"B0```(/[!0^&\@$``(/[?P^$Z0$``.MU]D(!(.DT`0``N`````"%VP^$
-MX@$``(/[`74.BX>\,0``P>@;Z7<!``"%VW0*@_L!=!'I(P$``/9"`1`/E<#I
-MMP```(N!P#$``,'H`NE2`0``@[]\`P``!0^'B0$``(._?`,```5U#F:#OX`#
-M```'#X=R`0``N`T```#I>0$``+@`````A=L/A&P!``"#^P$/A<4```!(BT<@
-MBX`(H@``P>@-Z?D```"+AZ@#``#I,@$``+@`````A=L/A#D!``"#^P$/A1\!
-M``"#O\PQ````ZR:%VW0'@_L!=`SK)F:#OSX4````ZQ%(N```_____P``2(6'
-M0!0```^4P`^VP.GV````N`$```#I[````+@`````A=L/A-\```"#^P%U/(N'
-MO#$``/?0P>@?Z<H```"%VW0'@_L!=!CK(?9"`A"Z`````+@-````#T7"Z:D`
-M``"+A\`Q``#!Z`/K1K@,````Z90```"+A]`Q``"#X#_K=8N'T#$``"4`/P``
-MP>@(ZV6#^P%T%K@`````@_L!<FJX#````(/[!G=@ZPZ+AQ`R``"#\`&#X`'K
-M4.@`````2(G"N`$```!(A=)T/H/[!G<HB=C_),4`````#[9"">L6#[9"#.L0
-M#[9"#>L*#[9""^L$#[9""HE%`+@`````ZPI(B>F)VN@`````2(M<)`A(BVPD
-M$$B#Q!C#2(/L"$F)^DR-CY`#``"#_AT/AW`!``")\/\DQ0````"%R70/@8^\
-M,0``````".E-`0``@:>\,0``____]^D^`0``0?9!`1!U"K@`````Z3D!``"%
-MR70)@Z?`,0``^^L'@X_`,0``!$B+5R!!BX+`,0``B8(@@0``Z0,!``!(BT<@
-MB[`(H@``B?*`SB")\(#DWX7)B=8/1/!(BT<@B;`(H@``Z=D```")CZ@#``!(
-MBT<@B8A(@```Z<0```"%R0^5P`^VP(F'S#$``.FQ````A<ET#X&/O#$`````
-M`(#IG@```(&GO#$``/___W_ICP````^_A^PQ```!P8/Y0+@_````#T/(@_X:
-M=0V)R`N'T#$``(/@/^L8BY?0,0``@>(`/P``B<@E`#\``,'H"`G008F"T#$`
-M`$B+5R!!BX+0,0``B8+H@```ZS>X`````(/Z!G<YB="+-(4`````B<KH````
-M`.LG0?9!`A!T&X7)=`F#C\`Q```(ZP>#I\`Q``#WN`$```#K!>@`````2(/$
-M",-(@^P(Z`````"%P`^5P`^VP$B#Q`C#D)!54TB#[`A(B?N%]G1E2(M7((N"
-M!$```"7___S_B8($0```OPH```#H`````+TH````2(M#((N`$$```*D```$`
-M="6_,@```.@`````2(M3((N"!$```"7___S_B8($0```_\UUS.L$A>UU![@`
-M````ZQI(BU,@BX($@```)?__^_^)@@2```"X`0```$B#Q`A;7<-(BU<@BX($
-M@```#0``!`")@@2```"%]G0:2(M7((N"!$```"7___S_#0```0")@@1```##
-M2(M7((N"!(````T```0`B8($@```A?9T&DB+5R"+@@1````E___\_PT```(`
-MB8($0```PTB#[!A(B1PD2(EL)`A,B60D$(GS2(G]0;P!````@_X!=!B#_@%R
-M!X/^`G07ZQZ)UNC0_O__08G$ZQF)UNA7____ZQ")UNB"____ZP>X`````.L)
-MB9VH,0``1(G@2(L<)$B+;"0(3(MD)!!(@\08PTB+1R"+@`1````E```#`,'H
-M$,.0D)!3@_X(#X2'````@_X(=R*#_@(/A((```"#_@)W"H/^`70XZ:````"#
-M_@1T7.F6````@?X``0``='.!_@`!``!W!X/^('1=ZW^!_@`"``!T98'^``0`
-M`'1FZVU(Q\,`````2(._Z!,```!T8TB+A^@3``#V0`-`=3U(BX?H$P``9H-X
-M`@!Y2.LV2,?#`````.L]2,?#`````.LT2,?#`````.LK2,?#`````.LB2,?#
-M`````.L92,?#`````.L02,?#`````.L'N`````#K"TB)WN@`````2(G86\.0
-M2(M'((M`#,-(BT<@B7`,PTB+1R#'0`@$````PTB#[`A(BT<@QT`((````+D`
-M````N@0```"^"````.@`````A<`/E<`/ML!(@\0(PU-(B?M(BU<@BX)(@```
-M@^#?B8)(@```Z`````"^`0```$B)W^@`````6\-(@^P(2(M7((N"2(```(/(
-M((F"2(```.@`````2(/$",-(BT<@B;!`@```2(M'((F01(```,.X`````(/^
-M/W='@_X?=B!(BU<@1(N"1(```(U.X+C^____T\!$(<")@D2```#K'4B+5R!$
-MBX)`@```N/[___^)\=/`1"'`B8)`@```N`$```##N`````"#_C]W1X/^'W8@
-M2(M7($2+@D2```"-3N"X`0```-/@1`G`B8)$@```ZQU(BT<@1(N`0(```+H!
-M````B?'3XD0)PHF00(```+@!````PTB+5R"+@CR```"+B@R!``")PH#.`O;!
-M(`]%PHG"@,X!]\$```("#T7"PTB+5R!`#[;&B8(\@```N`````#WQ@`"``"Z
-M(`````]%PHG"@<H```("]\8``0``#T7"2(M7((F"#($``(7`=`Q(BU<@BT(T
-M@\@0ZPI(BU<@BT(T@^#OB4(TP\=&"`````")T"7_#P``B48,]L$@=`:`S"")
-M1@S'1A0`````QT80`````+@!````PTB#[`A-B<CV1A0!=0JY#P```.GS````
-M]D$4`7442(M'((M`#+D/````.=`/A-D````/MT809B7_#V9!B0"+1A0E``#_
-M?\'H$&9!B4`"0<9`!`"+1A`E``#P#\'H%$&(0`8\@'4%0<9`!@"+1A3VQ`%T
-M#B4`_@``P>@)08A`!^L%0<9`!_^+1A`E`(`/`,'H#T&(0`B+1A`E````\,'H
-M'$&(0`F+1A#!Z`R#X`%!B$`*BT84J`)U3J@$=`=!@$@$`>M#]D84$'0E08!(
-M!`(/MD8508A`!8._%#(```!U)X/X!70B3(G&Z`````#K&/9&%`AT!T&`2`0(
-MZPOV1A0@=`5!@$@$$+D`````B<A(@\0(PY"005=!5D%505154TB#[$A(B?V)
-M="1`28G4B4PD/$R)1"0P2(E\)"!!O0`````/MT("]L0!=`>I@````.L,#[="
-M`L'H!X/P`:@!#X5D`@``00^W1"0"J"!T!*A`ZPY!#[=$)`+!Z`:#\`&H`0^%
-M0@(``+H!````O@````!(B>_H`````+H`````A<`/A*T,``!,B>9(B>_H````
-M`$B)1"08N@P```!(A<`/A'X,``"#?"1`!G0?@WPD0`9W#8-\)$`!#X?L`0``
-MZPN#?"1`"`^%WP$``,=$)!0`````@WPD/`!T*$B+12"+@$`1``")1"042(MT
-M)!A(B>_H`````+X`````2(GOZ`````"#O7P#```'="Z#O7P#```+="6#O7P#
-M```*=!R#O7P#```)=!.#O7P#```*=5UF@[V``P```W=3@WPD/`!T3$B#O>@3
-M````=$)(BXWH$P``00^W!"1F.P%T,4$/MU0D`H'B\`$```^W00(E\`$``#G"
-M=1A,B>9(B>_H`````+H!````A<`/A:@+``!(BT4@BX!8@```B40D$(7`N`$`
-M```/140D$(E$)!!(BU4@BX($@```)0``(`*)1"0(BX(00```)6``_@")1"0,
-MBX(40```B40D+(N2&$```(E4)"B+="1`2(GOZ`````!(B>_H`````$R)YDB)
-M[^@`````N@,```"%P`^$%PL``$$/MT0D`B7P`0``/4`!``!T3#U``0``?R`]
-MP````'1C/<````!_"3V@````=$OK;CW0````=%;K93W`"```=$,]P`@``'\'
-M/5`!``#K##U`"0``=`D]4`D``'0,ZT#'1"0$`0```.L(QT0D!`(```#'!"0!
-M````ZR_'1"0$`P```.L2QT0D!`0```#K",=$)`0%````QP0D`@```.L*N@P`
-M``#I;PH``$B+12#'@`"8```'````NP````!)Q\<`````1(MT)`1(8\-(C01`
-M08L,QTB+52!)C01&08L$AXD$$4'_Q4'VQ3]U"K\!````Z`````#_PX/[&';,
-MNP````!(8\.+%,4`````@WPD/`!T%HV"X'___X/X&'8QC8(L?___@_@(=B:)
-MT4B+52!(8\.+!,4`````B0010?_%0?;%/W4*OP$```#H`````/_#@?O#````
-M=JE$B>F+%"2+="0$2(GO2(M<)"#_DX`N``!!]D0D`T!U"69!@WPD`@!Y"TR)
-MYDB)[^@`````9H.]@@,``$$/ANT```!(BT4@QX`LF````J`"`&9!@3PDM`EU
-M+TB+1"0@#[:02A0```^W@%04```IPDACPDAIP&=F9F9(P>@@T?C!^A^)QF8I
-MUNL=2(M4)"`/MH)*%```2)A(:<!G9F9F2,'H((G&T>Y!#[=$)`(ET````#W`
-M````=3%(BTT@2(M<)"`/MI-*%```]]K!X@:!XL`/``")\,'@$O?8)0``_``)
-MPHF13)D``.L.2(M%(,>`3)D```````!(BU4@BX(HH@``@.3]B8(HH@``2(M5
-M((N"**(``"7_`_[_@,P(B8(HH@``2(M%(,>`8(````\```!F@[V"`P``0G8.
-M2(M%(,>`5*(```````!(BT4@QX!XF```#@```(.]?`,```IT'(.]?`,```ET
-M$X.]?`,```IU.F:#O8`#```#=S"Y`0```&9!@3PDG@ET"69!@3PDHPEU!;D`
-M````2(M5((N"3*(``#G(=`:)BDRB``!(C50D1$B+="082(GOZ`````"Z`P``
-M`(7`#X3W!P``@WPD0`9T$8.]M`,```!T"$B)[^@`````#[=4)`1(C4PD1$B+
-M="082(GO2(M<)"#_DY@N``"Z`P```(7`#X2U!P``0?9$)`)`=%^#O7P#```*
-M="R#O7P#```)=".#O7P#```*=0IF@[V``P```W802(M$)"!F@;@H%````E!V
-M'T$/MT0D`B6@````/:````!T#4B+="082(GOZ`````!,B>9(B>_H`````$B+
-M="082(GOZ`````"Z`P```(7`#X0T!P``@WPD/`!T#DB+12"+5"04B9!`$0``
-M2(M-($B+7"0@#[:3^"T```^V@_DM``#!X`@)P@^V@_HM``#!X!`)P@^V@_LM
-M``#!X!@)PHF1`(```$B+32`/MI/]+0``P>((#[:#_"T```G0"T0D"`N#O#$`
-M``T``(``B8$$@```BW0D0$B)[^@`````2(M-(`^VDP0N```/MH,%+@``P>`(
-M"<(/MH,&+@``P>`0"<(/MH,'+@``P>`8"<*)D>"```!(BTT@#[:3"2X``,'B
-M"`^V@P@N```)T(F!Y(```$B+52"+@A!````+1"0,B8(00```2(M%((M4)"R)
-MD!1```!(BT4@BTPD*(F(&$```$B+12"+7"00B9A8@```2(M-($B+1"0@#[:0
-M_BT```^V@/\M``#!X`@)PDB+7"0@#[:#`"X``,'@$`G"#[:#`2X``,'@&`G"
-MB9$(@```2(M-(`^VDP,N``#!X@@/MH,"+@``"=")@0R```!(BU4@BX/$,0``
-MB8(8@```2(M%(,>`@````/____](BW0D&$B)[^@`````N@,```"%P`^$B04`
-M``^VM?`3``"Z`0```$B)[^@`````3(GF2(GOZ``````/MX6$`P``)?````"#
-MZ#"#^#]W0$B+A>@3``#V0`-`=0=F@W@"`'DL2(N%Z!,``/9``T`/E,`/ML"#
-MP`Q(BTT@BY$DF```@^+P@^`/"<*)D228``!(BT4@BX`4F0``B<*!XO\_``!!
-M]D0D`B!T'8T$E0````")P+JCBRZZ2`^OPDC!Z"")PL'J!.L4B="ZS<S,S$@/
-MK\)(P>@@B<+!Z@-(BT4@QX`<F````0```$B+A>@3``#V0`-`=`:-?!)DZQI(
-MBX7H$P``9H-X`@!Y"8T\E60```#K`XUZ9.@`````2(M%($2+J`B8``#'@`B8
-M````.```NP$```!(BT4@BX`DG```J!!T(;_(````Z`````")V/_#@_@3?PY(
-MBT4@BX`DG```J!!UWTB+12!$B:@(F```2(M5((N"8)@``(/(`XF"8)@``$$/
-MMT0D`B6@````/:````!T1TB+1"0@@[BP,0```G0Y2(M5((N"()D``(#,\(F"
-M()D``$B+52"+@B"9```-```!`(F"()D``$B+5"0@QX*P,0```0```.L/2(M,
-M)"#'@;`Q````````2(GOZ`````"[`````+X!````C02=`````$B82(M]((GR
-MB=G3XHF4.``0``#_PX/["7[?2(M<)"#'@Z1(````````NP````!F@[V8`P``
-M`'07B=Y(B>_H`````/_##[>%F`,``#G#?.E(BT0D(,>`#"X``&4)"`"#?"1`
-M!G4*QX`,+@``91D(`$B+52!(BTPD((N!#"X``(F"H````$B+52"+@JP````-
-M```'`(F"K````(.]!!0```!T"$B)[^@`````N0````"Z`0```+Y@F```2(GO
-MZ`````"+="1`2(GOZ`````!(BU4@BX(@@```)?__?_Z)@B"```"#O7P#```%
-M=Q.#O7P#```%=29F@[V``P``!W8<2(M%(,>`&($``*H``0!(BT4@QX`<@0``
-M$#(``$B+12#'@`B!``!2````0?9$)`,!=`Y(BUPD(`^V@T84``#K#$B+5"0@
-M#[:"1Q0```^^T$R)YDB)[^@`````08G!2(M,)"!$BX'0,0``08/@/P^_@>PQ
-M``!$B<$IP4B+7"08#[Y3!HT$$#G11`]'P`^^0P4!P$$/OM&)QBG603GP=A!(
-MBU0D(`^_@NPQ``!$C00P2(M,)""+N=`Q``"!YP`_``#![P@/OX'L,0``B?DI
-MP4B+7"08#[Y3!HT$$#G1#T?X#[Y#!0'`00^^T2G0B<(YQW8/2(M,)"`/OX'L
-M,0``C3P02(M<)""+L]`Q``"!Y@``/P#![A`/OX/L,0``B?$IP4B+7"08#[Y3
-M!HT$$#G1#T?P#[Y#!0'`00^^T2G0B<(YQG8/2(M,)"`/OX'L,0``C30008/X
-M0+@_````1`]#P(/_0`]#^(/^0`]#\$2)PH/B/XGXP>`()0`_```)PHGPP>`0
-M)0``/P`)PDB+12")D.B```!(BUPD((.[P#$```!T$$B+52"+@\`Q``")@B"!
-M``!(BT0D((.X\#$``/]T#HNP\#$``$B)[^@`````2(M4)""#NO0Q``#_=`Z+
-MLO0Q``!(B>_H`````$B+3"0@@[GX,0``_W0.B['X,0``2(GOZ`````"#O:@#
-M````=!!(BU4@BX6H`P``B8)(@```BUPD0(F=C`,``(-\)#P`='%(BT0D&/9`
-M!`)U!(!@!/Y(BU0D&`^W0@)F08E$)`(/MD($08A$)`0/MD(%08A$)`4/MD(&
-M08A$)`8/MD('08A$)`=(BX7H$P``2,=`,`````!(BYWH$P``2(GOZ`````!(
-MB4,HO@$```!(B>_H`````+H!````ZQ%(BTPD,(,Y`'0"B1&Z`````(G02(/$
-M2%M=05Q!74%>05_#B[>T`P``0/;&`W0@2(M/((N11)D``('B____WXGP@^`!
-MP>`="<*)D429``")\(/@#'0KJ`1U%$B+5R"+@M"```"#X..)@M"```##2(M7
-M((N"T(```(/('(F"T(```)##2(/L"/^7D"X``(7`#Y7`#[;`2(/$",-!5T%6
-M055!5%532(/L"$B)_4F)]$&]`0```$F)_^@`````28G&NP````!F@[V8`P``
-M`'0;B=Y(B>_H`````(7`=1W_PP^WA9@#```YPW+EN@````!%A>T/A+L!``#K
-M"$&]`````.OH2(M%(,>`?)D```$```"[`````$B+12"+@""<``"%P'43OP4`
-M``#H`````/_#@_MC=N'K!8/[8W8*N@````#I;@$``$R)]DB)[^@`````N@``
-M``"%P`^$5@$``$B+12"+@!29```E_S\``$'V1@(@=!?!X`*)P+JCBRZZ2`^O
-MPDC!Z"#!Z`3K$HG`NLW,S,Q(#Z_"2,'H(,'H`XUX9.@`````2(GB3(GV2(GO
-MZ`````"Z`````(7`#X3T````2(M%(,>`?)D```````!!]D8"0'19@[U\`P``
-M"G0H@[U\`P``"70?@[U\`P``"G4*9H.]@`,```-V#&9!@;\H%````E!V'4$/
-MMT0D`B6@````/:````!T"TR)]DB)[^@`````3(GF2(GOZ`````!(BU4@BX)@
-MF```@\@"B8)@F```0?9&!`)U!4&`9@3^00^W1@)F08E$)`)!#[9&!$&(1"0$
-M00^V1@5!B$0D!4$/MD8&08A$)`9!#[9&!T&(1"0'2(N%Z!,``$C'0#``````
-M2(N=Z!,``$B)[^@`````2(E#*+X!````2(GOZ`````"Z`0```(G02(/$"%M=
-M05Q!74%>05_#2(M'((N`!(```"7___S_@_X!=$^#_@%_!H7V="F0PX/^!G0'
-M@_X(=#J0PTB+5R`-```!$(F"!(```$B+5R"+0A2#X-_K&4B+5R`-```"$(F"
-M!(```$B+5R"+0A2#R"")0A3#2(M7(`T````0B8($@```PTB#[`B^`@```.@>
-M!0``2(/$",-32(G[N@$```"^`````.@`````N@````"%P'0/OA,```!(B=_H
-M\`0``(G"B=!;PTB#["A(B5PD"$B);"003(ED)!A,B6PD($B)^TB)];X3````
-MZ,($``"Z`````(7`#X0``@``N@$```"^`````$B)W^@`````N@````"%P`^$
-MX0$``+X`````2(G?Z(D$``"Z`````(7`#X3'`0``2(7M#X2Y`0``@[M\`P``
-M"G0<@[M\`P``"703@[M\`P``"G4O9H.[@`,```-W)4&]"`````^W10*H('57
-M)=````"Y!````#W`````#X6L````ZT`/MX.$`P``)?````"#Z#"#^#]V$H.[
-M?`,```=T"8.[?`,```MU0T&]"`````^W10*H('4,)=`````]P````'4'N>L`
-M``#K8_9%`T!T![GJ`0``ZU9F@WT"`'D'N>H"``#K2+GJ````ZT%!O0`````/
-MMT4"J"!U#"70````/<````!U![FK````ZR#V10-`=`>YJ@$``.L39H-]`@!Y
-M![FJ`@``ZP6YJ@````^W10*H0'06J"!U#"70````/<````!U!D&#S03K#D2)
-MZ(/(`?9%`D!$#T3H1(GH@\@"]D4#`40/1.CV10(0#Y7`1`^VX$>-)&1(BT,@
-MBY!\F```#[=%`J@@=0PET````#W`````=3!(BT,@1(F@!)@``$B+0R!$B:@`
-MH@``.<IT1$B+0R")B'R8``"_+`$``.@`````ZRXYRG042(M#((F(?)@``+\L
-M`0``Z`````!(BT,@1(F@!)@``$B+0R!$B:@`H@``N@$```")T$B+7"0(2(ML
-M)!!,BV0D&$R+;"0@2(/$*,-!5D%505154TB)^TF)]DB)U4F)_<<"`````.@`
-M````28G$N`````!-A>0/A&$"``"#N[`Q```"=`F#N[`Q````=0?'10`!````
-M08.]L#$```$/A4@!``!(BT,@BX`@F0``J0```0`/A3,!``!!QX6P,0``````
-M`,=%``$```"^`````$B+0R"+N!"<``"+B!2<``!$BX`8G```A?]T!(7)=1Q(
-MBU,@BX(@F0``#0```0")@B"9``#_QH/^"7[%B?C1Z(G*T>H!T(G.P>X'B<'!
-MZ0</A!T!``"#_@$/CA0!``!$B<#WV$0/OL!$B<"9]_E!B<"#^.!]"$&XX/__
-M_^L,@_@@N!\```!$#TW`B?BZ`````/?VC7"`@_[P?0>^\/___^L+@_X0N`\`
-M```/3?!(BTL@BY$@F0``@>(?^/__1(G`P>`%)>`'```)PHF1()D``$B+2R"+
-M@2"9``"#X.")\H/B'PG0B8$@F0``2(M3((N"()D``(#,"(F"()D``$''A;`Q
-M```"````0<=$)!`!````18A$)!1!B'0D%>M600^W1@(EH````#V@````=$5!
-M@[VP,0```G4[08-\)!``=3-(BU,@BX(@F0``@,SPB8(@F0``2(M3((N"()D`
-M``T```$`B8(@F0``0<>%L#$```$```!,B>9(B=_H`````$'V1"0"`G5W2(M3
-M((N"8)@``(/(`HF"8)@``$$/MU8"]L8!=1D/MX.$`P``)?````"#Z#"#^#]W
-M4_;"0'1.@[M\`P``!W1%@[M\`P``"W0\@[M\`P``"G0S@[M\`P``"70J@[M\
-M`P``"G4*9H.[@`,```-V%TB)W^C6'@``ZPUF08-.`@)F08-D)`+]N`$```!;
-M74%<05U!7L-(@^P82(D<)$B);"0(3(ED)!!(B?V)\X7VN/____]!B<1$#T7F
-M@[]\`P``"703@[]\`P``"G4-9H._@`,```-W`X/C[TB+12"+4`R)F`!```"_
-M#P```.@`````@^,#1(GB@^(#B=F^`$```$B)[^@`````08G$]L,!=2M(BT4@
-MQT`4`````+H!````O@````!(B>_H`````(7`=`I(BT4@BX#`````1(G@2(L<
-M)$B+;"0(3(MD)!!(@\08PTB+1R"+@&28``#!Z!-F)?\!]L0!=`1F-0#^F,,/
-MMT8")>`!```]P````'0I/<````!_"3V@````=!+K*3U``0``=2(/MX>$%```
-MZQ`/MX>&%```ZP</MX>(%```9HD"N`$```##N`````##2(/L*$B)7"002(EL
-M)!A,B60D($B)^TB)]4B+1R"+@&"8``!!O`````"H`G4TZ`````!!B<1(C50D
-M#DB)[DB)W^AL____A<!T#69$.V0D#GX+9H--`@)!O`````!F1(EE%D$/O\1(
-MBUPD$$B+;"083(MD)"!(@\0HPTB)_O:'D`,```1T=DB+1R#'@"`$```!````
-M2(M'(,>```8```````!(BU<@BX(`!@``@\@(B8(`!@``2(M'(,>`!`8```$"
-M$`!(BT<@QX`@!@```````+D`````2(M&((F(``0``$B+5B!(8\$/MH0'*#$`
-M`(F"!`0``/_!@_E_?MJ0PT%505154TB#[`A(B?U!B?2_`````$2-4O]!P>H#
-M1(U"_T&#X`=!B?%!NP````"%]GYFNP$```"--,T`````1XTL`4&#_0FX"```
-M`$0/0^B)V$2)Z=/@_\B)VD2)P=/B_\HQT(GQT^!$B=(C1)4`T^A$B<'3Z$2)
-MV=/@"<=$B>E$*<%!`<M'C4P(^$&X`````$'_PD6%R7^F1(GFZ`````!(@\0(
-M6UU!7$%=PTF)^0^W0@(EX`$``#W`````="L]P````'\,/:````!T%NG!````
-MN@`````]0`$``'01Z;````"Z`0```.L%N@(```!(8])%#[>$4:(4``!!#[>$
-M4:@4``#!X`9!"<!!#[>$4:X4``#!X`Q!"<!!#[>$4;04``#!X!)!"<!!#[>$
-M4;H4``#!X!A!"<!!#[>,4<`4``!!#[>$4<84``#!X`8)P4$/MX11S!0``,'@
-M#`G!00^WA%'2%```P>`2"<%!#[>$4=@4``#!X!@)P8/^`70,@_X!<A>#_@)T
-M!^L*1(G!ZPM!B<CK!K@`````PT0YP74/2(M7((N""*(``(#DW^L-2(M7((N"
-M"*(``(#,((F""*(``$&)L:PQ``!(BT<@1(F`8)D``$B+1R")B&29``"X`0``
-M`,-3@[]\`P``"G1'@[]\`P``"70^@[]\`P``"G4*9H._@`,```-V*X._?`,`
-M``=T(H._?`,```MT&0^WAX0#```E\````(/H,+H@````@_@_=P6Z*````+D`
-M````#[<&B=.Z`````/?SA=)T#HU"]H/X#;@!````#T/(B<A;PT%7059!54%4
-M55-(@^P82(G]28GV28G\1`^W;@)!P>T'08/E`0^W1@(E\`$``#U``0``=&0]
-M0`$``'\R/<`````/A-,````]P````'\0/:`````/A+D```#IQ````#W0````
-M#X2Q````Z;0````]P`@```^$H0```#W`"```?P<]4`$``.L,/4`)``!T"SU0
-M"0``#X6)````0;\`````#[>%A`,``"7P````@^@P@_@_=GF#O7P#```'='"#
-MO7P#```+=&>#O7P#```*=%Z#O7P#```)=%6#O7P#```*=0IF@[V``P```W9"
-M2(M-((N11)D``(/BQTF+A"3P+0``#[\`P>`#@^`X"<*)D429``#K&D&_`0``
-M`.L20;\"````ZPJX`````.D6`P``2(M-((N1$)D``('B!OS__TECWT$/MX1<
-MG!0``,'@!`G"@\H!B9$0F0``08NT)*PQ``!,B?)(B>_H`````$B+52!!#[^$
-M7(04```E_P$``(#,`HF":)D``&9!@;PD*!0``/]/=CE!]D8"$'0R26/%00^W
-MM$3\%```00^VO`0$%0``10^VA`0&%0``10^WC$0`%0``00^WA$0(%0``ZS-)
-M8\=!#[>T1%H4``!!#[:\!'X4``!)8\5%#[:$!($4``!%#[>,1&`4``!!#[>$
-M1.H4``!FB00D2(M-((N11)@``('B?\#__XGPP>`')8`_```)PHF11)@``$B+
-M32"+@5"8``"P`$`/MM<)T(F!4)@``$B+32"+D5"8```P]D2)P,'@""4`_P``
-M"<*)D5"8``!(BTT@BY%(F```@>+_#_S_1(G(P>`,)0#P`P`)PHF12)@``$B+
-M?2!)8_=!#[>4='(4``")T,'@&,'B$`G000^WC'1X%```B<K!X@@)T`G(B8<T
-MF```2(M-((N1*)@``##V00^WA'1F%```P>`("<*)D2B8``!(BTT@BY%DF```
-M@>+_#_C_00^WA'1L%```P>`,)0#P!P`)PHF19)@``+L"````9D&!O"0H%```
-M`C!W&6:!O7H#```B$'4K0?9&`D!T)+L(````ZQU,B?9(B>_H`````(7`=`Y)
-M8\=!#[>$1-X4```!PTB+32"+D229``"`X@&-!!LE_@````G"B9$DF0``08-^
-M$`!T#$$/OG8400^^?A7K%4ECQ4$/M[1$;A4``$$/M[Q$<A4``$B+32"+D2"9
-M``"!XA_X__^)\,'@!27@!P``"<*)D2"9``!(BTT@BX$@F0``@^#@B?J#XA\)
-MT(F!()D``$B+52"+@B"9``"`S`B)@B"9``!F08&\)"@4````0'9!00^W1@(E
-MT````#W0````=0UF08&\)"@4``#_3W8C2(M-((N1#*(``('B__\#_XL$),'@
-M$B4``/P`"<*)D0RB``!F08&\)"@4````4'8.2(M%(,>`X)D```````"X`0``
-M`$B#Q!A;74%<05U!7D%?PT%7059!54%455-(@^Q(28G]28GT2,=$)!``````
-M2,=$)#``````2,=$)#@`````9L=$)`P``,=$)`@`````QT0D!`````#'1"08
-M`0`"`,=$)!P"``$`9L=$)"`!`&;'1"0B`@!FQT0D)`$`#[=>`L'K!P^W!H/C
-M`70-C02`1(VT`"BF___K"XT$@$2-M`"80```9D&#?"0X`'0900^W1"0X9HE$
-M)`[K=F:!X?\_9HE,)`[K7V;'1"0.`(!!OU<```!!]D0D`A"XK@```$0/1?B]
-M``````^W]8G:3(GO0?^5<`,``(G!9CT`@'0G00^W_D$/M_>)^"GPB<J!XO\_
-M```YT'\'C00^.=!]G?_%9H/]!';"#[=4)`YF08E4)#AF@7PD#@"`#X43`0``
-M28M5((N"()D``*D```!`#X1Y!```BX(,F0``)?___P")@@R9``!)BT4@BY`@
-MF0``@>+___^/B9`,F0``28M%(,>`H)D```````!)BT4@QX"`F0```````$F+
-M52"+@H29```E``#P_XF"A)D``$F+12#'@)B9````````28M5((N"G)D``"4`
-M`/#_B8*<F0``28M%(,>``)D```````!)BT4@QX`$F0```````$F+12#'@`B9
-M````````28M5((N"#)D``"4`P/__B8(,F0``28M%(,>`B)D```````!)BT4@
-MQX",F0```````$F+12#'@)"9````````28M5((N"E)D``"4`P/__B8*4F0``
-MZ7L#```/MTPD#D$/M\8IP4$/MT0D`B7P`0``/=`````/A)P````]T````'\,
-M/<````!T1.FZ````/4`!``!T##U0`0``='OIIP```(G+P>,12&/#2&G`'X7K
-M44C!Z"")QL'^`XG8F2G6B70D"(GRP?H*B50D!.M!B<O!XPA(8\-(:<"5($\)
-M2,'H((G&T?Z)V)DIUHET)`2)RL'B$4ACPDAIP!^%ZU%(P>@@B<;!_@.)T)DI
-MUHET)`AFQT0D##4,ZS&)RL'B$$ACPDAIP!^%ZU%(P>@@B<;!_@.)T)DIUHET
-M)`B)\L'Z"HE4)`1FQT0D#&H8:<GH`P``P>$$#[=4)`R)R(G3F??[B<&H#W0-
-M0;@$````3(U,)!CK"T&X`P```$R-3"0@O0````!F187`#X0*`0``B<_!_P1!
-MN@$```!)NP````#_____@_\<#X\M`@``#[?%C70X&8/^('<V@_X9?Q)$B=")
-M\=/@"T0D$$PA7"00ZT6#_AI^18U._T2)T]/CB=D+3"003"%<)!!("4PD$.LK
-MC4[?@_D3=R-(BU0D$$C!ZB!$B=#3X`G02,'@(+K_____2"%4)!!("40D$(U&
-M`8/X#W<4#[?%00^W!$&-3#8"T^`)1"0PZU*-1O&#^`]W%`^WQ4$/MP1!C4PV
-MXM/@"40D-.LVC4;A@_@/=Q0/M\5!#[<$08U,-L+3X`E$)#CK&HU&T8/X!G<2
-M#[?%00^W!$&-3#:BT^`)1"0\_\4/M]5!#[_`.<(/C`O___])BU4@BX(,F0``
-M#0```/^)@@R9``!)BT4@BY`@F0``@<H```!PB9`@F0``28M-((M$)`3!X!0E
-M``#P/XM4)`B!XO__#P`)T`T```!`B8&@F0``28M%((M,)!")B("9``!)BTT@
-MBX&$F0``)0``\/](BU0D$$C!ZB"!XO__#P`)T(F!A)D``$F+12"+7"00B9B8
-MF0``28M-((N!G)D``"4``/#_"=")@9R9``!)BU4@BT0D,(F"`)D``$F+52"+
-M1"0TB8($F0``28M5((M$)#B)@@B9``!)BTT@BX$,F0``)0#`__^+5"0\@>+_
-M/P``"=")@0R9``!)BU4@BT0D,(F"B)D``$F+52"+1"0TB8*,F0``28M5((M$
-M)#B)@I"9``!)BTT@BX&4F0``)0#`__^+5"0\@>+_/P``"=")@929``!(@\1(
-M6UU!7$%=05Y!7\.Z````9/9&`A"X````R$@/1=#V1@-`=`5(T>KK"V:#?@(`
-M>01(P>H"2`^W#DB)T+H`````2/?Q2(G&0;D?````2(GP1(G)2-/HJ`%U!4G_
-MR77NN"8```!,*<A)B<&X%P```(G"1"G*N`$```")T=/@2)A(C00PNA@```!!
-MB=!%*<A$B<%(T^A(BW<@BY84F```@>+__P$`P>`1"<*)EA28``!(BW<@BY84
-MF```@>+_'_[_1(G(P>`-)0#@`0`)PHF6%)@``,-(@^P(@_Y`N#\````/0_!F
-MB;>L`P``2(NWZ!,``$B-5"0$Z`````!(@\0(PT%505154TB#[!A(B?U)B?1)
-MB=5(B?N+MX!(``!(B[]X2```Z`````!(C;V$2```OB````#H``````^WC:P#
-M``!F@_E`N#\````/3<AF@_D^?PJX`````&:%R74.BX6P`P``#[>$```````/
-MO\D/O]!(C40D%DB)!"1,C4PD%$&X`0```$R)YDB)[^BF`@``N@````"%P`^$
-MC`(``$V)Z$R)X4B-5"062(UT)!1(B>__DZ`N``"Z`````(7`#X1F`@``@[U\
-M`P``!W0V@[U\`P``"W0M@[U\`P``"G0D@[U\`P``"70;@[U\`P``"G4*9H.]
-M@`,```-V"&:#@Z)(```$0;@`````#[>3[#$``$ECP&8!E$.$2```9H.\0X1(
-M```_=@IFQX1#A$@``#\`0?_`08/X#W;79H.[5A0```$/A[L```!F@[V"`P``
-M07=D00^W1"0")=`````]P````'529D&!/"2T"74H#[:32A0```^W@U04```I
-MPDACPDAIP&=F9F9(P>@@T?C!^A]F*=#K%@^V@TH4``!(F$AIP&=F9F9(P>@@
-MT>@/M_!(B>_HX@<``$&X`````$*-#(4`````2&/)2(M]($EC\$B+@WA(```/
-MMU2P`L'B&('*``#_``^W!+#!X`@,_R7__P``"<*)E#F`H0``0?_`08/X'WZY
-M2(M-(`^WDXI(``"#XC_!XA@/MX.(2```@^`_P>`0"<(/MX.&2```@^`_P>`(
-M"<(/MX.$2```@^`_"<*)D329``!(BTT@#[>3DD@``(/B/\'B&`^W@Y!(``"#
-MX#_!X!`)P@^W@XY(``"#X#_!X`@)P@^W@XQ(``"#X#\)PHF1.)D``$B+32`/
-MMY.82```@^(_P>(8#[>#ED@``(/@/\'@$`G"#[>#HD@``(/@/\'@"`G"#[>#
-ME$@``(/@/PG"B9$TH@``2(M-(`^WDZ!(``"#XC_!XA@/MX.>2```@^`_P>`0
-M"<(/MX.<2```@^`_P>`("<(/MX.:2```@^`_"<*)D3BB``!(BT4@@[O,,0``
-M`'0'NG\```#K!;H_````B9`\F0``N@$```")T$B#Q!A;74%<05W#05=!5D%5
-M05154TB![+@```!(B;PDB````$F)]$2)1"1L3(E,)&!FB90DA@```&:)3"1P
-M2(G]2(GX2`6$2```2(E$)%AFQT0D0#\`9L=$)#`_`&;'1"00```/OD8%`<!F
-MB40D+DB+E"3P````9L<"P?](BUPD8&;'`S\`2(N\)(@```#H`````$&)Q;L`
-M````2(N$)(@```!F@[@L%0````^$B````&9%#[;]10^V]42)\H/B^(E4)`Q(
-M8\-F@[Q%+A4```!T6F9$.;Q%+A4``'02#[>$12X5``"#X`<,X$$YQG4]2&/#
-M2,'@!DB-M"B,&0``00^W/"3HB@8``(%\)`S@````=1-F.T0D0(M4)$`/1M!F
-MB50D0.L'9HE$)$#K#?_##[>%+!4``#G#?(M!#[=$)`(ET````#W`````#X6A
-M````08/E^$&#S0&[`````&:#O2P5````#X2/````9D4/MO5%#[;M18GO08/G
-M^$ACPV:#O$4N%0```'199D0YM$4N%0``=!(/MX1%+A4``(/@!PS@03G%=3Q(
-M8\-(P>`&2(VT*(P9``!!#[<\).C4!0``08'_X````'439CM$)#"+5"0P#T;0
-M9HE4)##K!V:)1"0PZQC_PP^WA2P5```YPWR,ZPF+7"1`9HE<)#!!]D0D`P%T
-M"0^VA484``#K!P^VA4<4```/OM!,B>9(B[PDB````.@`````B<-!]D0D`D`/
-MA-X!``!!@'PD`@!Y&$R-A"2@````#[>-5!D``$B-E589``#K%DR-A"2@````
-M#[>-`AD``$B-E009``!,B>9(B[PDB````.A'!@``#[=$)$`/MU0D+@^^RRG*
-M.<*)Q@].\D'V1"0"$'1`9H&]*!0````P=A$/O]8/MX4V%```.=")U@].\&:!
-MO2@4``#_/W8908!\)`(`>1$/O]8/MX4X%```.=")U@].\`^_U@^WA"2F````
-M.=`/3M!FB50D$`^WA"2&`````<")UF8IQK@`````#TCP9CET)'"+1"1P#T[P
-M@WPD;``/A-````!(BU0D6&:)<@AFB7(&9HER!&:)<@)FB3*)]XN$)*0```!F
-M.?!V`HGP2(M4)%AFB4(*#[>$)*(```!F.P)V`P^W`DB+5"189HE"#(N$)*``
-M``!F.P)V`P^W`DB+5"189HE"#HG!9H&]*!0``/\_=D(/O]9!@'PD`@!Y"0^W
-MA3P4``#K!P^WA3H4```YPGP:08!\)`(`>0D/MX4\%```ZPL/MX4Z%```ZP*)
-M\$B+5"18ZPA(BU0D6`^W`F:)0AY(BY0D\`````^_`HF%Z#$``.L4B?</O]8/
-MMX0DH````#G0B=$/3LA(BT0D8&:)"$B+E"3P````9HDZ00^W1"0"J"!U$"70
-M````/<`````/A0X!``!,C80DD`````^WC709``!(C95V&0``3(GF2(N\)(@`
-M``#H;P0```^W3"0P#[=$)"X/OM,IT#G(B<X/3O`/O]8/MX0DE@```#G0B=8/
-M3O`/MX0DA@````'`9BG&N``````/2/"+1"1P9CGP#T[P@WPD;`!T7@^_U@^W
-MA"26````.=`/3\)(BUPD6&:)0Q`/MX0DE````#G0#T_"9HE#$HG!9HE#%`^W
-MA"22````.=`/3\)FB4,69HE#&`^WA"20````.=`/3\)FB4,:B<)FB4,<ZQ\/
-MO]8/MX0DE````#G0B=$/3L@/MX0DD````#G0#T[02(M$)&!F.Q!]`V:)$$B+
-ME"3P````9CL*?@-FB0J#?"1L`'0G2(N<)/`````/OP.)A;@Q```/MX6X,0``
-M2(N4)(@```!FB8*N`P``N`$```!(@<2X````6UU!7$%=05Y!7\-!5T%6055!
-M5%532(/L&$F)_4F)]T&)UO^7J"X``+H`````A<`/A+,```!%#[>EK`,``&9!
-M@_Q`N#\```!$#TW@9D&#_#Y_#6;'1"02``!F187D=11!BX6P`P``#[>$````
-M``!FB40D$KT`````1#GU<V:)Z$F-',=(C40D%DB)!"1,C4PD%$&X`````$$/
-MO\P/OU0D$DB)WDR)[^CN^?__N@````"%P'0T9@^^0P9F.40D%GT(#[9$)!:(
-M0P9F#[Y#!V8Y1"04?0@/MD0D%(A#!__%1#GU<IJZ`0```(G02(/$&%M=05Q!
-M74%>05_#05154TB#["")]4B)^T0/MZ=2%```2(VWA$@``$B)Y[H@````Z```
-M``!!N0@```!!#[?!9D0I)$2_`````$&Z`````$F)P&9"@SQ$`'D'9D+'!$0`
-M`&:#_PAU![\/````ZT=!#[?)#[\43`^W]P^WA'.$2```.<)U+F:#O'.$2```
-M`'4&9O\$3.L39D&#^C)V!V9"_P1$ZP5F0O\,1+\`````0?_"ZP+_QV:#_P]V
-MET$/M\%F@SQ$/WX&9L<$1#\`00^WP0^WA$.$2```*>BZ``````](PD$/M]%(
-M#[\,5$B+DWA(``!(F`^W!$)FB01*0?_!9D&#^0X/AC'___]!N0@```!!#[?1
-M#[<$5&:)A%.$2```0?_!9D&#^0YVYDB#Q"!;74%<PT%455-(@^P@2(GS08G\
-MN@````!(8\IF@SS+`'00#[<$RV:)1$P0_\*#^@=^YHG5#[?22(UT)!!!#[?\
-M3(U$)`Y(C4PD#.@`````N@`````YZGT=BT0D#&8[1"00=!*)P?_".>I]"DAC
-MPF8[3$00=?"+1"0,9CM$)`YU!F9$.>!T"DACPH-\PP0`=`I(8\(/MT3#`NL%
-MN#\````/M\!(@\0@6UU!7,-308G208G)#[?!00^WT`^OPKH`````A<!T:8G(
-M9D$Y\G1>#[?'#[?6*=!KR&1!#[?"*=")PHG(B=.9]_N)P42)R&:%R7@Z1(G`
-M9H/Y9'\Q#[_)00^WT`^OT;AD````*<A!#[?)#Z_!`<)(8\)(:<`?A>M12,'H
-M(,'X!<'Z'V8IT`^WT(G06\-!5T%6055!5%532(/L*$F)]TB)U4R)!"1!B<V^
-M``````^WP8G!.<9]%TACQDB-%(`/MU15"&:)5$00_\8YSGSI00^WW4B-="00
-M00^W/TR-1"0.2(U,)`R)VN@`````0;P`````0;D`````O@`````YWGTMBWPD
-M#`^W3"0.B=I(8\9F.WQ$$'4#08GQ2&/&9CM,1!!U!4&)].L&_\8YUGS>10^W
-MY$^-)*1-`>1&#[=$)09!#[?92(T<FT@!VP^W3!T&1`^W;"0.1`^W="0,00^W
-M/T2)ZD2)]NB=_O__2(L4)&:)0@9&#[=$)00/MTP=!$$/MS]$B>I$B?;H>_[_
-M_TB+%"1FB4($1@^W1"4"#[=,'0)!#[<_1(GJ1(GVZ%G^__](BQ0D9HE"`D8/
-MMT0E``^W3!T`00^W/T2)ZD2)]N@W_O__2(L4)&:)`DB#Q"A;74%<05U!7D%?
-MPP^W_VO_9`^WTDB-%%8/MP9KP&2#Z`HYQW(:#[="_FO`9(/`"CG'=B`/MT+^
-M9D&)`&:)`<,/MP;K\P^W!F:)`0^W1@)F08D`PT@YUG,L1`^_SP^_!FO`9$0I
-MR(/`"8/X$G;2#[=&`FO`9(/H"CG'<LE(@\8"2#G6<MB0PTB-E]`M```/MX>$
-M`P``)?````"#Z#"#^#]W-(L%`````(F'T"T``(G`2(T$P$B-!(4`````2(E"
-M(,="&`$```#'0@P4````QT(050```,.+!0````")`HG`2(T$P$B-!(4`````
-M2(E"(,="&`$```#'0@P4````QT(0(P```,-32(GZ2(GS#[>'A`,``"7P````
-M@^@P@_@_=U&^!P```/^7B"X``$B)Q[D`````NB0```"^`0```.@@Y/__0;D`
-M````0;AK````OP````"^:P```(/X`75Y0;A3````OE,```#'0Q`W````ZV6^
-M!P```/^2B"X``$B)Q[D`````NB4```"^!@```.C/X___0;D`````C4@$@_@_
-MNC(```!!B=!$#T7!ND````")UT$/1/F-=S)!C5$4@_@_00]%T8E3#(U.\8U6
-M!8/X/P]$T8E3$(M3!+@`````1#G*<@5$.<)V#3GZ<@0Y\G8%N`$```!;PP^_
-MA^PQ```#A^@Q``!(BU<@P>`))0!^``"`S(")@C"9``#'A[0Q```!````PTB#
-M[!A(B1PD2(EL)`A,B60D$$B)^TF)_$B-K]`M``"#?1@`=0JX`````.GA````
-M@[^T,0```0^%S@```$B+1R"+@#"9``!FA<`/B+L```")PL'J&8E5!"4``(`!
-MP>@7@_@"=1QF@[^"`P``078.#[>'4A0```'0B44$ZP2#100%00^WA"2$`P``
-M)?````"#Z#"#^#]W'TR)Y^B8`0``BT4$.T44<@@K112)103K!\=%!`````#'
-M@[0Q````````2(GN3(GGZ!?^__^%P'4\2(GN3(GGZ$H```"%P'0M2(GN3(GG
-MZ%,```"%P'X>QX.T,0```@```,>#R#$```$```#'@[`Q````````BX.T,0``
-M2(L<)$B+;"0(3(MD)!!(@\08P[@`````BU8$.U8,=@4[5A!R!;@!````PP^W
-MAX0#```E\````(/H,(/X/TC'P@````!(Q\``````2(G'2`]'^HL&2(T$P$B-
-M1(<(2(E&((M&!#M&$')3@SX`=0:X_____\.+1@2)1@@[1A!R-X,^`'0R_PZ+
-M%DB-%-)(C1272(M.((M"&"M!$`'`BTX(*<&)3@A(@\((2(E6(#M.$'(%@SX`
-M=<ZX`0```,.+1@0[1@QW7(L'_\@Y!G4&N/[____#BT8$B48(.T8,=SV+!__(
-M.09S-?\&BQ9(C1322(T4ETB+3B"+0A@K01`!P(M.""G!B4X(2(/""$B)5B`[
-M3@QW"(L'_\@Y!G++N`(```##N`````##2(/L&$B)'"1(B6PD"$R)9"002(G[
-M2(VOT"T``,=%%`````"^!P```/^7B"X``$B)Q[D`````NB0```"^`0```.C#
-MX/__@_@!=5M(BT4@1`^_(+X'````2(G?_Y.(+@``2(G'N0````"Z(````+X$
-M````Z)'@__]!@_P!="5!@_P!<@Y!@_P"=!%!@_P#=!'K%,=%%`````#K"XU$
-M`/OK`@'`B4442(L<)$B+;"0(3(MD)!!(@\08PT%505154TB#[`A(B?V)]T&)
-MU(G+18G%B=;H`````$&)P42-0_]!P>@#C7O_@^<'187D?GI!NP$```!&C13M
-M`````+L(````08T,/(/Y";@(````#TW(1(G8T^")P8U1_T2)V(GYT^#_R#'0
-M08G%1(G10=/E1(G&1(GJ]](C5+4`1(G(B?G3X$2)T=/@1"'H"=")1+4`1HUD
-M)_B)V2GY0=/IOP````!!_\!%A>1_F4B#Q`A;74%<05W#05=!5D%505154TB#
-M[`A)B?])B?;V1@-`=`>^``(``.LB9H-^`@!Y![X`!```ZQ'V1@(0O@`!``"X
-M`@````]%\$R)_^@`````2(G%0;T`````1#LH?4A)8\5(C01`2(U$A2`/ME@(
-MP>,"2&/;38MG(`^V2`M!N`````"Z#@```$B)[DR)_^@`````#[?`0HF$(P"'
-M``!!_\5$.VT`?+A!]D8"$`^%M````+X(````3(G_Z`````!(B<5!O0````!$
-M.R@/C94```!)8\5(C01`3(UTA2!!#[9&"(T$A0"'``")1"0$08!^!0!U94&)
-MQ$F+7R!!#[9."T&X`````+H.````2(GN3(G_Z``````/M\!!B00<08!^"0!T
-M-4$/MD8)BU0D!(T4@D&)U$F+7R!!#[9."T&X`0```+H.````2(GN3(G_Z```
-M```/M\!!B00<0?_%1#MM``^,:____TB#Q`A;74%<05U!7D%?PTB+1R"+@!R`
-M```E@#\``/9&`T!T)$&Z!`$``$&[``"`'[X``!L`N1,```!!N*P-``!!N10`
-M``#K(D&ZT@```$&[``"`'[X``#8`N0D```!!N$@-``!!N0H```!(BU<@"<@)
-M\$0)V(F"'(```$B+1R!$B9!P$```2(M'($2)@+`0``!(BT\@BX'P$```)?\#
-M\/]$B<K!X@H)T(F!\!```,.0D)!(@^PH2(E<)`A(B6PD$$R)9"083(EL)"!)
-MB?V)\XNW#"X``('F____?^@`````B<9)BT4@BU`PB=6!Y?`#``#![01!B>R%
-MVW0/N"4````IZ-'H1(TD*.L,08U$)/^#_0)$#T/@03GL=!I)BTT@@>(/_/__
-M1(G@P>`$)?`#```)PHE1,$R)[^@`````03GL#Y7`#[;`2(M<)`A(BVPD$$R+
-M9"083(ML)"!(@\0HPTB#[`@/MX>8`P``N0`````YQGT<2&/&2(G&2,'F!$@I
-MQDB-M+?0+@``Z`````")P8G(2(/$",-(@^P(28G0#[>'F`,``+H`````.<9]
-M'TACQDB)PDC!X@1(*<)(C927T"X``$R)QN@`````B<*)T$B#Q`C#05=!5D%5
-M05154TB#[`A)B?U!B?1)B=9(B?Y(C8^0`P``0;\+````08/\`G0B08/\`G<+
-M08/\`715Z:0```!!@_P#=!I!@_P$="3IDP````^W:0C_S4&!S\``!0#K:0^W
-M:0B#[0)!@<_``04`ZUD/MVD(@^T#2&/52(G02,'@!$@IT(.\A]0N````=#OK
-M5+T`````#[=!"(G'.<5]'4ACU4B)T$C!X`1(*="#O(;4+@```'0&_\4Y_7SC
-M#[=!"+K_____.<5T?$ACU4B)T$C!X`1(*=!(C9R&T"X``(-[!`!T![K_____
-MZUJ^/````$B)W^@`````1(EC!$V%]G4N1(E[#,=#%`(```#'0QC_____QT,<
-M_P,``&;'0R`*`&;'0R(*`,=#-`````#K%$&+1C")0S1,B?*)[DR)[^@`````
-MB>J)T$B#Q`A;74%<05U!7D%?PTB+3R"+E[PN``"!XO\#``"+A\0N``#!X!`E
-M``#_`PG"B9&D````2(M/((N7P"X``('B_P,``(N'R"X``,'@$"4``/\#"<*)
-MD:@```!(BT\@BX&L````)0#\__^+E\PN``"!XO\#```)T(F!K````,-(@^P(
-M#[>'F`,``+H`````.<9S7HGR2(G02,'@!$@IT$R-A(?0+@``08-X!`!U![H`
-M````ZSQ!QT`$`````+C^____B?'3P"&'O"X``"&'P"X``"&'Q"X``"&'R"X`
-M`"&'S"X``$R)QN@C____N@$```")T$B#Q`C#4T&)\DF)^TB+C^@3```/MX>8
-M`P``N@`````YQ@^#L0,``(GR2(G02,'@!$@IT$R-A(?0+@``08-X!``/A(T#
-M``!!@W@8_W4S2(7)=!4/MT$"):````"Z'P```#V@````=`6Z#P```+@!````
-M.=!S#P'`@\@!.=!R]^L$08M`&$*-')4`````C;-`$```2(M/((G"@>+_`P``
-M08M`','@"B4`_`\`"<)!BT`4P>`4)0``\`\)PHD4#HVS@!```$B+3R!!#[=`
-M(L'@!"7P````00^W4""#X@\)T`T`(`@`B00.O@`(``!!N0`!``!!@W@D`'0Q
-MC;/`"```2(M/($&+4"2!XO___P!!BT`HP>`8"<*)%`Z^`0@``$&#>"@`=`6^
-M`0D``$&#>#``=!U"C0R5``D``$B+5R!!BT`P)?___P`-`````8D$$4*-#)7`
-M$```2(M7($&+0"PE__\/`$&#>"P`=`4-```0`(D$$4&#>#``=`V)\(#,`D'V
-M0`P@#T7P0?9`#$!T!H/F\(/.`D#VQ@]T*(GR@\I`B?"#X+]!]D`-`8G6#T3P
-MB?*#RB")\(/@WT&`>`P`B=8/2?!$B<@-```@`$'V0`X!1`]%R$2)R(#,`D'V
-M0`Z`1`]%R$'V0`X$=`E!@<D```0`ZQ%$B<@-```"`$'V0`X"1`]%R$2)R(#,
-M0$'V0`X(1`]%R$2)R`T``!``0?9`#A!$#T7(08M`!(/X`G0'@_@#=`_K4$"`
-MSJ)!@<D``"4`ZT.#SF)!@W@P`'4RBQ4`````*Q4`````08N#U#$``"G0*P4`
-M````P>`*0HT,E0`)``!(BU<@#0````&)!!%!@<D```0`1(G(#0``)`!!]D`X
-M`40/1<A"C125`````(V*P`D``$B+1R")-`&!P@`1``!(BT<@1(D,`D&#>#0`
-M=#A(BU<@0XU$$E")@@`+``!(BU<@08M`-(F"!`L``$B+1R#'@`@+```)````
-M2(M7((L$$8#,$(D$$4'V0`P!=!.X`0```$2)T=/@00F#O"X``.L1N/[___]$
-MB='3P$$A@[PN``!!]D`,`703N`$```!$B='3X$$)@\`N``#K$;C^____1(G1
-MT\!!(8/`+@``0?9`#`)T$[@!````1(G1T^!!"8/$+@``ZQ&X_O___T2)T=/`
-M02&#Q"X``$'V0`P$=!.X`0```$2)T=/@00F#R"X``.L1N/[___]$B='3P$$A
-M@\@N``!!]D`,"'03N`$```!$B='3X$$)@\PN``#K$;C^____1(G1T\!!(8/,
-M+@``3(G&Z$G[__^Z`0```(G06\.--+4`"```2(M'((L$!L.--+4`"```2(M'
-M((D4!K@!````PXGQ2(M7(+@!````T^")@D`(``"X`0```,.-!+4`"@``2(M7
-M((L$$(G'@^<#=1FX`0```(GQT^"+DD`(``"%PK@!````#T7XB?C#055!5%53
-M2(/L"$B)^T&)]$B+5R"X`0```(GQT^")@H`(``!!O>@#``!$B>9(B=_H````
-M`(7`=`^_9````.@`````0?_-=>)$B>9(B=_H`````(7`#X3R````@[M\`P``
-M!W0V@[M\`P``"W0M@[M\`P``"G0D@[M\`P``"70;@[M\`P``"@^%P0```&:#
-MNX`#```##X>S````O@````!(BT,@BY!,@```QX``@0``9``*`$B+2R#!Z@H/
-MM\(-```!`(F!_(```$B+0R"+@$R```#!Z`HYT'0'_\:#_@%VOTB+4R"+@DB`
-M```-``!``(F"2(```+_(````Z`````!(BU,@BX+\@```)?___O^)@OR```"]
-M9````.L._\UT&;\*````Z`````!$B>9(B=_H`````(7`=>-(BU,@BX)(@```
-M)?__O_^)@DB```!(BT,@QX"`"````````$6%[0^5P`^VP$B#Q`A;74%<05W#
-M1(M<)!A$BU0D*`^_A^PQ``!!`<%!@_E`N#\```!$#T/(@>+_#P``0<'A$$0)
-MRHG0#0``@`!!]L(@#T70BT0D(,'@&24````>"<*)T`T````!0?;"`0]$PHG"
-M@<H````@0?;"$`]%PHE&"$'!X!2+3"10P>$9BU0D0,'B'8M$)$C!X!M!"<A!
-M"=!!"<!$B<`-`````4'VP@)$#T7`1(E&#(M$)!#!X!`E```/`(G"@,Z`0?;"
-M0`]%PHE&$(M$)`B)1A1!@_O_=!5$B=C!X`TE`.`/``E&#(%."````$!!]L(,
-M=$ZX`/\`?P^V3"0PT_BZ`````*@!=#Y!]L((N`````"Z````@`]%PHG"@<H`
-M`$``0?;"!`]%P@E&"(M$)#@E_W\```E&$(M$)##!X!0)1A2Z`0```(G0PXM\
-M)!"%R70;B<C!X!0E``#P``M&$(#,@(E&$(G0P>`%"484187)=!U$B<C!X!@E
-M````#PM&$(#,@(E&$$2)P,'@"@E&%(7_=!B)^,'@'`M&$(#,@(E&$(M$)`C!
-MX`\)1A2X`0```,.!3@@````@PX7)=!6+1@P)T(G"@,X0187`#T3"B48,ZSQ%
-MA<!T&L=&"`````")5@Q!BT$0B48008M!%(E&%.L=QT8(`````(G0@,P0B48,
-MQT80`````,=&%`````#'1AP`````QT88`````+@!````PTB)T4B)\O9&'`%U
-M!K@/````PXM&'"7^'P``T>AFB0$/MT8:9HE!`L9!!`"+1ABH`74<J`)T!,9!
-M!`'V0A@(=`2`200"]D(8!'0$@$D$!(M"'"4``&``P>@5B$$+#[;`@_@!=""#
-M^`%_!H7`=`[K0(/X`G0=@_@#="7K-`^V0A2#X!_K*(M"%"7@`P``P>@%ZQB+
-M0A0E`'P``,'H"NL+BT(4)0"`#P#!Z`^#R("(006+0APE`.`?`,'H#8A!!HM"
-M&"7P````P>@$B$$'BT(8)0`/``#!Z`B(00@/MD$+@_@"=!^#^`)_!X/X`70C
-MZR^#^`-U*HM"$"4````/P>@8`$$(BT(0)0``\`#!Z!0`00B+0A`E```/`,'H
-M$`!!"(M"&"4`\```P>@,B$$)]D(?`0^4P+H"````*,*(40JX`````,.+!B.'
-MI$@``(D&]]`AAZ1(``##D)!32(G[2(VW3"X``.@`````2(M#(,>`)($`````
-M``!(BT,@QX`H@0```````$B+0R#'0$``````2(M#(,>`,($``````@!(BT,@
-MQX`X@0```````EO#4TB)^TB+1R#'0$`&````2(VW3"X``.@`````2(M#(,>`
-M)($```````!(BT,@QX`H@0```````%O#N0````!(8\%(:\!8#[>$!R@R``!F
-M.P9T+$ACP4AKP%A(C90'(#(``&:#>@@`=1D/MP9FB4((#[=&`F:)0@H/MD8$
-MB$(,B<C#_\&#^3]VMK@`````PTB+AR`R``##4TB)^TB-MTPN``#H`````$B-
-M@Q`N``!;PT%455-(B?U!B?1(B?L/MH>3`P``@^`!B8<4,@``2(V_*#(``+X`
-M%@``Z`````"^`````(.]?`,```9W$4ACQDAKP%C&A`,P,@``!^L/2&/&2&O`
-M6,:$`S`R```"2&/&2&O`6$B-#`-(C8$P,@``QT`,]`$``,=`$,@```#'0!3(
-M````2(V!0#(``,=`"&0```#'0!`H````QT`,!P```$B-@2`R``#&0!0`QD`5
-M``^V4!"(4!+&0!,`@[L4,@```'052(V!8#(``,=`#`S^OP#'0!`X_[\`_\:#
-M_C\/AE'___^#NQ0R````="A(BU4@BX-L,@``B8(L@0``2(M5((N#<#(``(F"
-M-($``$B)[^@`````QX,8,@``9````$6%Y'0)@XL0,@```>L'@Z,0,@``_EM=
-M05S#4TB)^X._%#(```!T(>@`````2(M#(,>`+($```````!(BT,@QX`T@0``
-M`````%O#2('LB````$B)7"1X2(FL)(````!(B?M(B?U,BX<@,@``N`````"#
-M_@8/AX`$``")\/\DQ0````")U[@`````@_H$#X=G!```2(M+((N14)@``('B
-M__\/\(G^BX2S*$@``,'@%"4``/`/"<*)D5"8``!(BTL@BY%<F```@>)_@/__
-MBX2S4$@``,'@!R6`?P``"<*)D5R8``!(BTL@BY%<F```@>+_?\#_BX2S/$@`
-M`,'@#R4`@#\`"<*)D5R8``!(BTL@BY%8F```@>+__P/\BX2S9$@``,'@$B4`
-M`/P#"<*)D5B8``!!#[9`"3G'=@C_@Q`N``#K#T$/MD`).<=S!O^#%"X``$&(
-M>`GIFP,``,=$)#A_````QT0D/#(```#'1"0P?P```,=$)#0H````QT0D*'\`
-M``#'1"0L30```,=$)"!_````QT0D)$````#'1"08'P```,=$)!P0````QT0D
-M$#\```#'1"04,````(72#Y7`#[;X2(MS((N6;)@``('B_S_@_XGY2,'A`HM$
-M##C!X`XE`,`?``G"B99LF```2(MS((N6;)@``('B__\?\(M$###!X!4E``#@
-M#PG"B99LF```2(MS((N6:)@``('B__\!_XM$#"C!X!$E``#^``G"B99HF```
-M2(MS((N6:)@``('B____@(M$#"#!X!@E````?PG"B99HF```2(MS((N&:)@`
-M`(/@X(M4#!B#XA\)T(F&:)@``$B+<R"+EFR8``"`YL"+1`P0P>`()0`_```)
-MPHF6;)@``(7_=`](BU,@BX)LF```@\@!ZPU(BU,@BX)LF```@^#^B8)LF```
-MA?\/E,`/ML!!#[90##G0#X0E`@``A?]T"/^%("X``.L&_X4D+@``A?]!#Y1`
-M#.D'`@``QT0D"`@```#'1"0,!@```(72#Y7`#[;P2(M/((N!"*(``(/@P(GR
-MBU24"(/B/PG0B8$(H@``00^V0`TYQ@^$Q`$``(7V=`C_AR@N``#K!O^'+"X`
-M`$&(<`WIJ0$``,=$)&``````QT0D9`0```#'1"1H"````(G6N`````"#^@(/
-MAX8!``!(BT\@BY%8F```@>+_#_S_B?"+1(1@P>`,)0#P`P`)PHF16)@``$$/
-MMD`+.<9V"/^',"X``.L/00^V0`LYQG,&_X<T+@``08AP"^DR`0``QT0D0`(`
-M``#'1"1$!````,=$)$@&````QT0D3`@```#'1"10"@```,=$)%0,````QT0D
-M6`X```#'1"1<$````(G6N`````"#^@</A^<```!(BT\@BY$DF0``@.(!B?"+
-M1(1``<`E_@````G"B9$DF0``00^V0`HYQG8(_X<8+@``ZP]!#[9`"CG&<P;_
-MAQPN``!!B'`*Z9<```"%TG4F@Z<0,@``_>@`````2(G?Z`````")QH'F__[_
-M_TB)W^@`````ZVWVAQ`R```"=62#OQ0R````=#_H`````(G&@>;__O__2(G?
-MZ`````!(BU,@BX-L,@``B8(L@0``2(M3((N#<#(``(F"-($``$B)W^@`````
-MZQ7H`````(G&@<X``0``2(G?Z`````"#C1`R```"N`$```!(BUPD>$B+K"2`
-M````2('$B````,-32(GY2(N?(#(``,=#$`````"#OQ0R````='R!>Q0``,``
-M=@G'0T0`````ZPNX``#``"M#%(E#1(%['```P`!^"<=#2`````#K"[@``,``
-M*T,<B4-(2(M7((M#1(F"+($``$B+5R"+0TB)@C2!``!(BT<@QX`P@0`````"
-M`$B+1R#'@#B!```````"2(VQ3"X``.@`````QT,\`````,=#0`````!;PTB#
-M[!A(B5PD"$B);"002(G[2(NWZ!,``(N'$#(``(/@`X/X`P^%WP```$B+KR`R
-M``"`?0D#=Q`/ME4)_\*^`0```.F]````#[9%"CI%"','#[;0_\+K0(N/8"X`
-M`(G(@^!_@_@_=@6-07_K!HN'8"X``,'H!SM%*'XD@'T,`'4[N@````"^`@``
-M`$B)W^@`````N@````"^!0```.MC.T4D?B:`?0P`=!*Z`0```+X"````2(G?
-MZ`````"`?0L!=T@/ME4+_\+K,TB)W^@`````@^@"@_@!=S"`?0P`=1*Z````
-M`+X"````2(G?Z`````"`?0L`=!*Z`````+X$````2(G?Z`````!(BUPD"$B+
-M;"002(/$&,-(@^P82(E<)`A(B6PD$$B)^TB+M^@3``"+AQ`R``"#X`.#^`-U
-M<TB+KR`R``"`?0D#=PT/ME4)_\*^`0```.M4BY=@+@``B="#X'^#^#]V!8U"
-M?^L&BX=@+@``P>@'.T4D?@Z`?0L!=S`/ME4+_\+K&TB)W^@`````@^@"@_@!
-M=QB`?0L`=!*Z`````+X$````2(G?Z`````!(BUPD"$B+;"002(/$&,-!54%4
-M55-(@^P(2(G[08GU28G\2(NWZ!,``.C9]O__2)A(:\!82(VL&"@R``!(B:L@
-M,@``@[N,`P```74)@XL0,@```NL'@Z,0,@``_8.[C`,```$/A(<```!!_X0D
-M0"X``+H`````O@$```!(B=_H`````+H`````O@4```!(B=_H`````+H`````
-MO@0```!(B=_H`````+H`````O@(```!(B=_H`````+H`````O@,```!(B=_H
-M`````$B)W^@`````B<:!S@`!``!(B=_H`````$B)W^B]_/__Z2D!``"+@Q`R
-M``"#X`.#^`,/A1<!``!%A>UT4`^V50F^`0```$B)W^@`````#[95"KX%````
-M2(G?Z`````"`?0P`#Y3"#[;2O@(```!(B=_H``````^V50V^`P```$B)W^@`
-M````#[95"^M,N@0```"^`0```$B)W^@`````#[95"+X%````2(G?Z`````"Z
-M`0```+X"````2(G?Z`````"Z`0```+X#````2(G?Z`````"Z`@```+X$````
-M2(G?Z`````!!@[PD%#(```!T/DB)W^@`````B<:!YO_^__](B=_H`````$B)
-MW^C-^___2(M#(,>`,($``````@!(BT,@QX`X@0```````NL@2(G?Z*?[__](
-MB=_H`````(G&@<X``0``2(G?Z`````!(@\0(6UU!7$%=PT%455-(B?U(B?-)
-MB?Q(BT<@QX`D@0```````$B+1R#'@"B!````````2(VW3"X``.@`````2(L#
-M2(F%8"X``(M#"(F%:"X``$B+12"+D"R!``"+B#2!``")T"4``,``/0``P`!T
-M#HG()0``P``]``#``'5828N<)"`R```K4T2)T"M#/$$!A"0X+@``B5,\B<HK
-M4TB)T"M#0$$!A"0\+@``B5-`BT,\.T,4=@A(B>_H=_O__XM#0#M#''8(2(GO
-MZ'_\__](B>_HN/K__UM=05S#4TB)^TB+ER`R``"`?@41=1C_0CS_AS@N``"+
-M0CP[0A1V*^@S^___ZQR`?@49=1[_0D#_ASPN``"+0D`[0AQV#>@M_/__2(G?
-MZ&;Z__];PTB#[`A(BY<@,@``BX]@+@``B<B#X'^#^#]V!8U!?^L&BX=@+@``
-MP>@'.T(H?RH[0B1^$H!Z#`!T#+H!````O@(```#K-X!Z"P!T#0^V4@O_RKX$
-M````ZR2`>@H`=`T/ME(*_\J^!0```.L1@'H)`'00#[92"?_*O@$```#H````
-M`$B#Q`C#2(M'($2+B.R```!$BY#P@```1(N`^(```$B+MR`R``"#?C@`=`9$
-M.48X=@VY`````/^'1"X``.LP1(G!*TXX1(G0*T8T1(G**U8P*<$IT4ACP4AI
-MP"DY4U](P>@@B<?!_PZ)R)F)^2G11(E&.$2)3C!$B58TB<C#2(/L*$B)7"0(
-M2(EL)!!,B60D&$R);"0@2(G[28G]3(NG(#(``$B+!DB)AV`N``"+1@B)AV@N
-M``!-A>0/A*\!``#H0O___XG%A<!Y#O^#2"X``$B)W^@,^?__00%L)!!!@[T4
-M,@````^$L````$F-M4PN``!(B=_H`````$B+0R"+D"R!``"+B#2!``!!.U0D
-M1'(.03M,)$AS44$[5"1$<QU(BT,@08M4)$2)D"R!``!(BT,@QX`P@0`````"
-M`$$[3"1(#X,G`0``2(M#($&+5"1(B9`T@0``2(M#(,>`.($```````+I!0$`
-M`$$K5"1$B=!!*T0D/$$!A3@N``!!B50D/(G*02M4)$B)T$$K1"1`00&%/"X`
-M`$&)5"1`BX,0,@``@^`#@_@##X7!````08N%&#(``(T$@$$Y1"00=DU!BU0D
-M$(G000^O1"082&G`TTUB$$C!Z"#!Z`9!.40D/`^'@@```(G000^O1"0@2&G`
-MTTUB$$C!Z"#!Z`9!.40D0'=E2(G?Z'?]___K6T&+1"0003N%&#(``'9500^O
-M1"042&G`TTUB$$C!Z"#!Z`9!.40D/'8*2(G?Z$_X___K*$&+1"0000^O1"0<
-M2&G`TTUB$$C!Z"#!Z`9!.40D0'802(G?Z#WY__](B=_H=O?__TB+7"0(2(ML
-M)!!,BV0D&$R+;"0@2(/$*,.0D$B+A^@3```/MP!FB09(BX?H$P``@$@$"(!.
-M!`A(BX?H$P``#[=``F:)1@)(BX?H$P``#[9`!(A&!$B+A^@3```/MD`%B$8%
-MN`````##D)"005=!5D%505154TB#[`A)B?Q!B=>)R[T`````2<?&`````$&)
-M]4ACQ4B-!$!!BPS&28M4)"!)C41%`$&+!(:)!!'_P_;#/W4*OP$```#H````
-M`/_%@_T-=LR]`````$ACQ8L,Q0````!)BU0D((L$Q0````")!!'_P_;#/W4*
-MOP$```#H`````/_%@_U'=L^]`````$G'Q@````!%B?U(8\5(C01`08L,ADF+
-M5"0@3`'H08L$AHD$$?_#]L,_=0J_`0```.@`````_\6#_3]VSDB#Q`A;74%<
-M05U!7D%?PT%505154TB#[`A)B?Q)B?4/MU8"#[<VZ`````!!@'T"`'E<2`^_
-MV$B-!%M(C1R%`````(M[!+X(````Z`````")Q8'E_P```,'E!8L#P>`$"<4/
-MMTL(28M4)""+@@2B``!F08%]`+0)=06#R!#K"$F+5"0@@^#OB8($H@``ZP>)
-MP;T`````9H'YD`!_!?;!`70?#[_Y@^\8O@@```#H`````(G&@>;_````N`$`
-M``#K)@^_^8/O&(GXP>@?`<?1_[X(````Z`````")QH'F_P```+@`````P>8"
-M`<`)QH'.`00``$F+3"0@0`^VQ<'@"$`/MM8)T(F!G)@``$F+3"0@B>@E`/\`
-M`$B)\P^VUPG0B8'0F```38FL).@3``"X`0```$B#Q`A;74%<05W#2(N7X#$`
-M`(/^!W<IB?#_),4`````2(G0PTB-0D3#2(U"2,-(C4),PTB-0E##2(V"E```
-M`,.X`````,-!5T%6055!5%532(/L>$F)_DB)="089HE4)!9)B?^]``````^W
-M1@(E\`$``#W`````#X2'`0``/<````!_$#V@````#X04`0``Z=$!```]0`$`
-M`'0+/5`!```/A;\!``!(BU0D&`^W`F8MH0]F/>H$=Q=!#[>'#!4``&:)1"0,
-M00^WEPX5``#K4$B+5"08#[<"9BV,%&8][P!W%T$/MX<0%0``9HE$)`Q!#[>7
-M$A4``.LG2(M4)!@/MP)F+7P59CW@`'<<00^WAQ05``!FB40D#$$/MY<6%0``
-M9HE4)`KK-DB+1"089H$X7!9V'$$/MY<8%0``9HE4)`Q!#[>'&A4``&:)1"0*
-MZPYFQT0D"@``9L=$)`P``$&\`````+X`````00^WEY`4``!FB50D%$$/MX>6
-M%```9HE$)!)F08._EA0````/E,!F#[;`9HE$)!!!#[>7Y!0``.F[````#[>'
-M'!4``&:)1"0,#[>7'A4``&:)5"0*#[>W)!4``$0/MZ<H%0``#[>'DA0``&:)
-M1"04#[>7F!0``&:)5"029H._F!0````/E,!F#[;`9HE$)!`/MX?F%```9HE$
-M)`[K:P^WER`5``!FB50D#`^WAR(5``!FB40D"@^WMR85``!$#[>G*A4```^W
-MEY04``!FB50D%`^WAYH4``!FB40D$F:#OYH4````#Y3`9@^VP&:)1"00#[>7
-MZ!0``&:)5"0.ZPJX`````.G,`P``NP````!(#[=,)!9(Q\<`````2&/#2(T4
-M0$B-%%&+%)>)5(0@_\.#^Q!VYTB+1"08@'@"`'DX2(U<)"!!N`````"Y=P``
-M`+H#````2(G?Z`````!!N`````"Y>@```+H#````1(GF2(G?Z`````"[````
-M`$ACPTB-%$"+#-4`````28M6((M$A"")!!'_Q4#VQ3]U"K\!````Z`````#_
-MPX/[$';.NP````!(8\.+#,4`````28M6((L$Q0````")!!'_Q4#VQ3]U"K\!
-M````Z`````#_PW32NP````!)Q\4`````3`^W9"062&/#2(T$0$&+3,4`28M6
-M($F-!$1!BT2%`(D$$?_%0/;%/W4*OP$```#H`````/_#=,Z[`````$G'Q0``
-M``!,#[=D)!9(8\-(C01`08M,Q0!)BU8@28T$1$&+1(4`B001_\5`]L4_=0J_
-M`0```.@`````_\-TSKL`````2`^W3"062,?&`````$ACPTB-%$!(C111BQ26
-MB52$(/_#@_L0=N=(BU0D&`^W0@(E0`$``#U``0``=45!#[>WA!4``$B-7"0@
-M0;@#````N3,```"Z`0```$B)W^@`````00^WMX85``!!N`,```"Y+0```+H!
-M````2(G?Z``````/MW0D$$B-7"0@0;@`````N5\```"Z`0```$B)W^@`````
-M#[=T)!1!N`````"Y8````+H$````2(G?Z``````/MW0D#$&X`````+EH````
-MN@,```!(B=_H``````^W="0*0;@`````N6L```"Z`P```$B)W^@`````NP``
-M``!(8\-(C11`BPS5`````$F+5B"+1(0@B001_\5`]L4_=0J_`0```.@`````
-M_\.#^Q!VSKL`````2`^W3"062,?&`````$ACPTB-%$!(C111BQ26B52$(/_#
-M@_L'=N</MW0D#DB-7"0@0;@`````N1T```"Z!@```$B)W^@`````#[=T)!)!
-MN`````"Y!````+H!````2(G?Z`````!(BT0D&&:#>`(`>`;V0`-`='1(BU0D
-M&/9"`T"Z'P```+@0````08G$1`]$XDB-7"0@0;@`````N1,```"Z!0```+X?
-M````2(G?Z`````!!N`````"Y&````+H%````1(GF2(G?Z`````!!N`````"Y
-M,0```+H"````O@,```!(B=_H`````+L`````2&/#2(T40(L,U0````!)BU8@
-MBT2$((D$$?_%0/;%/W4*OP$```#H`````/_#@_L'=LY!QX>T,0```````+@!
-M````2(/$>%M=05Q!74%>05_#4T&)TD&)R0^WP4$/M]`/K\*Z`````(7`=&F)
-MR&9!.?)T7@^WQP^WUBG0:\AD00^WPBG0B<*)R(G3F??[B<%$B<AFA<EX.D2)
-MP&:#^61_,0^_R4$/M]`/K]&X9````"G(00^WR0^OP0'"2&/"2&G`'X7K44C!
-MZ"#!^`7!^A]F*=`/M]")T%O#05=!5D%505154TB![$@!``!)B<U)B?YFQT0D
-M#@``9L=$)`P_``^W00(E\`$``#W0````='D]T````'\3/:````!T2CW`````
-M=&3I@0```#U0`0``=!4]4`$``'\'/4`!``#K!3U`"0``=65!#[>&GA4``&:)
-M1"0828V&BA4``$B)1"0028V&H!4``.M-#[>'J!<``&:)1"082(V'L!<``$B)
-M1"002(V'9A@``.LL00^WAJ@7``!FB40D&$F-AJH7``!(B40D$$F-ALH7``#K
-M"K@`````Z<8"``!(B40D($B-7"0PO@@!``!(B=_H`````$R->PA,C:.(````
-MNP$```"]`````$ACQ69!B1Q'_\/_Q8/[/W[O9HEL)#9FQT0D,@$`9L=$)#0_
-M`+T`````9H-\)#8`="=(8]U!#[<T7T$/MWT`2(U4)!#H9`(``&9!B01<_\4/
-MMT0D-CG%?-E!#[<T)$@/MT0D-D$/MWQ$_KT`````9H-\)#8`='9(8\5F03LT
-M1'P*00^W-$1FB6PD#HGH]]!F`T0D-@^WV(7;="9(8]-!#[=$5/YF03L$5'X+
-M00^W!%1F08E$5/[_Q0^W1"0V.<5\MKT`````9H-\)#8`=!\/MTPD-DACQ69!
-M.SQ$?0I!#[<\1&:);"0,_\4YS7SF#[_6@\(92&/"2&G`'X7K44C!Z"#!^`3!
-M^A\IT&OH,D&]`````+L`````#[_5B=%(8\)(:<`?A>M12,'H(,'X!,'Z'RG0
-M_\`YPWTW2&/!2&G`'X7K44C!Z"")QL'^!(GP*="-2`%!#[?528N&>$@```^W
-M="0.9HDT4$'_Q?_#.<M\X[L`````2`^W1"0V2(G"9D$[;$3^#XW>````9D&#
-M_3\/A_@```"#Q3)(B==F03ML5/Y]40^_S8G.2&/300^_!%1!B<A!*<!$B<!!
-M#[]45`(IT0^OP87`?BS_PV9!.VQ\_GTB2&/300^_!%2)\2G!B<A!#[]45`)!
-MB?!!*=!!#Z_`A<!_U$ACPT4/MT1'`D4!P$4/M\!!#[<,1P')#[?)00^W5$0"
-M00^W-$0/M_WH5/S____`00^WS4F+EGA(``!FT>AFB01*28N&>$@``(M4)`QF
-M.11(=@1FB11(0?_%2`^W5"0V9D$[;%3^?0UF08/]/P^&+____^LE9D&#_3]W
-M'D$/M\U)BY9X2```#[=$2OYFB01*0?_%9D&#_3]VXF9!QX;L,0````"X`0``
-M`$B!Q$@!``!;74%<05U!7D%?PTB#[#A(B5PD&$B);"0@3(ED)"A,B6PD,$B)
-MU4&)_8GS#[?V#[?_2(U,)!;H,`$``(7`=`H/MT0D%ND)`0``#[=5"$4/M^U,
-MC40D%$B-3"022(MU`$2)[^@`````#[=T)!(/M]M,C40D$$B-3"0.2(GJB=_H
-M4`$```^W="043(U$)`Q(C4PD"DB)ZHG?Z#<!```/MW0D#@^W?"022(U,)`A(
-MB>KHN`````^W="00#[=\)!)(C4PD!DB)ZNBA````1`^W1"0&#[=,)`@/MU0D
-M$`^W="0.B=_H[/K__T&)Q`^W="0*#[=\)!1(C4PD"$B)ZNAK````#[=T)`P/
-MMWPD%$B-3"0&2(GJZ%0```!$#[=$)`8/MTPD"`^W5"0,#[=T)`J)W^B?^O__
-M#[?`00^WS`^W5"04#[=T)!)!B<!$B>_H@_K__P^WP$B+7"082(ML)"!,BV0D
-M*$R+;"0P2(/$.,-,BTH00;L`````9H-Z"`!T469!.3EU.TV-00A!N@````!F
-M08-Y!@!T*69!.3!U$DECPD$/MT1!'F:)`;@!````PTF#P`)!_\)!#[=!!D$Y
-MPGS728/!-$'_PP^W0@A!.<-\K[@`````PTB#[`A!B?)(BW(00;D`````#[="
-M"(G"03G!?1)F1#D6=`Q(@\8T0?_!03G1?.X/MU8&2(/&"`^W_^@`````2(/$
-M",-32(G[2(._>$@```!T%TB+OWA(``#H`````$C'@WA(````````2(.[X#$`
-M``!T%TB+N^`Q``#H`````$C'@^`Q````````6\.X`0```,.Z`````$C'QP``
-M```/MP:)P68[!0````!W"__"2&/"9CL,AW;U2&/"#[\$A0````##2(/L&$B)
-M7"0(2(EL)!!(B?5(B?N_M````.@`````2(F#X#$``$B%P'0@QX.`2```@```
-M`+^`````Z`````!(B8-X2```2(7`=0['10`"````N`````#K74C'@W@N````
-M````2,>#@"X```````!(QX.(+@```````$C'@Y`N````````2,>#F"X`````
-M``!(QX.@+@```````$C'@Z@N````````2,>#L"X```````"X`0```$B+7"0(
-M2(ML)!!(@\08PY!!5T%6055!5%532(/L"$F)_$&)UXG+O0````!)Q\8`````
-M08GU2&/%2(T$0$&+#,9)BU0D($F-1$4`08L$AHD$$?_#]L,_=0J_`0```.@`
-M````_\6#_0]VS+T`````2&/%BPS%`````$F+5"0@BP3%`````(D$$?_#]L,_
-M=0J_`0```.@`````_\6#_41VS[T`````2<?&`````$6)_4ACQ4B-!$!!BPR&
-M28M4)"!,`>A!BP2&B001_\/VPS]U"K\!````Z`````#_Q8/]/W;.2(/$"%M=
-M05Q!74%>05_#059!54%455-)B?Q(B?5!O@````!!O0````!F@3Z_$@^'XP``
-M``^W/HV'</?__TACT$AITF=F9F9(P>H@T?J)P<'Y'RG*C122.=!U(XV</^#N
-M__](8\-(:<!G9F9F2,'H((G!P?D"B=B9B<LIT^M7#[<VC890]___2&/02&G2
-M9V9F9DC!ZB#1^HG!P?D?*<J-%)*Y`````#G0#X4V`@``C9PVH.[__TACPTAI
-MP&=F9F9(P>@@B<'!^0*)V)F)RRG30;X!````P>,"@>/_````O@@```")W^@`
-M````B<-)BU0D((N"!*(``&:!?0"T"74%@\@0ZPA)BU0D((/@[XF"!*(``.F#
-M`0``#[<6#[?":<#-S```P>@09L'H`HT$@(G19BG!9H/Y`G5*9H'Z.Q5W0XU"
-M_@^WP(T$@(V$`(!$__](8_A(:?\?A>M12,'O(,'_`\'X'RG'_\>^"````.@`
-M````B<.^`@```+\`````Z1`!```/MU4`#[?":<#-S```P>@09L'H!(T$@,'@
-M`F8YPG5#9H'Z_Q-V/`^WPBW`$@``2&/X2&G_9V9F9DC![R#!_P/!^!\IQ\'G
-M`KX(````Z`````")P[X"````OP,```#IK@````^W50`/M\)IP,W,``#!Z!!F
-MP>@#C02``<!F.<)U.`^WPBW`$@``2&/X2&G_9V9F9DC![R#!_P+!^!\IQP'_
-MO@@```#H`````(G#O@(```"_`@```.M8#[=5``^WPFG`S<P``,'H$&;!Z`*-
-M!("Y`````&8YP@^%A0````^WPBW`$@``2&/X2&G_9V9F9DC![R#1_\'X'RG'
-MO@@```#H`````(G#O@(```"_`0```.@`````08G%B=[!Y@1"C02M``````G&
-M0XT$-@G&@<X!$```28M4)"!`#[;&B8*<F```P>X(28M4)"")\(/@?XF"V)@`
-M`$F)K"3H$P``N0$```")R%M=05Q!74%>PTB+E^`Q``"#_@=W)(GP_R3%````
-M`$B)T,-(C4($PTB-0@C#2(U"#,-(C8*L````P[@`````PT%7059!54%455-(
-M@^PH28G]28GV2(E,)!AFB50D)DF)_V;'1"04``!FQT0D$@``9L=$)!```&;'
-M1"0.``!(BZ_@,0``2(V'T"T``$B)!"1!O``````/MT8")?`!```]T`````^$
-M$@$``#W0````?QL]H`````^$V````#W`````#X3U````Z1D!```]4`$``'09
-M/5`!``!_!SU``0``ZP4]``@```^%^0```$$/MP9F+:$/9CWJ!'<700^WEPP5
-M``!FB50D%$$/MX<.%0``ZV=!#[<&9BV,%&8][P!W%T$/MY<0%0``9HE4)!1!
-M#[>'$A4``.M"00^W!F8M?!5F/>``=Q=!#[>7%!4``&:)5"0400^WAQ85``#K
-M'69!@3Y<%G8:00^WEQ@5``!FB50D%$$/MX<:%0``9HE$)!)!#[>WEA0``$$/
-MMY?D%```9HE4)!;K6P^WAR05``!FB40D$`^WER@5``!FB50D#@^WMY@4```/
-MMX?F%```ZR)!#[>7)A4``&:)5"0.9HE4)!!!#[>WFA0``$$/MX?H%```9HE$
-M)!;K"K@`````Z;,%``"Y`````$C'QP````!(8]&+!->)1)4`_\%T\KD`````
-M2`^W?"0F2<?``````$ACP4B-%$!(C11708L4D(E4A03_P73IN0````!(#[=\
-M)"9)Q\``````2&/!2(T40$B-%%=!BQ20B52%"/_!=.FY`````$@/MWPD)DG'
-MP`````!(8\%(C11`2(T45T&+%)")5(4,_\&#^2=VY@^W]DB-70Q!N`````"Y
-M+@$``+H!````2(G?Z`````!(BU0D&`^W,D&X`````+D.`0``N@(```!(B=_H
-M`````$B+1"08#[=P`D&X`````+D!`0``N@(```!(B=_H`````$'V1@)`#X38
-M````2(L4)$B+0B`/OW`"0;@#````N:@```"Z`0```$B)W^@`````2(L4)$B+
-M0B`/OW`$0;@#````N:D```"Z`0```$B)W^@`````2(L4)$B+0B`/OW`&0;@#
-M````N:H```"Z`0```$B)W^@`````2(L4)$B+0B`/OW`(0;@#````N:X```"Z
-M`0```$B)W^@`````2(L4)$B+0B`/OW`*0;@#````N:\```"Z`0```$B)W^@`
-M````2(L4)$B+0B`/OW`,0;@#````N;````"Z`0```$B)W^@`````08!^`@!Y
-M,P^W="002(U=#$&X`````+D?`0``N@,```!(B=_H``````^W="0.0;@`````
-MN2(!``#K,0^W="042(U=#$&X`````+D7`0``N@,```!(B=_H``````^W="02
-M0;@`````N1H!``"Z`P```$B)W^@`````00^WA80#```E\````(/H,(/X/P^'
-MI````&9!@[V$`P``-70A9D&#O80#``!%=!9F08.]A`,``$9T"V9!@[V$`P``
-M-G5X2(U=#$&X`@```+E:````N@(```"^`@```$B)W^@`````0;@"````N5P`
-M``"Z`@```+X"````2(G?Z`````!!N`(```"Y7@```+H"````O@(```!(B=_H
-M`````$&X`@```+G^````N@$```"^`@```$B)W^@`````9D&#O8(#``!!#X:5
-M````2(U=#$&X`0```+D9`0``N@$```"^`0```$B)W^@`````0;@#````N0$`
-M``"Z`@```+X!````2(G?Z`````!!N`,```"Y`P```+H"````O@$```!(B=_H
-M`````$&X`P```+F+````N@$```"^`0```$B)W^@`````0;@#````N8P```"Z
-M`0```+X!````2(G?Z`````"Y`````$@/MW0D)DC'QP````!(8\%(C11`2(T4
-M5HL4EXF4A:P```#_P8/Y#';D0?9&`D!T)TB+%"1(BT(@#[\P2(V]K````$&X
-M`````+DE````N@(```#H``````^W="062(V]K````$&X`````+D.````N@8`
-M``#H`````$'V1@-`=0AF08-^`@!Y54'V1@-`N@\```"X"````$&)QD0/1/)(
-MC9VL````0;@`````N3H```"Z!````+X/````2(G?Z`````!!N`````"Y1@``
-M`+H$````1(GV2(G?Z`````"[`````$ACPXL,Q0````!)BU4@BT2%`(D$$4'_
-MQ$'VQ#]U"K\!````Z`````#_PW34NP````!(8\-(C11`BPS5`````$F+52"+
-M1(4$B0010?_$0?;$/W4*OP$```#H`````/_#=-"[`````$ACPTB-%$"+#-4`
-M````28M5((M$A0B)!!%!_\1!]L0_=0J_`0```.@`````_\-TT+L`````2&/#
-M2(T40(L,U0````!)BU4@BT2%#(D$$4'_Q$'VQ#]U"K\!````Z`````#_PX/[
-M)W;-NP````!(8\-(C11`BPS5`````$F+52"+A(6L````B0010?_$0?;$/W4*
-MOP$```#H`````/_#@_L,=LI!QX>T,0```````+@!````2(/$*%M=05Q!74%>
-M05_#05=!5D%505154TB!["@$``!(B70D0$B)5"0X2(E,)#!,B40D*$B)?"0@
-M#[>'A`,``"7P````@^@P@_@_=S)F@[^$`P``-70>9H._A`,``$5T%&:#OX0#
-M``!&=`IF@[^$`P``-G4*QT0D'`(```#K",=$)!P!````2(M4)#`/MT(")?`!
-M```]T````'1Q/=````!_$#V@````=$0]P````'1<ZW@]4`$``'05/5`!``!_
-M!SU``0``ZP4]``@``'5<2(M,)"!(@<&0(0``2(E,)!!(BT0D(`^WD)`4``#K
-M1TB+5"0@2('"J"$``$B)5"002(M,)"`/MY&2%```ZRA(BT0D($@%P"$``$B)
-M1"002(M,)"`/MY&4%```ZPJ^`````.FM!0``2(M,)!`/MT$*O@````"%T`^$
-MEP4``$B+5"0X#[\"`<!FB40D#$B+3"1`#[\!`<!FB40D#F;'1"18K=YFQT0D
-M6JW>0;X`````O0````!(BT0D$`^W4`I(C7PD6(G0B>G3^*@!=!F^`````$&#
-M_@$/ASD%``!$B?!FB2Q'0?_&_\6#_0-VUDB+1"00#[=0"$B+3"0P#[<Y3(U$
-M)%1(C4PD4$B+,.A6!0``0;X`````1(M\)%!$.WPD5`^'W`$``$2)^$AKP%1)
-MB<5(BU0D$$P#:A!F@7PD6JW>#X6)````2`^W1"182(T$@$F-;(4`1`^W909!
-M#[?<2`';2(UU"(G:2(V\)``#``#H`````$B-=1")VDB-O"3@`@``Z`````!!
-M#[]-`D$/M_Q,C40D8$B-E"3@`@``2(VT)``#``#H+04``+X`````A<`/A%X$
-M``!$B?=(P><'2(V,).`!``!(C3P/Z1,!``!(#[=$)%A(C02`28ULA0!$#[=E
-M!D$/M]Q(`=M(C74(B=I(C;PD``,``.@`````2(UU$(G:2(V\).`"``#H````
-M`$$/OTT"00^W_$R-1"1@2(V4).`"``!(C;0D``,``.BD!```O@````"%P`^$
-MU0,``$2)]TC!YP=(C80DX`$``$B-/`>Z@````$B-="1@Z`````!(#[=$)%I(
-MC02`28ULA0!$#[=E!D$/M]Q(`=M(C74(B=I(C;PD``,``.@`````2(UU$(G:
-M2(V\).`"``#H`````$$/OTT"00^W_$R-1"1@2(V4).`"``!(C;0D``,``.@1
-M!```O@````"%P`^$0@,``$2)\$C!X`=(C;P$X````+J`````2(UT)&#H````
-M`$'_QD'_QT0[?"14#X8D_O__BT0D4$B+3"002(L1#[<$0F:)1"0*BT0D5$0/
-MMRQ"BT0D5$&)QD0K="109H%\)%JMW@^%P````+T`````1(GP28G$2<'D!HGK
-M2HT$(T0/OX1$X`$```^_C%S@`0``2(M$)#`/MSA!#[?5#[=T)`KHM`(``&:)
-MA%R@`P``_\6#_3]VQ$B+5"0@2(NR>$@``$B-O"2@`P``Z`($``")PF;!Z`^-
-M!!!FT?A(BTPD0&:)`0^WA"0>!```B<)FP>H/`=!FT?AFB40D7@^WA"0>!```
-MB<)FP>H/`=!FT?A(BU0D.&:)`HM$)%A(BTPD*&:)`6:)00+I_@$``+T`````
-M1(GP28G'2<'G!D4/M_5$#[=L)`J)ZTZ-)#M&#[^$9.`!```/OXQ<X`$``$B+
-M1"0P#[<X1(GR1(GNZ.T!``!FB81<H`,``$8/OX1DX`````^_C%S@````2(M4
-M)#`/MSI$B?)$B>[HP0$``&:)A%P@`P``_\6#_3]VFX-\)!P"#X6$````2(M,
-M)"!(BY%X2```2(VT)"`#``!(C;PDH`,``$B-3"1.Z*T#``")PF;!Z`^-!!!F
-MT?A(BU0D0&:)`@^W1"1.B<)FP>H/`=!FT?AFB40D7@^WA"0>!```B<)FP>H/
-M`=!FT?A(BTPD.&:)`8M$)%A(BU0D*&:)`@^W1"1:9HE"`NGQ````#[=,)`YF
-M.XPDG@,``']PBT0D#&8[A"2>`P``?V)(BU0D($B+LGA(``!(C;PD(`,``.AC
-M`@``B<(/MT0D6DB+3"0H9HD!9HE!`HG09L'H#XT$$&;1^$B+5"1`9HD"#[>$
-M))X#``")PF;!Z@\!T&;1^&:)1"1>#[>$))X#``#K7TB+1"0@2(NP>$@``$B-
-MO"2@`P``Z`$"``")PHM$)%A(BTPD*&:)`6:)00*)T&;!Z`^-!!!FT?A(BU0D
-M0&:)`@^WA"0>!```B<)FP>H/`=!FT?AFB40D7@^WA"0>!```B<)FP>H/`=!F
-MT?A(BTPD.&:)`;@_````2(M4)#AF*P)(BTPD(&:)@>PQ``"^`0```(GP2('$
-M*`0``%M=05Q!74%>05_#08GZB?=!B=%!B<N)R&9!.?%T*$$/M_(/M_^)\"GX
-M00^_T`^OPD$/M\F)RBGR00^_\P^OU@'0*?F9]_F8PP^W_P^WPDR-#$8/MP8Y
-MQW,.0<<``````,<!`````,-!#[=!_CG'<B</M\+_R.L)2(G02"GP2-'X08D`
-MB0'#2(G02"GP2-'XB0'_P$&)`,-(B?),.<YS&`^W`CGX=-$/MT(".<=RV$B#
-MP@),.<IRZ)##05=!5D%505154TB#[`A)B?1)B==,B<5!B<UFQT0D!@``0;X!
-M````N@````!F@_\!#X:!````NP`````/M\?_R(D$)$$/M\9F03L<1'8100^W
-MQCL$)'T(9O]$)`9!_\9!#[?610^_!%=(#[=$)`9!#[\,1T$/MQ1400^W-$0/
-MM_OHS?[__P^WTV:)1%4`9D0YZ'P79H/[/W<1#[?#9D2);$4`_\-F@_L_=N__
-MPV:#^S]VD;H!````B=!(@\0(6UU!7$%=05Y!7\,/OT=^#[\7*="#^'Y^"T0/
-MMU=^08/J?NL$1`^W%T0/MT]^N3\````/OU=^B=#_R#G"?A6)PO_)2`^_P0^_
-M!$<YT'X%9H7)>>V)RD6)R$&Y/P```(U"_XG!9H/X/G<A2`^_PF9$.01'?!:)
-MRHU*_V:#^3YW"T@/O\)F1#D$1WWJ9H72=1MF187)>"=)#[_1#[=$5@)FB016
-M9D'_R7GMZQ))#[_!9HD41D&#Z`)F0?_)>:)!#[_"PT%455-)B=-(B<NY0```
-M``^_1WX/OQ8IT(/X?GX+1`^W9WY!@^Q^ZP1$#[<F#[=O?D&X/P````^_5WZ)
-MT/_(.<)^%XG"0?_(20^_P`^_!$<YT'X&9D6%P'GK#[=&?F:)`T&Z/P```$&)
-MZ69$.PM^#&9%A<!U%&:#^4!U#KD`````2(GW0;@_````9D6%P'X?20^_P&9$
-M.0Q'?!1!_\AF187`?@M)#[_`9D0Y#$=][&9%A<!U(F:%R74=9D6%TG@S20^_
-MTD$/MT13`F9!B0139D'_RGGKZQQ)#[_21(G`"<AF08D$4T&#Z0)F0?_*#XEW
-M____00^_Q%M=05S#4TB)^TB#OWA(````=!=(B[]X2```Z`````!(QX-X2```
-M`````$B#N^`Q````=!=(B[O@,0``Z`````!(QX/@,0```````%O#1`^W1@1!
-MN0````"Y`0```$ACP4B-!(!(C3R&#[=7!$$/O\`YPGT(08G)1`^W1P3_P8/Y
-M`W[:26/!2(T$@$B-!(8/MU`01`^W0`BY`0```$ECP4B-!(!(C3P`2&/!2(T$
-M.&8Y5$80?0L/MU1&$$0/MT1&"/_!@_D#?N!#C00`9BG"B="8PT%7059!54%4
-M55-(@^P(28G]2(GU2(G72(D,)$R)Z6;'`@``#[=&`B5``0``/4`!``!U$4F-
-MA9`A``!(BU@0#[=(".M0#[=&`B70````/<````!T!SW0````=1%(C8&0(0``
-M2(M80`^W2#CK*`^W1@(EH````+H!````/:`````/A5T!``!)C860(0``2(M8
-M*`^W2""Z`````(7)#XY!`0``#[=5`&8[$W(32&/!2&O`5&8[5`.L=BYF.Q-S
-M#P^W0P)FB0=(B=[I^P```$ACP4AKP%1(`=A(C7"L#[=`KF:)!^GA````0;@`
-M````N@`````YRGTC#[=%`(G&9CL#=AB)T/_"08G`.<I]#4ACPDAKP%1F.S0#
-M=^A(8\)(:_!41`^W)#-)8\!,:_A41@^W!#M%*<1%A>1^<@^_3#,"0@^_5#L"
-M*=$/MT4`1"G`#Z_!00^OU`'0F4'W_&:89HD'2(TT'DR)[^@1_O__1`^_\$P!
-M^TB)WDR)[^C__?__F$$IQ@^W10`/MQ,IT$2)]0^OZ$B)WDR)[^CA_?__F$$/
-MK\2-!"B90??\9ICK)4ACPDAKT%0/MT4`9CL$$W4B#[=$$P)FB0=(C30:3(GO
-MZ*S]__](BQ0D9HD"N@$```#K!;H`````B=!(@\0(6UU!7$%=05Y!7\-!5T%6
-M055!5%532(/L"$F)_DF)]$&)U4&_`0```+T`````.=5S0$ACW4F---Q(C4PD
-M!DB-5"0$3(GWZ,[]__^%P'06#[9$)`1!B$3<!@^V1"0&08A$W`?K!D&_````
-M`/_%1#GM<L!$B?A(@\0(6UU!7$%=05Y!7\-(@^P82(E<)`A(B6PD$$B)]4B)
-M^[_@````Z`````!(B8/@,0``2(7`="#'@X!(``"`````OX````#H`````$B)
-M@WA(``!(A<!U#L=%``(```"X`````.MGQX.`2```0````$C'@W@N````````
-M2,>#@"X```````!(QX.(+@```````$C'@Y`N````````2,>#F"X```````!(
-MQX.@+@```````$C'@Z@N````````2,>#L"X```````"X`0```$B+7"0(2(ML
-M)!!(@\08PY"0D$%7059!54%455-(@^P(28G\08G7B<N]`````$G'Q@````!!
-MB?5(8\5(C01`08L,QDF+5"0@28U$10!!BP2&B001_\/VPS]U"K\!````Z```
-M``#_Q8/]#W;,O0````!(8\6+#,4`````28M4)""+!,4`````B001_\/VPS]U
-M"K\!````Z`````#_Q8']B@```';,O0````!)Q\8`````18G]2&/%2(T$0$&+
-M#(9)BU0D($P!Z$&+!(:)!!'_P_;#/W4*OP$```#H`````/_%@_T_=LY(@\0(
-M6UU!7$%=05Y!7\-!5D%505154TF)_$B)]4&^`````$&]`````&:!/K\2#X?C
-M````#[<^C8=P]___2&/02&G29V9F9DC!ZB#1^HG!P?D?*<J-%)(YT'4CC9P_
-MX.[__TACPTAIP&=F9F9(P>@@B<'!^0*)V)F)RRG3ZU</MS:-AE#W__](8]!(
-M:=)G9F9F2,'J(-'ZB<'!^1\IRHT4DKD`````.=`/A38"``"-G#:@[O__2&/#
-M2&G`9V9F9DC!Z"")P<'Y`HG8F8G+*=-!O@$```#!XP*!X_\```"^"````(G?
-MZ`````")PTF+5"0@BX($H@``9H%]`+0)=06#R!#K"$F+5"0@@^#OB8($H@``
-MZ8,!```/MQ8/M\)IP,W,``#!Z!!FP>@"C02`B=%F*<%F@_D"=4IF@?H[%7=#
-MC4+^#[?`C02`C80`@$3__TAC^$AI_Q^%ZU%(P>\@P?\#P?@?*<?_Q[X(````
-MZ`````")P[X"````OP````#I$`$```^W50`/M\)IP,W,``#!Z!!FP>@$C02`
-MP>`"9CG"=4-F@?K_$W8\#[?"+<`2``!(8_A(:?]G9F9F2,'O(,'_`\'X'RG'
-MP><"O@@```#H`````(G#O@(```"_`P```.FN````#[=5``^WPFG`S<P``,'H
-M$&;!Z`.-!(`!P&8YPG4X#[?"+<`2``!(8_A(:?]G9F9F2,'O(,'_`L'X'RG'
-M`?^^"````.@`````B<.^`@```+\"````ZU@/MU4`#[?":<#-S```P>@09L'H
-M`HT$@+D`````9CG"#X6%````#[?"+<`2``!(8_A(:?]G9F9F2,'O(-'_P?@?
-M*<>^"````.@`````B<.^`@```+\!````Z`````!!B<6)WL'F!$*-!*T`````
-M"<9#C00V"<:!S@$0``!)BU0D($`/ML:)@IR8``#![@A)BU0D((GP@^!_B8+8
-MF```28FL).@3``"Y`0```(G(6UU!7$%=05[#05=!5D%505154TB#[`A)B?U!
-MB=9)B?^]`````$R+I^`Q```/MT8")?`!```]P````'0I/<````!_"3V@````
-M=`OK*SW0````=!+K(@^WMQP5```/MX<>%0``ZQQ!#[>W(!4``$$/MX<B%0``
-MZPJX`````.D;`@``9HE$)`:Y`````$C'QP````!(8]&+!-=!B024_\%T\KD`
-M````00^W_DG'P`````!(8\%(C11`2(T45T&+%)!!B52$!/_!=.BY`````$$/
-MM_Y)Q\``````2&/!2(T40$B-%%=!BQ2008E4A`C_P73HN0````!!#[?^2<?`
-M`````$ACP4B-%$!(C11708L4D$&)5(0,_\&#^1IVY0^W]DF-7"0,0;@`````
-MN:@```"Z`P```$B)W^@`````#[=T)`9!N`````"YI0```+H#````2(G?Z```
-M``"Y`````$$/M_9(Q\<`````2&/!2(T40$B-%%:+%)=!B52$>/_!@_D"=N:[
-M`````$ACPXL,Q0````!)BU4@08L$A(D$$?_%0/;%/W4*OP$```#H`````/_#
-M=-6[`````$ACPTB-%$"+#-4`````28M5($&+1(0$B001_\5`]L4_=0J_`0``
-M`.@`````_\-TT+L`````2&/#2(T40(L,U0````!)BU4@08M$A`B)!!'_Q4#V
-MQ3]U"K\!````Z`````#_PW30NP````!(8\-(C11`BPS5`````$F+52!!BT2$
-M#(D$$?_%0/;%/W4*OP$```#H`````/_#@_L:=LV[`````$ACPTB-%$"+#-4`
-M````28M5($&+1(1XB001_\5`]L4_=0J_`0```.@`````_\.#^P)VS4''A[0Q
-M````````N`$```!(@\0(6UU!7$%=05Y!7\-(BY?@,0``@_X'=R&)\/\DQ0``
-M``!(B=##2(U"!,-(C4((PTB-0@S#2(U">,.X`````,-!B=$/M\),C11&#[_7
-M#[<&.<)]#D''``````#'`0````###[_700^W0OXYPGPH00^WP?_(ZPE,B<A(
-M*?!(T?A!B0")`<-,B<A(*?!(T?B)`?_`08D`PTF)\4PYUG,=#[_700^W`3G0
-M=,U!#[=!`CG"?--)@\$"33G1<N:0PT%7059!54%455-(@^P82(G+38G&08GW
-M9HE4)`Y%B<Q#C2P_0;T`````N`````!F08/Y`0^&VP````^W1"0.9BGP9D$Y
-MQ0^'Q````(GX2,'@!DB)!"0/O_U,C40D%$B-3"0000^WU$B)WN@5____@WPD
-M%`!U",=$)!0!````00^WU(U"_SE$)!!U!XU"_HE$)!"+3"00BU0D%`^W!$MF
-M.P13=0=!#[<43NL[#[_-BW0D$`^_/'-!B<A!*?B+5"0400^W!%9$#Z_`#[\4
-M4XG0*<A!#[<,=@^OP4*-!``I^HG1F??YB<)!#[?%2`,$)$B+3"109HD404'_
-MQ8/%`@^W1"0.9D0I^&9!.<4/AD;___^X`0```$B#Q!A;74%<05U!7D%?PT&)
-M^HGW08G108G+B<AF03GQ="A!#[?R#[?_B?`I^$$/O]`/K\)!#[?)B<HI\D$/
-MO_,/K]8!T"GYF??YF,-!5T%6055!5%532(/L2$F)UDR)1"0@3(E,)!AFB70D
-M+F:)3"0L2(NO<"X``,=$)!``````#[=2%`^_?"0N3(U$)$1(C4PD0$R)]NC4
-M_?__QT0D%`````"X`P```$&)P40K3"041(G(BU0D0$AKTF9(C01`2(TTQ0``
-M``!(`?))C0P61`^W:2!F187M#X3;`0``BU0D$`^W01Y(BYPD@````&:)!%-(
-MC3P23(U$)#@/MU$L9D&)%#B+1"1$2&O`9D@!\$P!\&8[4"Q^"0^W0"QF08D$
-M.(M$)!!,C00`0@^W1`0XB<)FP>H/`=!FT?AF0HE$!#A,C50D,$2)R8M$)$!!
-M#[?]2(T$0$B)PDC!X@1(`=!(C0Q)2,'A`D@!R$@!^$$/MW1&*F9#B30"BT0D
-M1$B-!$!(B<)(P>($2`'02`'(2`'X9D$[=$8J?@M!#[=$1BIF0XD$`D2+9"00
-M30'D0@^W1"0PB<)FP>H/`=!FT?AF0HE$)#!%#[?MBTPD0$AKR69$B<M(C1Q;
-M2,'C`T@!V4P!\4R-02)(@\$L#[_00@^_="0X2(DL)$6)Z8M\)!#H[OS__XM,
-M)$1(:\EF2`'93`'Q3(U!(DB#P2Q"#[]4)#!"#[]T)#A(C84``@``2(D$)$6)
-MZ8M\)!#HM?S__T(/MT0D,$&]`````&9".T0D.'1IBT0D$$B)PDC!X@9(B50D
-M"$0/MWPD+DR-)`!$B>M(`UPD"$0/OX1=``(```^_3%T`BT0D1$$/MQ1&BT0D
-M0$$/MS1&1(G_Z'K]__]FB81=``0``$'_Q4(/MT0D,&9"*T0D.`^WP$$YQ7*Q
-M_T0D$/]$)!2#?"04`P^&W/W__XM$)#A(BTPD(&:)`4&]`````,=$)!0`````
-M1#ML)!`/@_,!``!(C5PD,$R-7"0X1`^W9"0LBT0D$/_(.40D%'47BU0D%`^W
-M!%.#P`1,BW0D&&9!B016ZR>+3"04#[\$2XM4)!3_PD$/OQ13`=")PL'J'P'0
-MT?A(BU0D&&:)!$J^`````(-\)!0`=!^+1"04_\A(BTPD&`^W!$&+5"0400^_
-M%%,IT(G&1"GFBT0D%$C!X`</MY0%`@0``(G19BN,!0`$``"X`0````]$R(7V
-M>4"+1"042,'@!TB-?`4`1`^WP8GP00^OP$2)ZD'_Q0^WCP`$``!F`<&X````
-M``])P4R+M"2(````9D&)!%;_QGC1BU0D%$B-!!)$#[\4`T$/OP0#02G"2(M,
-M)!@/MSQ11`'G*<=%B=%!.?I$#T?/00^_P4&)P#G&?3!(B=%(P>$&1(GH2&/6
-M2(T4"O_&#[>450`$``!,B[0DB````&9!B11&0?_%1#G&?->+1"0408U*_TC!
-MX`9(C0P!08U2_D@!T`^WE$T`!```B=%F*XQ%``0``+@!````#T3(1#G/=E8/
-MO\<YQGU/BT0D%$&-4O](P>`&3(T4`D0/M\$/O_^)\$0IR$$/K\!"#[>,50`$
-M```!P42)ZD'_Q6:#^7^X?P````].P4B+C"2(````9HD$4?_&.?Y\R/]$)!1$
-MBW0D$$0Y="04#X(=_O__@WPD%`-W(HM$)!2+5"04_\I(BTPD&`^W%%%FB11!
-M_T0D%(-\)!0#=MY!@_U_=R!$B>A!C57_2(N<)(@````/MQ139HD40T'_Q4&#
-M_7]VX$B#Q$A;74%<05U!7D%?PT%6055!5%532(/L($B)_4B)RDF)_4B+GWA(
-M```/MT$")=`````]P````'0'/=````!U"4V-I;@I``#K(`^W00(EH````+D`
-M````/:`````/A28!``!,C:>D)0``2(M%((N`;*(``$&)QD&#Y@]!#[?.#[<R
-M2(E<)`A,B00D3(U,)!A,C40D%DR)XDB)[^A]^O__2(M-((N16*(``(#F/T$/
-MMT0D'/_(P>`.)0#````)PHF16*(``&:#?"06`'01#[=$)!;WV&9!B87L,0``
-MZPIF0<>%[#$`````OX"B``"^`````(T,M0````")R`^V%$.-00$/M@1#P>`(
-M"<*-00(/M@1#P>`0"<*#P0,/M@1+P>`8"<*)^4B+12")%`&#QP3_QH/^'W:\
-M2(MU($2)\H/B#P^W1"08P>`$)?`#```)PDB-3"08#[=!`L'@"B4`_```"<(/
-MMT$$P>`0)0``/P`)P@^W00;!X!8E``#`#PG"B99LH@``N0$```")R$B#Q"!;
-M74%<05U!7L-32(G[2(._>$@```!T%TB+OWA(``#H`````$C'@WA(````````
-M2(.[X#$```!T%TB+N^`Q``#H`````$C'@^`Q````````2(.[<"X```!T%TB+
-MNW`N``#H`````$C'@W`N````````6\.Z`````+D#````B<@IT$B-!$!(C03&
-M9H-X"`!T!0^_0!3#_\*#^@-VX;@`````P[H`````B=!(C0Q`#[=$S@AFA<!T
-M#0^WP$B-!(@/OT1&$L/_PH/Z`W;<N`````##05=!5D%505154TB#["A)B?U(
-MB?5)B=9(B4PD($B)^F9!QP8```^W1@(ET````#W`````=`<]T````'4)2(V"
-MN"D``.L@#[=&`B6@````N0`````]H`````^%L0$``$B-AZ0E```/MU`42(U8
-M&+D`````9H72#X24`0``#[=-`&8["W(3#[?"2&O`9F8[3`.:=C5F.PMS'TB)
-MWDR)[^@O____9D&)!DB)WDR)[^CQ_O__Z0T!```/M\)(:\!F2(U<&)KI&@$`
-M`+\`````N0`````/M\*)QCG!?2(/MT4`B<)F.P-V%XG(_\&)QSGQ?0U(8\%(
-M:\!F9CL4`W?I2&/!2&O09D0/MSP32&/'2&O`9DB)1"00#[<$`T$IQT6%_P^.
-MJ0```$R-)!I,B>9,B>_HGO[__YB)1"0<2`-<)!!(B=Y,B>_HB?[__Y@I1"0<
-M#[=%``^W$RG0#Z]$)!R)1"0,2(G>3(GOZ&?^__^800^OQP-$)`R90??_9IAF
-M08D&3(GF3(GOZ!K^__]$#[_@2(G>3(GOZ`O^__^802G$#[=%``^W$RG01(GE
-M#Z_H2(G>3(GOZ.W]__^800^OQXT$*)E!]_]FF$B+5"0@9HD"ZS9(8\%(:]!F
-M#[=%`&8[!!-U+$@!TTB)WDR)[^CE_?__9D&)!DB)WDR)[^BG_?__2(MT)"!F
-MB0:Y`0```.L%N0````")R$B#Q"A;74%<05U!7D%?PT%7059!54%455-(@^P(
-M28G^28GT08G50;\!````O0`````YU7-`2&/=28TTW$B-3"0&2(U4)`1,B??H
-MH?W__X7`=!8/MD0D!$&(1-P&#[9$)`9!B$3<!^L&0;\`````_\5$.>URP$2)
-M^$B#Q`A;74%<05U!7D%?PTB#[!A(B5PD"$B);"002(GU2(G[OX0```#H````
-M`$B)@^`Q``!(A<!T-L>#@$@````!``"_``$``.@`````2(F#>$@``$B%P'06
-MOP`&``#H`````$B)@W`N``!(A<!U#L=%``(```"X`````.M=2,>#>"X`````
-M``!(QX.`+@```````$C'@X@N````````2,>#D"X```````!(QX.8+@``````
-M`$C'@Z`N````````2,>#J"X```````!(QX.P+@```````+@!````2(M<)`A(
-MBVPD$$B#Q!C#05=!5D%505154TB#[`A)B?Q!B=>)R[T`````2<?&`````$&)
-M]4ACQ4B-!$!!BPS&28M4)"!)C41%`$&+!(:)!!'_P_;#/W4*OP$```#H````
-M`/_%@_T==LR]`````$ACQ8L,Q0````!)BU0D((L$Q0````")!!'_P_;#/W4*
-MOP$```#H`````/_%@_U_=L^]`````$G'Q@````!%B?U(8\5(C01`08L,ADF+
-M5"0@3`'H08L$AHD$$?_#]L,_=0J_`0```.@`````_\6#_3]VSDB#Q`A;74%<
-M05U!7D%?PT%6055!5%5328G\2(GU0;X`````0;T`````9H$^OQ(/A^,````/
-MMSZ-AW#W__](8]!(:=)G9F9F2,'J(-'ZB<'!^1\IRHT4DCG0=2.-G#_@[O__
-M2&/#2&G`9V9F9DC!Z"")P<'Y`HG8F8G+*=/K5P^W-HV&4/?__TACT$AITF=F
-M9F9(P>H@T?J)P<'Y'RG*C122N0`````YT`^%"@(``(V<-J#N__](8\-(:<!G
-M9F9F2,'H((G!P?D"B=B9B<LITT&^`0```,'C`H'C_P```+X(````B=_H````
-M`(G#28M4)""+@@2B``!F@7T`M`EU!8/($.L(28M4)""#X.^)@@2B``#I5P$`
-M``^W%@^WPFG`S<P``,'H$&;!Z`*-!(")T68IP6:#^0)U2F:!^CL5=T.-0OX/
-MM\"-!("-A`"`1/__2&/X2&G_'X7K44C![R#!_P/!^!\IQ__'O@@```#H````
-M`(G#O@(```"_`````.GD````#[=5``^WPFG`S<P``,'H$&;!Z`2-!(#!X`)F
-M.<)U+6:!^O\3=B8/M\(MP!(``$AC^$AI_V=F9F9(P>\@P?\#P?@?*<?!YP+I
-M@@````^W50`/M\)IP,W,``#!Z!!FP>@#C02``<!F.<)U(@^WPBW`$@``2&/X
-M2&G_9V9F9DC![R#!_P+!^!\IQP'_ZT(/MU4`#[?":<#-S```P>@09L'H`HT$
-M@+D`````9CG"#X6%````#[?"+<`2``!(8_A(:?]G9F9F2,'O(-'_P?@?*<>^
-M"````.@`````B<.^`@```+\!````Z`````!!B<6)WL'F!$*-!*T`````"<9#
-MC00V"<:!S@$0``!)BU0D($`/ML:)@IR8``#![@A)BU0D((GP@^!_B8+8F```
-M28FL).@3``"Y`0```(G(6UU!7$%=05[#05=!5D%505154TB#[`A)B?U!B==)
-MB?Y!N@````!FQT0D!@``0;D`````9L=$)`0``+T`````3(NGX#$```^W1@(E
-M\`$``#W0````#X3`````/=````!_&SV@````#X2=````/<`````/A*,```#I
-MM0```#U``0``=`L]4`$```^%HP````^W!F8MH0]F/>H$=Q)%#[>6#!4``$$/
-MMX8.%0``ZU4/MP9F+8P49CWO`'<210^WEA`5``!!#[>&$A4``.LV#[<&9BU\
-M%68]X`!W$D4/MY84%0``00^WAA85``#K%V:!/EP6=DE%#[>6&!4``$$/MX8:
-M%0``9HE$)`;K,D0/MX\<%0``#[>''A4``.L010^WCB`5``!!#[>&(A4``&:)
-M1"0$ZPJX`````.G)`@``N0````!(Q\<`````2&/1BP3708D$E/_!=/*Y````
-M`$$/M_])Q\``````2&/!2(T40$B-%%=!BQ2008E4A`3_P73HN0````!!#[?_
-M2<?``````$ACP4B-%$!(C11708L4D$&)5(0(_\%TZ+D`````00^W_TG'P```
-M``!(8\%(C11`2(T45T&+%)!!B52$#/_!@_DD=N6`?@(`#XFB````00^W\4F-
-M7"0,0;@`````N?$```"Z`P```$B)W^@`````#[=T)`1!N`````"Y[@```+H#
-M````2(G?Z`````!!N`(```"Y(P$``+H!````O@$```!(B=_H`````$&#O7P#
-M```)=!5!@[U\`P``"G5Q9D&#O8`#```#=V:^`P```+\&````Z`````")QDF-
-M?"0,0;@#````N8,```"Z`P```.LY00^W\DF-7"0,0;@`````N?<```"Z`P``
-M`$B)W^@`````#[=T)`9!N`````"Y]````+H#````2(G?Z`````"Y`````$$/
-MM_=(Q\<`````2&/!2(T40$B-%%:+%)=!B92$H````/_!@_D"=N.[`````$AC
-MPXL,Q0````!)BU4@08L$A(D$$?_%0/;%/W4*OP$```#H`````/_#=-6[````
-M`$ACPTB-%$"+#-4`````28M5($&+1(0$B001_\5`]L4_=0J_`0```.@`````
-M_\-TT+L`````2&/#2(T40(L,U0````!)BU4@08M$A`B)!!'_Q4#VQ3]U"K\!
-M````Z`````#_PW30NP````!(8\-(C11`BPS5`````$F+52!!BT2$#(D$$?_%
-M0/;%/W4*OP$```#H`````/_#@_LD=LV[`````$ACPTB-%$"+#-4`````28M5
-M($&+A(2@````B001_\5`]L4_=0J_`0```.@`````_\.#^P)VRD''AK0Q````
-M````N`$```!(@\0(6UU!7$%=05Y!7\-(BY?@,0``@_X'=R2)\/\DQ0````!(
-MB=##2(U"!,-(C4((PTB-0@S#2(V"H````,.X`````,-!B=$/M\),C11&#[_7
-M#[<&.<)]#D''``````#'`0````###[_700^W0OXYPGPH00^WP?_(ZPE,B<A(
-M*?!(T?A!B0")`<-,B<A(*?!(T?B)`?_`08D`PTF)\4PYUG,=#[_700^W`3G0
-M=,U!#[=!`CG"?--)@\$"33G1<N:0PT%7059!54%455-(@^P82(G+38G&08GW
-M9HE4)`Y%B<Q#C2P_0;T`````N`````!F08/Y`0^&VP````^W1"0.9BGP9D$Y
-MQ0^'Q````(GX2,'@!DB)!"0/O_U,C40D%$B-3"0000^WU$B)WN@5____@WPD
-M%`!U",=$)!0!````00^WU(U"_SE$)!!U!XU"_HE$)!"+3"00BU0D%`^W!$MF
-M.P13=0=!#[<43NL[#[_-BW0D$`^_/'-!B<A!*?B+5"0400^W!%9$#Z_`#[\4
-M4XG0*<A!#[<,=@^OP4*-!``I^HG1F??YB<)!#[?%2`,$)$B+3"109HD404'_
-MQ8/%`@^W1"0.9D0I^&9!.<4/AD;___^X`0```$B#Q!A;74%<05U!7D%?PT&)
-M^HGW08G108G+B<AF03GQ="A!#[?R#[?_B?`I^$$/O]`/K\)!#[?)B<HI\D$/
-MO_,/K]8!T"GYF??YF,-!5T%6055!5%532(/L2$F)UDR)1"0@3(E,)!AFB70D
-M+F:)3"0L2(NO<"X``,=$)!``````#[=2%`^_?"0N3(U$)$1(C4PD0$R)]NC4
-M_?__QT0D%`````"X`P```$&)P40K3"041(G(BU0D0$AKTF9(C01`2(TTQ0``
-M``!(`?))C0P61`^W:2!F187M#X3;`0``BU0D$`^W01Y(BYPD@````&:)!%-(
-MC3P23(U$)#@/MU$L9D&)%#B+1"1$2&O`9D@!\$P!\&8[4"Q^"0^W0"QF08D$
-M.(M$)!!,C00`0@^W1`0XB<)FP>H/`=!FT?AF0HE$!#A,C50D,$2)R8M$)$!!
-M#[?]2(T$0$B)PDC!X@1(`=!(C0Q)2,'A`D@!R$@!^$$/MW1&*F9#B30"BT0D
-M1$B-!$!(B<)(P>($2`'02`'(2`'X9D$[=$8J?@M!#[=$1BIF0XD$`D2+9"00
-M30'D0@^W1"0PB<)FP>H/`=!FT?AF0HE$)#!%#[?MBTPD0$AKR69$B<M(C1Q;
-M2,'C`T@!V4P!\4R-02)(@\$L#[_00@^_="0X2(DL)$6)Z8M\)!#H[OS__XM,
-M)$1(:\EF2`'93`'Q3(U!(DB#P2Q"#[]4)#!"#[]T)#A(C84``@``2(D$)$6)
-MZ8M\)!#HM?S__T(/MT0D,$&]`````&9".T0D.'1IBT0D$$B)PDC!X@9(B50D
-M"$0/MWPD+DR-)`!$B>M(`UPD"$0/OX1=``(```^_3%T`BT0D1$$/MQ1&BT0D
-M0$$/MS1&1(G_Z'K]__]FB81=``0``$'_Q4(/MT0D,&9"*T0D.`^WP$$YQ7*Q
-M_T0D$/]$)!2#?"04`P^&W/W__XM$)#A(BTPD(&:)`4&]`````,=$)!0`````
-M1#ML)!`/@_,!``!(C5PD,$R-7"0X1`^W9"0LBT0D$/_(.40D%'47BU0D%`^W
-M!%.#P`1,BW0D&&9!B016ZR>+3"04#[\$2XM4)!3_PD$/OQ13`=")PL'J'P'0
-MT?A(BU0D&&:)!$J^`````(-\)!0`=!^+1"04_\A(BTPD&`^W!$&+5"0400^_
-M%%,IT(G&1"GFBT0D%$C!X`</MY0%`@0``(G19BN,!0`$``"X`0````]$R(7V
-M>4"+1"042,'@!TB-?`4`1`^WP8GP00^OP$2)ZD'_Q0^WCP`$``!F`<&X````
-M``])P4R+M"2(````9D&)!%;_QGC1BU0D%$B-!!)$#[\4`T$/OP0#02G"2(M,
-M)!@/MSQ11`'G*<=%B=%!.?I$#T?/00^_P4&)P#G&?3!(B=%(P>$&1(GH2&/6
-M2(T4"O_&#[>450`$``!,B[0DB````&9!B11&0?_%1#G&?->+1"0408U*_TC!
-MX`9(C0P!08U2_D@!T`^WE$T`!```B=%F*XQ%``0``+@!````#T3(1#G/=E8/
-MO\<YQGU/BT0D%$&-4O](P>`&3(T4`D0/M\$/O_^)\$0IR$$/K\!"#[>,50`$
-M```!P42)ZD'_Q6:#^7^X?P````].P4B+C"2(````9HD$4?_&.?Y\R/]$)!1$
-MBW0D$$0Y="04#X(=_O__@WPD%`-W(HM$)!2+5"04_\I(BTPD&`^W%%%FB11!
-M_T0D%(-\)!0#=MY!@_U_=R!$B>A!C57_2(N<)(@````/MQ139HD40T'_Q4&#
-M_7]VX$B#Q$A;74%<05U!7D%?PT%6055!5%532(/L($B)_4B)SDF)_4B+GWA(
-M```/MT$")=`````]P````'0'/=````!U"4V-I;@I``#K(P^W00(EH````$B-
-MCZ0E``!(C9>0(0``/:````!)B<Q,#T7B2(M%((N`;*(``$&)QD&#Y@]!#[?.
-M#[<V2(E<)`A,B00D3(U,)!A,C40D%DR)XDB)[^AZ^O__2(M-((N16*(``(#F
-M/T$/MT0D'/_(P>`.)0#````)PHF16*(``&:#?"06`'01#[=$)!;WV&9!B87L
-M,0``ZPIF0<>%[#$`````OX"B``"^`````(T,M0````")R`^V%$.-00$/M@1#
-MP>`("<*-00(/M@1#P>`0"<*#P0,/M@1+P>`8"<*)^4B+12")%`&#QP3_QH/^
-M'W:\2(MU($2)\H/B#P^W1"08P>`$)?`#```)PDB-3"08#[=!`L'@"B4`_```
-M"<(/MT$$P>`0)0``/P`)P@^W00;!X!8E``#`#PG"B99LH@``N`$```!(@\0@
-M6UU!7$%=05[#4TB)^TB#OWA(````=!=(B[]X2```Z`````!(QX-X2```````
-M`$B#N^`Q````=!=(B[O@,0``Z`````!(QX/@,0```````$B#NW`N````=!=(
-MB[MP+@``Z`````!(QX-P+@```````%O#N@````"Y`P```(G(*=!(C01`2(T$
-MQF:#>`@`=`4/OT`4P__"@_H#=N&X`````,.Z`````(G02(T,0`^W1,X(9H7`
-M=`T/M\!(C02(#[]$1A+#_\*#^@-VW+@`````PT%7059!54%455-(@^P828G]
-M2(GU2(E4)!!(B4PD"$B)^DB+1"009L<````/MT8")=`````]P````'0'/=``
-M``!U"4B-@K@I``#K(P^W1@(EH````$B-CZ0E``!(@<*0(0``/:````!(B<A(
-M#T7"#[=0%$B-6!BX`````&:%T@^$=`$```^W30!F.PL/@C4!```/M\)(:\!F
-M9CM,`YIV&F8["P^"'@$```^WPDAKP&9(C5P8FND-`0``OP````"Y``````^W
-MPHG&.<%](@^W10")PF8[`W87B<C_P8G'.?%]#4ACP4AKP&9F.Q0#=^E(8\%(
-M:]!F1`^W-!-(8\=(:\!F2(D$)`^W!`-!*<9%A?8/CIT```!,C20:3(GF3(GO
-MZ*W^__]$#[_X2`,<)$B)WDR)[^B:_O__F$$IQP^W10`/MQ,IT$0/K_A(B=Y,
-MB>_H?O[__YA!#Z_&0HT$.)E!]_YFF$B+5"009HD"3(GF3(GOZ"W^__]$#[_@
-M2(G>3(GOZ![^__^802G$#[=%``^W$RG01(GE#Z_H2(G>3(GOZ`#^__^800^O
-MQHT$*)E!]_YFF.LR2&/!2&O09@^W10!F.P03=3!(`=-(B=Y,B>_H`/[__TB+
-M5"009HD"2(G>3(GOZ+[]__](BW0D"&:)!K@!````ZP6X`````$B#Q!A;74%<
-M05U!7D%?PT%7059!54%455-(@^P(28G^28GT08G50;\!````O0`````YU7-`
-M2&/=28TTW$B-3"0&2(U4)`1,B??HNOW__X7`=!8/MD0D!$&(1-P&#[9$)`9!
-MB$3<!^L&0;\`````_\5$.>URP$2)^$B#Q`A;74%<05U!7D%?PTB#[!A(B5PD
-M"$B);"002(GU2(G[OZP```#H`````$B)@^`Q``!(A<!T-L>#@$@````!``"_
-M``$``.@`````2(F#>$@``$B%P'06OP`&``#H`````$B)@W`N``!(A<!U#L=%
-M``(```"X`````.M=2,>#>"X```````!(QX.`+@```````$C'@X@N````````
-M2,>#D"X```````!(QX.8+@```````$C'@Z`N````````2,>#J"X```````!(
-MQX.P+@```````+@!````2(M<)`A(BVPD$$B#Q!C#*%`6+%@H````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````H/^C_Y[_H/^C_Z#_````````!0`*`!0`'@`R`$8`50!:`%\`9```````
-M```````````*`!0`'@`H`#(`/`!&`%``6@!D``````````````#"````Q```
-M`,4```#0````V@```.0``````````````,(```##````U````/(````-`0``
-M*`$``,\```#*`````@!0(0$`0`$$`*``"`#``"``T`!``%`!````````````
-M````````````````````)`&8&0`F$`8`````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M________`````````````````````````)@``$<````(F`````````R8``"F
-MCH0)$)@```#@,CT4F```:P<``!R8````````()@````"`@(DF```#@X``"B8
-M```!`@(*+)@``/QO`P`PF````````#28```.#@``.)@```<````\F`````$"
-M`$"8`````&.)1)@``)P6<A-(F```,[88`$R8```\88024)@``."XZ`U4F```
-M64@'`%B8``"ZOH!^7)@``%YF.C%@F```"!T``&28````S@$`:)@``)!!FD!P
-MF```#P```'28``"`````>)@```0`````F0````````29````````")D`````
-M```,F0````"``!"9```#`````)L````````$FP``(`````B;```0````#)L`
-M`#`````0FP``"````!2;```H````&)L``"@````<FP``!````"";```D````
-M))L``!0````HFP``-````"R;```,````,)L``"P````TFP```@```#B;```B
-M````/)L``!(```!`FP``,@```$2;```*````2)L``"H```!,FP```0```%";
-M```A````5)L``!$```!8FP``,0```%R;```)````8)L``"D```!DFP``!0``
-M`&B;```E````;)L``!4```!PFP``-0```'2;```-````>)L``"T```!\FP``
-M`P```(";```C````A)L``!,```"(FP``,P```(R;```+````D)L``"L```"4
-MFP``!P```)B;```G````G)L``!<```"@FP``-P```*2;```/````J)L``"\`
-M``"LFP``+P```+";```O````M)L``"\```"XFP``+P```+R;```O````P)L`
-M`"\```#$FP``+P```,B;```O````S)L``"\```#0FP``+P```-2;```O````
-MV)L``"\```#<FP``+P```.";```O````Y)L``"\```#HFP``+P```.R;```O
-M````\)L``"\```#TFP``+P```/B;```O````_)L``"\`````F@``'0````2:
-M``!=````")H``)T````,F@``W0```!":```=`0``%)H``"$````8F@``80``
-M`!R:``"A````()H``.$````DF@``,0```"B:``!Q````+)H``+$````PF@``
-M'````#2:``!<````.)H``"D````\F@``:0```$":``"I````1)H``"````!(
-MF@``&0```$R:``!9````4)H``)D```!4F@``,````%B:```%````7)H``"4`
-M``!@F@``90```&2:``"E````:)H``"@```!LF@``:````'":```?````=)H`
-M`!X```!XF@``&````'R:``!8````@)H``)@```"$F@```P```(B:```$````
-MC)H``$0```"0F@``A````)2:```3````F)H``!(```"<F@``4@```*":``"2
-M````I)H``-(```"HF@``*P```*R:```J````L)H``&H```"TF@``J@```+B:
-M```;````O)H``!H```#`F@``6@```,2:``":````R)H``-H```#,F@``!@``
-M`-":```&````U)H```8```#8F@``!@```-R:```&````X)H```8```#DF@``
-M!@```.B:```&````[)H```8```#PF@``!@```/2:```&````^)H```8```#\
-MF@``!@```-28```@````S)@```0```#(F```!@$&`)R8``!M````P)@`````
-M``#0F```%```````````````"0D```````("!@8&!@8&`@(````#``8`"0`\
-M`````````````````````````````````````/````#,````````````````
-M````"N(````@```*`@```1@```$```!`&`0`````````````````````````
-M```````````````%!%<9`"80!@``````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````````````!L"8\)
-MM`D```````````````````````#_______\`````````````````````````
-M```````````````@````(````$````!````````&````!@````8`,````!4`
-M```5````'0```!4```!`$```#_PO``_\+P`?_"\`#_PO`$00```/_"\`#_PO
-M`!_\+P`/_"\`2!````_\+P`/_"\`'_PO``_\+P!,$```#_PO``_\+P`?_"\`
-M#_PO`%`0```/_"\`#_PO`!_\+P`/_"\`5!````_\+P`/_"\`'_PO``_\+P!8
-M$```#_PO``_\+P`?_"\`#_PO`%P0```/_"\`#_PO`!_\+P`/_"\`8!````_\
-M+P`/_"\`'_PO``_\+P!D$```#_PO``_\+P`?_"\`#_PO`'`0``!H`0``X`$`
-M`+@!``!H`0``,!```#`"``#@`0``L````#`"``"P$```F`T``(`1``!('P``
-MF`T``/`0``#@H```:$`!`(!8``#@H```%(`````$``0`"``(`#``(``$``0<
-M@```IX^-#L^/C0Z5CV`!IX^-#@28`````````P``````````````()@````"
-M`@(``@("``(!`@`"`@(DF```#@X```X.```'!P``#@X``"B8```!``(*`0`"
-M"@```04!``(*-)@```X.```.#@``#@X```X.```XF```!P````<````+````
-M"P```$28``"<%G(3I19R$Z@6<A.<%G(32)@``&>Z&`!GNA@`:;H8`&FZ&`!0
-MF```X+0H#."T*`S@M"@,X+0H#%B8```N#8!^+@V`?BX-P'XN#8!^7)@``%Y=
-M-S%>73<Q7ETZ,5Y=-S%@F```$+T``!"]```XO0``$+T``&28````S@$``,X!
-M``#.`0``S@$`%)D``!`G```0)P``?!4``!`G```8F0``D`$``)`!``"$````
-MD`$``$29```@$.!O(!#@;R`)X&\@$.!O@*$``/\4_P7_%/\%_Q3_!?\9_P74
-MF```$````!0````0````$``````````,`````````"@```"<G(2$+````'Q\
-M?'PT````!0```$``````````1`````@```!(````"````$P````0````4```
-M``````!4````'P`````(````````!`@````````("`````````P(````````
-M$`@````````4"````````!@(````````'`@````````@"````````"0(````
-M````,!(````````$@`````````B`````````#(`````````8@````````"2`
-M````````*(```#`````L@```__\'`#"```#___\!-(```#$````X@```````
-M`#R`````````0(````````!$@````@```$B`````````5(````````!8@```
-M``````B8````````#)@``).0A"T0F````.`R?128``!K#P``')@````````L
-MF```_F\"`#"8````````/)@````!`@!`F```>@%J($R8```\88025)@``%D(
-M``!HF```D$&:0&R8``"!L`P%<)@```\```!TF```@````'B8```,`````)D`
-M```````$F0````````B9````````#)D`````@``0F0```0```!R9```J"0``
-M()D````````DF0``!8H%`"B9```!````+)D````````PF0```````#29````
-M````.)D````````\F0``/P```$"9```$````2)D```````!,F0```````%"9
-M````````5)D``$SQ4%U8F0``&````%R9``".:DL`A*$``/\%_P:(H0``_P?_
-M!XRA``#_"/\(D*$``/\)_PF4H0``_PK_"IBA``#_"_\+G*$``/\,_PR@H0``
-M_PW_#:2A``#_#O\/J*$``/\2_Q*LH0``_Q/_%+"A``#_%?\6M*$``/\7_QFX
-MH0``_QK_&[RA``#_'?\>P*$``/\@_R/$H0``_R7_)\BA``#_*?\LS*$``/\O
-M_S'0H0``_S3_-]2A``#_.O\ZV*$``/\Z_SK<H0``_SK_.N"A``#_.O\ZY*$`
-M`/\Z_SKHH0``_SK_.NRA``#_.O\Z\*$``/\Z_SKTH0``_SK_.OBA``#_.O\Z
-M_*$``/\Z_SH`FP````````2;```@````")L``!`````,FP``,````!";```(
-M````%)L``"@````8FP``!````!R;```D````()L``!0````DFP``-````"B;
-M```,````+)L``"P````PFP```@```#2;```B````.)L``!(````\FP``,@``
-M`$";```*````1)L``"H```!(FP``!@```$R;```F````4)L``!8```!4FP``
-M-@```%B;```.````7)L``"X```!@FP```0```&2;```A````:)L``!$```!L
-MFP``,0```'";```)````=)L``"D```!XFP``!0```'R;```E````@)L``!4`
-M``"$FP``-0```(B;```-````C)L``"T```"0FP```P```)2;```C````F)L`
-M`!,```"<FP``,P```*";```+````I)L``"L```"HFP``*P```*R;```K````
-ML)L``"L```"TFP``*P```+B;```K````O)L``"L```#`FP``*P```,2;```K
-M````R)L``"L```#,FP``*P```-";```K````U)L``"L```#8FP``*P```-R;
-M```K````X)L``"L```#DFP``*P```.B;```K````[)L``"L```#PFP``*P``
-M`/2;```K````^)L```(```#\FP``%@```-28```@````V)@``&@08```````
-M``````":``"I`0````````2:``#I`0``0`````B:```I````@`````R:``!I
-M````4`$``!":``"9`0``D`$``!2:``#9`0``T`$``!B:```9````$````!R:
-M``!9````1````"":``"9````A````"2:``"E`0``2`$``"B:``#E`0``B`$`
-M`"R:```E````R`$``#":``#(`0``%````#2:```(````0@```#B:``!(````
-M@@```#R:``"(````>`$``$":``"8`0``N`$``$2:``#8`0``^`$``$B:```8
-M````$@```$R:``!8````4@```%":``"8````D@```%2:``"D`0``?`$``%B:
-M``#D`0``O`$``%R:```D````_`$``&":``!D````"@```&2:``"D````2@``
-M`&B:``#D````B@```&R:```*`0``6@$``'":``!*`0``F@$``'2:``"*`0``
-MV@$``'B:``#*`0``#@```'R:```*````3@```(":``!*````C@```(2:``"*
-M````7@$``(B:``"Z`0``G@$``(R:``#Z`0``W@$``)":```Z````"0```)2:
-M``!Z````20```)B:``"&`0``B0```)R:``#&`0``>0$``*":```&````N0$`
-M`*2:``!&````^0$``*B:``"&````.0```*R:``#&````>0```+":``#&````
-MN0```+2:``#&````O0$``+B:``#&````_0$``+R:``#&````/0```,":``#&
-M````?0```,2:``#&````O0```,B:``#&````_0```,R:``#&````_0```-":
-M``#&````_0```-2:``#&````_0```-B:``#&````_0```-R:``#&````_0``
-M`.":``#&````_0```.2:``#&````_0```.B:``#&````_0```.R:``#&````
-M_0```/":``#&````_0```/2:``#&````_0```/B:``#&````_0```/R:``#&
-M````_0````$```!&````8`````$```!&````80````$```!&````8@````$`
-M``!&````8P````$```!&````9`````$```!&````90````$```!&````9@``
-M``$```!&````9P````$```!&````:`````$```!&````:0````$```!&````
-M:@````$```!&````:P````$```!&````;`````$```!&````=`````$```!&
-M````=`````$```!&````=`````$```!&````=`````$```!&````=`````$`
-M``!&````=`````$```!&````=`````$```!&````=`````$```!&````=0``
-M``$```!&````=@````$```!&````=P````$```!&````>`````$```!&````
-M>0````$```!&````>@````$```!&````>P````$```!&````?`````$```!&
-M````?0````$```!&````?@````$```!&````?P````$```!&````@`````$`
-M``!$````?`````$```!&````B`````$```!&````C`````$```!&````D```
-M``$```!&````E`````$```!&````F`````$```!&````G`````$```!&````
-MH`````$```!&````I`````$```!&````J`````$```!&````K`````$```!&
-M````L`````$```!&````M``````"!P```````````````````````````)X6
-M"P!B%@H`.A8)`!P6"`#J%0<`FA4%`$H5!``#%0(`610``````0````,`!@`)
-M`#\`````````````````````````````````````````````````````````
-M````````````````````````````````````````````````"0````0````$
-M``$``0`!``8```!&1S@`````````````````!`````$``0`$````1D<W````
-M``````````````,``0`!``$``P```$9'-@`````````````````$```````!
-M``$```!&1S4`````````````````!``!``$`````````1D<T````````````
-M``````0````!````_O___T9',P`````````````````#``$``0```/W___]&
-M1S(`````````````````!`````````#\____1D<Q``````````````````(`
-M`0`!````^O___T9',```````````````````````````````````````````
-M````````````%!!4&0`F$`8`````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````;`F/";0)
-M"`EL";0)________!0(/!P(/"@`/"0`/````````````````````````````
-M```````````````````````````````````````````````````````@````
-M(````$````!````````&````!@````8`GA8+`&(6"@`Z%@D`'!8(`.H5!P":
-M%04`2A4$``,5`@!9%```N`L!````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````````````&`````0````(````#````!`````4`````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M`````````````````````````````````````````````$`0```/_"\`#_PO
-M`!_\+P`/_"\`#_PO`$00```/_"\`#_PO`!_\+P`/_"\`#_PO`$@0```/_"\`
-M#_PO`!_\+P`/_"\`#_PO`$P0```/_"\`#_PO`!_\+P`/_"\`#_PO`%`0```/
-M_"\`#_PO`!_\+P`/_"\`#_PO`%00```/_"\`#_PO`!_\+P`/_"\`#_PO`%@0
-M```/_"\`#_PO`!_\+P`/_"\`#_PO`%P0```/_"\`#_PO`!_\+P`/_"\`#_PO
-M`&`0```/_"\`#_PO`!_\+P`/_"\`#_PO`&00```/_"\`#_PO`!_\+P`/_"\`
-M#_PO`#`0```P`@``X`$``+````!@`0``X`$``'`0``!H`0``X`$``+@!``",
-M`0``X`$``+`0``!@#@``@!$``!P?```X/@``@!$``/`0``#@H```:$`!`(!8
-M``#@L```:$`!`!2```#H`^@#X`;@!B`$(`1`"$`(X`;@!@28`````````P``
-M`````````````P```""8`````@("``("`@`"`0(``@("``("`B28```.#@``
-M#@X```<'```.#@``#@X``$28```<%G(3)1QR$R(7<A.B%G(3)1QR$V"8```0
-MG0``$)T``!B=```8G0``$)T``&28````S@$``,X!``#.`0``S@$``,X!`&B8
-M``"009I`D$&:0)!!FD"009I`D$&:0!B9``"X`0``N`$``(0````(`0``N`$`
-M`"29```%B@40!8H%$`6*!1`%B@40!8H%$#"B```````````````````(`0``
-M````````````````#``````````T````!0```$``````````1`````@```!(
-M````"````$P````0````4`````````!4````'P`````(````````!`@`````
-M```("`````````P(````````$`@````````4"````````!@(````````'`@`
-M```````@"````````"0(````````<!(````````X$````````'@0````````
-MN!````````#X$````````#@1````````>!$```````"X$0```````/@1````
-M````.!(```````!X$@```````+@2````````^!(````````X$P```````'@3
-M````````N!,```````#X$P```````#@4````````>!0```````"X%```````
-M`/@4````````.!4```````!X%0```````+@5````````^!4````````X%@``
-M`````'@6````````N!8```````#X%@```````#@7````````>!<```````"X
-M%P```````/@7````````/!````````!\$````````+P0````````_!``````
-M```\$0```````'P1````````O!$```````#\$0```````#P2````````?!(`
-M``````"\$@```````/P2````````/!,```````!\$P```````+P3````````
-M_!,````````\%````````'P4````````!(`````````(@`````````R`````
-M````((`````````D@````````"B````P````+(```/__!P`P@```____`32`
-M```Q````.(`````````\@````````$B`````````5(````````!8@```````
-M`%R```"/QP\`P(```!HP@BK$@```X`'<!<B````0)T`?S(``````]`'0@```
-M'!X``-2```"JJ@(`V(```%55``+<@````````."```#_____Y(```/__``#H
-M@````````.R`````````\(````````#T@````````/B`````````_(```(@`
-M````AP````````2'``",````"(<``.0````,AP``U0(``!"'````````%(<`
-M```````8AP``H````!R'``#)`0``((<``"P````DAP``+````"B'```P````
-M+(<``#P````PAP``+````#2'```L````.(<``#`````\AP``/````$"'````
-M````1(<```````!(AP```````$R'````````4(<```````!4AP```````%B'
-M````````7(<```````!@AP``U0```&2'``#?````:(<```(!``!LAP``.@$`
-M`'"'``!U````=(<``'\```!XAP``H@```'R'`````````($```(``0`$@0``
-M`0````B!``#`````#($````````0@0``:`$``!2!````````P(<````!`@/$
-MAP``!`4&!\B'```("0H+S(<```P-#@_0AP``$!$2$]2'```4%187V(<``!@9
-M&AO<AP``'!T>'^"'`````0(#Y(<```0%!@?HAP``"`D*"^R'```,#0X/\(<`
-M`!`1$A/TAP``%!46%_B'```8&1H;_(<``!P='A\,F```&8Z$K1"8````X"A]
-M%)@``&N?"IP<F````````$"8``!Z`6H@5)@``%D(````F0````````29````
-M````")D````````,F0````"``!"9```!````')D``(`,```@F0`````0!2B9
-M```!````+)D```0````TF0``(B`?'CB9```-#`L*/)D``#\```!(F0``$K*`
-MDE29``"(X5!=7)D``(YJ2P!HF0``S@,``'"9```5M2\9>)D```$```!\F0``
-M`````!"B```S8X``%*(``!!L$``8H@``8$"<`""B``#&,(@!)*(````$```L
-MH@```````#2B```@("`@.*(``"`@("!`H@``(`I).$2B``"V>P``2*(``/P_
-M_P\`FP```````"B;```,````.)L``!(```!DFP``(0```(R;```M````G)L`
-M`#,```````,`!@`)`#\````#``8`"0`_``````````````````D````$````
-M!``!``$``0````````````8```!&1S@`````````````````!`````$``0``
-M``````````0```!&1S<``````````````````P`!``$``0````````````,`
-M``!&1S8`````````````````!````````0````````````$```!&1S4`````
-M````````````!``!``$```````````````````!&1S0`````````````````
-M!`````$``````````````/[___]&1S,``````````````````P`!``$`````
-M`````````/W___]&1S(`````````````````!````````````````````/S_
-M__]&1S$``````````````````@`!``$``````````````/K___]&1S``````
-M````````````````````````````````````````````````````````````
-M``````````````````````@````!`````P````````````````````8```!&
-M1S<``````````````````@````````````````````````!&1S8`````````
-M`````````0```````````````````/W___]&1S4`````````````````````
-M`````````````````/K___]&1S0````````````````````!``$`````````
-M`````/C___]&1S,````````````````````!``$````!``$``````/;___]&
-M1S(````````````````````!`````0`!``$``````//___]&1S$`````````
-M```````````!`````0`!`````0```/#___]&1S``````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````P````%8```!6````5@```%8```!6````<@```IX^-
-M$L\/B`F5#^`$JP_@$L\/B`DHF````0`""@$``@H``0$%`0`""@$``@HTF```
-M#@X```X.```.#@``#@X```X.```XF```!P````<````+````"P````L```!(
-MF```6MH8`%K:&`!IRA@`:<H8`&G*&`!0F```X+3H#>"TZ`W@M.@-X+3H#>"T
-MZ`U8F```+@V`?BX-@'XN3>A^+DWH?BX-@'Y<F```7F8W,5YF-S%>9C<Q7F8W
-M,5YA-S%LF```@;`,!8&P#`6!L`P%@+`,!8"P#`44F0``$"<``!`G``!\%0``
-M^"H``!`G``!$F0``(!"X]R`0N/<@#;CW(!"X]R`0N/<,H@``:D$L9&I!+&1J
-M04!D:D%`9&I!0&0<H@``"H"#&`J`@Q@*@',8"H"#&`J`@Q@`````````````
-M````````,!(````````(F````````"R8``#^+P(`/)@````!`@!,F```/&&$
-M$C"9``"#2```0)D```0```!8F0``_P```'29````````^)D``!@````$H@``
-M``````BB``"(9S[0**(``+4!```\H@``KXG($P2;```@````")L``!`````,
-MFP``,````!";```(````%)L``"@````8FP``!````!R;```D````()L``!0`
-M```DFP``-````"R;```L````,)L```(````TFP``(@```#R;```R````0)L`
-M``H```!$FP``*@```$B;```&````3)L``"8```!0FP``%@```%2;```V````
-M6)L```X```!<FP``+@```&";```!````:)L``!$```!LFP``,0```'";```)
-M````=)L``"D```!XFP``!0```'R;```E````@)L``!4```"$FP``-0```(B;
-M```-````D)L```,```"4FP``(P```)B;```3````H)L```L```"DFP``*P``
-M`*B;```K````K)L``"L```"PFP``*P```+2;```K````N)L``"L```"\FP``
-M*P```,";```K````Q)L``"L```#(FP``*P```,R;```K````T)L``"L```#4
-MFP``*P```-B;```K````W)L``"L```#@FP``*P```.2;```K````Z)L``"L`
-M``#LFP``*P```/";```K````])L``"L```#XFP```@```/R;```6````G)@`
-M````````````````````````````G)@`````````````````````````````
-MG)@`````````````````````````````G)@`````````````````````````
-M````G)@`````````````````````````````G)@`````````````````````
-M````````G)@`````````````````````````````G)@`````````````````
-M````````````G)@`````````````````````````````G)@`````````````
-M````````````````G)@`````````````````````````````G)@`````.```
-M`#@````X````.````#@`G)@`````````````````````````````G)@`````
-M````````````````````````G)@`````````````P````(````"`````G)@`
-M`/D`!`#Y``0`_P`$`/T`!`#]``0`U)@`````````````!`````0````$````
-M````````````F@``J0$````````$F@``Z0$``$`````(F@``*0```(`````,
-MF@``:0```%`!```0F@``F0$``)`!```4F@``V0$``-`!```8F@``&0```!``
-M```<F@``60```$0````@F@``F0```(0````DF@``I0$``$@!```HF@``Y0$`
-M`(@!```LF@``)0```,@!```PF@``R`$``!0````TF@``"````$(````XF@``
-M2````((````\F@``B````'@!``!`F@``F`$``+@!``!$F@``V`$``/@!``!(
-MF@``&````!(```!,F@``6````%(```!0F@``F````)(```!4F@``I`$``'P!
-M``!8F@``Y`$``+P!``!<F@``)````/P!``!@F@``9`````H```!DF@``I```
-M`$H```!HF@``Y````(H```!LF@``"@$``%H!``!PF@``2@$``)H!``!TF@``
-MB@$``-H!``!XF@``R@$```X```!\F@``"@```$X```"`F@``2@```(X```"$
-MF@``B@```%X!``"(F@``N@$``)X!``",F@``^@$``-X!``"0F@``.@````D`
-M``"4F@``>@```$D```"8F@``A@$``(D```"<F@``Q@$``'D!``"@F@``!@``
-M`+D!``"DF@``1@```/D!``"HF@``A@```#D```"LF@``Q@```'D```"PF@``
-MQ@```+D```"TF@``Q@```+T!``"XF@``Q@```/T!``"\F@``Q@```#T```#`
-MF@``Q@```'T```#$F@``Q@```+T```#(F@``Q@```/T```#,F@``Q@```/T`
-M``#0F@``Q@```/T```#4F@``Q@```/T```#8F@``Q@```/T```#<F@``Q@``
-M`/T```#@F@``Q@```/T```#DF@``Q@```/T```#HF@``Q@```/T```#LF@``
-MQ@```/T```#PF@``Q@```/T```#TF@``Q@```/T```#XF@``Q@```/T```#\
-MF@``Q@```/T```#4F```(```````````````U)@``!`````4````$````!``
-M```4``````````````#8F```:!!@`&@08`!H$&``:!!@`&@08```````````
-M``````````````````````"<F`````````````````````````````"<F```
-M``````````````````````````"<F`````````````````````````````"<
-MF`````````````````````````````"<F```````````````````````````
-M``"<F```````$````!`````0````$````!"<F```````!`````0````$````
-M!`````2<F`````````````````````````````"<F```````````````````
-M``````````"<F`````````````````````````````"<F```````````````
-M```*``````````"<F```P``X`(``.`#``#@"P``X`,``.`"<F```!@`"``8`
-M`@`&````!@`"``8``@"<F```B0```(D```")````B0```(D```"<F```H```
-M`*````"@````H````*````"<F```!P`$``<`!``'``0`!P`$``<`!`#4F```
-M&@```!H````:````&@```!H``````````````)R8``!`````2````$````!`
-M````0````)R8```0````$````!`````0````$````)R8```(````"`````@`
-M```(````"````)R8``!/````3P```$\```!/````3P```)R8``#Q````\0``
-M`&$```#Q````\0```)R8``!/D```3Y```$R0``!/D```3Y```)R8``!:$@``
-M6A(``)H2``!:$@``6A(``,R8```.````#@````\````.````#@````$```!&
-M````8`````$```!&````80````$```!&````8@````$```!&````8P````$`
-M``!&````9`````$```!&````90````$```!&````9@````$```!&````9P``
-M``$```!&````:`````$```!&````:0````$```!&````:@````$```!&````
-M:P````$```!&````;`````$```!&````=`````$```!&````=`````$```!&
-M````=`````$```!&````=`````$```!&````=`````$```!&````=`````$`
-M``!&````=`````$```!&````=`````$```!&````=0````$```!&````=@``
-M``$```!&````=P````$```!&````>`````$```!&````>0````$```!&````
-M>@````$```!&````>P````$```!&````?`````$```!&````?0````$```!&
-M````?@````$```!&````?P````$```!&````@`````$```!$````?`````$`
-M``!&````B`````$```!&````C`````$```!&````D`````$```!&````E```
-M``$```!&````F`````$```!&````G`````$```!&````H`````$```!&````
-MI`````$```!&````J`````$```!&````K`````$```!&````L`````$```!&
-M````M```````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````">%@8`8A8$`#H6`P`<%@(`ZA4!`)H5``!*%0```Q4!`%D4`P"X"P4`
-M````````````````````````````````,````!6````5@```%8```!6````5
-M@```'(```*>3C1+/$X@)E1/@!*L3X!+/$X@)*)@```$``@H!``(*``$"!0$`
-M`@H!``(*-)@```X.```.#@``#@X```X.```.#@``.)@```<````'````"P``
-M``L````+````2)@``&W:&`!MVA@`=<H8`'7*&`!URA@`4)@``."TZ`W@M.@-
-MX+3H#>"TZ`W@M.@-6)@``"X-@'XN#8!^+@WH?BX-Z'XN#8!^7)@``%YF-S%>
-M9C<Q7F8W,5YF-S%>9C<Q;)@``(&P#`6!L`P%@;`,!8&P#`6!L`P%%)D``-`'
-M``#0!P``3`0``)@(``#0!P``1)D``"`0N/<@$+CW$`VX]Q`0N/<0$+CW!*(`
-M````````````"`````@````(````"*(``(AGOM:(9[[6B&<^T(AG/M"(9S[0
-M#*(``$`!+&1``2QD8,%"9&#!0F1@P4)D'*(```J`@Q@*@(,8"H!S&`J`@Q@*
-M@(,8,!(````````(F````````"R8``#^+P(`/)@````!`@!,F```/&&$$C"9
-M``""2```0)D```0```!8F0``_P```'29````````**(``+4!```\H@``KXG(
-M$P2;```!````")L```(````,FP```P```!";```$````%)L```4````8FP``
-M"````!R;```)````()L```H````DFP``"P```"R;```-````,)L``!`````T
-MFP``$0```#R;```3````0)L``!0```!$FP``%0```$B;```8````3)L``!D`
-M``!0FP``&@```%2;```;````6)L``!P```!<FP``'0```&";```@````:)L`
-M`"(```!LFP``(P```'";```D````=)L``"4```!XFP``*````'R;```I````
-M@)L``"H```"$FP``*P```(B;```L````D)L``#````"4FP``,0```)B;```R
-M````H)L``#0```"DFP``-0```*B;```U````K)L``#4```"PFP``-0```+2;
-M```U````N)L``#4```"\FP``-0```,";```U````Q)L``#4```#(FP``-0``
-M`,R;```U````T)L``#4```#4FP``-0```-B;```U````W)L``#4```#@FP``
-M-0```.2;```U````Z)L``#4```#LFP``-0```/";```U````])L``#4```#X
-MFP``$````/R;```:`````````````````````````````````````)H```<`
-M```'````!)H``$<```!'````")H``(<```"'````#)H``*`!``"@`0``$)H`
-M`.`!``#@`0``%)H``"`````@````&)H``&````!@````')H``*$!``"A`0``
-M()H``.$!``#A`0``))H``"$````A````*)H``&$```!A````+)H``&(!``!B
-M`0``,)H``*(!``"B`0``-)H``.(!``#B`0``.)H``"(````B````/)H``&(`
-M``!B````0)H``&,!``!C`0``1)H``*,!``"C`0``2)H``.,!``#C`0``3)H`
-M`",````C````4)H``&,```!C````5)H``(0!``"$`0``6)H``,0!``#$`0``
-M7)H```0````$````8)H``.H!```+````9)H``"H```!+````:)H``&H```"+
-M````;)H``*H```"L`0``<)H``*L!``#L`0``=)H``.L!```L````>)H``"L`
-M```2````?)H``&L```!2````@)H``*L```"2````A)H``*P!``"3`0``B)H`
-M`.P!``#3`0``C)H``"P````3````D)H``#H```!3````E)H``'H```"3````
-MF)H``+H```"4`0``G)H``+L!``#4`0``H)H``/L!```4````I)H``#L````Z
-M````J)H``'L```!Z````K)H``+L```"Z````L)H``+P!``"[`0``M)H``/P!
-M``#[`0``N)H``#P````[````O)H``'P```![````P)H``+P```"[````Q)H`
-M`/P```"\`0``R)H``/P```#\`0``S)H``/P````\````T)H``/P```!\````
-MU)H``/P```"\````V)H``/P```#\````W)H``/P```#\````X)H``/P```#\
-M````Y)H``/P```#\````Z)H``/P```#\````[)H``/P```#\````\)H``/P`
-M``#\````])H``/P```#\````^)H``/P```#\````_)H``/P```#\````U)@`
-M`"```````````````-"8```(!`8#"`0'`P@$!@,(!`8#"`0'`P``````````
-MW)@``,`@H`#`(*``P"#@`,`@X`#`(.``````````````````````````````
-M````G)@```````\````/````#P````\````/G)@`````````````````````
-M````````G)@`````@````(````"`````@````(``G)@`````*@```"H````J
-M````*@```"H`G)@``````0````$````!`````0````$`G)@`````````````
-M````````````````G)@`````&````!@````8````&````!@`G)@`````8```
-M`&````!N````;@```&X`G)@`````QP```,<```#'````QP```,<`G)@`````
-M2P```$L```!+````2P```$L`G)@`````2`0``$@$``!(!```2`0``$@$G)@`
-M````3````$P```!,````3````$P`G)@`````Y````.0```#D````Y````.0`
-MG)@`````````````````````````````G)@`````_````/P```#\````_```
-M`/P`G)@`````_P```/\```#_````_P```/\`G)@`````/P0``#\$```_!```
-M/P0``#\$G)@`````#`````P````,````#`````P`G)@`````&0(``!D"```9
-M`@``&0(``!D"G)@`````)````"0````D````)````"0`G)@`````M````+0`
-M``"T````M````+0`G)@`````F0```)D```"9````F0```)D`G)@`````4```
-M`%````!0````4````%``G)@`````*@```"H````J````*@```"H`G)@`````
-M$@```!(````2````$@```!(`G)@`````,L```#+````RP```,L```#+`G)@`
-M````=`$``'0!``!T`0``=`$``'0!G)@`````$0```!$````1````$0```!$`
-MG)@`````*(8``"B&```HA@``*(8``"B&G)@`````A#$``(0Q``"$,0``A#$`
-M`(0QG)@``(``\@"``/(`@`#R`(``\@"``/(`G)@``!D`)P`9`"<`&0`G`!D`
-M)P`9`"<`G)@```,````#`````P````,````#````G)@`````````````````
-M````````````G)@``+(```"R````L@```+(```"R````G)@``(0@L`"$(+``
-MA""P`(0@L`"$(+``G)@``*0E00"D)4$`I"5!`*0E00"D)4$`G)@``""2$0`@
-MDA$`()(1`""2$0`@DA$`G)@```!(&@``2!H``$@:``!(&@``2!H`V)@``#`"
-M"P`P`@L`,`(+`#`""P`P`@L`G)@``)0```"4````E````)0```"4````G)@`
-M`)$```"1````D0```)$```"1````G)@``!(````2````$@```!(````2````
-MG)@``(````"`````@````(````"`````G)@``-D```#9````V0```-D```#9
-M````G)@``&````!@````8````&````!@````G)@``/````#P````\````/``
-M``#P````G)@``*(```"B````H@```*(```"B````G)@``%(```!2````4@``
-M`%(```!2````G)@``-0```#4````U````-0```#4````G)@``,P4``#,%```
-MS!0``,P4``#,%```G)@``(P$``",!```C`0``(P$``",!```Q)@```,````#
-M`````P````,````#````````````````````````````````````````````
-M````````````````````````````````````````````````````````,```
-M`!4````5````%0```!4````5````'(```*>3C1+/$X@)E1/@!*L3X!+/$X@)
-M*)@```$``@H!``(*```"!0$``@H!``(*-)@````.````#@````X````.````
-M#@``.)@```(````"````"@````H````*````2)@``&W:&`!MVA@`9&H:`&1J
-M&@!D:AH`4)@``."TZ`W@M.@-VK#H#=JPF`S:L.@-6)@``"X-@'XN#8!^+@WH
-M?BX-R'XN#8!^7)@``%YF-S%>9C<Q7F8W,5Y@.3%>9C<Q;)@``(&P#`6!L`P%
-M@;`,!8&P#`6!L`P%%)D``-`'``#0!P``3`0``)@(``#0!P``1)D````0N/<`
-M$+CW``VX]P`0N/<`$+CW!*(`````````````````````````````"*(``(AG
-MOM:(9[[6B&<^T(AG/M"(9S[0#*(``$`!+`!``2P`0,%"`$#!0@!`P4(`'*(`
-M``J`@Q@*@(,8"H!C&`J`@Q@*@(,8,!(``.`#``!@@```#P```!B!````````
-M'($````````@@0```````"2!````````*($````````L@0```````#"!````
-M````-($````````X@0```````#R!````````0($``*@``(!$@0````````B8
-M````````+)@```"@```\F`````0@`$R8```\(X02<)@``!\```!TF```@```
-M`'B8```.````6)D``/\```"`F0```````(29`````(`"H)D```````#@F0``
-M`````.29``"JJJJJZ)D``'AD1CSLF0``J@```/"9```,````])D``/\```#X
-MF0``%````"BB``"U"0``/*(``*^)R)-,H@```0```%"B````H```5*(`````
-M``!8H@``@%/'#%RB```!#P\/8*(```$/:5]DH@``$8I!`&BB````````;*(`
-M`&K!,`QPH@``(`B"`'2B``"J?!L`>*(``,XYYQQ\H@``S@$7!0"C``````$8
-M!*,```(F`S`(HP``!CX'2`RC```*3`M6$*,```]@&F04HP``&VY/>!BC``!:
-M?(^&'*,``%N&SXX@HP``#Y=/G22C``"/H<^E**,``!^O7[4LHP``G[G?O3"C
-M```_QW_--*,``+_1_]4XHP```````#RC````````0*,```````!$HP``````
-M`$BC``#___\_3*,``/___S]0HP``____/U2C``#__P,`6*,``!^JJ'E<HP``
-M#T)L!F"C```'(B@/9*,``(468!=HHP``!!&`'VRC```##*`W<*,``(,(Q#]T
-MHP```PC`5WBC``""!MA??*,``(($X'^`HP``NGL\?X2C``#P?S#S!)L```$`
-M```(FP```@````R;```#````$)L```0````4FP``!0```!B;```(````')L`
-M``D````@FP``"@```"2;```+````+)L```T````PFP``$````#2;```1````
-M/)L``!,```!`FP``%````$2;```5````2)L``!@```!,FP``&0```%";```:
-M````5)L``!L```!8FP``'````%R;```=````8)L``"````!HFP``(@```&R;
-M```C````<)L``"0```!TFP``)0```'B;```H````?)L``"D```"`FP``*@``
-M`(2;```K````B)L``"P```"0FP``,````)2;```Q````F)L``#(```"@FP``
-M-````*2;```U````J)L``#4```"LFP``-0```+";```U````M)L``#4```"X
-MFP``-0```+R;```U````P)L``#4```#$FP``-0```,B;```U````S)L``#4`
-M``#0FP``-0```-2;```U````V)L``#4```#<FP``-0```.";```U````Y)L`
-M`#4```#HFP``-0```.R;```U````\)L``#4```#TFP``-0```/B;```0````
-M_)L``!H```````````````":``````````````2:````````0`````B:````
-M````@`````R:````````@0$``!":````````P0$``!2:`````````0```!B:
-M````````00```!R:````````@0```"":````````:`$``"2:````````J`$`
-M`"B:````````Z`$``"R:````````*````#":````````:````#2:````````
-MB0$``#B:````````R0$``#R:````````"0```$":````````20```$2:````
-M````B0```$B:````````D`$``$R:````````T`$``%":````````$````%2:
-M````````4````%B:````````D````%R:````````D0$``&":````````T0$`
-M`&2:````````$0```&B:````````40```&R:````````D0```'":````````
-M>`$``'2:````````N`$``'B:````````^`$``'R:````````.````(":````
-M````>````(2:````````F0$``(B:````````V0$``(R:````````&0```)":
-M````````60```)2:````````F0```)B:````````V0```)R:````````^0``
-M`*":````````^0```*2:````````^0```*B:````````^0```*R:````````
-M^0```+":````````^0```+2:````````^0```+B:````````^0```+R:````
-M````^0```,":````````^0```,2:````````^0```,B:````````^0```,R:
-M````````^0```-":````````^0```-2:````````^0```-B:````````^0``
-M`-R:````````^0```.":````````^0```.2:````````^0```.B:````````
-M^0```.R:````````^0```/":````````^0```/2:````````^0```/B:````
-M````^0```/R:````````^0```-28```@``````````````#0F```"!0``@@4
-M`0((%``""!0``@@4`0(``````````-R8``#`(*``P""@`,`@X`#`(.``P"#@
-M`````````````````````````````````)R8``````#P````\````/````#P
-M````\)R8`````````````````````````````)R8```````#`````P````,`
-M```#`````YR8`````````````````````````````)R8````````````````
-M`````````````)R8`````````````````````````````)R8````````````
-M`````````````````)R8`````````````````````````````)R8`````$!`
-M``!`0```0$```$!```!`0)R8``````5E```%90``!64```5E```%99R8````
-M`````````````````````````)R8`````````````````````````````)R8
-M`````$(```!"````0@```$(```!"`)R8`````+4```"U````M0```+4```"U
-M`)R8``````,````#`````P````,````#`)R8`````/<```#W````]P```/<`
-M``#W`)R8`````)T```"=````G0```)T```"=`)R8`````"(````B````(@``
-M`"(````B`)R8`````"($```B!```(@0``"($```B!)R8```8`",`&``C`!@`
-M(P`8`",`&``C`)R8`````"@````H`&``*`!@`"@`8``H`)R8``#``%``P`!0
-M`,,`4`##`%``PP!0`)R8``!_``0`?P`$`'\`!`!_``0`?P`$`)R8``!8!```
-M6`0``%@$``!8!```6`0``)R8`````````````````````````````)R8````
-MP````,````#`````P````,```-B8```P`D``,`)``#`"0``P`D``,`)`````
-M`````````````````````````````)R8````9````&0```!D````9````&0`
-M`)R8````"`````@````(````"`````@``,R8```.````#@````X````.````
-M#@``````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```P````%0```!4````5````%0```!4````<@```IY.-$L\3B`F5$^`$JQ/@
-M$L\3B`DHF````0`""@$``@H``0(%`0`""@$``@HTF```#@X```X.```.#@``
-M#@X```X.```XF```!P````<````+````"P````L```!(F```8?H8`&'Z&`!C
-M&AH`8QH:`&,:&@!0F```X+28#."TF`S:L)@,VK"8#-JPF`Q8F```+@W(?BX-
-MR'XN#<A^+@W(?BX-R'Y<F```7F`Y,5Y@.3%>8#DQ7F`Y,5Y@.3%LF```@;`,
-M!8&P#`6!L`P%@;`,!8&P#`44F0``T`<``-`'``!,!```F`@``-`'``!$F0``
-M`!"X]P`0N/<`#;CW`!"X]P`0N/<$H@`````````````````````````````(
-MH@``B&>^UHAGOM:(9S[0B&<^T(AG/M`,H@``X,$N`.#!+@`@P2H`(,$J`"#!
-M*@`<H@``"H"#&`J`@Q@*@&,8"H"#&`J`@Q@`HP`````!&````1@```$8```!
-M&````1@$HP```B8#,`(F`S`")@,P`B8#,`(F`S`(HP``!CX'2`8^!T@&/@=(
-M!CX'2`8^!T@,HP``"DP+5@I,"U8*3`M6"DP+5@I,"U80HP``#V`:9`]@&F0/
-M8!ID#V`:9`]@&F04HP``&VY/>!MN3W@;;D]X&VY/>!MN3W@8HP``6GR/AEI\
-MCX9:?(^&6GR/AEI\CX8<HP``6X;/D%N&SY!;AL^.6X;/CEN&SXX@HP``#Y=/
-MG0^73YT/ET^;#Y=/FP^73YLDHP``CZ//IX^CSZ>/G\^CCY_/HX^?SZ,HHP``
-M'Z]?M1^O7[4?KU^S'Z]?LQ^O7[,LHP``G[G?O9^YW[V?N=^[G[G?NY^YW[LP
-MHP``/\5_RS_%?\L_QW_+/\=_RS_'?\LTHP``O]'_U;_1_]6_T?_3O]'_T[_1
-M_],`````````````````````,!(``.`#``!H0```$````&"````/````G(``
-M``````"@@````````!B!````````'($````````@@0```````"2!````````
-M*($````````L@0```````#"!````````-($````````X@0```````#R!````
-M````0($``/D#`(!$@0````````B8````````+)@```"@```\F`````0@`$R8
-M```\(X02<)@``!\```!TF```@````'B8```.````6)D``/\?"`"`F0``````
-M`(29`````(`"H)D```````#@F0```````.29``"JJJJJZ)D``'AD1CSLF0``
-MJ@```/"9```,````])D``/\```#XF0``%````"BB``"U"0``/*(``*^)R)-,
-MH@```0```%"B````H```5*(```````!8H@``@%/'#%RB```!#P\/8*(```$/
-M:5]DH@``$8I!`&BB````````;*(``&K!,`QPH@``(`B"`'2B``"J?!L(>*(`
-M`,XYYQQ\H@``S@$7!3BC````````/*,```````!`HP```````$2C````````
-M2*,``/___S],HP``____/U"C``#___\_5*,``/__`P!8HP``'ZJH>5RC```/
-M0FP&8*,```<B*`]DHP``A19@%VBC```$$8`?;*,```,,H#=PHP``@PC$/W2C
-M```#",!7>*,``((&V%]\HP``@@3@?X"C``"Z>SQ_A*,``/!_,/,$FP```0``
-M``B;```"````#)L```,````0FP``!````!2;```%````&)L```@````<FP``
-M"0```"";```*````))L```L````LFP``#0```#";```0````-)L``!$````\
-MFP``$P```$";```4````1)L``!4```!(FP``&````$R;```9````4)L``!H`
-M``!4FP``&P```%B;```<````7)L``!T```!@FP``(````&B;```B````;)L`
-M`",```!PFP``)````'2;```E````>)L``"@```!\FP``*0```(";```J````
-MA)L``"L```"(FP``+````)";```P````E)L``#$```"8FP``,@```*";```T
-M````I)L``#4```"HFP``-0```*R;```U````L)L``#4```"TFP``-0```+B;
-M```U````O)L``#4```#`FP``-0```,2;```U````R)L``#4```#,FP``-0``
-M`-";```U````U)L``#4```#8FP``-0```-R;```U````X)L``#4```#DFP``
-M-0```.B;```U````[)L``#4```#PFP``-0```/2;```U````^)L``!````#\
-MFP``&@````":``````````````2:``!`````0`````B:``"`````@`````R:
-M``"A`0``80$``!":``#A`0``H0$``!2:```A````X0$``!B:``!A````(0``
-M`!R:``"(`0``80```"":``#(`0``B`$``"2:```(````R`$``"B:``!(````
-M"````"R:``"(````2````#":``"I`0``B````#2:``#I`0``:0$``#B:```I
-M````J0$``#R:``!I````Z0$``$":``#0`0``*0```$2:```0````:0```$B:
-M``!0````D`$``$R:``"0````T`$``%":``"Q`0``$````%2:``#Q`0``4```
-M`%B:```Q````D````%R:``!Q````<0$``&":``"X`0``L0$``&2:``#X`0``
-M\0$``&B:```X````,0```&R:``!X````<0```'":``"9`0``F`$``'2:``#9
-M`0``V`$``'B:```9````&````'R:``!9````6````(":``"9````F````(2:
-M``#9````>0$``(B:``#Y````N0$``(R:``#Y````^0$``)":``#Y````.0``
-M`)2:``#Y````>0```)B:``#Y````N0```)R:``#Y````^0```*":``#Y````
-M^0```*2:``#Y````^0```*B:``#Y````^0```*R:``#Y````^0```+":``#Y
-M````^0```+2:``#Y````^0```+B:``#Y````^0```+R:``#Y````^0```,":
-M``#Y````^0```,2:``#Y````^0```,B:``#Y````^0```,R:``#Y````^0``
-M`-":``#Y````^0```-2:``#Y````^0```-B:``#Y````^0```-R:``#Y````
-M^0```.":``#Y````^0```.2:``#Y````^0```.B:``#Y````^0```.R:``#Y
-M````^0```/":``#Y````^0```/2:``#Y````^0```/B:``#Y````^0```/R:
-M``#Y````^0```-28```@``````````````#0F```"`````@````(````"```
-M``@``````````````-R8``#``*``P`"@`,``X`#``.``P`#@````````````
-M`````````````````````)R8```````S````,P```#,````S````,YR8````
-M```!`````0````$````!`````9R8`````````````````````````````)R8
-M`````````````````````````````)R8````````````````````````````
-M`)R8```````?````'P```!\````?````'YR8````````````````````````
-M`````)R8`````+@```"X````N````+@```"X`)R8`````+<```"W````MP``
-M`+<```"W`)R8`````(0```"$````A````(0```"$`)R8`````)@```"8````
-MF````)@```"8`)R8`````,````#`````P````,````#``)R8`````/\```#_
-M````_P```/\```#_`)R8`````/\```#_````_P```/\```#_`)R8`````/\`
-M``#_````_P```/\```#_`)R8`````/\```#_````_P```/\```#_`)R8````
-M`-<```#7````UP```-<```#7`)R8`````&$```!A````80```&$```!A`)R8
-M`````/X```#^````_@```/X```#^`)R8`````-X```#>````W@```-X```#>
-M`)R8`````'\```!_````?P```'\```!_`)R8`````#T$```]!```/00``#T$
-M```]!)R8`````'<```!W````=P```'<```!W`)R8`````$0```!$````1```
-M`$0```!$`)R8`````)@```"8````F````)@```"8`)R8``"``!``@``0`(``
-M$`"``!``@``0`)R8```TP`4`-,`%`#3`!0`TP`4`-,`%`)R8``#P`#$`\``Q
-M`/``,0#P`#$`\``Q`)R8```?`0P`'P$,`!\!#``?`0P`'P$,`)R8``!``%$`
-M0`!1`$``40!``%$`0`!1`)R8``#:`%``V@!0`-H`4`#:`%``V@!0`)R8````
-M`````````````````````````)R8``!$0```1$```$1```!$0```1$```)R8
-M`````````````````````````````)R8``#`8```P&```,!@``#`8```P&``
-M`)R8````+````"P````V````-@```"P``,B8```#!````P0```,$```#!```
-M`P0`````````````G)@```!D````9````&0```!D````9```G)@````(````
-M"`````@````(````"```S)@```X````.````#@````X````.````````````
-M````````````````````````````````````````````````````````````
-M`````````````````$%2-3(Q,`!!4C4R,3$`05(U,C$R`%)&-3$Q,0!21C4Q
-M,3(`4D8R-#$S`%)&-30Q,P!!=&AE<F]S(#(S,3,@5VE3;T,`071H97)O<R`U
-M-#(T+S(T,C0`071H97)O<R`R,S$W(%=I4V]#`$%T:&5R;W,@-3(Q,B`H1E!'
-M02D`071H97)O<R`U,C$Q("A&4$=!*0!!=&AE<F]S(#4R,3``071H97)O<R`U
-M,C$Q`$%T:&5R;W,@-3,Q,B!7:5-O0P!!=&AE<F]S(#(S,34@5VE3;T,`071H
-M97)O<R`U,C$R````````````````````````````````````,"XY+C(P+C,`
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````````````````#_
-M`?\!`````````````/________]_```````````#`)@!F0$`````````````
-M_________W\```````````<`F`$P"P````````````#_________?P``````
-M````"`"8`3`,`````````````/________]_```````````@`"`!$`H`````
-M````````_________W\``````````"$`(`&9`0````````````#_________
-M?P``````````(@`@`3`,`````````````/________]_```````````Z`&`!
-M$`H`````````````_________W\``````````#L`8`&9`0````````````#_
-M________?P``````````$@!E`1`*```#`````````/________]_````````
-M```W`#`!F0$```,`````````_________W\``````````#4`,`*9`0```P``
-M``````#_________?P``````````-@`P`YD!```#`````````/________]_
-M```````````P`#`$F0$```,`````````_________W\``````````#D`,`69
-M`0```P````````#_________?P``````````-``P!ID!```#`````````/__
-M______]_```````````R`#`#F0$```,`````````_________W\`````````
-M`#$`,`.9`0````````````#_________?P``````````$0`0`9D!````````
-M`````/________]_```````````0`!`!$`H`````````````_________W\`
-M`````````%(`4`&9`0````````````#_________?P``````````10!0`ID!
-M`````````````/________]_``````````!'`%`#F0$`````````````____
-M_____W\``````````$(`4`29`0````````````#_________?P``````````
-M6`!0!9D!`````````````/________]_``````````!;`%`&F0$`````````
-M````_________W\``````````%T`4`B9`0````````````#_________?P``
-M````````7@!0"9D!`````````````/________]_``````````!0`%`#$`H`
-M````````````_________W\``````````%4`4`$P#`````````````#_____
-M____?P``````````5@!0`C`,`````````````/________]_``````````!)
-M`%`"4`T`````````````_________W\``````````$``0`%`"@``1@````0`
-M```H`````````(@!````````00!``4`*``!'````!````&@`````````B0$`
-M``````!(`$`!$`H``$8````$````"`````````"*`0```````$H`0`%`"@``
-M1@````0````(&````````(P!````````2P!``4`*``!&````!`````A@````
-M````C0$```````!,`$`!4`H``$8````$````"`````````"/`0```````$,`
-M0`)`"@``1P````0```!P`````````(L!````````\`!``T`*``!&````!```
-M`"````````````````````"``$`#0`H``$<````$````8`````````"G#P``
-M`````/$`0`-`"@``1@````0`````&```````````````````@0!``T`*``!&
-M````!`````!@````````J`\```````""`$`#4`H``$8````$````````````
-M``"I#P```````/(`0`,0"@``1@````0`````````````````````````@P!`
-M!$`*``!'````!````&"`````````J@\```````#T`$`$0`H``$8````$````
-M`)@``````````````````(0`0`1`"@``1@````0`````X````````*L/````
-M````A0!`!%`*``!&````!`````"`````````K`\```````#U`$`$$`H``$8`
-M```$`````(```````````````````(8`0`5`"@``1P````0```!@@```````
-M`*T/````````AP!`!4`*``!&````!`````#@````````K@\```````"(`$`%
-M4`H``$8````$`````(````````"O#P```````(D`0`9`"@``1P````0```!H
-M`````````+`/````````B@!`!D`*``!&````!`````A@````````L0\`````
-M``"+`$`&4`H``$8````$````"`````````"R#P```````(P`0`=`"@``1P``
-M``0```!H@````````+,/````````C0!`!T`*``!&````!`````C@````````
-MM`\```````".`$`'4`H``$8````$````"(````````"U#P```````(\`0`A`
-M"@``1P````0```!H@````````+8/````````D`!`"$`*``!&````!`````C@
-M````````MP\```````"1`$`(4`H``$8````$````"(````````"X#P``````
-M`/8`0`E`"@``1P````0```!@@```````````````````]P!`"T`*``!'````
-M!````&"```````````````````!@`&``8```````````````_________W\`
-M`````````&$`80!A`````P````````#_________?P``````````8@!B`&(`
-M```"`````````/________]_``````````!C`&,`8P``````````````____
-M_____W\``````````&0`9`!D`````P````````#_________?P``````````
-M90!E`&4````#`````````/________]_``````````!F`&8`9@``````````
-M````_________W\``````````&<`9P!G``````````````#_________?P``
-M````````:`!H`&@``````````````/________]_``````````!I`&D`:0``
-M``,`````````_________W\``````````&H`:@!J`````P````````#_____
-M____?P``````````90````$```#_____@````/____\`````2E```+0/````
-M````:@````$```#_____@````/____\`````2E```+0/````````````````
-M````````````````````````_P$```$````!`````0```%@;`````!```0``
-M``$````!````6!L```@``P`!``````````$```!8&P``#``#``$`````````
-M`0```%@;```@`$<`````````````````6!L``#,`,``!``````````$```!8
-M&P``)``A``$````!`````0```%@;```H`#<``0`````````!````6!L``!\`
-M,``!`````0````$```!8&P``,`!;``$``````````0```%@;``!P``,``0``
-M```````!````6!L``#@`-P`!``````````$```!8&P``5`!5``$````!````
-M`0```%@;``!$`%4``0````$````!````6!L``$P`.P`!``````````````!8
-M&P``8`!2``$````!`````0```%@;``!D`#0``0`````````!````6!L``'P`
-M(``!`````0````$```!8&P``F`!;``$````!`````0```%@;``"<`%(``0``
-M``$````!````6!L``*H`$``!``````````$```!8&P``O``#``$`````````
-M`0```%@;``"_`#8``0`````````!````6!L``,0`-P`!`````0````$```!8
-M&P``RP`W``$``````````0```%@;``#0`#<``0`````````!````6!L``-8`
-M$``!`````0````$```!8&P``V@`#`````````````````%@;```R`S8``0``
-M```````!````6!L``-X``P`!``````````$```!8&P``Z0`W``$`````````
-M`0```%@;``#V`#<``0`````````!````6!L``/H`-P`!``````````$```!8
-M&P``_P`V``$``````````0```%@;```,`3```0````$````!````6!L``!0!
-M-P`!``````````$```!8&P``+`$W``$``````````0```%@;``!``1```0``
-M``$````!````6!L``%0!`P`!``````````$```!8&P``6`$A``$````!````
-M`0```%@;``!<`3<``0`````````!````6!L``&`!-P`!``````````$```!8
-M&P``9`%;``$``````````0```%@;``!H`5(``0`````````!````6!L``&P!
-M4@`!`````0````$```!8&P``=`$W``$``````````0```%@;``!X`0,``0``
-M```````!````6!L``'P!-P`!``````````$```!8&P``B`%```$`````````
-M`````%@;``")`4$``0``````````````6!L``(H!2``!``````````````!8
-M&P``BP%#``$``````````````%@;``",`4H``0``````````````6!L``(T!
-M2P`!``````````````!8&P``CP%,``$``````````````%@;``"G#X```0``
-M````````````6!L``*@/@0`!``````````````!8&P``J0^"``$`````````
-M`````%@;``"J#X,``0``````````````6!L``*L/A``!``````````````!8
-M&P``K`^%``$``````````````%@;``"M#X8``0``````````````6!L``*X/
-MAP`!``````````````!8&P``KP^(``$``````````````%@;``"P#XD``0``
-M````````````6!L``+$/B@`!``````````````!8&P``L@^+``$`````````
-M`````%@;``"S#XP``0``````````````6!L``+0/C0`!``````````````!8
-M&P``M0^.``$``````````````%@;``"V#X\``0``````````````6!L``+</
-MD``!``````````````!8&P``N`^1``$``````````````%@;``"0`4(``0``
-M```````!````6!L``(X!`P`!``````````$```!8&P``F`%%``$````!````
-M`0```%@;``":`44``0``````````````6!L``)L!10`!``````````````!8
-M&P``G`%>``$``````````````%@;``">`0,``0`````````!````6!L``*P!
-M-P`!``````````$```!8&P``I@$#``$``````````0```%@;``"V`3<``0``
-M```````!````6!L``+@!-P`!``````````$```!8&P``N@$W``$`````````
-M`0```%@;``"^`2$``0````$````!````6!L``"<#`P`!``````````$```!8
-M&P``R@%=``$``````````````%@;``#6`3<``0`````````!````6!L``.0!
-M$``!`````0````$```!8&P``[`$P``$````!`````0```%@;``#X`0,``0``
-M```````!````6!L``!`"-P`!``````````$```!8&P``*@(B``$`````````
-M`0```%@;``!"`C<``0`````````!````6!L````"6P`!``````````$```!8
-M&P``2@(#``$``````````0```%@;``!/`A```0````$````!````6!L``%P"
-M4@`!``````````$```!8&P``8`([``$````!`````0```%@;``!H`C<``0``
-M```````!````6!L``&P"-P`!``````````$```!8&P``=@(0``$````!````
-M`0```%@;``!Z`@,``0`````````!````6!L``(("`P`!``````````$```!8
-M&P``@P(#``$``````````0```%@;``"J`B$``0`````````!````6!L``+X"
-M6P`!`````0````$```!8&P``OP(W``$``````````0```%@;``#!`C<``0``
-M```````!````6!L``,8".P`!``````````$```!8&P``U`(W``$`````````
-M`0```%@;``#P`C<``0`````````!````6!L``/0"-P`!``````````$```!8
-M&P``^`(#``$``````````0```%@;``">`%```0````$````!````6!L``/P"
-M`P`!``````````$```!8&P``#`,P``$``````````0```%@;```4`S8``0``
-M```````!````6!L``!@#-@`!``````````$```!8&P``)`,#``$`````````
-M`0```%@;```0`P,``0`````````!````6!L``#H#-P`!``````````$```!8
-M&P``2`,0``$````!`````0```,$6``!*`Q(``0````$````!````6!L``%H#
-M$0`!``````````$```!8&P``7`,Z``$````!`````0```%@;``!>`U8``0``
-M```````!````6!L``,`"`P`!``````````$```!8&P``=P,#``$`````````
-M`0```%@;``#,`@,``0`````````!````6!L````````S$ST3%P`*!0``````
-M````$``````````0`````````$<341,7``H%```````````0`````````!``
-M````````.!-T$Q<`%!0``````````!``````````!P````````!.$WL3&P8%
-M!0```````````0```````````````````%$3>1,>!@H%```````````!````
-M````````````````5A-T$R$&%`4```````````$```````````````````"K
-M$[`3%P`*!0``````````$``````````,`````````+`3V!,7`!04````````
-M```0``````````(`````````OQ._$Q<`"@4``````````!``````````#```
-M````````%'@4!084%````````````````````````````````#(4;A07`!04
-M```````````8``````````$`````````,A1N%!0`%!0``````````!@`````
-M`````0`````````\%'@4#P`4%```````````!0```````````````````#P4
-M>!01!A04```````````!``````````$`````````/!1X%!(`%!0`````````
-M``4````````````````````\%'@4%``4%```````````!0``````````````
-M`````#P4>!07`!04```````````%````````````````````/!1X%!<&%!0`
-M``````````$````````````````````\%,@4%`84%`(`````````!```````
-M`````````````'@4H!07`!04`0`````````%````````````````````C!2@
-M%!<`%!0#``````````4```````````````````",%,@4$@`4%`,`````````
-M!0```````````````````(P4R!04`!04!P`````````%@```````````````
-M````C!3(%!0&%!0#``````````$``````````@````````",%,@4%P84%`,`
-M`````````0`````````"`````````(P4R!07!A04`P`````````!````````
-M````````````C!3(%!X`%!0```````````````````````````````",%$06
-M!084%`,``````````````````````````````*`4R!01!A04`P`````````!
-M````````````````````?!7T%1X&%!0"``````````0`````````````````
-M``!\%406%`84%`,``````````0`````````$`````````'P51!8;`!04`P``
-M```````%````````````````````?!5$%AX`%!0#``````````4`````````
-M``````````!\%406%P`4%`<``````````8```````````````````'$6K187
-M`!04````````````````````````````````<1:M%AX&%!0`````````````
-M``````````````````!Q%JT6'@84%`(`````````!```````````````````
-M`'$6P18%!A04````````````````````````````````<1;!%A$`%!0`````
-M``````````````````````````!Q%L$6%``4%```````````````````````
-M`````````'$6P18>`!04````````````````````````````````<1;!%AX&
-M%!0``````````````````````P````````!Q%L$6'@84%```````````````
-M`````````````````#@3=!,>`!04````````````!```````````````````
-ML!/8$QX`%!0````````````$```````````````````R%&X4'@`4%`,`````
-M``````0``````````````````#P4>!0>`!04`P``````````!```````````
-M````````C!3(%!X`%!0#```````````$``````````````````!Q%L$6'@`4
-M%`````````````0``````````````````'P51!8>`!04`P``````````!```
-M````````````````C!3(%!X`%!0````````````````````````````````\
-M%'@4'@`4%````````````````````````````````,$6P18>`!04````````
-M````!```````````````````"A1:%`4&*"@`````````````````````````
-M``````""%-(4!08H*`$``````````````````````````````/H4<A4%!B@H
-M````````````````````````````````FA42%@4&*"@!````````````````
-M```````````````>%$84!08H*````````````````````````````````&X4
-MOA0%!B@H`0``````````````````````````````YA1>%04&*"@`````````
-M``````````````````````"&%286!08H*`$`````````````````````````
-M`````%`4>!01!B@H````````````````````````````````4!1X%!<&*"@`
-M``````````````````````````````!:%%H4$08H*```````````````````
-M`````````````%H46A07`"@H````````````````````````````````H!2@
-M%!<&*"@!``````````(```````````````````"@%*`4%`8H*`$`````````
-M`@```````````````````((4@A01`"@H`0`````````"````````````````
-M````JA2J%!0`*"@!``````````(```````````````````""%*H4%``H*`$`
-M`````````@```````````````````((4JA07!B@H`0`````````"````````
-M````````````I!4<%A0&*"@!``````````(```````````````````"`%J@6
-M%``H*````````````````````````````````(`6J!8>!B@H````````````
-M````````````````````A1:M%AX&*"@`````````````````````````````
-M``!:%((4#P`H*`,```````````0``````````````````*H4JA02`"@H`P``
-M````````!```````````````````I!4<%A0`*"@#```````````$````````
-M``````````"`%J@6%``H*`````````````0```````````````````@)1`D%
-M!A0%````````````````````````````````"`E$"10`%`4`````````````
-M``````````````````!L":@)!084!0``````````````````````````````
-M`&P)J`D4`!0%```````````@````````````````````;`FH"1X`%`4`````
-M``````````````````````````!L"9X)&P84!0``````````````````````
-M`````````&P)G@D4`!0%```````````@````````````````````@`F*"10`
-M%`4```````````````````````````````"9":@)%``4!0``````````````
-M`````````````````*,)J`D4`!0%```````````@(```````````````````
-MM`FT"04&%`4```````````````````````````````"T";0)%``4!0``````
-M````("@``````````````````-`)K`H%!A0%````````````````````````
-M````````"`E$"10`%`4```````````````````````````````!L"6P)%``4
-M!0```````````````````````````````'$)@`D4`!0%````````````````
-M````````````````A0F*"10`%`4```````````````````````````````"/
-M"9D)%``4!0```````````````````````````````)X)G@D4`!0%````````
-M````````````````````````HPFC"10`%`4````````````$``````"`````
-M``````"C":,)%``4!0```````````````````(```````````*@)J`D4`!0%
-M````````````!```````@```````````J`FH"10`%`4`````````````````
-M``"```````````"T";0)%``4!0````````````0``````(```````````+0)
-MM`D4`!0%````````````````````@```````````"`E$"04&%`4`````````
-M```````````````````````("40)%``4!0``````````````````````````
-M`````&P)J`D%!A0%````````````````````````````````;`FH"10`%`4`
-M`````````$````````````````````!L":@)'@`4!0``````````````````
-M`````````````&P)G@D;!A0%````````````````````````````````;`F>
-M"10`%`4``````````$````````````````````"`"8H)%``4!0``````````
-M`````````````````````)D)J`D4`!0%````````````````````````````
-M````T`FL"@4&%`4```````````````````````````````"C":@)%``4!0``
-M````````("````````````````````@)1`D4`!0%````````````````````
-M````````````;`EL"10`%`4```````````````````````````````!Q"8`)
-M%``4!0```````````````````````````````(4)B@D4`!0%````````````
-M````````````````````CPF9"10`%`4`````````````````````````````
-M``">"9X)%``4!0```````````````````````````````*,)HPD4`!0%````
-M````````!```````@```````````HPFC"10`%`4```````````````````"`
-M``````````"H":@)%``4!0````````````0``````(```````````*@)J`D4
-M`!0%````````````````````@```````````"`E$"04&*"@`````````````
-M``````````````````"%"84)!08H*```````````````````````````````
-M`(4)A0D4!B@H````````````````````````````````A0F%"1(&*"@`````
-M```````$``````````````````#0":P*!08H*```````````````````````
-M`````````/\!$````````0````````````````````````````````(`""``
-M`````````````/\`````````````````````$20`````````````````!10`
-M``````````````````4"```````````````````3````````````````````
-M4`$0``````````````````````````````````````````````$`````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````````!0`A``````
-M```````````````````````````````````````$````````````````````
-M````````````````````````````````````````````````````````````
-M`````````````````````````````````````````%`#$```````````````
-M````````````````````````````$`@`````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````4`00````````````````````````
-M````````````````@```@```````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````!0!1``````````````````````````````````
-M``````````!`````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M`````````````%`&,````````@`````````#`````````````````````(!`
-M`(`````````````````("0``````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````4`@P`````````````````````````````P`````````````$``$`````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````````````!0"3``
-M``````(`````````!``````````#````````````!"`0````````````````
-M````````````````````````````````````````````````````````````
-M`````````````````````````````````````````````#`!,````````@``
-M```````$``````````,```````````!`@```"```````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````,`(P```````"``````````0`
-M`````````P``````````0```````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````````````P`S````````(`````````!``````````#
-M````````````0`````@`````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M`````````````````#`$,````````@`````````$``````````,`````````
-M`$`@````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````,`4P```````"``````````0``````````P``````````$```````
-M````````````````````````````````````````````````````````````
-M```````````````````````````````````````````````````````````P
-M!C````````(`````````!``````````#````````````$0`!````````````
-M````````````````````````````````````````````````````````````
-M`````````````````````````````````````````````````!`!$```````
-M`````````````````````````````````"```0`"```````````````$$@``
-M````````````````$2``````````````````````````````````````````
-M````````````````````````````````````````(`$0````````````````
-M``````````````````````````("``0`````````````````````````````
-M```````2(```````````````````````````````````````````````````
-M``````````````````````````````!@`1````````$``````````P``````
-M```````````````@@$```@``````````````Q!```````````````````"$$
-M````````````````````````````````````````````````````````````
-M`````````````````````&4!$````````0`````````#````````````````
-M````.```````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````0`%```````````````````@``````````@``````````!```
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``!``D``````````````````$``````````"`````````,<%````````````
-M````````````````````````````````````````````````````````````
-M`````````````````````````````````````````````````````$`#0```
-M````````````````@`````````(``````````(``````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````0`1````````$````
-M``````"``````````@``````````@$``````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````!`!4````````0``````````(``
-M```````"``````````"`0``"````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M`````````````````````````$`&0``````````````````(``````````(`
-M`````````(@`````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````0`=````````$``````````B``````````@``````````
-MA$``````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````!`"$````````0`````````"(`````````"``````````"$0``"````
-M````````````````````````````````````````````````````````````
-M`````````````````````````````````````````````````````````$`)
-M0```````````````````@`````````(`````````QX$`````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````0`M````````$
-M``````````"``````````@````````#'@4``````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````!0#?\`````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````H````````````````````*````````````
-M`````````````````````````````#`*_P````````````````"`````````
-M``,`````````````````````````````````````````````````````````
-M``````````````````$````````````````````!```````````````````$
-M````````````````````,`LP```````````````````!`````````P``````
-M````````````````````````````````````````````````````````````
-M``````"`````````````````````@`````````````````````0`````````
-M```````````P##````````````````````(````````#````````````````
-M`````````````````````````````````````````````````````````!``
-M```````````````````0````````````````````!```````````````````
-M`!`*$```````````````````````````````````````````````````````
-M````````````````````````````````````````````````(```````````
-M`````````"`````````````````````$````````````````````0`I`````
-M`````````````&!X`````````@``````````````````````````````````
-M``````````````````````````````````````!`"@``````````````````
-M0`0```````````````````0```````````````````!0"D``````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````@````````````````````(````````
-M````````````!````````````````````)D!,```````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````"`````````````````````@`````````````````
-M```$````````````````````8`#_```````#```````````$````````"```
-M`````````````.`#``````````````#``@``````````````````````````
-M````````````P*\``````````````````/`+``````````````````@`````
-M``````````````!F`/\```````,```````````0````````(````````````
-M````X`,``````````````,`"````````````````````````````````````
-M``#`!P``````````````````\`$`````````````````"```````````````
-M`````&<`_P```````P``````````!`````````@```````````````#@`P``
-M````````````P`(``````````````````````````````````````,`O````
-M``````````````#P"P`````````````````(````````````````````:`#_
-M```````#```````````$````````"````````````````.`#````````````
-M``#``@``````````````````````````````````````P%<`````````````
-M`````/`5``````````````````@```````````````````!A`/\```````,`
-M``````````0````````0````````````````X`,`````````````````````
-M``````````````````````````````````#`KP``````````````````\`L`
-M````````````````"````````````````````&(`_P```````P``````````
-M!````````!````````````````#@`P``````````````P`(`````````````
-M`````````````````````````,"O``````````````````#P"P``````````
-M```````(````````````````````8P#_```````#```````````$````````
-M"````````````````.`!``````````````#``@``````````````````````
-M````````````````P"\``````````````````/`+``````````````````@`
-M``````````````````!D`/\```````,```````````0````````0````````
-M```````(`!P``````````````,`"````````````````````````````````
-M``````#`!P``````````````````\`$`````````````````"```````````
-M`````````&4`_P```````P``````````!````````!````````````````"$
-M"````````````````````````````````````````````````````````,!7
-M``````````````````#P%0`````````````````(````````````````````
-M:0#_```````#```````````$````````$````````````````,`#````````
-M``````#``@``````````````````````````````````````P`<`````````
-M`````````/`!``````````````````@```````````````````!J`/\`````
-M``,```````````0````````0````````````````P`,`````````````````
-M``````````````````````````````````````#`+P``````````````````
-M\`L`````````````````"````````````````````)@!_P``````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````0`#P`/,`B('P`/,`00"``(,`B8&`
-M`(,`2`#R`/4`BH'R`/4`0P#V`/<`BX'V`/<`2@#Q`/0`C('Q`/0`2P"!`(0`
-MC8&!`(0`3`""`(4`CX&"`(4`````````````````B`'P`/,`B0&``(,`B@'R
-M`/4`BP'V`/<`C`'Q`/0`C0&!`(0`CP&"`(4`````````````````````````
-M``````@```````````````````````````````````````````````$"<!<+
-M`(P```````$"*",/`!(```````$"X"X*`)@"``````$"4$8.`"0"``````$"
-MP%T)`+`$``````$"H(P-`$@$``````$"@+L(`&`$``````$"\-(,`&P$````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```(```````````````````````````````````````````````!`W`7"P",
-M```````!`R@C#P`2```````!`^`N"@"8`@`````!`U!&#@`D`@`````!`\!=
-M"0"P!``````!`Z",#0!(!``````!`X"["`!@!``````!`_#2#`!L!```````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M"````````````````````````````````````````````````0)P%PL`C```
-M`````0(H(P\`$@```````0+@+@H`F`(``````0)01@X`)`(``````0+`70D`
-ML`0``````0*@C`T`2`0``````0*`NP@`8`0``````0+PT@P`;`0`````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````````````````@`
-M``````````````````````````````````````````````$#<!<+`(P`````
-M``$#*",/`!(```````$#X"X*`)@"``````$#4$8.`"0"``````$#P%T)`+`$
-M``````$#H(P-`$@$``````$#@+L(`&`$``````$#\-(,`&P$````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````````````````````````````````````````$````
-M```````````````````````````````````````````!`.@#"P""```````!
-M`-`'"@2$`0`````!`'P5"02+`0`````!`/@J"`26`0``````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````!*(`````
-M````````"*(``$9&/E!&1CY0#*(``&Q!@&1L08!D$*(```.@F0$#H)D!%*(`
-M`!#63`00UDP$&*(``$``@!-``(`3'*(``&``X!M@`.`;(*(```J`4PP*@%,,
-M)*(``#O?%``[WQ0`**(``+4!``"U`0``+*(``"`````@````G)@`````````
-M````G)@`````````````G)@`````````````G)@`````````````G)@`````
-M````````G)@`````````````G)@`````````````G)@`````````````G)@`
-M````````````G)@`````````````G)@`````````````G)@`````.````#@`
-MG)@`````````````G)@`````````````G)@`````````````G)@``/D`!`#Y
-M``0`U)@````````$`````````````````````````)R8`````````````)R8
-M`````````````)R8`````````````)R8`````````````)R8````````````
-M`)R8```````0````$)R8```````$````!)R8`````````````)R8````````
-M`````)R8`````````````)R8````````````"IR8``"``#@`@``X`IR8```&
-M``(`!@```)R8``"2````D@```)R8``"@````H````)R8```'``0`!P`$`-28
-M```:````&@```)R8``!(````2````)R8```0````$````)R8```(````"```
-M`)R8```/````#P```)R8``#R````8@```)R8``!/D```3)```)R8``!:$@``
-MFA(``,R8```.````#P``````````````````````````````"```````````
-M`````````````````````````````````````0)P%PL`C````````0(H(P\`
-M$@```````0+@+@H`F`(``````0)01@X`)`(``````0+`70D`L`0``````0*@
-MC`T`2`0``````0*`NP@`8`0``````0+PT@P`;`0`````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````@`````````````
-M``````````````````````````````````$"N`L+`(8```````$"E!$/``D`
-M``````$"<!<*`(P"``````$"*",.`!("``````$"X"X)`)@$``````$"4$8-
-M`"0$``````$"P%T(`#`$``````$">&D,`#8$````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````````````````````````````(````````````````
-M```````````````````````````````!`MP%"P"#```````!`LH(#P`$````
-M```!`K@+"@"&`@`````!`I01#@`)`@`````!`G`7"0",!``````!`B@C#0`2
-M!``````!`N`N"``8!``````!`KPT#``;!```````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````!P``````````````````
-M`````````````````````````````0-P%PL`C````````0/@+@H`F`(`````
-M`0-01@X`)`(``````0/`70D`L`,``````0.@C`T`2`,``````0.`NP@`8`,`
-M`````0/PT@P`;`,`````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````@`````````````````````
-M``````````````````````````$#<!<+`(P```````$#*",/`!(```````$#
-MX"X*`)@"``````$#4$8.`"0"``````$#P%T)`+`$``````$#H(P-`$@$````
-M``$#@+L(`&`$``````$#\-(,`&P$````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````````````````````$````````````````````````
-M```````````````````````!`.@#&P""```````!`-`'&@2$`0`````!`'P5
-M&02+`0`````!`/@J&`26`0``````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````#```````````````````````````
-M`````````````````````0#H`QL`@@```````0#0!QH$A`$``````0!\%1D$
-MBP(``````0#X*A@$E@,```````)P%PL`#`0```````(H(P\`$@0``````0+@
-M+@H`&`8``````0)01@X`)`8``````0+`70D`,`@``````0*@C`T`2`@`````
-M`0*`NP@`8`@``````0+PT@P`;`@`````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````T`````````````````````````````
-M``````````````````$$^@`#`($`9`)D`@$$]`$'`($`R0')`0$$Z`,"`((!
-MY`#D``$$T`<&`(0"H`"@``$$N`L!`(8#C`",``$"<!<+`(P$/``\``$"*",/
-M`!($/``\``$"X"X*`)@&,``P``$"4$8.`"0&,``P``$"P%T)`#`(+``L``$"
-MH(P-`$@(+``L``$"@+L(`&`(+``L``$"\-(,`&P(+``L````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````````````````````````````````````````4````
-M``````$``7@0#`<(D`$````````4````'```````````````%@$````````<
-M````-```````````````+0````````!$#A```````!P```!4````````````
-M```-`0```````$0.$```````%````'0```````````````P`````````-```
-M`(P``````````````%$`````````0@X00@X80@X@00XH00XP@P:&!8P$C0..
-M`@`````````4````Q```````````````(0`````````4````W```````````
-M````U0$````````4````]```````````````5``````````<````#`$`````
-M````````1`$```````!$#B!*A@*#`QP````L`0`````````````G````````
-M`$$.$(,"````'````$P!`````````````$0`````````00X0@P(````T````
-M;`$`````````````L@````````!"#A!"#AA"#B!!#BA!#C"#!H8%C`2-`XX"
-M`````````!0```"D`0````````````!%`0```````!0```"\`0``````````
-M``!O`````````!P```#4`0````````````!D`````````$$.$(,"````'```
-M`/0!`````````````)0`````````00X0@P(````4````%`(`````````````
-M-`$````````4````+`(`````````````:``````````D````1`(`````````
-M````<@````````!$#B!.C`*&`X,$````````/````&P"`````````````%0!
-M````````0@X00@X80@X@0@XH00XP00XX1`Y`@P>&!HP%C02.`X\"````````
-M`!0``````````0`!>!`,!PB0`0```````!P````<``````````````!L````
-M`````$$.$(,"````%````#P``````````````$0`````````%````%0`````
-M`````````"4`````````+````&P``````````````)X"````````0@X00@X8
-M00X@00XH1`XP@P6&!(P#C0(`)````)P``````````````.0`````````0@X0
-M00X800X@@P2&`XP"`!P```#$``````````````!C`@```````$0.$```````
-M/````.0``````````````(@$````````0@X00@X80@X@0@XH00XP00XX1PZ0
-M`X,'A@:,!8T$C@./`@```````"0````D`0````````````!$`````````$$.
-M$$$.&$0.((,#A@(````4````3`$`````````````:0`````````\````9`$`
-M````````````(`8```````!"#A!"#AA"#B!"#BA!#C!!#CA$#H`!@P>&!HP%
-MC02.`X\"````````'````*0!`````````````-P`````````00X0@P(````\
-M````Q`$`````````````:@$```````!"#A!"#AA"#B!"#BA!#C!!#CA$#DB#
-M!X8&C`6-!(X#CP(`````````/`````0"`````````````/$!````````0@X0
-M0@X80@X@0@XH00XP00XX1`Y`@P>&!HP%C02.`X\"`````````#P```!$`@``
-M```````````G`P```````$(.$$(.&$(.($(.*$$.,$$..$0.4(,'A@:,!8T$
-MC@./`@`````````\````A`(`````````````50(```````!"#A!"#AA"#B!"
-M#BA!#C!!#CA$#E"#!X8&C`6-!(X#CP(`````````/````,0"````````````
-M``\$````````0@X00@X80@X@0@XH00XP00XX1`Y0@P>&!HP%C02.`X\"````
-M`````#0````$`P`````````````O#@```````$(.$$(.&$(.($$.*$$.,$0.
-M0(,&A@6,!(T#C@(`````'````#P#`````````````'P`````````1`X@2H8"
-M@P,<````7`,`````````````'`````````!$#A```````!0``````````0`!
-M>!`,!PB0`0```````!0````<```````````````H`````````!0````T````
-M```````````-`````````!0```!,```````````````B`````````!P```!D
-M``````````````!K`````````$0.$```````'````(0``````````````'4`
-M````````00X0@P(````D````I```````````````=P````````!$#B!.C`*&
-M`X,$````````)````,P``````````````),`````````1PZP`6"-`HP#A@2#
-M!0```!P```#T``````````````!#`````````$$.$(,"````%````!0!````
-M`````````#8`````````)````"P!`````````````',`````````00X000X8
-M1`X@@P.&`@```!P```!4`0````````````!2`````````$0.$```````%```
-M`'0!`````````````#@`````````/````(P!`````````````+L!````````
-M0@X00@X80@X@0@XH00XP00XX1`Y0@P>&!HP%C02.`X\"`````````!0```#,
-M`0`````````````M`````````!0```#D`0`````````````P`````````"P`
-M``#\`0`````````````I!P```````$<.\`-PCP*.`XT$C`6&!H,'````````
-M`!P````L`@````````````"Y`````````$$.$(,"````'````$P"````````
-M`````"L`````````00X0@P(````D````;`(`````````````]`````````!$
-M#B!.C`*&`X,$````````'````)0"`````````````"4`````````1`X0````
-M```\````M`(`````````````AP````````!"#A!"#AA"#B!"#BA!#C!!#CA$
-M#E"#!X8&C`6-!(X#CP(`````````'````/0"`````````````)0`````````
-M1`X@2H8"@P,<````%`,`````````````=P````````!!#A"#`@```"P````T
-M`P````````````"$`````````$(.$$$.&$$.($0.,(,$A@.,`@```````"P`
-M``!D`P````````````"$`````````$(.$$$.&$$.($0.,(,$A@.,`@``````
-M`!P```"4`P````````````!<`````````$0.($J&`H,#%``````````!``%X
-M$`P'")`!````````/````!P``````````````"\&````````0@X00@X80@X@
-M0@XH00XP00XX1P[@`8,'A@:,!8T$C@./`@```````!P```!<````````````
-M```.`````````$0.$```````%````'P``````````````!T`````````%```
-M`)0```````````````8`````````%````*P``````````````&L`````````
-M%``````````!``%X$`P'")`!````````%````!P``````````````$$`````
-M````'````#0``````````````&0`````````1`XP```````4````5```````
-M````````-P`````````4````;```````````````ZP`````````4````````
-M``$``7@0#`<(D`$````````4````'```````````````$P`````````4````
-M-```````````````6P`````````4````3```````````````!P`````````4
-M````9```````````````A``````````4``````````$``7@0#`<(D`$`````
-M```4````'```````````````!@`````````4````-```````````````+@``
-M```````4````3```````````````F0`````````4````9```````````````
-MAP`````````D````?```````````````J@$```````!$#C!4C0*,`X8$@P4`
-M````%``````````!``%X$`P'")`!````````'````!P``````````````"``
-M````````1`X0```````<````/```````````````'P````````!$#A``````
-M`!P```!<```````````````=`````````$0.$```````%````'P`````````
-M``````8`````````'````)0``````````````&,`````````1`X@2H8"@P,4
-M````M```````````````,0`````````4````S```````````````!@``````
-M```D````Y```````````````6@````````!$#B!.C0*,`X,$````````%```
-M``P!`````````````"T`````````%````"0!`````````````"0`````````
-M%````#P!`````````````"P`````````%````%0!`````````````!\`````
-M````'````&P!`````````````&<`````````1`X0```````4````C`$`````
-M````````,P`````````4````I`$`````````````&``````````4````O`$`
-M````````````+@`````````4````U`$`````````````!@`````````4````
-M[`$`````````````"0`````````D````!`(`````````````K`````````!!
-M#A!!#AA$#B"#`X8"````%````"P"`````````````"@`````````%````$0"
-M``````````````L`````````%````%P"`````````````!8`````````%```
-M`'0"`````````````#4`````````%````(P"`````````````"$`````````
-M%````*0"`````````````$$`````````)````+P"`````````````'(`````
-M````1`X@3HP"A@.#!````````!P```#D`@`````````````>`````````$0.
-M$```````)`````0#`````````````)<`````````1`XP6(X"C0.,!(8%@P8`
-M`!P````L`P`````````````>`````````$0.$```````%````$P#````````
-M``````X`````````%````&0#`````````````$H`````````)````'P#````
-M`````````)H`````````1`XP6(X"C0.,!(8%@P8``!P```"D`P``````````
-M```A`````````$0.$```````%````,0#``````````````8`````````%```
-M`-P#``````````````$`````````%````/0#``````````````8`````````
-M%`````P$``````````````$`````````%````"0$``````````````$`````
-M````'````#P$`````````````"0`````````1`X0```````<````7`0`````
-M````````.P````````!$#A```````!P```!\!``````````````.````````
-M`$0.$```````%``````````!``%X$`P'")`!````````%````!P`````````
-M`````"\`````````)````#0``````````````),`````````00X000X81`X@
-M@P.&`@```!0```!<```````````````O`````````"0```!T````````````
-M``!O`````````$0.($Z,`H8#@P0````````4````G```````````````$P``
-M```````4``````````$``7@0#`<(D`$````````<````'```````````````
-M,0````````!!#A"#`@```!0``````````0`!>!`,!PB0`0```````!0````<
-M```````````````(`````````!0````T```````````````(`````````!0`
-M``!,```````````````,`````````"0```!D``````````````!+````````
-M`$$.$$$.&$0.((,#A@(````4````C```````````````%``````````4````
-MI```````````````%``````````4````O```````````````%0`````````4
-M````U```````````````4@`````````4````[```````````````4@``````
-M```4````!`$`````````````"P`````````4````'`$`````````````'```
-M```````4````-`$`````````````.P`````````4````3`$`````````````
-M'@$````````4``````````$``7@0#`<(D`$````````\````'```````````
-M````]@4```````!"#A!"#AA"#B!"#BA!#C!!#CA$#D"#!X8&C`6-!(X#CP(`
-M````````%````%P``````````````'0`````````'````'0`````````````
-M`!0`````````1`X0```````<````E```````````````&`````````!$#A``
-M`````!P```"T``````````````!F`````````$$.$(,"````'````-0`````
-M`````````-H`````````1`X@2H8"@P,\````]```````````````(P(`````
-M``!"#A!"#AA"#B!"#BA!#C!!#CA$#E"#!X8&C`6-!(X#CP(`````````)```
-M`#0!`````````````'0`````````1`X@3HP"A@.#!````````!0```!<`0``
-M``````````"M`````````!P```!T`0````````````#E`````````$$.$(,"
-M````%````)0!`````````````!@`````````/````*P!`````````````.@"
-M````````0@X00@X80@X@0@XH00XP00XX1`Y`@P>&!HP%C02.`X\"````````
-M`"P```#L`0````````````#*`@```````$(.$$$.&$$.($0.D`&#!(8#C`(`
-M`````!P````<`@````````````!T`````````$0.($J,`H,#%````#P"````
-M`````````!P`````````)````%0"`````````````(8`````````0@X000X8
-M00X@@P2&`XP"`!0```!\`@`````````````&`````````!0```"4`@``````
-M```````&`````````!0``````````0`!>!`,!PB0`0```````!P````<````
-M```````````M`````````$0.$```````'````#P``````````````#,`````
-M````1`X0```````D````7```````````````W0````````!$#C!8C@*-`XP$
-MA@6#!@``%````(0``````````````%X`````````%````)P`````````````
-M`&`"````````%````+0``````````````"D`````````%````,P`````````
-M`````$$`````````)````.0``````````````)(`````````1`X@3HP"A@.#
-M!````````!0````,`0````````````!G`````````!0````D`0``````````
-M```R`````````"0````\`0````````````"8`````````$$.$$$.&$0.((,#
-MA@(````4````9`$`````````````KP`````````4````?`$`````````````
-M!@`````````4````E`$`````````````"``````````4````K`$`````````
-M````2@`````````4````Q`$`````````````CP`````````4````W`$`````
-M`````````0`````````4``````````$``7@0#`<(D`$````````4````'```
-M````````````"@`````````4``````````$``7@0#`<(D`$````````<````
-M'```````````````6P````````!$#A```````#P````\``````````````"C
-M!````````$(.$$(.&$(.($(.*$$.,$$..$0.4(,'A@:,!8T$C@./`@``````
-M```<````?```````````````&@````````!!#A"#`@```!P```"<````````
-M``````#W`````````$$.$$0.,(,"%````+P``````````````#@`````````
-M%````-0```````````````8`````````+````.P``````````````/0`````
-M````0@X00@X800X@00XH1`XP@P6&!(P#C0(`%``````````!``%X$`P'")`!
-M````````%````!P``````````````$$`````````'````#0`````````````
-M`'``````````1`XP```````4````5```````````````-P`````````4````
-M;```````````````[@`````````4``````````$``7@0#`<(D`$````````4
-M````'```````````````$P`````````4````-```````````````K```````
-M```4````3```````````````!P`````````4````9```````````````G@``
-M```````4``````````$``7@0#`<(D`$````````4````'```````````````
-M!@`````````4````-```````````````+@`````````4````3```````````
-M````F0`````````4````9```````````````AP`````````L````?```````
-M````````MP$```````!"#A!"#AA!#B!!#BA$#C"#!88$C`.-`@`4````````
-M``$``7@0#`<(D`$````````<````'```````````````(`````````!$#A``
-M`````!P````\```````````````?`````````$0.$```````'````%P`````
-M`````````!T`````````1`X0```````4````?```````````````!@``````
-M```<````E```````````````;0````````!$#B!*A@*#`Q0```"T````````
-M```````Q`````````!0```#,```````````````Q`````````"0```#D````
-M``````````!X`````````$0.($Z-`HP#@P0````````4````#`$`````````
-M````(@`````````4````)`$`````````````)``````````4````/`$`````
-M````````+``````````4````5`$`````````````'P`````````<````;`$`
-M````````````0P````````!$#A```````!0```",`0`````````````@````
-M`````!P```"D`0````````````"1`````````$0.($J&`H,#%````,0!````
-M`````````"@`````````%````-P!``````````````L`````````%````/0!
-M`````````````!8`````````%`````P"`````````````#4`````````%```
-M`"0"`````````````#4`````````%````#P"`````````````$$`````````
-M)````%0"`````````````&X`````````1`X@3HP"A@.#!````````!P```!\
-M`@`````````````>`````````$0.$```````)````)P"`````````````)<`
-M````````1`XP6(X"C0.,!(8%@P8``!P```#$`@`````````````>````````
-M`$0.$```````%````.0"``````````````X`````````%````/P"````````
-M`````$H`````````)````!0#`````````````)H`````````1`XP6(X"C0.,
-M!(8%@P8``!P````\`P`````````````A`````````$0.$```````%````%P#
-M``````````````8`````````%````'0#``````````````$`````````%```
-M`(P#``````````````8`````````%````*0#``````````````$`````````
-M%````+P#``````````````$`````````%````-0#`````````````!``````
-M````%````.P#``````````````X`````````%`````0$``````````````X`
-M````````%````!P$``````````````<`````````'````#0$````````````
-M`"<`````````1`X0```````<````5`0`````````````*0````````!$#A``
-M`````!P```!T!``````````````O`````````$0.$```````'````)0$````
-M`````````!8`````````1`X0```````4``````````$``7@0#`<(D`$`````
-M```D````'```````````````DP````````!!#A!!#AA$#B"#`X8"````%```
-M`$0``````````````"\`````````%````%P``````````````"\`````````
-M)````'0``````````````&\`````````1`X@3HP"A@.#!````````!0```"<
-M```````````````3`````````!0``````````0`!>!`,!PB0`0```````!P`
-M```<``````````````!(`````````$$.$(,"````%``````````!``%X$`P'
-M")`!````````%````!P```````````````@`````````%````#0`````````
-M``````@`````````%````$P```````````````P`````````'````&0`````
-M`````````#``````````1`X0```````4````A```````````````%```````
-M```4````G```````````````%``````````4````M```````````````%0``
-M```````4````S```````````````4@`````````4````Y```````````````
-M4@`````````4````_```````````````"P`````````4````%`$`````````
-M````"P`````````4````+`$`````````````.P`````````4````1`$`````
-M````````VP`````````4``````````$``7@0#`<(D`$````````\````'```
-M````````````H`@```````!"#A!"#AA"#B!"#BA!#C!!#CA$#K`!@P>&!HP%
-MC02.`X\"````````'````%P``````````````!,`````````1`X0```````<
-M````?```````````````10````````!!#A"#`@```!P```"<````````````
-M``"I`0```````$0.($J&`H,#)````+P``````````````&,!````````1`XP
-M6(X"C0.,!(8%@P8``"0```#D``````````````!Y`````````$0.($Z,`H8#
-M@P0````````L````#`$``````````````0$```````!"#A!"#AA!#B!!#BA$
-M#C"#!88$C`.-`@`4````/`$`````````````'``````````D````5`$`````
-M````````I0````````!"#A!!#AA!#B"#!(8#C`(`%````'P!````````````
-M`$\`````````'````)0!`````````````&4`````````1`X@2H8"@P,D````
-MM`$`````````````MP````````!$#C!/C`*&`X,$````````%````-P!````
-M`````````$4`````````/````/0!`````````````$8#````````0@X00@X8
-M0@X@0@XH00XP00XX1`Z``8,'A@:,!8T$C@./`@```````!0````T`@``````
-M```````/`0```````#0```!,`@````````````!L`@```````$(.$$(.&$(.
-M($$.*$$.,(,&A@6,!(T#C@(`````````%````(0"`````````````"(`````
-M````/````)P"`````````````(`!````````0@X00@X80@X@0@XH00XP00XX
-M1`Y@@P>&!HP%C02.`X\"`````````#P```#<`@````````````!2`P``````
-M`$(.$$(.&$(.($(.*$$.,$$..$0.4(,'A@:,!8T$C@./`@`````````\````
-M'`,`````````````6P0```````!"#A!"#AA"#B!"#BA!#C!!#CA$#J`!@P>&
-M!HP%C02.`X\"````````)````%P#`````````````'(!````````1`Y`5(T"
-MC`.&!(,%`````!0```"$`P````````````!@`````````!P```"<`P``````
-M``````"E`````````$$.$(,"````%````+P#`````````````)T`````````
-M'````-0#`````````````$,`````````1`X0```````4````]`,`````````
-M````0@`````````4````#`0`````````````=P`````````4````)`0`````
-M````````)@`````````D````/`0`````````````J0````````!$#B!.C`*&
-M`X,$````````%````&0$`````````````!@`````````%````'P$````````
-M`````!8!````````%````)0$`````````````$(`````````%````*P$````
-M`````````&8`````````'````,0$`````````````!0`````````1`X0````
-M```4``````````$``7@0#`<(D`$````````D````'```````````````J0``
-M``````!$#B!.C`*&`X,$````````'````$0``````````````"T`````````
-M1`X0```````<````9```````````````,P````````!$#A```````"0```"$
-M``````````````#T`````````$0.,%B.`HT#C`2&!8,&```4````K```````
-M````````<``````````<````Q```````````````<0````````!$#A``````
-M`!P```#D``````````````#%`P```````$0.$```````%`````0!````````
-M``````\`````````%````!P!`````````````!0`````````%````#0!````
-M`````````!D`````````%````$P!`````````````#$`````````)````&0!
-M`````````````&0`````````0@X000X800X@@P2&`XP"`!0```",`0``````
-M``````"0`````````!0```"D`0`````````````&`````````!0```"\`0``
-M```````````(`````````!0```#4`0````````````!*`````````!0```#L
-M`0````````````"V`````````!0````$`@`````````````!`````````!0`
-M`````````0`!>!`,!PB0`0```````!0````<```````````````O````````
-M`!0``````````0`!>!`,!PB0`0```````!0````<``````````````"-````
-M`````!P````T``````````````!;`````````$0.$```````'````%0`````
-M`````````/4`````````1PZ0`0`````4````=```````````````$@``````
-M```T````C```````````````\`````````!"#A!"#AA"#B!"#BA!#C"#!HP%
-MC02.`X\"`````````!0```#$``````````````!%`````````#P```#<````
-M``````````"9!@```````$(.$$(.&$(.($(.*$$.,$$..$0.0(,'A@:,!8T$
-MC@./`@`````````<````'`$`````````````3P````````!!#A"#`@```!P`
-M```\`0````````````#W`````````$$.$$0.,(,"%````%P!````````````
-M`$$`````````+````'0!```````````````$````````0@X00@X800X@00XH
-M1`XP@P6&!(P#C0(`'````*0!`````````````!8`````````1`X0```````4
-M````Q`$`````````````'0`````````4``````````$``7@0#`<(D`$`````
-M```<````'```````````````CP````````!$#B!*A@*#`QP````\````````
-M``````!P`````````$0.,```````%````%P``````````````#<`````````
-M%````'0``````````````$(!````````%``````````!``%X$`P'")`!````
-M````'````!P``````````````&T`````````1`X@2H8"@P,4``````````$`
-M`7@0#`<(D`$````````4````'```````````````(@`````````4````-```
-M````````````)``````````4````3```````````````+``````````4````
-M9```````````````'P`````````<````?```````````````8P````````!$
-M#A```````!0``````````0`!>!`,!PB0`0```````!0````<````````````
-M```4`````````!0````T``````````````!S`0```````!0```!,````````
-M```````'`````````!0```!D```````````````-`0```````!0`````````
-M`0`!>!`,!PB0`0```````!0````<```````````````(`````````!0````T
-M```````````````Q`````````!0```!,``````````````#V`````````!0`
-M``!D``````````````"+`````````#P```!\``````````````"P`P``````
-M`$(.$$(.&$(.($(.*$$.,$$..$0.4(,'A@:,!8T$C@./`@`````````4````
-M``````$``7@0#`<(D`$````````<````'```````````````(`````````!$
-M#A```````!P````\```````````````?`````````$0.$```````'````%P`
-M`````````````"``````````1`X0```````<````?```````````````;@``
-M``````!!#A"#`@```!0```"<```````````````Q`````````!0```"T````
-M``````````!9`````````"0```#,``````````````"#`````````$0.($Z,
-M`H8#@P0````````4````]```````````````(``````````<````#`$`````
-M````````D0````````!$#B!*A@*#`Q0````L`0`````````````H````````
-M`!0```!$`0`````````````+`````````!0```!<`0`````````````@````
-M`````!0```!T`0````````````!W`````````!0```",`0`````````````U
-M`````````!0```"D`0`````````````U`````````!0```"\`0``````````
-M``!!`````````!0```#4`0`````````````&`````````!0```#L`0``````
-M```````0`````````!0````$`@`````````````.`````````!0````<`@``
-M```````````.`````````!0````T`@`````````````'`````````!P```!,
-M`@`````````````G`````````$0.$```````%````&P"``````````````8`
-M````````)````(0"`````````````'(`````````1`X@3HP"A@.#!```````
-M`!P```"L`@`````````````>`````````$0.$```````)````,P"````````
-M`````)<`````````1`XP6(X"C0.,!(8%@P8``!P```#T`@`````````````>
-M`````````$0.$```````%````!0#``````````````X`````````%````"P#
-M`````````````$H`````````)````$0#`````````````)H`````````1`XP
-M6(X"C0.,!(8%@P8``!P```!L`P`````````````A`````````$0.$```````
-M%````(P#`````````````$$`````````'````*0#`````````````"<!````
-M````1`X@2H8"@P,<````Q`,`````````````%`````````!$#A```````!0`
-M``#D`P`````````````B`````````!P```#\`P`````````````>`@``````
-M`$$.$(,"````'````!P$`````````````.L`````````00X0@P(````4````
-M/`0`````````````,0`````````<````5`0`````````````80(```````!$
-M#B!*A@*#`QP```!T!`````````````"1`0```````$0.$```````'````)0$
-M`````````````!8`````````1`X0```````4``````````$``7@0#`<(D`$`
-M```````D````'```````````````DP````````!!#A!!#AA$#B"#`X8"````
-M%````$0``````````````#0`````````%````%P``````````````#0`````
-M````)````'0``````````````&\`````````1`X@3HP"A@.#!````````!0`
-M``"<```````````````3`````````!0``````````0`!>!`,!PB0`0``````
-M`!P````<``````````````#;`````````$$.$(,"````%``````````!``%X
-M$`P'")`!````````%````!P```````````````@`````````%````#0`````
-M``````````@`````````%````$P```````````````P`````````'````&0`
-M`````````````#``````````1`X0```````<````A```````````````*P``
-M``````!!#A"#`@```!P```"D```````````````A`````````$0.$```````
-M%````,0``````````````!4`````````%````-P``````````````%(`````
-M````%````/0``````````````%(`````````%`````P!`````````````"H`
-M````````%````"0!`````````````%H`````````%````#P!````````````
-M`#``````````'````%0!`````````````!$!````````1`X0```````4````
-M``````$``7@0#`<(D`$````````\````'```````````````30T```````!"
-M#A!"#AA"#B!"#BA!#C!!#CA$#H`!@P>&!HP%C02.`X\"````````%````%P`
-M`````````````&``````````'````'0``````````````!<`````````1`X0
-M```````\````E```````````````*0(```````!"#A!"#AA"#B!"#BA!#C!!
-M#CA$#D"#!X8&C`6-!(X#CP(`````````%````-0``````````````',`````
-M````'````.P``````````````!,`````````1`X0```````<````#`$`````
-M````````+P````````!!#A"#`@```"0````L`0````````````!0`@``````
-M`$0.,%2-`HP#A@2#!0`````T````5`$`````````````F@(```````!"#A!"
-M#AA"#B!!#BA!#C"#!H8%C`2-`XX"`````````"0```",`0````````````"\
-M`````````$0.($Z,`H8#@P0````````4````M`$`````````````'```````
-M```4````S`$`````````````3P`````````D````Y`$`````````````>0``
-M``````!$#C!/C`*&`X,$````````%`````P"`````````````(0`````````
-M+````"0"`````````````*L`````````0@X00@X800X@00XH1`XP@P6&!(P#
-MC0(`%````%0"`````````````#8!````````'````&P"`````````````'T`
-M````````00X0@P(````\````C`(`````````````4`0```````!"#A!"#AA"
-M#B!"#BA!#C!!#CA$#E"#!X8&C`6-!(X#CP(`````````/````,P"````````
-M`````,@%````````0@X00@X80@X@0@XH00XP00XX1`Z``8,'A@:,!8T$C@./
-M`@```````!0````,`P````````````#&`````````!P````D`P``````````
-M```L`````````$0.$```````+````$0#`````````````#4#````````0@X0
-M0@X800X@00XH1`Y`@P6&!(P#C0(`/````'0#`````````````'(%````````
-M0@X00@X80@X@0@XH00XP00XX1P[P`8,'A@:,!8T$C@./`@```````#P```"T
-M`P````````````#N`````````$(.$$(.&$(.($(.*$$.,$$..$0.4(,'A@:,
-M!8T$C@./`@`````````L````]`,`````````````)P$```````!"#A!!#AA!
-M#B!$#D"#!(8#C`(````````L````)`0`````````````I@````````!"#A!!
-M#AA!#B!$#D"#!(8#C`(````````<````5`0`````````````AP````````!!
-M#A"#`@```#P```!T!`````````````!8`0```````$(.$$(.&$(.($(.*$$.
-M,$$..$0.8(,'A@:,!8T$C@./`@`````````4````M`0`````````````>P``
-M```````4````S`0`````````````?P`````````<````Y`0`````````````
-M\@````````!!#A"#`@```!0````$!0`````````````M`````````"0````<
-M!0`````````````C`0```````$0.($Z,`H8#@P0````````4````1`4`````
-M````````&``````````4````7`4`````````````^P`````````D````=`4`
-M````````````N`````````!$#B!.C`*&`X,$````````+````)P%````````
-M`````+D`````````0@X00@X800X@00XH1`XP@P6&!(P#C0(`/````,P%````
-M`````````&P!````````0@X00@X80@X@0@XH00XP00XX1`Y`@P>&!HP%C02.
-M`X\"`````````!0````,!@````````````"@`````````!0``````````0`!
-M>!`,!PB0`0```````"0````<``````````````"M`````````$0.,%2-`HP#
-MA@2#!0`````<````1```````````````-P````````!$#A```````!P```!D
-M```````````````]`````````$0.$```````/````(0``````````````%0!
-M````````0@X00@X80@X@0@XH00XP00XX1`Y`@P>&!HP%C02.`X\"````````
-M`!0```#$``````````````!P`````````!P```#<``````````````!Y````
-M`````$0.$```````'````/P``````````````-<#````````00X0@P(````4
-M````'`$`````````````#P`````````4````-`$`````````````%```````
-M```4````3`$`````````````&0`````````4````9`$`````````````,0``
-M```````L````?`$`````````````;@$```````!"#A!"#AA!#B!!#BA$#C"#
-M!88$C`.-`@`4````K`$`````````````.0$````````4````Q`$`````````
-M````9P`````````4````W`$`````````````"``````````4````]`$`````
-M````````:0`````````4````#`(`````````````0@$````````4````)`(`
-M````````````$P`````````4``````````$``7@0#`<(D`$````````<````
-M'```````````````50````````!!#A"#`@```!P````\```````````````Y
-M`````````$$.$(,"````%````%P``````````````%4`````````%````'0`
-M``````````````@`````````'````(P``````````````!D`````````00X0
-M@P(````D````K```````````````-P$```````!"#A!!#AA!#B"#!(8#C`(`
-M'````-0``````````````#``````````00X0@P(````D````]```````````
-M````Q`0```````!'#I`!388"@P,`````````'````!P!`````````````*<`
-M````````00X0@P(````<````/`$`````````````&`$```````!$#B!*A@*#
-M`QP```!<`0````````````"H`````````$0.($J&`H,#+````'P!````````
-M`````!4"````````0@X00@X800X@00XH1`XP@P6&!(P#C0(`)````*P!````
-M`````````-$`````````0@X000X800X@@P2&`XP"`!P```#4`0``````````
-M``!/`````````$$.$(,"````'````/0!`````````````(8`````````1`X0
-M```````4````%`(`````````````>``````````D````+`(`````````````
-M"0(```````!$#C!4C0*,`X8$@P4`````%``````````!``%X$`P'")`!````
-M````%````!P``````````````$T`````````%``````````!``%X$`P'")`!
-M````````/````!P``````````````-\`````````0@X00@X80@X@0@XH00XP
-M00XX1`Y`@P>&!HP%C02.`X\"`````````"P```!<```````````````N`0``
-M`````$(.$$(.&$$.($$.*$0.,(,%A@2,`XT"`!0```",```````````````[
-M`````````#P```"D```````````````$!@```````$(.$$(.&$(.($(.*$$.
-M,$$..$0.L`&#!X8&C`6-!(X#CP(````````<````Y```````````````AP``
-M``````!!#A"#`@```#P````$`0````````````"R`P```````$(.$$(.&$(.
-M($(.*$$.,$$..$<.@`.#!X8&C`6-!(X#CP(````````D````1`$`````````
-M````8`$```````!$#D!4C0*,`X8$@P4`````%````&P!`````````````&@`
-M````````'````(0!`````````````$,`````````1`X0```````<````I`$`
-M````````````2`````````!!#A"#`@```!0```#$`0`````````````&````
-M`````!0```#<`0`````````````Q`````````!P```#T`0````````````#$
-M`````````$0.($J&`H,#%``````````!``%X$`P'")`!````````/````!P`
-M`````````````-\`````````0@X00@X80@X@0@XH00XP00XX1`Y`@P>&!HP%
-MC02.`X\"`````````#0```!<``````````````#@`@```````$(.$$(.&$(.
-M($$.*$$.,(,&A@6,!(T#C@(`````````%````)0``````````````#8`````
-M````/````*P``````````````'`'````````0@X00@X80@X@0@XH00XP00XX
-M1`Y@@P>&!HP%C02.`X\"`````````#P```#L``````````````#G!@``````
-M`$(.$$(.&$(.($(.*$$.,$$..$<.X`B#!X8&C`6-!(X#CP(````````4````
-M+`$`````````````/0`````````4````1`$`````````````<0`````````\
-M````7`$`````````````R`````````!"#A!"#AA"#B!"#BA!#C!!#CA$#D"#
-M!X8&C`6-!(X#CP(`````````%````)P!`````````````+8`````````)```
-M`+0!`````````````/L`````````0@X000X800X@@P2&`XP"`!P```#<`0``
-M``````````!(`````````$$.$(,"````%````/P!`````````````(4`````
-M````/````!0"`````````````/,!````````0@X00@X80@X@0@XH00XP00XX
-M1`Y`@P>&!HP%C02.`X\"`````````#P```!4`@````````````!X````````
-M`$(.$$(.&$(.($(.*$$.,$$..$0.0(,'A@:,!8T$C@./`@`````````<````
-ME`(`````````````S@````````!$#B!*A@*#`Q0``````````0`!>!`,!PB0
-M`0```````#P````<``````````````#B`````````$(.$$(.&$(.($(.*$$.
-M,$$..$0.0(,'A@:,!8T$C@./`@`````````T````7```````````````X`(`
-M``````!"#A!"#AA"#B!!#BA!#C"#!H8%C`2-`XX"`````````#P```"4````
-M``````````"B`@```````$(.$$(.&$(.($(.*$$.,$$..$0.0(,'A@:,!8T$
-MC@./`@`````````4````U```````````````,P`````````4````[```````
-M````````?0`````````\````!`$`````````````(P$```````!"#A!"#AA"
-M#B!"#BA!#C!!#CA$#E"#!X8&C`6-!(X#CP(`````````%````$0!````````
-M`````#T`````````/````%P!`````````````/$$````````0@X00@X80@X@
-M0@XH00XP00XX1`Z``8,'A@:,!8T$C@./`@```````#0```"<`0``````````
-M``"*`0```````$(.$$(.&$(.($$.*$$.,$0.4(,&A@6,!(T#C@(`````'```
-M`-0!`````````````&D`````````00X0@P(````4````]`$`````````````
-M+P`````````4````#`(`````````````+P`````````\````)`(`````````
-M````(`(```````!"#A!"#AA"#B!"#BA!#C!!#CA$#F"#!X8&C`6-!(X#CP(`
-M````````/````&0"`````````````'@`````````0@X00@X80@X@0@XH00XP
-M00XX1`Y`@P>&!HP%C02.`X\"`````````!P```"D`@````````````#:````
-M`````$0.($J&`H,#%``````````!``%X$`P'")`!````````/````!P`````
-M`````````-\`````````0@X00@X80@X@0@XH00XP00XX1`Y`@P>&!HP%C02.
-M`X\"`````````#0```!<``````````````"T`@```````$(.$$(.&$(.($$.
-M*$$.,(,&A@6,!(T#C@(`````````/````)0```````````````H$````````
-M0@X00@X80@X@0@XH00XP00XX1`Y`@P>&!HP%C02.`X\"`````````!0```#4
-M```````````````V`````````!0```#L``````````````!]`````````#P`
-M```$`0`````````````C`0```````$(.$$(.&$(.($(.*$$.,$$..$0.4(,'
-MA@:,!8T$C@./`@`````````4````1`$`````````````/0`````````\````
-M7`$`````````````\00```````!"#A!"#AA"#B!"#BA!#C!!#CA$#H`!@P>&
-M!HP%C02.`X\"````````-````)P!`````````````(L!````````0@X00@X8
-M0@X@00XH00XP1`Y0@P:&!8P$C0..`@`````<````U`$`````````````:0``
-M``````!!#A"#`@```!0```#T`0`````````````O`````````!0````,`@``
-M```````````O`````````#P````D`@`````````````'`@```````$(.$$(.
-M&$(.($(.*$$.,$$..$0.4(,'A@:,!8T$C@./`@`````````\````9`(`````
-M````````>`````````!"#A!"#AA"#B!"#BA!#C!!#CA$#D"#!X8&C`6-!(X#
-MCP(`````````'````*0"`````````````-H`````````1`X@2H8"@P,`````
-M````````````````````````````1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N
-M-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H1TY5*2`S+C,N-```1T-#.B`H
-M1TY5*2`S+C,N-```+G-Y;71A8@`N<W1R=&%B`"YS:'-T<G1A8@`N<F5L82YT
-M97AT`"YR96QA+G)O9&%T80`N<F]D871A+G-T<C$N,0`N<F5L82YD871A`"YR
-M96QA+F5H7V9R86UE`"YB<W,`+F-O;6UE;G0`+FYO=&4N1TY5+7-T86-K````
-M````````````````````````````````````````````````````````````
-M```````````````````````````````@`````0````8`````````````````
-M``!``````````."A`0`````````````````$````````````````````&P``
-M``0`````````````````````````T!H#``````!03`````````X````!````
-M"``````````8`````````"L````!`````@```````````````````""B`0``
-M````2)<``````````````````"`````````````````````F````!```````
-M```````````````````@9P,```````@K````````#@````,````(````````
-M`!@`````````,P````$````R````````````````````:#D"``````#>````
-M`````````````````0`````````!`````````$<````!`````P``````````
-M`````````&`Z`@``````!%<``````````````````"``````````````````
-M``!"````!``````````````````````````HD@,``````*@`````````#@``
-M``8````(`````````!@`````````4@````$````"````````````````````
-M:)$"```````@20``````````````````"````````````````````$T````$
-M`````````````````````````-"2`P``````<#(````````.````"`````@`
-M````````&`````````!<````"`````,```````````````````"@V@(`````
-M`+`!```````````````````@````````````````````80````$`````````
-M````````````````H-H"``````"H`P```````````````````0``````````
-M`````````&H````'`````````````````````````$C>`@``````````````
-M``````````````$````````````````````1`````P``````````````````
-M``````!(W@(``````'H````````````````````!````````````````````
-M`0````(`````````````````````````R.("``````!`)@````````\````)
-M````"``````````8``````````D````#``````````````````````````@)
-M`P``````Q1$```````````````````$`````````````````````````````
-M`````````````````````````````P`!````````````````````````````
-M`P`#`````````````````````````````P`%````````````````````````
-M`````P`&`````````````````````````````P`*````````````````````
-M`````````P`(`````````````````````````````P`+````````````````
-M`````````````P`,```````````````````````!````$@`!`&V(````````
-M<``````````,````$@`!`!5Y````````!@`````````7````$@`!`#OS````
-M````D0$````````B````$@`!`'E?````````EP`````````M````$@`!`!P(
-M`0``````*0(````````X````$@`!`+C)````````+P````````!#````$@`!
-M`+,2`0``````-@$```````!.````$@`!`)15````````ZP````````!9````
-M$@`!`*-,`0``````T0````````!D````$0`&`,`]````````I`$```````!O
-M````$@`!`+?W````````(0````````!Z````$@`!`()7````````+@``````
-M``"%````$@`!`-Q)````````]`````````"0````$0`&`&!.````````I`$`
-M``````";````$@`!`'[M````````(@````````"F````$@`!`$KI````````
-M$`````````"Q````$@`!`-C?````````"`````````"\````$@`!``#)````
-M````M@````````#'````$@`!`/33````````]P````````#2````$@`!`)T(
-M````````;P````````#=````$@`!`!&^````````J0````````#H````$@`!
-M`,^H````````MP````````#S````$@`!`.63````````2@````````#^````
-M$@`!`("7````````"``````````)`0``$@`!`!=]````````*0`````````4
-M`0``$@`!`*GP````````,0`````````?`0``$@`!`*C(````````!@``````
-M```J`0``$@`!`#S=````````%``````````U`0``$@`!`$4*`0``````<P``
-M``````!``0``$@`!`&(&````````1`````````!+`0``$@`!`-?+````````
-M\`````````!6`0``$@`!`&B+````````!@````````!A`0``$@`!`#@_`0``
-M````:0````````!L`0``$@`!`/-_````````!@````````!W`0``$@`!`(B7
-M````````"`````````""`0``$@`!`!(,````````5`$```````"=`0``$0`&
-M`"!)````````I`$```````"H`0``$@`!`#KJ````````EP````````"S`0``
-M$@`!`!-^````````9P````````"^`0``$@`!`*T"````````(0````````#)
-M`0``$@`!`/A``0``````50````````#4`0``$```````````````````````
-M``#U`0``$@`!`-5<````````,P```````````@``$@`!`$/L````````)P$`
-M```````+`@``$@`!``+L````````00`````````6`@``$@`!`*3`````````
-MJ0`````````A`@``$@`!`(=>````````(0`````````L`@``$@`!`*Z0````
-M````0P`````````W`@``$@`!`"^4````````F@````````!"`@``$@`!`'K!
-M````````,P````````!-`@``$@`!`+..````````'0````````!8`@``$@`!
-M`/WJ````````2@````````!C`@``$@`!``&`````````2@````````!N`@``
-M$@`!`"-<````````+`````````!Y`@``$@`!`$EY````````,P````````"$
-M`@``$@`!`*/E````````;@````````"/`@``$@`!`'R5````````+P``````
-M``":`@``$@`!`-'J````````'@````````"E`@``$@`!`*KI````````<@``
-M``````"P`@``$@`!`'7*````````6P````````"[`@``$@`!`,L*`0``````
-M+P````````#&`@``$@`!`'Q7````````!@````````#1`@``$@`!`$?K````
-M````F@````````#<`@``$@`!`.Q-````````+P8```````#G`@``$@`!`"R5
-M````````)P````````#R`@``$@`!`,_G````````*`````````#]`@``$@`!
-M`%P"````````40`````````(`P``$@`!`!SJ````````'@`````````3`P``
-M$@`!`,HN`0``````(P$````````>`P``$@`!`&K<````````)``````````I
-M`P``$@`!`(01`0``````A``````````T`P``$@`!`#Q>````````%@``````
-M```_`P``$@`!`)R+````````F0````````!*`P``$@`!`*6/````````>```
-M``````!5`P``$@`!`&UX````````'`````````!@`P``$@`!`(`T`0``````
-MK0````````!K`P``$@`!``9N````````(P(```````!V`P``$@`!`$YA````
-M`````0````````"!`P``$@`!`"TU`0``````-P````````",`P``$@`!`+=Z
-M````````8`(```````"7`P``$@`!`$,!````````#0$```````"F`P``$@`!
-M`'`?`0``````-0,```````"Q`P``$@`!`&3V````````VP````````"\`P``
-M$@`!``F5````````#@````````#'`P``$@`!`'$R`0``````;`$```````#2
-M`P``$@`!`+[O````````ZP````````#=`P``$@`!`$CW````````"```````
-M``#H`P``$@`!`%`"````````#`````````#S`P``$@`!`,J1````````"P``
-M``````#^`P``$@`!`*W!````````]``````````)!```$@`!`$W!````````
-M+0`````````4!```$@`!`(^B````````10`````````?!```$@`!`!M4````
-M````#@`````````J!```$@`!`%)>````````-0`````````U!```$@`!`,X"
-M````````U0$```````!+!```$@`!`*`0`0``````'`````````!6!```$@`!
-M`$N`````````CP````````!A!```$@`!`%M?````````'@````````!L!```
-M$@`!``2*````````$P````````!W!```$@`!`+@*`0``````$P````````""
-M!```$@`!`(RP````````(@````````"-!```$@`!`)+A````````L`,`````
-M``"8!```$@`!`,/>````````!P````````"C!```$@`!`$E8````````AP``
-M``````"N!```$@`!`-V(````````-P````````"Y!```$@`!`#-#`0``````
-M,`````````#$!```$@`!`!'@````````]@````````#/!```$@`!`/>4````
-M`````0````````#:!```$@`!`&Y<````````9P````````#E!```$@`!`)#`
-M````````%`````````#P!```$@`!``S-````````F08```````#[!```$@`!
-M`+@Q`0``````N0`````````&!0``$@`!`$3I````````!@`````````1!0``
-M$@`!`)2.````````'P`````````<!0``$@`!`#_X````````4@`````````G
-M!0``$@`!``]Y````````!@`````````R!0``$@`!`)`]`0``````.0$`````
-M```]!0``$@`!`,.8````````.P````````!(!0``$@`!`'A;````````6@``
-M``````!3!0``$@`!`.'K````````(0````````!>!0``$@`!`*73````````
-M3P````````!I!0``$@`!`%;'````````%`````````!T!0``$@`!`$U!`0``
-M````.0````````!_!0``$`````````````````````````",!0``$@`!`%EZ
-M````````7@````````"7!0``$@`!`-=D````````.P````````"B!0``$@`!
-M`#`_`0``````"`````````"M!0``$@`!`-M!`0``````"`````````"X!0``
-M$@`!`"+H````````=P````````##!0``$@`!`/<$````````1`$```````#4
-M!0``$@`!`-XW`0``````UP,```````#?!0``$@`!`*A>````````00``````
-M``#J!0``$@`!`*Q^````````F`````````#U!0``$@`!`/"4`````````0``
-M````````!@``$@`!`%KI````````#@`````````+!@``$@`!`'1-`0``````
-M3P`````````6!@``$@`!`%YD````````4@`````````A!@``$@`!`&#9````
-M````CP`````````L!@``$@`!`&Z+````````+@`````````W!@``$@`!`'VD
-M````````8P$```````!"!@``$@`!`(EX````````A@````````!-!@``$@`!
-M`+88`0``````R`4```````!8!@``$@`!`!7Y````````,`````````!C!@``
-M$@`!`,ST````````%@````````!N!@``$@`!`/Z8````````VP````````!Y
-M!@``$@`!`*#M````````'@(```````"$!@``$@`!`):2````````;@``````
-M``"/!@``$@`!`/F4````````$`````````":!@``$@`!`-KP````````80(`
-M``````"E!@``$@`!`*$U`0``````5`$```````"P!@``$@`!`&-#`0``````
-MQ`0```````"[!@``$@`!`%.5````````*0````````#&!@``$@`!`-R`````
-M````"@````````#1!@``$@`!`.Y6````````!P````````#<!@``$@`!`!2)
-M````````[@````````#G!@``$@`!`![G````````(`````````#R!@``$@`!
-M`*]A````````#@````````#]!@``$@`!`+J,`0``````V@`````````(!P``
-M$@`!`$=A`````````0`````````3!P``$@`!`';I````````!P`````````>
-M!P``$@`!`,[H````````-0`````````I!P``$0`&`.!1````````I`$`````
-M```T!P``$@`!`+3'````````9``````````_!P``$@`!`,Q0`0``````30``
-M``````!*!P``$@`!`#Q@````````2@````````!5!P``$@`!`)"7````````
-M#`````````!@!P``$@`!`!)E````````'@$```````!K!P``$@`!``4(`0``
-M````%P````````!V!P``$@`!`&3E````````'P````````"!!P``$@`!`#[G
-M````````D0````````",!P``$@`!`/Q!`0``````-P$```````"7!P``$@`!
-M`*YL````````&`````````"B!P``$@`!`'!C````````"`````````"M!P``
-M$@`!`%U=````````K`````````"X!P``$@`!`+MD````````'`````````##
-M!P``$@`!`)OF````````@P````````#.!P``$@`!`$H-`0``````F@(`````
-M``#9!P``$@`!`"(\`0``````;@$```````#D!P``$0`&`$!!````````I`$`
-M``````#O!P``$@`!`-!8````````J@$```````#Z!P``$@`!`$$^````````
-M0P`````````%"```$@`!`!QY````````+0`````````0"```$@`!`+!D````
-M````"P`````````;"```$``````````````````````````["```$@`!`#!F
-M````````]@4```````!&"```$0`&````````````"0````````!6"```$@`!
-M`.D3`0``````?0````````!A"```$@`!`!V0````````(@````````!L"```
-M$@`!``:A`0``````V@````````!W"```$@`!`.O4````````00````````""
-M"```$@`!``+H````````(`````````"-"```$@`!`$]A`````````0``````
-M``"8"```$@`!``L1`0``````>0````````"C"```$@`!`/&4````````!@``
-M``````"N"```$@`!`"27````````$P````````"Y"```$@`!`#6,````````
-MAP````````#$"```$@`!`'WI````````)P````````#/"```$```````````
-M``````````````#>"```$@`!`&.0````````+`````````#I"```$0`&`"!0
-M````````I`$```````#T"```$@`!`$[V````````$P````````#_"```$@`!
-M`%_:````````-P`````````*"0``$@`!`(:I````````10`````````5"0``
-M$@`!`)IL````````%``````````@"0``$@`!`"*3````````EP`````````K
-M"0``$@`!`,K>````````#0$````````V"0``$0`&`.!*````````I`$`````
-M``!!"0``$@`!`&KM````````%`````````!,"0``$@`!`**1````````*```
-M``````!7"0``$@`!`+OX````````6@````````!B"0``$@`!`(Y*`0``````
-M%0(```````!M"0``$@`!`+R,````````MP$```````!X"0``$@`!`.-C````
-M````%`````````"#"0``$@`!`$./````````,0````````"."0``$@`!`!&M
-M````````#P$```````"9"0``$@`!`"]R````````&`````````"D"0``$@`!
-M`.WW````````4@````````"O"0``$0`&`*!,````````I`$```````"Z"0``
-M$@`!`#^0````````)`````````#%"0``$@`!`!&1````````D0````````#0
-M"0``$@`!``E>````````*`````````#;"0``$@`!`,0[`0``````%```````
-M``#F"0``$`````````````````````````#U"0``$@`!`*[(````````"```
-M````````"@``$@`!`(/E````````(``````````+"@``$@`!`)Q:````````
-M'P`````````6"@``$@`!`._J````````#@`````````A"@``$@`!`.J4````
-M````!@`````````L"@``$@`!`$+F````````60`````````W"@``$0`&``!#
-M````````I`$```````!""@``$@`!`*V8````````"P````````!-"@``$@`!
-M`!>*````````K`````````!8"@``$@`!`!8!````````+0````````!F"@``
-M$0`&`(`_````````I`$```````!Q"@``$@`!`%N8````````4@````````!\
-M"@``$@`!`,.*````````!P````````"'"@``$0`&`"``````````0```````
-M``"9"@``$@`!``A=````````&`````````"D"@``$@`!`%1=````````"0``
-M``````"O"@``$@`!`.#?````````,0````````"Z"@``$@`!`+%B````````
-M;P````````#%"@``$@`!`,%.`0``````"0(```````#0"@``$@`!`"!C````
-M````$P````````#;"@``$@`!`->3````````#@````````#F"@``$@`!`(SW
-M````````*P````````#Q"@``$@`!`/A(````````N0````````#\"@``$@`!
-M`+4[`0``````#P`````````'"P``$@`!``F8````````4@`````````2"P``
-M$@`!`,F4````````(0`````````="P``$@`!`%SW````````,``````````H
-M"P``$@`!`&K'````````&0`````````S"P``$@`!`&0U`0``````/0``````
-M```^"P``$@`!`+F3````````'@````````!)"P``$@`!`'X>`0``````Q@``
-M``````!4"P``$@`!`,J*````````G@````````!?"P``$@`!`+;(````````
-M2@````````!J"P``$0`&`,!$````````I`$```````!U"P``$@`!`,]C````
-M````%`````````"`"P``$@`!`.-!`0``````&0````````"+"P``$@`!`)-6
-M````````6P````````"6"P``$@`!`#1C````````,0````````"A"P``$@`!
-M`(+#````````Q0,```````"L"P``$@`!`'1A````````.P````````"W"P``
-M$@`!`"Y@````````#@````````#""P``$@`!`);:````````0@$```````#-
-M"P``$@`!`-TS`0``````H`````````#8"P``$@`!`+B8````````"P``````
-M``#C"P``$@`!`+%)````````*P````````#N"P``$@`!`-G<````````8P``
-M``````#Y"P``$@`!`#@+````````:``````````$#```$@`!`%@'````````
-M10$````````/#```$@`!`$C<````````(@`````````:#```$@`!`(9@````
-M````F@`````````E#```$@`!`&AC````````"``````````P#```$@`!`"PM
-M`0``````?P`````````[#```$@`!`/];````````)`````````!&#```$@`!
-M`$0?`0``````+`````````!1#```$@`!`.0[````````'`````````!<#```
-M$@`!`*,$````````5`````````!G#```$@`!`!'F````````,0````````!R
-M#```$`````````````````````````""#```$@`!`*ZP````````@`$`````
-M``"-#```$@`!`(!6````````$P````````"8#```$@`!`,D^`0``````9P``
-M``````"C#```$@`!`$]<````````'P````````"N#```$@`!``?A````````
-MBP````````"Y#```$@`!`%62````````00````````#$#```$@`!`!C(````
-M````D`````````#/#```$`````````````````````````#O#```$@`!`*8&
-M````````L@````````#Z#```$@`!`-Y:````````8P`````````%#0``$@`!
-M`$%;````````,0`````````0#0``$@`!`'2/````````,0`````````;#0``
-M$@`!`+!7````````F0`````````F#0``$@`!`/&0````````(``````````Q
-M#0``$@`!`"S5``````````0````````\#0``$@`!`!>5````````#@``````
-M``!'#0``$@`!`$7Y````````$0$```````!2#0``$@`!`$%A````````!@``
-M``````!=#0``$@`!`'Q:````````(`````````!H#0``$@`!`$Y=````````
-M!@````````!S#0``$`````````````````````````"!#0``$@`!`'2.````
-M````(`````````",#0``$@`!`'`)````````E`````````"7#0``$@`!`%!A
-M````````)`````````"B#0``$@`!`/27````````%0````````"M#0``$@`!
-M`*N5````````%@````````"X#0``$@`!`"QM````````V@````````###0``
-M$@`!`/=C````````%0````````#.#0``$@`!`"!=````````+@````````#9
-M#0``$@`!`$3E````````(`````````#D#0``$@`!`%#W````````#```````
-M``#O#0``$@`!`*4'`0``````8`````````#Z#0``$@`!`(^0````````'P``
-M```````%#@``$@`!`+K<````````'P`````````0#@``$@`!`&84`0``````
-M4`0````````;#@``$@`!`#%>````````"P`````````F#@``$@`!`#B7````
-M````2``````````Q#@``$@`!`-61````````%@`````````\#@``$@`!`$1_
-M````````KP````````!'#@``$@`!`-:.````````;0````````!2#@``$@`!
-M`/B4`````````0````````!=#@``$@`!`'QY````````W0````````!H#@``
-M$0`&`*!3````````I`$```````!S#@``$@`!`-A:````````!@````````!^
-M#@``$@`!`-".````````!@````````")#@``$@`!`%U5````````-P``````
-M``"4#@``$@`!`/56````````A`````````"?#@``$@`!`([<````````+```
-M``````"J#@``$@`!`*`+````````<@````````"U#@``$@`!`.-``0``````
-M$P````````#`#@``$@`!`*3I````````!@````````#+#@``$@`!`""2````
-M````-0````````#6#@``$@`!`+$L`0``````>P````````#A#@``$@`!`+66
-M````````;P````````#L#@``$@`!`-R9````````H`@```````#W#@``$0`&
-M`&!5````````I`$````````"#P``$@`!`$+9````````'0`````````-#P``
-M$@`!`-);````````+0`````````8#P``$@`!`#L&````````)P`````````C
-M#P``$@`!`+M:````````'0`````````N#P``$@`!`*$_`0``````0@$`````
-M```Y#P``$@`!`&4W`0``````>0````````!$#P``$@`!`'AC````````#```
-M``````!/#P``$@`!``23````````'@````````!:#P``$@`!`$#W````````
-M"`````````!E#P``$@`!`(1C````````2P````````!P#P``$@`!`+A4````
-M````00````````![#P``$@`!`!!@````````'@````````"&#P``$@`!`.:%
-M````````&@````````"1#P``$@`!``0*````````-`$```````"<#P``$@`!
-M`+;)`````````0````````"G#P``$@`!`$!]````````00````````"R#P``
-M$@`!`,R7````````%`````````"]#P``$@`!`$AA````````!@````````#(
-M#P``$@`!`!'#````````<0````````#3#P``$@`!`-CW````````%0``````
-M``#>#P``$@`!`"M@`0``````Q`````````#I#P``$@`!`"!A````````(0``
-M``````#T#P``$@`!`-!*````````)0````````#_#P``$@`!`,]!````````
-M*0<````````5$```$@`!`)'X````````*@`````````@$```$@`!``QD````
-M````4@`````````K$```$@`!`%CZ````````30T````````V$```$@`!`%#=
-M````````<P$```````!!$```$@`!`(/'````````,0````````!,$```$@`!
-M`."7````````%`````````!7$```$@`!`(%]````````D@````````!B$```
-M$@`!`&@[````````?`````````!M$```$@`!`/E_````````"`````````!X
-M$```$@`!`,9L````````9@````````"#$```$@`!`)R7````````,```````
-M``".$```$@`!`'RB````````$P````````"9$```$@`!`/E4````````9```
-M``````"D$```$@`!`-J``````````0````````"O$```$@`!`.E>````````
-M<@````````"Z$```$@`!`#*]````````0@````````#%$```$@`!`-_U````
-M````;P````````#0$```$@`!``/I````````00````````#;$```$@`!`.N1
-M````````-0````````#F$```$@`!`$.!````````HP0```````#Q$```$@`!
-M`"]U````````R@(```````#\$```$@`!`&CI````````#@`````````'$0``
-M$@`!`$?'````````#P`````````2$0``$@`!`)MY`0``````S@`````````=
-M$0``$@`!`)GH````````-0`````````H$0``$@`!`-C;````````;0``````
-M```S$0``$@`!`/H*`0``````4`(````````^$0``$@`!`-@[`0``````&0``
-M``````!)$0``$@`!`"R(````````00````````!4$0``$@`!`._9````````
-M<`````````!?$0``$@`!`');````````!@````````!J$0``$@`!`"65````
-M````!P````````!U$0``$@`!`'I^````````,@````````"`$0``$@`!`/?G
-M````````"P````````"+$0``$@`!`!<H`0``````[@````````"6$0``$@`!
-M`-2B````````J0$```````"A$0``$@`!`*X]````````DP````````"Z$0``
-M$@`!`/$[`0``````,0``````````>GHP,#5B-3@T-@!Z>C`P,F1B,3%C`'IZ
-M,#)D8F8X-S4`>GHP,F1B8C%B,@!Z>C`R9&(R,#4S`'IZ,#`R9&)A-#(`>GHP
-M9F)B,64S9@!Z>C!B-SEE83DT`'IZ,#5B.&,V-6$`>GHP,#5B-#!A9`!Z>C`U
-M8CDT,F5D`'IZ,&0X9&,V,F,`>GHP,#$Y9C0W,`!Z>C`R9&0Y-#)D`'IZ,#)D
-M8F4W,V0`>GHP,#5B-CDR8@!Z>C!B-F0R,S(U`'IZ,#`U8C@U,V0`>GHP,#$V
-M9#DR90!Z>C!C9F(Q.#<U`'IZ,#`R9&(S,6,`>GHP,F1A8F)A8P!Z>C`R9&)C
-M.#4Q`'IZ,#`P8C9C-C@`>GHP,#!B-F)F.`!Z>C`P8C9C9C5E`'IZ,#$V93%D
-M9F0`>GHP8C9F-3!B.`!Z>C`V93!A-&9E`'IZ,#`V-V0R8C$`>GHP,#)D8F,V
-M,0!Z>C!B-F-A,S(U`'IZ,#`U8C9C9F0`>GHP,39E,&1F9`!Z>C`P,&(V9C8X
-M`&%T:%]H86Q?<')O8V5S<U]N;VES969L;V]R`'IZ,#`U8C0X860`>GHP,F1B
-M9C%B,@!Z>C`P-6(X.&-B`'IZ,#,S96,X8F8`>GHP9&(T,C5C-0!A=&A?:&%L
-M7V1M85]B96%C;VY?<F5S<&]N<V5?=&EM90!Z>C`P8C9F,38Q`'IZ,#9E,#!B
-M.&$`>GHP,F1B9F,Q9`!Z>C!D8S1E,SDP`'IZ,&1A9F5D.#8`>GHP,&(V93(W
-M80!Z>C`R9&)B86(R`'IZ,&(V9#%E9F8`>GHP,39D.3!D9`!Z>C`R9&)E.#4Q
-M`'IZ,#`U8C8T9F0`>GHP,#!B-F0U,@!Z>C!B-F,Y969F`'IZ,#$V93`P9&0`
-M>GHP,F1B9#@W-0!Z>C`R9&(S,6(R`'IZ,#!B-S`Y,C,`>GHP,&(V9#0U,`!Z
-M>C`P,&(V9#%D`'IZ,&(V8S(S,C4`>GHP,F1B9&%B,@!Z>C`P,#5B-C,R`'IZ
-M,#9D961D.3,`>GHP,#$V9&$U,`!Z>C`P,#8W9#,R`'IZ,#!B-F0Y,C,`>GHP
-M,#)D8C4Q8P!Z>C`Q-F1C8F9E`'IZ,#!B-S`Q-#4`>GHP,#$V9&8R8P!Z>C!B
-M-V9A9#-E`'IZ,#$V9#DY,C``>GHP,F1B,6)A8P!Z>C!D8S9E,SDP`'IZ,#5B
-M-S`Q93``>GHP,#!B-F(Q,`!Z>C!B-S`Y969F`'IZ,#$V9&8X.6(`871H7VAA
-M;%]A='1A8V@`>GHP-F4P9F,P9`!Z>C`Q-F1A8C)D`'IZ,#)D8C$S-60`>GHP
-M93`T-C@T8@!Z>C`Q-F4R.3%D`'IZ,#`P8C9F93@`>GHP,&-F8C-E,`!Z>C`P
-M,39D.30X`'IZ,#$V93(P.6(`>GHP8C<P,65F9@!Z>C`P,&(V8SED`'IZ,#`P
-M-6(U83(`>GHP,F1B,3<P80!A=&A?:&%L7V-O;7!U=&5T>'1I;64`>GHP,F1B
-M-6)A8P!Z>C`P-6(X,3-D`'IZ,#!B-F,Y,C,`>GHP8C9B-3!B.`!Z>C`P-6(W
-M9CED`'IZ,&(W,#%D,#(`>GHP-F1F9C0T80!Z>C`R9&(U-S8S`'IZ,#9E96%F
-M-C``>GHP93`P-V-A,0!Z>C`P,F1A9C8R`'IZ,&(X,V%D,V4`>GHP,#!B-F(Y
-M,`!Z>C`Q-F0Y969A`'IZ,#$V9&4P-3$`>GHP,#`U8C9B,@!Z>C`U8C=F,3$T
-M`'IZ,#1A93`S,68`>GHP,F1B9&1F9`!Z>C`P-30W9F5D`'IZ,#!B-F)F-64`
-M>GHP,&(W,3<W9`!Z>C`P8C<P9C-D`'IZ,#$V9#@Y,C``>GHP,F1B,6%B,@!Z
-M>C`P,#5B-C(R`'IZ,#`P8C9F-S@`>GHP8C8Y8C`W8P!A=&A?:&%L7V9R964`
-M>GHP-6(W.6(Q8@!Z>C`P8C<P-S-D`'IZ,#)D8F5B8F0`>GHP8C5E,S$U,@!Z
-M>C`Q-F1F8F8Q`&%T:%]H86Q?;6AZ,FEE964`>GHP,39E,3@Y8@!Z>C!D8S)A
-M-6,U`'IZ,#`R9&,V,&(`>GHP-F1F,&(X80!Z>C`R9&(S,S5D`'IZ,&(V8S4S
-M830`>GHP9C4T9#%B,`!Z>C!B-F9D,S8S`'IZ,&0Y9&,V,F,`>GHP-6(W-#%E
-M,`!Z>C`R9&$Y8F%C`'IZ,&1C,C%D,V$`>GHP,&(W,3<S9`!Z>C`Q-F0Y9#0Q
-M`'IZ,#`U8C@T9F0`>GHP,#5B.&%B9`!Z>C`P8C<P,3(S`'IZ,#`U8C8U,F(`
-M>GHP,F1B,S@W-0!Z>C`Q-F4S,#EB`'IZ,#`U8C8P8C(`>GHP,F1B,3@W-0!Z
-M>C`P,F1B.#0R`'IZ,#)D8C$W-C,`>GHP8C=D96$Y-`!Z>C`P8C<P,38Q`'IZ
-M,#$V9#=D-#$`>GHP,#$V8V0S,@!Z>C`V9&4P8CAA`'IZ,#9D.61D.3,`>GHP
-M9&(S960X-@!Z>C`P-6(T.&5D`'IZ,#`R9&,X,&(`>GHP,#)D8F,T,@!Z>C`R
-M9&)A.#4Q`'IZ,#)D8C,S960`>GHP,#5B.#!F9`!Z>C`P-6(W9C)E`'IZ,#)D
-M8F9D9F0`>GHP,39E-C0X80!Z>C`P,F1A9F8R`'IZ,#`U8C<W.60`>GHP,#!B
-M-F5E.`!Z>C`Q-F4T-#AA`'IZ,#!B-F8V8F,`>GHP,39D83DR,`!Z>C`U8C<X
-M,64P`'IZ,#`R9&-A,&(`>GHP,#5B-#1A9`!Z>C`V9&1F-#1A`'IZ,&9A8S!C
-M.6(`>GHP8C9F.65F9@!Z>C`P8C9C-F)C`&%T:%]H86Q?861D:71I;VYA;%]S
-M=V)A7V)A8VMO9F8`>GHP,#`R9&(Y,@!A=&A?:&%L7W9E<G-I;VX`>GHP,F1B
-M86,R90!Z>C`R9&(W.6%E`'IZ,#`Q-F4U,S(`>GHP8C9C9C`P.0!Z>C`P,39E
-M,3)C`'IZ,#`Q-F0Y930`>GHP,#`R9&%E80!Z>C`P-6(U8V(R`'IZ,#$V9&$R
-M-3$`>GHP-F8V868V,`!Z>C`V9&9D9#DS`&%T:%]H86Q?;6%L;&]C`'IZ,#`P
-M8C9D9#(`>GHP,F1D.3)A9`!Z>C`Q-F1B,C4Q`'IZ,&4Q,#=C83$`>GHP,&(V
-M8S<U90!Z>C`Q-F1D,#4Q`'IZ,#)D8F0Q8C(`>GHP,F1C,3<V,P!Z>C!B-CDP
-M9#9D`'IZ,#$V9&8P-3$`>GHP,#$V9#DU,`!Z>C`P8C<P-F)C`'IZ,#`Q-F0X
-M-S(`>GHP-F1E9C0T80!Z>C`U8CAC,F5D`'IZ,#9F8CDT-V(`>GHP96)B,64S
-M9@!Z>C!B-F8Y9#`R`'IZ,&0Q-&0Q8C``>GHP8C0X,#,Q90!Z>C`Q-F1B8F9E
-M`'IZ,#$V934T.&$`>GHP,#$V9#@U,`!Z>C`P,&(V9F8X`&%T:%]H86Q?;65M
-M8W!Y`'IZ,#)D8F-B8F0`>GHP,39D83!D9`!Z>C`R9&)B9&9D`'IZ,#)D8C(X
-M-3$`>GHP,F1B9&,Q9`!Z>C`V9&(P8V8R`'IZ,#$V96(Y860`>GHP,&(V8V5B
-M8P!Z>C!D.30X-&$Q`&%T:%]H86Q?<')O8F4`>GHP,39E83EA9`!Z>C!F9#1D
-M,6(P`'IZ,#)D8C,W-C,`871H7VAA;%]B=6EL9&]P=',`>GHP,F1A9C,U9`!Z
-M>C`V9&1D9#DS`'IZ,&1A9&,V,F,`>GHP,39D9C(U,0!Z>C`P,&(V8S$P`'IZ
-M,#$V9#DR-3$`>GHP,F1B,#@U,0!Z>C!B-S(Q865D`'IZ,#8W8V9C864`>GHP
-M,#!B-F-F.`!Z>C!C.31D,6(P`'IZ,#)D869A8C(`>GHP-6(Y,F%E9`!Z>C`P
-M-6(X8V-B`'IZ,&(V9#EE9F8`>GHP,F1B,3%B,@!Z>C`R9&)F9F(Q`'IZ,#)D
-M8F8W-C,`>GHP,#5B-CAF9`!Z>C`P-6(T-&5D`'IZ,&(W,3%A960`>GHP8C5E
-M,S$V,`!Z>C!D.#0X-&$Q`'IZ,#$V9#AB,F0`>GHP,39E,#@Y8@!Z>C`R9&)B
-M.#<U`'IZ,#)D864X-3$`>GHP8C@Q96$Y-`!Z>C`Q-F1E8S%F`'IZ,#!B-F9E
-M8F,`>GHP93@Y-#DP-P!Z>C`P8C9E83=A`'IZ,#,S93AF8F8`>GHP8V9A-3@W
-M-0!Z>C`R9&(Y.6%E`'IZ,#)D8CEA8C(`>GHP,#!B-F)E.`!Z>C!D938X,S=F
-M`'IZ,#$V9&%B9F4`>GHP8C<P.60P,@!Z>C`V-V0R-64R`'IZ,#$Y9C-A,#$`
-M>GHP-S`S.30W8@!A=&A?:&%L7VUE;7IE<F\`>GHP-F1F9F,P9`!Z>C!B-C<U
-M,&(X`'IZ,#$V93)D9F0`>GHP,#!B-F0R,@!Z>C`V9F5A9C8P`'IZ,&1C-&$U
-M8S4`>GHP,&(W,&8W9`!A=&A?:&%L7W-W7V)E86-O;E]R97-P;VYS95]T:6UE
-M`'IZ,#EF-C1B-F$`>GHP,#5B-C4W80!Z>C`V9C,Y-#=B`'IZ,#9D83!C9C(`
-M>GHP8C=B860S90!Z>C`P8C9F.38Q`'IZ,&(V.3<S8F,`>GHP,F1B9#,U9`!Z
-M>C`P-6(X.&9D`'IZ,#)D8F)C,60`>GHP,F1A9F1F9`!Z>C`V9#=D9#DS`&%T
-M:%]H86Q?9&5L87D`>GHP,F1B,61F9`!Z>C`V-V0R9C0Q`'IZ,#)D868X-S4`
-M>GHP8C=E9&4V9`!Z>C`Q-F0X9#0Q`'IZ,#`R9&%E.3(`>GHP8C=A9&4V9`!Z
-M>C`R9&)B,S5D`'IZ,#)D8C-D9F0`>GHP,F1B-3-E9`!Z>C`Q-F1C96%E`'IZ
-M,#`P8C9D83(`>GHP,#!B-F4R,@!Z>C`U8C@P,#0Q`'IZ,#`Q-F0X-#@`>GHP
-M,39D.6(R9`!Z>C`P,39E,#)C`'IZ,#!B-S`W-V0`>GHP,#5B-CDW80!Z>C`P
-M,39D864T`'IZ,#$V93$P.6(`>GHP,#5B-&$R9`!Z>C`Q-F1E,&1D`'IZ,#$V
-M9&8P9&0`>GHP9&8P-V-A,0!Z>C`R9&)D-S8S`'IZ,#`P8C9E-3(`>GHP-C=D
-M,&,T-P!Z>C`U8C9C-F1B`'IZ,&,S,35E8C4`>GHP9&(Q960X-@!Z>C`V9#0P
-M-F4P`'IZ,#$V93`R-3$`>GHP,#`R9&)B,@!Z>C`P,F1D.#9D`'IZ,#`Q-F4Q
-M-&0`>GHP,F1B-3EA90!Z>C`P-C=D,C(Q`'IZ,#$V9#@P9&0`>GHP,#5B.#DS
-M9`!Z>C`U8C@Q8C%B`'IZ,#)D8C$S960`>GHP,&(V9#$R,P!Z>C`P,&(V8V4X
-M`'IZ,#5B.&%A960`>GHP8C9E9#,V,P!Z>C`R9&%F,6(R`'IZ,#`P-6(U93(`
-M>GHP,S-E8F9B9@!Z>C`U8C8X-F1B`'IZ,#`P8C9E9C@`>GHP8C<Q.6%E9`!Z
-M>C`P-6(U.&(R`'IZ,#5B-V1B,6(`>GHP8C@R9&4V9`!Z>C`P,39D-S,R`'IZ
-M,#)D861A8C(`>GHP9C0U939E,P!A=&A?:&%L7VEN:71?8VAA;FYE;',`>GHP
-M,&(V9#9B8P!Z>C!C,31D,6(P`'IZ,#`P,F1B9#(`>GHP9&$T.#1A,0!Z>C`Q
-M-F4P8C@W`'IZ,#5B.3`R960`>GHP9&,R93,Y,`!Z>C!A-C!D,30U`'IZ,#)D
-M8F%B8F0`>GHP,#!B-F,Q9`!Z>C`U8CAE865D`'IZ,#`U8C=B.60`>GHP,#5B
-M-30T-@!Z>C`U8C8T-F1B`'IZ,#!B-F8Y,C,`>GHP9&0V.#,W9@!Z>C`Q-F4Q
-M,C4Q`'IZ,&1C-F$U8S4`>GHP,F1B,S<P80!Z>C`P,#5B-C<R`'IZ,#9D969C
-M,&0`>GHP,F1B9C,U9`!Z>C`P,&(V8S<X`'IZ,#`Q-F0X,S(`>GHP,F1B-3<P
-M80!Z>C`P-6(V9#=A`'IZ,#`R9&(R.3(`>GHP,#5B.3!C8@!Z>C!B-F8U,S8S
-M`'IZ,#`U8C5C-#8`>GHP-F0Y,&-F,@!Z>C`V9#AD9#DS`'IZ,#$V9&9B.#<`
-M>GHP,#$V9&$T.`!Z>C!B-C8S,6$X`'IZ,#`R9&(P.3(`871H7VAA;%]G971W
-M:7)E;&5S<VUO9&5S`'IZ,#$V93%B.#<`````!@`````````+`````P```#$`
-M````````6``````````+`````P```$0`````````@``````````+`````P``
-M`%8`````````Q0`````````+`````P```&D`````````TP`````````+````
-M`P```'T`````````XP`````````+`````P```)$`````````[``````````+
-M`````P```)X`````````]0`````````+`````P```*L`````````_@``````
-M```+`````P```+X`````````!P$````````+`````P```-$`````````SP$`
-M```````"````=P```/S_________V0$````````"````A0$``/S_________
-MXP$````````"````2````/S_________CP(````````"````-@$``/S_____
-M____,04````````"````O0```/S_________HP4````````"````O0```/S_
-M________2P8````````"````'P$``/S_________5`8````````+`````@``
-M````````````<@8````````"````'P$``/S_________>P8````````+````
-M`@``````````````(0<````````"````9P```/S_________/@<````````"
-M````9P```/S_________;0<````````+`````@````@`````````N0L`````
-M```"````_@```/S_________V`L````````"````'P$``/S_________\`L`
-M```````+`````@```"`!````````<@P````````"````'P$``/S_________
-M@`P````````+`````@```"`!````````[`P````````+`````@```"`!````
-M````=0T````````+`````@```#`!````````?@T````````+`````@```%`!
-M````````!1$````````"````S@```/S_________FA4````````"````(0$`
-M`/S_________W!@````````"````A````/S_________["$````````"````
-MS@```/S_________&"(````````"````(0$``/S_________I2(````````"
-M````(0$``/S_________+B,````````"````(0$``/S_________F",`````
-M```"````A````/S_________82T````````+`````@```)`!````````<RT`
-M```````+`````@```'`!````````=#P````````+````!````"`*````````
-MH#P````````+````!````&``````````"CT````````+````!````"`*````
-M````CCX````````+````!````"`*````````I3X````````+````!````"`*
-M````````\SX````````+````!````&``````````!S\````````+````!```
-M`'``````````1C\````````+````!````*`D````````5C\````````+````
-M!````*`D````````8S\````````"````YP```/S_________D#\````````+
-M````!````&``````````/$`````````+````!````&``````````5D``````
-M```+````!````&``````````KT`````````+````!````,`)````````X$``
-M```````+````!````,`)````````E$,````````+`````@```+`!````````
-MFT,````````+`````@```,@!````````2D0````````+````!``````;````
-M````>40````````+````!````&`4````````I40````````+````!````$`>
-M````````U$0````````+````!````&`A````````!$4````````+````!```
-M```D````````-$4````````+````!``````;````````9D8````````"````
-M(0$``/S_________SD<````````+`````@```,@!````````^4<````````+
-M`````0`````\````````M4D````````"````_@```/S_________BDH`````
-M```"````_@```/S_________U4H````````"````_@```/S_________LTP`
-M```````+````!````"`]````````-TT````````+````!````(`]````````
-M%4X````````"````S@```/S_________-DX````````+`````@```.`!````
-M````/DX````````"````YP```/S_________NTX````````"````/`$``/S_
-M________.T\````````"````,````/S_________<$\````````"````*P$`
-M`/S_________I$\````````"````*P$``/S_________T$\````````"````
-M*P$``/S_________(U`````````"````*P$``/S_________85`````````"
-M````*P$``/S_________&U$````````+````?```````````````;E,`````
-M```"````*P$``/S_________\%,````````"````A````/S_________(%0`
-M```````"````A````/S_________#E4````````"````,@```/S_________
-M'54````````"````*0$``/S_________5%4````````"````9`$``/S_____
-M____75H````````"````<````/S_________DUH````````"````YP```/S_
-M________K5H````````"````YP```/S_________REH````````+`````@``
-M``@6````````SUH````````"````YP```/S_________$%L````````"````
-M2P```/S_________J%L````````"````)0$``/S_________NUL````````"
-M````=0```/S_________S%P````````"````4`$``/S_________=5T`````
-M```"````YP```/S_________#E\````````"````)@```/S_________+U\`
-M```````"````7`$``/S_________<%\````````"````)@```/S_________
-MH5\````````"````)@```/S_________U%\````````"````7`$``/S_____
-M____)6`````````"````)@```/S_________KF`````````"````)@```/S_
-M________X6`````````"````7`$``/S_________.&$````````"````)@``
-M`/S_________:V$````````"````%P$``/S_________IF$````````"````
-M'````/S_________M&$````````"````.`$``/S_________%V(````````"
-M````-@$``/S_________-V(````````"````-@$``/S_________/6,`````
-M```+````\@``````````````2V,````````+````$@``````````````7&,`
-M```````"````*@$``/S_________LV,````````"````-@$``/S_________
-M6V8````````"````_@```/S_________JV8````````"````/`$``/S_____
-M____O6@````````"````MP```/S_________?VD````````+`````@```"`6
-M````````OFD````````"````A@$``/S_________"&L````````"````-@$`
-M`/S_________,FL````````"````2P```/S_________/6L````````"````
-ME0```/S_________8&L````````"````6````/S_________>&L````````"
-M````?P```/S_________J&L````````"````@`$``/S_________PVL`````
-M```"````#````/S_________WFL````````"````&0$``/S_________U6P`
-M```````"````^0```/S_________`VT````````"````-@$``/S_________
-M'VT````````"````-@$``/S_________2VT````````"````^0```/S_____
-M____G6T````````"````-@$``/S_________PFT````````"````-@$``/S_
-M________U&T````````"````^0```/S_________(&X````````"````_@``
-M`/S_________9VX````````"````-@$``/S_________AFX````````"````
-M-@$``/S_________J&X````````"````-@$``/S_________'V\````````"
-M````-@$``/S_________/F\````````"````-@$``/S_________:V\`````
-M```"````-@$``/S_________E6\````````"````2P```/S_________PV\`
-M```````"````E0```/S_________T6\````````"````-@$``/S_________
-MW&\````````"````E0```/S_________6G`````````"````-@$``/S_____
-M____<7`````````"````2P```/S_________VG,````````+`````@```'(;
-M````````2'4````````+`````@```(`;````````374````````"````YP``
-M`/S_________7G4````````+`````@```&`;````````9G4````````"````
-MYP```/S_________PG4````````"````,````/S_________Z74````````"
-M````,````/S_________=G<````````"````,````/S_________D7<`````
-M```"````,````/S_________J7<````````"````,````/S_________,7@`
-M```````"````,````/S_________MG@````````"````2P```/S_________
-MSG@````````"````-@$``/S_________UG@````````"````4P```/S_____
-M____0'D````````"````9P$``/S_________<WD````````"````%@$``/S_
-M_________'D````````"````(0$``/S_________-7H````````"````O@``
-M`/S_________F7T````````"````H@```/S_________K'T````````"````
-M4`$``/S_________VWT````````"````4`$``/S_________]WT````````"
-M````4`$``/S_________^WX````````"````-@$``/S_________,G\`````
-M```"````2P```/S_________.H$````````"````,````/S_________:8$`
-M```````"````S@```/S_________BH$````````+`````@```.`;````````
-MDH$````````"````YP```/S_________$((````````"````E0$``/S_____
-M____3X(````````"````-@$``/S_________W8(````````"````-@$``/S_
-M________%8,````````"````20$``/S_________=(,````````"````20$`
-M`/S_________KX,````````"````20$``/S_________'80````````+````
-M`@````@P````````980````````"````>0$``/S_________GH0````````"
-M````-@$``/S_________Q80````````"````-@$``/S__________80`````
-M```"````20$``/S_________*84````````+````TP``````````````.84`
-M```````"````@0$``/S_________7H4````````"````20$``/S_________
-MP(4````````"````9@$``/S_________\H4````````"````'@$``/S_____
-M____^H4````````"````A````/S_________Z(8````````"````-@$``/S_
-M________9(<````````"````W@```/S_________[H<````````"````20$`
-M`/S_________I8@````````"````,@```/S_________M(@````````"````
-M*0$``/S_________U(@````````"````C@$``/S_________9(X````````"
-M````S````/S_________BXX````````"````YP```/S_________I8X`````
-M```"````YP```/S_________PHX````````+`````@```"`P````````QXX`
-M```````"````YP```/S_________$H\````````"````2P```/S_________
-MU8\````````"````XP```/S_________\X\````````"````0@$``/S_____
-M____!I`````````"````.````/S_________Z)`````````"````!P$``/S_
-M________!I$````````+`````@```$`P````````,9$````````"````YP``
-M`/S_________NY(````````"````)@```/S_________V)(````````"````
-M7`$``/S_________&9,````````"````)@```/S_________2I,````````"
-M````)@```/S_________?9,````````"````7`$``/S_________SI,`````
-M```"````)@```/S_________5Y0````````"````)@```/S_________BI0`
-M```````"````7`$``/S_________X90````````"````)@```/S_________
-M2I4````````"````WP```/S_________<Y4````````"````%P$``/S_____
-M____HI4````````"````'````/S_________L)4````````"````.`$``/S_
-M________[)4````````"````-@$``/S_________#)8````````"````-@$`
-M`/S_________5)<````````+````NP``````````````79<````````+````
-M"0$`````````````9I<````````+````[@``````````````=Y<````````"
-M````*@$``/S_________NY<````````"````2P```/S_________6IH`````
-M```"````_@```/S_________9IL````````"````E0$``/S_________:IP`
-M```````"````,````/S_________?)P````````"````,````/S_________
-MBYP````````+````!````*Q'````````J9P````````+````!````+A'````
-M````U9P````````+````!````(!&````````#YT````````+`````@```&`P
-M````````0)T````````+`````@```(`X````````;YT````````+`````@``
-M`"`S````````=IT````````+`````@```"0S````````HY\````````"````
-M(@$``/S_________=J`````````"````-@$``/S_________H*`````````"
-M````2P```/S_________K:`````````"````'@```/S_________):$`````
-M```"````#@$``/S_________RZ$````````"````4@```/S_________^Z$`
-M```````"````FP```/S_________%J(````````"````U0```/S_________
-M,:(````````"````.0```/S_________GJ(````````"````5P$``/S_____
-M____QZ(````````"````-@$``/S_________\J(````````"````5P$``/S_
-M________A:,````````"````-@$``/S_________NJ,````````"````-@$`
-M`/S_________$*0````````"````-@$``/S_________/J0````````"````
-M-@$``/S_________4*0````````"````5P$``/S_________IJ0````````"
-M````_@```/S_________;Z4````````"````'@```/S_________?:4`````
-M```"````-@$``/S_________B*4````````"````'@```/S_________%J8`
-M```````"````-@$``/S_________+:8````````"````2P```/S_________
-M<:8````````"````B@```/S_________B:8````````+`````@```&0\````
-M````EJ8````````"````,````/S_________S:8````````"````,````/S_
-M________]:8````````"````,````/S_________]*<````````"````-@$`
-M`/S_________\J@````````"````<`$``/S_________'ZD````````+````
-M`@```*@]````````CJD````````+`````@```,`]````````FJD````````"
-M`````@```+P]````````LJD````````+`````@```,(]````````^:H`````
-M```+````!````!Q(````````&*L````````+````!````"A(````````-ZL`
-M```````+````!````-Q(````````V*L````````+````!````&1(````````
-M\:L````````"````,````/S_________$*P````````+````!````'!(````
-M````):P````````"````,````/S_________1ZP````````"````,````/S_
-M________7:P````````+````!````'Q(````````<JP````````"````,```
-M`/S_________D*P````````"````,````/S_________I*P````````+````
-M!````*Q(````````QZP````````+````!````.!'````````\ZX````````"
-M````WP```/S_________R;$````````"````%0```/S_________7;(`````
-M```+````!0``````````````8K(````````"````(0$``/S_________;K(`
-M```````+````!0```"`!````````<[(````````"````(0$``/S_________
-M>K(````````+````!0````@`````````@;(````````+````!0```(@`````
-M````I+(````````"````!0````(`````````J[(````````"````!0```/S_
-M________M+(````````"````!0```/[_________PK(````````"````!0``
-M``(`````````YK(````````"````!0````(`````````];(````````"````
-M!0````(`````````![,````````"````!0````(`````````*K,````````"
-M````!0````(`````````4+,````````"````!0````(`````````7K,`````
-M```"````!0````(`````````9[,````````"````!0````(`````````U+,`
-M```````+````!0```"`!````````%+0````````"````!0````(`````````
-MPK0````````+````!0```"`!````````X;0````````"````!0````(`````
-M````^[0````````+````!0```"`!`````````;4````````!````!0```!X!
-M````````++4````````+````!0```"(!````````,[4````````+````!0``
-M`"`!````````T;4````````+````!0```*`!````````$[8````````"````
-M%`$``/S_________:K<````````+`````@```/@]````````D+@````````+
-M`````@```.@]````````M[D````````"````;0```/S_________.[T`````
-M```"`````@```$`^````````5KT````````+`````@```$@^````````Z;X`
-M```````+`````@```$@^````````%[\````````+`````@```$`^````````
-M'K\````````+`````@```$@^````````;+\````````"`````@```#P^````
-M````B;\````````"`````@```#P^````````EK\````````+`````@```$`^
-M````````G;\````````+`````@```$@^````````O,`````````"````]```
-M`/S_________S\`````````"````!P$``/S_________!L$````````"````
-M!P$``/S_________,<$````````"````!P$``/S_________<<$````````"
-M````9P$``/S_________I,$````````"````%@$``/S_________/<(`````
-M```"````(0$``/S_________?<(````````"````8P```/S_________Z,4`
-M```````"````*0$``/S_________[L4````````"````,@```/S_________
-M_\4````````"````P````/S_________W<<````````"````=@$``/S_____
-M____Z\<````````"````-@$``/S_________Q\H````````"````,````/S_
-M________N<L````````"````LP```/S_________]\L````````+`````@``
-M`&`_````````_,L````````"````YP```/S_________K<P````````+````
-M`@```)13````````LLP````````"````YP```/S_________S\P````````+
-M`````@```)I3````````ULP````````+`````@```)M3````````W<P`````
-M```+`````@```)Q3````````+LT````````"````S@```/S_________6<T`
-M```````"````)P```/S_________;LT````````"````@@$``/S_________
-MPLT````````"````C`$``/S_________$\X````````"````&P```/S_____
-M____5<X````````"````1````/S_________:L\````````"````BP$``/S_
-M________Z,\````````"````BP$``/S_________#]`````````"````BP$`
-M`/S_________0M`````````"````BP$``/S_________A-`````````"````
-MBP$``/S_________[=`````````+`````@```(A3````````]-`````````+
-M`````@```(Y3````````/]$````````"````>0$``/S_________U-$`````
-M```"````-@$``/S_________W-$````````"````1````/S_________^]$`
-M```````"````-@$``/S_________*M(````````"````BP$``/S_________
-M3M(````````"````,`$``/S_________AM(````````"````Q0```/S_____
-M____I=(````````"````I@```/S_________QM(````````"````B0$``/S_
-M________T](````````"````;@$``/S_________\=(````````"````&P$`
-M`/S_________%-,````````"````BP$``/S_________@M,````````"````
-M@0```/S_________JM,````````"````<@```/S_________Q=,````````"
-M````10```/S_________U],````````"````@@$``/S_________YM,`````
-M```"````'@$``/S_________[M,````````"````A````/S_________W-0`
-M```````"````-@$``/S_________--D````````"````K````/S_________
-M2-D````````+`````0```"S9````````3]D````````+````C0$`````````
-M````LMD````````"````K````/S_________)]H````````"````,@```/S_
-M________-MH````````"````*0$``/S_________5MH````````"````D@``
-M`/S_________%-P````````"````2P```/S_________,]T````````"````
-MU@```/S_________X.$````````+`````@```*A3````````EN,````````"
-M````)@$``/S_________*.4````````"````)@$``/S_________6^4`````
-M```"````YP```/S_________=>4````````"````YP```/S_________FN4`
-M```````"````YP```/S_________M.4````````"````YP```/S_________
-M,^<````````+`````@```.!3````````7N<````````"````YP```/S_____
-M____F^D````````"````#P```/S_________S^D````````"````)@```/S_
-M________\.D````````"````7`$``/S_________,>H````````"````)@``
-M`/S_________8NH````````"````)@```/S_________E>H````````"````
-M7`$``/S_________YNH````````"````)@```/S_________;^L````````"
-M````)@```/S_________HNL````````"````7`$``/S_________^>L`````
-M```"````)@```/S_________C^P````````"````7`$``/S_________=>T`
-M```````"````)0```/S_________I>T````````"````%P```/S_________
-MP^\````````"````%P```/S_________L?`````````+`````@````!4````
-M````O?`````````"`````@```/Q3````````U?`````````+`````@````)4
-M````````!?$````````+`````@```#!4````````W?(````````"````B```
-M`/S_________^/(````````+`````@```"!5````````*/,````````"````
-M%P$``/S_________5_,````````+`````@```(!5````````D_0````````+
-M`````@```&!5````````FO0````````"````GP```/S_________P_0`````
-M```"````'````/S_________T?0````````"````.`$``/S_________#/4`
-M```````"````-@$``/S_________+/4````````"````-@$``/S_________
-MP?8````````+````+0``````````````[_8````````+````J@``````````
-M````^/8````````+````3`$``````````````?<````````+````T```````
-M````````"O<````````+````%@``````````````$_<````````+````60$`
-M````````````'/<````````+````UP``````````````)?<````````+````
-MX@``````````````-O<````````"````*@$``/S_________>_<````````"
-M````2P```/S_________I/<````````"````,0```/S_________L?<`````
-M```"````VP```/S_________S_<````````"````@P```/S_________+/H`
-M```````"````D````/S_________UOH````````"````@@$``/S_________
-M[OH````````"````_@```/S_________4?L````````"````R0```/S_____
-M____7OL````````"````VP```/S_________V_L````````"````#0```/S_
-M________2/P````````"````7@```/S_________4/P````````"````30``
-M`/S_________6_P````````"````C`$``/S_________*OT````````+````
-M`@```(!6````````7/T````````"````-@$``/S_________<OT````````+
-M`````@```.!8````````G_T````````+`````@```.18````````M?T`````
-M```"````-@$``/S_________\_T````````"````$@$``/S_________>_\`
-M```````"````6@```/S_________H/\````````"````00$``/S_________
-M)@`!```````"````E@```/S_________,0`!```````"````!@$``/S_____
-M____/@`!```````"````1`$``/S_________T@`!```````"````)0```/S_
-M________Z0$!```````"````L````/S_________"@(!```````"````-```
-M`/S_________%0(!```````"````70```/S_________]`(!```````"````
-M-@$``/S_________)@,!```````"````-@$``/S_________RP,!```````"
-M````3P```/S_________'@0!```````"````BP```/S_________A@0!````
-M```"````N````/S_________G00!```````"````2P```/S_________J00!
-M```````"````F@```/S_________-`4!```````"````%`$``/S_________
-MI08!```````"````0P```/S_________P08!```````"````+@```/S_____
-M____W08!```````"````1P```/S_________9P<!```````"````2@```/S_
-M________>`<!```````"````6@$``/S_________.@@!```````"````_@``
-M`/S_________5@@!```````"````EP$``/S_________J@@!```````"````
-M-@$``/S_________S0@!```````"````L````/S_________(0D!```````"
-M````-@$``/S_________+PD!```````"````6@```/S_________GPD!````
-M```"````E@```/S_________J@D!```````"````!@$``/S_________&@H!
-M```````"````2@```/S_________*PH!```````"````6@$``/S_________
-MV@H!```````"````@@$``/S_________/0L!```````"````@@$``/S_____
-M____]@P!```````"````-@$``/S_________$`T!```````"````-@$``/S_
-M________90T!```````"````_@```/S_________1@\!```````"````R0``
-M`/S_________.Q`!```````"````-@$``/S_________4Q`!```````"````
-M2P```/S_________>!`!```````"````@@$``/S_________.1$!```````"
-M````:````/S_________I!(!```````"````,````/S_________RA4!````
-M```"````#P```/S_________CQ<!```````"````PP```/S_________9Q\!
-M```````"````6@```/S_________E!\!```````"````(0$``/S_________
-MI1\!```````"````(0$``/S_________UA\!```````+`````@````!?````
-M````*2,!```````"````%0```/S_________NB0!```````"````%`$``/S_
-M________=B@!```````+`````@````I?````````*BD!```````"````YP``
-M`/S_________<BH!```````"````5@$``/S_________LRL!```````"````
-M5@$``/S_________22T!```````"`````@```*!@````````72T!```````+
-M`````@```*A@````````?2T!```````"`````@```"!?````````C2T!````
-M```+`````@```"A?````````&C`!```````+`````@```"!?````````(3`!
-M```````+`````@```*!@````````TC$!```````"````,````/S_________
-MM3(!```````"````6P```/S_________]S(!```````"````9P```/S_____
-M____(S,!```````"````6P```/S_________>C,!```````"````9P```/S_
-M________MC,!```````"````9P```/S_________JC0!```````"````U@``
-M`/S_________!S4!```````"````U@```/S_________5S4!```````"````
-M9P$``/S_________E#4!```````"````%@$``/S_________DS8!```````"
-M````(0$``/S_________WC8!```````"````5P```/S_________(SH!````
-M```"````*0$``/S_________*3H!```````"````,@```/S_________.#H!
-M```````"````P````/S_________4CP!```````"````EP$``/S_________
-M8#P!```````"````-@$``/S_________<#P!```````"````EP$``/S_____
-M____'#T!```````"````-@$``/S_________1CT!```````"````-@$``/S_
-M________43T!```````"````EP$``/S_________!$$!```````"````@P$`
-M`/S_________9$$!```````"````@P$``/S_________[T$!```````"````
-M@P$``/S_________)D(!```````"````(0$``/S_________"T,!```````"
-M````,0```/S_________04,!```````"````@P```/S_________ET,!````
-M```+`````@```!!B````````@D<!```````"````<@```/S_________BD<!
-M```````"````<@$``/S_________FD<!```````"````V@```/S_________
-MLT<!```````"````<@$``/S_________PT<!```````"````V@```/S_____
-M____ZT<!```````"````,0```/S_________\D<!```````"````<@$``/S_
-M________`D@!```````"````V@```/S_________ND@!```````"````@P$`
-M`/S_________7$D!```````"````GP```/S_________A4D!```````"````
-MGP```/S_________FTD!```````"````'P$``/S_________NTD!```````"
-M````GP```/S_________TTD!```````"````GP```/S_________6TH!````
-M```"````'P$``/S_________>TH!```````"````GP```/S__________DH!
-M```````"````GP```/S_________$$L!```````"````GP```/S_________
-M(DL!```````"````GP```/S_________-$L!```````"````GP```/S_____
-M____1DL!```````"````GP```/S_________3DL!```````"````<@$``/S_
-M________7DL!```````"````V@```/S_________DTL!```````"````GP``
-M`/S_________I$L!```````"````GP```/S_________NTL!```````"````
-MGP```/S_________S$L!```````"````GP```/S_________Y$L!```````"
-M````GP```/S_________]4L!```````"````GP```/S_________!TP!````
-M```"````GP```/S_________&4P!```````"````GP```/S_________*TP!
-M```````"````GP```/S_________/DP!```````"````<@$``/S_________
-M3DP!```````"````V@```/S_________A$P!```````"````<@$``/S_____
-M____E$P!```````"````V@```/S_________U$P!```````"````@P$``/S_
-M________0$X!```````"````GP```/S_________.4\!```````"````@P$`
-M`/S_________.E$!```````+`````@```&!B````````:E$!```````"````
-M-@$``/S_________@%$!```````+`````@```,!C````````C%$!```````+
-M`````@```,1C````````H%$!```````"````-@$``/S_________LU$!````
-M```+`````@```*!G````````X5$!```````"````-@$``/S_________$U(!
-M```````"````B@```/S_________*E(!```````+`````@```$1N````````
-M-U(!```````"````,````/S_________F5(!```````"````,````/S_____
-M____P5(!```````"````,````/S_________.E,!```````+`````@```(AO
-M````````FU4!```````+`````@````!F````````W%4!```````"````>```
-M`/S_________]U4!```````"````>````/S_________"E8!```````+````
-M`@````!F````````)U8!```````"````-@$``/S_________/58!```````+
-M`````@```*!J````````2%8!```````+`````@```*1J````````758!````
-M```"````-@$``/S_________;58!```````+`````@```+!J````````H58!
-M```````"````-@$``/S_________L58!```````+`````@```-!J````````
-MY58!```````"````-@$``/S_________^U8!```````+`````@````!K````
-M````3E<!```````"````>````/S_________;E<!```````"````>````/S_
-M________D%<!```````"````>````/S_________K5<!```````"````>```
-M`/S_________RE<!```````"````>````/S_________YU<!```````"````
-M>````/S_________^E<!```````+`````@````!K````````%U@!```````"
-M````-@$``/S_________,%@!```````+`````@```*!L````````:U@!````
-M```"````>````/S_________B%@!```````"````>````/S_________UE@!
-M```````"````>````/S_________\5@!```````"````>````/S_________
-M#ED!```````"````>````/S_________(5D!```````+`````@```*!L````
-M````/ED!```````"````-@$``/S_________W%H!```````"````(0$``/S_
-M________^5T!```````"````5@$``/S_________HU\!```````"````5@$`
-M`/S_________PE\!```````"````A````/S_________XU\!```````"````
-MA````/S_________`F`!```````+`````@```.!O````````#F`!```````"
-M`````@```-QO````````)F`!```````+`````@```.)O````````16`!````
-M```"````S@```/S_________96`!```````"````S@```/S_________BF`!
-M```````+`````0```*Q?`0``````E6`!```````+`````0```!Q1`0``````
-MH&`!```````+`````0```"E3`0``````JV`!```````+`````0```/M1`0``
-M````MF`!```````+`````0```&13`0``````P6`!```````+`````0```.]9
-M`0``````S&`!```````+`````0```/1?`0``````UV`!```````+`````0``
-M`/I?`0``````#F$!```````+`````@```"!P````````/F$!```````"````
-M-@$``/S_________5&$!```````+`````@```*!Q````````8&$!```````+
-M`````@```*1Q````````=&$!```````"````-@$``/S_________AV$!````
-M```+`````@```.!S````````M6$!```````"````-@$``/S_________IF(!
-M```````"````,````/S_________+6,!```````"````,````/S_________
-MCV,!```````"````,````/S_________Z&,!```````"````,````/S_____
-M____0F0!```````"````,````/S_________4V0!```````"````,````/S_
-M________P&0!```````+`````@```#A\````````FV8!```````+`````@``
-M`.1V````````NV8!```````+`````@```/!V````````Y&8!```````+````
-M`@```!!W````````#6<!```````+`````@```$!W````````1F<!```````"
-M````>````/S_________9F<!```````"````>````/S_________AV<!````
-M```"````>````/S_________MF<!```````"````>````/S_________VF<!
-M```````"````>````/S__________F<!```````"````>````/S_________
-M(F@!```````"````>````/S_________1F@!```````"````>````/S_____
-M____:F@!```````"````>````/S_________DF@!```````"````>````/S_
-M________Q6@!```````"````>````/S_________XF@!```````"````>```
-M`/S_________2&D!```````"````>````/S_________96D!```````"````
-M>````/S_________@FD!```````"````>````/S_________GVD!```````"
-M````>````/S_________SVD!```````"````>````/S_________[&D!````
-M```"````>````/S_________"6H!```````"````>````/S_________)FH!
-M```````"````>````/S_________0VH!```````"````>````/S_________
-M56H!```````+`````@````![````````GVH!```````"````>````/S_____
-M____P&H!```````"````>````/S_________"6L!```````"````>````/S_
-M________)&L!```````"````>````/S_________,VL!```````+`````@``
-M`.!V````````46L!```````"````-@$``/S_________:&L!```````+````
-M`@```/!V````````AFL!```````"````-@$``/S_________G6L!```````+
-M`````@```!!W````````NVL!```````"````-@$``/S_________TFL!````
-M```+`````@```$!W````````\&L!```````"````-@$``/S_________"FP!
-M```````+`````@````![````````*VP!```````"````-@$``/S_________
-M@VX!```````"````YP```/S_________EFX!```````"````YP```/S_____
-M____#&\!```````"````YP```/S_________'V\!```````"````YP```/S_
-M________<6\!```````"````YP```/S_________GV\!```````"````YP``
-M`/S_________LF\!```````"````YP```/S_________`'`!```````"````
-MYP```/S_________>78!```````"````A````/S_________FG8!```````"
-M````A````/S_________M7D!```````"````S@```/S_________U7D!````
-M```"````S@```/S_________!'H!```````+`````0```&-V`0``````#WH!
-M```````+`````0```/!@`0``````&GH!```````+`````0```*]D`0``````
-M)7H!```````+`````0```,]A`0``````,'H!```````+`````0```.5D`0``
-M````.WH!```````+`````0```%5L`0``````1GH!```````+`````0```"-Y
-M`0``````47H!```````+````(@``````````````BGH!```````+`````@``
-M`(!\````````NGH!```````"````-@$``/S_________T'H!```````+````
-M`@````!^````````W'H!```````+`````@````1^````````\'H!```````"
-M````-@$``/S_________!GL!```````+`````@```&""````````-'L!````
-M```"````-@$``/S_________)7P!```````"````,````/S_________K'P!
-M```````"````,````/S_________#GT!```````"````,````/S_________
-M9WT!```````"````,````/S_________P7T!```````"````,````/S_____
-M____TGT!```````"````,````/S_________LWX!```````+`````@```&2%
-M````````T7X!```````+`````@```'"%````````^7X!```````+`````@``
-M`)"%````````(7\!```````+`````@```,"%````````7'\!```````"````
-M>````/S_________>7\!```````"````>````/S_________B7\!```````+
-M`````@```&"(````````LG\!```````+`````@```&"%````````SW\!````
-M```"````-@$``/S_________YG\!```````+`````@```'"%````````!(`!
-M```````"````-@$``/S_________&X`!```````+`````@```)"%````````
-M.8`!```````"````-@$``/S_________4(`!```````+`````@```,"%````
-M````;H`!```````"````-@$``/S_________B(`!```````+`````@```&"(
-M````````IH`!```````"````-@$``/S_________X8`!```````+`````@``
-M`*B(````````<8D!```````"````A````/S_________DHD!```````"````
-MA````/S_________LXD!```````"````A````/S_________U(P!```````"
-M````S@```/S_________](P!```````"````S@```/S_________"HT!````
-M```"````S@```/S_________+XT!```````+`````0```%N)`0``````.HT!
-M```````+`````0```&QZ`0``````18T!```````+`````0```-"``0``````
-M4(T!```````+`````0```$Y[`0``````6XT!```````+`````0```"Y^`0``
-M````9HT!```````+`````0```-&'`0``````<8T!```````+`````0```$*,
-M`0``````?(T!```````+````(@``````````````LHT!```````+`````@``
-M``")````````XHT!```````"````-@$``/S_________^(T!```````+````
-M`@```."+````````!(X!```````+`````@```.2+````````&(X!```````"
-M````-@$``/S_________*XX!```````+`````@```."/````````68X!````
-M```"````-@$``/S_________2H\!```````"````,````/S_________T8\!
-M```````"````,````/S_________NI`!```````"````,````/S_________
-MRY`!```````"````,````/S_________89(!```````+`````@```.22````
-M````?Y(!```````+`````@```/"2````````IY(!```````+`````@```!"3
-M````````SY(!```````+`````@```$"3````````%9,!```````"````>```
-M`/S_________,I,!```````"````>````/S_________3Y,!```````"````
-M>````/S_________?9,!```````"````,````/S_________MY,!```````"
-M````>````/S_________U),!```````"````>````/S_________Y),!````
-M```+`````@```,"6````````$)0!```````+`````@```."2````````+90!
-M```````"````-@$``/S_________1)0!```````+`````@```/"2````````
-M8I0!```````"````-@$``/S_________>90!```````+`````@```!"3````
-M````EY0!```````"````-@$``/S_________KI0!```````+`````@```$"3
-M````````S)0!```````"````-@$``/S_________YI0!```````+`````@``
-M`,"6````````!Y4!```````"````-@$``/S_________0I4!```````+````
-M`@````B7````````UIT!```````"````A````/S_________]YT!```````"
-M````A````/S_________&)X!```````"````A````/S_________(*$!````
-M```"````S@```/S_________0*$!```````"````S@```/S_________5J$!
-M```````"````S@```/S_________>Z$!```````+`````0```,"=`0``````
-MAJ$!```````+`````0```)2-`0``````D:$!```````+`````0```#&5`0``
-M````G*$!```````+`````0```'..`0``````IZ$!```````+`````0```">1
-M`0``````LJ$!```````+`````0```#6<`0``````O:$!```````+`````0``
-M`(Z@`0``````R*$!```````+````(@``````````````"``````````!````
-M`0```'$'````````$``````````!`````0```(@(````````&``````````!
-M`````0```(@(````````(``````````!`````0```(@(````````*```````
-M```!`````0```'H'````````,``````````!`````0```(@(````````.```
-M```````!`````0```(8'````````0``````````!`````0```),'````````
-M2``````````!`````0```)<(````````4``````````!`````0```)H'````
-M````6``````````!`````0```*$'````````8``````````!`````0```-('
-M````````:``````````!`````0```+0'````````<``````````!`````0``
-M`,8'````````>``````````!`````0```,P'````````@``````````!````
-M`0```-H'````````B``````````!`````0```)<(````````D``````````!
-M`````0```)<(````````F``````````!`````0```!P(````````H```````
-M```!`````0```",(````````J``````````!`````0```(@(````````L```
-M```````!`````0```"H(````````N``````````!`````0```(@(````````
-MP``````````!`````0```#$(````````R``````````!`````0```#@(````
-M````T``````````!`````0```$((````````V``````````!`````0```)<(
-M````````X``````````!`````0```)<(````````Z``````````!`````0``
-M`(@(````````\``````````!`````0```)<(````````^``````````!````
-M`0```'L(``````````$````````!`````0```)<(````````"`$````````!
-M`````0```)<(````````$`$````````!`````0```)<(````````&`$`````
-M```!`````0```(X(````````&`(````````!````#0$`````````````(`(`
-M```````!````90``````````````*`(````````!````P0``````````````
-M,`(````````!````M```````````````.`(````````!````>P$`````````
-M````0`(````````!````U```````````````2`(````````!````50``````
-M````````4`(````````!````X```````````````6`(````````!````H0``
-M````````````8`(````````!````>`$`````````````:`(````````!````
-M2P$`````````````<`(````````!````O@``````````````>`(````````!
-M````/P``````````````@`(````````!````A0``````````````B`(`````
-M```!````6```````````````D`(````````!````(0``````````````F`(`
-M```````!````:0$`````````````H`(````````!````D@$`````````````
-MJ`(````````!````+P``````````````L`(````````!````C0``````````
-M````N`(````````!````2`$`````````````P`(````````!````*@``````
-M````````R`(````````!````/0``````````````T`(````````!````:0``
-M````````````V`(````````!````?P$`````````````X`(````````!````
-M>@$`````````````Z`(````````!````&@$`````````````\`(````````!
-M````M0``````````````^`(````````!````8`$```````````````,`````
-M```!````8P$`````````````"`,````````!````"@$`````````````$`,`
-M```````!````W0``````````````&`,````````!````/0$`````````````
-M(`,````````!````D0``````````````*`,````````!````<P$`````````
-M````,`,````````!````OP``````````````.`,````````!````MP``````
-M````````0`,````````!````A@``````````````2`,````````!````KP``
-M````````````4`,````````!````5@``````````````6`,````````!````
-MR```````````````8`,````````!````.0$`````````````:`,````````!
-M````#P$`````````````<`,````````!````I0``````````````>`,`````
-M```!````-`$`````````````@`,````````!````Z@``````````````B`,`
-M```````!````70$`````````````D`,````````!````30$`````````````
-MF`,````````!````+`$`````````````H`,````````!````,P``````````
-M````J`,````````!````M@``````````````L`,````````!````6P$`````
-M````````N`,````````!````'`$`````````````P`,````````!````)0$`
-M````````````R`,````````!````/@``````````````T`,````````!````
-M=0``````````````V`,````````!````10$`````````````X`,````````!
-M````Y0``````````````Z`,````````!````4```````````````\`,`````
-M```!````-P``````````````^`,````````!````C`````````````````0`
-M```````!````"@``````````````"`0````````!````]@``````````````
-M$`0````````!````/@$`````````````&`0````````!````-0$`````````
-M````(`0````````!````]P``````````````*`0````````!````@`$`````
-M````````,`0````````!````:@``````````````.`0````````!````#```
-M````````````0`0````````!````90$`````````````2`0````````!````
-MK0``````````````4`0````````!````$`$`````````````6`0````````!
-M````&0$`````````````8`0````````!````;P$`````````````:`0`````
-M```!````,P$`````````````<`0````````!````IP``````````````>`0`
-M```````!````1@``````````````@`0````````!````+@$`````````````
-MB`0````````!````%```````````````D`0````````!````O```````````
-M````F`0````````!````<```````````````H`0````````!````^0``````
-M````````J`0````````!````^P``````````````L`0````````!````4@$`
-M````````````N`0````````!````9`$`````````````P`0````````!````
-M?@$`````````````R`0````````!````$```````````````T`0````````!
-M````3P$`````````````V`0````````!````(P$`````````````X`0`````
-M```!````#`$`````````````Z`0````````!````H@``````````````\`0`
-M```````!````4`$`````````````^`0````````!`````0```"E4````````
-M``4````````!````D`$`````````````"`4````````!````*P$`````````
-M````&`4````````!````6P$`````````````(`4````````!````'`$`````
-M````````*`4````````!````)0$`````````````,`4````````!````/@``
-M````````````.`4````````!````=0``````````````0`4````````!````
-M`0```$94````````&!P````````!````1@$`````````````(!P````````!
-M````9@$`````````````*!P````````!````6`$`````````````,!P`````
-M```!````?0$`````````````.!P````````!````9```````````````0!P`
-M```````!````=@``````````````2!P````````!````E```````````````
-M4!P````````!````;0``````````````6!P````````!````#@``````````
-M````8!P````````!````-@``````````````:!P````````!````8@``````
-M````````<!P````````!````8P``````````````>!P````````!````.@``
-M````````````@!P````````!````;`$`````````````B!P````````!````
-M#@$`````````````D!P````````!````B`$`````````````F!P````````!
-M````@@``````````````H!P````````!````=@$`````````````J!P`````
-M```!`````P$`````````````L!P````````!````JP``````````````N!P`
-M```````!````*`$`````````````P!P````````!````(P``````````````
-MR!P````````!````"`$`````````````T!P````````!````&@``````````
-M````V!P````````!````:`$`````````````X!P````````!````Z```````
-M````````Z!P````````!````(```````````````\!P````````!````*P``
-M````````````^!P````````!````K@```````````````!T````````!````
-M?`$`````````````"!T````````!````:@$`````````````$!T````````!
-M````=P$`````````````&!T````````!````.@$`````````````(!T`````
-M```!````\P``````````````*!T````````!``````$`````````````,!T`
-M```````!````[P``````````````.!T````````!````$P$`````````````
-M0!T````````!````?@``````````````2!T````````!````F0``````````
-M````4!T````````!````=```````````````6!T````````!````2@$`````
-M````````8!T````````!````H```````````````:!T````````!````00``
-M````````````<!T````````!````.P$`````````````>!T````````!````
-M-P$`````````````@!T````````!````>@``````````````B!T````````!
-M````.P``````````````D!T````````!````3@$`````````````F!T`````
-M```!````W@``````````````H!T````````!````+P$`````````````J!T`
-M```````!````Y```````````````L!T````````!````Q```````````````
-MN!T````````!````XP``````````````P!T````````!````0@$`````````
-M````R!T````````!````SP``````````````T!T````````!````.```````
-M````````V!T````````!````80``````````````X!T````````!````V0``
-M````````````Z!T````````!````1P$`````````````\!T````````!````
-M50$`````````````^!T````````!````)P$``````````````!X````````!
-M````'0``````````````"!X````````!````7```````````````$!X`````
-M```!````,0$`````````````&!X````````!````D0$`````````````(!X`
-M```````!````20``````````````*!X````````!````FP``````````````
-M,!X````````!````80$`````````````.!X````````!````U0``````````
-M````0!X````````!````!0$`````````````2!X````````!````'P``````
-M````````4!X````````!````_```````````````6!X````````!````.0``
-M````````````8!X````````!`````0$`````````````:!X````````!````
-M[```````````````<!X````````!````C@``````````````>!X````````!
-M````*```````````````@!X````````!````40``````````````B!X`````
-M```!````DP``````````````D!X````````!````W```````````````F!X`
-M```````!````S```````````````H!X````````!````5P$`````````````
-MJ!X````````!````RP``````````````L!X````````!````4@$`````````
-M````N!X````````!````C@$`````````````P!X````````!````"0``````
-M````````R!X````````!````HP``````````````T!X````````!````<0``
-M````````````V!X````````!````:P``````````````X!X````````!````
-M\```````````````Z!X````````!````]```````````````\!X````````!
-M````!P$`````````````^!X````````!`````0```/>&`````````!\`````
-M```!````+0$`````````````"!\````````!````20$`````````````&!\`
-M```````!````Q```````````````(!\````````!````XP``````````````
-M*!\````````!````0@$`````````````,!\````````!````SP``````````
-M````.!\````````!````.```````````````0!\````````!`````0```"^'
-M````````^#T````````!`````0```&ZW`````````#X````````!`````0``
-M`&ZW````````"#X````````!`````0```)6W````````$#X````````!````
-M`0```)6W````````&#X````````!`````0```+RW````````(#X````````!
-M`````0```+RW````````*#X````````!`````0```..W````````,#X`````
-M```!`````0```..W````````F#\````````!````6P``````````````H#\`
-M```````!````@0``````````````J#\````````!````=`$`````````````
-ML#\````````!````;```````````````N#\````````!````10``````````
-M````P#\````````!````V```````````````R#\````````!````N0``````
-M````````T#\````````!````'0$`````````````V#\````````!````K```
-M````````````X#\````````!````5```````````````Z#\````````!````
-MG@``````````````\#\````````!````5P``````````````^#\````````!
-M````!`$``````````````$`````````!````7P$`````````````"$``````
-M```!````BP``````````````$$`````````!````_P``````````````&$``
-M```````!````Y@``````````````($`````````!````EP$`````````````
-M*$`````````!````C0$`````````````,$`````````!````N@``````````
-M````.$`````````!````?0``````````````0$`````````!````)`$`````
-M````````2$`````````!````*0``````````````4$`````````!````7@$`
-M````````````6$`````````!````4P$`````````````8$`````````!````
-MAP``````````````:$`````````!````8@$`````````````<$`````````!
-M````7P``````````````>$`````````!````0`$`````````````@$``````
-M```!`````@$`````````````B$`````````!````_0``````````````D$``
-M```````!````$P``````````````F$`````````!````;0$`````````````
-MH$`````````!````>P``````````````J$`````````!````X0``````````
-M````L$`````````!````<@$`````````````N$`````````!````V@``````
-M````````P$`````````!````EP``````````````R$`````````!````,@$`
-M````````````T$`````````!````^@``````````````V$`````````!````
-M$0``````````````X$`````````!````G0``````````````Z$`````````!
-M````"P``````````````\$`````````!````F```````````````^$``````
-M```!````/P$``````````````$$````````!````L0``````````````"$$`
-M```````!````Z0``````````````$$$````````!````0```````````````
-M&$$````````!````(`$`````````````($$````````!````I```````````
-M````*$$````````!````L@``````````````,$$````````!````&`$`````
-M````````.$$````````!````3@``````````````0$$````````!````0P$`
-M````````````2$$````````!````40$`````````````4$$````````!````
-M%0$`````````````6$$````````!````DP$`````````````8$$````````!
-M````2@``````````````:$$````````!````QP``````````````<$$`````
-M```!````J0``````````````>$$````````!````@P$`````````````@$$`
-M```````!````30``````````````B$$````````!````CP``````````````
-MD$$````````!````AP$`````````````F$$````````!````J```````````
-M````H$$````````!````S0``````````````J$$````````!````0P``````
-M````````L$$````````!````3```````````````N$$````````!````+@``
-M````````````P$$````````!````0@``````````````R$$````````!````
-M/```````````````T$$````````!````ZP``````````````V$$````````!
-M````1P``````````````X$$````````!````@```````````````Z$$`````
-M```!````-0``````````````\$$````````!````-```````````````^$$`
-M```````!````&0```````````````$(````````!````<P``````````````
-M"$(````````!````^```````````````$$(````````!````;@``````````
-M````&$(````````!````)@$`````````````($(````````!````@@$`````
-M````````*$(````````!````T0``````````````,$(````````!````4@$`
-M````````````.$(````````!````D@``````````````0$(````````!````
-MCP$`````````````2$(````````!````$0$`````````````4$(````````!
-M````T@``````````````6$(````````!````)```````````````8$(`````
-M```!````=0$`````````````:$(````````!````;P``````````````<$(`
-M```````!````U@``````````````>$(````````!````Q@``````````````
-M@$(````````!````[0``````````````B$(````````!````BP$`````````
-M````F$(````````!````&`$`````````````H$(````````!````3@``````
-M````````J$(````````!````0P$`````````````L$(````````!````40$`
-M````````````N$(````````!````%0$`````````````P$(````````!````
-ME`$`````````````T$(````````!`````0```,7+````````J%,````````!
-M`````0```"/B````````L%,````````!`````0```.3A````````N%,`````
-M```!`````0```.SA````````P%,````````!`````0```%CB````````R%,`
-M```````!`````0```/KA````````T%,````````!`````0```%#B````````
-M,%0````````!`````0```"+S````````.%0````````!`````0````GQ````
-M````0%0````````!`````0```#WQ````````2%0````````!`````0```%WQ
-M````````4%0````````!`````0```"+S````````6%0````````!`````0``
-M`+/Q````````8%0````````!`````0```"+S````````:%0````````!````
-M`0```"+S````````<%0````````!`````0```"+S````````>%0````````!
-M`````0```"+S````````@%0````````!`````0```"+S````````B%0`````
-M```!`````0```-OQ````````D%0````````!`````0```"+S````````F%0`
-M```````!`````0```"+S````````H%0````````!`````0```"+S````````
-MJ%0````````!`````0```"+S````````L%0````````!`````0```.;Q````
-M````N%0````````!`````0````7R````````P%0````````!`````0```"+S
-M````````R%0````````!`````0```$#R````````T%0````````!`````0``
-M`&+R````````V%0````````!`````0```"+S````````X%0````````!````
-M`0```(7Q````````Z%0````````!`````0```"+S````````\%0````````!
-M`````0```"+S````````^%0````````!`````0```"+S`````````%4`````
-M```!`````0```)CR````````"%4````````!`````0```*/R````````$%4`
-M```````!`````0```"+S````````&%4````````!`````0```+/R````````
-M(%4````````!`````0```!OS````````*%4````````!`````0```!OS````
-M````,%4````````!`````0```/SR````````.%4````````!`````0````+S
-M````````0%4````````!`````0````CS````````2%4````````!`````0``
-M``[S````````4%4````````!`````0```!3S````````@%4````````!````
-M`0```,+T````````B%4````````!`````0```,+T````````D%4````````!
-M`````0```%OS````````F%4````````!`````0```'WS````````H%4`````
-M```!`````0```,+T````````J%4````````!`````0```+CS````````L%4`
-M```````!`````0```,+T````````N%4````````!`````0```,+T````````
-MP%4````````!`````0```,+T````````R%4````````!`````0```,+T````
-M````T%4````````!`````0```,+T````````V%4````````!`````0```.+S
-M````````X%4````````!`````0```,+T````````Z%4````````!`````0``
-M`,+T````````\%4````````!`````0```,+T````````^%4````````!````
-M`0```,+T`````````%8````````!`````0```/?S````````"%8````````!
-M`````0```,+T````````$%8````````!`````0```,+T````````&%8`````
-M```!`````0````KT````````(%8````````!`````0```*#T````````*%8`
-M```````!`````0```,+T````````,%8````````!`````0```,+T````````
-M.%8````````!`````0```,+T````````0%8````````!`````0```,+T````
-M````2%8````````!`````0```,+T````````4%8````````!`````0```"ST
-M````````6%8````````!`````0```"ST````````8%8````````!`````0``
-M`,+T````````:%8````````!`````0```(3T````````$&(````````!````
-M`0````U(`0``````&&(````````!`````0```)M#`0``````(&(````````!
-M`````0```')$`0``````*&(````````!`````0````9&`0``````,&(`````
-M```!`````0```&1&`0``````.&(````````!`````0```-M&`0``````0&(`
-M```````!`````0```'9'`0``````B&\````````!`````0```#Y3`0``````
-MD&\````````!`````0```$)3`0``````F&\````````!`````0```$=3`0``
-M````H&\````````!`````0```$Q3`0``````J&\````````!`````0```%Y3
-M`0``````L&\````````!`````0```%Y3`0``````N&\````````!`````0``
-M`%%3`0``````P&\````````!`````0```%93`0``````.'P````````!````
-M`0```-]D`0``````0'P````````!`````0```,1D`0``````2'P````````!
-M`````0```,AD`0``````4'P````````!`````0```,UD`0``````6'P`````
-M```!`````0```-]D`0``````8'P````````!`````0```-]D`0``````:'P`
-M```````!`````0```-)D`0``````<'P````````!`````0```-=D`0``````
-MJ(@````````!`````0```/V``0``````L(@````````!`````0```.6``0``
-M````N(@````````!`````0```.F``0``````P(@````````!`````0```.Z`
-M`0``````R(@````````!`````0```/V``0``````T(@````````!`````0``
-M`/V``0``````V(@````````!`````0```/.``0``````X(@````````!````
-M`0```/B``0``````")<````````!`````0```&&5`0``````$)<````````!
-M`````0```$:5`0``````&)<````````!`````0```$J5`0``````()<`````
-M```!`````0```$^5`0``````*)<````````!`````0```&&5`0``````,)<`
-M```````!`````0```&&5`0``````.)<````````!`````0```%25`0``````
-M0)<````````!`````0```%F5`0``````(``````````!`````P``````````
-M````*``````````!`````P````<`````````,``````````!`````P````X`
-M````````.``````````!`````P```!4`````````0``````````!`````P``
-M`!P`````````2``````````!`````P```",`````````4``````````!````
-M`P```"H`````````(``````````!`````0``````````````.``````````!
-M`````0```!8!````````6``````````!`````0```$,!````````>```````
-M```!`````0```%`"````````D``````````!`````0```%P"````````R```
-M```````!`````0```*T"````````X``````````!`````0```,X"````````
-M^``````````!`````0```*,$````````$`$````````!`````0```/<$````
-M````,`$````````!`````0```#L&````````4`$````````!`````0```&(&
-M````````<`$````````!`````0```*8&````````J`$````````!`````0``
-M`%@'````````P`$````````!`````0```)T(````````V`$````````!````
-M`0````P)````````^`$````````!`````0```'`)````````&`(````````!
-M`````0````0*````````,`(````````!`````0```#@+````````2`(`````
-M```!`````0```*`+````````<`(````````!`````0```!(,````````R`(`
-M```````!`````0```&@-````````Z`(````````!`````0```-0-````````
-M``,````````!`````0```!@.````````&`,````````!`````0```#T.````
-M````2`,````````!`````0```-L0````````<`,````````!`````0```+\1
-M````````D`,````````!`````0```"(4````````T`,````````!`````0``
-M`*H8````````^`,````````!`````0```.X8````````$`0````````!````
-M`0```%<9````````4`0````````!`````0```'<?````````<`0````````!
-M`````0```%,@````````L`0````````!`````0```+TA````````\`0`````
-M```!`````0```*XC````````,`4````````!`````0```-4F````````<`4`
-M```````!`````0```"HI````````L`4````````!`````0```#DM````````
-MZ`4````````!`````0```&@[````````"`8````````!`````0```.0[````
-M````0`8````````!`````0`````\````````6`8````````!`````0```"@\
-M````````<`8````````!`````0```#4\````````B`8````````!`````0``
-M`%<\````````J`8````````!`````0```,(\````````R`8````````!````
-M`0```#<]````````\`8````````!`````0```*X]````````&`<````````!
-M`````0```$$^````````.`<````````!`````0```(0^````````4`<`````
-M```!`````0```+H^````````>`<````````!`````0```"T_````````F`<`
-M```````!`````0```'\_````````L`<````````!`````0```+<_````````
-M\`<````````!`````0```')!````````"`@````````!`````0```)]!````
-M````(`@````````!`````0```,]!````````4`@````````!`````0```/A(
-M````````<`@````````!`````0```+%)````````D`@````````!`````0``
-M`-Q)````````N`@````````!`````0```-!*````````V`@````````!````
-M`0```/5*````````&`D````````!`````0```'Q+````````.`D````````!
-M`````0```!!,````````6`D````````!`````0```(=,````````B`D`````
-M```!`````0````M-````````N`D````````!`````0```(]-````````\`D`
-M```````!`````0```.Q-````````,`H````````!`````0```!M4````````
-M4`H````````!`````0```"E4````````:`H````````!`````0```$94````
-M````@`H````````!`````0```$Q4````````L`H````````!`````0```+A4
-M````````R`H````````!`````0```/E4````````Z`H````````!`````0``
-M`%U5``````````L````````!`````0```)15````````,`L````````!````
-M`0```(!6````````2`L````````!`````0```)-6````````8`L````````!
-M`````0```.Y6````````>`L````````!`````0```/56````````J`L`````
-M```!`````0```'Q7````````P`L````````!`````0```()7````````V`L`
-M```````!`````0```+!7````````\`L````````!`````0```$E8````````
-M"`P````````!`````0```-!8````````2`P````````!`````0```'Q:````
-M````:`P````````!`````0```)Q:````````B`P````````!`````0```+M:
-M````````J`P````````!`````0```-A:````````P`P````````!`````0``
-M`-Y:````````X`P````````!`````0```$%;````````^`P````````!````
-M`0```');````````$`T````````!`````0```'A;````````.`T````````!
-M`````0```-);````````4`T````````!`````0```/];````````:`T`````
-M```!`````0```"-<````````@`T````````!`````0```$]<````````F`T`
-M```````!`````0```&Y<````````N`T````````!`````0```-5<````````
-MT`T````````!`````0````A=````````Z`T````````!`````0```"!=````
-M``````X````````!`````0```$Y=````````&`X````````!`````0```%1=
-M````````,`X````````!`````0```%U=````````6`X````````!`````0``
-M``E>````````<`X````````!`````0```#%>````````B`X````````!````
-M`0```#Q>````````H`X````````!`````0```%)>````````N`X````````!
-M`````0```(=>````````T`X````````!`````0```*A>````````Z`X`````
-M```!`````0```.E>````````$`\````````!`````0```%M?````````,`\`
-M```````!`````0```'E?````````6`\````````!`````0```!!@````````
-M>`\````````!`````0```"Y@````````D`\````````!`````0```#Q@````
-M````J`\````````!`````0```(9@````````T`\````````!`````0```"!A
-M````````\`\````````!`````0```$%A````````"!`````````!`````0``
-M`$=A````````(!`````````!`````0```$AA````````.!`````````!````
-M`0```$YA````````4!`````````!`````0```$]A````````:!`````````!
-M`````0```%!A````````B!`````````!`````0```'1A````````J!``````
-M```!`````0```*]A````````X!`````````!`````0```,!A````````^!``
-M```````!`````0```.]A````````(!$````````!`````0```()B````````
-M.!$````````!`````0```+%B````````8!$````````!`````0```"!C````
-M````D!$````````!`````0```#1C````````R!$````````!`````0```&AC
-M````````X!$````````!`````0```'!C````````^!$````````!`````0``
-M`'AC````````$!(````````!`````0```(1C````````.!(````````!````
-M`0```,]C````````4!(````````!`````0```.-C````````:!(````````!
-M`````0```/=C````````@!(````````!`````0````QD````````F!(`````
-M```!`````0```%YD````````L!(````````!`````0```+!D````````R!(`
-M```````!`````0```+MD````````X!(````````!`````0```-=D````````
-M^!(````````!`````0```!)E````````*!,````````!`````0```#!F````
-M````:!,````````!`````0```"9L````````@!,````````!`````0```)IL
-M````````H!,````````!`````0```*YL````````P!,````````!`````0``
-M`,9L````````X!,````````!`````0```"QM`````````!0````````!````
-M`0````9N````````0!0````````!`````0```"EP````````:!0````````!
-M`````0```)UP````````@!0````````!`````0```$IQ````````H!0`````
-M```!`````0```"]R````````N!0````````!`````0```$=R````````^!0`
-M```````!`````0```"]U````````*!4````````!`````0```/EW````````
-M2!4````````!`````0```&UX````````8!4````````!`````0```(EX````
-M````B!4````````!`````0````]Y````````H!4````````!`````0```!5Y
-M````````T!4````````!`````0```!QY````````\!4````````!`````0``
-M`$EY````````$!8````````!`````0```'QY````````.!8````````!````
-M`0```%EZ````````4!8````````!`````0```+=Z````````:!8````````!
-M`````0```!=]````````@!8````````!`````0```$!]````````F!8`````
-M```!`````0```(%]````````P!8````````!`````0```!-^````````V!8`
-M```````!`````0```'I^````````\!8````````!`````0```*Q^````````
-M&!<````````!`````0```$1_````````,!<````````!`````0```/-_````
-M````2!<````````!`````0```/E_````````8!<````````!`````0````&`
-M````````>!<````````!`````0```$N`````````D!<````````!`````0``
-M`-J`````````P!<````````!`````0```-R`````````\!<````````!````
-M`0```.B`````````$!@````````!`````0```$.!````````4!@````````!
-M`````0```.:%````````<!@````````!`````0````"&````````D!@`````
-M```!`````0```/>&````````J!@````````!`````0```"^'````````P!@`
-M```````!`````0```#6'````````"!D````````!`````0```"R(````````
-M(!D````````!`````0```&V(````````0!D````````!`````0```-V(````
-M````6!D````````!`````0```!2)````````B!D````````!`````0````2*
-M````````H!D````````!`````0```!>*````````N!D````````!`````0``
-M`,.*````````T!D````````!`````0```,J*`````````!H````````!````
-M`0```&B+````````&!H````````!`````0```&Z+````````,!H````````!
-M`````0```)R+````````2!H````````!`````0```#6,````````8!H`````
-M```!`````0```+R,````````J!H````````!`````0```'2.````````R!H`
-M```````!`````0```)2.````````Z!H````````!`````0```+..````````
-M"!L````````!`````0```-".````````(!L````````!`````0```-:.````
-M````0!L````````!`````0```$./````````6!L````````!`````0```'2/
-M````````<!L````````!`````0```*6/````````F!L````````!`````0``
-M`!V0````````L!L````````!`````0```#^0````````R!L````````!````
-M`0```&.0````````X!L````````!`````0```(^0````````^!L````````!
-M`````0```*Z0````````&!P````````!`````0```/&0````````,!P`````
-M```!`````0```!&1````````4!P````````!`````0```**1````````:!P`
-M```````!`````0```,J1````````@!P````````!`````0```-61````````
-MF!P````````!`````0```.N1````````L!P````````!`````0```""2````
-M````R!P````````!`````0```%62````````X!P````````!`````0```):2
-M````````"!T````````!`````0````23````````*!T````````!`````0``
-M`"*3````````4!T````````!`````0```+F3````````<!T````````!````
-M`0```->3````````B!T````````!`````0```.63````````H!T````````!
-M`````0```"^4````````R!T````````!`````0```,F4````````Z!T`````
-M```!`````0```.J4`````````!X````````!`````0```/"4````````&!X`
-M```````!`````0```/&4````````,!X````````!`````0```/>4````````
-M2!X````````!`````0```/B4````````8!X````````!`````0```/F4````
-M````>!X````````!`````0````F5````````D!X````````!`````0```!>5
-M````````J!X````````!`````0```"65````````P!X````````!`````0``
-M`"R5````````X!X````````!`````0```%.5`````````!\````````!````
-M`0```'R5````````(!\````````!`````0```*N5````````6!\````````!
-M`````0```,25````````@!\````````!`````0```%>6````````F!\`````
-M```!`````0```(:6````````L!\````````!`````0```+66````````V!\`
-M```````!`````0```"27````````""`````````!`````0```#B7````````
-M0"`````````!`````0```("7````````6"`````````!`````0```(B7````
-M````<"`````````!`````0```)"7````````B"`````````!`````0```)R7
-M````````J"`````````!`````0```,R7````````P"`````````!`````0``
-M`."7````````V"`````````!`````0```/27````````\"`````````!````
-M`0````F8````````""$````````!`````0```%N8````````("$````````!
-M`````0```*V8````````."$````````!`````0```+B8````````4"$`````
-M```!`````0```,.8````````:"$````````!`````0```/Z8````````F"$`
-M```````!`````0```-R9````````V"$````````!`````0```'RB````````
-M^"$````````!`````0```(^B````````&"(````````!`````0```-2B````
-M````."(````````!`````0```'VD````````8"(````````!`````0```."E
-M````````B"(````````!`````0```%FF````````N"(````````!`````0``
-M`%JG````````T"(````````!`````0```':G````````^"(````````!````
-M`0```!NH````````$",````````!`````0```&JH````````,",````````!
-M`````0```,^H````````6",````````!`````0```(:I````````<",`````
-M```!`````0```,NI````````L",````````!`````0```!&M````````R",`
-M```````!`````0```""N`````````"0````````!`````0```(RP````````
-M&"0````````!`````0```*ZP````````6"0````````!`````0```"ZR````
-M````F"0````````!`````0```("U````````V"0````````!`````0```-NY
-M`````````"4````````!`````0```$V[````````&"4````````!`````0``
-M`*V[````````."4````````!`````0```%*\````````4"4````````!````
-M`0```.^\````````<"4````````!`````0```#*]````````B"4````````!
-M`````0```'2]````````H"4````````!`````0```.N]````````N"4`````
-M```!`````0```!&^````````X"4````````!`````0```+J^````````^"4`
-M```````!`````0```-*^````````$"8````````!`````0```.B_````````
-M*"8````````!`````0```"K`````````0"8````````!`````0```)#`````
-M````>"8````````!`````0```*3`````````H"8````````!`````0```$W!
-M````````P"8````````!`````0```'K!````````X"8````````!`````0``
-M`*W!````````""<````````!`````0```*'"````````("<````````!````
-M`0```!'#````````0"<````````!`````0```(+#````````8"<````````!
-M`````0```$?'````````>"<````````!`````0```%;'````````D"<`````
-M```!`````0```&K'````````J"<````````!`````0```(/'````````P"<`
-M```````!`````0```+3'````````Z"<````````!`````0```!C(````````
-M`"@````````!`````0```*C(````````&"@````````!`````0```*[(````
-M````,"@````````!`````0```+;(````````2"@````````!`````0````#)
-M````````8"@````````!`````0```+;)````````D"@````````!`````0``
-M`+C)````````P"@````````!`````0```.C)````````V"@````````!````
-M`0```'7*````````^"@````````!`````0```-#*````````&"D````````!
-M`````0```,7+````````,"D````````!`````0```-?+````````:"D`````
-M```!`````0```,?,````````@"D````````!`````0````S-````````P"D`
-M```````!`````0```*73````````X"D````````!`````0```/33````````
-M`"H````````!`````0```.O4````````&"H````````!`````0```"S5````
-M````2"H````````!`````0```"S9````````:"H````````!`````0```$+9
-M````````F"H````````!`````0```&#9````````N"H````````!`````0``
-M`._9````````V"H````````!`````0```%_:````````\"H````````!````
-M`0```);:````````("L````````!`````0```-C;````````6"L````````!
-M`````0```$C<````````<"L````````!`````0```&K<````````B"L`````
-M```!`````0```([<````````H"L````````!`````0```+K<````````N"L`
-M```````!`````0```-G<````````\"L````````!`````0```#S=````````
-M""P````````!`````0```%#=````````("P````````!`````0```,/>````
-M````."P````````!`````0```,K>````````:"P````````!`````0```-C?
-M````````@"P````````!`````0```.#?````````F"P````````!`````0``
-M`!'@````````L"P````````!`````0````?A````````R"P````````!````
-M`0```)+A````````("T````````!`````0```$3E````````0"T````````!
-M`````0```&3E````````8"T````````!`````0```(/E````````@"T`````
-M```!`````0```*/E````````H"T````````!`````0```!'F````````N"T`
-M```````!`````0```$+F````````T"T````````!`````0```)OF````````
-M^"T````````!`````0```![G````````$"X````````!`````0```#[G````
-M````,"X````````!`````0```,_G````````2"X````````!`````0```/?G
-M````````8"X````````!`````0````+H````````>"X````````!`````0``
-M`"+H````````D"X````````!`````0```)GH````````J"X````````!````
-M`0```,[H````````P"X````````!`````0````/I````````V"X````````!
-M`````0```$3I````````\"X````````!`````0```$KI````````""\`````
-M```!`````0```%KI````````("\````````!`````0```&CI````````."\`
-M```````!`````0```';I````````4"\````````!`````0```'WI````````
-M<"\````````!`````0```*3I````````B"\````````!`````0```*KI````
-M````L"\````````!`````0```!SJ````````T"\````````!`````0```#KJ
-M````````^"\````````!`````0```-'J````````&#`````````!`````0``
-M`._J````````,#`````````!`````0```/WJ````````2#`````````!````
-M`0```$?K````````<#`````````!`````0```.'K````````D#`````````!
-M`````0````+L````````J#`````````!`````0```$/L````````R#``````
-M```!`````0```&KM````````Z#`````````!`````0```'[M`````````#$`
-M```````!`````0```*#M````````(#$````````!`````0```+[O````````
-M0#$````````!`````0```*GP````````6#$````````!`````0```-KP````
-M````>#$````````!`````0```#OS````````F#$````````!`````0```,ST
-M````````T#$````````!`````0```.3T````````^#$````````!`````0``
-M`'?U````````$#(````````!`````0```*OU````````*#(````````!````
-M`0```-_U````````4#(````````!`````0```$[V````````@#(````````!
-M`````0```&3V````````N#(````````!`````0```$#W````````T#(`````
-M```!`````0```$CW````````Z#(````````!`````0```%#W`````````#,`
-M```````!`````0```%SW````````(#,````````!`````0```(SW````````
-M0#,````````!`````0```+?W````````8#,````````!`````0```-CW````
-M````>#,````````!`````0```.WW````````D#,````````!`````0```#_X
-M````````J#,````````!`````0```)'X````````P#,````````!`````0``
-M`+OX````````V#,````````!`````0```!7Y````````\#,````````!````
-M`0```$7Y````````*#0````````!`````0```%CZ````````:#0````````!
-M`````0```*4'`0``````@#0````````!`````0````4(`0``````H#0`````
-M```!`````0```!P(`0``````X#0````````!`````0```$4*`0``````^#0`
-M```````!`````0```+@*`0``````&#4````````!`````0```,L*`0``````
-M.#4````````!`````0```/H*`0``````8#4````````!`````0```$H-`0``
-M````F#4````````!`````0```.0/`0``````P#4````````!`````0```*`0
-M`0``````V#4````````!`````0```+P0`0``````\#4````````!`````0``
-M``L1`0``````&#8````````!`````0```(01`0``````,#8````````!````
-M`0````@2`0``````8#8````````!`````0```+,2`0``````>#8````````!
-M`````0```.D3`0``````F#8````````!`````0```&84`0``````V#8`````
-M```!`````0```+88`0``````&#<````````!`````0```'X>`0``````,#<`
-M```````!`````0```$0?`0``````4#<````````!`````0```'`?`0``````
-M@#<````````!`````0```*4B`0``````P#<````````!`````0```!<H`0``
-M`````#@````````!`````0````4I`0``````,#@````````!`````0```"PJ
-M`0``````8#@````````!`````0```-(J`0``````@#@````````!`````0``
-M`%DK`0``````P#@````````!`````0```+$L`0``````V#@````````!````
-M`0```"PM`0``````\#@````````!`````0```*LM`0``````$#D````````!
-M`````0```)TN`0``````*#D````````!`````0```,HN`0``````4#D`````
-M```!`````0```.TO`0``````:#D````````!`````0````4P`0``````@#D`
-M```````!`````0`````Q`0``````J#D````````!`````0```+@Q`0``````
-MV#D````````!`````0```'$R`0``````&#H````````!`````0```-TS`0``
-M````2#H````````!`````0```(`T`0``````<#H````````!`````0```"TU
-M`0``````D#H````````!`````0```&0U`0``````L#H````````!`````0``
-M`*$U`0``````\#H````````!`````0```/4V`0``````"#L````````!````
-M`0```&4W`0``````*#L````````!`````0```-XW`0``````2#L````````!
-M`````0```+4[`0``````8#L````````!`````0```,0[`0``````>#L`````
-M```!`````0```-@[`0``````D#L````````!`````0```/$[`0``````J#L`
-M```````!`````0```"(\`0``````V#L````````!`````0```)`]`0``````
-M\#L````````!`````0```,D^`0``````"#P````````!`````0```#`_`0``
-M````(#P````````!`````0```#@_`0``````.#P````````!`````0```*$_
-M`0``````4#P````````!`````0```.-``0``````@#P````````!`````0``
-M`/A``0``````H#P````````!`````0```$U!`0``````P#P````````!````
-M`0```(9!`0``````V#P````````!`````0```-M!`0``````\#P````````!
-M`````0```.-!`0``````$#T````````!`````0```/Q!`0``````.#T`````
-M```!`````0```#-#`0``````6#T````````!`````0```&-#`0``````@#T`
-M```````!`````0```"=(`0``````H#T````````!`````0```,Y(`0``````
-MP#T````````!`````0```.9)`0``````X#T````````!`````0```(Y*`0``
-M````$#X````````!`````0```*-,`0``````.#X````````!`````0```'1-
-M`0``````6#X````````!`````0```,--`0``````>#X````````!`````0``
-M`$E.`0``````D#X````````!`````0```,%.`0``````T#X````````!````
-M`0```,Q0`0```````#\````````!`````0```!Q1`0``````0#\````````!
-M`````0```/M1`0``````<#\````````!`````0```"E3`0``````B#\`````
-M```!`````0```&13`0``````R#\````````!`````0```&A9`0``````Z#\`
-M```````!`````0```.]9`0``````*$`````````!`````0```*%=`0``````
-M4$`````````!`````0````%?`0``````:$`````````!`````0```&E?`0``
-M````B$`````````!`````0```*Q?`0``````J$`````````!`````0```/1?
-M`0``````P$`````````!`````0```/I?`0``````V$`````````!`````0``
-M`"M@`0``````$$$````````!`````0```/!@`0``````4$$````````!````
-M`0```,]A`0``````B$$````````!`````0```*]D`0``````H$$````````!
-M`````0```.5D`0``````X$$````````!`````0```%5L`0``````($(`````
-M```!`````0```#QS`0``````.$(````````!`````0```'ES`0``````4$(`
-M```````!`````0```.IS`0``````D$(````````!`````0```+)T`0``````
-MJ$(````````!`````0```&AU`0``````T$(````````!`````0```&-V`0``
-M````\$(````````!`````0```*MV`0``````"$,````````!`````0```#!W
-M`0``````2$,````````!`````0```"-Y`0``````B$,````````!`````0``
-M`)MY`0``````P$,````````!`````0```&QZ`0```````$0````````!````
-M`0```$Y[`0``````.$0````````!`````0```"Y^`0``````>$0````````!
-M`````0```-"``0``````D$0````````!`````0````.!`0``````J$0`````
-M```!`````0```("!`0``````Z$0````````!`````0```*."`0```````$4`
-M```````!`````0```.""`0``````0$4````````!`````0```-&'`0``````
-M>$4````````!`````0```%N)`0``````F$4````````!`````0```,2)`0``
-M````L$4````````!`````0```/.)`0``````R$4````````!`````0```"**
-M`0``````"$8````````!`````0```$*,`0``````2$8````````!`````0``
-M`+J,`0``````@$8````````!`````0```)2-`0``````P$8````````!````
-M`0```'..`0``````^$8````````!`````0```">1`0``````.$<````````!
-M`````0```#&5`0``````4$<````````!`````0```&>5`0``````:$<`````
-M```!`````0```.25`0``````J$<````````!`````0````>7`0``````P$<`
-M```````!`````0```$27`0```````$@````````!`````0```#6<`0``````
-M.$@````````!`````0```,"=`0``````6$@````````!`````0```"F>`0``
-M````<$@````````!`````0```%B>`0``````B$@````````!`````0```(>>
-M`0``````R$@````````!`````0```(Z@`0``````"$D````````!`````0``
-)``:A`0``````
-`
-end
diff --git a/sys/contrib/dev/ath/public/amd64-elf.inc b/sys/contrib/dev/ath/public/amd64-elf.inc
deleted file mode 100644
index e7dae08..0000000
--- a/sys/contrib/dev/ath/public/amd64-elf.inc
+++ /dev/null
@@ -1,63 +0,0 @@
-#
-# Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer,
-#    without modification.
-# 2. Redistributions in binary form must reproduce at minimum a disclaimer
-#    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
-#    redistribution must be conditioned upon including a substantially
-#    similar Disclaimer requirement for further binary redistribution.
-# 3. Neither the names of the above-listed copyright holders nor the names
-#    of any contributors may be used to endorse or promote products derived
-#    from this software without specific prior written permission.
-#
-# Alternatively, this software may be distributed under the terms of the
-# GNU General Public License ("GPL") version 2 as published by the Free
-# Software Foundation.
-#
-# NO WARRANTY
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
-# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-# THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
-# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
-# IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-# THE POSSIBILITY OF SUCH DAMAGES.
-#
-# $Id: //depot/sw/branches/sam_hal/public/x86_64-elf.inc#1 $
-#
-
-#
-# Compilation configuration for building x86-64-elf.
-#
-
-#
-ifndef TOOLPREFIX
-TOOLPREFIX=	/pub/gnu/bin/x86_64-linux-
-endif
-#
-CC=	${TOOLPREFIX}gcc
-LD=	${TOOLPREFIX}ld
-STRIP=	${TOOLPREFIX}strip
-OBJCOPY=${TOOLPREFIX}objcopy
-NM=	${TOOLPREFIX}nm
-
-COPTS+=	-DAH_BYTE_ORDER=AH_LITTLE_ENDIAN
-#
-# NB: this should come from inttypes.h but can't until we cleanp
-#     the definition of va_list on linux
-#
-COPTS+=	-DAH_WORDSIZE=64
-COPTS+=	-mcmodel=kernel -mno-red-zone
-ifndef CONFIG_FRAME_POINTER
-COPTS+=	-fomit-frame-pointer
-endif
diff --git a/sys/contrib/dev/ath/public/amd64-elf.opt_ah.h b/sys/contrib/dev/ath/public/amd64-elf.opt_ah.h
deleted file mode 100644
index de94323..0000000
--- a/sys/contrib/dev/ath/public/amd64-elf.opt_ah.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#define AH_SUPPORT_AR5210	1
-#define AH_SUPPORT_AR5211	1
-#define AH_SUPPORT_AR5212	1
-#define AH_SUPPORT_5111	1
-#define AH_SUPPORT_5112	1
-#define AH_SUPPORT_2413	1
-#define AH_SUPPORT_5413	1
diff --git a/sys/contrib/dev/ath/public/i386-elf.hal.o.uu b/sys/contrib/dev/ath/public/i386-elf.hal.o.uu
deleted file mode 100644
index 45a31f1..0000000
--- a/sys/contrib/dev/ath/public/i386-elf.hal.o.uu
+++ /dev/null
@@ -1,4300 +0,0 @@
-/*-
- * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
- * Communications, Inc.  All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. The materials contained herein are unmodified and are used
- *    unmodified.
- * 2. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following NO
- *    ''WARRANTY'' disclaimer below (''Disclaimer''), without
- *    modification.
- * 3. Redistributions in binary form must reproduce at minimum a
- *    disclaimer similar to the Disclaimer below and any redistribution
- *    must be conditioned upon including a substantially similar
- *    Disclaimer requirement for further binary redistribution.
- * 4. Neither the names of the above-listed copyright holders nor the
- *    names of any contributors may be used to endorse or promote
- *    product derived from this software without specific prior written
- *    permission.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
- * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
- * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/sam_hal/public/i386-elf.hal.o.uu#6 $
- */
-#define	ATH_HAL_VERSION	"0.9.20.3"
-begin 644 hal.o
-M?T5,1@$!`0D```````````$``P`!``````````````!<E0(``````#0`````
-M`"@`#0`*``^W1"0$NC$```"#^%@/A`4!``"#^%A_:(/X&W\S@_@:#XWB````
-M@_@2?Q>#^!$/C;\```"#^`</A*\```#IS@```(/X$P^$O0```.G`````@_A2
-M#X2A````@_A2?Q.Z1````(/X'`^$K````.F?````@_A7#X2`````Z9$```"0
-M/0<1``!T93T'$0``?RJZ5@```#V1````='X]D0```'\,+88```"#^`%W9>M4
-M/100``!T5.M:B?8]$Q$``'1)/1,1``!_"3T2$0``=";K0;II````/1/P``!T
-M/;I]````/1OQ``!T,>LGC78`NI$```#K);J>````ZQZZJP```.L7NKX```#K
-M$+K1````ZPF0N@````"-=@")T,.0BU0D!(M$)`AF@?J,%G039H'Z)Z=T#+D`
-M````9H'ZMQ!U#@^WP%#HN?[__X/$!(G!B<C#D%=64XM\)!2+="08BUPD'(M,
-M)""+5"00#[?"/0<"```/A+L````]!P(``'\P@_@2?Q>#^!$/C8X```"#^`</
-MA)T```#IL````(/X$W1D@^@:@_@"#X>?````ZU&0/1,1``!T3CT3$0``?R(]
-M!Q$``'1O/0<1``!_"3T4$```="WK=ST2$0``=$#K;HGV/1OQ``!T-3T;\0``
-M?PD]$_```'00ZU4]&?\``'5.B?:Z$P```(/L#%%35E</M\)0Z/S___^)PH/$
-M(.L\@^P,45-65P^WPE#H_/___XG"@\0@ZR60@^P,45-65P^WPE#H_/___XG"
-M@\0@ZPV0N@````#'`0$```"0A=)T2V:+@L@!``!FB4((9HN"R@$``&:)0@J+
-M@LP!``")0AQFBX+0`0``9HE"(&:+@M(!``!FB4(B9HN"U`$``&:)0B1FBX+6
-M`0``9HE")HG06UY?PXUV`(M4)`B+1"0$B9#8`0``N`$```##55=64X/L#(ML
-M)"2+?"0HBW0D++L`````BU0D((M"%(L$*"'X.?!U"+@!````ZQR0@^P,:@KH
-M_/___X/$$$.!^^<#``!^TK@`````@\0,6UY?7<.05E.+3"0,BW0D$+L`````
-MN``````Y\',1C10`B<B#X`$)T-'I0SGS<N];7L-75E.+="00BTPD%(M\)!B+
-M5"0<#[?"C01`#[=<@2:X`````(7;#X25`0``#[?"C01`#[9$@26#^`)T:8/X
-M`G\,A<!T'^EO`0``C78`@_@##X3\````@_@$#X0<`0``Z54!``"^P````(-\
-M)"``=!$/M\*-!$"`?($I`'0$9KY@`(T$_0````"-!("-!("-!(#!X`.Z````
-M`/?SC40P"ND:`0``D(.^-!````!T>XN&-!```&:#>`(`>2N)VL'B!+C336(0
-M]^+!Z@:-3/H5B<B)T[H`````]_/!X`0%D````.G8````@[XT$````'0ZBX8T
-M$```]D`#0'0NC13=`````+C336(0]^+!Z@:-3/H5B<B)T[H`````]_.-!,5(
-M````Z9<```")]HT4G0````"XTTUB$/?BP>H&C4SZ%8G(B=.Z`````/?SC02%
-M)````.MLC13=`````+C336(0]^+!Z@:-3/H5B<B)T[H`````]_.-!(46````
-MZT.-%)T`````N---8A#WXL'J!HU,^A6)R(G6N@````#W]HT$A0````"!^^<#
-M``!W!P6]````ZPV#P%SK"(UV`+@`````#[?`6UY?PXM,)`BZ`@```/9!`B!U
-M2`^W00(ET````+H#````/<````!T,P^W00(ET````+H$````/=````!T'KH!
-M````]D$"$'43#[=!`B4`"```@_@!&=+WTH/B!8G0PXGV55=64X/L#(M4)""+
-M7"0D@'PD*`!Y4K@.````@?NT"0``#X39`0``@?NS"0``=QV-BYGV__^X9V9F
-M9O?IB=#1^,'Y'RG(Z;8!``")]HV3,/;__[C-S,S,]^*)T,'H!(/`#^F:`0``
-MB?;W1"0H``$```^$H@```(/L#%+H_/___X/$$(7`=%*-@[/L__^#^#!W1XT$
-MFXT,`+H%````B=B)UKH`````]_:#^@)U$HV1#3___[C-S,S,]^+!Z@+K$(V1
-M"#___[C-S,S,]^+!Z@*)T.DK`0``C78`]T0D*$`!``!T'X'[B!,``'<7C9-@
-M\/__N,W,S,SWXHG0P>@"Z?\```"-DWCL__^XS<S,S/?BB=#!Z`+IZ````+@.
-M````@?NT"0``#X37````@?NS"0``=QN-BYGV__^X9V9F9O?IB=#1^,'Y'RG(
-MZ;0```"!^X<3```/AY0```"#[`Q2Z/S___^#Q!"%P'10C8.S[/__@_@P=T6-
-M!)N-#`"^S<S,S(G8]^:)T,'H`HT$@"G#@_L"=1&!Z?/```")R/?FB='!Z0+K
-M$H'I^,```+C-S,S,]^&)T<'I`HG(ZTB!^R03``!V%(V38/#__[C-S,S,]^*)
-MT,'H`NLLC9,P]O__N,W,S,SWXHG0P>@$@\`/ZQ60C9-X[/__N,W,S,SWXHG0
-MP>@"B?:#Q`Q;7E]=PU.+5"0(BUPD#(N"-!```(7`=!E04NC\____@\0(#[:`
-M``````^OP^L'C78`:\,6D%O#B?93BU0D"(N"-!```(7`="504NC\____@\0(
-M#[:0`````(M$)`R)T[H`````]_.)P>L3C78`N*.++KKW9"0,B='!Z02)]HG(
-M6\-55U93@^P$BWPD'(!_!`!U<;L`````B?;&1!\$_T.#^Q]^];L`````@S\`
-M?E6-=@"-!%N-=(<@BD8(BDX+#[;0B%P7!`I&"0^VP(A<!P0/MNEJ`%5J#E?_
-M="0HZ/S___^#Q!1FB48,:@%5:@Y7_W0D*.C\____@\049HE&#D,Y'W^N@\0$
-M6UY?7<.)]E93BTPD#(M4)!"+7"04BW0D&(V!X`$``(/Z(@^'+`(``/\DE0@`
-M```/MX$(`@``B0:X`````.D9`@``N`T```#I#P(``+@-````Z04"``#V0`,!
-M#Y3`#[;`Z?8!``"X#0```.GL`0``N`T```#IX@$```^W0`J)!K@`````Z=(!
-M```/MT`(B0:X`````.G"`0``BD`"T.B#X`&#^`$9P(/@#>FM`0``#[9``H/@
-M`8/X`1G`]]"#X`WIEP$``(H`P.@"@^`!@_@!&<"#X`WI@@$``(H`P.@#@^`!
-M@_@!&<"#X`WI;0$``(H`P.@$@^`!@_@!&<"#X`WI6`$``(N!^`$``(D&N```
-M``#I1@$``(/[`70:N`````"#^P$/@C,!``"#^P)T&H/[`W0HZS@/OX'\`0``
-MB0:X`````.D4`0``#[>!_@$``(D&N`````#I`0$``(N!``(``(D&N`````#I
-M[P```+@-````Z>4```"0BD`"P.@"@^`!@_@!&<"#X`WIS@```(I``L#H`X/@
-M`8/X`1G`@^`-Z;@```"X#0```.FN````#[9``8/@`8/X`1G`@^`-Z9H```"*
-M0`+`Z`6#X`&#^`$9P(/@#>F$````BD`"P.@&@^`!@_@!&<"#X`WK<8/[`70?
-M@_L!<@>#^P)T(^LQBD`"P.@'#[;`@_@!&<"#X`WK38.Y3!````$9P(/@#>L_
-M#[>!2!```(D&N`````#K+[@-````ZRBX#0```.LA@[EH$````1G`@^`-ZQ.+
-M0!2)!K@`````ZP>X#````(GV6U[#D%93BW0D#(M$)!"+5"04BTPD&(M<)!R#
-M^!ET+8/X&7<(@_@/=`OK89"#^!YT2^M9D(/Z`W53@_D$=TZ)C@`"``"X`0``
-M`.M0D(/Z`70'@_H"=!?K-(7)#Y7`#[;`B89,$```N`$```#K+F:)CD@0``"X
-M`0```.L@D(F.:!```+@!````ZQ*-=@"%VW0&QP,,````N`````!;7L.)]E57
-M5E.+;"04BUPD((M,)!R_`````(/[!W8^B?:+1"08#[<4N`^W=+@"B=#!X!`)
-M\(D!@\$$@^L$BT44BP00B0&#P02#P@2#ZP0Y\G<%@_L#=^9'@_L'=\2)R"M$
-M)!Q;7E]=PY!75E.+="00BTPD%(M\)!B+1"0<BU0D((M<)"2#^0UT-(/Y#7\+
-MA<ET$^F"````B?:#^1UT-X/Y'G1'ZW2-AL@!``")`L<#$````+H!````ZV2-
-M=@#_,_\R5U;H/?___XD#N@$```"#Q!#K2I"-AE`0``")`L<#&````+H!````
-MZS2%P'42QP,$````BQ*+A@0"``")`NL2N@````"#^`1U%(L'B88$`@``N@$`
-M``#K!;H`````B=!;7E_#D%.+7"0,BTPD$+@`````@WL$``^$+0$``(L!B0.+
-M002)0PB+00B)0PR+00R)0Q"#>1#_=!2+01`]_P```'8%N/\```")0Q3K",=#
-M%`(```"0@WD4_W0PBU$4@?H`!```=@6Z``0``,=#&`$````Y4QAS&K@!````
-MD-'@@\@!.=!R]XE#&.L&BT$4B4,8@WD8_W0PBU$8@?H`!```=@6Z``0``,=#
-M'`$````Y4QQS'K@!````D-'@@\@!.=!R]XE#'.L*QT,<_P,``(UV`&:#>1P`
-M=!5FBT$<9H/X#W8%N`\```!FB4,@ZP9FQT,@"@!F@WD>`'079HM!'F:#^`]V
-M!;@/````9HE#(NL(B?9FQT,B"@"+02")0R2+022)0RB+02B)0RR+02R)0S"#
-M>00$=1"#>P0!=0K'0S@!````C78`N`$```!;PY"+3"0(BU0D#+@`````@WH$
-M`'1;BT(,B4$(BP*)`8M""(E!!(M"#(E!"(M"$(E!#(M"%(E!$(M"&(E!%(M"
-M'(E!&&:+0B!FB4$<9HM"(F:)01Z+0B2)02"+0BB)022+0BR)02B+0C")02RX
-M`0```,.05U93BWPD$(M<)!2#[`A35^C\____B<:#Q!"X`````(7V=#)F@WX6
-M`'4B4U?H_/___XG#5E?_E\`!``!F`X0;E````)B#Q!#K#(UV`&:+1A9F`T88
-MF%M>7\.-=@!55U93@^P<BVPD,&;'1"06``!FQT0D&@``9L=$)!0``&;'1"08
-M``"_`````#N],!````^#N0```(T$_0`````I^(VTQ3`"``!F@WX6``^)D0``
-M`%95Z/S___^)1"089HN$`)0```!FB40D%HG#9@->%E95_Y7``0``C00#@\00
-M]D8#`70M9CM$)!1]6&:)1"04@^P(5E7_E<`!``!F`T869HM4)!YF*<)FB50D
-M*(/$$.LR9CM$)!9]*V:)1"06@^P(5E7_E<`!``!F`T86BTPD(&:+E`F4````
-M9BG"9HE4)"J#Q!!'.[TP$```#X)'____OP````")]HT$_0`````I^(VTQ3`"
-M``!F@WX6`'DE@^P(5E7_E<`!``"8@\00]D8#`70&`T0D&.L%9@-$)!IFB488
-MD$>#_S]^OH/$'%M>7UW#D)!55U93@^P4BUPD-(M,)"R+5"0PQT0D#*````"+
-M1"0H9H$X`3!V",=$)`RV````O@`````/M^H/M_F-=@"+5"0,#[<$<HG!#Z_-
-MNF0````IPHG0#Z_'`<&X'X7K4??IB00DB50D!(M$)`3!^`7!^1\IR&:)`X/#
-M`D:#_@I^OX/$%%M>7UW#C78`BU0D"`^WPF:!^O\`=$2+1"0$9H$X`C!W*V:#
-M^CYV$0^WPHT$@`4B%0``#[?`PXGV#[?"C02`C80`[!,```^WP,.-=@`/M\*-
-M!(`%P!(```^WP,.0BU0D"`^WPF:!^O\`=!^+1"0$9H$X`C!W"XV"8`D```^W
-MP,.0C8+\"```#[?`PXGV55=64X/L#(ML)""+="0D9H$^_S]V&F:#?BX`=!.Z
-M`0```&:#?A8`#X13`@``C78`9H$^`C!V9[]0`0``NP````!F@[YV`0````^$
-M+`(``)"#[`2-1"0.4`^WQU!'5?^5H`$``(/$$(7`#X2]`0``9@^V1"0+9HF$
-M7F(!``!F#[9$)`IFB81>9`$``(/#`@^WAG8!```YV'^WZ:4!``"#[`2-1"0.
-M4&@``0``OP$!``!5_Y6@`0``@\00N@````"%P`^$N0$``&:+1"0*B<)FP>H)
-M9HF68@$``&;!Z`*#X']FB89D`0``#[=$)`K!X`6#X']FB89F`0``@^P$C40D
-M#E`/M\=01U7_E:`!``"#Q!"Z`````(7`#X1C`0``9HM$)`J)PF;!Z@MF"99F
-M`0``9L'H!(/@?V:)AF@!```/MT0D"L'@`X/@?V:)AFH!``"#[`2-1"0.4`^W
-MQU!'5?^5H`$``(/$$+H`````A<`/A`T!``!FBT0D"HG"9L'J#68)EFH!``!F
-MP>@&@^!_9HF&;`$```^W1"0*T>"#X']FB89N`0``@^P$C40D#E`/M\=01U7_
-ME:`!``"#Q!"Z`````(7`#X2X````9HM4)`J)T&;!Z`]F"89N`0``B=!FP>@(
-M@^!_9HF&<`$``&;1ZH/B?V:)EG(!```/MT0D"L'@!H/@?V:)AG0!``"#[`2-
-M1"0.4`^WQU!5_Y6@`0``@\00N@````"%P'18ZPF)]KH`````ZTUFBT0D"F;!
-MZ`IF"89T`0``NP````!F@[YV`0```'0I#[>^=@$``(UV``^WA%YB`0``4%;H
-M$?W__X/$"&:)A%YB`0``0SG??^&Z`0```(G0@\0,6UY?7<.)]E575E.#[!B+
-M1"0PBWPD-&:+4!1FB50D$HE$)!0/M\*-%("-%)"-1``#P>@"`<+!X@)2Z/S_
-M__^)P8/$$+@`````A<D/A*4```")#P^W5"0&C402`R7\_P<``<B)1PAFBVPD
-M!F:);P2^`````(/Z`'YXC78`BQ^+3PB-!+:-!(:+;"0(9HM4=0!FB12!9HD4
-M<[D`````C02VC02&C1R%`````(GVC02)C02#B<(#5PAFB4H$`T<(9L=`!@``
-M08/Y`W[BBU<(C02VC02&P>`"9L=$$`8$`(M7"&;'1!!"`P!&#[=$)`8Y\'^+
-MN`$```"#Q`Q;7E]=PXGV55=64X/L!(ML)""+5"0<9HM"%F:)109FQP0DK=YF
-MQT0D`JW>N@````"Y``````^WV(GFD(G8T_BH`70*@_H!?REFB0Q60D&#^0-^
-MZ(M4)!QFBT(49HE%!+@`````9H-]!``/A-4!``#K"K@`````Z<D!``"_````
-M`&:#?00`#X2T`0``C11_C127BT0D'(T44(U:&(MU"(T$OXT$A\'@`F:+4AAF
-MB10PBW4(9HM3$F:)5#`"N0````"-!+^-!(>-%(4`````B?:-!(F-!((#10AF
-MQT`&``!!@_D#?NMF@7PD`JW>=68/MPPDC12_C127C02)P>`"C120`U4(@\($
-M9L="`@0`9HM#`F:)0@1F`T,&9HE"!F8#0PIFB4((9@-##F:)0@IFBT,$9HE"
-M#&:+0PAFB4(.9HM##&:)0A!FBT,09HE"$NGA````B?:-!+^-!(>--(4`````
-M#[<$)(T$@(T$A@-%"&:+4P)FB5`(#[=$)`*-!("-!(8#10AFQT`(%``/MT0D
-M`HT$@(T$A@-%"&;'0`HC``^W1"0"C02`C02&`T4(9L=`##\`#[<,)(T$B8T4
-MA@-5"(/"!&;'0@($`&:+0@1F`T,&9HE"!F8#0PIFB4((9@-##F:)0@IFBT,$
-M9HE"#&:+0PAFB4(.9HM##&:)0A!FBT,09HE"$@^W3"0"C02)C12&`U4(@\($
-M9L="`@,`9HM#%&:)0@QFBT,69HE"#F:+0QAFB4(01P^W100Y^`^/3/[__[@!
-M````@\0$6UY?7<.-=@!55U93@>Q<`0``OU`!``#'1"0(`````,=$)`0`````
-M@WPD"`$/A-X```"#?"0(`7\/@WPD"`!T&.EC`0``C78`@WPD"`(/A`D!``#I
-M4`$``(N$)'0!``!F@W@6``^$/@0``(-\)`0)#X\_`0``@^P$C40D$E!71_^T
-M)'P!``"+E"2``0``_Y*@`0``@\00A<`/A!X$``"`?"0.``^$"P$``(M<)`0/
-MMD0D#O]$)`10_[0D>`$``.CU^/__@\0(9HF$7#`!``!F#[9$)`]FA<`/A-<`
-M``"+7"0$#[;`_T0D!%#_M"1X`0``Z,/X__^#Q`AFB81<,`$``(-\)`0)#XYJ
-M____Z:0```"+C"1T`0``9H-Y&@`/A(8#``"[`````)"+A"1T`0``9H&\6%0!
-M``#_`'099HN$6%0!``"+3"0$9HF$3#`!``!!B4PD!$.#^P)^SNM8BX0D=`$`
-M`&:#>!P`#X0Z`P``NP````"0BY0D=`$``&:!O%I.`0``_P!T&6:+A%I.`0``
-MBTPD!&:)A$PP`0``08E,)`1#@_L"?L[K#+@`````Z0H#``")]H/L"&@<`0``
-MC40D'%#H_/___XM$)!1FB40D-+L`````@\00.UPD!`^-7`(``(UL)`Z-=@!F
-MBX1<,`$``&:)1%P0C11;C1239HE$5"B#[`155T?_M"1\`0``BY0D@`$``/^2
-MH`$``(/$$(7`#X27`@``C0Q;C0R+C4Q,(&:+1"0.#[;09L'H!X/@`<'@"&8I
-MPF:)40QFBT0D#HG"9L'J"&;!Z`_!X`AF*<)FB5$0@^P$55='_[0D?`$``(N,
-M)(`!``#_D:`!``"#Q!"%P`^$-@(``(T,6XT,BXV,3%`!``!FBT0D#@^VT&;!
-MZ`>#X`'!X`AF*<)FB9'D_O__9HM$)`Z)PF;!Z@AFP>@/P>`(9BG"9HF1Z/[_
-M_X/L!%571_^T)'P!``"+E"2``0``_Y*@`0``@\00A<`/A,P!``"-%%N-%).-
-M5%0@9HM$)`Z#X!]FB4(.9HM$)`YFP>@%@^`?9HE"$F:+1"0.9L'H"H/@'V:)
-M0A:#[`155T?_M"1\`0``BXPD@`$``/^1H`$``(/$$(7`#X1Q`0``C0Q;C0R+
-MC4Q,,&:+1"0.#[;09L'H!X/@`<'@"&8IPF:)40QFBT0D#HG"9L'J"&;!Z`_!
-MX`AF*<)FB5$.@^P$55='_[0D?`$``(N4)(`!``#_DJ`!``"#Q!"%P`^$$`$`
-M`(T$6XT$@XVT1%`!``"-CN#^__]FBT0D#@^VT&;!Z`>#X`'!X`AF*<)FB5$0
-MBX0D=`$``&:!.`)`=AIFBT$(9HE!"F8/MD0D#X/@/V:)AMK^___K,HT$6XT$
-M@XV$1%`!``!FBU0D#HG19L'I"&;!Z@_!X@AF*=%FB8CJ_O__9L>`VO[__P$`
-M0SM<)`0/C*O]__^+5"0(BXPD=`$``&:+1%%H9HE$)":#[`2-!%*-A(%D#0``
-M4(U$)!A0_[0D?`$``.A7^/__@\00A<!T1(M4)`B-!%*+C"1T`0``C82!9`T`
-M`%"-1"044/^T)'@!``#H(?G__X/$#(7`=!:)]O]$)`B#?"0(`@^.:/O__[@!
-M````@<1<`0``6UY?7<.05E.#[`2+="04NP````")]HT$6XT$AHN09`T``(72
-M=!;'@&0-````````@^P,4NC\____@\000X/[`G[4@\0$6U[#B?955U93BWPD
-M%(M$)!B)Q6:)1Q0/MU<6O@````#VP@%T!;X!````B="#X`*#^`%F@][_B="#
-MX`2#^`%F@][_B="#X`B#^`%F@][_NP````!F.>MS*I`/M\.+5"0<9HL,0F:)
-M#$>-%("-%)*-%%"-%%=FB4H89HER&D-F.>MRUUM>7UW#B?955U93@^P\BVPD
-M4(I$)&2(1"0-BW0D7+\`````@WPD8``/A,$```"0@^P$C40D$E`/M\901E7_
-ME:`!``"#Q!"%P`^$D@4``(!\)`X`#X26````@'PD#0!U'P^WWP^V1"0.1U#_
-M="18Z+SS__^#Q`AFB41<$.L=B?8/M]\/MD0D#D=0_W0D6.CQ\___@\0(9HE$
-M7!!F#[9$)`]FA<!T2H!\)`T`=1L/M]\/ML!'4/]T)%CH<O/__X/$"&:)1%P0
-MZQL/M]\/MD0D#T=0_W0D6.BI\___@\0(9HE$7!`/M\<[1"1@#X)`____C40D
-M$%`/M\=0_W0D8.B"_O__BW0D;-'N`W0D:&;'1"06``"#Q`R+5"189H-Z%``/
-MAK<$``"-?"0.C78`#[=4)`J-!)*-!("-!$*+5"18C5Q"&&:#>P(`#X2_````
-M@^P$5P^WQE!&5?^5H`$``(/$$(7`#X1Y!```9HM$)`Z#X!]FB4,,9HM$)`YF
-MP>@%@^!_9HE#!&:+1"0.9L'H#&:)0SR#[`17#[?&4$95_Y6@`0``@\00A<`/
-MA#4$``!FBT0D#H/@/V:)0Q1FBT0D#F;!Z`:#X`]FB4-$9HM$)`YFP>@*9HE#
-M'(/L!%</M\901E7_E:`!``"#Q!"%P`^$\0,``&:+1"0.@^`/9HE#3&:+1"0.
-M9L'H!(/@/V:)0R1F@WL"`0^&Y0```&:+1"0.9L'H"H/@'V:)0PYFBT0D#F;!
-MZ`]FB4,&@^P$5P^WQE!&5?^5H`$``(/$$(7`#X22`P``#[=$)`Z#X#_1X&8)
-M0P9FBT0D#F;!Z`:#X`]FB4,^9HM$)`YFP>@*9HE#%H/L!%</M\901E7_E:`!
-M``"#Q!"%P`^$3`,``&:+1"0.@^`/9HE#1F:+1"0.9L'H!(/@/V:)0QYFBT0D
-M#F;!Z`J#X`]FB4-.9HM$)`YFP>@.9HE#)H/L!%</M\901E7_E:`!``"#Q!"%
-MP`^$^`(```^W1"0.@^`/P>`"9@E#)NM2B?9F@WL"`75)9HM$)`YFP>@*@^`/
-M9HE#5&:+1"0.9L'H#F:)0RR#[`17#[?&4$95_Y6@`0``@\00A<`/A*8"```/
-MMT0D#H/@#\'@`F8)0RR)]F:#>P("#X:]````9HM$)`YFP>@$@^`?9HE#$&:+
-M1"0.9L'H"6:)0PB#[`17#[?&4$95_Y6@`0``@\00A<`/A%("``!FBT0D#H/@
-M#V:)0T!FBT0D#F;!Z`2#X#]FB4,89HM$)`YFP>@*@^`/9HE#2&:+1"0.9L'H
-M#F:)0R"#[`17#[?&4$95_Y6@`0``@\00A<`/A/X!```/MT0D#H/@#\'@`F8)
-M0R!FBT0D#F;!Z`2#X`]FB4-09@^V1"0/@^`_9HE#*.LGC78`9H-[`@)U'6:+
-M1"0.9L'H!(/@#V:)0U9F#[9$)`^#X#]FB4,N9H-[`@,/AC4!``!FBT0D#F;!
-MZ`YFB4,2@^P$5P^WQE!&5?^5H`$``(/$$(7`#X1V`0``#[=$)`Z#X`?!X`)F
-M"4,29HM$)`YFP>@#@^!_9HE#"F:+1"0.9L'H"H/@#V:)0T)FBT0D#F;!Z`YF
-MB4,:@^P$5P^WQE!&5?^5H`$``(/$$(7`#X0?`0``#[=$)`Z#X`_!X`)F"4,:
-M9HM$)`YFP>@$@^`/9HE#2F8/MD0D#X/@/V:)0R)FBT0D#F;!Z`YFB4-2@^P$
-M5P^WQE!&5?^5H`$``(/$$(7`#X3+````#[=$)`Z#X`/!X`)F"4-29HM$)`YF
-MP>@"@^`_9HE#*F8/MD0D#X/@#V:)0UIFBT0D#F;!Z`QFB4,R@^P$5P^WQE!&
-M5?^5H`$``(/$$(7`='L/MT0D#H/@`\'@!&8)0S+K39!F@WL"`W5%9HM$)`YF
-MP>@.9HE#6(/L!%</M\901E7_E:`!``"#Q!"%P'0^#[=$)`Z#X`/!X`)F"4-8
-M9HM$)`YFP>@"@^`_9HE#,(GV9O]$)`IFBU0D"HM$)%AF.5`4#X=0^___N`$`
-M``"#Q#Q;7E]=PXUV`%575E.#[`R+5"0D9HM"%(ML)"!FB4449HM%%F:)1"0(
-M9L=$)`8``*@!=`=FQT0D!@$`BT0D"&;1Z(/@`8/X`6:#7"0&_XM$)`AFP>@"
-M@^`!@_@!9H-<)`;_BT0D"&;!Z`.#X`&#^`%F@UPD!O]FQT0D"@``BU0D)&:#
-M>A0`#X;'````D`^W5"0*BVPD)&:+3%4`BT0D(&:)#%"-!)*-!("-!$*+5"0@
-MC01"9HE(&&:+;"0&9HEH'+\`````NP`````/MW0D"HT$MHT$@(T$1M'@B00D
-M#[?+C01)BQ0DC03"BVPD((T4*&:)6AX/MT0D"-/XJ`%T%F;'0B`$`$=F@_\!
-M=2AFQT(@!0#K()`/M].-%%*-!+:-!("-!$;1X(T4T(M$)"!FQT0"(```0V:#
-M^P-VHF;_1"0*9HML)`J+5"0D9CEJ%`^'.O___X/$#%M>7UW#B?955U93@^PD
-M9L=$)!BMWHU$)!AFQT`"K=YFQT`$K=YFQT`&K=['1"00`````&;'1"04``"+
-M1"1`#[=0%KL#````C70D&`^W1"04B=DIP8G0T_BH`704B=AF*T0D%(M,)!!F
-MB01.08E,)!!F_T0D%&:#?"04`W;.BU0D/&:+0A2+3"1`9HE!%&;'1"06``!F
-M@WD4``^&_P````^W5"06C022C02`C01"T>"+3"0\C10(C6H89HM2&(M,)$!F
-MB50(&&;'1"04``"#?"00``^$K@````^W5"06C022C02`C01"T>")1"0,C78`
-M#[=4)!0/MT14&(T$0(M,)`R-!,&+3"1`C70('@^_1%4,P>`"9HE&#F:+1%4$
-M9HE&!+\!````9H-^`@%V1@^W1"04B40D"&:+5@)FB50D!I`/M\^+1"0(C1R(
-M#[]$731FBU1.#(T$0F:)1$X.9HM$3@)F`T1=#&:)1$X$1V8Y?"0&=\UF_T0D
-M%`^W1"04.T0D$`^":?___V;_1"069HM,)!:+5"1`9CE*%`^'`?___[@!````
-M@\0D6UY?7<-55U93@^P<BWPD-&;'1"00!`"-1"009L=``@8`9L=`!`D`9L=`
-M!@P`QT0D#`````"#[`QH%`0``.C\____B<.#Q!"%P`^$=@$```^WK]````!F
-M@W\6`'1X@^P(:!0$``!0Z/S___]FBT=H9HE#%H/$"&H`:@I54U?_="1,Z*/V
-M__^#Q""%P`^$)`$``(VW9`T``&:+1VAFB4864U;H9_S__XDT)%/_="0\Z*[]
-M__^#Q!"%P`^$]P````^W0QH/MU1$#@^W0Q0/K\*-;`4%C78`9H-_&@!T<8/L
-M"&@4!```4^C\____9HM':F:)0Q:#Q`AJ`6H$55-7_W0D3.@D]O__@\0@A<`/
-MA*4```"-MW@1``!FBT=J9HE&%E-6Z.C[__^)-"13_W0D/.@O_?__@\00A<!T
-M?`^W0QH/MU1$#@^W0Q0/K\*-;`4"9H-_'`!T68/L"&@4!```4^C\____9HM'
-M;&:)0Q:#Q`AJ`FH$55-7_W0D3.BL]?__@\0@A<!T,8VWC!4``&:+1VQFB486
-M4U;H=/O__XDT)%/_="0\Z+O\__^#Q!"%P'0(QT0D#`$```"%VW0,@^P,4^C\
-M____@\00BT0D#(/$'%M>7UW#55=64X/L'(M\)#"+1"0T9H$X_S]V&F:#>"X!
-M=1.#[`A05^BI[___@\00Z2H#``"0BU0D-&:!.O]/=DUF@WHN`G5&@^P(4E?H
-MZ/W__X/$$.D%`P``N`````#I^P(``+@`````Z?$"``"X`````.GG`@``N```
-M``#IW0(``+@`````Z=,"``")]L=$)!``````BTPD-&:!.0,P&?:#YK"!QE`!
-M``"#?"00`71.@WPD$`%_#H-\)!``=!/IGP```(GV@WPD$`)T9.F1````@\8%
-MBT0D-&:+@'8!``!FB40D&(M<)#2!PW@!``"+5"0T@<)B`0``B50D#.MOBTPD
-M-&:#>1H`#X0]`@``@\8W9HN!@`,``&:)1"08B<N!PSX$``"!P8@#``")3"0,
-MZSV+5"0T9H-Z'``/A`L"``"#QD9FBXJ``P``9HE,)!B)TX'#H@,``('"@@,`
-M`(E4)`SK"[@`````Z?(!``"0QT0D%`````!F@WPD&``/A,D!``"-;"0:BU0D
-M%(M,)`QFBP119HD#@^P$559&5_^7H`$``(/$$(7`#X2M_O__9HM$)!IFP>@*
-M9HE#!&:+1"0:9L'H!(/@/V:)0P(/MT0D&L'@`H/@/V:)0QZ#[`155D97_Y>@
-M`0``@\00A<`/A'/^__]FBT0D&F;!Z`YF"4,>9@^V1"0;@^`_9HE#(&:+1"0:
-M9L'H`H/@/V:)0R(/MT0D&L'@!(/@/V:)0R2#[`155D97_Y>@`0``@\00A<`/
-MA"S^__]FBT0D&F;!Z`QF"4,D9HM$)!IFP>@&@^`_9HE#)F:+1"0:@^`_9HE#
-M*(/L!%561E?_EZ`!``"#Q!"%P`^$]?W__V:+1"0:9L'H"F:)0RIFBT0D&F;!
-MZ`2#X#]FB4,L#[=$)!K!X`*#X#]FB4,N@^P$559&5_^7H`$``(/$$(7`#X2[
-M_?__9HM$)!IFP>@.9@E#+F8/MD0D&X/@/V:)0S!FBT0D&F;!Z`*#X#]FB4,R
-MC4,(4`^W0P10#[=#`E#_="1`Z/;E__^Z`````(/$$`^W0P:)P8/X`'X:C78`
-M#[]$4QZ-!("-!(#1X&:)1%,>0CG1?^F#PS3_1"04#[=$)!@[1"04#X\[_O__
-M_T0D$(-\)!`"#XX\_?__N`$```"#Q!Q;7E]=PXUV`%575E.#[!R+?"0TO0``
-M``!F@3__/W8)#[=')(UPJ^L09H$_`S`9]H/FL('&4`$``(/]`70S@_T!?P:%
-M[70*ZWB#_0)T2^MQD(/&5<=$)!`(````C9_<!```C8?:!```B40D#.M?C78`
-M9H-_&@`/A-$!``"#QF7'1"00`@```(V?3@4``(V73`4``(E4)`SK-&:#?QP`
-M#X2I`0``@\9IQT0D$`,```"-GRX%``"-ARP%``")1"0,ZPRX`````.F1`0``
-MB?:+5"0,9L<"``#'1"04`````(M$)!`Y1"04#XUA`0``D(/L!(U$)!Y05D;_
-M="0\BU0D0/^2H`$``(/$$(7`#X1,`0``9H$_`C!V#F8/MD0D&V:)0PCK#XGV
-M9HM$)!IFP>@)9HE#"&:#>P@`#X3Z````A>UU%`^W0PA05^C9Y/__@\0(9HE#
-M".L2#[=#"%!7Z!GE__^#Q`AFB4,(9H$_`C!V(V:+1"0:9L'H`H/@/V:)0P8/
-MMT0D&L'@!(/@/V:)0P3K(8GV9HM$)!IFP>@#@^`_9HE#!@^W1"0:P>`#@^`_
-M9HE#!(/L!(U$)!Y05D;_="0\BU0D0/^2H`$``(/$$(7`#X2)````9H$_`C!V
-M*V:+1"0:9L'H#&8)0P1FBT0D&F;!Z`:#X#]FB4,"9HM$)!J#X#]FB0/K+)!F
-MBT0D&F;!Z`UF"4,$9HM$)!IFP>@'@^`_9HE#`F:+1"0:9M'H@^`_9HD#BT0D
-M#&;_`(/#"O]$)!2+5"00.50D%`^,H?[__Y!%@_T"#X["_?__N`$```"#Q!Q;
-M7E]=PY!55U93@^P,BVPD((MT)"2!QF0%``"+1"0D9H$X_S]V"0^W>"2#QQKK
-M=[^_`0``BU0D)&:!.@(P=V?K7;@`````Z;D#``"X`````.FO`P``N`````#I
-MI0,``+@`````Z9L#``"X`````.F1`P``N`````#IAP,``+@`````Z7T#``"X
-M`````.ES`P``N`````#I:0,``(UV`+]O`0``C78`QT0D!`````"+3"0D9H.Y
-M!`$````/A#\#``")]HM$)`2+5"0D9H.\0@8!````=1EF@3H",'8&@\<(ZP20
-M@\<'@\9`Z?D"``"0BTPD)&:!.0(P#X:M````NP````"#[`2-1"0.4%='5?^5
-MH`$``(/$$(7`#X0C____9HM$)`J)PF;!Z@AFB13>)?\```!FB43>"(/#`H/[
-M!W[#NP````")]H/L!(U4)`Y25T=5_Y6@`0``@\00A<`/A.G^__]F#[9$)`N#
-MX#]FB43>`F:+1"0*9L'H#H/@`8E$W@1FBT0D"H/@/V:)1-X*9HM$)`IFP>@&
-M@^`!B43>#(/#`H/[!WZAZ=D!``"#[`2-3"0.45='5?^5H`$``(/$$(7`#X2/
-M_O__9HM$)`J)PF;!Z@EFB19FP>@"@^!_9HE&"`^W1"0*P>`%@^!_9HE&$(/L
-M!(U$)`Y05T=5_Y6@`0``@\00A<`/A%7^__]FBT0D"HG"9L'J"V8)5A!FP>@$
-M@^!_9HE&&`^W1"0*P>`#@^!_9HE&((/L!(U4)`Y25T=5_Y6@`0``@\00A<`/
-MA!K^__]FBT0D"HG"9L'J#68)5B!FP>@&@^!_9HE&*`^W1"0*T>"#X']FB48P
-M@^P$C4PD#E%71U7_E:`!``"#Q!"%P`^$X/W__V:+5"0*B=!FP>@/9@E&,(G0
-M9L'H"(/@?V:)1CAFP>H"@^(_9HE6`@^W1"0*P>`$@^`_9HE&"H/L!(U$)`Y0
-M5T=5_Y6@`0``@\00A<`/A)C]__]FBU0D"HG09L'H#&8)1@J)T&;!Z`:#X#]F
-MB482@^(_9HE6&H/L!(U4)`Y25T=5_Y6@`0``@\00A<`/A&/]__]FBT0D"HG"
-M9L'J"F:)5B)FP>@$@^`_9HE&*@^W1"0*P>`"@^`_9HE&,H/L!(U,)`Y15T=5
-M_Y6@`0``@\00A<`/A"C]__]FBT0D"HG"9L'J#F8)5C)FP>@(@^`_9HE&.KL`
-M````B?:#/-X`=$J+5"0$BTPD)`^WA%$&`0``@^`'=`6#^`-U&`^W!-Y0_W0D
-M*.@.X/__@\0(9HD$WNL9D`^W!-Y0_W0D*.A*X/__@\0(9HD$WHUV`$.#^P=^
-MJH/&0(UV`/]$)`2+5"0D#[>"!`$``#M$)`0/C\/\__^X`0```(/$#%M>7UW#
-MB?955U93@^P,BVPD((MT)"1FQT8J#P!FQT8L#P!F@3X",'82QP0DY````&;'
-MA@0!```@`.L0QP0DS````&;'A@0!```0`(/L!(U$)`Y0BT0D"/\P5?^5H`$`
-M`(/$$,=$)`0`````A<`/A"P.``!FBU0D"HG09L'H#V:)1@:)T&;!Z`Z#X`%F
-MB48*B=!FP>@+@^`'9HE&#(G09L'H!(/@?V:)1@YF@3[_/W8/B=!FP>@#@^`!
-M9HE&".L&9L=&"`$`9HM4)`J)T&;!Z`*#X`%FB48<B=!FT>B#X`%FB48:@^(!
-M9HE6%HL$)(M8!(/L!(U$)`Y04T-5_Y6@`0``@\00QT0D!`````"%P`^$BPT`
-M`&:+5"0*B=!FP>@(B$8>B%8?9H$^_S\/AM<```"#[`2-1"0.4%-#5?^5H`$`
-M`(/$$,=$)`0`````A<`/A$L-``!FBU0D"HG09L'H#F:)1BZ)T&;!Z`V#X`&)
-MAL@```")T&;!Z`R#X`&)ALP```"!XO\/``!FB58P@^P$C40D#E!30U7_E:`!
-M``"#Q!#'1"0$`````(7`#X3P#```9HM$)`J)PH'B_P\``&:)5B1FP>@.@^`!
-MB$8C9H$^_T]V-H/#`H/L!(U$)`Y04U7_E:`!``"#Q!#'1"0$`````(7`#X2H
-M#```9HM$)`IFP>@$9HF&T````+\`````BP0DBURX"(/L!(U$)`Y04T-5_Y6@
-M`0``@\00A<`/A`\+``!F#[9$)`N#X']FB41^,F:+1"0*9L'H`H/@/V:)1'XX
-M#[=$)`K!X`2#X#]FB41^=(/L!(U$)`Y04T-5_Y6@`0``@\00A<`/A-$*``!F
-MBT0D"F;!Z`QF"41^=&:+1"0*9L'H!H/@/V:)1'YZ9HM$)`J#X#]FB81^@```
-M`(/L!(U$)`Y04T-5_Y6@`0``@\00A<`/A),*``!FBT0D"F;!Z`IFB81^A@``
-M`&:+1"0*9L'H!(/@/V:)A'Z,````#[=$)`K!X`*#X#]FB81^D@```(/L!(U$
-M)`Y04T-5_Y6@`0``@\00A<`/A$P*``!FBT0D"F;!Z`YF"81^D@```&8/MD0D
-M"X/@/V:)A'Z8````9HM$)`IFP>@"@^`_9HF$?IX````/MT0D"L'@!(/@/V:)
-MA'ZD````@^P$C40D#E!30U7_E:`!``"#Q!"%P`^$]`D``&:+1"0*9L'H#&8)
-MA'ZD````9HM$)`IFP>@&@^`_9HF$?JH```!FBT0D"H/@/V:)A'ZP````@^P$
-MC40D#E!30U7_E:`!``"#Q!"%P`^$L`D``&8/MD0D"XA$-U:#_P%T48/_`7\,
-MA?]T#^G_````C78`@_\"=%SK>6:+1"0*B<)FP>H%@^('9HF6\````&;!Z`*#
-MX`=FB8;R````#[=$)`K1X(/@!V:)ANP```#K0XUV`&:+5"0*B=!FP>@$@^`'
-M9HF&]````(/B!V:)EO8```#K'V:+5"0*B=!FP>@$@^`'9HF&^````(/B!V:)
-MEOH```"%_W5X@^P$C40D#E!30U7_E:`!``"#Q!"%P`^$_0@``&:+5"0*B=!F
-MP>@/9@F&[````(G09L'H#(/@!V:)ANX```")T&;!Z`F#X`=FB8;H````B=!F
-MP>@&@^`'9HF&Z@```(G09L'H`X/@!V:)AN0```"#X@=FB9;F````@^P$C40D
-M#E!30U7_E:`!``"#Q!"%P`^$D@@``&8/MD0D"V:)1'X^9@^V1"0*9HE$?D2#
-M[`2-1"0.4%-#5?^5H`$``(/$$(7`#X1M"```9@^V1"0+9HE$?DIF#[9$)`IF
-MB41^4(/L!(U$)`Y04T-5_Y6@`0``@\00A<`/A$@(``!F#[9$)`N(1#=99@^V
-M1"0*9HE$?ER$P'D*#0#___]FB41^7(/L!(U$)`Y04T-5_Y6@`0``@\00A<`/
-MA!8(``!FBT0D"F;!Z`4E_P```&:)1'YB9HM$)`IFT>B#X`]FB41^:&:+1"0*
-M@^`!9HE$?FYF@3[_/W8RA?]T"H/_`G07ZR>-=@!FBT0D"F;!Z`V#X`%FB48F
-MZQ)FBT0D"F;!Z`V#X`%FB48HB?9F@3X",`^&E0```(/L!(U$)`Y04T-5_Y6@
-M`0``@\00A<`/A),'``!FBT0D"F;!Z`:#X']FB81^M@```(/_`702@_\!?P:%
-M_W1+ZU6#_P)T(^M.9HM$)`J)PH/B!V:)EOP```!FP>@#@^`'9HF&``$``.LM
-M9HM$)`J)PH/B!V:)EOX```!FP>@#@^`'9HF&`@$``.L,9HM$)`J#X#]FB482
-M9H$^`S`/AID```!FBT0D"F;!Z`UFB81^O````(/L!(U$)`Y04T-5_Y6@`0``
-M@\00A<`/A.\&```/MT0D"L'@`X/@.&8)A'Z\````@_\"=2!FBU0D"HG09L'H
-M`XA&(F:!/@5`=@N)T&;!Z`MFB48LD(7_=3YF@3[_/P^&R0,``&:+5"0*B=!F
-MP>@(@^`_9HF&1@$``&;!Z@.#XA]FB99*`0``ZPYFQX1^O`````H`QD8B#V:!
-M/O\_#X:+`P``@_\!=""#_P%_#87_#X21`@``Z70#``"#_P(/A)L```#I9@,`
-M`(/L!(U$)`Y04T-5_Y6@`0``@\00A<`/A#8&```/MD0D"E!6Z%;8__^#Q`AF
-MB894`0``#[9$)`M05NA`V/__@\0$9HF&5@$``(U$)`Y04U7_E:`!``"#Q!"%
-MP`^$_P4```^V1"0*4%;H$MC__X/$"&:)AE@!``!F@3X`0`^&Y0(``&8/MD0D
-M"X/@/V:)AL0```#IT`(``(/L!(U$)`Y04T-5_Y6@`0``@\00A<`/A+H%```/
-MMD0D"E!6Z,#7__^#Q`AFB89.`0``#[9$)`M05NBJU___@\0$9HF&4`$``(U$
-M)`Y04T-5_Y6@`0``@\00A<`/A((%``!FBT0D"HG"@^)_9HE6$&;!Z`>#X#]F
-MB484@^P$C40D#E!30U7_E:`!``"#Q!"%P`^$6@4```^V1"0*4%;H1M?__X/$
-M"&:)AE(!``!F@3X`0'809@^V1"0+@^`_9HF&Q@```(/L!(U$)`Y04T-5_Y6@
-M`0``@\00A<`/A!L%``!FBU0D"HG09L'H!8/@/V:)AD@!``"#XA]FB99,`0``
-M9H$^`4`/AL<!``"#[`2-1"0.4%-#5?^5H`$``(/$$(7`#X3?!```9HM4)`IF
-M#[;"9HE&*F:!/O]/#X:3`0``B=!FP>@(@^!_9HF&U@```(G09L'H#V:)AMH`
-M``"#[`2-1"0.4%-#5?^5H`$``(/$$(7`#X28!```#[=$)`J#X!_1X&8)AMH`
-M``!FBU0D"HG09L'H!8/@/V:)AN(```!FP>H+B);=````@^P$C40D#E!35?^5
-MH`$``(/$$(7`#X17!```#[=$)`J#X`?!X`4(AMT```!FBT0D"F;!Z`.(AM\`
-M``#IZ@```(GV9H$^`$`/AMT```"#[`2-1"0.4%-#5?^5H`$``(/$$(7`#X03
-M!```9HM4)`J)T(/@/V:)AL(```!F@3[_3P^&I0```(G09L'H!H/@?V:)AM0`
-M``")T&;!Z`UFB8;8````@^P$C40D#E!30U7_E:`!``"#Q!"%P`^$R`,```^W
-M1"0*@^`'P>`#9@F&V````&:+5"0*B=!FP>@#@^`_9HF&X````&;!Z@F(EMP`
-M``"#[`2-1"0.4%-5_Y6@`0``@\00A<`/A(8#```/MT0D"H/@`<'@!PB&W```
-M`&:+1"0*9M'HB(;>````D$>#_P(/C@?W__]F@3X",`^'CP```(/L!(U$)`Y0
-M:.P```!5_Y6@`0``@\00QT0D!`````"%P`^$:`,``&:+1"0*B<*#X@=FB9;\
-M````9L'H`X/@!V:)A@`!``"#[`2-1"0.4&CM````5?^5H`$``(/$$,=$)`0`
-M````A<`/A"(#``!FBT0D"HG"@^('9HF6_@```&;!Z`.#X`=FB88"`0``C78`
-M9L>&8`$```0`9L>&7@$```$`9L>&7`$```$`9L>&6@$`````BP0DBU@4OP``
-M``!F@[X$`0```'1)C78`@^P$C40D#E!30U7_E:`!``"#Q!"%P`^$=`(``&8/
-MMD0D"V:)A'X&`0``9@^V1"0*9HF$?@@!``"#QP(/MX8$`0``.?A_NF:!/@)0
-M=F&_`````(GV@^P$C40D#E!35?^5H`$``(/$$(7`#X0K`@``9HM$)`IFB82^
-MC@,``(/L!(U$)`Y0C4,%4%7_E:`!``"#Q!"%P`^$"@(``&:+1"0*9HF$OI`#
-M``!#1X/_!'ZF9H$^`C!W)F;'1ES*_V;'1E[__V;'1F#__W<29L=&1`\`9L=&
-M1AP`9L=&2!P`9H$^_S]V*8/L!(U$)`Y0:,H```!5_Y6@`0``@\00QT0D!```
-M``"%P`^$NP$``.LG@^P$C40D#E!HSP```%7_E:`!``"#Q!#'1"0$`````(7`
-M#X22`0``9HM$)`IFB4889H-^%@`/A70!``!F@3[_/P^&70$```^WP,'H"X/@
-M`6:)1A;I5P$``,=$)`0`````Z50!``#'1"0$`````.E'`0``QT0D!`````#I
-M.@$``,=$)`0`````Z2T!``#'1"0$`````.D@`0``QT0D!`````#I$P$``,=$
-M)`0`````Z08!``#'1"0$`````.GY````QT0D!`````#I[````,=$)`0`````
-MZ=\```#'1"0$`````.G2````QT0D!`````#IQ0```,=$)`0`````Z;@```#'
-M1"0$`````.FK````QT0D!`````#IG@```,=$)`0`````Z9$```#'1"0$````
-M`.F$````QT0D!`````#K>L=$)`0`````ZW#'1"0$`````.MFQT0D!`````#K
-M7,=$)`0`````ZU+'1"0$`````.M(QT0D!`````#K/L=$)`0`````ZS3'1"0$
-M`````.LJQT0D!`````#K(,=$)`0`````ZQ9FBT889L'H#V:)1A;'1"0$`0``
-M`(GVBT0D!(/$#%M>7UW#5E.#[`R+="08BUPD'%-6Z$CQ__^#Q!"Z`````(7`
-M=%2#[`A35NANT?__@\00N@````"%P'0^@^P(4U;H5.?__X/$$+H`````A<!T
-M*(/L"%-6Z*+J__^#Q!"Z`````(7`=!*#[`A35NCH[/__B<*#Q!"-=@")T(/$
-M!%M>PX/L#(M$)!1F@3C_/W8:9H-X+@%U$X/L"%#_="0<Z(;;__^#Q!"-=@"#
-MQ`S#BU0D!(M,)`AFBP)F.P%U&`^W4@*!XO#!```/MT$")?#!```IPNL)D`^W
-M$@^W`2G"B=##D(M$)`0/MX`(`@``)?^_``##C78`BTPD!+H`````BT31!`L$
-MT70&N`````##0H/Z`7[KN`$```##_W0D!.B_____@\0$B<&Z`````&:%P'DL
-M@>'_?P``B?:-!))F.0R%X`@``'0+0H'Z@@```';JZR6X`0```,.X`0```,.-
-M!-4`````*=!F.0R%0````'3G0H/Z2G;GN`````##D%.+7"0,N`$```!FA=MT
-M<?]T)`CH3/___X/$!(G!9H7`>14/M\.)RH'B_W\``#G0#Y3`#[;`ZTEF/?\!
-M=`JZ`````&:%P'41N`$```#K,K@!````ZRN-=@"-!)+!X`)F.9C@"```=0EF
-M.8CB"```=-Y"@?J"````=M^X`````(GV6\.)]E93@^P0BT0D'(MT)"!0_Y"<
-M`0``B<.#Q!"H0G0+@WX(`'4%@^.]B?;VPR!T"X-^#`!U!8/CWXGV]L,(=`N#
-M?@0`=06#X_>)]O;#`707BT0D&(/`&%#HFO[__X/$!(7`=`.#X_Z)V(/$!%M>
-MPU575E.![)@```"+K"2L````OP`````/MX0DL````%#HE````(G#@\00A<!T
-M)XGF5FA__P``4%7HR`$``(/$$(7`=!&#[`164U7H1O___XG'@\00D(GX@<2,
-M````6UY?7<.-=@!3BUPD"%/H!?[__X/$!`^WP(/X$G0>@_@2?PF%P'0=ZRN-
-M=@`]_P$``'01/4J#``!U&HGVN`$```#K%I"X`0```&:!NPH"``!*`W0%N```
-M``!;PY"+3"0$N@````"-=@"-!)+!X`)F.8C@"```=0D%X`@``,.-=@!"@?J"
-M````=M^X`````,.05E/_="0,Z'W]__^#Q`2)QF:%P'DCB?.!X_]_``!3Z*G_
-M__^#Q`2)VH7`=4?K"@^W5!`(ZSZ-=@"Z`````(UV`(T$U0`````IT,'@`F8Y
-ML$````!U$[I0````9H-\$`@`=<RZ2P```)!"@_I*=M*Z`````(G06U[#5E.#
-M[`2+7"00BW0D%+H`````B?:-!%*-!("-#,4`````#[>!H"$``#G8=2"%]G05
-M@^P$:GB-@:`A``!05NC\____@\00N`$```#K"T*#^C!VPK@`````@\0$6U[#
-MC78`BTPD!+@`````A<ET+^L&N`$```##N@````")]HT$U0`````IT`^W!(5`
-M````.<ATWD*#^DIVY;@`````PXUV`%575E.#[!R+1"0X9HE$)!J_`````+T`
-M````QT0D%`````#'1"00`````(M4)#1F@SH`=4[_="0PZ#/\__^#Q`2)PV:%
-MP'@Q@^P(:@`/M_!6Z`O___^#Q!"%P'4-5NA>____@\0$A<!T!0^W\^L<BT0D
-M-`^W<`+K$HM4)#0/MW("ZPB+1"0T#[=P`O?&`/\```^%.@$``+D`````NP``
-M``"-!,T`````*<B-%(4`````#[>"0````#GP=1&!PD````")5"04NP$```")
-M]D&#^4IW!H7;=,KK$+@`````A=L/A$(!``"-=@"`?"0:`'@0BU0D%`^W<@*+
-M>@B]`````(!\)!H`>1"+1"04#[=P!(MX#+T`````N0````"[`````(T$R8T4
-MA0`````/MX*`"```.?!U(XM$)#"+@-@!```[@H0(``!U$8'"@`@``(E4)!"[
-M`0```(GV08/Y`7<&A=MTONL$A=MT:(!\)!H`>"R+5"00BTH(NP````")^"'(
-MB>HAVHG'BT0D$(M(#+L`````B?@)R`G:B<>)U8!\)!H`>2Z+5"00BTH0NP``
-M``")^"'(B>HAVHG'BT0D$(M(%+L`````B?@)R`G:B<>)U8GV@^P(_W0D1%;H
-M@_W__XG#@\00N`````"%VW0\BU0D/(M"#(M:$(G"BW0D%"-6$(G9(TX4BT0D
-M/(E0#(E($(M4)#1F]T("`/]U"8GN"?YT`XEX%+@!````@\0<6UY?7<.05U93
-MBU0D$(MT)!2)T(72>0.-0C^)Q\'_!HGXP>`&B=,IP[@!````N@````"(V0^E
-MPM/@]L,@=`>)PK@`````(P3^(U3^!(G1"<$/E<`/ML!;7E_#5E.+3"0,BUPD
-M$(MT)!2*5"08A-)T)K@`````.=AS$9`X%`%T%X`\`0!T!4`YV'+P.=AT"(@4
-M`?\&C78`6U[#D%575E.![(P!``"+G"2\`0``BX0DP`$``&:)1"0Z9L=$)#)8
-M&XN4)*`!``"!PC`"``")5"0HOP````#_M"2@`0``Z)[Y__^#Q`2Z`````(7`
-M#X3>!@``_[0DH`$``.C"^___BXPDI`$``&:)@0H"``"#Q`1FA<!U+P^WPU!1
-MZ,;Y__^#Q`BZ`````(7`#X2B!@``B=@E_S\``(N<)*`!``!FB8,*`@``@^P,
-M_[0DK`$``.@Z"P``B[0DL`$```^WA@H"``!0Z";[__^)PX/$%+H`````A<`/
-MA%@&``"-A"0``0``4&A__P``4_^T)*P!``#H1OS__X/$$+H`````A<`/A"X&
-M``"-A"2`````4&B`````4_^T)*P!``#H'/S__X/$$+H`````A<`/A`0&``"+
-MA"0$`0``@^`%N@````")T0G!=`6_`0```(N$)`0!``"#X`*Z`````(G6"<9T
-M!;\"````BX0DH`$``#FX#`(``'0&B;@,`@``@^P$C80D!`$``%!3_[0DK`$`
-M`.@[^?__B40D1(/$$(.\),0!````=0EFBUL09HE<)#+'1"0D`````(.\)*@!
-M``!`=@O'A"2H`0``0````(N4)*`!``"*@N(!``"(PL#J!8G1@^$!B4PD%,#H
-M!HG#@^,!B5PD&,=$)"P$`0``@7PD+!P!```/@QX$``"-=@!FBWPD.HMT)"QF
-MA3X/A/8#```/MP:%1"0T#X3I`P``C40D/E"-1"1`4`^W1@)0_[0DK`$``(N4
-M)+`!``#_DI@!``"#Q!"%P`^$NP,```^W!H/X!`^$G0```(/X!'\/@_@!=&6#
-M^`)T+^F;`P``@_@@#X3?````@_@@?PZ#^`@/A*,```#I?P,``(/X0`^$\0``
-M`.EQ`P``C8PD``$``(E,)`R-G"0H`0``B5PD$,=$)`0`&0``BH0D`@$``(/(
-M`XA$)!_IYP```(V4)``!``")5"0,C8PD&`$``(E,)!#'1"0$(!,``(J<)`(!
-M``"(7"0?Z;D```"-M"2`````B70D#(V\),@```")?"00QT0D!.`;``"*A"2"
-M````@\@!B$0D'^F(````C90D@````(E4)`R-C"38````B4PD$,=$)`2@'@``
-MBIPD@@```(/+`HA<)!_K6HVT)(````")="0,C;PDZ````(E\)!#'1"0$`"$`
-M`(J$)((```"#R`2(1"0?ZRR-E"0``0``B50D#(V,)#@!``")3"00QT0D!``9
-M``"*G"0"`0``@\L$B%PD'_]T)!#H`/;__X/$!(7`#X5%`@``QT0D(`````"0
-M_W0D$/]T)"3HB_O__X/$"(7`#X04`@``BT0D(,'@`RM$)""+="0$C02&B40D
-M"`^V0!A0_[0DO`$``/^T)+P!``#_M"2\`0``Z)_[__^+?"089HLO@\009CEO
-M`@^"RP$``(UV`&8Y;"0\#X>E`0``9CML)#X/AYH!``"+1"0(@'@&"G4+@WPD
-M%``/A(4!``"+5"0(@'H&!74+@WPD&``/A'`!```/M\6+3"0(#[91!P'0T?@/
-MMU0D,H/""CG0#X]1`0``BYPDJ`$``#E<)"0/@WL!``"#>10`>0Z#O"3(`0``
-M``^$+`$``(MT)`R`?A0`>12+O"2@`0``@[_<`0``!@^$#@$``(/L"&HXC40D
-M3%#H_/___V:);"10BU0D/&:+0@)FB40D4H/$$(M,)`@/ME$&@_H%=`^#^@IU
-M$8#,0&:)1"1"ZP=F@4PD0@"`BUPD"(I#!(A$)$6*0P6(1"1:BW0D#(M&%(E$
-M)%P/MD0D'XE$)&"+2Q"+6Q2)R"-&#(G:(U80B=$)P70)9H%,)$(``NL'9H%D
-M)$+__8M<)`B+2PB)WHM;#(G(BWPD#"-'!(G:(U<("="#^`$9P/?0@^`"B$0D
-M1(M."(G((T<$@^`"N@````")T0G!=`6`3"1$"(M<)`SV0Q1`=`6`3"1$!(M\
-M)"3!YP,K?"0DBW0D*(T\_HU$)$#\N0X```")QO.E_T0D)(UV`(M\)`AF#[9'
-M!P'%9CEO`@^#._[__XUV`/]$)""#?"0@?P^.Q?W__Y"#1"0L!(%\)"P<`0``
-M#X+E^___@WPD)``/A-X```"#?"0D0'8(QT0D)$````!H^#\``&HX_W0D+/]T
-M)#3H_P(``(M4)#2+A"2P`0``B9`P$```N0````"#Q!`YT7U`C03-`````"G(
-MP>`#BUPD*&:+%!B+M"2D`0``9HD4SF:+5!@"9HE4S@**5!@$B%3.!(I$&`6(
-M1,X%03M,)"1\P(/L!/]T)"C_M"2L`0``_[0DK`$``(N\)+`!``#_E[P!``"Y
-M`````(/$$#M,)"1]+HT$S0`````IR,'@`XN<)*0!``"*5,L&BW0D*(A4,`:*
-M5,L'B%0P!T$[3"0D?-*+A"2L`0``BWPD)(DXBY0DH`$``&:+@@H"``!FB4(8
-MA?\/E<`/MM"0B="!Q(P!``!;7E]=PXUV`%575E.+3"04BUPD&`^W>P*!Y_#!
-M``"+D300``"%TG0P9HL"9CL#=2@/MW("B?`E\,$``#GX=1GV0@0!=`VX````
-M`/?&`@```'5ZB=#K=HGVC:DP`@``BXDP$```A<ET7P^W,Y")R-'XC13%````
-M`"G"C535``^W`HGS*<.)V'4S#[=:`HG8)?#!```Y^'45]D($`70*N`````#V
-MPP)U)8G0ZR&0#[="`B7PP0``B?LIPXG8A<!^!(UJ.$G1^76EN`````!;7E]=
-MPXUV`/]T)`C_="0(Z/S___^#Q`BZ`````(7`=!L/OE`:T>*+1"0,*-`/OM"$
-MP'D(N@````"-=@")T,.055=64XMT)!2+;"08O_\```!F@[X*`@````^%A0``
-M`%;H/_'__X/$!(G#B=@E\````(/X8'005N@H\?__@\0$9H'[F0%U7@^W10(E
-MH````+_A````/:````!T?0^W10(ET````+_B````/<````!T:`^W10(ET```
-M`+_D````/=````!T4P^W10(E4`$``#U0`0``#Y3`#[;XC;Q_X````.LVB?95
-M5NC\____@\0(A<!T)HMX(`^W10(EP````#W`````=1.)^(/@#X/X`74)@^?P
-M@\\"C78`B?A;7E]=PY#_="0(_W0D".C\____@\0(N@````"%P'0+BT`<P>@"
-MB<*#X@&)T,.055=64X/L#(ML)"B+1"0@B40D!`'HB00DBT0D)$B)1"0(=$.+
-M/"2+1"0$.<=V+XGVB?XI[H/L"%=6_U0D/(/$$(7`?AF)^8GKBA:*`8@&1H@1
-M04MU\RGO.WPD!'?3`2PD_TPD"'6]@\0,6UY?7<.)]E93@^P(BW0D%(GSC40D
-M!E!HP0```%;_EJ`!``"#Q!"Z`````(7`=%R#[`2-1"0$4&:!?"0*`$`9P(/@
-M!07*````4%;_EJ`!``"#Q!"Z`````(7`="]F@7PD`O\_=A(/MP0DP>@+@^`!
-MB88\$```ZPT/OP0DP>@?B88\$```BY,\$```D(G0@\0$6U[#4X/L"(M<)!!3
-MZ%+O__^#Q`0/M\"#^$AT/X/X2'\:@_A!?PV#^$!],(7`=#KK8HGV@_A#="/K
-M69`]C8$``'\1/8B!``!]$H/H2H/X`G="ZP@]CX$``'4YD(/L#%/H$____X/$
-M$.LO#[>#"@(``#V(`0``?!P]C0$``'X'/8\!``!U#H/L#%/HZ?[__X/$$.L%
-MN`````"#Q`A;PXGV5U93@^P4BWPD)(M<)"B)_HU$)!)0:,$```!7_Y>@`0``
-M@\00A<!T5+H`````C78`C012T>!F.9B@.```=39F@7PD#@)0=PEFBX"B.```
-MZPN-!%)FBX0`I#@``&:)A@@"``!7Z-3P__]FB88*`@``@\0$ZPA"@_H-=K:)
-M]H/$$%M>7\.05U93@^P4BWPD)(MT)"B)^XU$)!)0:,$```!7_Y>@`0``@\00
-MA<!T4KH`````C78`C012T>!F.;``.0``=39F@7PD#@)0=PEFBX`".0``ZPN-
-M!%)FBX0`!#D``&:)@P@"``!7Z%#P__]FB8,*`@``@\0$ZP9"@_H&=K:#Q!!;
-M7E_#C78`5E.#[!"+7"0<4^A-_O__@\00A<!T/O:#Y`$```%T-6:#NP@"````
-M=!>#[`@/MX,(`@``4%/HOO[__X/$$.L5D(/L"`^W@PH"``!04^@K____@\00
-M@\0$6U[#D)!55U93@>RH````BZPDO````&@$$@``Z/S___^)PX/$$+X"````
-MA<`/A(`%``")QX/L!&AL$```:"`!``!0Z/S___^+A"3$````B4,,BX0DR```
-M`(E#$(N$),P```")0Q1FB:O(`0``9L>#R@$`````9L>#_`$``#P`QX,``@``
-M`````,>#,!$```,```#'@_`1````````QX/T$0````<``,>#^!$``/_____'
-M@_P1``#_____QX,`$@``_____X/$"&H`4^C\____@\00O@,```"%P`^$TP0`
-M`,>#S`$```$```"+0Q2+D"!```!F#[;29HF3T`$``(N0&)@``&:)D](!``!F
-MQX/6`0````#'@-"8```6'```O@````"-=@"+1Q3'@("8``````$`1H/^`W;M
-MBT<4BX``G```P>@<@^P(:@10Z/S___]`9HF'U`$``(M7%(N"$$```(E$)!B#
-MR`&)@A!```"#Q`R-1"024&H]5^C\____@\00O@@```"%P`^$&`0``+X$````
-M9H%\)`ZE6@^%!@0``(/L!(U$)!)0:C]7Z/S___^#Q!"^"````(7`#X3F`P``
-M9HM$)`YFB8-N$```@^P$C40D$E!HP0```%?H_/___X/$$+X(````A<`/A+<#
-M``!FBT0D#F;!Z`QFB8-L$```O@4```!F@_@!#X68`P``O0````"^`````(GV
-M@^P$C41T%%"-AL````!05^C\____@\00A<`/A&0#```/MT1T$#'%1H/^/W;3
-MO@<```"!_?__```/A4X#``"#[`2-1"024&B_````5^C\____@\00O@@```"%
-MP`^$*P,``&8/MD0D#F:)AP@"``"+1"049HF#<!```&:+1"069HF#<A```(M$
-M)!B(@W00``!F#[9$)!F(@W40``!FBT0D&HB#=Q```&8/MD0D&XB#=A```&8/
-MMD0D'8B#>A```(M$)!R(@WL0``!F#[9$)!^(@WP0``!FBT0D'HB#?1```(I$
-M)""#X`&(@W@0``"+1"0@9M'H@^`'B(-Y$```QX?``0```````+X`````O0D`
-M``"-%/4`````*?*-%)8!VHV*?A```&:+1&P09L'H"HB"?A```&:+1&P09L'H
-M!(/@/XA!"P^W1&P0P>`"@^`\9HM4;!)FP>H."="(00&*1&P3@^`_B$$,9HM$
-M;!)FP>@"@^`_B$$"#[=$;!+!X`2#X#!FBU1L%&;!Z@P)T(A!#6:+1&P49L'H
-M!H/@/XA!`XI$;!2#X#^(00YFBT1L%F;!Z`J(001FBT1L%F;!Z`2#X#^(00\/
-MMT1L%L'@`H/@/&:+5&P89L'J#@G0B$$%BD1L&8/@/XA!$&:+1&P89L'H`H/@
-M/XA!!@^W1&P8P>`$@^`P9HM4;!IFP>H,"="(01%FBT1L&F;!Z`:#X#^(00>*
-M1&P:@^`_B$$29HM$;!QFP>@*B$$(9HM$;!QFP>@$@^`_B$$3#[=$;!S!X`*#
-MX#QFBU1L'F;!Z@X)T(A!"8I$;!^#X#^(011FBT1L'F;!Z`*#X#^(00H/MT1L
-M'L'@!(/@,&:+5&P@9L'J#`G0B$$59HM$;"!FP>@&@^`_B$$6BD1L((/@/XA!
-M%V:+1&PB9L'H"HA!&&:+1&PB9L'H!(/@/XA!&0^W1&PBP>`"@^`\9HM4;"1F
-MP>H."="(01J*1&PE@^`_B$$;9HM$;"1FP>@"@^`_B$$<1H/%"X/^!`^&$O[_
-M_X/L#%?H`0$``+T`````O@````"#Q!"#[`2-1"024+@?````*?!05^C\____
-M@\00A<!T2@^W1"0.`<5F#[9$)`^(A',/$0``9HM$)`Z(A',0$0``1H/^`G:]
-MA>UT"(']_?\"`'4'O@D```#K(HM'%(M4)`B)D!!```")^.M&O@@```#K%XGV
-MO@@```"-=@"+1Q2+5"0(B9`00```A=MT#(/L#%/H_/___X/$$(.\),``````
-M=`F+A"3`````B3"X`````('$G````%M>7UW#@^P8_W0D'.C\____@\0<P[@`
-M````]D0D"0%T%XM$)`QFQP``%(M$)!!FQP`V%;@!````P[@!````PXGVBTPD
-M!(V1X`$``(-*!`%FQT(,`!1FQT(.-A6`B>`!```"BD("9L=""`,`9L=""D``
-M@^">B$("@+EX$````'079L>!2!``````QX%,$````0```(!*`H#'0A0/````
-MQX%H$````0```+@!````PY"0D%.+3"0(BUPD#(M1%(M#!(F"+(```(M1%(M#
-M#(F",(```(M1%(M#$(F"-(```(M1%(M#"(F".(```(M1%(L#B8(D@```6\.)
-M]H/L+(M,)#"+5"0TB50D!(.YW`$```%T)(G0*P4`````P>`#B40D#(G0*P4`
-M````P>`#B40D$(E4)`CK&,=$)`S_____QT0D$/_____'1"0(`0```(M$)#@E
-M__^``8D$)(G@4%'H_/___X/$-,.-=@"+5"0$BT(4QX`L@````````(M*%(N!
-M!(````T``!``)?__7_^)@02```"+0A3'@"2```#__P``PU=64XM\)!"+3"04
-MB?YF@WD2`'1$BU<4BX($@```)?__?_\-```@`(F"!(```(M7%`^W01")@BB`
-M``"+5Q0/MT$2B8)(@```BU<4BT$4P>`#B8(T@```ZQ2+5Q2+@@2````E__]?
-M_XF"!(```(M7%(L!B8(L@```BU\4BX,D@```)0``@/\/MU$("<)F@WD8`'01
-M#[=!&(/`!,'@$"4``'\`"<*)DR2```!F@[_0`0```W8Y#[=!&J@'=#&+EO01
-M``"`YOAF@WD:!W<-P>`()0`'```)PNL$D(#.!XF6]!$``(M'%(F0&(```(GV
-M6UY?PXM$)`2+0!2+@`A```"%P`^5P`^VP,.)]E93BW0D#(M,)!"+1A2+4!R#
-M^O]U#\<!`````+@`````ZT2)]HG0(X88$0``);K8!0&)`??"(`!P`'0'#0``
-M`$")`?;"!70#@PD!]\+`!0``=`.#"4#V00-`=`:)EE`0``"X`0```%M>PXUV
-M`(M$)`2+@!@1``##D%=64XMT)!"+7"04B?&+OA@1``"%_WD-BT84QT`D````
-M`(UV`(G:@>*ZV`4!]L,!=`.#R@7VPT!T,X.Y'!$```!T`X/*0(.Y(!$```!T
-M`X#.`8.Y)!$```!T`X#*@(.Y*!$```!T!H#.!(UV`(M&%(E0((F9&!$``(7;
-M>0R+1A3'0"0!````B?:)^%M>7\.0D+A`````PXGVBT0D"&:#^#]W'0^WP,'@
-M!8M4)`0#0A2+@!R0``"Z`0```&:%P'@%N@````")T,.0BTPD!(M$)`BZ````
-M`&:#^#\/AX$````/M\#!X`6)P@-1%,>"`)````````")P@-1%,>"!)``````
-M``")P@-1%,>"")````````")P@-1%,>"#)````````")P@-1%,>"$)``````
-M``")P@-1%,>"%)````````")P@-1%,>"&)`````````#013'@!R0````````
-MN@$```")T,.05U93BWPD$(M4)!B+="04N`````!F@_X_=VJ%TG0X#[9:!<'C
-M"`^V0@0)PP^V2@/!X1@/MD("P>`0"<$/MD(!P>`("<$/M@()P='IB=C!X!\)
-MP='KZPJ[`````+D`````#[?&P>`%B<(#5Q2)BAB0```#1Q2)VH#.@(F0')``
-M`+@!````6UY?PU575E.#[!"+="0LBT0D*&:)1"0.@WPD-`$9R??1@>&JJJJJ
-MN`````!F@WPD#C\/AU`!``"X`````(`^``^%0@$``+@`````9H-^`@0/AC(!
-M``#'!"0`````9H-^`@5V$&:#?@(.&=*#XOZ#P@.)%"0/MFX$#[9&!<'@"`G%
-M#[9&!L'@$`G%#[9&!\'@&`G%,<T/MD8)P>`(#[96"`G",<J!XO__``")5"0(
-M#[9^"@^V1@O!X`@)QP^V1@S!X!`)QP^V1@W!X!@)QS'/#[9&#\'@"`^V5@X)
-MPC'*@>+__P``B50D!`^V7A`/MD81P>`("<,/MD82P>`0"<,/MD83P>`8"<,Q
-MRV:#?@(-=P:!X_\````/MTPD#HG(P>`%B<*+="0D`U84B:H`D```B<(#5A2+
-M="0(B;($D```B<*+="0D`U84B;H(D```B<(#5A2+="0$B;(,D```B<*+="0D
-M`U84B9H0D````T84BQ0DB9`4D```_W0D,%%6Z/S___^#Q`R-=@"#Q!!;7E]=
-MPX/L$&H&BT0D&`4/$0``4/]T)"#H_/___X/$',.#[!!J!O]T)!R+1"0<!0\1
-M``!0Z/S___^X`0```(/$',.-=@"#[!!J!FB,$0``_W0D(.C\____@\0<PY"X
-M`````,.)]E.#[`B+7"00BU,4BT0D%(N$@@!@``!J`FH#:`!L``!3Z/S___^#
-MQ!"Z`````(7`=!6+0Q2+D`!H``"+1"089HD0N@$```")T(/$"%O#C78`4XM<
-M)!"+3"0(N@P```"+1"0,9CF!"`(``'03BH%N$```@^"`/`$9TH/B^(/""X7;
-M=`*)$[@`````6\.0N`$```##B?975E.+?"009HN?2!```(G>@^8<P?X"@^,"
-MT?N#[`A65^C\____@\0,.=@/E,`/ML!05E?H_/___X/$$%M>7\.04XM$)`B+
-M6!2+3"0,T>&Z`P```-/B]]*+@Q1````APK@"````T^`)PHF3%$```+@!````
-M6\.-=@!3BT0D"(M8%(M,)`S1X;@#````T^#WT(N3%$```"'0B8,40```N`$`
-M``!;PU.+3"0,BT0D"(M8%(N3&$```+C^____T\`APHM$)!"#X`'3X`G"B9,8
-M0```N`$```!;PY"+3"0(N/____^#^05W%8M$)`2+0!2+@!Q```"#X"_3Z(/@
-M`<-64X/L!(MT)!"+3"04BT84BY@40```B<K!X@S1X;@#````T^`)T`T`@`$`
-M]]`APPG3@,^`@WPD&`!T!H'+```!`(M&%(F8%$```(/L"(N&&!$```T````!
-M4%;H_/___X/$%%M>PXUV`%.+7"0(BTPD#(M#%(N0$$```(7)=`J#^01T#>L3
-MC78`@^*?ZQ&-=@"#XM^#RD#K!H/*((/BOXM#%(F0$$```%O#C78`BT0D!(M`
-M%(N`!(```"4``(``@_@!&<"#P`+#D(M,)`2+5"0(BT$4BX`$@```J0``@`!T
-M"(/Z`G4(PXGV@_H!=`Z+410-``"``(F"!(```,.X`````,.)]H-\)`@`#Y3`
-M#[;`PU93@^P(BW0D%(M<)!QJ!O]T)!R-AC01``!0Z/S___^+3A0/MI8T$0``
-M#[:&-1$``,'@"`G"#[:&-A$``,'@$`G"#[:&-Q$``,'@&`G"B9$(@```@\00
-MBTX4#[:&.1$``,'@"`^VEC@1```)PHG8)?\_``#!X!`)PHF1#(```&:%VW49
-MBU84BX($@```#0``$`")@@2```#K%XUV`(M6%(N"!(```"7__^__B8($@```
-M@\0$6U[#B?93BT0D"(M`%(N(;(```(N0<(```(N8;(```#G+@](`N`````")
-MV;L`````"<@)VEO#C78`BT0D!(M`%(N`;(```,.)]HM$)`2+4!2+@B2````-
-M`````8F")(```,.-=@"+5"0$BT(4BX!DF```B<'!Z1.!X?\!``#VQ0%T!H'Q
-M`/[__XM2%(N"<(```(N2;(```#'0,<C#D(M$)`0/MY#0`0``BT`4BX`@0```
-M)?\````YP@^4P`^VT(G0PXM,)`2+1"0(BU$4BY*8@````1"+412+DI2````!
-M4`2+412+DIR````!4`R+412+DI"````!4`B+412+DJ"````!4!##5U93BWPD
-M$(MT)!2)^X/^"'86@^P(:/__``!7Z/S___^#Q!`Y\',2D,>#^!$``/____^X
-M`````.LC@^P(5E?H_/___XM7%(F"$(```(/$$(FW^!$``+@!````B?9;7E_#
-M@^P4BU0D&(M"%(N`$(```"7__P``4%+H_/___X/$',-55U93@^P4BVPD*&C_
-M'P``5>C\____@\00.T0D)',1QX7\$0``_____[@`````ZSR+=12+GA2```"!
-MXP#@__^#[`C_="0L5>C\____)?\?```)PXF>%(```(/$$(M$)"2)A?P1``"X
-M`0```)"#Q`Q;7E]=PX/L%(M4)!B+0A2+@!2````E_Q\``%!2Z/S___^#Q!S#
-MBT0D!`^V@/,1``"#\`&#X`'#B?:+1"0$B<&#?"0(`'0CBU`4BX($@```)?__
-M__Z)@@2```"!H?`1``#____^ZR&-=@"+4!2+@@2````-`````8F"!(```(&)
-M\!$```````&X`0```,-55U93@^P4BVPD*&C_'P``5>C\____@\00.T0D)',1
-MQX4`$@``_____[@`````ZT"+=12+GA2```"!X___`."#[`C_="0L5>C\____
-MP>`0)0``_Q\)PXF>%(```(/$$(M$)"2)A0`2``"X`0```(GV@\0,6UY?7<.#
-M[!2+5"08BT(4BX`4@```)0``_Q_!Z!!04NC\____@\0<PY"X`0```,.)]L.-
-M=@"X`````,.)]L.-=@##C78`@^P,BT0D%(M4)!B#^`%U#(/Z`1G`]]"#X`WK
-M$O]T)!Q24/]T)!SH_/___X/$$(/$#,.)]E.#[`B+7"00BTPD%(M4)!R#^0MT
-M#[@`````@_D>=#?K'XUV`(/B!HF3^`$``(M#%(F0:(```+@!````ZQF-=@"#
-M[`S_="0L4O]T)"Q14^C\____@\0@@\0(6\.0@^P4_W0D+/]T)"S_="0L_W0D
-M+/]T)"S_="0LZ/S___^#Q"S#BTPD!(M1%(N"!(````T```0`B8($@```@WPD
-M"`!T%(M1%(N"!$```"7___S_B8($0```PU93@^P$BW0D$(-\)!0`='2+5A2+
-M@@1````E___\_XF"!$```(/L#&C0!P``Z/S___^["@```(/$$(UV`(M&%(N`
-M$$```*D```$`="F#[`QHR````.C\____BU84BX($0```)?___/^)@@1```"#
-MQ!!+=<GK!X7;=0N-=@"X`````.L:D(M6%(N"!(```"7___O_B8($@```N`$`
-M``"#Q`1;7L.0BTPD!(M1%(N"!(````T```0`B8($@```@WPD"`!T%(M1%(N"
-M!$```"7___S_B8($0```PU=64XM$)!"+7"04BU0D&(G&OP$```"#^P%T(8/[
-M`7((@_L"="/K+9"#[`A24.CV_O__B<>#Q!#K(XUV`%)0Z(G___^#Q`CK%%)0
-MZ*7^__^#Q`CK"+@`````ZPF0B9XP$0``B?A;7E_#BT0D!(M`%(N`!$```"4`
-M``,`P>@0PY"04X/L"(M$)!2#^`%T#[L`````@_@"=!7K"XUV`+L`````ZPF0
-MN`````#K$Y"#[`A3_W0D'.C\____B=B#Q!"#Q`A;PY"+1"0$BT`4BT`,PY"+
-M1"0$BU`4BT0D"(E"#,.0BT0D!(M`%,=`"`0```##D%93@^P$BW0D$(M&%,=`
-M""````"[`````(M&%(M`"*@$=0JX`0```.L>C78`@^P,:@KH_/___X/$$$.!
-M^^<#``!^UK@`````@\0$6U[#C78`BT0D!(M0%(N":(```(/@OXF":(```,.0
-MBT0D!(M0%(N":(```(/(0(F":(```,.0BTPD!(M1%(M$)`B)@E"```"+412+
-M1"0,B8)4@```PY!3BU0D"(M,)`RX`````(/Y/W="@_D?=B"+4A2+FE2```"#
-MZ2"X_O___]/`(=B)@E2```#K&XUV`(M2%(N:4(```+C^____T\`AV(F"4(``
-M`+@!````6\.04XM4)`B+3"0,N`````"#^3]W0H/Y'W8@BU(4BYI4@```@^D@
-MN`$```#3X`G8B8)4@```ZQN-=@"+4A2+FE"```"X`0```-/@"=B)@E"```"X
-M`0```%O#D(M$)`2+0!2+@$R```##B?:+5"0(]L8"=`:`YOV#RB"+1"0$BT`4
-MB9!,@```PXUV`(M4)`R+3"0(QT$(`````(G0)?\/``")00RX`````#E1#'4A
-M]D0D$"!T!X%)#``@``#'010`````QT$0`````+@!````PXUV`%=64XM\)!"+
-M="0HBUPD%(M$)!RZ#P```/9#%`$/A`4!``#V0!0!=16+1Q2+0`RZ#P```#M$
-M)!@/A.H```!FBT,0)?\/``!FB0:+2Q2!X0"`_P_!Z0^+1Q2+@&R```")PL'J
-M"H'B__\``(G0)?\?```YR',0C8(`X/__)?__```)P>L#D`G1B<@E_W\``&:)
-M1@+&1@0`BT,4J`)U.*@$=`C&1@0!ZRZ)]O9#%!!T!H!.!`CK(/9#%`AT!H!.
-M!`3K%(!.!`*+0Q0EX````,'H!8A&!8GVBT,0)0``^`?!Z!.(1@:+0Q3VQ`%T
-M#B4`?@``P>@)B$8'ZP60QD8'_XM#$"4`@`<`P>@/B$8(BT,0P>@.@^`!B$8)
-MBT,0P>@,@^`!B$8*N@````")T%M>7\.0D)!55U93@^P,BWPD((ML)"R)?"0(
-MN@P```"+1"0H]D`#`0^$P@4``(/L"/]T)#!7Z/S___^)1"04@\00N@P```"%
-MP`^$H04``(-\)"0&="&#?"0D!G<)@WPD)`%W">L1@WPD)`AT"KH,````Z7D%
-M``"+1Q2+@!!```")PX/C8(/L"/]T)#!7Z/S___^#Q!"Z`P```(7`#X1.!0``
-MBT\4BW0D"`^VE@\1```/MH80$0``P>`("<(/MH81$0``P>`0"<(/MH82$0``
-MP>`8"<*)D0"```"+3Q0/MI84$0``P>((#[:&$Q$```G0B8$$@```@^P(_W0D
-M+%?H!04``(/$$(-\)"0!=$F#?"0D`7(I@WPD)`9T"8-\)"0(=$WK8HM'%,=`
-M*`````"+1Q3'@!!```!`$```ZTF+1Q3'0"@!````BT<4QX`00```)!```.LP
-MBT<4QT`H`````(M'%,>`$$```"00``#K%XM'%,=`*`````"+1Q3'@!!```!`
-M$```BU<4BX(00```"=B)@A!```"+3Q2+1"0(#[:0-!$```^V@#41``#!X`@)
-MPHM<)`@/MH,V$0``P>`0"<(/MH,W$0``P>`8"<*)D0B```"+3Q0/MI,Y$0``
-MP>((#[:#.!$```G0B8$,@```BT<4QP``````BT<4QT`$`````(M'%,=`#```
-M``"+1Q2+4!S'0"``````BT<4QT`D`````,>#&!$```````"+1Q2+4"S'0#`%
-M````BT<4QT`T!0```(M'%,=`1`@```"+1Q3'0$@(````BT<4QT!0`````(M'
-M%,=`3`````"+1Q3'@`Q`````````BT<4QT!``````(M7%(N#]!$``(F"&(``
-M`(M'%,>`2(````````"#[`AJ`%?H_/___XM'%,>`4(````````"#Q!"+1Q3'
-M@%2`````````BT<4QX!8@````````(M'%,>`7(````````"+1Q3'@&"````!
-M````BT<4QX!D@````0```(M'%,>`:(````````"+1Q3'@"B`````````BT<4
-MQX`L@````````(M'%,>`;(````````"+1Q3'@#"```#_____BT<4QX`T@```
-M_____XM'%,>`.(````$```"Y`````+Z@$0``BQS.A>UT#8V#`(#__SW_#P``
-M=@J+5Q2+1,X$B00:08'YI@```';9@^P(_W0D,%?H_/___X/$$+H#````A<`/
-MA$P"``"+3Q2+D2B8```P]HMT)`@/MH9U$```P>`("<*)D2B8``"+7Q0/MI9V
-M$```B=#!X!C!XA`)T`^VCG<0``")RL'B"`G0"<B)@S28``"+3Q2+D428``"!
-MXG_`__]FBX9P$```9M'H)8`_```)PHF11)@``(M/%(N12)@``('B_P_\_P^W
-MAG`0``#!X`HE`/`#``G"B9%(F```BT\4BY%DF```@>+_#_C_#[:&=!```,'@
-M#"4`\`<`"<*)D628``"+3Q2+D1"9``"#XOP/MX9P$```@^`#"<*)D1"9``"#
-M[`C_="0,5^A$#0``@\00N@,```"%P`^$5`$``(7M="2+1"0$]D`$`G4$@&`$
-M_HM4)`1FBT("BTPD*&:)00**0@2(002+1Q3'@!R8```!````@^P,:.@#``#H
-M_/___XM7%(N"8)@``(/(`8F"8)@``(/$$&H`:@%H8)@``%?H_/___X/$"/]T
-M)`Q7Z/S___^#Q!"[`````(7`=1.+7"0H9H-+`@*Z`P```.G"````@^P(4U?H
-M_/___X/$$$.#^P)^[8._3!````!T#(/L#%?H_/___X/$$(M7%(N")(```"7_
-M_W_^B8(D@```BW0D"(.^^!$``/]T$H/L"/^V^!$``%?H_/___X/$$(M$)`B#
-MN/P1``#_=!*#[`C_L/P1``!7Z/S___^#Q!"+5"0(@[H`$@``_W02@^P(_[(`
-M$@``5^C\____@\00@[_X`0```'0/BU<4BX?X`0``B8)H@```BTPD)(F/W`$`
-M`+@!````ZQ"+7"0P@SL`=`*)$[@`````@\0,6UY?7<-3BUPD"(M4)`R+0Q2+
-M@`2````E__\``(/Z`71$@_H!?P>%TG0EZV60@_H&=`>#^@AT1NM8BU,4"X/P
-M$0``#0``40")@@2```#K0HM3%`N#\!$```T``%(`B8($@```ZRR+4Q0+@_`1
-M```-```4`(F"!(```.L6B?:+4Q0+@_`1```-```0`(F"!(```%O#B?:+1"0$
-M_[#<`0``4.A@____@\0(PX/L$&H*:@C_="0<Z&`#``"#Q!S#4X/L#(M<)!1J
-M`6H`4^C\____@\00N@````"%P'1.@^P$:"!.``!J#U/H+@,``(/$$+H`````
-MA<!T,H/L#&CH`P``Z/S___^#Q`QH($X``&H?4^@%`P``QP0D-`@``.C\____
-MN@$```"#Q!"0B="#Q`A;PY!64X/L"(MT)!2+7"08:@%J`%;H_/___X/$$+H`
-M````A<`/A)D```"+1A2Z`````(7;=`CV0P(0=`*R`8F0!)@``(/L!&@@3@``
-M:@]6Z)<"``"#Q!"Z`````(7`=&.#[`QHZ`,``.C\____@\0,:"!.``!J'U;H
-M;@(``(/$$+H`````A<!T.H/L#&@T"```Z/S___^#Q`QJ`6H`5NC\____@\00
-MN@````"%P'04@^P$:@IJ`%;H+P(``(G"@\00B?:)T(/$!%M>PU575E.#[!2+
-M;"0H_W0D+%7H_/___XG'@\00N@````"%P`^$[0$``(M5%(N":(```(/(8(F"
-M:(```(M5%(NR)(```(GP)?__?_^)@B2```"#[`QHH`\``.C\____BU44BX((
-MF```#0````B)@@B8``#'!"0*````Z/S___^#Q`A75>A."0``@\00N@````"%
-MP`^$?@$``(/L#&CH`P``Z/S___^+512+@@B8```E____]XF"")@``(/$!(M%
-M%(N86)@``(N07)@``(E4)!2+D&B8``")5"00B=J!R@``_`.)D%B8``"+512+
-M1"04)7\`P/\-@,`_`(F"7)@``(M5%(M$)!`E'P#^_PV`$0``B8)HF```:A3H
-M_/___XM5%(N"")@```T````(B8((F```QP0D"@```.C\____BT44QX#4F```
-M(0```(M5%(N"")@``"7____WB8((F```QP0DZ`,``.C\____BU44BX)@F```
-M@\@!B8)@F```@\00:@!J`6A@F```5>C\____@\0(BT44B9A8F```BT44BU0D
-M$(F07)@``(M%%(M4)`R)D&B8``!75>C\____@\00A<!U*8/L#&B($P``Z/S_
-M__^#Q`A75>C\____@\00A<!U"XM$)"1F@T@"`HGVBU44BX)H@```@^"?B8)H
-M@```BT44B;`D@```BT0D*,<``0```+H!````B?:)T(/$#%M>7UW#B?975E.+
-M?"00BW0D%(GPA?9U!;C_____B<.+1Q2)L`!```"#[`S_="0DZ/S___^#Y@^#
-MXP]64V@`0```5^C\____B<*#Q"#WQ@0```!U"HM'%,=`%`````")T%M>7\.-
-M=@!64X/L!(M,)!2*1"08B$0D`[L`````N@H````/ML"-<`&-=@"-1!(#.D0D
-M`W4:@#P1/W0,#[8$$>F>````C78`NP$```#K<9"-1!(##[;`.<9U4872?DV`
-M/!$_=#^`?`K_/W0X#[8<$0^V3`K_*<N-!)N-!("-%,4`````*<*-G!+G`P``
-MN---8A#WXXG0P>@&C1P(#[;#ZT*-=@"[`0```.L5D(/[`74/@#P1/W0)#[8$
-M$>LFC78`2@^)9?___[H`````@#P1/W0&#[8$$>L+0H/Z"G[NN`$```"#Q`1;
-M7L.-=@!55U93@^P$BUPD'(ML)"2*5"0@O_____^^_____[D`````B?:`/`L_
-M="HX%`MT3S@4"W,"B<XX%`MV&8G/@_[_=1J-1`D#B$4`#[9$"POID@```)!!
-M@_D*?LKK!8/Y"GXKN#\```"#_O]T>H/Y"GX<C40V`XA%``^V1#,+ZV>-1`D#
-MB$4`#[9$"POK68U$/@.(10`/MM(/M@PS*<J-%)*-%)*-%)*-+-4`````#[8$
-M.RG(B<&)Z)GW^8G%#[9$.PL/MDPS"RG(B>H/K]"!PN<#``"XTTUB$/?BB=#!
-MZ`8"1#,+#[;`@\0$6UY?7<.-=@"+5"0(@_H\=@6Z/````(M$)`1FB9#\`0``
-MN`$```##D%575E.#[!"+;"0DBU0D*(M\)"R);"0$9HN%<A```&;!Z`2#X`>(
-M1P^*A7(0``"#X`>(1Q!FBP(M,A0``+D`````9CV6``^'3`(``+L`````BTPD
-M!&8/MH0+>A```&8YA0@"``!T!D.#^P-VY+D`````@_L$#X0=`@``#[<*@>DR
-M%```N&=F9F;WZ<'Z`HG(P?@?B=$IP8/Y#(/1_[BKJJJJ]^&)T='IC03-````
-M`"G(C32!BT0D!(VT!GX0``"*1!X9B$<.BE0>&8I&%CC0=@*(T(A'"8I4'AF*
-M1A<XT'8"B-"(1PB*5!X9BD88.-!V`HC0B$<'C40D#U`/MD0>&5!65>CI_?__
-MB,.-1"0>4`^V1PE05E7HUOW__XA$)".#Q""-1"0-4`^V1PA05E7HOOW__XA$
-M)!*-1"0<4`^V1P=05E7HJ?W__XC"@\0@@[T``@````^$]````(N%``(``&:+
-MC`#J%@``#[94)`\/M\&#P`,YPGT'QD0D#P/K!"A,)`\/MD0D#U!65>A^_/__
-MB$<.C40D%U`/MD<.4%95Z$[]__^(PXI4)"J*1"0K@\0<.-!V`HC0B$0D#@^V
-MP%!65>A(_/__B$<)C40D%U`/MD<)4%95Z!C]__^(1"0?BE0D*8I$)"N#Q!PX
-MT'8"B-"(1"0-#[;`4%95Z!#\__^(1PB-1"074`^V1PA05E7HX/S__XA$)!Z*
-M5"0HBD0D*X/$'#C0=@*(T(A$)`P/ML!05E7HV/O__XA'!XU$)!=0#[9'!U!6
-M5>BH_/__B,*#Q!P/MD0D#]'@9HF%_@$``(I'#HA'"HA'"XA'#(A'#8C8*-"(
-M!XC8*D0D`HA'`8C8*D0D`XA'`L9'!@#&1P4`QD<$`,9'`P"Y`0```(G(@\00
-M6UY?7<.-=@!75E.#['2+O"2$````:D1H`!<``(U$)`Q0Z/S___^#Q`QJ$6C8
-M%@``C5PD7%/H_/___U/_M"28````5^@<_?__@\0<N@````"%P`^$8`(``(I$
-M)%](N@`````\!`^'3@(``(I$)&!(N@`````\!`^'/`(``+X`````C78`#[?>
-M@^P(:@4/MD0<7%#H_/___XA$'&"#Q!!&9H/^!G;?O@<```")]@^WWH/L"&H&
-M#[9$'%Q0Z/S___^(1!Q@@\001F:#_@YVWP^V1"11P>`%)>`````/ME0D4(/B
-M'PG0"00D#[94)%/!X@>!XH`````/MD0D4L'@`H/@?`G"BD0D4<#H`X/@`PG"
-M"50D!`^V5"14P>($@>+P````BD0D4]#H@^`/"<()5"0(#[94)%;!X@:!XL``
-M```/MD0D5='@@^`^"<**1"14P.@$@^`!"<()5"0,#[94)%?!X@.!XO@```"*
-M1"16P.@"@^`'"<()5"00#[94)%G!X@>!XH`````/MD0D6-'@@^!^"<**1"17
-MP.@%@^`!"<()5"04#[94)%K!X@6!XN````"*1"19T.B#X!\)P@E4)!@/ME0D
-M6\'B`X'B^````(I$)%K`Z`.#X`<)P@E4)!P/ME0D7-'B@^)^BD0D6\#H!8/@
-M`0G""50D(`^V1"1=P>`%)>`````)1"0D#[94)%[!X@.!XO@```"*1"1=P.@#
-M@^`'"<()5"0HBD0D7L#H!8/@`0E$)"R#[`AJ`P^V1"1K4.C\____P>`')8``
-M```)1"0P@\0(:@,/MD0D:U#H_/___]'H@^`#"40D-(/$"&H##[9$)&Q0Z/S_
-M___!X`*#X!P)1"0TO@````"#Q!")]HM'%`^WUHL4E(F0G)@``$9F@_X/=NJ+
-M1Q0/M]:+%)2)D-28``"Z`0```(GVB="#Q'!;7E_#C78`5E.#[`R+7"08BW0D
-M'&H%#[<.@>D`%```N&=F9F;WZ8G0P?@"P?D?*<A0Z/S____1X(/(08M3%(F"
-MG)@``(M#%,>`P)@```````")LS00``"X`0```(/$%%M>PY"+1"0$BT`4BX!D
-MF```P>@3)?\!``#VQ`%T!34`_O__F,.-=@!75E.+="00BWPD%(M&%(N08)@`
-M`(/*`HF08)@``&H`:@)H8)@``%;H_/___X/$$+H`````A<!T2;L`````C78`
-M@^P,:.@#``#H_/___U;H_/___YB#Q!1#@_L4?P>#^+A_WNL4@_BX?@]FQT<6
-M``"Z`````.L+B?9FB4<6N@$```")T%M>7\.0N`````##B?:X`````,.0D%.#
-M[`B+7"00BU0D%+@`````@_H"?QZ#[`3_="0<C012C02`C82#/!$``%!3Z/S_
-M__^#Q!"#Q`A;PXUV`%.#[`B+7"00BU0D%+@`````@_H"?QZ#[`2-!%*-!("-
-MA(,\$0``4/]T)"!3Z/S___^#Q!"#Q`A;PXUV`%575E.#[`R+;"0@BW0D)(GJ
-M@_X"=!:#_@)W"8/^`70<ZR*)]H/^`W0+ZQF0OP(```#K&9"_`0```.L1D+\`
-M````ZPF0N/_____K:)"-!'^-!("-G((\$0``N/____^#>P0`=4^#[`AJ/%/H
-M_/___XES!(/$$(-\)"@`=23'0PP+````QT,4`@```,=#&/____]FQT,@"@!F
-MQT,B"@#K$I"#[`3_="0L5U7H_/___X/$$(GX@\0,6UY?7<.04XM,)`R+5"0(
-MNP````"#^0)W28T$28T$@(V$@CP1``"[`````(-X!`!T,<=`!`````"X_O__
-M_]/`(8(<$0``(8(@$0``(8(D$0``(8(H$0``(8(L$0``NP$```")V%O#55=6
-M4XMT)!2+3"08B?.+EC00``"X`````(/Y`@^'#@(``(T$28T$@(V\ACP1``"X
-M`````(-_!``/A/(!``"X`0```(-_!`$/A>,!``#V0@(0='B+1A3'@!"```#@
-M`0``BT84QX`4@`````@`"(M&%,>`((```,^/W0&+5A2+1Q2-!$"-!(#!X!"-
-M@```#P`-X`$``(F"0(```(M&%,>`1(```,`#K@6+5A2+@D28``"#X("#R#B)
-M@D28``"+1A3'@`28```C(`!OZWJ+1A3'@!"```!H`0``BT84QX`4@`````0`
-M!(M&%,>`((```*>/W0&+;A2+5Q2-!)*-!$*-!(*-!,4P`@``P>`+#3`"``")
-MA4"```"+1A3'@$2```"8`]<$BU84BX)$F```@^"`@\@<B8)$F```BT84QX`$
-MF```(!``;[@/````@W\8_W0#BT<8BW84B<+!XA0/MT<BP>`$)?`````)P@^W
-M1R"#X`\)PH'*`"`(`(F6'(```/9'#`%T#[@!````T^`)@QP1``#K#;C^____
-MT\`A@QP1``#V1PP!=`^X`0```-/@"8,@$0``ZPVX_O___]/`(8,@$0``]D<,
-M`G0/N`$```#3X`F#)!$``.L-N/[____3P"&#)!$``/9'#`1T#[@!````T^`)
-M@R@1``#K#;C^____T\`A@R@1``#V1PP(=`^X`0```-/@"8,L$0``ZPVX_O__
-M_]/`(8,L$0``N`$```"-=@!;7E]=PXUV`(M,)`2+1"0(C01`C02`NO____^#
-MO(%`$0```74%BT$4BQ")T,.-=@"+5"0$BT0D"(M,)`R-!$"-!("+A()`$0``
-M@_@!=`Z#^`%R&8/X`W<4ZPJ)]HM"%(D(ZQ&0BT(4B4@$ZPBX`````,.)]K@!
-M````PXGV5E.#[!"+="0<5NC\____B<.#Q`@E____?U!6Z/S___^+1A2+D&2`
-M``"#Q!"#?"04`'0-N"4````IT-'H`<+K'(/Z`78#2NL4@^P(4U;H_/___[@`
-M````@\00ZQN+1A2)D&2```"#[`A35NC\____N`$```"#Q!"#Q`1;7L.-=@"+
-M5"0$BT0D"(T$0(T$@(N$@D`1``"#^`)T.H/X`G<)@_@!=`SK.HGV@_@#=`_K
-M,9"+0A3'0`@!````ZRR+0A3'0`@"````BT(4QT`H#@```.L6B?:+0A3'0"@*
-M````ZPBX`````,.)]K@!````PXGVBTPD!(M$)`B-!$"-!("Z`````(.\@4`1
-M```!=1.+012+0!0E`'@``(G"P>H+C78`B=##D%93@^P$BW0D$(M$)!2-!$"-
-M!("+A(9`$0``@_@!=`>#^`)T3>M>BT84QT`("````+L`````C78`BT84BT`4
-M]L1X=!:#[`QJ"NC\____@\000X'[YP,``'[?BT84QT`(`````('[YP,```^>
-MP`^VP.L8:@!J!&HL5NC\____@\00ZP>)]K@`````@\0$6U[#D%=64XM4)""+
-M?"0PBW0D.(M,)!2-0OV[````#(/X`78%B=/!XQJ+1"08)?\/``"+5"0HP>(2
-M"="+5"0<P>(,@>(`\`,`"=`)V/?&`0```'0%#0````'WQA````!T!0T````@
-MB<*#?"0T`'0&@<H````"B5$(@___=!N)^,'@#24`X`<`B4$,B=`-````0(E!
-M".L*B?;'00P`````D/?&!````'03@4D(``!``(M$)$`E``#X_PE!#+@!````
-M6UY?P[@`````PXGVBT0D"(%("````"##4XM,)!"+7"08BU0D#(-\)!0`=!2+
-M0@P)R(7;=0.`S!")0@SK)XUV`(7;=!"+1"0<BT`(B4((B4H,ZQ&0QT((````
-M`(G(@,P0B4(,D,="%`````#'0A``````N`$```!;PXUV`(M,)`R+5"0(N`\`
-M``#V0A0!#X2"````9HM"%"7^'P``9HD!#[="$F:)00+&000`BT(0J`%U'J@"
-M=`3&000!]D(0"'0$@$D$`O9"$`1T!H!)!`2)]HM"""4``#P`P>@2B$$%BT(4
-M)0#@'P#!Z`V(00:+0A`E``\``,'H"(A!!XM"$"7P````P>@$B$$(QD$*`,9!
-M"P"X`````,.)]L.0D)"+1"0(@$@$"+@`````PY"0@^P,BTPD$(M!%,>`T)@`
-M`!8<``"Z`````(UV`(M!%,>`@)@``````0!"@_H'?NV+012+@`"<``#!Z!B)
-MPL'J!(/@#\'@!`G0@^P(:@A0Z/S___^#Q!S#D%575E.#[!B+;"0L:.PL``#H
-M_/___XG#@\00O@(```"%P`^$.00``(G'@^P$:&P0``!H8!<``%#H_/___XM$
-M)#2)0PR+1"0XB4,0BT0D/(E#%&:)J\@!``!FQX/*`0````!FQX/\`0``/P#'
-M@P`"````````QX.H+````````,>#Q"P```````#'@\PL````!P``QX/0+```
-M_____\>#U"P``/_____'@]@L``#_____@\0(:@!3Z/S___^#Q!"^`P```(7`
-M#X25`P``9H&[R`$``!OQ=2J+0Q3'@`"B````````BT,4QX!\F```&0```(/L
-M#&CH`P``Z/S___^#Q!"+1Q2+@"!````E_P```(G"P>H$B9?,`0``@^`/9HF'
-MT`$``(/J`KX-````@_H"#X<L`P``BT<4BX`8F```9HF'T@$``(/L#%?H8P,`
-M`(/$$+X.````A<`/A`,#``"#O\P!```#=A*+1Q3'@`"8```'````ZQ"-=@"+
-M1Q3'@`"8``!'````@^P,:-`'``#H_/___XD\).@._O__9HF'U`$```^WP"7P
-M````@\00O@T```"#^!`/A:8"``"#[`2-1"0.4&C!````5^C\____@\00O@@`
-M``"%P`^$@P(``+X%````9H%\)`K_+P^&<0(``&:+1"0*9HF#;!```(M'%(N`
-M$$```(/@&,'H`[X*````@_@"#X5(`@``@^P$C40D#E!J/U?H_/___X/$$+X(
-M````A<`/A"@"``!FBT0D"F:)@VX0``"]`````+X`````B?:#[`2-1"0.4(V&
-MP````%!7Z/S___^#Q!"%P`^$Z`$```^W1"0*,<5&@?X_`P``=M"^!P```(']
-M__\```^%SP$``&;'@^(1```*`&;'@^P3```#`+X`````C01VC02&9L>$@^H1
-M```+`$:#_@EVZKX`````NLPG``!FBP1R9HF$<_03``!FB81S[A,``(T$=HT$
-MAHT$@V;'@+`4```+`&;'@!04```+`$:#_@)VRX/L"(V#;!```%!7Z/S___^#
-MQ!"^"````(7`#X1#`0``@[_,`0```W9K9H.[AA````!T88M'%,>``)@```=`
-M``"#[`QHT`<``.C\____B3PDZ%;\__]FB8?6`0``BT<4QX``F```!P```,<$
-M)-`'``#H_/___P^WA]8!```E\````(/$$+X-````@_@@#X71````ZPEFQX.&
-M$`````"#[`2-1"0.4&B_````5^C\____@\00O@@```"%P`^$HP```&:+1"0*
-M9HF#<!```&:)AP@"``#'A\`!````````@^P,5^@-`@``B3PDZ/S___^]````
-M`+X`````@\00@^P$C40D#E"X'P```"GP4%?H_/___X/$$(7`=#L/MT0D"@'%
-M9@^V1"0+B(1S*"H``&:+1"0*B(1S*2H``$:#_@)VO87M=`J)^(']_?\"`'4Y
-MO@D```#K$+X(````ZPF0O@@```"-=@"%VW0,@^P,4^C\____@\00@WPD,`!T
-M!HM$)#"),+@`````@\0,6UY?7<.)]E.#[!"+7"08C8-L$```4%/H_/___XD<
-M).C\____@\086\.)]E575E.#["R+="1`QT0D"`"```#'1"0,()@``,=$)!!5
-M5555QT0D%*JJJJK'1"089F9F9L=$)!R9F9F9OP````"-;"0(C02]`````(L<
-M*(M6%(L4&HD4!+D`````B<C!X!")P@G*BT84B108BT84BP08.=!T![@`````
-MZV%!@?G_````?M>Y`````(M4C!"+1A2)%!B+1A2+!!@YPG0*N`````#K.(UV
-M`$&#^0-^W(T$O0````"+3A2+%"B+!`2)!!%'@_\!#XYY____@^P,:F3H_/__
-M_[@!````@\00@\0L6UY?7<.-=@"+5"0,BTPD$(M$)`CVQ`%T$V;'`C@39L<!
-MU!>X`0```,.-=@"$P'D@BT0D!&:#N(80````=!)FQP(("6;'`:P*N`$```##
-MB?:X`````,.)]K@!````PXGV55=64X/L#(ML)"")[HGOC9W@`0``9H.]"`(`
-M``%U%8/L!(U$)`Q0:A!5Z/S___^#Q!")]L=#!`````!F@[Z"$````'0;QT,$
-M`0```&:#OG(0````=0K'0P0#````C78`9H.^AA````!T!(-+!`1FQT,0"`EF
-MQT,2K`IFQT,,.!-FQT,.U!>`"P.*0P*#R`-FQT,("@!FQT,*@`"#X)^(0P)F
-M@[YV$````'0I@^P$C8=($```4&H/5>C\____@\00A<!T$,>'3!````$```"`
-M2P*`B?;'0Q0-````QX=H$````0```+@!````@\0,6UY?7<.0D%.+3"0(BUPD
-M#(M1%(M#!(F"*(```(M1%(M##(F"+(```(M1%(M#$(F",(```(M1%(M#"(F"
-M-(```(M1%(L#B8(@@```6\.)]H/L+(M,)#"+5"0TB50D!(N!W`$``(/X`702
-M@_@!<B&#^`9T'(/X"'4UC78`QT0D#/__``#'1"00__\'`.L@B?:)T"L%````
-M`,'@`XE$)`R)T"L%`````,'@`XE$)!"-0@&)1"0(BT0D."7__X`!B00DB>!0
-M4>C\____@\0TPXGVBU0D!(M"%,>`*(````````"+2A2+@02````-```$`"7_
-M_\__B8$$@```BT(4QX`@@```__\``,-75E.+3"00BUPD%(G/9H-[$@!T0(M1
-M%(N"!(````T``!``B8($@```BU$4#[=#$(F")(```(M1%`^W0Q*)@CB```"+
-M412+0Q3!X`.)@C"```#K%9"+412+@@2````E___O_XF"!(```(M1%(L#B8(H
-M@```BW$4BX8@@```)0``@/\/MU,("<)F@WL8`'01#[=#&(/`!,'@$"4``'\`
-M"<*)EB"```"+E\PL```P]@^W0QK!X`@E`/\```G"B9?,+```BT$4B9`8@```
-MBTD4BY$$0```@>(``/__BT,<@^@#P>`#)?__```)PHF1!$```%M>7\.0BT0D
-M!(M`%(N`"$```(7`#Y7`#[;`PXGV4XM<)`B+3"0,BT,4BY#`````@_K_=1''
-M`0````"X`````.F1````D(G0);K8!0&)`??"```(`'0'#0```$")`?;"!70#
-M@PD!]\+`!0``=`.#"4#VPB!T$(.[:!````!T!X$)````0)#V00-`=$6)DU`0
-M``"+4Q2+@L0```")@U00``"+@L@```")@U@0``"+@LP```")@UP0``"+@M``
-M``")@V`0``"+@M0```")@V00``"X`0```%O#B?:+1"0$BX`T*@``PY!75E.+
-M="00BUPD%(GQB[XT*@``A?]Y$8M&%,=`)`````"+1A2+0"20B=J!XKK8!0'V
-MPT!T,X.Y."H```!T`X/*0(.Y/"H```!T`X#.`8.Y0"H```!T`X#*@(.Y1"H`
-M``!T!H#.!(UV`/;#`70#@\H']\,```!`=`:!R@``"`"+1A2)D*````")F30J
-M``"%VWD+BT84QT`D`0```)")^%M>7\.0D+B`````PXGVBT0D"&:#^']W'0^W
-MP,'@!8M4)`0#0A2+@!R(``"Z`0```&:%P'@%N@````")T,.0BTPD!(M$)`BZ
-M`````&:#^'\/AX$````/M\#!X`6)P@-1%,>"`(@```````")P@-1%,>"!(@`
-M``````")P@-1%,>""(@```````")P@-1%,>"#(@```````")P@-1%,>"$(@`
-M``````")P@-1%,>"%(@```````")P@-1%,>"&(@````````#013'@!R(````
-M````N@$```")T,.05U93BWPD$(M4)!B+="04N`````!F@_Y_=VJ%TG0X#[9:
-M!<'C"`^V0@0)PP^V2@/!X1@/MD("P>`0"<$/MD(!P>`("<$/M@()P='IB=C!
-MX!\)P='KZPJ[`````+D`````#[?&P>`%B<(#5Q2)BAB(```#1Q2)VH#.@(F0
-M'(@``+@!````6UY?PU575E.#[!"+?"0LBT0D*&:)1"0.@WPD-`$9R??1@>&J
-MJJJJN`````!F@WPD#G\/AWP!```/M@>#^`%T%(/X`7\'A<!T%.M-D(/X!70\
-MZT60QP0D!0```.M'N`````!F@W\"!`^&1P$``,<$)`````!F@W\"!78I9H-_
-M`@X9TH/B_H/"`XD4).L7QP0D!P```.L.B?:X`````.D2`0``B?8/MF\$#[9'
-M!<'@"`G%#[9'!L'@$`G%#[9'!\'@&`G%,<T/MD<)P>`(#[97"`G",<J!XO__
-M``")5"0(#[9W"@^V1PO!X`@)Q@^V1PS!X!`)Q@^V1PW!X!@)QC'.#[9'#\'@
-M"`^V5PX)PC'*@>+__P``B50D!`^V7Q`/MD<1P>`("<,/MD<2P>`0"<,/MD<3
-MP>`8"<,QRV:#?P(-=P:!X_\````/MTPD#HG(P>`%B<*+?"0D`U<4B:H`B```
-MB<(#5Q2+?"0(B;H$B```B<*+?"0D`U<4B;((B```B<(#5Q2+="0$B;(,B```
-MB<(#5Q2)FA"(```#1Q2+/"2)N!2(``#_="0P4?]T)"SH_/___X/$#(/$$%M>
-M7UW#@^P0:@:+1"08!2@J``!0_W0D(.C\____@\0<PX/L$&H&_W0D'(M$)!P%
-M*"H``%#H_/___[@!````@\0<PXUV`(/L$&H&:.`G``#_="0@Z/S___^#Q!S#
-MD+@`````PXGV4X/L"(M<)!"+4Q2+1"04B8(`8```BT,4QX`(8````0```&H"
-M:@-H#&```%/H_/___X/$$+H`````A<!T%8M#%(N0!&```(M$)!AFB1"Z`0``
-M`(G0@\0(6\.-=@!3BUPD$(M,)`BZ#````(M$)`QF.8$(`@``=!.*@6X0``"#
-MX(`\`1G2@^+X@\(+A=MT`HD3N`````!;PY"+5"0$N`````!F@[J"$````'0.
-M9H.Z<A````$9P(/@0D!F@[J&$````'0#@\@$PY!75E.+?"009HN?2!```(G>
-M@^8<P?X"@^,"T?N#[`A65^C\____BU<4BX(`F```@,P@B8(`F```@\0(5E?H
-M_/___X/$##G8#Y7`#[;`4%97Z/S___^#Q!!;7E_#D%.+1"0(BU@4BY,40```
-MBTPD#-'AN`,```#3X`G"B9,40```N`$```!;PXGV4XM$)`B+6!2+DQ1```"+
-M3"0,T>&X`P```-/@]]`APHF3%$```+@!````6\-3BTPD#(M$)`B+6!2+DQA`
-M``"X_O___]/`(<*+1"00@^`!T^`)PHF3&$```+@!````6\.0BTPD"+C_____
-M@_D%=Q6+1"0$BT`4BX`<0```@^`OT^B#X`'#@^P,BTPD$(M!%(N0%$```('B
-M_'_^_X#.@(-\)!@`=`:!R@```0"+012)D!1```"#[`B+@30J```-`````5!1
-MZ/S___^#Q!S#BT0D!(M(%(N!$$```"6?__'_BU0D"(/B!PL$E0`H``")@1!`
-M``##D%93@^P(BUPD%(MT)!QJ!O]T)!R-@RXJ``!0Z/S___^+2Q0/MI,N*@``
-M#[:#+RH``,'@"`G"#[:#,"H``,'@$`G"#[:#,2H``,'@&`G"B9$(@```BTL4
-M#[:#,RH``,'@"`^VDS(J```)PH'F_S\``,'F$`GRB9$,@```@\046U[#4XM$
-M)`B+0!2+B$R```"+D%"```"+F$R````YRX/2`+@`````B=F[``````G("=I;
-MPXUV`(M$)`2+0!2+@$R```##B?:+1"0$BU`4BX(@@```#0````&)@B"```##
-MC78`BU0D!(M"%(N`9)@``(G!P>D3@>'_`0``]L4!=`:!\0#^__^+4A2+@E"`
-M``"+DDR````QT#'(PY!3BU0D"(M"%(N`($```"7_````B<&#X0^[`````,'H
-M!#F"S`$``'4,9CF*T`$``'4#LP&0B=A;PXM,)`2+1"0(BU$4BY*0@````1"+
-M412+DHR````!4`2+412+DI2````!4`R+412+DHB````!4`B+412+DIB````!
-M4!##5U93BWPD$(MT)!2)^X/^"'86@^P(:/__``!7Z/S___^#Q!`Y\',.D(FS
-MT"P``+@`````ZR.#[`A65^C\____BU<4B8)P$```@\00B;?0+```N`$```")
-M]EM>7\.#[!2+5"08BT(4BX!P$```)?__``!04NC\____@\0<PU575E.#[!2+
-M;"0H:/\?``!5Z/S___^#Q!`[1"0D<Q''A=0L``#_____N`````#K/(MU%(N>
-M%(```('C`.#__X/L"/]T)"Q5Z/S___\E_Q\```G#B9X4@```@\00BT0D)(F%
-MU"P``+@!````D(/$#%M>7UW#@^P4BU0D&(M"%(N`%(```"7_'P``4%+H_/__
-M_X/$',.+1"0$#[:`QRP``(/P`8/@`<.)]HM$)`2)P8-\)`@`=".+4!2+@@2`
-M```E_____HF"!(```(&AQ"P``/____[K(8UV`(M0%(N"!(````T````!B8($
-M@```@8G$+````````;@!````PU575E.#[!2+;"0H:/\?``!5Z/S___^#Q!`[
-M1"0D<Q''A=@L``#_____N`````#K0(MU%(N>%(```('C__\`X(/L"/]T)"Q5
-MZ/S____!X!`E``#_'PG#B9X4@```@\00BT0D)(F%V"P``+@!````B?:#Q`Q;
-M7E]=PX/L%(M4)!B+0A2+@!2````E``#_'\'H$%!2Z/S___^#Q!S#D+@!````
-MPXGVPXUV`+@`````PXGVPXUV`,.-=@"+1"0$BT`4BX`<G```)?\```##D(M$
-M)`2+0!2+@%B```"#X`?#C78`BT0D!(M0%(M$)`B#X`>)@EB```##C78`BT0D
-M!(N`J"P``,.0@^P,BU0D$(M,)!2+@C00``"%P'4+B8JH+```L`'K#Y"#[`10
-M45+H_/___X/$$(/$#,.)]H/L#(M$)!2+5"08@_@!=12#^@%V![`-@_H%=1JX
-M`````.L3D/]T)!Q24/]T)!SH_/___X/$$(/$#,.)]H/L#(M$)!"+3"04BU0D
-M'(/Y"W4<@^(&B9#X`0``BT`4B9!(@```N`$```#K&8UV`(/L#/]T)"Q2_W0D
-M+%%0Z/S___^#Q""#Q`S#B?:#[!3_="0L_W0D+/]T)"S_="0L_W0D+/]T)"SH
-M_/___X7`#Y7`#[;`@\0LPU93@^P$BW0D$(-\)!0`='"+5A2+@@1````E___\
-M_XF"!$```(/L#&H*Z/S___^["@```(/$$(GVBT84BX`00```J0```0!T*8/L
-M#&C(````Z/S___^+5A2+@@1````E___\_XF"!$```(/$$$MUR>L'A=MU"XUV
-M`+@`````ZQJ0BU84BX($@```)?__^_^)@@2```"X`0```(/$!%M>PY"+3"0$
-MBU$4BX($@```#0``!`")@@2```"#?"0(`'04BU$4BX($0```)?___/^)@@1`
-M``##BTPD!(M1%(N"!(````T```0`B8($@```@WPD"`!T%(M1%(N"!$```"7_
-M__S_B8($0```PU=64XM$)!"+7"04BU0D&(G&OP$```"#^P%T(8/[`7((@_L"
-M="/K+9"#[`A24.C&_O__B<>#Q!#K(XUV`%)0Z%7___^#Q`CK%%)0Z'W___^#
-MQ`CK"+@`````ZPF0B9ZD+```B?A;7E_#BT0D!(M`%(N`!$```"4```,`P>@0
-MPY"04X/L"(M$)!2#^`)T)X/X`G<*@_@!=`WK(XUV`(/X!'0+ZQF0NP````#K
-M&9"[`````.L1D+L`````ZPF0N`````#K$Y"#[`A3_W0D'.C\____B=B#Q!"#
-MQ`A;PY"+1"0$BT`4BT`,PY"+1"0$BU`4BT0D"(E"#,.0BT0D!(M`%,=`"`0`
-M``##D(/L#(M4)!"+0A3'0`@@````:@!J!&H(4NC\____A<`/E<`/ML"#Q!S#
-MC78`BT0D!(M0%(N"2(```(/@WXF"2(```,.0BT0D!(M0%(N"2(```(/(((F"
-M2(```,.0BTPD!(M1%(M$)`B)@D"```"+412+1"0,B8)$@```PY!3BU0D"(M,
-M)`RX`````(/Y/W="@_D?=B"+4A2+FD2```"#Z2"X_O___]/`(=B)@D2```#K
-M&XUV`(M2%(N:0(```+C^____T\`AV(F"0(```+@!````6\.04XM4)`B+3"0,
-MN`````"#^3]W0H/Y'W8@BU(4BYI$@```@^D@N`$```#3X`G8B8)$@```ZQN-
-M=@"+4A2+FD"```"X`0```-/@"=B)@D"```"X`0```%O#D(M$)`2+0!2+@#R`
-M``##B?:+1"0$BU`4BT0D"(F"/(```,.)]HM4)`R+3"0(QT$(`````(G0)?\/
-M``")00RX`````#E1#'4A]D0D$"!T!X%)#``@``#'010`````QT$0`````+@!
-M````PXUV`%.+3"0@BU0D#(M$)!2[#P```/9"%`$/A,4```#V0!0!=1F+1"0(
-MBT`4BT`,NP\````[1"00#X2F````9HM"$"7_#P``9HD!BT(4)0"`_P_!Z`]F
-MB4$"QD$$`(M"%*@"=2NH!'0'QD$$`>LAD/9"%!!T!H!)!`CK%(!)!`*+0A0E
-MX````,'H!8A!!8GVBT(0)0``^`?!Z!.(00:+0A3VQ`%T#B4`?@``P>@)B$$'
-MZP60QD$'_XM"$"4`@`<`P>@/B$$(BT(0)0```#C!Z!N(00F+0A#!Z`R#X`&(
-M00J[`````(G86\.0D)!55U93@^QLBZPD@````(EL)"1FQT0D%@``9L=$)!0`
-M`,=$)!``````QT0D#`````"+E"2(````#[="`HG"P>H'P>@(,="Z#````*@!
-M#X1N"```BXPDB`````^W00*)PL'J!L'H!3'0N@P```"H`0^$3`@``(/L"/^T
-M))````!5Z/S___^)1"0P@\00N@P```"%P`^$*`@``(.\)(0````&="J#O"2$
-M````!G<,@[PDA`````%W#.L4@[PDA`````AT"KH,````Z?0'``"#O"2,````
-M`'1SBT44BYA,@```B5PD$(N04(```(E4)`R#O<P!```#=@R+@$`1``")1"0P
-MZR"^`````(M5%(T$M0````"+A`)`$0``B42T,$:#_@EVZ(M,)"#V000"=02`
-M803^BUPD(&:+0P*+E"2(````9HE"`HI#!(A"!(M%%(N`6(```(E$)`B%P'4(
-MQT0D"`$```"+512+@@2````E`````HE$)!B+@A!````E8`#^`(E$)!R+BA1`
-M``")3"0LBY(80```B50D*(/L"(N<))`````/MT,"4%7H_/___X/$$+H#````
-MA<`/A`0'``"+E"2(````#[="`B7P`0``/<````!T4#W`````?PD]H````'0R
-MZTX]0`$``'0)/5`!``!T$NL^9L=$)!8!`&;'1"04`0#K+F;'1"06`@!FQT0D
-M%`$`ZQYFQT0D%@,`9L=$)!0"`.L.9L=$)!8$`&;'1"04`@"#O<P!```#=@^+
-M113'@`"8```'````ZPV+113'@`"8``!'````@[W,`0```P^&X@```(N,)(@`
-M``"`>0(`#XFG````BUPD)&:!NVP0````,`^&E````/9!`B!T%`^WNV@1```/
-MMX-L$0``B40D!.L6BU0D)`^WNFH1```/MXIN$0``B4PD!(/L"&H#5^C\____
-MB<>#Q`AJ`_]T)!#H_/___XE$)!0/MUPD)+DL0P``BQ29@.(_B?C!X`8EP```
-M``G"B129OCA#``"+#)Z#X?")^L'J`H/B`8M$)!31X(/@#@G""=&)#)Z#Q!"^
-M`````+\`0@``#[=<)!2-!':+312+%(4`0@```=B+!(>)!!%&@_X;=N6#[`C_
-MM"20````5>C_#```O@````"#Q!"_("@```^W7"06D(T$MHM-%(L4A2`H```!
-MV(L$AXD$$4:#_B)VY;X`````OT`P```/MUPD%(GVC01VBTT4BQ2%0#````'8
-MBP2'B0011H/^/W;EO@````"[X"H``+_D*@``B?:+#/.#O"2,`````'0-C8$`
-M@/__/?\/``!V"8M5%(L$]XD$"D:!_JH```!VU(.]S`$```-W1(M5%(N*'(``
-M`(G()?__#P`-``#0`8F"'(```(M%%,=`7`````"+113'@'B8```(````BU44
-MBX)(@```@,P$B8)(@```@[PDC`````!T5(M%%(M<)!")F$R```"+112+5"0,
-MB9!0@```O@````"#O<P!```#=A&+512+1"0PB8)`$0``ZQV)]HT,M0````"+
-M512+1+0PB80*0!$``$:#_@EVY8M-%(M<)"0/MI,H*@``#[:#*2H``,'@"`G"
-M#[:#*BH``,'@$`G"#[:#*RH``,'@&`G"B9$`@```BTT4#[:3+2H``,'B"`^V
-M@RPJ```)T`M$)!B)@02```"#[`C_M"2,````5>@M(P``BU44BX(00```"T0D
-M+(F"$$```(/$$(M%%(M4)"R)D!1```"+112+3"0HB8@80```BT44BUPD"(F8
-M6(```(M-%(M$)"0/MI`N*@``#[:`+RH``,'@"`G"BUPD)`^V@S`J``#!X!`)
-MP@^V@S$J``#!X!@)PHF1"(```(M-%`^VDS,J``#!X@@/MH,R*@``"=")@0R`
-M``"+512+@\PL``")@AB```"+113'@(````#_____@[W,`0``!'469H.]T`$`
-M``%W#(M5%(M"%(#,!(E"%(/L"/^T))````!5Z/S___^#Q!"Z`P```(7`#X31
-M`@``@[PDA`````9T)XN%!`(``*@#=!V+312+D429``"!XO___]^#X`'!X!T)
-MPHF11)D``(/L"/^T))````!5Z,0.``"#Q`C_="0H5>A[!@``@\00N@,```"%
-MP`^$<P(``&:!O<@!```;\74:BX0DB````(!X`@!Y#8M%%,>`"-@```(%``"+
-M113'@!R8```!````BT44BX`4F0``B<&!X?\_``"+E"2(````]D("('05C12-
-M`````+BCBRZZ]^*)T,'H!.L,N,W,S,SWX8G0P>@#@^P,@\!D4.C\____BU44
-MBX)@F```@\@!B8)@F```@\00:@!J`6A@F```5>C\____@\0(_W0D*%7H_/__
-M_X/$$(7`=1R+C"2(````]D$"('4%9H-)`@*Z`P```.FB`0``BUPD)(.[K"P`
-M``!T%XM%%,>`()D```#P`0#'@[`L```!````NP````"^`0```(T\G0````"+
-M512)\(C9T^")A#H`$```0X/["7[CNP````"#[`A35>C\____@\000X/["7[M
-MBT44QX"D`````0`!`(M%%,>`J`````$```"+113'@*P````!````BU44BX*P
-M$```B8*P$```BT44QX"@````90D(`(M<)"3'@S0J``!E"0@`BU44BX*L````
-M#0``!P")@JP```"#O"2$````!G4<BU44BX*@````@,P0B8*@````@8LT*@``
-M`!```(.]3!````!T#(/L#%7H_/___X/$$(M5%(N"((```"7__W_^B8(@@```
-MBT0D)(.XT"P``/]T$H/L"/^PT"P``%7H_/___X/$$(M4)"2#NM0L``#_=!*#
-M[`C_LM0L``!5Z/S___^#Q!"+3"0D@[G8+```_W02@^P(_['8+```5>C\____
-M@\00@[WX`0```'0/BU44BX7X`0``B8)(@```BYPDA````(F=W`$``+@!````
-MZQ6)]HN$))````"#.`!T`HD0N`````"#Q&Q;7E]=PY"#[!1J`O]T)!SH;@,`
-M`(/$',.)]E.#[`R+7"04:@%J`%/H_/___X/$$+H`````A<!T+H/L"&H34^@_
-M`P``@\00N@````"%P'07@^P,:#0(``#H_/___[H!````@\00B?:)T(/$"%O#
-MD%93@^P(BUPD%(MT)!AJ`6H`4^C\____@\00N@````"%P`^$B0$``(GP)?`!
-M```]P`````^$AP```#W`````?Q0]H````'0[/;````!T-.D-`0``D#U``0``
-M#X2H````/4`!``!_##W0````=%/I[@```#U0`0``#X2*````Z=X```"+0Q3'
-M@`28````````BT,4QX``H@```P```(M#%,>`?)@``!D```"#[`QH+`$``.C\
-M____@\00Z:(```")]HM#%,>`!)@```````!F@[O(`0``$@^%A0```(M#%,>`
-M?)@``!@```"#[`QH+`$``.C\____BT,4QX``H@```@```(/$$.M9]\80````
-M=`^+0Q3'@`28```#````ZPV+0Q3'@`28````````9H.[R`$``!)U*XM#%,>`
-M?)@``!@```"#[`QH+`$``.C\____BT,4QX``H@```````(/$$)"#[`AJ$U/H
-MJ0$``(/$$+H`````A<!T.8/L#&@T"```Z/S___^#Q`QJ`6H`4^C\____@\00
-MN@````"%P'03@^P(:@!3Z&P!``")PH/$$(UV`(G0@\0$6U[#55=64X/L)(M\
-M)#B)_O]T)#Q7Z/S___^)PX/$$+@`````A=L/A"L!``"#O[`L````#X2.````
-MBT<4BX`@F0``J0```0!U?L>'L"P```````"+;Q2+A1"<``")1"04BX44G```
-MBY48G```B50D&(M4)!31ZHG!T>D!RHG!P>D&P>H'B50D#'0]A<ET.8M$)!CW
-MV)GW?"0,@^`_B40D$(M$)!29]_F)P8/A'XM$)!#!X`6+E2"9```)T`G(@,P(
-MB84@F0``D(/L"%-7Z#H#``"#Q!"%P'43BU0D-&:#2@("9H-C`OWK;XUV`(/L
-M"%-7Z/S___^#Q!"%P'4W@^P,:(@3``#H_/___X/$"%-7Z/S___^#Q!"%P'49
-MBT0D-/9``B!U!6:#2`("N`````#K)XUV`(/L#%?HOQD``(/$$(.^L"P````/
-ME,(/MM*+1"0XB1"X`0```(/$'%M>7UW#5U93BWPD$(MT)!2)\(7V=06X____
-M_XG#BT<4BU`,B;``0```@^P,:@_H_/___X/F`X/C`U93:`!```!7Z/S___^)
-MPH/$(/?&`0```'4*BT<4QT`4`````(G06UY?PXGV55=64X/L$(ML)"@/MT4"
-M4`^W10!0_W0D+.C\____@\00O@````"`?0(`>3P/O_B-''_!XP*-NR0T``"#
-M[`AJ"/]W!.C\____B<:!YO\```#!Y@6+@R0T``#!X`0)QF:+1PB#Q!"-=@!F
-M/9``?P2H`70B@^P(:@B8@^@84.C\____B<.!X_\```"X`0```(/$$.LID(/L
-M"&H(F(/H&(G"P>H?`=#1^%#H_/___XG#@>/_````N`````"#Q!#!XP+1X`G#
-M@<L!!```BT0D((M(%(GP)?\```#!X`@/MM,)T(F!G)@``(M$)""+2!2)\"4`
-M_P``#[;7"=")@="8``"+1"0@B:@T$```N`$```"#Q`Q;7E]=PXUV`(M$)`2+
-M0!2+@&28``#!Z!,E_P$``/;$`70%-0#^__^8PXUV`%=64XM\)!"*7"04BT\4
-MBY%DF```@>(`\/__B=C!X`DE``X```G"#[]$)!@E_P$```G"B9%DF```BU<4
-MBX)@F```@\@"B8)@F```OC@```"$VW01#[;SC03U`````"GPB<;!Y@F[````
-M`(UV`(M'%(N`8)@``*@"=!2#[`Q6Z/S___^#Q!!#@_L[?N'K!8/[.WX'N```
-M``#K"E?H/?___YB#Q`1;7E_#D(M,)`R+5"0$BT0D"`^W0`(EX`$``#W`````
-M=#`]P````'\)/:````!T%NLL/4`!``!U)6:+@L@0``!FB0'K(9!FBX+*$```
-M9HD!ZQ1FBX+,$```9HD!ZPBX`````,.)]K@!````PXGV5E.#[`2+7"00BW0D
-M%(U$)`)05E/H?____X/$#+H`````A<!T+XM#%(N`8)@``%/HF/[__X/$!&8[
-M1"0"?@5F@TX"`F:)1A9F.T0D`@^>P`^VT(GVB="#Q`1;7L-75E.#[!"+7"0@
-MBW0D)(.[S`$```-W:8/L"%93Z/S___^#Q!"%P'18C40D#E!64^@(____@\0,
-MN@````"%P'17OP````"#[`1J``^VAV@U``!04^@\_O__@\009CM$)`Y^"&;'
-M1A8``.L$9HE&%D>#_P)VT8/_`P^6P`^VT.L8D(M3%(N"8)@``(/(`HF"8)@`
-M`+H!````B="#Q!!;7E_#4[H`````BT0D#&:+`(G!9CL%@#4``'</N(`U``"-
-M=@!"9CL,D';Y9HL<E8(U```/O].-!)*-!(*-!(*)P<'A"`'(`=#!Z!!FP?L/
-M9BG8F%O#C78`55=64X/L/(M4)%2+1"10B40D+(!Z`@`/F<!F#[;`9HE$)`BX
-M`@```&8K1"0(9HE$)`@/MT(")>`!```]P`````^$Q@$``#W`````?Q`]H```
-M``^$9P$``.G\`0``/4`!```/A?$!``!FBP(MH0\``&8]Z@1W)8M4)"QFBY)0
-M$0``9HE4)`R+="0L9HNV4A$``&:)="0*Z9<```!FBP(MC!0``&8][P!W(HM$
-M)"QFBX!4$0``9HE$)`R+5"0L9HN25A$``&:)5"0*ZV=FBP(M?!4``&8]X`!W
-M(HMT)"QFB[98$0``9HET)`R+1"0L9HN`6A$``&:)1"0*ZS=F@3I<%G8BBU0D
-M+&:+DEP1``!FB50D#(MT)"QFB[9>$0``9HET)`KK#F;'1"0*``!FQT0D#```
-MBT0D+&:+J-00``!FBY#:$```9HE4)!!F@[C:$`````^4P&8/ML!FB40D#@^W
-M3"0(NYQ#``"+%(N!XO___^^+="0L#[>&R!$``,'@'`G"B12+NZA#``"+%(N!
-MXO____L/MX;*$0``P>`:"<*)%(N[7$0``(L4BX/B]P^WAL81``#!X`,)PHD4
-MB^FD````BT0D+&:+@&`1``!FB40D#(M4)"QFBY)B$0``9HE4)`J+="0L9HNN
-MUA```&:+AMP0``!FB40D$&:#OMP0````#Y3`9@^VP&:)1"0.ZU>+5"0L9HN2
-M9!$``&:)5"0,BW0D+&:+MF81``!FB70D"HM$)"QFBZC8$```9HN0WA```&:)
-M5"009H.XWA`````/E,!F#[;`9HE$)`[K"K@`````Z1,!```/MW0D"+_D0P``
-MBQRW@.,_@^P(:@0/M^U5Z/S____!X`</MU0D'L'B!@G0)<`````)PXD<M[_P
-M0P``BQRW@^/X@\0(:@15Z/S____1Z(/@!PG#B1RW@.-_@\0(:@,/MVPD&%7H
-M_/___\'@!R6`````"<.)'+>__$,``(L<MX/C_(/$"&H#5>C\____T>B#X`,)
-MPXD<MX/CXX/$"&H##[=$)!90Z/S____!X`*#X!P)PXD<M[DL1```BQ2Q@^+W
-MBT0D(,'@`X/@"`G"B12QNP````"#Q!"_8$,```^W="0(B?:-!%N+5"10BTH4
-MBQ2%8$,```'PBP2'B0010X/[&';ABW0D+,>&O"P```````"X`0```(/$/%M>
-M7UW#B?955U93BWPD%(ML)!B)^XM$)!P/MT`")>`!```]P````'0J/<````!_
-M"SV@````=!3K(HGVO@`````]0`$``'0@ZQ*)]KX!````ZQ60O@(```#K#9"X
-M`````.F[````B?8/MXQSYA````^WA'/L$```P>`&"<$/MX1S\A```,'@#`G!
-M#[>$<_@0``#!X!()P0^WA'/^$```P>`8"<$/MY1S!!$```^WA',*$0``P>`&
-M"<(/MX1S$!$``,'@#`G"#[>$<Q81``#!X!()P@^WA',<$0``P>`8"<*#_0%T
-M#X/]`7(:@_T"=`GK"XUV`(G*ZPR)T>L(N`````#K'I")JZ@L``"+1Q2)B&"9
-M``"+1Q2)D&29``"X`0```%M>7UW#B?955U93BWPD%(G^BU0D&`^W0@(EX`$`
-M`#W`````=$H]P````'\+/:````!T-.M"B?8]0`$``'4YO0````"+3Q2+D429
-M``"#XL</MX?,$0``P>`#@^`X"<*)D429``#K'9"]`0```.L5D+T"````ZPV0
-MN`````#ITP$``(GV@[_,`0```W<7BU<4BX(0F0``@\@#B8(0F0``ZU.-=@"+
-M3Q2+@1"9```E!OS__P^WE&[@$```P>($"="#R`&)@1"9``#_="08_[:H+```
-M5^C\____BU<4#[^$;L@0```E_P$``(#,`HF":)D``(/$#(M/%(N11)@``('B
-M?\#__P^WA&Z>$```P>`')8`_```)PHF11)@``(M/%(N12)@``('B_P_\_P^W
-MA&ZD$```P>`,)0#P`P`)PHF12)@``(M/%(N14)@``('B``#__P^^A#7%$```
-MP>`()0#_```)P@^VA#7"$```"<*)D5"8``"+7Q0/MY1NMA```(G0P>`8P>(0
-M"=`/MXQNO!```(G*P>(("=`)R(F#-)@``(M/%(N1*)@``##V#[>$;JH0``#!
-MX`@)PHF1*)@``(M/%(N19)@``('B_P_X_P^WA&ZP$```P>`,)0#P!P`)PHF1
-M9)@``+L"````9H&^;!````(P=QQF@;_*`0``(A!U-8M$)!CV0`)`="NS".LG
-MC78`BU0D&&:+`H/@'P^WP(7`=!.#Z`J#^`QV"P^WA&XB$0```<.0BT\4BY$D
-MF0``@.(!C00;)?<````)PHF1))D``+@!````6UY?7<.)]HM,)`2+5"0(B="#
-M^C]V!;@_````9HF!_`$``(M!%(F0/)D``+@!````PXGV55=64X/L+(M\)$2+
-M7"1`#[='`B7@`0``/<````!T5CW`````?PX]H````'1[Z:H```")]CU``0``
-M#X6=````9HN#XA$``&:)1"04C8/.$0``B40D$(V#Y!$``(E$)!@/MX-&%0``
-MB40D"(VK2!4``.F#````9HN#[!,``&:)1"04C8/N$P``B40D$(V##A0``(E$
-M)!@/MX.8%0``B40D"(VKFA4``.M09HN#[!,``&:)1"04C8/T$P``B40D$(V#
-MJA0``(E$)!@/MX.X%0``B40D"(VKNA4``.L=D+@`````Z98```")T,'@!HV<
-M&-`5``")7"0,ZV2#[`0/MP=0C40D&%#_="1,Z'<```#'1"0<`````(/$"%?_
-M="1,Z/S___^)QKH`````@\009H.[<!$```!T)@^WBW`1``"-=@!F@[Q3<A$`
-M``!T#`^WA%-R$0``.?!TCT(YT7_D@^P,5P^W1"084%7_="0D_W0D7.A4`P``
-MN`$```"#Q""#Q"Q;7E]=PU575E.#[#2+7"109L=$)"X``&;'1"0L/P!H"`$`
-M`&@`````Z/S___^#Q`AH@````&@@`0``Z/S___^]B````+\!````O@````"#
-MQ!`/M\9FB;P`"````$=&9H/_/W;M9HDU!@```&;'!0(````!`&;'!00````_
-M`+X`````9H,]!@````!V+@^W^P^WWH/L!/]T)$@/MX0;"````%!7Z*D'``!F
-MB41=`(/$$$9F.34&````=]5FBTT`#[<%!@```&:+7$7^O@````!F@ST&````
-M`'9V#[?&9CE,10!_"F:+3$4`9HET)":)\/?0B<=F`ST&````=",/M]=FBT15
-M_F8[1%4`?@IFBT15`&:)1%7^1F8Y-08```!WNKX`````9H,]!@````!V(6:+
-M%08````/M\9F.5Q%`'X*9HM<10!FB70D)$9F.?)WY@^_R8/!&;L?A>M1B<CW
-MZXG0P?@$P?D?*<B-!("-!("--`!FQT0D(@``OP`````/O\Z)3"0<B<CWZXE$
-M)!")5"04BT0D%,'X!,'Y'RG(0(7`?CJY(`$``+@?A>M1]VPD'(G3P?L$BT0D
-M')F)V"G0C5`!#[=$)")FBUPD)F:)'$%F_T0D(D</M\<YT'SEOP`````/MP4&
-M````B<)F.71%_@^.V0```(/&,HE4)!AF.715_GY9#[_.B<L/M\>)1"0,#[]$
-M10")RBG"B50D$(M$)`P/OU1%`BG1BT0D$`^OP87`?BI'BU0D&&8Y=%7^?AX/
-MM]</OT15`(G9*<&)R`^_5%4"B=DIT0^OP87`?]:#[`AJ``^WUP^WA!(*````
-MT>`/M\!0#[>$$@@```#1X`^WP%`/MT15`E`/MT15`%`/M\90Z)$'``!`#[=4
-M)$*Y(`$``&;1Z&:)!%&#Q""+7"0D9CG8=@1FB1Q19O]$)"(/MQ4&````9CET
-M5?X/CR?___]F@WPD(C]W)+L@`0``N1X!```/MU0D(F:+!%%FB0139O]$)")F
-M@WPD(C]VYKF`H0``OP````"^(@$``+L@`0``#[?'#[<4AL'B&('*``#_``^W
-M!(/!X`@,_R7__P``"<*+;"1`BT44B10(@\$$1V:#_Q]VS(/$+%M>7UW#55=6
-M4X/L/(MT)%R+1"10B40D&&;'1"06``!FQT0D%```9L=$)!(``&;'1"00``!F
-MQT0D#C\`9L=$)`H``+^@`0``BU0D8`^^0@71X&:)1"0,]D(#`706BTPD4(J!
-MBA```.L49HE<)!+I6`$``(M4)!B*@HL0``"#[`0/OL!0_W0D:/]T)%SH_/__
-M_XA$)!F#Q!"#?"14``^$HP```+L`````B?8/M].+3"149H,\T0!T$&:+!-%F
-MB414($-F@_L'=N*)W8/L#(U$)"I0C40D+%`/M\-0C40D.%"+5"1\#[<"4.C=
-M!@``NP````"#Q"!F.>MS%(M4)!P/M\-F.51$('0&0V8YZW+PBT0D'&8[1"0>
-M=0Z+3"1@9HL!9CM$)!QT#@^WPXM4)%2#?,($`'01#[?#BTPD5&:+1,$"9HE$
-M)`Z[`````&8Y\W,<B?8/M\.-%("+3"189HM440AFB51$($-F.?-RYH/L#(U$
-M)"I0C40D+%`/M\90C40D.%"+5"1\#[<"4.@[!@``NP````"#Q"!F.?-S+XGV
-M#[?#9HM$1"!F.T0D''4%9HE<)!8/M\-FBT1$(&8[1"0>#X2D_O__0V8Y\W+3
-MNP````")]HM,)&#V00)`#X36````9H/[!'<P#[=$)!:-!("+5"189HM$0@9F
-MB40D%`^W1"02C02`9HM$0@9FB40D$.E;`0``C78`9H/[!74N#[=$)!:-!("+
-M3"189HM$001FB40D%`^W1"02C02`9HM$001FB40D$.DE`0``D&:#^P9U+@^W
-M1"06C02`BU0D6&:+1$("9HE$)!0/MT0D$HT$@&:+1$("9HE$)!#I\0```)!F
-M@_L'#X7F````#[=$)!:-!("+3"189HL$06:)1"04#[=$)!*-!(!FBP1!9HE$
-M)!#INP```(UV``^WPX/X!P^'K````/\DA;0U```/MT0D%HT$@(M4)%AFBT1"
-M!F:)1"04#[=$)!*-!(!FBT1"!F:)1"00ZWL/MT0D%HT$@(M,)%AFBT1!!&:)
-M1"04#[=$)!*-!(!FBT1!!&:)1"00ZU$/MT0D%HT$@(M4)%AFBT1"`F:)1"04
-M#[=$)!*-!(!FBT1"`F:)1"00ZR</MT0D%HT$@(M,)%AFBP1!9HE$)!0/MT0D
-M$HT$@&:+!$%FB40D$)"#[`AJ``^W1"0<4`^W1"0D4`^W1"0R4`^W1"0T4(M4
-M)'P/MP)0Z$H#``")P8/$(&8[1"0.=@5FBTPD#HM$)&#V0`(0=!^+5"089H&Z
-M;!`````P=A!FBX)Z$```9CG!=@2)P8GV#[?S#[=4)`P/OD0D"2G"#[?!.<)^
-M`HG"9HD4=V:%VW4KBTPD4(N!``(```^WA`"H-0``T>!FBQ=F*<)FB50D"F:%
-MTG\'9L=$)`H!``^WRP^_1"0*#[<43SG0?@*)T&:)!$]#9H/[!P^&D_W__P^W
-M!XM4)!B)@L`L``"+3"10BUD4N0````"#X0'!X1ZX/P```&8C1P;!X!B)R@G"
-MN#\```!F(T<$P>`0"<*X/P```&8C1P(/M\#!X`@)PK@_````9B,'#[?`"<*)
-MDS29``"+1"10BU`4N#\```!F(T<.P>`8"<&X/P```&8C1PS!X!`)P;@_````
-M9B-'"@^WP,'@"`G!N#\```!F(T<(#[?`"<&)BCB9```/MP=0_W0D5.C\____
-M9HL'BU0D6&:)@OX!``"#Q$1;7E]=PXUV`%575E.#[!R+?"0XBW0D,(M<)#2-
-M1"0:4%</M\-0#[?&4.@^`0``@\00A<!T"P^W1"0:Z24!``"0@^P,C40D)%"-
-M1"0F4`^W1P10_S</M_96Z&<"``"#Q!2-1"0@4(U$)")05P^W1"0N4`^WVU/H
-M*@,``(/$%(U$)!Q0C40D'E!7#[=$)#!04^@0`P``@\0@C40D#%!7#[=$)!I0
-M#[=$)")0Z+X```"-1"0:4%</MT0D+%`/MT0D,E#HIP```(/$&&H`#[=$)!90
-M#[=$)!Q0#[=$)"A0#[=$)"I04^CT````B<6#Q""-1"0,4%</MT0D%E`/MT0D
-M)%#H:````(U$)!I05P^W1"0H4`^W1"0T4.A1````@\08:@`/MT0D%E`/MT0D
-M'%`/MT0D)%`/MT0D)E!3Z)X```"#Q!AJ``^WP%`/M\50#[=$)"Q0#[=$)"Y0
-M5NA_````#[?`@\0@D(/$'%M>7UW#55=64XMT)!R+;"04BWPD&(M."+L`````
-M9H-^!`!V1Y!F.2EU-XU1"+@`````9H-Y!@!V*&8Y.G47#[?`9HM401Z+1"0@
-M9HD0N`$```#K')"#P@)`9CE!!G?:B?:#P31#9CE>!'>ZN`````!;7E]=PU57
-M5E.#[`2+;"08BTPD'(M\)""+="0DBUPD*&;'1"0"9``/M\8/M],/K\*Z````
-M`(7`#X2C````@WPD+`!T!V;'1"0"`0!F.<]T=0^WQ0^WR2G(C02`C02`P>`"
-M#[?7*<J)T9GW^6:%P'D5#[?&@WPD+`!T8XT$@(T$@,'@`NM89H/X9'X6#[?#
-M@WPD+`!T2(T$@(T$@,'@`NL]D`^_R`^WPP^OP;ID````*<H/M\X/K]$!T`^W
-M5"0"B=&9]_GK&(GP@WPD+`!T#P^WQHT$@(T$@,'@`HUV``^WT(G0@\0$6UY?
-M7<.-=@!55U93BW0D&(M\)""+;"0DBUPD'`^WPV:+3$;^#[=4)!2-!)*-!("-
-M%(4`````#[<&C02`C02`C02%]O___SG0=A)FBP9FB0=FBP9FB44`Z80````/
-MM\&-!("-!("-!(4*````.=!S+&:)#V:)30#K9V:+!$YFB0=FBP1.9HE%`.M6
-M9HL$3F:)!V:+1$X"9HE%`.M$N0````!FA=MT.@^WVXUV``^W!$Z-!("-!(#!
-MX`(IT(/`"8/X$G:V#[=$3@*-!("-!("-!(7V____.=!WL4$YRW_.B?9;7E]=
-MPXUV`%=64XM$)!B+?"00BW0D%(M0"+D`````#[=`!(G#@_@`?@^)]F8Y,G0(
-M@\(T03G+?_/_="0@_W0D(`^W0@90C4((4`^WQU#HU?[__X/$%%M>7\.)]HM$
-M)`2-B`PJ``"+%>0U``")D`PJ``"-!-4`````*="-!(7H-0``B4$8QT$4`0``
-M`,=!#!0```#'01`C````PY!75E.+5"04BT0D$(N`-!```/9``B!T);\`````
-MNQP```"Y0````+YR````QT(,`````,="$'<```#K(Y"_`````+LR````N0``
-M``"^,@```,="#!0```#'0A`C````BU($N``````Y^G($.=IV#3G*<@0Y\G8%
-MN`$```!;7E_#D(M$)`2+2!2+D,`L``#!X@F!X@!^``"`SH")D3"9``#'@+PL
-M```!````PXGV5U93BWPD$(G[C;<,*@``N`````"#?A0`='2#O[PL```!=66+
-M1Q2+@#"9``!FA<!X5\'H&8E&!,>'O"P```````!65^@,____@\0(A<!U.8/L
-M"%97Z#L```"#Q!"%P'0H@^P(5E?H1@```(/$$(7`?A>#[`A65^A)`0``QX>\
-M+````@```(/$$(N#O"P``%M>7\.)]HM,)`BX`````(M1!#M1#'8%.U$0<@6X
-M`0```,-64XM<)!"Z_____X-[%``/A/<```"+`XT4Q0`````IPHT4E>@U``")
-M4QB+0P0[0Q!R8KK_____@SL`#X3,````BT,$B4,(.T,0<D&#.P!T/(L#2(D#
-MC13%`````"G"P>("BTL8BX+P-0``*T$(T>"+2P@IP8E+"('"Z#4``(E3&#M+
-M$'('@SL`=<:)]KH!````ZWF0BT,$N@`````[0PQW:Z'@-0``2+K^____.0-T
-M7(M#!(E#"#M##'=)H>`U``!(.0-S/XG&D(L#0(D#C13%`````"G"P>("BTL8
-MBX+P-0``*T$(T>"+2P@IP8E+"('"Z#4``(E3&#M+#'<'.3-RQXUV`+H"````
-MC78`B=!;7L.-=@"+3"0$BU0D"(-Z%`!T-XM"&&:+`&:)@<P1``"+0AAFBT`"
-M9HF!RA$``(M"&&:+0`1FB8'($0``BT(89HM`!F:)@<81``##B?93BUPD"(M4
-M)`R)V8M#%(N`!(```"7__P``@_H!=$:#^@%_"872="?K3XUV`(/Z!G0'@_H(
-M="[K0(M3%`N#Q"P```T``($`B8($@```ZRJ+4Q0+@\0L```-``!"`(F"!(``
-M`.L4BU,4"X'$+```#0``(`")@@2```!;PXGVBT0D!/^PW`$``%#H=/___X/$
-M",-75E.+?"00@^P,5^C\____B<:#Q`@E____?U!7Z/S___^+1Q2+4#")TX'C
-M\`,``,'K!(/$$(-\)!0`=!"X)0```"G8T>@!P^L?C78`@_L!=@-+ZQ2#[`A6
-M5^C\____N`````"#Q!#K*HM/%('B#_S__XG8P>`$)?`#```)PHE1,(/L"%97
-MZ/S___^X`0```(/$$%M>7\.)]E.#[`B+7"00BU0D%+@`````@_H)?QZ#[`3_
-M="0<C012C02`C82#3"H``%!3Z/S___^#Q!"#Q`A;PXUV`%.#[`B+7"00BU0D
-M%+@`````@_H)?QZ#[`2-!%*-!("-A(-,*@``4/]T)"!3Z/S___^#Q!"#Q`A;
-MPXUV`%575E.#[`R+;"0@BW0D)(GJ@_X"=!:#_@)W"8/^`70<ZS*)]H/^`W0+
-MZRF0OPD```#K*9"_"````.LAD+\`````N`````"#O5`J````=7SK"XUV`+C_
-M____ZW"0C01_C02`C9R"3"H``+C_____@WL$`'57@^P(:CQ3Z/S___^)<P2#
-MQ!"#?"0H`'4LQT,,"P```,=#%`(```#'0QC_____QT,<_P,``&;'0R`*`&;'
-M0R(*`.L3B?:#[`3_="0L5U7H_/___X/$$(GX@\0,6UY?7<.04XM,)`B+612+
-MD3@J``"!XO\#``"+@4`J``#!X!`E``#_`PG"B9.D````BUD4BY$\*@``@>+_
-M`P``BX%$*@``P>`0)0``_P,)PHF3J````(M9%(N#K````"4`_/__BY%(*@``
-M@>+_`P``"=")@ZP```!;PY!64XMT)`R+3"00N`````"#^0EW5(T$28T$@(V<
-MADPJ``"X`````(-[!`!T/,=#!`````"X_O___]/`(88X*@``(88\*@``(89`
-M*@``(89$*@``(89(*@``4U;H+?___[@!````@\0(D%M>PY!55U93BWPD&(ML
-M)!2+E300``"X`````(/_"0^'U`,``(T$?XT$@(VTA4PJ``"X`0```(-^!``/
-MA+@#``"#?AC_=3:%TG05#[="`B6@````NA\````]H````'0%N@\```"X`0``
-M`#G0<Q*-=@#1X(/(`3G0<O?K!)"+1AB-'+T`````BU0D%(M*%(G"@>+_`P``
-MBT8<P>`*)0#\#P`)PHM&%,'@%"4``/`/"<*)E!E`$```BT0D%(M(%`^W1B+!
-MX`0E\`````^W5B"#X@\)T`T`(`@`B809@!```(M4)!2+0A3'A!C`"0````@`
-M`(.ZS`$```-W#HM"%,>$&``1```````!@WXD`'1.C0R]`````(M$)!2+6!2+
-M5B2!XO___P"+1BC!X!@)PHF4"\`(``"+5"04BUH4BX0+P`D``(G"@\H!@WXH
-M`'0(B<*!R@$!``")E`O`"0``@WXP`'0BC0R]`````(M$)!2+4!2+1C`E____
-M``T````!B80*``D``(-^+`!T0XT,O0````"+1"04BU`4BT8L)?__#P`-```0
-M`(F$"L`0``#V1@P@=!N+1"04BU`4BX0*P`D``(#,`HF$"L`)``"-=@#V1@X!
-M="&-#+T`````BT0D%(M0%(N$"@`1```-```@`(F$"@`1``#V1@Z`=!^-#+T`
-M````BT0D%(M0%(N$"@`1``"`S`*)A`H`$0``BT8$@_@"=`J#^`-T4>G*````
-MC0R]`````(M$)!2+4!2+A`K`"0``#**)A`K`"0``BU0D%(.ZS`$```09VX'C
-M`````8'#```E`(G*BTPD%(M!%(F<$``1``#I?@```(T,O0````"+1"04BU`4
-MBX0*P`D```UB`@``B80*P`D``*$`````*P4`````BY7(+```B=,IPRL=````
-M`,'C"HM$)!2+4!2)V`T````!B80*``D``(M4)!2#NLP!```$&=N!XP````&!
-MPP``!`")RHM,)!2+012)G!#`"0``D/9&.`%T(8T,O0````"+1"04BU`4BX0*
-M`!$```T``"0`B80*`!$``/9&#`%T$[@!````B?G3X`F%."H``.L1B?:X_O__
-M_XGYT\`AA3@J``#V1@P!=!.X`0```(GYT^`)A3PJ``#K$8GVN/[___^)^=/`
-M(84\*@``]D8,`G03N`$```")^=/@"85`*@``ZQ&)]KC^____B?G3P"&%0"H`
-M`/9&#`1T$[@!````B?G3X`F%1"H``.L1B?:X_O___XGYT\`AA40J``#V1@P(
-M=!.X`0```(GYT^`)A4@J``#K$8GVN/[___^)^=/`(85(*@``5O]T)!CH-_O_
-M_[@!````@\0(C78`6UY?7<.-=@"+1"0(P>`"BU0D!(M2%(N$`@`(``##B?:+
-M5"0(P>("BT0D!(M(%(M$)`R)A!$`"```N`$```##D(M,)`B+1"0$BU`4N`$`
-M``#3X(F"0`@``+@!````PXGV5E.+5"00P>("BT0D#(MP%(N$%@`*``")PX/C
-M`W4:N`$```"*3"00T^"+ED`(``"%PG0%NP$```")V%M>PXUV`%=64XM\)!"+
-M="04BU<4N`$```")\=/@B8*`"```NP````")]E97Z/S___^#Q`B%P'06@^P,
-M:@KH_/___X/$$$.!^P\G``!^W(M'%,>`@`@```````"!^P\G```/GL`/ML!;
-M7E_#C78`5E.+="0LBUPD-(M,)!"+1"04)?\/``"+5"0DP>(2"="+5"0PP>(9
-M"=#VPP%T!0T````!]L,0=`4-````(/;#!'0%#0``0`#VPR!T!0T``(``B4$(
-MBT0D'(G"P>(:]L,"=`:!R@``@`")40R#_O]T%HGPP>`-)0#@#P`)T(E!#(%)
-M"````$"X`0```%M>PXGVN`````##B?:+1"0(@4@(````(,-3BTPD$(M<)!B+
-M5"0,@WPD%`!T%(M"#`G(A=MU`X#,$(E"#.LGC78`A=MT$(M$)!R+0`B)0@B)
-M2@SK$9#'0@@`````B<B`S!")0@R0QT(4`````,="$`````"X`0```%O#C78`
-M4XM,)!"+5"0,N`\```#V0A0!#X2D````BT(4)?X?``#1Z&:)`0^W0A)FB4$"
-MQD$$`(M"$*@!=1RH`G0$QD$$`?9"$`AT!(!)!`+V0A`$=`2`200$BT(()0``
-M/`#!Z!*(006+0A0E`.`?`,'H#8A!!HM"$"4`#P``B</!ZPB(60>+0A`E\```
-M`,'H!(A!"(M"$"4`\```P>@,B$$)QD$*`,9!"P"$VW0&C4,!B$$'@'D(`'0#
-M_D$(N`````!;PXGVPY"0D(M4)`2+3"0(@(JX+```"(!)!`AFBX*V+```9HD!
-MBH*X+```B$$$BH*Y+```B$$%N`````##D)"0BU0D!(M"%,>`@$````#\2)*+
-M0A3'@(!````D29(DBT(4QX"`0```.0``*(M"%,>`@$```"0(%E.+0A3'@(!`
-M``!Y!9CEBT(4QX"`0```_^\=`(M"%,>`@$```$"^JAJ+0A3'@(!```!451"^
-MBT(4QX"`0```!S`.`(M"%,>`A$````````##D(/L#(M,)!"+013'@-"8```6
-M'```N@````"-=@"+013'@("8``````$`0H/Z!W[MBT$4BX``G```P>@8B<+!
-MZ@2#X`_!X`0)T(/L"&H(4.C\____@\0<PY!55U93@>R<````BZPDL````(GK
-MC7PD<+YX1P``_+D%````\Z6-?"10OHQ'``"Q!?.EC7PD,+Z@1P``L07SI8U\
-M)!"^M$<``+$%\Z6Z`````(M$E'")A),D1```BT244(F$DSA$``"+1)0PB823
-M3$0``(M$E!")A)-@1```0H/Z!'[.@^P(:@%5Z/S___^!Q*P```!;7E]=PXM$
-M)`C1X`-$)`R+5"0$#[>$0OH3``##D%93@^P(BUPD%(MT)!AH;!```&@`-P``
-M4^C\____BT0D*(E##(M$)"R)0Q"+1"0PB4,49HFSR`$``&;'@\H!`````&;'
-M@_P!```_`,>#``(```````#'@[@M````````QX.\+0```````,>#R"T`````
-M``C'@]`M``"!!P``QX/8+0```````,>#W"T``#\_/P#'@^`M``!D````QX/D
-M+0```@```,>#]"T``/_____'@_@M``#_____QX/\+0``_____X/$#&H&:,A'
-M``"-@S@J``!0Z/S____&@P`N````@\046U[#B?93BDPD"(I<)`RZ`````(GV
-MC012.(C.1P``=1DXF,]'``!W$3B8T$<``'()N`$```#K#8GV0H/Z`W;6N```
-M``!;PXUV`%575E.#["B+;"1,BUPD/&B@1```Z/S___^)QH/$$(7`=1+'10`"
-M````N`````#I&0<``)"#[`A5_W0D2/]T)$C_="1(#[?#4%;H_/___XGS@\0<
-M:@%J`%;H_/___X/$$(7`=1#'1"04`P```.F[!@``C78`BT84BX`@0```#[;0
-MB=#!Z`2)ALP!``")T(/@#V:)AM`!```/ML!0#[:&S`$``%#H%/___X/$"(7`
-M=0W'1"04#0```.EP!@``@^P(:@!6Z/S___^#Q!"%P'4.QT0D%`,```#I408`
-M`)"+1A2+@!B8``!FB8;2`0``@[[,`0``"703@[[,`0``"G469H.^T`$```-W
-M#%/H-OS__X/$!(UV`(/L#%/H_/___X/$$(7`=1#'1"04#@```.G[!0``C78`
-M@[O,`0``!'82BU,4BX(00```@,P0B8(00```BT,4QX``F```!P```(/L#%/H
-M_/___V:)@]0!``"#Q!`/M\`E\````(/X,`^$L````(/X,'\4@_@0#X2B````
-M@_@@#X29````ZR"#^&`/A(X```"#^&!_"X/X4`^$@````.L'/:````!T=V:#
-MN]0!````=6V#N\P!```%=1B!N]`!```)`$,`=0QFQX/4`0``1@#K39"#N\P!
-M```'=`F#N\P!```+=0MFQX/4`0``40#K+X.[S`$```IT'(.[S`$```ET$X.[
-MS`$```IU'6:#N]`!```#=PIFQX/4`0``8@"0@[O,`0``"G1+@[O,`0``"71"
-M@[O,`0``"G4*9H.[T`$```-V+P^WD]0!``")T"7P````@^@P@_@_=QF)T(/@
-M#X/X!'\/QT0D%`T```#IJ@0``(GV@^P$C40D'E!HP0```%/H_/___X/$$(7`
-M=0['1"04"````.F!!```D&:!?"0:`3!W#<=$)!0%````Z6H$``!FBT0D&F:)
-MAFP0``"+0Q2+D!!```"#XAC!Z@.#^@)T.X/Z`W4-QT0D%`H```#I.`0``(.[
-MS`$```ET((.[S`$```IU"F:#N]`!```#=@W'1"04"@```.D/!```@^P$C40D
-M'E!J/U/H_/___X/$$(7`=0W'1"04"````.GK`P``9HM$)!IFB89N$```@^P$
-MC40D'E!J'%/H_/___X/$$(7`=0W'1"04"````.F[`P``QT0D#$`#``!F@WPD
-M&@!T1@^W1"0:)?#_``#!X`R)1"0,@^P$C40D'E!J&U/H_/___X/$$(7`=0W'
-M1"04"````.EV`P``#[=$)!H)1"0,@6PD#,````#'1"00`````+\`````BT0D
-M##G'<S"#[`2-1"0>4(V'P````%!3Z/S___^#Q!"%P`^$*`,```^W1"0:,40D
-M$$<[?"0,<M"!?"00__\``'0-QT0D%`<```#I"0,``&;'AN(1```*`&;'ANP3
-M```#`+\`````C01_C02'9L>$ANH1```+`$>#_PEVZK\`````N6Q'``"Z<D<`
-M`&:+!'EFB81^]!,``&:+!'IFB81^[A,``(T$?XT$AXT$AF;'@+`4```+`&;'
-M@!04```+`$>#_P)VQX/L"(V&;!```%!3Z/S___^#Q!"%P'4-QT0D%`@```#I
-M<`(``&:!OFP0```"4'=)@[O,`0``"G0<@[O,`0``"703@[O,`0``"G4N9H.[
-MT`$```-W)&;'AOP3``!H!F;'A@`4``"P!&;'A@04````@&;'AOH3````@&:#
-MOH80````='8/MX/4`0``)?````"#^!!U98M#%,>``)@```=```"#[`QHT`<`
-M`.C\____B1PDZ/S___]FB8/6`0``BT,4QX``F```!P```,<$)-`'``#H_/__
-M_P^W@]8!```E\````(/$$(/X('0/QT0D%`T```#IG@$``(GV@^P$C40D'E!H
-MOP```%/H_/___X/$$(7`=0W'1"04"````.EU`0``9HM$)!IFB89P$```9HF#
-M"`(``(/L#%/H_/___X/$$(7`=0W'1"04"````.E%`0``@[O,`0``"G0<@[O,
-M`0``"703@[O,`0``"G4=9H.[T`$```-W$X/L"(U$)!Q04^C\____@\00ZUV#
-MN\P!```'=`F#N\P!```+=1.#[`B-1"0<4%/H_/___X/$$.LX#[>#U`$``"7P
-M````@^@P@_@_=Q.#[`B-1"0<4%/H_/___X/$$.L1@^P(C40D'%!3Z/S___^#
-MQ!"%P`^$J````(N&P"H``(F#P`$``(/L#%/H_/___\=$)"``````OP````"#
-MQ!"#[`2-1"0>4+@?````*?A04^C\____@\00A<!T4P^W1"0:`40D$&8/MD0D
-M&XB$?BPJ``!FBT0D&HB$?BTJ``!'@_\"=KN#?"00`'0*@7PD$/W_`@!U"L=$
-M)!0)````ZR.#[`Q3Z!+W__^)V(/$$.LSQT0D%`@```#K"9#'1"04"````(7V
-M=`R#[`Q6Z/S___^#Q!"%[70'BT0D%(E%`+@`````@\0<6UY?7<-3@^P4BUPD
-M'%/H_/___X/$$(.[I"H```!T#H/L#%/_DZ0J``"#Q!"0@^P,4^C\____@\0,
-M:@%J`5/H_/___X/$"(V#;!```%!3Z/S___^)'"3H_/___X/$&%O#D%575E.#
-M["R+="1`QT0D"`"```#'1"0,()@``,=$)!!55555QT0D%*JJJJK'1"089F9F
-M9L=$)!R9F9F9OP````"-;"0(C02]`````(L<*(M6%(L4&HD4!+D`````B<C!
-MX!")P@G*BT84B108BT84BP08.=!T![@`````ZV%!@?G_````?M>Y`````(M4
-MC!"+1A2)%!B+1A2+!!@YPG0*N`````#K.(UV`$&#^0-^W(T$O0````"+3A2+
-M%"B+!`2)!!%'@_\!#XYY____@^P,:F3H_/___[@!````@\00@\0L6UY?7<.-
-M=@!3BTPD"(M4)!"+7"04BT0D#/;$`7029L<",Q-FQP/4%[@!````ZS60A,!Y
-M*&:#N880````=0IF@[F($````'049L<""`EFQP.L"K@!````ZPN-=@"X````
-M`(UV`%O#B?955U93@^P,BWPD((G]B7PD!(VWX`$``&;'1"0*``!F@;]L$```
-M`%!V)X/L!(U$)`Y0:,D```!7_Y>@`0``@\00N@````"%P`^$O`,``(UV``^W
-MA]0!```E\````(/X0'4+9L>%@A``````B?9F@WPD"@!U+(._S`$```=U(V:#
-MO]`!```(=1EFQT0D"@4`9L>%<A````$`9L>%=!````$`BT0D!(.XW`$```9T
-M0V:!N,H!``!E<'4X9HN0"`(``(U"G&:#^`%W$(U"!8M4)`1FB8((`@``ZQB+
-M1"0$9H.X"`(``$%U"F;'@`@"``!#`)#'1@0`````9H.]@A````!T&\=&!`$`
-M``!F@[UR$````'4*QT8$`P```(UV`&:#O880````=`2#3@0$9H.]B!````!T
-M+(M4)`1F@;K*`0``$0YT'8M6!(G0@\@(B48$9H.]=!````!U"(G0@\@HB48$
-M9L=&$`@)#[>'U`$``"7P````@^@P@_@_=CJ#O\P!```'=#&#O\P!```+="B#
-MO\P!```*=!^#O\P!```)=!:#O\P!```*=15F@[_0`0```W<+C78`9L=&$L0)
-MZPAFQT82K`J)]F;'1@PS$V;'1@[4%XI&`8/@OX/(@(A&`;@`````]D0D"@)U
-M)(._S`$```5W$X._S`$```5U$F:#O]`!```#=@BX`0```(UV`,'@!8I6`8/B
-MVPG"@\H(#[=$)`K1Z(/P`8/@`='@@^+]"<*(5@&#O\P!```&=@J(T(/($(A&
-M`>L$@&8![X`.`XM$)`1F@[C0`0```7<+@[_,`0``"W5?B?:X`````/9$)`H!
-M=0CV1@0)=`*P`8T<A0````"*%H/B\P^W3"0*B<C!Z`.#\`&#X`'!X`,)V@G"
-MB!:X`````/;!!'4)]D8$"70#L`&0B,+!X@2*!H/@[PG0@\B@B`:`)K^Z````
-M`(.]-!$```!T"8.].!$```!U!;H!````BD8!@^#^"="(1@&`3@(/BU0D!(.Z
-MS`$```5U#&:#NM`!```(=`^)]HM$)`2#N,P!```%=@2`3@(0#[=$)`HE\`$`
-M`'0+P?@$9HE&".L(B?9FQT8("@!F]T0D"@#P=!4/MTPD"L'I#+@!````T^!F
-MB48*ZP9FQT8*@``/MX?4`0``)?````"#Z#"#^#]W!H!.`F#K!(!F`I]F@[UV
-M$````'0R@^P$BT0D"`5($```4&H/5_^7H`$``(/$$(7`=!6+5"0$QX),$```
-M`0```(!.`H"-=@"#O\P!```$#Y;`#[;`BU0D!(F":!```+H`````@[_,`0``
-M!74+9H._T`$```ET"I"#O\P!```%=@6Z`0```(I&`X/@_@G0B$8#QT84#P``
-M`+H!````B="#Q`Q;7E]=PY"#[!2-1"0(4/]T)!SH_/___[@!````@\0<PXGV
-MBT0D!(-\)`@!=0G'0'``````PY#'0'#,X@``PU93@^P4BUPD((MT)"2+4Q2+
-M1@2)@BB```"+4Q2+1@R)@BR```"+4Q2+1A")@C"```"+4Q2+1@B)@C2```#V
-M1@,!=#6#[`B-1"004%/H_/___XN#-!```,=`)`````#'0"@`````BT,4QX`@
-M@````````8/$$(UV`(M3%(L&B8(@@```@\046U[#C78`@^PLBTPD,(M4)#2)
-M5"0$BX'<`0``@_@!=!*#^`%R(8/X!G0<@_@(=36-=@#'1"0,__\``,=$)!#_
-M_P<`ZR")]HG0*P4`````P>`#B40D#(G0*P4`````P>`#B40D$(U"`8E$)`B+
-M1"0X)?__@`&)!"2#[`B-1"0(4%'H_/___X/$/,.0BU0D!(M"%,>`*(``````
-M``"+2A2+@02````-```$`"7__\__B8$$@```BT(4QX`@@```__\``,-55U93
-MBWPD%(M,)!B)_F:#>1(`=#^+5Q2+@@2````-```0`(F"!(```(M7%`^W01")
-M@B2```"+5Q0/MT$2B8(X@```BU<4BT$4P>`#B8(P@```ZQ2+5Q2+@@2````E
-M___O_XF"!(```(M7%(L!B8(H@```BU\4BX,@@```)0``@/\/MU$("<)F@WD8
-M`'01#[=!&(/`!,'@$"4``'\`"<*)DR"```"+AM`M```PY`^W41K!X@B!X@#_
-M```)T(F&T"T``(M7%(F"&(````^W<0@Y<1QV`XMQ'(M9##E9''8#BUD<.=YU
-M!HMI!.L#D(LIBU<4BT$$@^@#P>`#)?__!P`-```8"HF"U(```(M7%(T$[>C_
-M__\E__\'``T````*B8+8@```BT\4B?`E__\``(G:P>(0"=")@=R```!;7E]=
-MPU.#[`B+7"00BU,4BT0D%(F"`&```(M#%,>`"&````$```!J`FH#:`Q@``!3
-MZ/S___^#Q!"Z`````(7`=!6+0Q2+D`1@``"+1"089HD0N@$```")T(/$"%O#
-MD)"04XM$)`B+6!2+3"0,T>&X`P```-/@BY,40```"=")@Q1```"X`0```%O#
-MB?93BT0D"(M8%(M,)`S1X;@#````T^#WT(N3%$```"'0B8,40```N`$```!;
-MPU.+3"0,BT0D"(M8%(N3&$```+C^____T\`APHM$)!"#X`'3X`G"B9,80```
-MN`$```!;PY"+3"0(N/____^#^05W%8M$)`2+0!2+@!Q```"#X"_3Z(/@`<-6
-M4X/L!(MT)!"+5"04BT84BY@40```C0P2N`,```#3X`T`\`$`]]`AP\'B#`G3
-M@,^`@WPD&`!T!H'+```!`(M&%(F8%$```(/L"(N&0"H```T````!4%;H_/__
-M_X/$%%M>PY"0BT0D!(M`%(N`"$```(/X`0^4P`^VP,.055=64X/L!(MT)!B+
-M?"0<O0````")-"2+1A2+F(````#WPP``@`!T/(N`C````*D````!=`6]```@
-M`*D````@=`:!S0``0`"I````!'0&@<T``(``J0````)T"8'-`````HUV`(M&
-M%(N8P````(/[_W42QP<`````N`````#IZ0```(GVB=@ENM@%`8D']\,```@`
-M=`<-````0(D']L,%=`.##P'WP\`%``!T4X,/0(M&%(N0Q````(G0)?\#``"+
-M#"0+@9Q$``"!X@``_P/!ZA`)PHF1G$0``(M&%(N`R````(G!@>'_`P``"=$E
-M``#_`\'H$`G(BQ0DB8*<1```]L,@=!"#OF@0````=`>!#P```$"0B>@+!XD'
-MJ0```$!T18F>4!```(M6%(N"Q````(F&5!```(N"R````(F&6!```(N"S```
-M`(F&7!```(N"T````(F&8!```(N"U````(F&9!```+@!````@\0$6UY?7<.0
-MBT0D!(N`0"H``,.055=64XMT)!2+3"08B?.+KD`J``"%[7D0BT84QT`D````
-M`(M&%(M`)(G*@>*ZV`4!OP````#VP4!T,H.[R"H```!T`X/*0(.[S"H```!T
-M`X#.`8.[T"H```!T`X#*@(.[U"H```!T!8#.!(GV]L$!=`.#R@?WP0``X`)T
-M0('*``"``/?!```@`'0&@<\````!]\$``$``=`:!SP```"#WP0``@`!T!H'/
-M````!/?!`````G0(@<\````"B?;WP0```$!T!H'*```(`(M&%(F0H````(M6
-M%(N"K````"7___]("?B)@JP```")BT`J``"%R7D-BT84QT`D`0```(UV`(GH
-M6UY?7<.0BT0D!`^W@.H!``##BU0D!(M$)`AF.8+J`0``=AD/M\#!X`4#0A2+
-M@!R(``"Z`0```&:%P'@%N@````")T,.)]E93BUPD#(MT)!"X`````&8YL^H!
-M```/AMD````/M\;!X`6)P@-3%(N*%(@``,>"`(@```````")P@-3%,>"!(@`
-M``````")P@-3%,>""(@```````")P@-3%,>"#(@```````")P@-3%,>"$(@`
-M``````")P@-3%,>"%(@```<```")P@-3%,>"&(@````````#0Q3'@!R(````
-M````@_D$=4WV@\LM```(=$2-1D`/M\#!X`6)P@-3%,>"`(@```````")P@-3
-M%,>"!(@```````")P@-3%,>""(@````````#0Q3'@`R(````````D+@!````
-M6U[#5U93BWPD$(M4)!B+="04N`````!F.;?J`0``=FN%TG0X#[9:!<'C"`^V
-M0@0)PP^V2@/!X1@/MD("P>`0"<$/MD(!P>`("<$/M@()P='IB=C!X!\)P='K
-MZPN[`````+D`````D`^WQL'@!8G"`U<4B8H8B````T<4B=J`SH")D!R(``"X
-M`0```%M>7\-55U93@^PHBUPD/(ML)$2+1"1`9HE$)":)7"0@C9/@`0``@WPD
-M3`$9R??1@>&JJJJJO@````!F.4(*#X:D`P``#[9%`(/X!0^'EP```/\DA=Q'
-M``#'1"00!0```.F/````O@````#V0@$@#X1T`P``QT0D$`8```#K=L=$)!`$
-M````]H/++0``"'1E#[=$)":#P$`/MU(*O@`````YT`^-0`,``.M*O@````!F
-M@WT"!`^&+@,``,=$)!``````9H-]`@5V*V:#?0(.&=*#XOZ#P@.)5"00ZQC'
-M1"00!P```.L.B?:^`````.GV`@``B?8/MGT$B7PD'`^V107!X`@)QXE\)!P/
-MMD4&P>`0"<>)?"0<#[9%!\'@&`G',<^)?"0<#[9%"<'@"`^V50@)PC'*@>+_
-M_P``B50D&`^V?0H/MD4+P>`("<</MD4,P>`0"<</MD4-P>`8"<<QSP^V10_!
-MX`@/ME4."<(QRH'B__\``(E4)!0/MG40#[9%$<'@"`G&#[9%$L'@$`G&#[9%
-M$\'@&`G&,<YF@WT"#7<&@>;_````@WPD$`0/A<<!``#V@\LM```(#X2Z`0``
-M9HM$)":#P$!FB40D#@^W5"0FB10DP>(%B=$#2Q2+1"0<]]")@0"(``")T0-+
-M%(M$)!CWT(F!!(@``(G0`T,4B;@(B```B=`#0Q2+3"04B8@,B```B=`#0Q2)
-ML!"(```#4Q3'@A2(```$````_W0D2/]T)`13Z/S___\/MGT4#[9%%<'@"`G'
-M#[9%%L'@$`G'#[9%%\'@&`G'#[9-&`^V11G!X`@)P0^V11K!X!`)P0^V11O!
-MX!@)P8/$#(M$)"#V@,PM```$=$,/MD4?P>`(#[95'@G"B50D"`^V11W!X`@/
-MME4<"<*)5"0$#[9U(`^V12'!X`@)Q@^V12+!X!`)Q@^V12/!X!@)QNL5O@``
-M``#'1"0$`````,=$)`@`````#[=$)`[!X`6)P@-3%(FZ`(@``(G"`U,4BWPD
-M"(FZ!(@``(G"`U,4B8H(B```B<(#4Q2+;"0$B:H,B```B<(#4Q2)LA"(``")
-MP@-3%,>"%(@```<```")P@-3%,>"&(@````````#0Q3'@!R(````````#[=$
-M)";!X`6)P@-3%(M,)!R)B@"(```#0Q2+?"08B;@$B```ZVJ)]@^W3"0FB<C!
-MX`6)P@-3%(ML)!R)J@"(``")P@-3%(ML)!B)J@2(``")P@-3%(FZ"(@``(G"
-M`U,4BWPD%(FZ#(@``(G"`U,4B;(0B````T,4BVPD$(FH%(@``/]T)$A14^C\
-M____@\0,O@$```"-=@")\(/$*%M>7UW#D)"#[!!J!HM$)!@%+"H``%#_="0@
-MZ/S___^#Q!S#@^P0:@;_="0<BT0D'`4L*@``4.C\____N`$```"#Q!S#C78`
-M@^P0:@:+1"08!3@J``!0_W0D(.C\____@\0<PU.#[`R+7"04:@;_="0<C8,X
-M*@``4.C\____BTL4#[:3."H```^V@SDJ``#!X`@)P@^V@SHJ``#!X!`)P@^V
-M@SLJ``#!X!@)PHF1X(```(M+%`^VDSTJ``#!X@@/MH,\*@``"=")@>2```"X
-M`0```(/$&%O#4XM<)!"+3"0(N@P```"+1"0,9CF!"`(``'03BH%N$```@^"`
-M/`$9TH/B^(/""X7;=`*)$[@`````6\.0BTPD!(G*N`````!F@[F"$````'0.
-M9H.Y<A````$9P(/@0D!F@[J&$````'0#@\@$9H.ZB!````!T'F:!N<H!```1
-M#G03@\@(9H.Z=!````!U!H/(((UV`,.-=@!75E.+="009HN&2!```(G'@^<<
-MP?\"B<.#XP+1^X/L"%=6_Y:L`0``BU84BX(`F```@,P@B8(`F```@\0(5U;_
-MEK`!``"#Q`R)VCG8=0J%VP^4P`^VT(GV4E=6_Y:X`0``@\006UY?PXM$)`2+
-M2!2+@1!````EG__Q_XM4)`B#X@<+!)4`2```B8$00```PY!64X/L"(M<)!2+
-M="0<:@;_="0<C8,R*@``4.C\____BTL4#[:3,BH```^V@S,J``#!X`@)P@^V
-M@S0J``#!X!`)P@^V@S4J``#!X!@)PHF1"(```(M+%`^V@S<J``#!X`@/MI,V
-M*@``"<*!YO\_``#!YA`)\HF1#(```(/$%%M>PU.+1"0(BT`4BXA,@```BY!0
-M@```BYA,@```.<N#T@"X`````(G9NP`````)R`G:6\.-=@"+1"0$BT`4BX!,
-M@```PXGVBTPD!(M1%(N"((````T````!B8(@@```BU$4B8(@@```PXGV5E.+
-M="0,BUPD$(N&-!```(7`=&#V0`(@=%JP`+D`````.PMS'(UV`(I4"P2$TGD,
-M@^)_.,)R!8C0C78`03L+<N>+5A2+B@2```"$P'06T.@\`G<0B<@-`````HF"
-M!(```.L1D(M6%(G()?____V)@@2```!;7L.0BU0D!(M"%(N`9)@``(G!P>D3
-M@>'_`0``]L4!=`:!\0#^__^+4A2+@E"```"+DDR````QT#'(PY!3BU0D"(M"
-M%(N`($```"7_````B<&#X0^[`````,'H!#F"S`$``'4,9CF*T`$``'4#LP&0
-MB=A;PXM,)`2+1"0(BU$4BY*0@````1"+412+DHR````!4`2+412+DI2````!
-M4`R+412+DHB````!4`B+412+DIB````!4!##N`$```##B?:+1"0$BT`4BX`<
-MG```)?\```##D(M$)`2+0!2+@%B```"#X`?#C78`BT0D!(M0%(M$)`B#X`>)
-M@EB```##C78`BT0D!(N`N"T``,.0@^P,BU0D$(M,)!2+@C00``"%P'4+B8JX
-M+0``L`'K#Y"#[`1045+H_/___X/$$(/$#,.)]K@!````PXGV5U93BWPD$(MT
-M)!2)^X/^!786@^P(:/__``!7Z/S___^#Q!`Y\',2D,>#]"T``/____^X````
-M`.LC@^P(5E?H_/___XM7%(F"<!```(/$$(FW]"T``+@!````B?9;7E_#@^P4
-MBU0D&(M"%(N`<!```"7__P``4%+H_/___X/$',-55U93@^P4BVPD*&C_/P``
-M5>C\____@\00.T0D)',1QX7X+0``_____[@`````ZSR+=12+GA2```"!XP#`
-M__^#[`C_="0L5>C\____)?\_```)PXF>%(```(/$$(M$)"2)A?@M``"X`0``
-M`)"#Q`Q;7E]=PX/L%(M4)!B+0A2+@!2````E_S\``%!2Z/S___^#Q!S#BT0D
-M!`^V@,LM``"#\`&#X`'#B?:+1"0$B<&#?"0(`'0CBU`4BX($@```)?____Z)
-M@@2```"!H<@M``#____^ZR&-=@"+4!2+@@2````-`````8F"!(```(&)R"T`
-M``````&X`0```,-55U93@^P4BVPD*&C_/P``5>C\____@\00.T0D)',1QX7\
-M+0``_____[@`````ZT"+=12+GA2```"!X___`,"#[`C_="0L5>C\____P>`0
-M)0``_S\)PXF>%(```(/$$(M$)"2)A?PM``"X`0```(GV@\0,6UY?7<.#[!2+
-M5"08BT(4BX`4@```)0``_S_!Z!!04NC\____@\0<PY!64XM<)`R+5"00N`P`
-M``!F@_I_=S"+0Q0/M\J)B``$``"+4Q2#?"04``^5P`^VP(F"!`0``(I$)!2(
-MA!DT+0``N`````!;7L-55U93@^P,BUPD((M$)"2)QHB#.!```(-\)"@`#X3Z
-M````A,`/A/(```"+@S00```/MT`")4`!```]0`$```^%V````(/L"&H!4^C\
-M____B<6+@S00``"#Q!#V0`-`="F)\`^V^(GHT>@/K_B-/'^!QP0!``")\@^V
-MR@^OR(T$28V,`*P-``#K6(N#-!```&:#>`(`>2J)\`^V^(GHP>@"#Z_XC3Q_
-M@<?2````B?(/MLH/K\B-!$F-C`!(#0``ZR&)\`^V^`^O_8T\?X'':`$```^V
-MR`^OS8T$28V,`&`.``")\`^VT`^OU8T44H'"Z`,``('B_S\``(M#%(FX<!``
-M`(M#%(F(L!```(M+%(G0P>`0"=")@12```")]H/$#%M>7UW#@^P4BT0D&/^P
-MW`$``%#H_/___X/$',.0BU0D!+@`````@WPD"`9T%("ZCQ````!T"X.ZY"T`
-M``%W`K`!PXUV`%.+7"0(_W0D#%/H_/___X/$"(7`#X1"`0``BT,4QX!PF```
-M'P```(M3%`^W@]0!```E\````(/H,(/X0!G`@^#\@\`8B8+XF0``BU,4BX(<
-M@```)7_`__\,@(F"'(```(M#%,>`!($``#T```"+4Q2+@A!```"#R`*)@A!`
-M``"#N\P!```'=#"#N\P!```+=">#N\P!```*=!Z#N\P!```)=!6#N\P!```*
-M=6!F@[O0`0```W=6B?:+0Q3'@'28```F````BT,4QX!XF```#0```(M#%,>`
-M\)D```<```"+0Q3'@/29```_````BU,4BX(00```)?____P-`````HF"$$``
-M`.D7`0``B?:+0Q3'@'28```*````BT,4QX!XF```#````(M#%,>`\)D```,`
-M``"+0Q3'@/29```@````BU,4BX(00```#0````.)@A!```#IR````(UV`(M3
-M%(N"$$```"7____\B8(00```BU,4BX(00```@^#]B8(00```BT,4QX!PF```
-M'P```(M#%,>`=)@``'\```"+0Q3'@'B8```.````BT,4QX#PF0``#````(M#
-M%,>`])D``/\```"+4Q0/MX/4`0``)?````"#Z#"#^$`9P(/@_(/`$HF"^)D`
-M`(M3%(N"'(```(G!@>%_P/__#[>#U`$``"7P````@^@P@_@_=PF)R`V`$P``
-MZP>)R`V`#P``B8(<@```6\.04XM<)`C_="0,4^C\____@\0(A<`/A-,```"+
-M4Q2+@A!````E_____(F"$$```(M3%(N"$$```(/@_8F"$$```(M#%,>`!($`
-M``$```"+4Q2+@AR```")P8'A?\#__P^W@]0!```E\````(/H,(/X/W<*B<@-
-M@!,``.L(D(G(#8`/``")@AR```"+0Q3'@'"8```?````BT,4QX!TF```?P``
-M`(M#%,>`>)@```X```"+0Q3'@/"9```,````BT,4QX#TF0``_P```(M3%`^W
-M@]0!```E\````(/H,(/X0!G`@^#\@\`8B8+XF0``6\.0N@````"+1"0(9HL`
-MB<%F.P4@2```=PRX($@``$)F.PR0=OD/OP25(D@``,-75E.+5"00BT0D%(MT
-M)!B+?"0<B=.-BN`!``"#^!T/AZ@"``#_)(5,2```@_X"=!:#_@)R)X/^!'(L
-M@_X%=AV#_G]T&.L@BD$!P.@%@^`!@_@!&<"#X`WI?`(``+@`````Z7("``"X
-M#0```.EH`@``N`````"%]@^$6P(``(/^`742]H+++0``"`^4P`^VP.E$`@``
-MA?9T!X/^`701ZR#V00$0#Y7`#[;`Z2H"``"+@\PM``#!Z`*#X`'I&0(``+@,
-M````Z0\"``"-=@"#NLP!```%=Q.#NLP!```%=11F@[K0`0``!W8*N`````#I
-MY@$``+@-````Z=P!``"X`````(7V#X3/`0``N`P```"#_@$/A<$!``"+0A2+
-M@`BB``#VQ"`/E,`/ML#IJ@$``(N"^`$``(D'N`````#IF`$``+@`````A?8/
-MA(L!``"X`````(/^`0^%?0$``(.ZV"T````/E,`/ML#I:P$``(7V=`>#_@%T
-M%>LZ9H.Z@A`````/E,`/ML#I30$``&:#NH@0````=1.X`0```&:#NH80````
-M#X0P`0``N`````#I)@$``+@!````Z1P!``"X`````(7V#X0/`0``N`P```"#
-M_@$/A0$!``"+@L@M``#WT,'H'^GQ````A?9T!X/^`708ZRB*00+`Z`2#X`&#
-M^`$9P(/@#>G0````]H+,+0``"`^4P`^VP.F^````N`P```#IM````(N"W"T`
-M`(/@/XD'N`````#IGP```(N"W"T``"4`/P``P>@(B0>X`````.F%````@_X!
-M=!.X`````(/^`7)VL`R#_@9W;^L/]H(4+@```0^4P`^VP.M>@^P,4NC\____
-MB<*#Q!"X`0```(72=$>#_@9W+?\DM<1(```/MD()B0?K'@^V0@R)!^L6#[9"
-M#8D'ZPX/MD(+B0?K!@^V0@J)![@`````ZPZ)]E=64%+H_/___X/$$%M>7\-5
-M5U93@^P,BWPD((M<)"2+;"0HBTPD+(G^C9?@`0``@_L=#X>$`0``_R2=_$@`
-M`(7)=`R!C\@M```````(ZPJ!I\@M``#____WN`$```#I;`$``+@`````]D(!
-M$`^$70$``(7)=`F#I\PM``#[ZP>#C\PM```$BU<4BX;,+0``B8(@@0``N`$`
-M``#I,`$``(M'%(N0"*(``(7)=`6`SB#K`X#FWXM'%(F0"*(``+@!````Z0@!
-M``")C_@!``"+1Q2)B$B```"X`0```.GO````A<D/E<`/ML")A]@M``"X`0``
-M`.G7````A<ET#(&/R"T``````(#K"H&GR"T``/___W^X`0```.FS````#[^'
-M\"T```'!@_D_=@6Y/P```(/[&G43B<@+AMPM``"#X#^)AMPM``#K'HN6W"T`
-M`('B`#\``(G()0`_``#!Z`@)T(F&W"T``(M7%(N&W"T``(F"Z(```+@!````
-MZU2X`````(/]!G=*@^P$4?\TK>!(``!7Z/S___^#Q!#K-/9"`A!T&X7)=`F#
-MC\PM```(ZP>#I\PM``#WN`$```#K$X/L#/]T)#Q155-7Z/S___^#Q""#Q`Q;
-M7E]=PY"#[!3_="0L_W0D+/]T)"S_="0L_W0D+/]T)"SH_/___X7`#Y7`#[;`
-M@\0LPU93@^P$BW0D$(-\)!0`=&R+5A2+@@1````E___\_XF"!$```(/L#&H*
-MZ/S___^[*````(/$$(GVBT84BX`00```J0```0!T)H/L#&HRZ/S___^+5A2+
-M@@1````E___\_XF"!$```(/$$$MUS.L$A=MU"K@`````ZQR-=@"+5A2+@@2`
-M```E___[_XF"!(```+@!````@\0$6U[#D(M,)`2+412+@@2````-```$`(F"
-M!(```(-\)`@`=!F+412+@@1````E___\_PT```$`B8($0```PXUV`(M,)`2+
-M412+@@2````-```$`(F"!(```(-\)`@`=!F+412+@@1````E___\_PT```(`
-MB8($0```PXUV`%=64XM$)!"+7"04BU0D&(G&OP$```"#^P%T(8/[`7((@_L"
-M="/K+9"#[`A24.BZ_O__B<>#Q!#K(XUV`%)0Z$7___^#Q`CK%%)0Z'7___^#
-MQ`CK"+@`````ZPF0B9ZT+0``B?A;7E_#BT0D!(M`%(N`!$```"4```,`P>@0
-MPY"04X/L"(M4)!"+1"04@_@(#X23````@_@(=R:#^`(/A(T```"#^`)W#(/X
-M`70[Z:8```")]H/X!'1GZ9H```")]CT``0``='D]``$``'<*@_@@=&3I@```
-M`#T``@``=&@]``0``'1HZW"[`````(.Z-!````!T:HN"-!```/9``T!T![L`
-M````ZU>+@C00``!F@W@"`'E*NP````#K0XUV`+L`````ZSF0NP````#K,9"[
-M`````.LINP````#K(HGVNP````#K&;L`````ZQ*[`````.L+C78`N`````#K
-M$)"#[`A34NC\____B=B#Q!"#Q`A;PXM$)`2+0!2+0`S#D(M$)`2+4!2+1"0(
-MB4(,PY"+1"0$BT`4QT`(!````,.0@^P,BU0D$(M"%,=`""````!J`&H$:@A2
-MZ/S___^%P`^5P`^VP(/$',.-=@!3@^P4BUPD'(M3%(N"2(```(/@WXF"2(``
-M`%/H_/___X/$"&H!4^C\____@\086\.#[!B+3"0<BU$4BX)(@```@\@@B8)(
-M@```4>C\____@\0<PY"+3"0$BU$4BT0D"(F"0(```(M1%(M$)`R)@D2```##
-MD%.+5"0(BTPD#+@`````@_D_=T*#^1]V((M2%(N:1(```(/I(+C^____T\`A
-MV(F"1(```.L;C78`BU(4BYI`@```N/[____3P"'8B8)`@```N`$```!;PY!3
-MBU0D"(M,)`RX`````(/Y/W="@_D?=B"+4A2+FD2```"#Z2"X`0```-/@"=B)
-M@D2```#K&XUV`(M2%(N:0(```+@!````T^`)V(F"0(```+@!````6\.0BT0D
-M!(M`%(N0/(```(N`#($``*@@=`.`S@*I```"`G0#@,X!B=##D%.+7"0(BTPD
-M#(M3%`^VP8F"/(```+H`````]L4"=`*R(/;%`70&@<H```("BT,4B9`,@0``
-MA=)T#XM3%(M"-(/($(E"-.L-D(M3%(M"-(/@[XE"-%O#B?:+5"0(QT((````
-M`(M$)`PE_P\``(E"#/9$)!`@=`:`S"")0@S'0A0`````QT(0`````+@!````
-MPU93@^P$BW0D$(M,)"B+5"04BT0D'+L/````]D(4`0^$]0```/9`%`%U%8M&
-M%(M`#+L/````.T0D&`^$V@```&:+0A`E_P\``&:)`8M"%"4``/]_P>@09HE!
-M`L9!!`"+0A`E``#P#\'H%(A!!CR`=03&008`BT(4]L0!=!`E`/X``,'H"8A!
-M!^L'C78`QD$'_XM"$"4`@`\`P>@/B$$(BT(0)0```/#!Z!R(00F+0A#!Z`R#
-MX`&(00J+0A2H`G55J`1T"8!)!`'K2XUV`/9"%!!T*H!)!`(/MD(5B$$%@[X8
-M+@```'4N@_@%="F#[`A15NC\____@\00ZQJ)]O9"%`AT!H!)!`CK#/9"%"!T
-M!H!)!!")]KL`````B=B#Q`1;7L.0D)!55U93@^P\BWPD4(G]O@````"+5"18
-M#[="`HG"P>H'P>@(,="Z#````*@!#X2W#```BTPD6`^W00*)PL'J!L'H!3'0
-MN@P```"H`0^$F`P``(/L!&H!:@!7Z/S___^#Q!"Z`````(7`#X2+#```@^P(
-M_W0D8%?H_/___XE$)#R#Q!"Z#````(7`#X1:#```@WPD5`9T(8-\)%0&=PF#
-M?"14`7<)ZQ&#?"14"'0*N@P```#I,@P``,=$)"@`````@WPD7`!T*(M'%(N`
-M0!$``(E$)"B#[`C_="0T5^C\____@\0(:@!7Z/S___^#Q!"#O\P!```'="Z#
-MO\P!```+="6#O\P!```*=!R#O\P!```)=!.#O\P!```*=5UF@[_0`0```W=3
-M@WPD7`!T3(._-!````!T0XN/-!```(M<)%AFBP-F.P%T,0^W4P*!XO`!```/
-MMT$")?`!```YPG4:@^P(4U?H_/___X/$$+H!````A<`/A8$+``"+1Q2+@%B`
-M``")1"0DA<!U",=$)"0!````BU<4BX($@```)0``(`*)1"0<BX(00```)6``
-M_@")1"0@BX(40```B40D-(N2&$```(E4)#"#[`C_="1<5^C\____B3PDZ/S_
-M__^#Q`C_="1@5^C\____@\00N@,```"%P`^$\0H``(M4)%@/MT(")?`!```]
-M0`$``'14/4`!``!_)CW`````='P]P````'\,/:````!T7.F-````/=````!T
-M=.F!````/<`(``!T5CW`"```?PD]4`$``'0DZVH]0`D``'0)/5`)``!T%.M:
-MQT0D&`$```#'1"04`0```.M2QT0D&`(```#'1"04`0```.M`QT0D&`,```#'
-M1"04`@```.LNQT0D&`0```#'1"04`@```.L<QT0D&`4```#'1"04`@```.L*
-MN@P```#I)0H``(M'%,>``)@```<```"[`````(UV`(T$6XM/%(L4Q8!)``")
-M5"0(BU0D&(T$0HL$A8!)``"+5"0(B0011O?&/P```'4-@^P,:@'H_/___X/$
-M$$.#^QAVOKL`````D(L,W>!+``"#?"1<`'06C8'@?___@_@8=B^-@2Q___^#
-M^`AV)(M7%(L$W>1+``")!`I&]\8_````=0Z#[`QJ`>C\____@\00D$.!^\,`
-M``!VKU;_="08_W0D(%?_E:@J``"#Q!"+3"18]D$#0'4'9H-Y`@!Y$(/L"/]T
-M)&!7Z/S___^#Q!!F@[_2`0``00^&T0```(M'%,>`+)@```*@`@"+7"189H$[
-MM`EU)0^VC8X0```/MX68$```*<&X9V9F9O?IB=#1^,'Y'XG#9BG+ZQ(/MI6.
-M$```N&=F9F;WZHG3T>N+="18#[=&`B70````/<````!U*XM/%`^VE8X0``#W
-MVL'B!H'BP`\``(G8P>`2]]@E``#\``G"B9%,F0``ZPV+1Q3'@$R9````````
-MBU<4BX(HH@``@.3]B8(HH@``BU<4BX(HH@``)?\#_O^`S`B)@BBB``"+1Q3'
-M@&"````/````9H._T@$``$)V#8M'%,>`5*(```````"+1Q3'@'B8```.````
-M@[_,`0``"G0<@[_,`0``"703@[_,`0``"G4Y9H._T`$```-W+[D!````BT0D
-M6&:!.)X)=`=F@3BC"74%N0````"+5Q2+@DRB```YR'0&B8I,H@``@^P$C40D
-M/%#_="0T5^C\____@\00N@,```"%P`^$R@<``(-\)%0&=!6#OP0"````=`R#
-M[`Q7Z/S___^#Q!"-1"0X4`^W1"0<4/]T)#17_Y6T*@``@\00N@,```"%P`^$
-MB`<``(M4)%CV0@)`=&2#O\P!```*=">#O\P!```)=!Z#O\P!```*=0IF@[_0
-M`0```W8+9H&];!````)0=B2+3"18#[=!`B6@````/:````!T$(/L"/]T)#17
-MZ/S___^#Q!"#[`C_="1@5^C\____@\00@^P(_W0D-%?H_/___X/$$+H#````
-MA<`/A/T&``"#?"1<`'0-BT<4BUPD*(F80!$``(M/%`^VE2PJ```/MH4M*@``
-MP>`("<(/MH4N*@``P>`0"<(/MH4O*@``P>`8"<*)D0"```"+3Q0/MI4Q*@``
-MP>((#[:%,"H```G0"T0D'`N%R"T```T``(``B8$$@```@^P(_W0D7%?H_/__
-M_XM/%`^VE3@J```/MH4Y*@``P>`("<(/MH4Z*@``P>`0"<(/MH4[*@``P>`8
-M"<*)D>"```"#Q`B+3Q0/MI4]*@``P>((#[:%/"H```G0B8'D@```BU<4BX(0
-M0```"T0D*(F"$$```(M'%(MT)#R)L!1```"+1Q2+5"0XB9`80```BT<4BTPD
-M+(F(6(```(M/%`^VE3(J```/MH4S*@``P>`("<(/MH4T*@``P>`0"<(/MH4U
-M*@``P>`8"<*)D0B```"+3Q0/MI4W*@``P>((#[:%-BH```G0B8$,@```BU<4
-MBX70+0``B8(8@```BT<4QX"`````______]T)#17Z/S___^#Q!"Z`P```(7`
-M#X1J!0``@^P$:@$/MH<X$```4%?H_/___X/$"/]T)&!7Z/S___\/MX?4`0``
-M)?````"#Z#"#Q!"#^#]W0XN'-!```/9``T!U!V:#>`(`>3"+AS00```/MT`"
-M)0!```"#^`$9P/?0@\`-BT\4BY$DF```@^+P@^`/"<*)D228``"+1Q2+@!29
-M``")PH'B_S\``(M<)%CV0P(@=`_!X@*XHXLNNO?BP>H$ZPJXS<S,S/?BP>H#
-MBT<4QX`<F````0```(N'-!```/9``T!T$H/L#(U$$F10Z/S___^#Q!#K,8N'
-M-!```&:#>`(`>16#[`R-!)5D````4.C\____@\00ZP^#[`R-0F10Z/S___^#
-MQ!"+1Q2+L`B8``#'@`B8````.```NP$```"+1Q2+@"2<``"H$'0E@^P,:,@`
-M``#H_/___X/$$(G80X/X$W\-BT<4BX`DG```J!!UVXM'%(FP")@``(M7%(N"
-M8)@``(/(`XF"8)@``(MT)%@/MT8"):`````]H````'0[@[V\+0```G0RBU<4
-MBX(@F0``@,SPB8(@F0``BU<4BX(@F0``#0```0")@B"9``#'A;PM```!````
-MZPK'A;PM````````@^P,5^C\____NP````"#Q!"^`0```(T$G0````")1"0$
-MBU<4B?"(V=/@BTPD!(F$"@`0``!#@_L)?MO'A9Q$````````NP````!F@[_H
-M`0```'09@^P(4U?H_/___X/$$$,/MX?H`0``.=A_Y\>%0"H``&4)"`"#?"14
-M!G4*QX5`*@``91D(`(M7%(N%0"H``(F"H````(M7%(N"K`````T```<`B8*L
-M````@[],$````'0,@^P,5^C\____@\00:@!J`6A@F```5^C\____@\0(_W0D
-M7%?H_/___XM7%(N"((```"7__W_^B8(@@```@\00@[_,`0``!7<3@[_,`0``
-M!74D9H._T`$```=V&HM'%,>`&($``*H``0"+1Q3'@!R!```0,@``BT<4QX`(
-M@0``4@```(M<)%CV0P,!=`B*A8H0``#K!HJ%BQ```(/L!`^^P%#_="1@5^C\
-M____B$0D(XNUW"T``(/F/XET)!P/OXWP+0``B?`IR(M<)#P/OE,&@\00.=!V
-M!@'*B50D#(MT)"P/OD8%T>`/OE0D$RG0B<([1"0,<PT/OX7P+0```<*)5"0,
-MBYW<+0``@>,`/P``P>L(#[^-\"T``(G8*<B+="0L#[Y6!CG0=@.-'`J+5"0L
-M#[Y"!='@#[Y4)!,IT(G".=AS"@^_A?`M``"-'`*+C=PM``"!X0``/P#!Z1`/
-MO[7P+0``B<@I\(D$)(M$)"P/OE`&.10D=@.-##*+5"0L#[Y"!='@#[Y4)!,I
-MT(G".<AS"@^_A?`M``"-#`*#?"0,/W8(QT0D##\```"#^S]V!;L_````@_D_
-M=@6Y/P```(M4)`R#XC^)V,'@""4`/P``"<*)R,'@$"4``#\`"<*+1Q2)D.B`
-M``"#O<PM````=`^+5Q2+A<PM``")@B"!``"#O?0M``#_=!*#[`C_M?0M``!7
-MZ/S___^#Q!"#O?@M``#_=!*#[`C_M?@M``!7Z/S___^#Q!"#O?PM``#_=!*#
-M[`C_M?PM``!7Z/S___^#Q!"#O_@!````=`^+5Q2+A_@!``")@DB```"+3"14
-MB8_<`0``@WPD7`!T;8M<)"SV0P0"=02`8P3^BW0D+&:+1@*+5"189HE"`HI&
-M!(A"!(I&!8A"!8I&!HA"!HI&!XA"!XN'-!```,=`+`````#'0#``````BY\T
-M$```@^P,5^C\____B4,DB5,H@\0(:@%7Z/S___^#Q!"Z`0```.L3C78`BTPD
-M8(,Y`'0"B1&Z`````(G0@\0\6UY?7<.)]E93BW0D#(N>!`(``/;#`W0?BTX4
-MBY%$F0``@>+____?B=B#X`'!X!T)PHF11)D``/;##'0O]L,$=1:+5A2+@M"`
-M``"#X..)@M"```#K%HGVBU84BX+0@```@\@<B8+0@```B?9;7L.0@^P4BT0D
-M&/]T)!Q0_Y"P*@``A<`/E<`/ML"#Q!S#B?955U93@^PDBW0D.+\!````B70D
-M%/]T)#Q6Z/S___^)Q;L`````@\009H.^Z`$```!T(HGV@^P(4U;H_/___X/$
-M$(7`=1Y##[>&Z`$``#G8=^.-=@"Z`````(7_#X2[`0``ZP>_`````.OJBT84
-MQX!\F0```0```+L`````BT84BX`@G```A<!U%8/L#&H%Z/S___^#Q!!#@_MC
-M=N#K!8/[8W8*N@````#I;P$``(/L"%56Z/S___^#Q!"Z`````(7`#X15`0``
-MBT84BX`4F0``B<*!XO\_``#V10(@=!'!X@*XHXLNNO?BB=#!Z`3K#+C-S,S,
-M]^*)T,'H`X/L#(/`9%#H_/___X/$#(U$)!1055;H_/___X/$$+H`````A<`/
-MA/8```"+1A3'@'R9````````]D4"0'1E@[[,`0``"G0K@[[,`0``"70B@[[,
-M`0``"G4*9H.^T`$```-V#XM$)`QF@;AL$````E!V(8M4)#0/MT("):`````]
-MH````'0-@^P(55;H_/___X/$$(/L"/]T)#Q6Z/S___^#Q!"+5A2+@F"8``"#
-MR`*)@F"8``#V100"=02`903^9HM%`HM4)#1FB4("BD4$B$($BD4%B$(%BD4&
-MB$(&BD4'B$('BX8T$```QT`L`````,=`,`````"+GC00``"#[`Q6Z/S___^)
-M0R2)4RB#Q`AJ`5;H_/___[H!````@\00B?:)T(/$'%M>7UW#B?:+3"0$BU0D
-M"(M!%(N`!(```"7___S_@_H!=%&#^@%_"(72="O#C78`@_H&=`>#^@AT.L.0
-MBU$4#0```1")@@2```"+412+0A2#X-^)0A3#BU$4#0```A")@@2```"+412+
-M0A2#R"")0A3#B?:+410-````$(F"!(```,.0@^P4:@+_="0<Z#8%``"#Q!S#
-MB?93@^P,BUPD%&H!:@!3Z/S___^#Q!"Z`````(7`=!*#[`AJ$U/H!P4``(G"
-M@\00B?:)T(/$"%O#D%575E.#[!2+7"0HBWPD+&H34^CA!```@\00N@````"%
-MP`^$_0$``(/L!&H!:@!3Z/S___^#Q!"Z`````(7`#X3@`0``@^P(:@!3Z*D$
-M``"#Q!"Z`````(7`#X3%`0``A?\/A+8!``"#N\P!```*=!R#N\P!```)=!.#
-MN\P!```*=39F@[O0`0```W<LO0@````/MT<"J"!U%270````N00````]P```
-M``^%L@```+GK````Z:@````/MX/4`0``)?````"#Z#"#^#]V$H.[S`$```=T
-M"8.[S`$```MU0KT(````#[='`J@@=0PET````#W`````=0>YZP```.MBN>H!
-M``#V1P-`=5</OT<"B<'!^1^!X0`"``"!P>H```#K0+T`````#[='`J@@=0PE
-MT````#W`````=0>YJP```.L@N:H!``#V1P-`=14/OT<"B<'!^1^!X0`"``"!
-MP:H````/MT<"J$!T%:@@=0PET````#W`````=06#S03K"?9'`D!U`X/-`?9'
-M`P%U`X/-`@^W1P*#X!"#^`$9]O?6@^8#BT,4BY!\F```#[='`J@@=0PET```
-M`#W`````=3&+0Q2)L`28``"+0Q2)J`"B```YRG1*BT,4B8A\F```@^P,:"P!
-M``#H_/___X/$$.LO.<IT&8M#%(F(?)@``(/L#&@L`0``Z/S___^#Q!"+0Q2)
-ML`28``"+0Q2)J`"B``"Z`0```(GVB="#Q`Q;7E]=PXGV55=64X/L%(M<)#"+
-M;"0HQP,`````_W0D+/]T)"SH_/___XG&@\00N`````"%]@^$BP(``(.]O"T`
-M``)T"8.]O"T```!U!L<#`0```(.]O"T```$/A5,!``"+5"0@BT(4BX`@F0``
-MJ0```0`/A3L!``#'A;PM````````QP,!````NP````")]HM,)""+012+N!"<
-M``"+B!2<``"+@!B<``")1"0(A?]T!(7)=1Z+1"0@BU`4BX(@F0``#0```0")
-M@B"9``!#@_L)?KV)^-'HB<K1Z@'0P>D'P>@'B40D!`^$'P$``(/Y`0^.%@$`
-M`(I$)`CWV`^^V(G8F?=\)`2)PX/XX'T'N^#____K"H/X'WX%NQ\```")^+H`
-M````]_&->("#__!]![_P____ZPJ#_P]^!;\/````BT0D((M(%(N1()D``('B
-M'_C__XG8P>`%)>`'```)PHF1()D``(M4)""+2A2+@2"9``"#X.")^H/B'PG0
-MB8$@F0``BTPD((M1%(N"()D``(#,"(F"()D``,>%O"T```(```#'1A`!````
-MB%X4B?B(1A7K69"+5"0D#[="`B6@````/:````!T1(.]O"T```)U.X-^$`!U
-M-8M,)""+412+@B"9``"`S/")@B"9``"+412+@B"9```-```!`(F"()D``,>%
-MO"T```$```"0@^P(5O]T)"SH_/___X/$$/9&`@(/A8X```"+1"0@BU`4BX)@
-MF```@\@"B8)@F```BTPD)`^W40+VQ@%U'XM,)"`/MX'4`0``)?````"#Z#"#
-M^#]W8?;"0'1<B?:+1"0@@[C,`0``!W1-@[C,`0``"W1$@[C,`0``"G0[@[C,
-M`0``"70R@[C,`0``"G4*9H.XT`$```-V'X/L#/]T)"SH91\``(/$$.L.BU0D
-M)&:#2@("9H-F`OVX`0```(/$#%M>7UW#D%=64XM\)!"+7"04B=B%VW4%N/__
-M__^)QH._S`$```ET$X._S`$```IU#6:#O]`!```#=P.#X^^+1Q2+4`R)F`!`
-M``"#[`QJ#^C\____@^8#@^,#4U9H`$```%?H_/___XG&@\0@]L,!=2J+1Q3'
-M0!0`````@^P$:@%J`%?H_/___X/$$(7`=`R+1Q2+@,````"-=@")\%M>7\.)
-M]HM$)`2+0!2+@&28``#!Z!,E_P$``/;$`70%-0#^__^8PXUV`(M,)`R+5"0$
-MBT0D"`^W0`(EX`$``#W`````=#`]P````'\)/:````!T%NLL/4`!``!U)6:+
-M@L@0``!FB0'K(9!FBX+*$```9HD!ZQ1FBX+,$```9HD!ZPBX`````,.)]K@!
-M````PXGV5U93@^P$BUPD%(M\)!B+0Q2+@&"8``"^`````*@"=3Q3Z/S___^)
-MQHU$)`905U/H9/___X/$$(7`=!5F.W0D`GX39H-/`@*^`````.L'B?:^````
-M`&:)=Q:-=@`/O\:#Q`1;7E_#B?964XMT)`R)\_:&X`$```1T:XM&%,>`(`0`
-M``$```"+1A3'@``&````````BU84BX(`!@``@\@(B8(`!@``BT84QX`$!@``
-M`0(0`(M&%,>`(`8```````"Y`````(M&%(F(``0``(M6%`^VA!DT+0``B8($
-M!```08/Y?W[@6U[#D%575E.#[`R+1"0HQT0D"`````"->/_![P-(@^`'B00D
-MBW0D)+T`````A?9^9XM$)"S!X`.)1"0$BQPD`?.#^PAV!;L(````N`$```"(
-MV=/@2+H!````B@PDT^)*,="*3"0$T^"+5"0@(P2ZT^B*#"33Z(GIT^`)1"0(
-MB=@K!"0!Q8L$)(UT!OC'!"0`````1X7V?Z2#[`C_="0L_W0D%.C\____B40D
-M&(M$)!B#Q!Q;7E]=PU575E.+?"04BVPD&(G^BT0D'`^W0`(EX`$``#W`````
-M="H]P````'\+/:````!T%.LBB?:Z`````#U``0``="#K$HGVN@$```#K%9"Z
-M`@```.L-D+@`````Z>4```")]@^WG%;F$```#[>$5NP0``#!X`8)PP^WA%;R
-M$```P>`,"<,/MX16^!```,'@$@G##[>$5OX0``#!X!@)PP^WC%8$$0``#[>$
-M5@H1``#!X`8)P0^WA%80$0``P>`,"<$/MX16%A$``,'@$@G!#[>$5AP1``#!
-MX!@)P8/]`70/@_T!<AJ#_0)T">L+C78`B=GK#(G+ZPBX`````.M(D#G9=12+
-M5Q2+@@BB``"`Y-^)@@BB``#K$HM7%(N""*(``(#,((F""*(``(FNN"T``(M'
-M%(F88)D``(M'%(F(9)D``+@!````6UY?7<-3BT0D"(.XS`$```IT2H.XS`$`
-M``ET08.XS`$```IU#&:#N-`!```#=BZ)]H.XS`$```=T(X.XS`$```MT&@^W
-M@-0!```E\````(/H,+H@````@_@_=P:0NB@```"Y`````(M$)`P/MP")T[H`
-M````]_.%TG0*C4+V@_@,=@*Q`8G(6\-55U93@^Q,BVPD8(GNBT0D9`^W>`+!
-M[P>#YP$/MT`")?`!```]0`$``'1M/4`!``!_,CW`````#X3C````/<````!_
-M$#V@````#X3%````Z=@````]T`````^$P0```.G(````/<`(```/A+$````]
-MP`@``'\./5`!``!T&^FJ````B?8]0`D``'0-/5`)```/A98```")]L=$)#P`
-M````#[>%U`$``"7P````@^@P@_@_#X:`````@[W,`0``!W1W@[W,`0``"W1N
-M@[W,`0``"G1E@[W,`0``"71<@[W,`0``"G4*9H.]T`$```-V28M-%(N11)D`
-M`(/BQXN&*"H```^_`,'@`X/@.`G"B9%$F0``ZR3'1"0\`0```.L:B?;'1"0\
-M`@```.L.B?:X`````.D%`P``B?:+312+@1"9```E!OS__XM<)#P/MY1>X!``
-M`,'B!`G0@\@!B8$0F0``_W0D9/^VN"T``%7H_/___XM5%`^_A%[($```)?\!
-M``"`S`*)@FB9``"#Q`QF@;YL$```_T]V08M$)&3V0`(0=#=FBX1^0!$``(J<
-M-T@1``"*E#=*$0``B%0D(&:+C'Y$$0``9HE,)!!FBY1^3!$``&:)%"3K.8GV
-MBTPD/&:+A$Z>$```BIPQPA```(J4-\40``"(5"0@9HN,?J00``!FB4PD$&:+
-ME'XN$0``9HD4)(M-%(N11)@``('B?\#__\'@!R6`/P``"<*)D428``"+312+
-M@5"8``"P``^VTPG0B8%0F```BTT4BY%0F```,/:*1"0@P>`()0#_```)PHF1
-M4)@``(M-%(N12)@``('B_P_\_XM$)!#!X`PE`/`#``G"B9%(F```BUT4BTPD
-M/`^WE$ZV$```B=#!X!C!XA`)T`^WC$Z\$```B<K!X@@)T`G(B8,TF```BTT4
-MBY$HF```,/:+7"0\#[>$7JH0``#!X`@)PHF1*)@``(M-%(N19)@``('B_P_X
-M_P^WA%ZP$```P>`,)0#P!P`)PHF19)@``+L"````9H&^;!````(P=QEF@;W*
-M`0``(A!U+HM$)&3V0`)`="2S".L@_W0D9%7H_/___X/$"(7`=`^+5"0\#[>$
-M5B(1```!PY"+312+D229``"`X@&-!!LE_@````G"B9$DF0``BTPD9(-Y$`!T
-M"@^^010/OED5ZQ`/MX1^LA$```^WG'ZV$0``BTT4BY$@F0``@>(?^/__P>`%
-M)>`'```)PHF1()D``(M-%(N!()D``(/@X(G:@^(?"=")@2"9``"+512+@B"9
-M``"`S`B)@B"9``!F@;YL$````$!V08M<)&0/MT,")=`````]T````'4+9H&^
-M;!```/]/=B*+312+D0RB``"!XO__`_^+!"3!X!(E``#\``G"B9$,H@``9H&^
-M;!````!0=@V+113'@."9````````N`$```"#Q$Q;7E]=PY!55U93@^QLQT0D
-M,`````#'1"0T`````(U\)%#\N@0```"X`````(G1\ZMFQT0D)@``QT0D(```
-M``#'1"0<`````&;'1"0X`0"-1"0X9L=``@(`9L=`!`(`9L=`!@$`9L=$)$`!
-M`&;'1"1"`@!FQT0D1`$`BYPDA`````^W:P+![0</MP.#Y0%T$XT$@(V$`"BF
-M__]FB40D*.L1B?:-!("-A`"80```9HE$)"B+A"2$````9H-X-`!T'V:+4#1F
-MB50D*NFB````@>'_/P``9HE,)"KI@@```)!FQT0D*@"`N%<```"+C"2$````
-M]D$"$'0"L*Z^``````^W7"0HB5PD%`^WP(E$)!"#[`15#[?&4/^T)(P```"+
-ME"20````_Y+$`0``B<&#Q!!F/0"`="J+7"04BWPD$(G8*?B)RH'B_S\``#G0
-M?PN-!#LYT`^-=?___T9F@_X$=J]FBUPD*HN,)(0```!FB5DT9H%\)"H`@`^%
-M&@$``(N$)(````"+4!2+@B"9``"I````0`^$I`0``(N"#)D``"7___\`B8(,
-MF0``BY0D@````(M"%(N0()D``('B____CXF0#)D``(N,)(````"+013'@*"9
-M````````BT$4QX"`F0```````(M1%(N"A)D``"4``/#_B8*$F0``BT$4QX"8
-MF0```````(M1%(N"G)D``"4``/#_B8*<F0``BT$4QX``F0```````(M!%,>`
-M!)D```````"+013'@`B9````````BU$4BX(,F0``)0#`__^)@@R9``"+013'
-M@(B9````````BT$4QX",F0```````(M!%,>`D)D```````"+412+@I29```E
-M`,#__XF"E)D``.FF`P``D`^W3"0J#[=$)"@IP8N<)(0````/MT,")?`!```]
-MT`````^$F@```#W0````?PP]P````'1*Z;<````]0`$``'0,/5`!``!T>>FD
-M````B<C!X!&)1"0@N!^%ZU'W;"0@P?H#BT0D(,'X'RG"B50D(,'Z"HE4)!QF
-MQT0D)C4,ZW*)RL'B"(E4)!RXE2!/"??JT?J+1"0<P?@?*<*)5"0<B<O!XQ&X
-M'X7K4??KP?H#B=C!^!\IPHE4)"!FQT0D)C4,ZS")R,'@$(E$)""X'X7K4?=L
-M)"#!^@.+1"0@P?@?*<*)5"0@P?H*B50D'&;'1"0F:AB-!(F-!("-!(")P<'A
-M!P^W5"0FB<B)TYGW^XG!J`]T"[\$````C6PD..L)OP,```"-;"1`O@````!F
-MA?\/A!0!``")R\'[!(/['`^/9`(```^WQHU$`QF)1"0,@_@@=S.#^!E_$K@!
-M````BDPD#-/@"40D,.LYD(-\)`P:?C&+1"0,2+H!````B,'3X@E4)##K'9"+
-M1"0,@^@A@_@3=Q"Z`0```(C!T^()5"0TC78`BT0D#$"#^`]W&@^WQ@^W1$4`
-MBTPD#(U,"0+3X`E$)%#K=HGVBT0D#(/H#X/X#W<<#[?&#[=$10"+3"0,C50)
-MXHC1T^`)1"14ZTZ)]HM$)`R#Z!^#^`]W'`^WQ@^W1$4`BTPD#(U4"<*(T=/@
-M"40D6.LFB?:+1"0,@^@O@_@&=Q@/M\8/MT1%`(M,)`R-5`FBB-'3X`E$)%Q&
-M#[?6#[_'.<(/C/'^__^+G"2`````BU,4BX(,F0``#0```/^)@@R9``"+0Q2+
-MD""9``"!R@```'")D""9``"+A"2`````BU@4BT0D','@%"4``/`_BU0D(('B
-M__\/``G0#0```$")@Z"9``"+E"2`````BT(4BTPD,(F(@)D``(N<)(````"+
-M4Q2+@H29```E``#P_XM<)#2!X___#P`)V(F"A)D``(N4)(````"+0A2+3"0P
-MB8B8F0``BX0D@````(M0%(N"G)D``"4``/#_"=B)@IR9``"+C"2`````BU$4
-MBT0D4(F"`)D``(M1%(M$)%2)@@29``"+412+1"18B8((F0``BUD4BX,,F0``
-M)0#`__^+5"1<@>+_/P``"=")@PR9``"+412+1"10B8*(F0``BU$4BT0D5(F"
-MC)D``(M1%(M$)%B)@I"9``"+612+@Y29```E`,#__XM4)%R!XO\_```)T(F#
-ME)D``(/$;%M>7UW#C78`5U93BW0D$(M$)!2Z````9/9``A!T!;H```#(]D`#
-M0'0$T>KK"F:#>`(`>0/!Z@(/MPB)T+H`````]_&)P[\?````B?:)V(GYT^BH
-M`74#3W7SN"8````I^(G'N!<```")PBGZL`&(T=/@`=BZ&````"GZB-'3Z(M>
-M%(N3%)@``('B__\!`,'@$0G"B9,4F```BUX4BY,4F```@>+_'_[_B?C!X`TE
-M`.`!``G"B9,4F```6UY?PXUV`(/L#(M4)!"+1"04@_@_=@6X/P```&:)@OP!
-M``"#[`2-1"0,4/^R-!```%+H_/___X/$',-55U93@^P4BVPD*(M<)"R)[_^U
-M>$0``/^U=$0``.C\____@\0(:B"-A7Q$``!0Z/S___]FBY7\`0``@\009H/Z
-M/WX%NC\```!F@_H^?PJY`````&:%TG4.BX4``@``9HN,``!2``"#[`2-1"0.
-M4(U$)!!0:@$/O\)0#[_!4%-5Z(0"``"#Q""Z`````(7`#X1H`@``@^P,_W0D
-M-%.-1"0>4(U$)"!05?^7N"H``(/$(+H`````A<`/A#\"``"#O<P!```'=#:#
-MO<P!```+="V#O<P!```*="2#O<P!```)=!N#O<P!```*=0IF@[W0`0```W8(
-M9H.'FD0```2^`````&:+A_`M``!F`81W?$0``&:#O'=\1```/W8*9L>$=WQ$
-M```_`$:#_@]VW6:#OYH0```!#X>F````9H.]T@$``$%W7`^W0P(ET````#W`
-M````=4QF@3NT"74C#[:/CA````^WAY@0```IP;AG9F9F]^F)T-'XP?D?9BG(
-MZQ(/MI>.$```N&=F9F;WZHG0T>B#[`@/M\!05>AT!P``@\00O@````"-'+4`
-M````BTT4BX=T1```#[=4L`+!XAB!R@``_P`/MP2PP>`(#/\E__\```G"B909
-M@*$``$:#_A]^Q8M-%`^WEX)$``"#XC_!XA@/MX>`1```@^`_P>`0"<(/MX=^
-M1```@^`_P>`("<(/MX=\1```@^`_"<*)D329``"+310/MY>*1```@^(_P>(8
-M#[>'B$0``(/@/\'@$`G"#[>'AD0``(/@/\'@"`G"#[>'A$0``(/@/PG"B9$X
-MF0``BTT4#[>7D$0``(/B/\'B&`^WAXY$``"#X#_!X!`)P@^WAYI$``"#X#_!
-MX`@)P@^WAXQ$``"#X#\)PHF1-*(``(M-%`^WEYA$``"#XC_!XA@/MX>61```
-M@^`_P>`0"<(/MX>41```@^`_P>`("<(/MX>21```@^`_"<*)D3BB``"+512#
-MO]@M```!&<"#X,"#P'^)@CR9``"Z`0```(G0@\0,6UY?7<.)]E575E.#[%2+
-M;"1LBT0D<&:)1"0FBU0D=&:)5"0DBW0D:(GQ@<%\1```B4PD(&;'1"0>/P!F
-MQT0D'#\`#[Y%!='@9HE$)!J+A"2`````9L<`P?^+5"1\9L<"/P!5_W0D;.C\
-M____B$0D(;L`````@\00BTPD8&:#N7`1````#X2%````#[9\)!&)^(/@^(E$
-M)`R-=@!F@[Q><A$```!T768/MD0D$68YA%YR$0``=!$/MX1><A$``(/@!PS@
-M.<=U/(G8P>`&C80PT!4``(/L"%`/MT4`4.A^!@``@\00@7PD#.````!U#F8Y
-M1"06=@YFB40D%NL'9HE$)!;K#$,/MX9P$0``.=A_C`^W10(ET````#W`````
-M#X6B````@&0D$?B`3"01`;L`````9H.^<!$````/A(\````/MGPD$8GZ@^+X
-MB50D")!F@[Q><A$```!T768/MD0D$68YA%YR$0``=!$/MX1><A$``(/@!PS@
-M.<=U/(G8P>`&C80PT!4``(/L"%`/MT4`4.C*!0``@\00@7PD".````!U#F8Y
-M1"04=@YFB40D%.L'9HE$)!3K&$,/MX9P$0``.=A_C.L*9HM,)!9FB4PD%/9%
-M`P%T"(J&BA```.L&BH:+$```@^P$#[[`4%7_="1LZ/S___^(1"0@@\00]D4"
-M0`^$TP$``(!]`@!Y)H/L#(U$)#Q0#[>&F!4``%"-AIH5``!05?]T)'SH9P8`
-M`(/$(.LD@^P,C40D/%`/MX9&%0``4(V&2!4``%!5_W0D?.A!!@``@\0@#[=4
-M)!(/OD0D$"G"#[=$)!8YPGX"B<*)T?9%`A!T0&:!OFP0````,'82#[>&>A``
-M``^_TCG0?@*)T(G!9H&^;!```/\_=AB`?0(`>1(/MX9\$```#[_1.=!^`HG0
-MB<$/MU0D-@^_P3G"?@*)PF:+1"0>T>")T68IP7D%N0````!F.TPD''X$BTPD
-M'(-\)'``#X3-````BT0D&&:)2`AFB4@&9HE(!&:)2`)FB0B)SXM$)#1F.<AV
-M`HG(BU0D&&:)0@J+1"089HL09HM$)#)F.=!V`HG0BU0D&&:)0@R+1"089HL0
-MBT0D,&8YT'8"B="+5"089HE"#HG"9H&^;!```/\_=D4/O]F`?0(`>0T/MX:`
-M$```.<-\#>L/#[>&?A```#G#?02)R.L6@'T"`'D)9HN&@!```.L'9HN&?A``
-M`(M,)!AFB4$>ZPN+3"089HL!9HE!'HM,)'@/OP&)ANPM``#K$HG/#[=$)#`/
-MO]$YT'X"B=")PHM$)'1FB1"+5"1X9HDZ#[=%`J@@=1`ET````#W`````#X4/
-M`0``@^P,C40D+%`/MX:X%0``4(V&NA4``%!5_W0D?.B"!```#[=,)#(/OD0D
-M,"G!#[=$)#2#Q"`YP7X"B<$/MU0D)@^_P3G"?@*)PF:+1"0>T>")T68IP7D%
-MN0````!F.TPD''X$BTPD'(-\)'``=&H/MT0D)@^_T3G0?@*)T(M4)!AFB4(0
-M#[=$)"0/O]$YT'X"B="+5"089HE"$HG#9HE"%`^W1"0B#[_1.=!^`HG0BU0D
-M&&:)0A9FB4(8#[=4)"`/O\$YPGX"B<*+3"089HE1&HG09HE1'.L>#[=$)"0/
-MO]$YT'X"B=")PP^W1"0@#[_1.=!^`HG0BU0D=&8Y`GX#9HD"BTPD>&8Y&7T$
-M9HD9D(-\)'``=!B+5"1X#[\"B8;$+0``BTPD8&:)@?X!``"X`0```(/$3%M>
-M7UW#55=64X/L$(ML)"3_="0L_W0D+%7_E;PJ``"#Q!"Z`````(7`#X2O````
-M9HN]_`$``&:#_S]^!;\_````9H/_/G\,9L=$)`8``&:%_W4>BX4``@``9HN$
-M``I2``!FB40D!NL)N@````#K;XGVO@`````[="0H<UV0BT0D)(T<\(/L!(U$
-M)`Y0C40D$%!J``^_QU`/OT0D&E!35>@]^O__@\0@A<!TO68/OD,&9CM$)`I^
-M"&:+1"0*B$,&9@^^0P=F.T0D"'X'BT0D"(A#!T8[="0H<J2Z`0```(G0@\0,
-M6UY?7<.055=64X/L0(ML)%1FBX66$```9HE$)`YJ((V%?$0``%"-1"0<4.C\
-M____9L=$)!X(`(/$$`^W1"0.9HM4)`IF*51$$+X`````9L=$)`P```^W?"0.
-MB7PD!&:#?'P0`'D(9L=$?!```)!F@_X(=0J^#P```.M0C78`BTPD!`^_5$P0
-M#[?>#[>$77Q$```YPG4T9H.\77Q$````=0=F_T1,$.L69H-\)`PR=@=F_T1\
-M$.L'9O],?!")]KX`````9O]$)`SK`49F@_X/=HT/MT0D#F:#?$00/WX'9L=$
-M1!`_``^W1"0.#[><17Q$```K7"14>0:[`````)`/MT0D#@^_3$00BY5T1```
-M9HL$6F:)!$IF_T0D#F:#?"0.#@^&$____V;'1"0."``/MU0D#F:+1%009HF$
-M57Q$``!F_T0D#F:#?"0.#G;A@\0\6UY?7<.05U93@^P@BUPD-(M\)#"Z````
-M`)!F@SS3`'0/9HL$TV:)1%000H/Z!W[JB=:#[`R-1"0:4(U$)!Q0#[?"4(U$
-M)"A0#[?'4.C\____N@````"#Q"`Y\GT=BT0D$&8[1"0,=!*+1"0,B?9".?)]
-M!V8Y1%00=?2+1"0,9CM$)`YU!68Y^'0,N#\```"#?-,$`'0%9HM$TP(/M\"#
-MQ"!;7E_#D%575E.+;"04BTPD&(M\)!R+7"0@BW0D)`^WPP^WU@^OPKH`````
-MA<!T88G89CG/=%</M\4/M\DIR(T$@(T$@,'@`@^WURG*B=&9]_F)PHG89H72
-M>#.)\&:#^F1_*P^_T@^WS@^ORKAD````*=`/M],/K\(!P;@?A>M1]^F)T,'X
-M!<'Y'V8IR)`/M]")T%M>7UW#B?955U93@^P\BVPD6(M\)%RZ``````^WQXG!
-M@_@`?A2)]HT$DF:+1$4(9HE$5"!".=%_[H/L#(U$)"I0C40D+%`/M]]3C40D
-M.%"+5"1P#[<"4.C\____O@````!FQT0D.@``N@````"#Q""#^P!^*XG8BWPD
-M'&:+3"0>C78`9CE\5"!U!6:)5"0:9CE,5"!U!8G6ZP:00CG0?^,/M_:--+;1
-MY@^W3"X&#[=<)!J-')O1XP^W1"L&B40D#`^W?"0>#[=4)!R)5"04BT0D5`^W
-M$%'_="005_]T)"!2Z([^__^#Q!2+5"1@9HE"!@^W1"X$B40D#`^W5"L$BT0D
-M5`^W"/]T)`Q25_]T)"!1Z%[^__^#Q!2+5"1@9HE"!`^W1"X"B40D#`^W5"L"
-MBT0D5`^W"/]T)`Q25_]T)"!1Z"[^__^#Q!2+5"1@9HE"`@^W!"X/MQ0KBUPD
-M5`^W"U!25_]T)"!1Z`?^__^+5"1T9HD"@\106UY?7<-55U93BU0D&(ML)""+
-M?"0D#[=,)!2-!(F-!("-#(4`````#[=<)!R-'%H/MP*-!("-!("-!(7V____
-M.<AV#F:+`F:)!V:)10#K?HGV#[=#_HT$@(T$@(T$A0H````YR',K9HM#_F:)
-M!V:)10#K6F:+`F:)!V:)10#K3F:+`F:)10!FBT("9HD'ZSZ)]CG:<S@/O_&0
-M#[\"C02`C02`P>`"*?"#P`F#^!)VQ`^W0@*-!("-!("-!(7V____.<AWNX/"
-M`CG:<LZ)]EM>7UW#C78`BTPD!(V1#"H```^W@=0!```E\````(/H,(/X/W<N
-MH:13``")@0PJ``"-!,"-!(6H4P``B4(<QT(8`0```,="#!0```#'0A!5````
-MPZ$D4@``B0*-!,"-!(4H4@``B4(<QT(8`0```,="#!0```#'0A`C````PXGV
-M55=64X/L#(M4)""+?"0D#[>"U`$``"7P````@^@P@_@_=TEJ`&HD:@&#[`QJ
-M!U+_DJPJ``"#Q!10Z(+C__^]`````+YK````N0````"[:P```(/$$(/X`75T
-M9KY3`+-3QT<0-P```.MEC78`:@!J)6H&@^P,:@=2_Y*L*@``@\044.@YX___
-MO0````"#Q!"^,@```(/X/W0#C7`$B>F#^#]T!;E`````C5DRB>J#^#]U!HU5
-M%(UV`(E7#(/X/W4(C4/QZP:-=@"-0P6)1Q"+5P2X`````#GJ<@0Y\G8-.<IR
-M!#G:=@6X`0```(/$#%M>7UW#D(M$)`0/OY#P+0```Y#L+0``BT@4P>()@>(`
-M?@``@,Z`B9$PF0``QX#`+0```0```,.-=@!75E.+?"00B?N-MPPJ``"X````
-M`(-^&``/A.@```"#O\`M```!#X75````BT<4BX`PF0``9H7`#XC#````B<+!
-MZAF)5@0E``"``<'H%X/X`G4<9H._T@$``$%V#@^WAY80```!T(E&!.L$@T8$
-M!0^WA]0!```E\````(/H,(/X/W<C@^P,5^B=`0``@\00BT8$.T84<@@K1A2)
-M1@3K!\=&!`````#'@\`M````````@^P(5E?H'_[__X/$$(7`=4"#[`A65^A"
-M````@\00A<!T+X/L"%97Z$T```"#Q!"%P'X>QX/`+0```@```,>#U"T```$`
-M``#'@[PM````````BX/`+0``6UY?PXGVBTPD"+@`````BU$$.U$,=@4[41!R
-M!;@!````PU93BUPD$(M$)`P/MX#4`0``)?````"#Z#"^H%,``(/X/W8%OB!2
-M``"+`XT$P(U$A@B)0QR+0P0[0Q!R6+K_____@SL`#X2N````BT,$B4,(.T,0
-M<C>#.P!T,HGVBQ-*B1.-%-*-%):+2QR+0A@K01#1X(M+""G!B4L(@\((B5,<
-M.TL0<@>#.P!UTHGVN@$```#K99"+0P2Z`````#M##'=7BP9(NO[___\Y`W1+
-MBT,$B4,(.T,,=SB+!D@Y`W,QD(L30HD3C132C126BTL<BT(8*T$0T>"+2P@I
-MP8E+"(/""(E3'#M+#'<'BP9(.0-RT+H"````C78`B=!;7L.-=@!75E.+7"00
-MC;,,*@``QT84`````&H`:B1J`8/L#&H'4_^3K"H``(/$%%#H0>#__X/$$(/X
-M`759BT8<#[\X:@!J(&H$@^P,:@=3_Y.L*@``@\044.@8X/__@\00@_\!=!J#
-M_P%R#(/_`G05@_\#=!GK'\=&%`````#K%HE&%.L1C40`^XE&%.L(T>")1A2-
-M=@!;7E_#55=64X/L%(MT)#"+7"0T5O]T)##H_/___XG%C7O_P>\#2X/C!X/$
-M$(7V?G*+1"0PP>`#B40D")"-##.#^0A^!;D(````N@$```#3XDJX`0```(C9
-MT^!(,<**3"0(T^*)T??1BT0D(",,N(E,)`2)Z(C9T^"*3"0(T^`AT`M$)`2+
-M5"0@B02ZC70>^+D(````*=G3[;L`````1X7V?YJ#Q`Q;7E]=PXGV55=64X/L
-M#(M$)"3V0`-`=!N#[`AH``(``/]T)"SH_/___XG'@\00ZU"-=@"+5"0D9H-Z
-M`@!Y&(/L"&@`!```_W0D+.C\____B<>#Q!#K*H/L"(M4)"P/MT("@^`0@_@!
-M&<`E_@```(/``E#_="0LZ/S___^)QX/$$+T`````@S\`?CR0C41M`(U$AR`/
-MME@(P>,"BU0D((MR%(/L#&H`#[9`"U!J#E=2Z/S___\/M\")A!X`AP``@\0@
-M13DO?\6+1"0D]D`"$`^%KP```(/L"&H(_W0D+.C\____B<>]`````(/$$(,X
-M``^.C@```(GVC41M`(UTAR`/MD8(C02%`(<``(E$)`B`?@4`=6.+5"0@BUH4
-M@^P,:@`/MD8+4&H.5U+H_/___P^WP(M4)"B)!!.#Q""`?@D`=#8/MD8)C02"
-MB40D"(M$)""+6!2#[`QJ`0^V1@M0:@Y7_W0D/.C\____#[?`BU0D*(D$$X/$
-M()!%.2\/CW?___^-=@"#Q`Q;7E]=PU575E.#[`2+3"08BT$4BX`<@```B<.!
-MXX`_``"+1"0<]D`#0'0>QP0D!`$``+X``!L`N!,```"_K`T``+T4````ZQR0
-MQP0DT@```+X``#8`N`D```"_2`T``+T*````BU$4"=@)\`T``(`?B8(<@```
-MBT$4BQ0DB9!P$```BT$4B;BP$```BTD4BX'P$```)?\#\/^)ZL'B"@G0B8'P
-M$```@\0$6UY?7<.0D)!55U93@^P4BWPD*(N'0"H``"7___]_4%?H_/___XG%
-MBT<4BU`PB=.!X_`#``#!ZP2)WH/$$(-\)"0`=!"X)0```"G8T>B--`/K"(GV
-M@_L"@];_.=YT&(M/%('B#_S__XGPP>`$)?`#```)PHE1,(/L"%57Z/S___\Y
-MW@^5P`^VP(/$'%M>7UW#5E.#[`2+3"00BU0D%`^W@>@!``"[`````#G0?B.#
-M[`3_="0<C012C02`C82!W"H``%!1Z/S___^)PX/$$(UV`(G8@\0$6U[#5E.#
-M[`2+3"00BU0D%`^W@>@!``"[`````#G0?B.#[`2-!%*-!("-A('<*@``4/]T
-M)"!1Z/S___^)PX/$$(UV`(G8@\0$6U[#55=64X/L#(ML)""+?"0DB>F-E>`!
-M``#'1"0("P```(/_`G0<@_\"=PN#_P%T5NF)````D(/_`W07@_\$="/K?`^W
-M<@A.@4PD",``!0#K=9`/MW((@^X"@4PD",`!!0#K8P^W<@B#[@.-!':-!("Z
-M_____X.\A>`J````#X7!````ZT&0O@`````/MT((B<.#^`!^%8T$=HT$@(.\
-M@>`J````=`5&.?-_ZP^W0@BZ_____SGP#X2(````ZPBZ_____^M_D(T$=HT$
-M@(V<@=PJ``"Z_____X-[!`!U9H/L"&H\4^C\____B7L$@\00@WPD*`!U-(M$
-M)`B)0PS'0Q0"````QT,8_____\=#'/\#``!FQT,@"@!FQT,B"@#'0S0`````
-MZQN-=@"+5"0HBT(PB4,T@^P$4E95Z/S___^#Q!")\HG0@\0,6UY?7<-3BTPD
-M"(M9%(N1R"H``('B_P,``(N!T"H``,'@$"4``/\#"<*)DZ0```"+612+D<PJ
-M``"!XO\#``"+@=0J``#!X!`E``#_`PG"B9.H````BUD4BX.L````)0#\__^+
-MD=@J``"!XO\#```)T(F#K````%O#D%=64XM\)!"+3"04#[>'Z`$``+X`````
-M.<AV58T$28T$@(V<A]PJ``"^`````(-[!`!T/<=#!`````"X_O___]/`(8?(
-M*@``(8?,*@``(8?0*@``(8?4*@``(8?8*@``4U?H)O___[X!````@\0(B?:)
-M\%M>7\.)]E575E.#[`B+;"0<BTPD((GNB[TT$```#[>%Z`$``+H`````.<@/
-MAG4#``"-!$F-!("-G(7<*@``N@$```"#>P0`#X19`P``@WL8_W4SA?]T%0^W
-M1P(EH````+H?````/:````!T!;H/````N`$````YT',/T>"#R`$YT'+WZP20
-MBT,8C3R-`````(G"@>+_`P``BT,<P>`*)0#\#P`)PHM#%,'@%"4``/`/"<*+
-M112)E#A`$```#[=#(L'@!"7P````#[=3((/B#PG0#0`@"`"+512)A#J`$```
-MQT0D!``(``#'!"0``0``@WLD`'0MBU,D@>+___\`BT,HP>`8"<*+112)E#C`
-M"```@WLH`1G2L@"!P@$)``")5"0$@WLP`'0>C3R-`````(M5%(M#,"7___\`
-M#0````&)A#H`"0``C3R-`````(M5%(M#+"7__P\`@WLL`'0%#0``$`")A#K`
-M$```@WLP`'0.]D,,('0(@4PD!``"``#V0PQ`=`J#9"0$\(-,)`0"]D0D!`]T
-M)?9##0%T!X-,)`1`ZP6#9"0$OX![#`!Y!X-,)`0@ZP:#9"0$WY#V0PX!=`>!
-M#"0``"``]D,.@'0'@0PD``(``/9##@1T#($,)```!`#K$XUV`/9##@)T"H$,
-M)````@"-=@#V0PX(=`>!#"0`0```]D,.$'0'@0PD```0`(M#!(/X`G0'@_@#
-M=!/K5X%,)`2B````@0PD```E`.M&@TPD!&*#>S``=3.+%0`````K%0````"+
-MAN`M```IT"L%`````,'@"HT\C0````"+510-`````8F$.@`)``"!#"0```0`
-MD/9#.`%T!X$,)```)`"-!(T`````BU44BWPD!(F\`L`)``"+512+/"2)O`(`
-M$0``@WLT`'0ZBU44C40)4(F"``L``(M5%(M#-(F"!`L``(M%%,>`"`L```D`
-M``"+512+A(K`"0``@,P0B82*P`D``/9##`%T#[@!````T^`)AL@J``#K#;C^
-M____T\`AAL@J``#V0PP!=!&X`0```-/@"8;,*@``ZP^)]KC^____T\`AALPJ
-M``#V0PP"=!&X`0```-/@"8;0*@``ZP^)]KC^____T\`AAM`J``#V0PP$=!&X
-M`0```-/@"8;4*@``ZP^)]KC^____T\`AAM0J``#V0PP(=!&X`0```-/@"8;8
-M*@``ZP^)]KC^____T\`AAM@J``!35>A\^___N@$```"#Q`B)T(/$"%M>7UW#
-MB?:+1"0(P>`"BU0D!(M2%(N$`@`(``##B?:+5"0(P>("BT0D!(M(%(M$)`R)
-MA!$`"```N`$```##D(M,)`B+1"0$BU`4N`$```#3X(F"0`@``+@!````PXGV
-M5E.+5"00P>("BT0D#(MP%(N$%@`*``")PX/C`W4:N`$```"*3"00T^"+ED`(
-M``"%PG0%NP$```")V%M>PXUV`%575E.#[`R+="0@BWPD)(M6%+@!````B?G3
-MX(F"@`@``+WH`P``B?975NC\____@\0(A<!T$(/L#&IDZ/S___^#Q!!-=>)7
-M5NC\____@\0(A<`/A/(```"#OLP!```'=#:#OLP!```+="V#OLP!```*="2#
-MOLP!```)=!N#OLP!```*#X7!````9H.^T`$```,/A[,```"[`````(M&%(N0
-M3(```,>``($``&0`"@"+3A3!Z@H/M\(-```!`(F!_(```(M&%(N`3(```,'H
-M"CG0=`9#@_L!=L.+5A2+@DB````-``!``(F"2(```(/L#&C(````Z/S___^+
-M5A2+@OR````E___^_XF"_(```(/$$+MD````ZQ!+=!N#[`QJ"NC\____@\00
-M5U;H_/___X/$"(7`=>*+5A2+@DB````E__^__XF"2(```(M&%,>`@`@`````
-M``"%[0^5P`^VP(/$#%M>7UW#D%575E.+;"0TBWPD/(MT)!B+1"04#[^`\"T`
-M``-$)"B#^#]V!;@_````BU0D'('B_P\``,'@$`G"]\<@````=`:!R@``@`"+
-M1"0XP>`9)0```!X)T/?'`0```'0%#0````'WQQ````!T!0T````@B48(BUPD
-M),'C%(M,)%#!X1F+5"1(P>(=BT0D3,'@&PG9"=$)P??'`@```'0&@<D````!
-MB4X,BT0D,,'@$"4```\`]\=`````=`.`S(")1A"+1"0LB484@_W_=!2)Z,'@
-M#24`X`\`"48,@4X(````0/?'#````'1+N`#_`'^*3"1`T_BZ`````*@!=#R)
-M^(/@"(/X`1G`]]`E````@/?'!````'0%#0``0``)1@B+1"1$)?]_```)1A"+
-M1"1`P>`4"484N@$```")T%M>7UW#C78`4XM$)!2+3"0<BUPD)(M4)`R%P'0;
-MP>`4)0``\``+0A"`S(")0A"+1"00P>`%"4(4A<ET'8G(P>`8)0````\+0A"`
-MS(")0A"+1"08P>`*"4(4A=MT&(G8P>`<"T(0@,R`B4(0BT0D(,'@#PE"%+@!
-M````6\.+1"0(@4@(````(,-3BT0D$(M,)!B+7"0<BU0D#(-\)!0`=!`+0@R%
-MR74#@,P0B4(,ZSF0A<ET&,=""`````")0@R+0Q")0A"+0Q2)0A3K',=""```
-M``"`S!")0@S'0A``````QT(4`````)#'0AP`````QT(8`````+@!````6\.-
-M=@"+3"0,BU0D"+@/````]D(<`0^$2P$``(M"'"7^'P``T>AFB0$/MT(:9HE!
-M`L9!!`"+0ABH`74=J`)T!,9!!`'V0A@(=`2`200"]D(8!'0%@$D$!)"+0APE
-M``!@`,'H%8A!"P^VP(/X`70F@_@!?PF%P'01ZU>-=@"#^`)T)X/X`W0VZTB*
-M0A2#X!^(007K/9"+0A0EX`,``,'H!8/(@(A!!>LID(M"%"4`?```P>@*@\B`
-MB$$%ZQ60BT(4)0"`#P#!Z`^#R("(006-=@"+0APE`.`?`,'H#8A!!HM"&"7P
-M````P>@$B$$'BT(8)0`/``#!Z`B(00@/MD$+@_@"="&#^`)_"(/X`70EZS&0
-M@_@#=2N+0A`E````#\'H&`!!")"+0A`E``#P`,'H%`!!"(M"$"4```\`P>@0
-M`$$(BT(8)0#P``#!Z`R(00F+0APE`````8/X`1G`@\`"B$$*N`````##D(M$
-M)`2+3"0(BQ$CD)Q$``")$??2(9"<1```PY!3@^P0BUPD&(V#@"H``%!3Z/S_
-M__^+0Q3'@"2!````````BT,4QX`H@0```````(M#%,=`0`````"+0Q3'@#"!
-M``````(`BT,4QX`X@0```````H/$&%O#4X/L$(M<)!B+0Q3'0$`&````C8.`
-M*@``4%/H_/___XM#%,>`)($```````"+0Q3'@"B!````````@\086\.)]E93
-MBW0D$(M<)`RZ`````)"-!)*-!$)FBX3#)"X``&8[!G4%B=#K/)"-!)*-!$*-
-MC,,@+@``9H-Y!`!U'&:+!F:)001FBT8"9HE!!HI&!(A!"(G0ZPZ-=@!"@_H_
-M=K*X`````%M>PXGVBT0D!(N`("X``,.04X/L$(M<)!B-@X`J``!04^C\____
-MC8-$*@``@\086\-75E.+?"00B?X/MH?C`0``@^`!B8<8+@``@^P(:``6``"-
-MAR0N``!0Z/S___^[`````(/$$(UV`(._S`$```9W$XT$FXT$0\:$QBPN```'
-MZQ&-=@"-!)N-!$/&A,8L+@```HT$FXT$0XT,QL>!."X``/0!``#'@3PN``#(
-M````QX%`+@``R````,>!1"X``&0```#'@4PN```H````QX%(+@``!P```(V!
-M("X``,9`$`#&0!$`BE`,B%`.QD`/`(.^&"X```!T%,>!:"X```S^OP#'@6PN
-M```X_[\`0X/[/P^&4O___X.^&"X```!T*HM7%(N&:"X``(F"+($``(M7%(N&
-M;"X``(F"-($``(/L#%?H_/___X/$$,>&'"X``&0```"#?"04`'0)@XX4+@``
-M`>L'@Z84+@``_EM>7\.)]E.#[`B+7"00@[L8+@```'0G@^P,4^C\____BT,4
-MQX`L@0```````(/$$(M#%,>`-($```````"0@\0(6\.-=@!55U93@>R,````
-MBY0DI````(N<)*@```"+K"2@````BX4@+@``B40D%+@`````@_H&#X?Z!```
-M_R25,%4``(G>N`````"#^P0/A^,$``"+E"2@````BTH4BY%0F```@>+__P_P
-MBX2=)$0``,'@%"4``/`/"<*)D5"8``"+O"2@````BT\4BY%<F```@>)_@/__
-MBX2=3$0``,'@!R6`?P``"<*)D5R8``"+3Q2+D5R8``"!XO]_P/^+A)TX1```
-MP>`/)0"`/P`)PHF17)@``(M/%(N16)@``('B__\#_(N$G6!$``#!X!(E``#\
-M`PG"B9%8F```BU0D%`^V0@DYV',(_X5$*@``ZQ*+3"04#[9!"3G8=@;_A4@J
-M``")\(M4)!2(0@GI!`0``,=$)$A_````C70D2,=&!#(```#'1"1`?P```,=$
-M)$0H````QT0D.'\```#'1"0\30```,=$)#!_````QT0D-$````#'1"0H'P``
-M`,=$)"P0````QT0D(#\```#'1"0D,````(7;#Y7`#[;`B40D$(N\)*````"+
-M3Q2+D6R8``"!XO\_X/^)P\'C`HL$,\'@#B4`P!\`"<*)D6R8``"+3Q2+D6R8
-M``"!XO__'_"+1!Q`P>`5)0``X`\)PHF1;)@``(M/%(N1:)@``('B__\!_XM$
-M'#C!X!$E``#^``G"B9%HF```BT\4BY%HF```@>+___^`BT0<,,'@&"4```!_
-M"<*)D6B8``"+3Q2+@6B8``"#X."+5!PH@^(?"=")@6B8``"+3Q2+D6R8``"`
-MYL"+1!P@P>`()0`_```)PHF1;)@``(-\)!``=!2+5Q2+@FR8``"#R`&)@FR8
-M``#K&8N$)*````"+4!2+@FR8``"#X/Z)@FR8``"#?"00``^4P`^VP(M,)!0/
-MME$,.=`/A'0"``"#?"00`'0(_X54*@``ZP;_A5@J``"#?"00`(M\)!0/E$<,
-MZ4T"``#'1"08"````(U4)!C'0@0&````A=L/E<`/MMB+A"2@````BT@4BX$(
-MH@``@^#`BQ2:@^(_"=")@0BB``"+5"04#[9"#3G8#X0!`@``A=MT"/^%7"H`
-M`.L&_X5@*@``BTPD%(A9#>GC`0``QT0D<`````#'1"1T!````,=$)'@(````
-MB=ZX`````(/[`@^'P`$``(N\)*````"+3Q2+D5B8``"!XO\/_/^+1)QPP>`,
-M)0#P`P`)PHF16)@``(M4)!0/MD(+.=AS"/^%9"H``.L2BTPD%`^V00LYV'8&
-M_X5H*@``B?"+5"04B$(+Z5T!``"-3"10B4PD#+X050``_+D(````BWPD#/.E
-MB=ZX`````(/[!P^'.0$``(N$)*````"+2!2+D229``"`X@&+1)Q0T>`E_@``
-M``G"B9$DF0``BU0D%`^V0@HYV',(_X5,*@``ZQ*+3"04#[9!"CG8=@;_A5`J
-M``")\(M4)!2(0@KIV@```(7;=4"#I10N``#]@^P,_[0DK````.C\____@\0$
-M_[0DK````.C\____@\0(@.3^4/^T)*P```#H_/___X/$$.F6````]H44+@``
-M`@^%B0```(.]&"X```!T5(/L#/^T)*P```#H_/___X/$"(#D_E#_M"2L````
-MZ/S___^+C"2P````BU$4BX5H+@``B8(L@0``BU$4BX5L+@``B8(T@0``B0PD
-MZ/S___^#Q!#K)8/L#/^T)*P```#H_/___X/$"(#,`5#_M"2L````Z/S___^#
-MQ!"#C10N```"N`$```"!Q(P```!;7E]=PU93@^P$BTPD$(G.BYD@+@``QT,0
-M`````(.Y&"X````/A(,```"!>Q0``,``=@K'0T0`````ZPR0N```P``K0Q2)
-M0T2!>QP``,``?@S'0T@`````ZPZ-=@"X``#``"M#'(E#2(M1%(M#1(F"+($`
-M`(M1%(M#2(F"-($``(M!%,>`,($``````@"+013'@#B!```````"@^P(C8:`
-M*@``4%'H_/___X/$$,=#/`````#'0T``````@\0$6U[#5U93BW0D$(N^-!``
-M`(N&%"X``(/@`X/X`P^%+0$``(N>("X``(!["0-W&8/L!`^V0PE`4&H!5NC\
-M____@\00Z0@!``"*0PHZ0PAS&(/L!`^VP$!0:@56Z/S___^#Q!#IZ````(N.
-ME"H``(G(@^!_@_@_=@B-07_!Z`?K"8N&E"H``,'H!SE#*'U(@'L,`'4B@^P$
-M:@!J`E;H_/___X/$#&H`:@56Z/S___^#Q!#IF@```(!["P$/AY````"#[`0/
-MMD,+0%!J!%;H_/___X/$$.MZ.4,D?3*`>PP`=!"#[`1J`6H"5NC\____@\00
-M@'L+`7=9@^P$#[9#"T!0:@16Z/S___^#Q!#K0X/L"%=6Z/S___^#Z`*#Q!"#
-M^`%W+H![#`!U$(/L!&H`:@)6Z/S___^#Q!"`>PL`=!*#[`1J`&H$5NC\____
-M@\00B?9;7E_#5U93BUPD$(N[-!```(N#%"X``(/@`X/X`P^%E0```(NS("X`
-M`(!^"0-W&8/L!`^V1@E`4&H!4^C\____@\00ZW.-=@"+DY0J``")T(/@?X/X
-M/W8(C4)_P>@'ZPF+@Y0J``#!Z`<Y1B1]'(!^"P%W1(/L!`^V1@M`4&H$4^C\
-M____@\00ZRZ#[`A74^C\____@^@"@\00@_@!=QF`?@L`=!.#[`1J`&H$4^C\
-M____@\00C78`6UY?PU=64XM<)!")W_^S-!```%/HU_7__XT4@(T44(VTTR0N
-M``")LR`N``"#Q`B#N]P!```!=0R#BQ0N```"ZPJ-=@"#HQ0N``#]@[O<`0``
-M`71L_X=T*@``@^P$:@!J`5/H_/___X/$#&H`:@53Z/S___^#Q`QJ`&H$4^C\
-M____@\0,:@!J`E/H_/___X/$#&H`:@-3Z/S___^)'"3H_/___X/$"(#,`5!3
-MZ/S___^)'"3HB/S__X/$$.DD`0``BX,4+@``@^`#@_@##X42`0``@WPD%`!T
-M6X/L!`^V1@E0:@%3Z/S___^#Q`P/MD8*4&H%4^C\____@\0,@'X,``^4P`^V
-MP%!J`E/H_/___X/$#`^V1@U0:@-3Z/S___^#Q`P/MD8+4&H$4^C\____@\00
-MZT>#[`1J!&H!4^C\____@\0,#[9&"%!J!5/H_/___X/$#&H!:@)3Z/S___^#
-MQ`QJ`6H#4^C\____@\0,:@)J!%/H_/___X/$$(._&"X```!T/8/L#%/H_/__
-M_X/$"(#D_E!3Z/S___^)'"3HGOO__XM#%,>`,($``````@"#Q!"+0Q3'@#B!
-M```````"ZR.#[`Q3Z';[__^)'"3H_/___X/$"(#,`5!3Z/S___^#Q!")]EM>
-M7\-75E.+="00BUPD%(GWBT84QX`D@0```````(M&%,>`*($```````"#[`B-
-MAH`J``!05NC\____BP.)AI0J``"+0P2)AI@J``"+0PB)AIPJ``"+1A2+D"R!
-M``"+B#2!``")T"4``,``@\00/0``P`!T#HG()0``P``]``#``'5ABY\@+@``
-M*U-$B=`K0SP!AVPJ``")4SR)RBM32(G0*T-``8=P*@``B5-`BT,\.T,4=@^#
-M[`Q6Z%K[__^#Q!"-=@"+0T`[0QQV#(/L#%;HD_S__X/$$(/L#%;H>_K__X/$
-M$%M>7\-3@^P(BUPD$(M$)!2+DR`N``"`>`41=2C_0CS_@VPJ``"+0CP[0A1V
-M0X/L#%/H_OK__XD<).@Z^O__@\00ZRV0@'@%&74F_T)`_X-P*@``BT)`.T(<
-M=A6#[`Q3Z"#\__^)'"3H#/K__X/$$)"#Q`A;PXUV`%93@^P$BW0D$(N.("X`
-M`(N6E"H``(G0@^!_@_@_=@F-0G_!Z`?K"I"+AI0J``#!Z`<Y02A\5CE!)'TU
-M@'D,`'03@^P$:@%J`E;H_/___X/$$.MQD(!Y"P!T,H/L!`^V00M(4&H$5NC\
-M____@\00ZU2`>0L`=!:#[`0/MD$+2%!J!%;H_/___X/$$.LX@'D*`'06@^P$
-M#[9!"DA0:@56Z/S___^#Q!#K'(!Y"0!T%H/L!`^V00E(4&H!5NC\____@\00
-MB?:#Q`1;7L.)]E575E.+5"04BT(4B[CL@```BZCP@```B[#X@```BYH@+@``
-M@WLX`'0%.7,X=@ZY`````/^">"H``.LID(GQ*TLXB>@K0S2)^BM3,"G!*=&X
-M*3E37_?IP?H.B<C!^!^)T2G!B?:)<SB)>S"):S2)R%M>7UW#55=64X/L#(M\
-M)""+5"0DB?V+GR`N``"+`HF'E"H``(M"!(F'F"H``(M""(F'G"H``(7;#X27
-M`0``5^A-____B<:#Q`2%P'D4_X=\*@``@^P,5^AI^/__@\00B?8!<Q"#O1@N
-M````#X28````@^P(C86`*@``4%?H_/___XM'%(N0+($``(N(-($``(/$$#E3
-M1'<-.4M(=D@Y4T1V'(UV`(M'%(M31(F0+($``(M'%,>`,($``````@`Y2T@/
-MA@X!``"+1Q2+4TB)D#2!``"+1Q3'@#B!```````"Z?`````K4T2)T"M#/`&%
-M;"H``(E3/(G**U-(B=`K0T`!A7`J``")4T"+AQ0N``"#X`.#^`,/A;H```"+
-MA1PN``"-!(`Y0Q!V1HM+$(G(#Z]#&+[336(0]^:)T,'H!CE#/'<>B<@/KT,@
-M]^:)T,'H!CE#0'<,@^P,5^AG_?__@\00@^P,5^A;]___@\00ZV:+0Q`[A1PN
-M``!V6XG"#Z]3%+C336(0]^*)T,'H!CE#/'86@^P,5^CG]___B3PDZ"/W__^#
-MQ!#K+HM#$`^O0QRZTTUB$/?BB=#!Z`8Y0T!V%H/L#%?H"?G__XD\).CU]O__
-M@\00B?:#Q`Q;7E]=PXM,)`2+5"0(BX$T$```9HL`9HD"BX$T$```@$@$"(!*
-M!`B+@300``!FBT`"9HE"`HN!-!```(I`!(A"!(N!-!```(I`!8A"!;@`````
-MPY"055=64X/L#(M\)""+;"0HBUPD++X`````C01VBT\4BQ3%8%4``(E4)`B+
-M5"0DC01"BP2%8%4``(M4)`B)!!%#]L,_=1"#[`QJ`>C\____@\00C78`1H/^
-M#7:^O@````"0BT\4BQ3UP%8``(L$]<16``")!!%#]L,_=0Z#[`QJ`>C\____
-M@\00D$:#_D=VTKX`````D(T$=HM/%(L4A:!:```!Z(L$A:!:``")!!%#]L,_
-M=0V#[`QJ`>C\____@\001H/^/W;.@\0,6UY?7<.)]E575E.#[!"+;"0DBU0D
-M*`^W0@)0#[<"4%7H_/___X/$$(M<)"2`>P(`>6D/O_"-'';!XP*-LR1A``"#
-M[`AJ"/]V!.C\____B<>!Y_\```#!YP6+@R1A``#!X`0)QV:+3@B+512+@@2B
-M``"#Q!"+7"0D9H$[M`EU#(/($(F"!*(``.L8D(M5%(/@[XF"!*(``.L)B?:)
-MP;\`````9H'YD`!_!?;!`70E@^P(:@@/O\&#Z!A0Z/S___^)PX'C_P```+@!
-M````@\00ZRZ)]H/L"&H(#[_!@^@8B<+!ZA\!T-'X4.C\____B<.!X_\```"X
-M`````(/$$(GVP>,"T>`)PX'+`00``(M-%(GX)?\```#!X`@/MM,)T(F!G)@`
-M`(M-%(GX)0#_```/MM<)T(F!T)@``(M$)"2)A300``"X`0```(/$#%M>7UW#
-MC78`BU0D"(M$)`2+@.@M``"#^@=W(?\DE6AB``")]H/`1,.#P$C#@\!,PX/`
-M4,,%E````,.)]K@`````PXGV55=64X/L?(NL))````"+A"28````9HE$)!Z)
-M;"08OP````"+E"24````#[="`B7P`0``/<`````/A.`!```]P````'\0/:``
-M```/A%,!``#I00(``#U``0``=`L]4`$```^%+P(``(N4))0```!FBP(MH0\`
-M`&8]Z@1W)8M$)!AFBX!0$0``9HE$)`Z+5"089HN24A$``&:)5"0,Z:P```"+
-ME"24````9HL"+8P4``!F/>\`=R*+1"089HN`5!$``&:)1"0.BU0D&&:+DE81
-M``!FB50D#.MUBY0DE````&:+`BU\%0``9CW@`'<BBT0D&&:+@%@1``!FB40D
-M#HM4)!AFBY):$0``9HE4)`SK/HN$))0```!F@3A<%G8BBU0D&&:+DEP1``!F
-MB50D#HM$)!AFBX!>$0``9HE$)`SK#F;'1"0,``!FQT0D#@``QT0D"`````"^
-M`````(M4)!AFBY+4$```9HE4)!:+1"089HN`VA```&:)1"04BU0D&&:#NMH0
-M````#Y3`9@^VP&:)1"029HN"*!$``&:)1"00Z?T```"+5"089HN28!$``&:)
-M5"0.BT0D&&:+@&(1``!FB40D#(M4)!@/M[)H$0``#[>";!$``(E$)`AFBY+6
-M$```9HE4)!:+1"089HN`W!```&:)1"04BU0D&&:#NMP0````#Y3`9@^VP&:)
-M1"029HN"*A$``&:)1"00Z8(```"+5"089HN29!$``&:)5"0.BT0D&&:+@&81
-M``!FB40D#(M4)!@/M[)J$0``#[>";A$``(E$)`AFBY+8$```9HE4)!:+1"08
-M9HN`WA```&:)1"04BU0D&&:#NMX0````#Y3`9@^VP&:)1"029HN"+!$``&:)
-M1"00ZPJX`````.E5`P``NP`````/MU0D'KD`60``D(T$6XT$0HL$@8E$G"!#
-M@_L0=NV+E"24````@'H"`'DJ@^P,:@!J=VH#5HU<)#Q3Z/S___^#Q!1J`&IZ
-M:@/_="0@4^C\____@\0@NP````"0C01;BTT4BQ3%`%D``(M$G"")!!%']\<_
-M````=0^#[`QJ`>C\____@\00B?9#@_L0=LZ[`````(M-%(L4W:!=``"+!-VD
-M70``B0011_?'/P```'4-@^P,:@'H_/___X/$$$-TT[L`````#[=T)!Z-!%N+
-M312+%,6H70``C01&BP2%J%T``(D$$4?WQS\```!U#8/L#&H!Z/S___^#Q!!#
-M=,V[``````^W="0>C01;BTT4BQ3%P%T``(T$1HL$A<!=``")!!%']\<_````
-M=0V#[`QJ`>C\____@\000W3-NP`````/MU0D'KG@70``C78`C01;C01"BP2!
-MB42<($.#^Q!V[8N4))0````/MT(")4`!```]0`$``'4]@^P,:@-J,VH!BU0D
-M,`^W@L@1``!0C5PD/%/H_/___X/$%&H#:BUJ`8M4)#`/MX+*$0``4%/H_/__
-M_X/$((/L#&H`:E]J`0^W1"0J4(U<)#Q3Z/S___^#Q!1J`&I@:@0/MT0D+E!3
-MZ/S___^#Q!1J`&IH:@,/MT0D)E!3Z/S___^#Q!1J`&IK:@,/MT0D)%!3Z/S_
-M__^[`````(/$()"-!%N+312+%,7@70``BT2<((D$$4?WQS\```!U#X/L#&H!
-MZ/S___^#Q!")]D.#^Q!VSKL`````#[=4)!ZY@%\``(UV`(T$6XT$0HL$@8E$
-MG"!#@_L'=NV#[`QJ`&H=:@8/MT0D*%"-7"0\4^C\____@\04:@!J!&H!#[=$
-M)"Q04^C\____@\0@BX0DE````&:#>`(`>`;V0`-`=%2+E"24````#[="`B4`
-M0```@_@!&=N#XP^#PQ"#[`QJ`&H3:@5J'XUT)#Q6Z/S___^#Q!1J`&H8:@53
-M5NC\____@\04:@!J,6H":@-6Z/S___^#Q""[`````(UV`(T$6XM-%(L4Q8!?
-M``"+1)P@B0011_?'/P```'4/@^P,:@'H_/___X/$$(GV0X/[!W;.BT0D&,>`
-MP"T```````"X`0```(/$?%M>7UW#C78`55=64XML)!2+3"08BWPD'(M<)""+
-M="0D#[?##[?6#Z_"N@````"%P'1AB=AF.<]T5P^WQ0^WR2G(C02`C02`P>`"
-M#[?7*<J)T9GW^8G"B=AFA=)X,XGP9H/Z9'\K#[_2#[?.#Z_*N&0````IT`^W
-MTP^OP@'!N!^%ZU'WZ8G0P?@%P?D?9BG(D`^WT(G06UY?7<.)]E575E.![$P!
-M``"+A"1@`0``B40D'&;'1"08``!FQT0D%C\`BY0D;`$```^W0@(E\`$``#W0
-M````#X2#````/=````!_$SV@````=$X]P````'1NZ8T````]4`$``'07/5`!
-M``!_"3U``0``=`GK=CU`"0``=6^+3"0<9HN!XA$``&:)1"0DB<@%SA$``(E$
-M)""-0!:)1"0HZU6+7"0<9HN#[!,``&:)1"0DB=@%]!,``(E$)""-@+8```")
-M1"0HZRZ+5"0<9HN"[!,``&:)1"0DB=`%[A,``(E$)""-0"")1"0HZPJX````
-M`.G8`@``C70D((/L"&@(`0``C40D/%#H_/___XVL),@```"_`0```+L`````
-M@\00C78`9HE\7#A'0X/_/W[T9HE<)#9FQT0D,@$`9L=$)#0_`+L`````9H-\
-M)#8`="R#[`16#[=$7$!0BXPD>`$```^W`5#H<@(``&:)1%T`@\000P^W1"0V
-M.=A_U&:+50`/MT0D-F:+3$7^NP````"#^`!^:F8Y5%T`?PIFBU1=`&:)7"08
-MB=CWT&8#1"0V#[?XA?]T(&:+1'W^9CM$?0!^"F:+1'T`9HE$??Y##[=$)#8Y
-MV'^_NP````!F@WPD-@!T'`^W1"0VD&8Y3%T`?@IFBTQ=`&:)7"060SG8?^H/
-MO\J#P1F['X7K48G(]^N)T,'X!,'Y'RG(C02`C02`T>!FB40D&F;'1"04``"_
-M``````^_R(G.B<CWZXE$)`B)5"0,BT0D#,'X!,'Y'RG(0(/X`'XZN!^%ZU'W
-M[HG1P?D$B?"9B<@IT(U(`8UV``^W5"04BUPD'(N#=$0``(M<)!AFB1Q09O]$
-M)!1'.?E_W[\`````#[=$)#:)PF:+3"0:9CE,1?X/CN<```!F@WPD%#\/AP@!
-M``!F@T0D&C*)UF:+7"0:9CE<5?Y^1P^_PXG##[]4?0")P2G1B<H/OTQ]`BG(
-M#Z_0A=)^*9!'9HM$)!IF.41U_GX;#[]$?0")VBG"B=`/OU1]`HG9*=$/K\&%
-MP'_8#[=4?#K1X@^WT@^W1'PXT>`/M\`/MTQ]`@^W7'T`#[=T)!I24%%35N@W
-M_/__@\040`^W3"04BUPD'(N3=$0``&;1Z&:)!$J+@W1$``!FBU0D%F8Y%$AV
-M!&:)%$AF_T0D%`^W5"0V9HM,)!IF.4Q5_GX.9H-\)!0_#X8G____ZRUF@WPD
-M%#]W)0^W3"04BUPD'(N3=$0``&:+1$K^9HD$2F;_1"049H-\)!0_=MN+1"0<
-M9L>`\"T`````N`$```"!Q$P!``!;7E]=PXGV55=64X/L'(ML)#B+7"0PBW0D
-M-(U$)!I050^WQE`/M\-0Z$(!``"#Q!"%P'0+#[=$)!KI*0$``)"#[`R-1"0D
-M4(U$)"90#[=%!%#_=0`/M]N)7"0@4^C\____@\04C40D(%"-1"0B4%4/MT0D
-M+E`/M_96Z'4!``"#Q!2-1"0<4(U$)!Y050^W1"0P4%;H6P$``(/$((U$)`Q0
-M50^W1"0:4`^W1"0B4.B]````C40D&E!5#[=$)"Q0#[=$)#)0Z*8```"#Q"`/
-MMT0D"@^W5"0,#[=,)!0/MUPD$E!245-6Z+7Z__^#Q!2)QXU$)`Q050^W1"06
-M4`^W1"0D4.AI````C40D&E!5#[=$)"A0#[=$)#10Z%(```"#Q"`/MT0D"@^W
-M5"0,#[=,)!`/MUPD#E!245-6Z&'Z__^#Q!0/M\`/M]\/MU0D&`^W3"064%-2
-M4?]T)!3H0?K__X/$%`^WP(UV`(/$'%M>7UW#55=64X/L!(ML)""+1"089HE$
-M)`*+?"0<BTT(O@````!F@WT$`'1-D&:+1"0"9CD!=3:-40B[`````&:#>08`
-M=">-=@!F.3IU$V:+5%D>BT0D)&:)$+@!````ZQV#P@)##[=!!CG8?]R#P31&
-M#[=%!#GP?[2X`````(/$!%M>7UW#C78`5U93BT0D&(M\)!"+="04BU`(N0``
-M```/MT`$B<.#^`!^#XGV9CDR=`B#PC1!.<M_\X/L#/]T)"S_="0L#[="!E"-
-M0@A0#[?'4.C\____@\0@6UY?PXUV`%.#[`B+7"00@[MT1````'0;@^P,_[-T
-M1```Z/S____'@W1$````````@\00@[OH+0```'0;@^P,_[/H+0``Z/S____'
-M@^@M````````@\00@\0(6\.-=@"X`0```,.)]KH`````BT0D"&:+`(G!9CL%
-MH&(``'<,N*!B``!"9CL,D';Y#[\$E:)B``##5E.#[!"+="0@BUPD'&BT````
-MZ/S___^)@^@M``"#Q!"%P'4,QP8"````Z84```"0QX-X1```@````(/L#&B`
-M````Z/S___^)@W1$``"#Q!"%P'4(QP8"````ZUC'@Z0J```H;0$`QX.H*@``
-M)%X!`,>#K"H``$!@`0#'@[`J``#T7@$`QX.T*@``?&`!`,>#N"H``!!G`0#'
-M@[PJ``"`;0$`QX/`*@``B&T!`+@!````C78`@\0$6U[#D)!55U93@^P,BWPD
-M((ML)"B+7"0LO@````"-!':+3Q2+%,7@8@``B50D"(M4)"2-!$*+!(7@8@``
-MBU0D"(D$$4/VPS]U$(/L#&H!Z/S___^#Q!"-=@!&@_X/=KZ^`````)"+3Q2+
-M%/5@9```BP3U9&0``(D$$4/VPS]U#H/L#&H!Z/S___^#Q!"01H/^1';2O@``
-M``"0C01VBT\4BQ2%H&8```'HBP2%H&8``(D$$4/VPS]U#8/L#&H!Z/S___^#
-MQ!!&@_X_=LZ#Q`Q;7E]=PXGV55=64X/L#(ML)""+="0DQT0D"`````"_````
-M`&:!/K\2#X?-````#[<&B40D!"V0"```N@4```")TYGW^X72=2.+1"0$C9P`
-MX.[__[AG9F9F]^O!^@*)V,'X'XG3*</K18UV``^W#HV!4/?__[H%````B=.9
-M]_NX`````(72#X4<`@``C9P)H.[__[AG9F9F]^O!^@*)V,'X'XG3*</'1"0(
-M`0```,'C`H'C_P```(/L"&H(4^C\____B<.+512+@@2B``"#Q!!F@3ZT"741
-M@\@0B8($H@``Z7\!``"-=@"+512#X.^)@@2B``#I:P$``(UV`&:+#KL%````
-MN@````")R&;W\V:#^@)U3&:!^3L5=T6#Z0*#[`AJ"`^WR8T,B8V,"8!$__^X
-M'X7K4??IB=#!^`/!^1\IR$!0Z/S___^)PX/$"&H":@#H_/___XG'@\00Z00!
-M``!FBP:Y%````+H`````9O?Q9H72=4=F@3[_$W9`@^P(:@@/MPZ!Z<`2``"X
-M9V9F9O?IB=#!^`/!^1\IR,'@`E#H_/___XG#@\0(:@)J`^C\____B<>#Q!#I
-MJ````&:+!KD*````N@````!F]_%FA=)U/X/L"&H(#[<.@>G`$@``N&=F9F;W
-MZ8G0P?@"P?D?*<C1X%#H_/___XG#@\0(:@)J`NC\____B<>#Q!#K5XUV`&:+
-M!KD%````N@````!F]_&X`````&:%TG5^@^P(:@@/MPZ!Z<`2``"X9V9F9O?I
-MB=#1^,'Y'RG(4.C\____B<.#Q`AJ`FH!Z/S___^)QX/$$(UV`(G9P>$$C02]
-M``````G!BT0D"-'@"<&!R0$0``"+510/ML&)@IR8``#!Z0B+512)R(/@?XF"
-MV)@``(FU-!```+@!````@\0,6UY?7<.+5"0(BT0D!(N`Z"T``(/Z!W<=_R25
-MV&X``(GV@\`$PX/`",.#P`S#!:P```##B?:X`````,.)]E575E.#[!R+1"0X
-M9HE$)!J+5"0PB50D%&;'1"00``!FQT0D#@``9L=$)`P``&;'1"0*``"+NN@M
-M``"!P@PJ``")5"0$O0````"+5"0T#[="`B7P`0``/=`````/A&,!```]T```
-M`'\;/:`````/A!@!```]P`````^$1@$``.EO`0``/5`!``!T'CU0`0``?PP]
-M0`$``'00Z54!```]``@```^%2@$``(M4)#1FBP(MH0\``&8]Z@1W)8M$)!1F
-MBX!0$0``9HE$)!"+5"049HN24A$``&:)5"0.Z9,```"+5"0T9HL"+8P4``!F
-M/>\`=R*+1"049HN`5!$``&:)1"00BU0D%&:+DE81``!FB50D#NM?BU0D-&:+
-M`BU\%0``9CW@`'<BBT0D%&:+@%@1``!FB40D$(M4)!1FBY):$0``9HE4)`[K
-M*XM$)#1F@3A<%G8@BU0D%&:+DEP1``!FB50D$(M$)!1FBX!>$0``9HE$)`Z+
-M5"049HNRVA```&:+@B@1``!FB40D$NMQBU0D%&:+DF@1``!FB50D#(M$)!1F
-MBX!L$0``9HE$)`J+5"049HNRW!```&:+@BH1``!FB40D$NLXBU0D%&:+DFH1
-M``!FB50D"F:)5"0,BT0D%&:+L-X0``!FBY`L$0``9HE4)!+K"K@`````Z?$$
-M``"Z`````+FD:0``BP31B0270G3WN@`````/MTPD&KNH:0``C012C01!BP2#
-MB427!$)T\+H`````#[=,)!J[P&D``(T$4HT$08L$@XE$EPA"=/"Z``````^W
-M3"0:N^!I``"-!%*-!$&+!(.)1)<,0H/Z)W;M@^P,:@!H+@$``&H!#[?&4(U?
-M#%/H_/___X/$%&H`:`X!``!J`HM4)%0/MP)04^C\____@\04:@!H`0$``&H"
-MBU0D5`^W0@)04^C\____@\0@BT0D-/9``D`/A+<```"#[`QJ`VBH````:@&+
-M5"0<BT(<#[]``E!3Z/S___^#Q!1J`VBI````:@&+5"0<BT(<#[]`!%!3Z/S_
-M__^#Q!1J`VBJ````:@&+5"0<BT(<#[]`!E!3Z/S___^#Q!1J`VBN````:@&+
-M5"0<BT(<#[]`"%!3Z/S___^#Q!1J`VBO````:@&+5"0<BT(<#[]`"E!3Z/S_
-M__^#Q!1J`VBP````:@&+5"0<BT(<#[]`#%!3Z/S___^#Q""+1"0T@'@"`'DX
-M@^P,:@!H'P$``&H##[=$)"10C5\,4^C\____@\04:@!H(@$``&H##[=$)")0
-M4^C\____@\0@ZS:#[`QJ`&@7`0``:@,/MT0D*%"-7PQ3Z/S___^#Q!1J`&@:
-M`0``:@,/MT0D)E!3Z/S___^#Q""+5"0P#[>"U`$``"7P````@^@P@_@_=W5F
-M@[K4`0``-70>9H.ZU`$``$5T%&:#NM0!``!&=`IF@[K4`0``-G5-@^P,:@)J
-M6FH":@*-7PQ3Z/S___^#Q!1J`FI<:@)J`E/H_/___X/$%&H":EYJ`FH"4^C\
-M____@\04:@)H_@```&H!:@)3Z/S___^#Q""+1"0P9H.XT@$``$%V9(/L#&H!
-M:!D!``!J`6H!C5\,4^C\____@\04:@-J`6H":@%3Z/S___^#Q!1J`VH#:@)J
-M`5/H_/___X/$%&H#:(L```!J`6H!4^C\____@\04:@-HC````&H!:@%3Z/S_
-M__^#Q""Z``````^W3"0:NZ!M``"0C012C01!BP2#B827K````$*#^@QVZHM4
-M)#3V0@)`=".#[`QJ`&HE:@*+5"0<BT(<#[\`4(V'K````%#H_/___X/$((/L
-M#&H`:@YJ!@^W1"0J4(V'K````%#H_/___X/$((M$)#3V0`-`=0=F@W@"`'E"
-MBU0D-`^W0@(E`$```(/X`1G;@^,'@\,(@^P,:@!J.FH$:@^-MZP```!6Z/S_
-M__^#Q!1J`&I&:@135NC\____@\0@NP````"+1"0PBT@4BQ3=H&D``(L$GXD$
-M$47WQ3\```!U#8/L#&H!Z/S___^#Q!!#=-.[`````(T$6XM4)#"+2A2+%,6H
-M:0``BT2?!(D$$47WQ3\```!U#8/L#&H!Z/S___^#Q!!#=,^[`````(T$6XM4
-M)#"+2A2+%,7`:0``BT2?"(D$$47WQ3\```!U#8/L#&H!Z/S___^#Q!!#=,^[
-M`````)"-!%N+5"0PBTH4BQ3%X&D``(M$GPR)!!%%]\4_````=0^#[`QJ`>C\
-M____@\00B?9#@_LG=LJ[`````)"-!%N+5"0PBTH4BQ3%H&T``(N$GZP```")
-M!!%%]\4_````=1"#[`QJ`>C\____@\00C78`0X/[#';&BT0D%,>`P"T`````
-M``"X`0```(/$'%M>7UW#C78`55=64X'L_`,``(N$)!`$``")1"08#[>`U`$`
-M`"7P````@^@P@_@_=S:+5"089H.ZU`$``#5T'F:#NM0!``!%=!1F@[K4`0``
-M1G0*9H.ZU`$``#9U"L=$)!0"````ZPC'1"04`0```(N,)!P$```/MT$")?`!
-M```]T````'1I/=````!_$#V@````=$$]P````'14ZVP]4`$``'07/5`!``!_
-M"3U``0``=`GK53T`"```=4Z+1"08!=`=``")1"0,BTPD&`^WD=00``#K/HM$
-M)!@%W!T``(E$)`R+3"08#[>1UA```.LDBT0D&`7H'0``B40D#(M,)!@/MY'8
-M$```ZPJY`````.GW!0``BTPD#`^W00:Y`````(7"#X3B!0``BY0D&`0```^_
-M`M'@9HE$)`2+C"04!```#[\!T>!FB40D!F;'1"0HK=YFQT0D*JW>QT0D"```
-M``"^`````(M$)`P/MU`&C5PD*(UV`(G0B?'3^*@!=!B#?"0(`0^'T00``(M$
-M)`AFB31#0(E$)`A&@_X#=MB#[`R-1"0P4(U$)#!0BU0D(`^W0@10_S*+C"0X
-M!```#[<!4.B<!0``QT0D*`````"+;"1`@\0@.VPD)`^']0$``(UV`(U$K0"-
-M1(4`BTPD#(M1"(T$@HE$)!!F@7PD*JW>#X67````#[=T)"B-'+:-')B#[`0/
-MMWL&C30_5HU#"%"-A"3<`@``4.C\____@\0,5H/#$%.-E"2\`@``4NC\____
-M@\0$C4PD/%&+5"0@#[]"`E"-C"3$`@``48V$).@"``!05^B*!0``@\0@A<`/
-MA/,#``"#[`1H@````(U4)#A2BT0D%,'@!XV$!+P!``!0Z/S___^#Q!#I*0$`
-M``^W="0HC1RVBTPD$(T<F8/L!`^W>P:--#]6C4,(4(V$)-P"``!0Z/S___^#
-MQ`Q6@\,04XV4)+P"``!2Z/S___^#Q`2-3"0\48M4)"`/OT("4(V,),0"``!1
-MC80DZ`(``%!7Z.\$``"#Q""%P`^$8@,``(/L!&B`````C50D.%*+1"04P>`'
-MC80$O`$``%#H_/___P^W="0ZC1RVBTPD((T<F8/$#`^W>P:--#]6C4,(4(V$
-M)-P"``!0Z/S___^#Q`Q6@\,04XV4)+P"``!2Z/S___^#Q`2-3"0\48M4)"`/
-MOT("4(V,),0"``!1C80DZ`(``%!7Z%P$``"#Q""%P`^$V0(``(/L!&B`````
-MC50D.%*+1"04P>`'C80$O````%#H_/___X/$$/]$)`A%.VPD)`^&#O[__XM,
-M)""+1"0,BQ!FBQQ*BT0D)&:+/$(IR(E$)`AF@7PD*JW>#X6X````O@````"#
-M[`R+1"04P>`&`?`/OX1$O`$``%`/OX1TP`$``%`/M\=0#[?#4(N4)#@$```/
-MMP)0Z.("``!FB81TD`,``(/$($:#_C]VN8/L"(M,)"#_L71$``"-A"1\`P``
-M4.AG!```B<)FP>@/C00"9M'XBY0D)`0``&:)`F:+A"3^`P``B<)FP>H/`=!F
-MT?AFB40D/HN,)"@$``!FB0&+1"0XBY0D,`0``&:)`F:)0@*#Q!#I.`(``+X`
-M````#[?O#[?[B?:#[`R+7"04P>,&`?,/OX1<O`$``%`/OX1TP`$``%!55XN,
-M)#@$```/MP%0Z"@"``!FB81TD`,``(/$%`^_A%R\````4`^_A'3`````4%57
-MBY0D.`0```^W`E#H^0$``&:)A'00`P``@\0@1H/^/W:0@WPD%`(/A8L```"-
-M1"0>4(M,)!S_L71$``"-A"3X`@``4(V$)'P#``!0Z#4$``")PF;!Z`^-!`)F
-MT?B+E"0D!```9HD"9HM$)"Z)PF;!Z@\!T&;1^&:)1"0^9HN$)/X#``")PF;!
-MZ@\!T&;1^(N,)"@$``!FB0&+1"0XBY0D,`0``&:)`F:+1"0Z9HE"`H/$$.DE
-M`0``9HM,)`9F.8PD;@,```^,J0```(M$)`1F.80D;@,```^,EP```(/L"(M4
-M)"#_LG1$``"-A"3\`@``4.C#`@``B<)FBT0D.HN,)#`$``!FB0%FB4$"B=!F
-MP>@/C00"9M'XBY0D)`0``&:)`F:+A"1^`P``B<)FP>H/`=!FT?AFB40D/HN,
-M)"@$``!FB0&#Q!#ID0```+D`````Z:8```"Y`````.F<````N0````#ID@``
-M`+D`````Z8@```"#[`B+1"0@_[!T1```C80D?`,``%#H+`(``(G"BT0D.(N,
-M)#`$``!FB0%FB4$"B=!FP>@/C00"9M'XBY0D)`0``&:)`F:+A"3^`P``B<)F
-MP>H/`=!FT?AFB40D/HN,)"@$``!FB0&#Q!"X/P```(N4)!@$``!F*P*+3"08
-M9HF!\"T``+D!````B<B!Q/P#``!;7E]=PY!75E.+7"00BW0D%(M,)!B+?"0<
-MBU0D((GX9CGQ="0/M]L/M_:)V"GP#[_2#Z_"#[?)B<HIV@^_WP^OTP'0*?&9
-M]_F86UY?PY!55U93BW0D&(ML)""+?"0DBU0D'`^W7"04#[?*C0Q.#[<&.=AV
-M$L<'`````,=%``````#K4XUV``^W0?XYV'<H#[?"2(D'B44`ZSV)T"GPT?B)
-M!XE%`.LPB=`I\-'XB44`0(D'ZR*)]HGR.<YS&HGV#[<".=ATU`^W0@(YV'?9
-M@\(".<IRZHGV6UY?7<.-=@!55U93@^P,BVPD,(M4)""+1"0L9HE$)`IFQT0D
-M"```9L=$)`8!`+@`````9H/Z`0^&FP```+\`````#[?"2(D$)(UV``^W1"0&
-MBU0D)&8Y/$)S$3L$)'T,9O]$)`AF_T0D!HGV#[=4)`:+7"0H#[\T4P^W1"0(
-M#[\,0XM<)"0/MQ13#[<$0P^WWU914E!3Z)7^__^#Q!1FB41=`&:+5"0*9CG0
-M?!MF@_\_=Q60#[?'9HM<)`IFB5Q%`$=F@_\_=NQ'9H/_/P^&>?___[@!````
-M@\0,6UY?7<-55U93@^P$BWPD&(ML)!P/OT=^#[\7*="#^'Y^#F:+1WZ#Z'YF
-MB40D`NL(9HL'9HE$)`)FBW=^N3\````/OU=^B=!(.<)^%HG"C78`20^_P0^_
-M!$<YT'X%9H7)>>^)RHGSOC\```")]HU"_XG!9H/X/G<=#[_"9CD<1WP4B<J-
-M2O]F@_D^=PD/O\)F.1Q'?>QFA=)U&V:%]G@EB?8/O]9FBT15`F:)1%4`9DYY
-M[^L0D`^_QF:)5$4`@^L"9DYYJ0^_1"0"@\0$6UY?7<-55U93@^P0BW0D)&;'
-M1"0"0``/OT9^BTPD*`^_$2G0@_A^?@YFBVY^@^U^9HEL)`[K#(M$)"AFBP!F
-MB40D#F:+5GYFB50D#+D_````#[]6?@^_1"0,2#G"?A.)PDD/O\$/OP1&.=!^
-M!6:%R7GOBVPD*&:+17Z+5"0P9HD"OS\```"+7"0,C78`BVPD,&8Y70!]#F:%
-MR7499H-\)`)`=1&09L=$)`(``(MT)"BY/P```&:%R7X:#[_!9CD<1GP1B?9)
-M9H7)?@D/O\%F.1Q&??%FA<EU)&:#?"0"`'4<9H7_>#@/O]>+3"0L9HM$40)F
-MB0119D]Y[.LBD`^_[XEL)`1FBT0D`@G(BU0D+&:)!&J#ZP)F3P^);____P^_
-M1"0.@\006UY?7<.)]E.#[`B+7"00@[MT1````'0;@^P,_[-T1```Z/S____'
-M@W1$````````@\00@[OH+0```'0;@^P,_[/H+0``Z/S____'@^@M````````
-M@\00@\0(6\.-=@!55U93BWPD&&:+=P2]`````+D!````B?:-!(F-'(</MU,$
-M#[_&.<)]!HG-9HMS!$&#^0-^XXU$K0"-!(=FBU@09HMP"+D!````C42M`-'@
-MD(T4"&8Y7%<0?0IFBUQ7$&:+=%<(08/Y`W[FC00V9BG#B=B86UY?7<-55U93
-M@^P(BWPD((M4)!R+1"0D9L<````/MT<")4`!```]0`$``'44BT0D'`70'0``
-MBU@(#[=0!.M2B?8/MT<")=`````]P````'0'/=````!U$8V"T!T``(M8(`^W
-M4!SK*HGV#[='`B6@````N0$````]H`````^%NP$``(V"T!T``(M8%`^W4!")
-M]KD`````A=(/CI\!``!FBP]F.PMR$XT$DHT$@F8[3(.L=F9F.PMS+9!FBT,"
-MBU0D)&:)`E/_="0@Z+_^__^+3"0P9HD!N0$```"#Q`CI6P$``(UV`(T$DHT$
-M@HU$@ZQFBU`"BTPD)&:)$5#_="0@Z(G^__^+5"0P9HD"N0$```"#Q`CI)0$`
-M`)"]`````+D`````.=%](F:+!XG&9CL#=AB)R$&)Q3G1?0^-!(F-!(%F.S2#
-M=^N-=@"-!(F-!('!X`*)1"0$#[<T&(U$K0"-1(4`P>`"B00D#[<L&"GNA?8/
-MCH0```"+1"0$#[],&`*+!"0/OU08`BG1#[<'*>@/K\$/K]8!T)GW_F:8BU0D
-M)&:)`HM$)`0!V%#_="0@Z-O]__\/O^@#7"0(4_]T)"CHROW__Y@IQ0^W%P^W
-M`RG"B=</K_U3_W0D,.BP_?__F`^OQHT$!YGW_F:8BTPD0&:)`;D!````@\08
-MZT.-!(F-!(&-%(4`````9HL'N0````!F.P0:=2AFBT0:`HM,)"1FB0&-!!I0
-M_W0D(.A?_?__BU0D,&:)`KD!````@\0(B<B#Q`A;7E]=PXGV55=64X/L"(ML
-M)!R+="0@BWPD),<$)`$```"[`````#G[<SV0C40D!E"-1"0(4(T$WE!5Z(3]
-M__^#Q!"%P'05BT0D!(A$W@9FBT0D!HA$W@?K"8GVQP0D`````$,Y^W+$BP0D
-M@\0(6UY?7<.05E.#[!"+="0@BUPD'&C@````Z/S___^)@^@M``"#Q!"%P'4,
-MQP8"````Z8T```"0QX-X1```@````(/L#&B`````Z/S___^)@W1$``"#Q!"%
-MP'4(QP8"````ZV#'@WA$``!`````QX.D*@``S(,!`,>#J"H``'!N`0#'@ZPJ
-M``#H<0$`QX.P*@``0&\!`,>#M"H``"!R`0#'@[@J```8>0$`QX.\*@``X(8!
-M`,>#P"H```````"X`0```)"#Q`1;7L.0D%575E.#[`R+?"0@BVPD*(MT)"R[
-M`````(T$6XM/%(L4Q0!O``")5"0(BU0D)(T$0HL$A0!O``"+5"0(B0011O?&
-M/P```'4-@^P,:@'H_/___X/$$$.#^P]VOKL`````D(M/%(L4W8!P``"+!-V$
-M<```B0011O?&/P```'4/@^P,:@'H_/___X/$$(GV0X'[B@```';+NP````")
-M]HT$6XM/%(L4A>!T```!Z(L$A>!T``")!!%&]\8_````=0Z#[`QJ`>C\____
-M@\00D$.#^S]VRH/$#%M>7UW#B?955U93@^P,BVPD((MT)"3'1"0(`````+\`
-M````9H$^OQ(/A\T````/MP:)1"0$+9`(``"Z!0```(G3F??[A=)U(XM$)`2-
-MG`#@[O__N&=F9F;WZ\'Z`HG8P?@?B=,IP^M%C78`#[<.C8%0]___N@4```")
-MTYGW^[@`````A=(/A1P"``"-G`F@[O__N&=F9F;WZ\'Z`HG8P?@?B=,IP\=$
-M)`@!````P>,"@>/_````@^P(:@A3Z/S___^)PXM5%(N"!*(``(/$$&:!/K0)
-M=1&#R!")@@2B``#I?P$``(UV`(M5%(/@[XF"!*(``.EK`0``C78`9HL.NP4`
-M``"Z`````(G(9O?S9H/Z`G5,9H'Y.Q5W18/I`H/L"&H(#[?)C0R)C8P)@$3_
-M_[@?A>M1]^F)T,'X`\'Y'RG(0%#H_/___XG#@\0(:@)J`.C\____B<>#Q!#I
-M!`$``&:+!KD4````N@````!F]_%FA=)U1V:!/O\3=D"#[`AJ"`^W#H'IP!(`
-M`+AG9F9F]^F)T,'X`\'Y'RG(P>`"4.C\____B<.#Q`AJ`FH#Z/S___^)QX/$
-M$.FH````9HL&N0H```"Z`````&;W\6:%TG4_@^P(:@@/MPZ!Z<`2``"X9V9F
-M9O?IB=#!^`+!^1\IR-'@4.C\____B<.#Q`AJ`FH"Z/S___^)QX/$$.M7C78`
-M9HL&N04```"Z`````&;W\;@`````9H72=7Z#[`AJ"`^W#H'IP!(``+AG9F9F
-M]^F)T-'XP?D?*<A0Z/S___^)PX/$"&H":@'H_/___XG'@\00C78`B=G!X02-
-M!+T`````"<&+1"0(T>`)P8')`1```(M5%`^VP8F"G)@``,'I"(M5%(G(@^!_
-MB8+8F```B;4T$```N`$```"#Q`Q;7E]=PU575E.#[`R+;"0@BT0D*&:)1"0*
-MB6PD!+\`````B[7H+0``BT0D)`^W0`(E\`$``#W`````=#H]P````'\)/:``
-M``!T"^M+/=````!T(^M"BT0D!&:+@&`1``!FB40D`HM$)`1FBX!B$0``9HD$
-M).LKBT0D!&:+@&01``!FB40D`HM$)`1FBX!F$0``9HD$).L*N`````#IX0$`
-M`+H`````N>1W``"+!-&)!)9"=/>Z``````^W3"0*N^AW``"-!%*-!$&+!(.)
-M1)8$0G3PN@`````/MTPD"KL`>```C012C01!BP2#B426"$)T\+H`````#[=,
-M)`J[('@``(T$4HT$08L$@XE$E@Q"@_H:=NV#[`QJ`&BH````:@,/MT0D&E"-
-M7@Q3Z/S___^#Q!1J`&BE````:@,/MT0D&%!3Z/S___^Z`````(/$(`^W3"0*
-MN\!Z``"-!%*-!$&+!(.)1)9X0H/Z`G;MNP````"+312+%-W@=P``BP2>B001
-M1_?'/P```'4-@^P,:@'H_/___X/$$$-TU[L`````C01;BTT4BQ3%Z'<``(M$
-MG@2)!!%']\<_````=0V#[`QJ`>C\____@\000W33NP````"-!%N+312+%,4`
-M>```BT2>"(D$$4?WQS\```!U#8/L#&H!Z/S___^#Q!!#=-.[`````(GVC01;
-MBTT4BQ3%('@``(M$G@R)!!%']\<_````=0^#[`QJ`>C\____@\00B?9#@_L:
-M=LZ[`````(T$6XM-%(L4Q<!Z``"+1)YXB0011_?'/P```'40@^P,:@'H_/__
-M_X/$$(UV`$.#^P)VS8M$)`3'@,`M````````N`$```"#Q`Q;7E]=PXUV`(M4
-M)`B+1"0$BX#H+0``@_H'=QG_))4(>P``B?:#P`3#@\`(PX/`#,.#P'C#N```
-M``##B?955U93BWPD&(ML)"2+3"0<BW0D%`^WV8T<7P^_U@^W!SG"?13'10``
-M````BT0D(,<``````.MED`^_U@^W0_XYPGPU#[?!2(E%`(M4)"")`NM*B<@I
-M^-'XB44`BU0D((D"ZSF)R"GXT?B+5"0@B0)`B44`ZR>-=@")^3G?<QX/O]:-
-M=@`/MP$YT'3'#[=!`CG"?-"#P0(YV7+JB?9;7E]=PXUV`%575E.#[!B+1"0P
-M9HE$)`Z+3"0T9HE,)`R+7"1`9HE<)`J)Q='E9L=$)`@``+@`````9H/[`0^&
-M!@$``(M$)`QF*T0D#F8[1"0(#X+M````#[=$)`J)1"0$C78`C40D%%"-1"04
-M4`^W1"024/]T)$0/O\50Z./^__^#Q!2#?"04`'4(QT0D%`$```"+5"0$C4+_
-M.T0D$'4(C4+^B40D$)"+3"00BUPD.&:+%$N+1"049CL40W4*BT0D/&:+#$CK
-M2P^_S8M<)!"+1"0X#[\T6(G/*?>+5"04BT0D/`^W!%`/K_B+1"0X#[\44(G0
-M*<B)!"2+1"0\#[<,6(L$)`^OP8T$!RGRB=&9]_F)P0^W1"0(BU0D+,'B!@'"
-MBUPD1&:)#%-F_T0D"(/%`HM$)`QF*T0D#F8[1"0(#X,?____N`$```"#Q!A;
-M7E]=PXGV5U93BUPD$(MT)!2+3"08BWPD'(M4)"")^&8Y\70D#[?;#[?VB=@I
-M\`^_T@^OP@^WR8G**=H/O]\/K],!T"GQF??YF%M>7\.055=64X/L3(M$)&1F
-MB40D+HM4)&QFB50D+(M$)&"+@*`J``")1"0HQT0D'`````"-1"1$4(U$)$10
-MBTPD<`^W011040^_1"0^4.AZ_?__QT0D.`````"#Q!2-=@"X`P```"M$)"2)
-M1"0@BU0D0(T$0(T<Q0````"-!)*-!("-!$*-!$.+="1HC10P9HMZ(&:%_P^$
-M[@$``&:+0AZ+3"0<BW0D>&:)!$Z)S='EC70D.&:+2BQFB4PU`(M4)$2-!)*-
-M!("-!$*-!$,#1"1H9CM(+'X)9HM`+&:)1#4`BVPD'-'E9HM$+#B)PF;!Z@\!
-MT&;1^&:)1"PXC40D,(E$)!2+5"1`#[?WBUPD((T,6\'A`HT$DHT$@(T$0HT$
-M`0'PBU0D:&:+7$(JBT0D%&:)7`4`BU0D1(T$DHT$@(T$0@'!C00QBU0D:&8[
-M7$(J?@YFBT1"*HM,)!1FB40-`(M<)!S1XV:+1!PPB<)FP>H/`=!FT?AFB40<
-M,/]T)"@/M_]7BU0D2(T$DHT$@(T$0HM4)"B--%+!Y@.-!$8#1"1PC5`B4H/`
-M+%`/OT0<0%`/OT0<3%#_="0TZ+3\__^+1"1$!0`"``!05XM4)&B-!)*-!("-
-M!$*-!$8#A"2,````C5`B4H/`+%`/OT0<7%`/OT0<:%#_="10Z'7\__^_````
-M`(/$.&:+1!PP9CM$'#AT=@^W3"0NB4PD$(ML)!S1Y8GVBUPD','C!@'[BW0D
-M*`^_C%X``@``#[\T7HM4)$2+1"1H#[<44(D4)(M$)$"+5"1H#[<$0E%6_W0D
-M"%#_="0@Z%C]__^#Q!2+3"0H9HF$60`$``!'9HM$+#!F*T0L.`^WP#GX=YO_
-M1"0<_T0D)(-\)"0##X;(_?__BU0D.(M$)'!FB1"_`````,=$)"0`````.WPD
-M'`^#[`$``(GVBT0D'$@[1"0D=1F+7"0D9HM$7#"#P`2+="1T9HD$7NLJC78`
-MBU0D)-'B#[]$%#`/OU04.@'0B<+!ZA\!T-'XBU0D)(M,)'1FB011N0````"#
-M?"0D`'0;BUPD)(MT)'0/MTQ>_@^_1%PX*<$/MT0D+"G!BU0D),'B!XM<)"AF
-MBX0:`@0``(G#BW0D*&8KG#(`!```B=AFA=MU!;@!````B<.%R7DWBT0D),'@
-M!XM4)"B-+!`/M].)]HG0#Z_!B?M'O@````!F`X4`!```>`*)QHM$)'QFB318
-M07C=D(M$)"31X`^_5`0PB50D!`^_5`0X*50D!(M<)"2+="1T#[<L7@^W1"0L
-M`<4IU8M$)`2)1"08.>AV!(EL)!@/OT0D&(G#.<A^)8M4)"3!X@:0C00*08MT
-M)"AFBX1&``0``(MT)'QFB01^1SG+?^.+1"0DP>`&`T0D!(M<)"AFBY1#_@,`
-M`(G3BW0D*&8KG$;\`P``B=AFA=MU!;@!````B<,[;"08=E8/O\4YR'Y/BT0D
-M),'@!@-$)`2+5"0HC01"B40D#)")R"M$)!@/M],/K\*+="0,9@.&_@,``(G^
-M1XG"9H/X?WX%NG\```"+1"1\9HD4<$$/O\4YR'_)D/]$)"2+5"0<.50D)`^"
-M%O[__X-\)"0#=QZ-=@"+3"0DBUPD=&:+1$O^9HD$2T&)3"0D@_D#=N6#_W]W
-M$XMT)'QFBT1^_F:)!'Y'@_]_=NV#Q$Q;7E]=PY!55U93@^PLBWPD0(M,)$R)
-M_8NW=$0```^W00(ET````#W`````=`<]T````'4(C9WX)0``ZQ\/MT$"):``
-M``"Z`````#V@````#X4'`0``C9_D(0``BT<4BX!LH@``@^`/9HD$)%;_="14
-MC40D(%"-1"0B4`^W1"004%,/MP%05^B3^O__BT\4BY%8H@``@.8_#[=#'$C!
-MX`XE`,````G"B9%8H@``@\0@9H-\)!8`=!!FBT0D%O?89HF%\"T``.L)9L>%
-M\"T`````NX"B``"Y``````^V%,X/MD3.`L'@"`G"#[9$S@3!X!`)P@^V1,X&
-MP>`8"<*+1Q2)%!B#PP1!@_D?=L^+7Q2+%"2#X@\/MT0D&,'@!"7P`P``"<*-
-M3"08#[=!`L'@"B4`_```"<(/MT$$P>`0)0``/P`)P@^W00;!X!8E``#`#PG"
-MB9-LH@``N@$```")T(/$+%M>7UW#4X/L"(M<)!"#NW1$````=!N#[`S_LW1$
-M``#H_/___\>#=$0```````"#Q!"#N^@M````=!N#[`S_L^@M``#H_/___\>#
-MZ"T```````"#Q!"#NZ`J````=!N#[`S_LZ`J``#H_/___\>#H"H```````"#
-MQ!"#Q`A;PXUV`%.+7"0,N@````"Y`P```)")R"G0C01`C03#9H-X"`!T!P^_
-M0!3K#)!"@_H#=N*X`````%O#C78`4XM<)`RZ`````(GVC0Q29HM$RPAFA<!T
-M#P^WP(T$B`^_1$,2ZPV)]D*#^@-VWK@`````6\.-=@!55U93@^P(BVPD((M4
-M)!R+1"0D9L<````/MT4")=`````]P````'0'/=````!U"8V"^"4``.LAD`^W
-M10(EH````+X`````/:`````/A0L"``"-@N0A``"09HM(%(UX&+X`````9H7)
-M#X3O`0``9HM=`&8['W(:#[?1C022C02`C01"9CM<1YIV=68['W,QB?97_W0D
-M(.@N____BU0D+&:)`E?_="0HZ.7^__^+5"0X9HD"O@$```"#Q!#IG0$```^W
-MP8T<@(T<FXT<6(U<7YI3_W0D(.CO_O__BU0D+&:)`E/_="0HZ*;^__^+5"0X
-M9HD"O@$```"#Q!#I7@$``+L`````N@`````/M\&)QH/X`'XF9HM%`(G!9CL'
-M=AN-=@")T$*)PSG6?@^-!)*-!("-!$)F.PQ'=^B-!)*-!("-!$*-#``/MP0Y
-MB40D!(T$FXT$@(T$0XT<``^W!#LI1"0$@WPD!``/CJ@```"--#E6_W0D(.A0
-M_O__F(E$)`@!^U/_="0HZ#_^__^8*40D$`^W50`/MP,IPHG7#Z]\)!!3_W0D
-M,.@@_O__F`^O1"0<C00'F?=\)!QFF(M4)#QFB0)6_W0D..C'_?__#[_P@\0@
-M4_]T)"#HM_W__Y@IQ@^W50`/MP,IP@^O\E/_="0HZ)[]__^8#Z]$)!2-!`:9
-M]WPD%&:8BU0D.&:)`KX!````@\00ZTF-!)*-!("-!$*-%`!FBT4`O@````!F
-M.P0Z=2Z-'#I3_W0D(.B-_?__BU0D+&:)`E/_="0HZ$3]__^+5"0X9HD"9KX!
-M`(/$$(GVB?"#Q`A;7E]=PXGV55=64X/L"(ML)!R+="0@BWPD),<$)`$```"[
-M`````#G[<SV0C40D!E"-1"0(4(T$WE!5Z&#]__^#Q!"%P'05BT0D!(A$W@9F
-MBT0D!HA$W@?K"8GVQP0D`````$,Y^W+$BP0D@\0(6UY?7<.05E.#[!"+="0@
-MBUPD'&B$````Z/S___^)@^@M``"#Q!"%P'4,QP8"````Z:4```"0QX-X1```
-M``$``(/L#&@``0``Z/S___^)@W1$``"#Q!"%P'4(QP8"````ZWB#[`QH``8`
-M`.C\____B8.@*@``@\00A<!U",<&`@```.M6QX.D*@``T)8!`,>#J"H``!"(
-M`0#'@ZPJ```<C@$`QX.P*@``[(@!`,>#M"H``)2+`0#'@[@J``!PE0$`QX.\
-M*@``))H!`,>#P"H```````"X`0```)"#Q`1;7L.0D%575E.#[`R+?"0@BVPD
-M)(MT)"R[`````(T$6XM/%(L4Q4![``"-1$4`BP2%0'L``(D$$4;WQC\```!U
-M$(/L#&H!Z/S___^#Q!"-=@!#@_L==L:[`````)"+3Q2+%-T@?@``BP3=)'X`
-M`(D$$4;WQC\```!U#X/L#&H!Z/S___^#Q!")]D.#^W]VSKL`````D(T$6XM/
-M%(L4A2""```#1"0HBP2%(((``(D$$4;WQC\```!U$(/L#&H!Z/S___^#Q!"-
-M=@!#@_L_=L:#Q`Q;7E]=PXGV55=64X/L#(ML)""+="0DQT0D"`````"_````
-M`&:!/K\2#X?-````#[<&B40D!"V0"```N@4```")TYGW^X72=2.+1"0$C9P`
-MX.[__[AG9F9F]^O!^@*)V,'X'XG3*</K18UV``^W#HV!4/?__[H%````B=.9
-M]_NX`````(72#X4<`@``C9P)H.[__[AG9F9F]^O!^@*)V,'X'XG3*</'1"0(
-M`0```,'C`H'C_P```(/L"&H(4^C\____B<.+512+@@2B``"#Q!!F@3ZT"741
-M@\@0B8($H@``Z7\!``"-=@"+512#X.^)@@2B``#I:P$``(UV`&:+#KL%````
-MN@````")R&;W\V:#^@)U3&:!^3L5=T6#Z0*#[`AJ"`^WR8T,B8V,"8!$__^X
-M'X7K4??IB=#!^`/!^1\IR$!0Z/S___^)PX/$"&H":@#H_/___XG'@\00Z00!
-M``!FBP:Y%````+H`````9O?Q9H72=4=F@3[_$W9`@^P(:@@/MPZ!Z<`2``"X
-M9V9F9O?IB=#!^`/!^1\IR,'@`E#H_/___XG#@\0(:@)J`>C\____B<>#Q!#I
-MJ````&:+!KD*````N@````!F]_%FA=)U/X/L"&H(#[<.@>G`$@``N&=F9F;W
-MZ8G0P?@"P?D?*<C1X%#H_/___XG#@\0(:@)J`>C\____B<>#Q!#K5XUV`&:+
-M!KD%````N@````!F]_&X`````&:%TG5^@^P(:@@/MPZ!Z<`2``"X9V9F9O?I
-MB=#1^,'Y'RG(4.C\____B<.#Q`AJ`FH!Z/S___^)QX/$$(UV`(G9P>$$C02]
-M``````G!BT0D"-'@"<&!R0$0``"+510/ML&)@IR8``#!Z0B+512)R(/@?XF"
-MV)@``(FU-!```+@!````@\0,6UY?7<-55U93@^P<BVPD,(M$)#AFB40D&HEL
-M)!1FQT0D$@``9L=$)!```&;'1"0.``!FQT0D#```OP````"+M>@M``"+5"0T
-M#[="`B7P`0``/=`````/A"4!```]T````'\;/:`````/A/$````]P`````^$
-M"`$``.DE`0``/4`!``!T"SU0`0``#X43`0``BU0D-&:+`BVA#P``9CWJ!'<E
-MBT0D%&:+@%`1``!FB40D$HM4)!1FBY)2$0``9HE4)!#IY@```(M4)#1FBP(M
-MC!0``&8][P!W)8M$)!1FBX!4$0``9HE$)!*+5"049HN25A$``&:)5"00Z:\`
-M``"+5"0T9HL"+7P5``!F/>``=R*+1"049HN`6!$``&:)1"02BU0D%&:+DEH1
-M``!FB50D$.M[BT0D-&:!.%P6=G"+5"049HN27!$``&:)5"02BT0D%&:+@%X1
-M``!FB40D$.M.BU0D%&:+DF`1``!FB50D#HM$)!1FBX!B$0``9HE$)`SK+(M4
-M)!1FBY)D$0``9HE4)`Z+1"049HN`9A$``&:)1"0,ZPJX`````.E]`@``N@``
-M``"Y)(4``(L$T8D$ED)T][H`````#[=,)!J[*(4``(T$4HT$08L$@XE$E@1"
-M=/"Z``````^W3"0:NT"%``"-!%*-!$&+!(.)1)8(0G3PN@`````/MTPD&KM@
-MA0``C012C01!BP2#B426#$*#^B1V[8M4)#2`>@(`#XF-````@^P,:@!H\0``
-M`&H##[=$)"90C5X,4^C\____@\04:@!H[@```&H##[=$)"104^C\____@\04
-M:@)H(P$``&H!:@%3Z/S___^#Q""#O<P!```)=!.#O<P!```*=6=F@[W0`0``
-M`W==@^P,:@-H@P```&H#:@-J!NC\____@\0(4(U&#%#H_/___X/$(.LV@^P,
-M:@!H]P```&H##[=$)"I0C5X,4^C\____@\04:@!H]````&H##[=$)"A04^C\
-M____@\0@N@`````/MTPD&KO@B```C012C01!BP2#B826H````$*#^@)VZKL`
-M````BTT4BQ3=((4``(L$GHD$$4?WQS\```!U#8/L#&H!Z/S___^#Q!!#=->[
-M`````(T$6XM-%(L4Q2B%``"+1)X$B0011_?'/P```'4-@^P,:@'H_/___X/$
-M$$-TT[L`````C01;BTT4BQ3%0(4``(M$G@B)!!%']\<_````=0V#[`QJ`>C\
-M____@\000W33NP````"-!%N+312+%,5@A0``BT2>#(D$$4?WQS\```!U#X/L
-M#&H!Z/S___^#Q!")]D.#^R1VSKL`````C01;BTT4BQ3%X(@``(N$GJ````")
-M!!%']\<_````=0V#[`QJ`>C\____@\000X/[`G;-BT0D%,>`P"T```````"X
-M`0```(/$'%M>7UW#C78`BU0D"(M$)`2+@.@M``"#^@=W'?\DE2B)``")]H/`
-M!,.#P`C#@\`,PP6@````PXGVN`````##B?955U93BWPD&(ML)"2+3"0<BW0D
-M%`^WV8T<7P^_U@^W!SG"?13'10``````BT0D(,<``````.MED`^_U@^W0_XY
-MPGPU#[?!2(E%`(M4)"")`NM*B<@I^-'XB44`BU0D((D"ZSF)R"GXT?B+5"0@
-MB0)`B44`ZR>-=@")^3G?<QX/O]:-=@`/MP$YT'3'#[=!`CG"?-"#P0(YV7+J
-MB?9;7E]=PXUV`%575E.#[!B+1"0P9HE$)`Z+3"0T9HE,)`R+7"1`9HE<)`J)
-MQ='E9L=$)`@``+@`````9H/[`0^&!@$``(M$)`QF*T0D#F8[1"0(#X+M````
-M#[=$)`J)1"0$C78`C40D%%"-1"044`^W1"024/]T)$0/O\50Z./^__^#Q!2#
-M?"04`'4(QT0D%`$```"+5"0$C4+_.T0D$'4(C4+^B40D$)"+3"00BUPD.&:+
-M%$N+1"049CL40W4*BT0D/&:+#$CK2P^_S8M<)!"+1"0X#[\T6(G/*?>+5"04
-MBT0D/`^W!%`/K_B+1"0X#[\44(G0*<B)!"2+1"0\#[<,6(L$)`^OP8T$!RGR
-MB=&9]_F)P0^W1"0(BU0D+,'B!@'"BUPD1&:)#%-F_T0D"(/%`HM$)`QF*T0D
-M#F8[1"0(#X,?____N`$```"#Q!A;7E]=PXGV5U93BUPD$(MT)!2+3"08BWPD
-M'(M4)"")^&8Y\70D#[?;#[?VB=@I\`^_T@^OP@^WR8G**=H/O]\/K],!T"GQ
-MF??YF%M>7\.055=64X/L3(M$)&1FB40D+HM4)&QFB50D+(M$)&"+@*`J``")
-M1"0HQT0D'`````"-1"1$4(U$)$10BTPD<`^W011040^_1"0^4.AZ_?__QT0D
-M.`````"#Q!2-=@"X`P```"M$)"2)1"0@BU0D0(T$0(T<Q0````"-!)*-!("-
-M!$*-!$.+="1HC10P9HMZ(&:%_P^$[@$``&:+0AZ+3"0<BW0D>&:)!$Z)S='E
-MC70D.&:+2BQFB4PU`(M4)$2-!)*-!("-!$*-!$,#1"1H9CM(+'X)9HM`+&:)
-M1#4`BVPD'-'E9HM$+#B)PF;!Z@\!T&;1^&:)1"PXC40D,(E$)!2+5"1`#[?W
-MBUPD((T,6\'A`HT$DHT$@(T$0HT$`0'PBU0D:&:+7$(JBT0D%&:)7`4`BU0D
-M1(T$DHT$@(T$0@'!C00QBU0D:&8[7$(J?@YFBT1"*HM,)!1FB40-`(M<)!S1
-MXV:+1!PPB<)FP>H/`=!FT?AFB40<,/]T)"@/M_]7BU0D2(T$DHT$@(T$0HM4
-M)"B--%+!Y@.-!$8#1"1PC5`B4H/`+%`/OT0<0%`/OT0<3%#_="0TZ+3\__^+
-M1"1$!0`"``!05XM4)&B-!)*-!("-!$*-!$8#A"2,````C5`B4H/`+%`/OT0<
-M7%`/OT0<:%#_="10Z'7\__^_`````(/$.&:+1!PP9CM$'#AT=@^W3"0NB4PD
-M$(ML)!S1Y8GVBUPD','C!@'[BW0D*`^_C%X``@``#[\T7HM4)$2+1"1H#[<4
-M4(D4)(M$)$"+5"1H#[<$0E%6_W0D"%#_="0@Z%C]__^#Q!2+3"0H9HF$60`$
-M``!'9HM$+#!F*T0L.`^WP#GX=YO_1"0<_T0D)(-\)"0##X;(_?__BU0D.(M$
-M)'!FB1"_`````,=$)"0`````.WPD'`^#[`$``(GVBT0D'$@[1"0D=1F+7"0D
-M9HM$7#"#P`2+="1T9HD$7NLJC78`BU0D)-'B#[]$%#`/OU04.@'0B<+!ZA\!
-MT-'XBU0D)(M,)'1FB011N0````"#?"0D`'0;BUPD)(MT)'0/MTQ>_@^_1%PX
-M*<$/MT0D+"G!BU0D),'B!XM<)"AFBX0:`@0``(G#BW0D*&8KG#(`!```B=AF
-MA=MU!;@!````B<.%R7DWBT0D),'@!XM4)"B-+!`/M].)]HG0#Z_!B?M'O@``
-M``!F`X4`!```>`*)QHM$)'QFB31807C=D(M$)"31X`^_5`0PB50D!`^_5`0X
-M*50D!(M<)"2+="1T#[<L7@^W1"0L`<4IU8M$)`2)1"08.>AV!(EL)!@/OT0D
-M&(G#.<A^)8M4)"3!X@:0C00*08MT)"AFBX1&``0``(MT)'QFB01^1SG+?^.+
-M1"0DP>`&`T0D!(M<)"AFBY1#_@,``(G3BW0D*&8KG$;\`P``B=AFA=MU!;@!
-M````B<,[;"08=E8/O\4YR'Y/BT0D),'@!@-$)`2+5"0HC01"B40D#)")R"M$
-M)!@/M],/K\*+="0,9@.&_@,``(G^1XG"9H/X?WX%NG\```"+1"1\9HD4<$$/
-MO\4YR'_)D/]$)"2+5"0<.50D)`^"%O[__X-\)"0#=QZ-=@"+3"0DBUPD=&:+
-M1$O^9HD$2T&)3"0D@_D#=N6#_W]W$XMT)'QFBT1^_F:)!'Y'@_]_=NV#Q$Q;
-M7E]=PY!55U93@^PLBWPD0(M4)$R)_8NW=$0```^W0@(ET````#W`````=`<]
-MT````'4(C9WX)0``ZQP/MT("):````"-G^0A```]H````'0&C9_0'0``BT<4
-MBX!LH@``@^`/9HD$)%;_="14C40D(%"-1"0B4`^W1"004%,/MP)05^B6^O__
-MBT\4BY%8H@``@.8_#[=#'$C!X`XE`,````G"B9%8H@``@\0@9H-\)!8`=!!F
-MBT0D%O?89HF%\"T``.L)9L>%\"T`````NX"B``"Y`````(UV``^V%,X/MD3.
-M`L'@"`G"#[9$S@3!X!`)P@^V1,X&P>`8"<*+1Q2)%!B#PP1!@_D?=L^+7Q2+
-M%"2#X@\/MT0D&,'@!"7P`P``"<*-3"08#[=!`L'@"B4`_```"<(/MT$$P>`0
-M)0``/P`)P@^W00;!X!8E``#`#PG"B9-LH@``N`$```"#Q"Q;7E]=PXGV4X/L
-M"(M<)!"#NW1$````=!N#[`S_LW1$``#H_/___\>#=$0```````"#Q!"#N^@M
-M````=!N#[`S_L^@M``#H_/___\>#Z"T```````"#Q!"#NZ`J````=!N#[`S_
-MLZ`J``#H_/___\>#H"H```````"#Q!"#Q`A;PXUV`%.+7"0,N@````"Y`P``
-M`)")R"G0C01`C03#9H-X"`!T!P^_0!3K#)!"@_H#=N*X`````%O#C78`4XM<
-M)`RZ`````(GVC0Q29HM$RPAFA<!T#P^WP(T$B`^_1$,2ZPV)]D*#^@-VWK@`
-M````6\.-=@!55U93@^P$BU0D&(M$)"!FQP```(M,)!P/MT$")=`````]P```
-M`'0'/=````!U"8V"^"4``.LCD(M,)!P/MT$"):`````]H````'4(C8+D(0``
-MZP:-@M`=``!FBT@4C7@8N@````!FA<D/A.T!``"+1"0<9HL89CL?<AD/M]&-
-M!)*-!("-!$)F.UQ'FG9V9CL?<S&05_]T)!SH*O___XM,)"AFB0%7_W0D).CA
-M_O__BU0D-&:)`KH!````@\00Z9D!``"0#[?!C1R`C1R;C1Q8C5Q?FE/_="0<
-MZ.K^__^+3"0H9HD!4_]T)"3HH?[__XM4)#1FB0*Z`0```(/$$.E9`0``D+L`
-M````N@`````/M\&)QH/X`'XHBTPD'&:+`8G!9CL'=AJ)]HG00HG#.=9^#XT$
-MDHT$@(T$0F8[#$=WZ(T$DHT$@(T$0HT,``^W+#F-!)N-!("-!$.-'``/MP0[
-M*<6%[0^.I0````'YB0PD4?]T)!SH3_[__P^_\`'[4_]T)"3H0/[__Y@IQHM$
-M)"P/MQ`/MP,IPHG7#Z_^4_]T)"SH(O[__Y@/K\6-!`>9]_UFF(M4)#AFB0+_
-M="08_W0D-.C*_?__#[_P@\0@4_]T)!SHNOW__Y@IQHM,)"0/MQ$/MP,IP@^O
-M\E/_="0DZ)[]__^8#Z_%C00&F??]9IB+5"0T9HD"N@$```"#Q!#K38T$DHT$
-M@(T$0HT,`(M4)!QFBP*Z`````&8[!#EU+XT<.5/_="0<Z([]__^+3"0H9HD!
-M4_]T)"3H1?W__XM4)#1FB0*Z`0```(/$$(GVB="#Q`1;7E]=PXGV55=64X/L
-M"(ML)!R+="0@BWPD),<$)`$```"[`````#G[<SV0C40D!E"-1"0(4(T$WE!5
-MZ&#]__^#Q!"%P'05BT0D!(A$W@9FBT0D!HA$W@?K"8GVQP0D`````$,Y^W+$
-MBP0D@\0(6UY?7<.05E.#[!"+="0@BUPD'&BL````Z/S___^)@^@M``"#Q!"%
-MP'4,QP8"````Z:4```"0QX-X1`````$``(/L#&@``0``Z/S___^)@W1$``"#
-MQ!"%P'4(QP8"````ZWB#[`QH``8``.C\____B8.@*@``@\00A<!U",<&`@``
-M`.M6QX.D*@``T*L!`,>#J"H``&R;`0#'@ZPJ```8HP$`QX.P*@``0)P!`,>#
-MM"H``.B>`0#'@[@J``!PJ@$`QX.\*@``)*\!`,>#P"H```````"X`0```)"#
-MQ`1;7L.0D"A0%BQ8*```F`@``*L(``"K"```M0@``+\(``#8"```X@@``/((
-M``"]"@```@D``!<)``!L"0``+0D``$()``!7"0``?@D``+T*``"]"@``X`D`
-M`/8)```,"@``%@H``,X(```J"@``0`H``%,*``"]"@``O0H``)P*``"]"@``
-MHPH``+T*``"]"@``O0H``+$*``"@_Z/_GO^@_Z/_H/\```4`"@`4`!X`,@!&
-M`%4`6@!?`&0````*`!0`'@`H`#(`/`!&`%``6@!D`,(```#$````Q0```-``
-M``#:````Y````,(```##````U````/(````-`0``*`$``,\```#*`````@!0
-M(0$`0`$$`*``"`#``"``T`!``%`!`````"0!F!D`)A`&````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M`````````````````````````````````````+Q8````````````````````
-M`````````````````````````.!8````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````````````````#_
-M______\```````````````````"8``!'````")@````````,F```IHZ$"1"8
-M````X#(]%)@``&L'```<F````````""8`````@("))@```X.```HF````0("
-M"BR8``#\;P,`,)@````````TF```#@X``#B8```'````/)@````!`@!`F```
-M``!CB428``"<%G(32)@``#.V&`!,F```/&&$$E"8``#@N.@-5)@``%E(!P!8
-MF```NKZ`?ER8``!>9CHQ8)@```@=``!DF````,X!`&B8``"009I`<)@```\`
-M``!TF```@````'B8```$`````)D````````$F0````````B9````````#)D`
-M````@``0F0```P````";````````!)L``"`````(FP``$`````R;```P````
-M$)L```@````4FP``*````!B;```H````')L```0````@FP``)````"2;```4
-M````*)L``#0````LFP``#````#";```L````-)L```(````XFP``(@```#R;
-M```2````0)L``#(```!$FP``"@```$B;```J````3)L```$```!0FP``(0``
-M`%2;```1````6)L``#$```!<FP``"0```&";```I````9)L```4```!HFP``
-M)0```&R;```5````<)L``#4```!TFP``#0```'B;```M````?)L```,```"`
-MFP``(P```(2;```3````B)L``#,```",FP``"P```)";```K````E)L```<`
-M``"8FP``)P```)R;```7````H)L``#<```"DFP``#P```*B;```O````K)L`
-M`"\```"PFP``+P```+2;```O````N)L``"\```"\FP``+P```,";```O````
-MQ)L``"\```#(FP``+P```,R;```O````T)L``"\```#4FP``+P```-B;```O
-M````W)L``"\```#@FP``+P```.2;```O````Z)L``"\```#LFP``+P```/";
-M```O````])L``"\```#XFP``+P```/R;```O`````)H``!T````$F@``70``
-M``B:``"=````#)H``-T````0F@``'0$``!2:```A````&)H``&$````<F@``
-MH0```"":``#A````))H``#$````HF@``<0```"R:``"Q````,)H``!P````T
-MF@``7````#B:```I````/)H``&D```!`F@``J0```$2:```@````2)H``!D`
-M``!,F@``60```%":``"9````5)H``#````!8F@``!0```%R:```E````8)H`
-M`&4```!DF@``I0```&B:```H````;)H``&@```!PF@``'P```'2:```>````
-M>)H``!@```!\F@``6````(":``"8````A)H```,```"(F@``!````(R:``!$
-M````D)H``(0```"4F@``$P```)B:```2````G)H``%(```"@F@``D@```*2:
-M``#2````J)H``"L```"LF@``*@```+":``!J````M)H``*H```"XF@``&P``
-M`+R:```:````P)H``%H```#$F@``F@```,B:``#:````S)H```8```#0F@``
-M!@```-2:```&````V)H```8```#<F@``!@```.":```&````Y)H```8```#H
-MF@``!@```.R:```&````\)H```8```#TF@``!@```/B:```&````_)H```8`
-M``#4F```(````,R8```$````R)@```8!!@"<F```;0```,"8````````T)@`
-M`!0````)"0```````@(&!@8&!@8"`@````,`!@`)`#P`````````````````
-M``````````````````````````````#P````S`````````````````````KB
-M````(```"@(```$8```!````0!@$````````````````````````````````
-M````````!017&0`F$`8`````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````@(P`````````````````````````````````````````````
-MT(P`````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M`````````````````````````````````&P)CPFT"0``````````````````
-M________````````````````````````````````````````(````"````!`
-M````0```````!@````8````&`#`````5````%0```!T````5````0!````_\
-M+P`/_"\`'_PO``_\+P!$$```#_PO``_\+P`?_"\`#_PO`$@0```/_"\`#_PO
-M`!_\+P`/_"\`3!````_\+P`/_"\`'_PO``_\+P!0$```#_PO``_\+P`?_"\`
-M#_PO`%00```/_"\`#_PO`!_\+P`/_"\`6!````_\+P`/_"\`'_PO``_\+P!<
-M$```#_PO``_\+P`?_"\`#_PO`&`0```/_"\`#_PO`!_\+P`/_"\`9!````_\
-M+P`/_"\`'_PO``_\+P!P$```:`$``.`!``"X`0``:`$``#`0```P`@``X`$`
-M`+`````P`@``L!```)@-``"`$0``2!\``)@-``#P$```X*```&A``0"`6```
-MX*```!2`````!``$``@`"``P`"``!``$'(```*>/C0[/CXT.E8]@`:>/C0X$
-MF`````````,``````````````""8`````@("``("`@`"`0(``@("))@```X.
-M```.#@``!P<```X.```HF````0`""@$``@H```$%`0`""C28```.#@``#@X`
-M``X.```.#@``.)@```<````'````"P````L```!$F```G!9R$Z46<A.H%G(3
-MG!9R$TB8``!GNA@`9[H8`&FZ&`!INA@`4)@``."T*`S@M"@,X+0H#."T*`Q8
-MF```+@V`?BX-@'XN#<!^+@V`?ER8``!>73<Q7ETW,5Y=.C%>73<Q8)@``!"]
-M```0O0``.+T``!"]``!DF````,X!``#.`0``S@$``,X!`!29```0)P``$"<`
-M`'P5```0)P``&)D``)`!``"0`0``A````)`!``!$F0``(!#@;R`0X&\@">!O
-M(!#@;X"A``#_%/\%_Q3_!?\4_P7_&?\%U)@``!`````4````$````!``````
-M````#``````````H````G)R$A"P```!\?'Q\-`````4```!``````````$0`
-M```(````2`````@```!,````$````%``````````5````!\`````"```````
-M``0(````````"`@````````,"````````!`(````````%`@````````8"```
-M`````!P(````````(`@````````D"````````#`2````````!(`````````(
-M@`````````R`````````&(`````````D@````````"B````P````+(```/__
-M!P`P@```____`32````Q````.(`````````\@````````$"`````````1(``
-M``(```!(@````````%2`````````6(`````````(F`````````R8``"3D(0M
-M$)@```#@,GT4F```:P\``!R8````````+)@``/YO`@`PF````````#R8````
-M`0(`0)@``'H!:B!,F```/&&$$E28``!9"```:)@``)!!FD!LF```@;`,!7"8
-M```/````=)@``(````!XF```#`````"9````````!)D````````(F0``````
-M``R9`````(``$)D```$````<F0``*@D``""9````````))D```6*!0`HF0``
-M`0```"R9````````,)D````````TF0```````#B9````````/)D``#\```!`
-MF0``!````$B9````````3)D```````!0F0```````%29``!,\5!=6)D``!@`
-M``!<F0``CFI+`(2A``#_!?\&B*$``/\'_P>,H0``_PC_")"A``#_"?\)E*$`
-M`/\*_PJ8H0``_PO_"YRA``#_#/\,H*$``/\-_PVDH0``_P[_#ZBA``#_$O\2
-MK*$``/\3_Q2PH0``_Q7_%K2A``#_%_\9N*$``/\:_QN\H0``_QW_'L"A``#_
-M(/\CQ*$``/\E_R?(H0``_RG_+,RA``#_+_\QT*$``/\T_S?4H0``_SK_.MBA
-M``#_.O\ZW*$``/\Z_SK@H0``_SK_.N2A``#_.O\ZZ*$``/\Z_SKLH0``_SK_
-M.O"A``#_.O\Z]*$``/\Z_SKXH0``_SK_.ORA``#_.O\Z`)L````````$FP``
-M(`````B;```0````#)L``#`````0FP``"````!2;```H````&)L```0````<
-MFP``)````"";```4````))L``#0````HFP``#````"R;```L````,)L```(`
-M```TFP``(@```#B;```2````/)L``#(```!`FP``"@```$2;```J````2)L`
-M``8```!,FP``)@```%";```6````5)L``#8```!8FP``#@```%R;```N````
-M8)L```$```!DFP``(0```&B;```1````;)L``#$```!PFP``"0```'2;```I
-M````>)L```4```!\FP``)0```(";```5````A)L``#4```"(FP``#0```(R;
-M```M````D)L```,```"4FP``(P```)B;```3````G)L``#,```"@FP``"P``
-M`*2;```K````J)L``"L```"LFP``*P```+";```K````M)L``"L```"XFP``
-M*P```+R;```K````P)L``"L```#$FP``*P```,B;```K````S)L``"L```#0
-MFP``*P```-2;```K````V)L``"L```#<FP``*P```.";```K````Y)L``"L`
-M``#HFP``*P```.R;```K````\)L``"L```#TFP``*P```/B;```"````_)L`
-M`!8```#4F```(````-B8``!H$&``````````````F@``J0$````````$F@``
-MZ0$``$`````(F@``*0```(`````,F@``:0```%`!```0F@``F0$``)`!```4
-MF@``V0$``-`!```8F@``&0```!`````<F@``60```$0````@F@``F0```(0`
-M```DF@``I0$``$@!```HF@``Y0$``(@!```LF@``)0```,@!```PF@``R`$`
-M`!0````TF@``"````$(````XF@``2````((````\F@``B````'@!``!`F@``
-MF`$``+@!``!$F@``V`$``/@!``!(F@``&````!(```!,F@``6````%(```!0
-MF@``F````)(```!4F@``I`$``'P!``!8F@``Y`$``+P!``!<F@``)````/P!
-M``!@F@``9`````H```!DF@``I````$H```!HF@``Y````(H```!LF@``"@$`
-M`%H!``!PF@``2@$``)H!``!TF@``B@$``-H!``!XF@``R@$```X```!\F@``
-M"@```$X```"`F@``2@```(X```"$F@``B@```%X!``"(F@``N@$``)X!``",
-MF@``^@$``-X!``"0F@``.@````D```"4F@``>@```$D```"8F@``A@$``(D`
-M``"<F@``Q@$``'D!``"@F@``!@```+D!``"DF@``1@```/D!``"HF@``A@``
-M`#D```"LF@``Q@```'D```"PF@``Q@```+D```"TF@``Q@```+T!``"XF@``
-MQ@```/T!``"\F@``Q@```#T```#`F@``Q@```'T```#$F@``Q@```+T```#(
-MF@``Q@```/T```#,F@``Q@```/T```#0F@``Q@```/T```#4F@``Q@```/T`
-M``#8F@``Q@```/T```#<F@``Q@```/T```#@F@``Q@```/T```#DF@``Q@``
-M`/T```#HF@``Q@```/T```#LF@``Q@```/T```#PF@``Q@```/T```#TF@``
-MQ@```/T```#XF@``Q@```/T```#\F@``Q@```/T````!````1@```&`````!
-M````1@```&$````!````1@```&(````!````1@```&,````!````1@```&0`
-M```!````1@```&4````!````1@```&8````!````1@```&<````!````1@``
-M`&@````!````1@```&D````!````1@```&H````!````1@```&L````!````
-M1@```&P````!````1@```'0````!````1@```'0````!````1@```'0````!
-M````1@```'0````!````1@```'0````!````1@```'0````!````1@```'0`
-M```!````1@```'0````!````1@```'4````!````1@```'8````!````1@``
-M`'<````!````1@```'@````!````1@```'D````!````1@```'H````!````
-M1@```'L````!````1@```'P````!````1@```'T````!````1@```'X````!
-M````1@```'\````!````1@```(`````!````1````'P````!````1@```(@`
-M```!````1@```(P````!````1@```)`````!````1@```)0````!````1@``
-M`)@````!````1@```)P````!````1@```*`````!````1@```*0````!````
-M1@```*@````!````1@```*P````!````1@```+`````!````1@```+0`````
-M`@<```````````````````````````">%@L`8A8*`#H6"0`<%@@`ZA4'`)H5
-M!0!*%00``Q4"`%D4``````$````#``8`"0`_````@[\``(._``"MOP``K;\`
-M`->_``#7OP```<````'````````````````````)````!`````0``0`!``$`
-M!@```$9'.``````````````````$`````0`!``0```!&1S<`````````````
-M`````P`!``$``0`#````1D<V``````````````````0```````$``0```$9'
-M-0`````````````````$``$``0````````!&1S0`````````````````!```
-M``$```#^____1D<S``````````````````,``0`!````_?___T9',@``````
-M```````````$`````````/S___]&1S$``````````````````@`!``$```#Z
-M____1D<P````````````````````````````````````````````````````
-M```4$%09`"80!@``````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M`````'S4````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````;`F/";0)"`EL";0)R?___\G____)____
-MR?___\+____R____\O____+____R____]/___\#____`____P/___\#___^Z
-M____LO___[+___^R____LO___[#___________\%`@\'`@\*``\)``\```;L
-M``"TZP``P>L``$3L``#:ZP``..P````````````````````````@````(```
-M`$````!````````&````!@````8`GA8+`&(6"@`Z%@D`'!8(`.H5!P":%04`
-M2A4$``,5`@!9%```N`L!``````"\_0``&_L``&#[``"$^P``O/T``.S[``"\
-M_0``O/T``+S]``"\_0``O/T``![\``"\_0``O/T``+S]``"\_0``,/P``%W\
-M``"\_0``K/P``-?\``"\_0``O/L``+S]``"\_0``O/T``!3]```I_0``O/T`
-M`$/]``"S_0``L_T``(W]``"5_0``G?T``*7]``"M_0````````8````!````
-M`@````,````$````!0```'C_``!X_P``^_T``!_^``!X_P``6_X``'C_``!X
-M_P``>/\``'C_``!X_P``@_X``'C_``!X_P``>/\``'C_``"<_@``>/\``'C_
-M``"T_@``5_\``'C_``!X_P``>/\``'C_``!X_P``V/X``-C^``!X_P``-_\`
-M`````````````````$`0```/_"\`#_PO`!_\+P`/_"\`#_PO`$00```/_"\`
-M#_PO`!_\+P`/_"\`#_PO`$@0```/_"\`#_PO`!_\+P`/_"\`#_PO`$P0```/
-M_"\`#_PO`!_\+P`/_"\`#_PO`%`0```/_"\`#_PO`!_\+P`/_"\`#_PO`%00
-M```/_"\`#_PO`!_\+P`/_"\`#_PO`%@0```/_"\`#_PO`!_\+P`/_"\`#_PO
-M`%P0```/_"\`#_PO`!_\+P`/_"\`#_PO`&`0```/_"\`#_PO`!_\+P`/_"\`
-M#_PO`&00```/_"\`#_PO`!_\+P`/_"\`#_PO`#`0```P`@``X`$``+````!@
-M`0``X`$``'`0``!H`0``X`$``+@!``",`0``X`$``+`0``!@#@``@!$``!P?
-M```X/@``@!$``/`0``#@H```:$`!`(!8``#@L```:$`!`!2```#H`^@#X`;@
-M!B`$(`1`"$`(X`;@!@28`````````P```````````````P```""8`````@("
-M``("`@`"`0(``@("``("`B28```.#@``#@X```<'```.#@``#@X``$28```<
-M%G(3)1QR$R(7<A.B%G(3)1QR$V"8```0G0``$)T``!B=```8G0``$)T``&28
-M````S@$``,X!``#.`0``S@$``,X!`&B8``"009I`D$&:0)!!FD"009I`D$&:
-M0!B9``"X`0``N`$``(0````(`0``N`$``"29```%B@40!8H%$`6*!1`%B@40
-M!8H%$#"B```````````````````(`0``````````````````#``````````T
-M````!0```$``````````1`````@```!(````"````$P````0````4```````
-M``!4````'P`````(````````!`@````````("`````````P(````````$`@`
-M```````4"````````!@(````````'`@````````@"````````"0(````````
-M<!(````````X$````````'@0````````N!````````#X$````````#@1````
-M````>!$```````"X$0```````/@1````````.!(```````!X$@```````+@2
-M````````^!(````````X$P```````'@3````````N!,```````#X$P``````
-M`#@4````````>!0```````"X%````````/@4````````.!4```````!X%0``
-M`````+@5````````^!4````````X%@```````'@6````````N!8```````#X
-M%@```````#@7````````>!<```````"X%P```````/@7````````/!``````
-M``!\$````````+P0````````_!`````````\$0```````'P1````````O!$`
-M``````#\$0```````#P2````````?!(```````"\$@```````/P2````````
-M/!,```````!\$P```````+P3````````_!,````````\%````````'P4````
-M````!(`````````(@`````````R`````````((`````````D@````````"B`
-M```P````+(```/__!P`P@```____`32````Q````.(`````````\@```````
-M`$B`````````5(````````!8@````````%R```"/QP\`P(```!HP@BK$@```
-MX`'<!<B````0)T`?S(``````]`'0@```'!X``-2```"JJ@(`V(```%55``+<
-M@````````."```#_____Y(```/__``#H@````````.R`````````\(``````
-M``#T@````````/B`````````_(```(@`````AP````````2'``",````"(<`
-M`.0````,AP``U0(``!"'````````%(<````````8AP``H````!R'``#)`0``
-M((<``"P````DAP``+````"B'```P````+(<``#P````PAP``+````#2'```L
-M````.(<``#`````\AP``/````$"'````````1(<```````!(AP```````$R'
-M````````4(<```````!4AP```````%B'````````7(<```````!@AP``U0``
-M`&2'``#?````:(<```(!``!LAP``.@$``'"'``!U````=(<``'\```!XAP``
-MH@```'R'`````````($```(``0`$@0```0````B!``#`````#($````````0
-M@0``:`$``!2!````````P(<````!`@/$AP``!`4&!\B'```("0H+S(<```P-
-M#@_0AP``$!$2$]2'```4%187V(<``!@9&AO<AP``'!T>'^"'`````0(#Y(<`
-M``0%!@?HAP``"`D*"^R'```,#0X/\(<``!`1$A/TAP``%!46%_B'```8&1H;
-M_(<``!P='A\,F```&8Z$K1"8````X"A]%)@``&N?"IP<F````````$"8``!Z
-M`6H@5)@``%D(````F0````````29````````")D````````,F0````"``!"9
-M```!````')D``(`,```@F0`````0!2B9```!````+)D```0````TF0``(B`?
-M'CB9```-#`L*/)D``#\```!(F0``$K*`DE29``"(X5!=7)D``(YJ2P!HF0``
-MS@,``'"9```5M2\9>)D```$```!\F0```````!"B```S8X``%*(``!!L$``8
-MH@``8$"<`""B``#&,(@!)*(````$```LH@```````#2B```@("`@.*(``"`@
-M("!`H@``(`I).$2B``"V>P``2*(``/P__P\`FP```````"B;```,````.)L`
-M`!(```!DFP``(0```(R;```M````G)L``#,```````,`!@`)`#\````#``8`
-M"0`_``````````````````D````$````!``!``$``0````````````8```!&
-M1S@`````````````````!`````$``0````````````0```!&1S<`````````
-M`````````P`!``$``0````````````,```!&1S8`````````````````!```
-M`````0````````````$```!&1S4`````````````````!``!``$`````````
-M``````````!&1S0`````````````````!`````$``````````````/[___]&
-M1S,``````````````````P`!``$``````````````/W___]&1S(`````````
-M````````!````````````````````/S___]&1S$``````````````````@`!
-M``$``````````````/K___]&1S``````````````````````````````````
-M``````````````````````````````````````````````````````@````!
-M`````P````````````````````8```!&1S<``````````````````@``````
-M``````````````````!&1S8``````````````````0``````````````````
-M`/W___]&1S4``````````````````````````````````````/K___]&1S0`
-M```````````````````!``$``````````````/C___]&1S,`````````````
-M```````!``$````!``$``````/;___]&1S(````````````````````!````
-M`0`!``$``````//___]&1S$````````````````````!`````0`!`````0``
-M`/#___]&1S``````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M`````@````0````&````"`````H````,````#@```!````"L5`$`OD\!`*A0
-M`0!?4@$`R5(!`$]3`0#24P$````````````````````````````P````%8``
-M`!6````5@```%8```!6````<@```IX^-$L\/B`F5#^`$JP_@$L\/B`DHF```
-M`0`""@$``@H``0$%`0`""@$``@HTF```#@X```X.```.#@``#@X```X.```X
-MF```!P````<````+````"P````L```!(F```6MH8`%K:&`!IRA@`:<H8`&G*
-M&`!0F```X+3H#>"TZ`W@M.@-X+3H#>"TZ`U8F```+@V`?BX-@'XN3>A^+DWH
-M?BX-@'Y<F```7F8W,5YF-S%>9C<Q7F8W,5YA-S%LF```@;`,!8&P#`6!L`P%
-M@+`,!8"P#`44F0``$"<``!`G``!\%0``^"H``!`G``!$F0``(!"X]R`0N/<@
-M#;CW(!"X]R`0N/<,H@``:D$L9&I!+&1J04!D:D%`9&I!0&0<H@``"H"#&`J`
-M@Q@*@',8"H"#&`J`@Q@`````````````````````,!(````````(F```````
-M`"R8``#^+P(`/)@````!`@!,F```/&&$$C"9``"#2```0)D```0```!8F0``
-M_P```'29````````^)D``!@````$H@````````BB``"(9S[0**(``+4!```\
-MH@``KXG($P2;```@````")L``!`````,FP``,````!";```(````%)L``"@`
-M```8FP``!````!R;```D````()L``!0````DFP``-````"R;```L````,)L`
-M``(````TFP``(@```#R;```R````0)L```H```!$FP``*@```$B;```&````
-M3)L``"8```!0FP``%@```%2;```V````6)L```X```!<FP``+@```&";```!
-M````:)L``!$```!LFP``,0```'";```)````=)L``"D```!XFP``!0```'R;
-M```E````@)L``!4```"$FP``-0```(B;```-````D)L```,```"4FP``(P``
-M`)B;```3````H)L```L```"DFP``*P```*B;```K````K)L``"L```"PFP``
-M*P```+2;```K````N)L``"L```"\FP``*P```,";```K````Q)L``"L```#(
-MFP``*P```,R;```K````T)L``"L```#4FP``*P```-B;```K````W)L``"L`
-M``#@FP``*P```.2;```K````Z)L``"L```#LFP``*P```/";```K````])L`
-M`"L```#XFP```@```/R;```6````G)@`````````````````````````````
-MG)@`````````````````````````````G)@`````````````````````````
-M````G)@`````````````````````````````G)@`````````````````````
-M````````G)@`````````````````````````````G)@`````````````````
-M````````````G)@`````````````````````````````G)@`````````````
-M````````````````G)@`````````````````````````````G)@`````````
-M````````````````````G)@`````.````#@````X````.````#@`G)@`````
-M````````````````````````G)@`````````````````````````````G)@`
-M````````````P````(````"`````G)@``/D`!`#Y``0`_P`$`/T`!`#]``0`
-MU)@`````````````!`````0````$````````````````F@``J0$````````$
-MF@``Z0$``$`````(F@``*0```(`````,F@``:0```%`!```0F@``F0$``)`!
-M```4F@``V0$``-`!```8F@``&0```!`````<F@``60```$0````@F@``F0``
-M`(0````DF@``I0$``$@!```HF@``Y0$``(@!```LF@``)0```,@!```PF@``
-MR`$``!0````TF@``"````$(````XF@``2````((````\F@``B````'@!``!`
-MF@``F`$``+@!``!$F@``V`$``/@!``!(F@``&````!(```!,F@``6````%(`
-M``!0F@``F````)(```!4F@``I`$``'P!``!8F@``Y`$``+P!``!<F@``)```
-M`/P!``!@F@``9`````H```!DF@``I````$H```!HF@``Y````(H```!LF@``
-M"@$``%H!``!PF@``2@$``)H!``!TF@``B@$``-H!``!XF@``R@$```X```!\
-MF@``"@```$X```"`F@``2@```(X```"$F@``B@```%X!``"(F@``N@$``)X!
-M``",F@``^@$``-X!``"0F@``.@````D```"4F@``>@```$D```"8F@``A@$`
-M`(D```"<F@``Q@$``'D!``"@F@``!@```+D!``"DF@``1@```/D!``"HF@``
-MA@```#D```"LF@``Q@```'D```"PF@``Q@```+D```"TF@``Q@```+T!``"X
-MF@``Q@```/T!``"\F@``Q@```#T```#`F@``Q@```'T```#$F@``Q@```+T`
-M``#(F@``Q@```/T```#,F@``Q@```/T```#0F@``Q@```/T```#4F@``Q@``
-M`/T```#8F@``Q@```/T```#<F@``Q@```/T```#@F@``Q@```/T```#DF@``
-MQ@```/T```#HF@``Q@```/T```#LF@``Q@```/T```#PF@``Q@```/T```#T
-MF@``Q@```/T```#XF@``Q@```/T```#\F@``Q@```/T```#4F```(````-28
-M```0````%````!`````0````%````-B8``!H$&``:!!@`&@08`!H$&``:!!@
-M````````````G)@`````````````````````````````G)@`````````````
-M````````````````G)@`````````````````````````````G)@`````````
-M````````````````````G)@`````````````````````````````G)@`````
-M`!`````0````$````!`````0G)@```````0````$````!`````0````$G)@`
-M````````````````````````````G)@`````````````````````````````
-MG)@`````````````````````````````G)@`````````````````"@``````
-M````G)@``,``.`"``#@`P``X`L``.`#``#@`G)@```8``@`&``(`!@````8`
-M`@`&``(`G)@``(D```")````B0```(D```")````G)@``*````"@````H```
-M`*````"@````G)@```<`!``'``0`!P`$``<`!``'``0`U)@``!H````:````
-M&@```!H````:``````````````"<F```0````$@```!`````0````$````"<
-MF```$````!`````0````$````!````"<F```"`````@````(````"`````@`
-M``"<F```3P```$\```!/````3P```$\```"<F```\0```/$```!A````\0``
-M`/$```"<F```3Y```$^0``!,D```3Y```$^0``"<F```6A(``%H2``":$@``
-M6A(``%H2``#,F```#@````X````/````#@````X````!````1@```&`````!
-M````1@```&$````!````1@```&(````!````1@```&,````!````1@```&0`
-M```!````1@```&4````!````1@```&8````!````1@```&<````!````1@``
-M`&@````!````1@```&D````!````1@```&H````!````1@```&L````!````
-M1@```&P````!````1@```'0````!````1@```'0````!````1@```'0````!
-M````1@```'0````!````1@```'0````!````1@```'0````!````1@```'0`
-M```!````1@```'0````!````1@```'4````!````1@```'8````!````1@``
-M`'<````!````1@```'@````!````1@```'D````!````1@```'H````!````
-M1@```'L````!````1@```'P````!````1@```'T````!````1@```'X````!
-M````1@```'\````!````1@```(`````!````1````'P````!````1@```(@`
-M```!````1@```(P````!````1@```)`````!````1@```)0````!````1@``
-M`)@````!````1@```)P````!````1@```*`````!````1@```*0````!````
-M1@```*@````!````1@```*P````!````1@```+`````!````1@```+0```!Y
-M8`$`7&`!`&!@`0!D8`$`=&`!`'1@`0!H8`$`;&`!````````````````````
-M`````````````)X6!@!B%@0`.A8#`!P6`@#J%0$`FA4``$H5```#%0$`610#
-M`+@+!0`````````````````````````````````P````%8```!6````5@```
-M%8```!6````<@```IY.-$L\3B`F5$^`$JQ/@$L\3B`DHF````0`""@$``@H`
-M`0(%`0`""@$``@HTF```#@X```X.```.#@``#@X```X.```XF```!P````<`
-M```+````"P````L```!(F```;=H8`&W:&`!URA@`=<H8`'7*&`!0F```X+3H
-M#>"TZ`W@M.@-X+3H#>"TZ`U8F```+@V`?BX-@'XN#>A^+@WH?BX-@'Y<F```
-M7F8W,5YF-S%>9C<Q7F8W,5YF-S%LF```@;`,!8&P#`6!L`P%@;`,!8&P#`44
-MF0``T`<``-`'``!,!```F`@``-`'``!$F0``(!"X]R`0N/<0#;CW$!"X]Q`0
-MN/<$H@`````````````(````"`````@````(H@``B&>^UHAGOM:(9S[0B&<^
-MT(AG/M`,H@``0`$L9$`!+&1@P4)D8,%"9&#!0F0<H@``"H"#&`J`@Q@*@',8
-M"H"#&`J`@Q@P$@````````B8````````+)@``/XO`@`\F`````$"`$R8```\
-M8802,)D``()(``!`F0``!````%B9``#_````=)D````````HH@``M0$``#RB
-M``"OB<@3!)L```$````(FP```@````R;```#````$)L```0````4FP``!0``
-M`!B;```(````')L```D````@FP``"@```"2;```+````+)L```T````PFP``
-M$````#2;```1````/)L``!,```!`FP``%````$2;```5````2)L``!@```!,
-MFP``&0```%";```:````5)L``!L```!8FP``'````%R;```=````8)L``"``
-M``!HFP``(@```&R;```C````<)L``"0```!TFP``)0```'B;```H````?)L`
-M`"D```"`FP``*@```(2;```K````B)L``"P```"0FP``,````)2;```Q````
-MF)L``#(```"@FP``-````*2;```U````J)L``#4```"LFP``-0```+";```U
-M````M)L``#4```"XFP``-0```+R;```U````P)L``#4```#$FP``-0```,B;
-M```U````S)L``#4```#0FP``-0```-2;```U````V)L``#4```#<FP``-0``
-M`.";```U````Y)L``#4```#HFP``-0```.R;```U````\)L``#4```#TFP``
-M-0```/B;```0````_)L``!H`````````````````````````````````````
-MF@``!P````<````$F@``1P```$<````(F@``AP```(<````,F@``H`$``*`!
-M```0F@``X`$``.`!```4F@``(````"`````8F@``8````&`````<F@``H0$`
-M`*$!```@F@``X0$``.$!```DF@``(0```"$````HF@``80```&$````LF@``
-M8@$``&(!```PF@``H@$``*(!```TF@``X@$``.(!```XF@``(@```"(````\
-MF@``8@```&(```!`F@``8P$``&,!``!$F@``HP$``*,!``!(F@``XP$``.,!
-M``!,F@``(P```",```!0F@``8P```&,```!4F@``A`$``(0!``!8F@``Q`$`
-M`,0!``!<F@``!`````0```!@F@``Z@$```L```!DF@``*@```$L```!HF@``
-M:@```(L```!LF@``J@```*P!``!PF@``JP$``.P!``!TF@``ZP$``"P```!X
-MF@``*P```!(```!\F@``:P```%(```"`F@``JP```)(```"$F@``K`$``),!
-M``"(F@``[`$``-,!``",F@``+````!,```"0F@``.@```%,```"4F@``>@``
-M`),```"8F@``N@```)0!``"<F@``NP$``-0!``"@F@``^P$``!0```"DF@``
-M.P```#H```"HF@``>P```'H```"LF@``NP```+H```"PF@``O`$``+L!``"T
-MF@``_`$``/L!``"XF@``/````#L```"\F@``?````'L```#`F@``O````+L`
-M``#$F@``_````+P!``#(F@``_````/P!``#,F@``_````#P```#0F@``_```
-M`'P```#4F@``_````+P```#8F@``_````/P```#<F@``_````/P```#@F@``
-M_````/P```#DF@``_````/P```#HF@``_````/P```#LF@``_````/P```#P
-MF@``_````/P```#TF@``_````/P```#XF@``_````/P```#\F@``_````/P`
-M``#4F```(````-"8```(!`8#"`0'`P@$!@,(!`8#"`0'`]R8``#`(*``P""@
-M`,`@X`#`(.``P"#@````````````G)@```````\````/````#P````\````/
-MG)@`````````````````````````````G)@`````@````(````"`````@```
-M`(``G)@`````*@```"H````J````*@```"H`G)@``````0````$````!````
-M`0````$`G)@`````````````````````````````G)@`````&````!@````8
-M````&````!@`G)@`````8````&````!N````;@```&X`G)@`````QP```,<`
-M``#'````QP```,<`G)@`````2P```$L```!+````2P```$L`G)@`````2`0`
-M`$@$``!(!```2`0``$@$G)@`````3````$P```!,````3````$P`G)@`````
-MY````.0```#D````Y````.0`G)@`````````````````````````````G)@`
-M````_````/P```#\````_````/P`G)@`````_P```/\```#_````_P```/\`
-MG)@`````/P0``#\$```_!```/P0``#\$G)@`````#`````P````,````#```
-M``P`G)@`````&0(``!D"```9`@``&0(``!D"G)@`````)````"0````D````
-M)````"0`G)@`````M````+0```"T````M````+0`G)@`````F0```)D```"9
-M````F0```)D`G)@`````4````%````!0````4````%``G)@`````*@```"H`
-M```J````*@```"H`G)@`````$@```!(````2````$@```!(`G)@`````,L``
-M`#+````RP```,L```#+`G)@`````=`$``'0!``!T`0``=`$``'0!G)@`````
-M$0```!$````1````$0```!$`G)@`````*(8``"B&```HA@``*(8``"B&G)@`
-M````A#$``(0Q``"$,0``A#$``(0QG)@``(``\@"``/(`@`#R`(``\@"``/(`
-MG)@``!D`)P`9`"<`&0`G`!D`)P`9`"<`G)@```,````#`````P````,````#
-M````G)@`````````````````````````````G)@``+(```"R````L@```+(`
-M``"R````G)@``(0@L`"$(+``A""P`(0@L`"$(+``G)@``*0E00"D)4$`I"5!
-M`*0E00"D)4$`G)@``""2$0`@DA$`()(1`""2$0`@DA$`G)@```!(&@``2!H`
-M`$@:``!(&@``2!H`V)@``#`""P`P`@L`,`(+`#`""P`P`@L`G)@``)0```"4
-M````E````)0```"4````G)@``)$```"1````D0```)$```"1````G)@``!(`
-M```2````$@```!(````2````G)@``(````"`````@````(````"`````G)@`
-M`-D```#9````V0```-D```#9````G)@``&````!@````8````&````!@````
-MG)@``/````#P````\````/````#P````G)@``*(```"B````H@```*(```"B
-M````G)@``%(```!2````4@```%(```!2````G)@``-0```#4````U````-0`
-M``#4````G)@``,P4``#,%```S!0``,P4``#,%```G)@``(P$``",!```C`0`
-M`(P$``",!```Q)@```,````#`````P````,````#````&'(!`!UR`0`$<@$`
-M"'(!`!AR`0`8<@$`#'(!`!!R`0```````````#`````5````%0```!4````5
-M````%0```!R```"GDXT2SQ.("943X`2K$^`2SQ.("2B8```!``(*`0`""@``
-M`@4!``(*`0`""C28````#@````X````.````#@````X``#B8```"`````@``
-M``H````*````"@```$B8``!MVA@`;=H8`&1J&@!D:AH`9&H:`%"8``#@M.@-
-MX+3H#=JPZ`W:L)@,VK#H#5B8```N#8!^+@V`?BX-Z'XN#<A^+@V`?ER8``!>
-M9C<Q7F8W,5YF-S%>8#DQ7F8W,6R8``"!L`P%@;`,!8&P#`6!L`P%@;`,!129
-M``#0!P``T`<``$P$``"8"```T`<``$29````$+CW`!"X]P`-N/<`$+CW`!"X
-M]P2B``````````````````````````````BB``"(9[[6B&>^UHAG/M"(9S[0
-MB&<^T`RB``!``2P`0`$L`$#!0@!`P4(`0,%"`!RB```*@(,8"H"#&`J`8Q@*
-M@(,8"H"#&#`2``#@`P``8(````\````8@0```````!R!````````(($`````
-M```D@0```````"B!````````+($````````P@0```````#2!````````.($`
-M```````\@0```````$"!``"H``"`1($````````(F````````"R8````H```
-M/)@````$(`!,F```/".$$G"8```?````=)@``(````!XF```#@```%B9``#_
-M````@)D```````"$F0````"``J"9````````X)D```````#DF0``JJJJJNB9
-M``!X9$8\[)D``*H```#PF0``#````/29``#_````^)D``!0````HH@``M0D`
-M`#RB``"OB<B33*(```$```!0H@```*```%2B````````6*(``(!3QPQ<H@``
-M`0\/#V"B```!#VE?9*(``!&*00!HH@```````&RB``!JP3`,<*(``"`(@@!T
-MH@``JGP;`'BB``#..><<?*(``,X!%P4`HP`````!&`2C```")@,P"*,```8^
-M!T@,HP``"DP+5A"C```/8!ID%*,``!MN3W@8HP``6GR/AARC``!;AL^.(*,`
-M``^73YTDHP``CZ'/I2BC```?KU^U+*,``)^YW[TPHP``/\=_S32C``"_T?_5
-M.*,````````\HP```````$"C````````1*,```````!(HP``____/TRC``#_
-M__\_4*,``/___S]4HP``__\#`%BC```?JJAY7*,```]";`9@HP``!R(H#V2C
-M``"%%F`7:*,```01@!]LHP```PR@-W"C``"#",0_=*,```,(P%=XHP``@@;8
-M7WRC``""!.!_@*,``+I[/'^$HP``\'\P\P2;```!````")L```(````,FP``
-M`P```!";```$````%)L```4````8FP``"````!R;```)````()L```H````D
-MFP``"P```"R;```-````,)L``!`````TFP``$0```#R;```3````0)L``!0`
-M``!$FP``%0```$B;```8````3)L``!D```!0FP``&@```%2;```;````6)L`
-M`!P```!<FP``'0```&";```@````:)L``"(```!LFP``(P```'";```D````
-M=)L``"4```!XFP``*````'R;```I````@)L``"H```"$FP``*P```(B;```L
-M````D)L``#````"4FP``,0```)B;```R````H)L``#0```"DFP``-0```*B;
-M```U````K)L``#4```"PFP``-0```+2;```U````N)L``#4```"\FP``-0``
-M`,";```U````Q)L``#4```#(FP``-0```,R;```U````T)L``#4```#4FP``
-M-0```-B;```U````W)L``#4```#@FP``-0```.2;```U````Z)L``#4```#L
-MFP``-0```/";```U````])L``#4```#XFP``$````/R;```:````````````
-M````F@`````````````$F@```````$`````(F@```````(`````,F@``````
-M`($!```0F@```````,$!```4F@````````$````8F@```````$$````<F@``
-M`````($````@F@```````&@!```DF@```````*@!```HF@```````.@!```L
-MF@```````"@````PF@```````&@````TF@```````(D!```XF@```````,D!
-M```\F@````````D```!`F@```````$D```!$F@```````(D```!(F@``````
-M`)`!``!,F@```````-`!``!0F@```````!````!4F@```````%````!8F@``
-M`````)````!<F@```````)$!``!@F@```````-$!``!DF@```````!$```!H
-MF@```````%$```!LF@```````)$```!PF@```````'@!``!TF@```````+@!
-M``!XF@```````/@!``!\F@```````#@```"`F@```````'@```"$F@``````
-M`)D!``"(F@```````-D!``",F@```````!D```"0F@```````%D```"4F@``
-M`````)D```"8F@```````-D```"<F@```````/D```"@F@```````/D```"D
-MF@```````/D```"HF@```````/D```"LF@```````/D```"PF@```````/D`
-M``"TF@```````/D```"XF@```````/D```"\F@```````/D```#`F@``````
-M`/D```#$F@```````/D```#(F@```````/D```#,F@```````/D```#0F@``
-M`````/D```#4F@```````/D```#8F@```````/D```#<F@```````/D```#@
-MF@```````/D```#DF@```````/D```#HF@```````/D```#LF@```````/D`
-M``#PF@```````/D```#TF@```````/D```#XF@```````/D```#\F@``````
-M`/D```#4F```(````-"8```(%``""!0!`@@4``((%``""!0!`MR8``#`(*``
-MP""@`,`@X`#`(.``P"#@````````````G)@``````/````#P````\````/``
-M``#PG)@`````````````````````````````G)@```````,````#`````P``
-M``,````#G)@`````````````````````````````G)@`````````````````
-M````````````G)@`````````````````````````````G)@`````````````
-M````````````````G)@`````````````````````````````G)@`````0$``
-M`$!```!`0```0$```$!`G)@`````!64```5E```%90``!64```5EG)@`````
-M````````````````````````G)@`````````````````````````````G)@`
-M````0@```$(```!"````0@```$(`G)@`````M0```+4```"U````M0```+4`
-MG)@``````P````,````#`````P````,`G)@`````]P```/<```#W````]P``
-M`/<`G)@`````G0```)T```"=````G0```)T`G)@`````(@```"(````B````
-M(@```"(`G)@`````(@0``"($```B!```(@0``"($G)@``!@`(P`8`",`&``C
-M`!@`(P`8`",`G)@`````*````"@`8``H`&``*`!@`"@`G)@``,``4`#``%``
-MPP!0`,,`4`##`%``G)@``'\`!`!_``0`?P`$`'\`!`!_``0`G)@``%@$``!8
-M!```6`0``%@$``!8!```G)@`````````````````````````````G)@```#`
-M````P````,````#`````P```V)@``#`"0``P`D``,`)``#`"0``P`D``````
-M````````````````````````````G)@```!D````9````&0```!D````9```
-MG)@````(````"`````@````(````"```S)@```X````.````#@````X````.
-M````2(X!`$V.`0`XC@$`/(X!`$B.`0!(C@$`0(X!`$2.`0``````````````
-M```````````````````P````%0```!4````5````%0```!4````<@```IY.-
-M$L\3B`F5$^`$JQ/@$L\3B`DHF````0`""@$``@H``0(%`0`""@$``@HTF```
-M#@X```X.```.#@``#@X```X.```XF```!P````<````+````"P````L```!(
-MF```8?H8`&'Z&`!C&AH`8QH:`&,:&@!0F```X+28#."TF`S:L)@,VK"8#-JP
-MF`Q8F```+@W(?BX-R'XN#<A^+@W(?BX-R'Y<F```7F`Y,5Y@.3%>8#DQ7F`Y
-M,5Y@.3%LF```@;`,!8&P#`6!L`P%@;`,!8&P#`44F0``T`<``-`'``!,!```
-MF`@``-`'``!$F0```!"X]P`0N/<`#;CW`!"X]P`0N/<$H@``````````````
-M```````````````(H@``B&>^UHAGOM:(9S[0B&<^T(AG/M`,H@``X,$N`.#!
-M+@`@P2H`(,$J`"#!*@`<H@``"H"#&`J`@Q@*@&,8"H"#&`J`@Q@`HP`````!
-M&````1@```$8```!&````1@$HP```B8#,`(F`S`")@,P`B8#,`(F`S`(HP``
-M!CX'2`8^!T@&/@=(!CX'2`8^!T@,HP``"DP+5@I,"U8*3`M6"DP+5@I,"U80
-MHP``#V`:9`]@&F0/8!ID#V`:9`]@&F04HP``&VY/>!MN3W@;;D]X&VY/>!MN
-M3W@8HP``6GR/AEI\CX9:?(^&6GR/AEI\CX8<HP``6X;/D%N&SY!;AL^.6X;/
-MCEN&SXX@HP``#Y=/G0^73YT/ET^;#Y=/FP^73YLDHP``CZ//IX^CSZ>/G\^C
-MCY_/HX^?SZ,HHP``'Z]?M1^O7[4?KU^S'Z]?LQ^O7[,LHP``G[G?O9^YW[V?
-MN=^[G[G?NY^YW[LPHP``/\5_RS_%?\L_QW_+/\=_RS_'?\LTHP``O]'_U;_1
-M_]6_T?_3O]'_T[_1_],`````````````````````,!(``.`#``!H0```$```
-M`&"````/````G(````````"@@````````!B!````````'($````````@@0``
-M`````"2!````````*($````````L@0```````#"!````````-($````````X
-M@0```````#R!````````0($``/D#`(!$@0````````B8````````+)@```"@
-M```\F`````0@`$R8```\(X02<)@``!\```!TF```@````'B8```.````6)D`
-M`/\?"`"`F0```````(29`````(`"H)D```````#@F0```````.29``"JJJJJ
-MZ)D``'AD1CSLF0``J@```/"9```,````])D``/\```#XF0``%````"BB``"U
-M"0``/*(``*^)R)-,H@```0```%"B````H```5*(```````!8H@``@%/'#%RB
-M```!#P\/8*(```$/:5]DH@``$8I!`&BB````````;*(``&K!,`QPH@``(`B"
-M`'2B``"J?!L(>*(``,XYYQQ\H@``S@$7!3BC````````/*,```````!`HP``
-M`````$2C````````2*,``/___S],HP``____/U"C``#___\_5*,``/__`P!8
-MHP``'ZJH>5RC```/0FP&8*,```<B*`]DHP``A19@%VBC```$$8`?;*,```,,
-MH#=PHP``@PC$/W2C```#",!7>*,``((&V%]\HP``@@3@?X"C``"Z>SQ_A*,`
-M`/!_,/,$FP```0````B;```"````#)L```,````0FP``!````!2;```%````
-M&)L```@````<FP``"0```"";```*````))L```L````LFP``#0```#";```0
-M````-)L``!$````\FP``$P```$";```4````1)L``!4```!(FP``&````$R;
-M```9````4)L``!H```!4FP``&P```%B;```<````7)L``!T```!@FP``(```
-M`&B;```B````;)L``",```!PFP``)````'2;```E````>)L``"@```!\FP``
-M*0```(";```J````A)L``"L```"(FP``+````)";```P````E)L``#$```"8
-MFP``,@```*";```T````I)L``#4```"HFP``-0```*R;```U````L)L``#4`
-M``"TFP``-0```+B;```U````O)L``#4```#`FP``-0```,2;```U````R)L`
-M`#4```#,FP``-0```-";```U````U)L``#4```#8FP``-0```-R;```U````
-MX)L``#4```#DFP``-0```.B;```U````[)L``#4```#PFP``-0```/2;```U
-M````^)L``!````#\FP``&@````":``````````````2:``!`````0`````B:
-M``"`````@`````R:``"A`0``80$``!":``#A`0``H0$``!2:```A````X0$`
-M`!B:``!A````(0```!R:``"(`0``80```"":``#(`0``B`$``"2:```(````
-MR`$``"B:``!(````"````"R:``"(````2````#":``"I`0``B````#2:``#I
-M`0``:0$``#B:```I````J0$``#R:``!I````Z0$``$":``#0`0``*0```$2:
-M```0````:0```$B:``!0````D`$``$R:``"0````T`$``%":``"Q`0``$```
-M`%2:``#Q`0``4````%B:```Q````D````%R:``!Q````<0$``&":``"X`0``
-ML0$``&2:``#X`0``\0$``&B:```X````,0```&R:``!X````<0```'":``"9
-M`0``F`$``'2:``#9`0``V`$``'B:```9````&````'R:``!9````6````(":
-M``"9````F````(2:``#9````>0$``(B:``#Y````N0$``(R:``#Y````^0$`
-M`)":``#Y````.0```)2:``#Y````>0```)B:``#Y````N0```)R:``#Y````
-M^0```*":``#Y````^0```*2:``#Y````^0```*B:``#Y````^0```*R:``#Y
-M````^0```+":``#Y````^0```+2:``#Y````^0```+B:``#Y````^0```+R:
-M``#Y````^0```,":``#Y````^0```,2:``#Y````^0```,B:``#Y````^0``
-M`,R:``#Y````^0```-":``#Y````^0```-2:``#Y````^0```-B:``#Y````
-M^0```-R:``#Y````^0```.":``#Y````^0```.2:``#Y````^0```.B:``#Y
-M````^0```.R:``#Y````^0```/":``#Y````^0```/2:``#Y````^0```/B:
-M``#Y````^0```/R:``#Y````^0```-28```@````T)@```@````(````"```
-M``@````(````W)@``,``H`#``*``P`#@`,``X`#``.````````````"<F```
-M````,P```#,````S````,P```#.<F````````0````$````!`````0````&<
-MF`````````````````````````````"<F```````````````````````````
-M``"<F`````````````````````````````"<F```````'P```!\````?````
-M'P```!^<F`````````````````````````````"<F`````"X````N````+@`
-M``"X````N`"<F`````"W````MP```+<```"W````MP"<F`````"$````A```
-M`(0```"$````A`"<F`````"8````F````)@```"8````F`"<F`````#`````
-MP````,````#`````P`"<F`````#_````_P```/\```#_````_P"<F`````#_
-M````_P```/\```#_````_P"<F`````#_````_P```/\```#_````_P"<F```
-M``#_````_P```/\```#_````_P"<F`````#7````UP```-<```#7````UP"<
-MF`````!A````80```&$```!A````80"<F`````#^````_@```/X```#^````
-M_@"<F`````#>````W@```-X```#>````W@"<F`````!_````?P```'\```!_
-M````?P"<F``````]!```/00``#T$```]!```/02<F`````!W````=P```'<`
-M``!W````=P"<F`````!$````1````$0```!$````1`"<F`````"8````F```
-M`)@```"8````F`"<F```@``0`(``$`"``!``@``0`(``$`"<F```-,`%`#3`
-M!0`TP`4`-,`%`#3`!0"<F```\``Q`/``,0#P`#$`\``Q`/``,0"<F```'P$,
-M`!\!#``?`0P`'P$,`!\!#`"<F```0`!1`$``40!``%$`0`!1`$``40"<F```
-MV@!0`-H`4`#:`%``V@!0`-H`4`"<F`````````````````````````````"<
-MF```1$```$1```!$0```1$```$1```"<F```````````````````````````
-M``"<F```P&```,!@``#`8```P&```,!@``"<F````"P````L````-@```#8`
-M```L``#(F````P0```,$```#!````P0```,$`````````````)R8````9```
-M`&0```!D````9````&0``)R8````"`````@````(````"`````@``,R8```.
-M````#@````X````.````#@```$BC`0!-HP$`-*,!`#BC`0!(HP$`2*,!`#RC
-M`0!`HP$`05(U,C$P`$%2-3(Q,0!!4C4R,3(`4D8U,3$Q`%)&-3$Q,@!21C(T
-M,3,`4D8U-#$S`$%T:&5R;W,@,C,Q,R!7:5-O0P!!=&AE<F]S(#4T,C0O,C0R
-M-`!!=&AE<F]S(#(S,3<@5VE3;T,`071H97)O<R`U,C$R("A&4$=!*0!!=&AE
-M<F]S(#4R,3$@*$901T$I`$%T:&5R;W,@-3(Q,`!!=&AE<F]S(#4R,3$`071H
-M97)O<R`U,S$R(%=I4V]#`$%T:&5R;W,@,C,Q-2!7:5-O0P!!=&AE<F]S(#4R
-M,3(````````````````````````````````````P+CDN,C`N,P``````````
-M```````````````````````````'````#@```!4````<````(P```"H`````
-M``````#_`?\!`````````````/________]_``````,`F`&9`0``````````
-M``#_________?P`````'`)@!,`L`````````````_________W\`````"`"8
-M`3`,`````````````/________]_`````"``(`$0"@````````````#_____
-M____?P`````A`"`!F0$`````````````_________W\`````(@`@`3`,````
-M`````````/________]_`````#H`8`$0"@````````````#_________?P``
-M```[`&`!F0$`````````````_________W\`````$@!E`1`*```#````````
-M`/________]_`````#<`,`&9`0```P````````#_________?P`````U`#`"
-MF0$```,`````````_________W\`````-@`P`YD!```#`````````/______
-M__]_`````#``,`29`0```P````````#_________?P`````Y`#`%F0$```,`
-M````````_________W\`````-``P!ID!```#`````````/________]_````
-M`#(`,`.9`0```P````````#_________?P`````Q`#`#F0$`````````````
-M_________W\`````$0`0`9D!`````````````/________]_`````!``$`$0
-M"@````````````#_________?P````!2`%`!F0$`````````````________
-M_W\`````10!0`ID!`````````````/________]_`````$<`4`.9`0``````
-M``````#_________?P````!"`%`$F0$`````````````_________W\`````
-M6`!0!9D!`````````````/________]_`````%L`4`:9`0````````````#_
-M________?P````!=`%`(F0$`````````````_________W\`````7@!0"9D!
-M`````````````/________]_`````%``4`,0"@````````````#_________
-M?P````!5`%`!,`P`````````````_________W\`````5@!0`C`,````````
-M`````/________]_`````$D`4`)0#0````````````#_________?P````!`
-M`$`!0`H``$8````$````*`````````"(`0``00!``4`*``!'````!````&@`
-M````````B0$``$@`0`$0"@``1@````0````(`````````(H!``!*`$`!0`H`
-M`$8````$````"!@```````",`0``2P!``4`*``!&````!`````A@````````
-MC0$``$P`0`%0"@``1@````0````(`````````(\!``!#`$`"0`H``$<````$
-M````<`````````"+`0``\`!``T`*``!&````!````"```````````````(``
-M0`-`"@``1P````0```!@`````````*</``#Q`$`#0`H``$8````$`````!@`
-M````````````@0!``T`*``!&````!`````!@````````J`\``((`0`-0"@``
-M1@````0``````````````*D/``#R`$`#$`H``$8````$````````````````
-M````@P!`!$`*``!'````!````&"`````````J@\``/0`0`1`"@``1@````0`
-M````F`````````````"$`$`$0`H``$8````$`````.````````"K#P``A0!`
-M!%`*``!&````!`````"`````````K`\``/4`0`00"@``1@````0`````@```
-M``````````"&`$`%0`H``$<````$````8(````````"M#P``AP!`!4`*``!&
-M````!`````#@````````K@\``(@`0`50"@``1@````0`````@````````*\/
-M``")`$`&0`H``$<````$````:`````````"P#P``B@!`!D`*``!&````!```
-M``A@````````L0\``(L`0`90"@``1@````0````(`````````+(/``",`$`'
-M0`H``$<````$````:(````````"S#P``C0!`!T`*``!&````!`````C@````
-M````M`\``(X`0`=0"@``1@````0````(@````````+4/``"/`$`(0`H``$<`
-M```$````:(````````"V#P``D`!`"$`*``!&````!`````C@````````MP\`
-M`)$`0`A0"@``1@````0````(@````````+@/``#V`$`)0`H``$<````$````
-M8(``````````````]P!`"T`*``!'````!````&"``````````````&``8`!@
-M``````````````#_________?P````!A`&$`80````,`````````________
-M_W\`````8@!B`&(````"`````````/________]_`````&,`8P!C````````
-M``````#_________?P````!D`&0`9`````,`````````_________W\`````
-M90!E`&4````#`````````/________]_`````&8`9@!F``````````````#_
-M________?P````!G`&<`9P``````````````_________W\`````:`!H`&@`
-M`````````````/________]_`````&D`:0!I`````P````````#_________
-M?P````!J`&H`:@````,`````````_________W\`````````````````````
-M90````$```#_____@````/____\`````2E```+0/````````:@````$```#_
-M____@````/____\`````2E```+0/````````````````````````````````
-M````````_P$```$````!`````0```%@;`````!```0````$````!````6!L`
-M``@``P`!``````````$```!8&P``#``#``$``````````0```%@;```@`$<`
-M````````````````6!L``#,`,``!``````````$```!8&P``)``A``$````!
-M`````0```%@;```H`#<``0`````````!````6!L``!\`,``!`````0````$`
-M``!8&P``,`!;``$``````````0```%@;``!P``,``0`````````!````6!L`
-M`#@`-P`!``````````$```!8&P``5`!5``$````!`````0```%@;``!$`%4`
-M`0````$````!````6!L``$P`.P`!``````````````!8&P``8`!2``$````!
-M`````0```%@;``!D`#0``0`````````!````6!L``'P`(``!`````0````$`
-M``!8&P``F`!;``$````!`````0```%@;``"<`%(``0````$````!````6!L`
-M`*H`$``!``````````$```!8&P``O``#``$``````````0```%@;``"_`#8`
-M`0`````````!````6!L``,0`-P`!`````0````$```!8&P``RP`W``$`````
-M`````0```%@;``#0`#<``0`````````!````6!L``-8`$``!`````0````$`
-M``!8&P``V@`#`````````````````%@;```R`S8``0`````````!````6!L`
-M`-X``P`!``````````$```!8&P``Z0`W``$``````````0```%@;``#V`#<`
-M`0`````````!````6!L``/H`-P`!``````````$```!8&P``_P`V``$`````
-M`````0```%@;```,`3```0````$````!````6!L``!0!-P`!``````````$`
-M``!8&P``+`$W``$``````````0```%@;``!``1```0````$````!````6!L`
-M`%0!`P`!``````````$```!8&P``6`$A``$````!`````0```%@;``!<`3<`
-M`0`````````!````6!L``&`!-P`!``````````$```!8&P``9`%;``$`````
-M`````0```%@;``!H`5(``0`````````!````6!L``&P!4@`!`````0````$`
-M``!8&P``=`$W``$``````````0```%@;``!X`0,``0`````````!````6!L`
-M`'P!-P`!``````````$```!8&P``B`%```$``````````````%@;``")`4$`
-M`0``````````````6!L``(H!2``!``````````````!8&P``BP%#``$`````
-M`````````%@;``",`4H``0``````````````6!L``(T!2P`!````````````
-M``!8&P``CP%,``$``````````````%@;``"G#X```0``````````````6!L`
-M`*@/@0`!``````````````!8&P``J0^"``$``````````````%@;``"J#X,`
-M`0``````````````6!L``*L/A``!``````````````!8&P``K`^%``$`````
-M`````````%@;``"M#X8``0``````````````6!L``*X/AP`!````````````
-M``!8&P``KP^(``$``````````````%@;``"P#XD``0``````````````6!L`
-M`+$/B@`!``````````````!8&P``L@^+``$``````````````%@;``"S#XP`
-M`0``````````````6!L``+0/C0`!``````````````!8&P``M0^.``$`````
-M`````````%@;``"V#X\``0``````````````6!L``+</D``!````````````
-M``!8&P``N`^1``$``````````````%@;``"0`4(``0`````````!````6!L`
-M`(X!`P`!``````````$```!8&P``F`%%``$````!`````0```%@;``":`44`
-M`0``````````````6!L``)L!10`!``````````````!8&P``G`%>``$`````
-M`````````%@;``">`0,``0`````````!````6!L``*P!-P`!``````````$`
-M``!8&P``I@$#``$``````````0```%@;``"V`3<``0`````````!````6!L`
-M`+@!-P`!``````````$```!8&P``N@$W``$``````````0```%@;``"^`2$`
-M`0````$````!````6!L``"<#`P`!``````````$```!8&P``R@%=``$`````
-M`````````%@;``#6`3<``0`````````!````6!L``.0!$``!`````0````$`
-M``!8&P``[`$P``$````!`````0```%@;``#X`0,``0`````````!````6!L`
-M`!`"-P`!``````````$```!8&P``*@(B``$``````````0```%@;``!"`C<`
-M`0`````````!````6!L````"6P`!``````````$```!8&P``2@(#``$`````
-M`````0```%@;``!/`A```0````$````!````6!L``%P"4@`!``````````$`
-M``!8&P``8`([``$````!`````0```%@;``!H`C<``0`````````!````6!L`
-M`&P"-P`!``````````$```!8&P``=@(0``$````!`````0```%@;``!Z`@,`
-M`0`````````!````6!L``(("`P`!``````````$```!8&P``@P(#``$`````
-M`````0```%@;``"J`B$``0`````````!````6!L``+X"6P`!`````0````$`
-M``!8&P``OP(W``$``````````0```%@;``#!`C<``0`````````!````6!L`
-M`,8".P`!``````````$```!8&P``U`(W``$``````````0```%@;``#P`C<`
-M`0`````````!````6!L``/0"-P`!``````````$```!8&P``^`(#``$`````
-M`````0```%@;``">`%```0````$````!````6!L``/P"`P`!``````````$`
-M``!8&P``#`,P``$``````````0```%@;```4`S8``0`````````!````6!L`
-M`!@#-@`!``````````$```!8&P``)`,#``$``````````0```%@;```0`P,`
-M`0`````````!````6!L``#H#-P`!``````````$```!8&P``2`,0``$````!
-M`````0```,$6``!*`Q(``0````$````!````6!L``%H#$0`!``````````$`
-M``!8&P``7`,Z``$````!`````0```%@;``!>`U8``0`````````!````6!L`
-M`,`"`P`!``````````$```!8&P``=P,#``$``````````0```%@;``#,`@,`
-M`0`````````!````6!L````````S$ST3%P`*!0``````````$``````````0
-M````1Q-1$Q<`"@4``````````!``````````$````#@3=!,7`!04````````
-M```0``````````<```!.$WL3&P8%!0```````````0``````````````41-Y
-M$QX&"@4```````````$``````````````%83=!,A!A0%```````````!````
-M``````````"K$[`3%P`*!0``````````$``````````,````L!/8$Q<`%!0`
-M`````````!```````````@```+\3OQ,7``H%```````````0``````````P`
-M````%'@4!084%```````````````````````````,A1N%!<`%!0`````````
-M`!@``````````0```#(4;A04`!04```````````8``````````$````\%'@4
-M#P`4%```````````!0``````````````/!1X%!$&%!0```````````$`````
-M`````0```#P4>!02`!04```````````%```````````````\%'@4%``4%```
-M````````!0``````````````/!1X%!<`%!0```````````4`````````````
-M`#P4>!07!A04```````````!```````````````\%,@4%`84%`(`````````
-M!```````````````>!2@%!<`%!0!``````````4``````````````(P4H!07
-M`!04`P`````````%``````````````",%,@4$@`4%`,`````````!0``````
-M````````C!3(%!0`%!0'``````````6``````````````(P4R!04!A04`P``
-M```````!``````````(```",%,@4%P84%`,``````````0`````````"````
-MC!3(%!<&%!0#``````````$``````````````(P4R!0>`!04````````````
-M``````````````",%$06!084%`,`````````````````````````H!3(%!$&
-M%!0#``````````$``````````````'P5]!4>!A04`@`````````$````````
-M``````!\%406%`84%`,``````````0`````````$````?!5$%AL`%!0#````
-M``````4``````````````'P51!8>`!04`P`````````%``````````````!\
-M%406%P`4%`<``````````8``````````````<1:M%A<`%!0`````````````
-M`````````````'$6K18>!A04``````````````````````````!Q%JT6'@84
-M%`(`````````!```````````````<1;!%@4&%!0`````````````````````
-M`````'$6P181`!04``````````````````````````!Q%L$6%``4%```````
-M````````````````````<1;!%AX`%!0``````````````````````````'$6
-MP18>!A04``````````````````````,```!Q%L$6'@84%```````````````
-M````````````.!-T$QX`%!0````````````$`````````````+`3V!,>`!04
-M````````````!``````````````R%&X4'@`4%`,```````````0`````````
-M````/!1X%!X`%!0#```````````$`````````````(P4R!0>`!04`P``````
-M````!`````````````!Q%L$6'@`4%`````````````0`````````````?!5$
-M%AX`%!0#```````````$`````````````(P4R!0>`!04````````````````
-M```````````\%'@4'@`4%```````````````````````````P1;!%AX`%!0`
-M```````````$````````````````````````````````````````"A1:%`4&
-M*"@``````````````````````````((4TA0%!B@H`0``````````````````
-M``````#Z%'(5!08H*```````````````````````````FA42%@4&*"@!````
-M`````````````````````!X41A0%!B@H``````````````````````````!N
-M%+X4!08H*`$`````````````````````````YA1>%04&*"@`````````````
-M`````````````(85)A8%!B@H`0````````````````````````!0%'@4$08H
-M*```````````````````````````4!1X%!<&*"@`````````````````````
-M`````%H46A01!B@H``````````````````````````!:%%H4%P`H*```````
-M````````````````````H!2@%!<&*"@!``````````(``````````````*`4
-MH!04!B@H`0`````````"``````````````""%((4$0`H*`$``````````@``
-M````````````JA2J%!0`*"@!``````````(``````````````((4JA04`"@H
-M`0`````````"``````````````""%*H4%P8H*`$``````````@``````````
-M````I!4<%A0&*"@!``````````(``````````````(`6J!84`"@H````````
-M``````````````````"`%J@6'@8H*```````````````````````````A1:M
-M%AX&*"@``````````````````````````%H4@A0/`"@H`P``````````!```
-M``````````"J%*H4$@`H*`,```````````0`````````````I!4<%A0`*"@#
-M```````````$`````````````(`6J!84`"@H````````````!```````````
-M``````````````@)1`D%!A0%```````````````````````````("40)%``4
-M!0``````````````````````````;`FH"04&%`4`````````````````````
-M`````&P)J`D4`!0%```````````@``````````````!L":@)'@`4!0``````
-M````````````````````;`F>"1L&%`4``````````````````````````&P)
-MG@D4`!0%```````````@``````````````"`"8H)%``4!0``````````````
-M````````````F0FH"10`%`4``````````````````````````*,)J`D4`!0%
-M```````````@(`````````````"T";0)!084!0``````````````````````
-M````M`FT"10`%`4``````````"`H`````````````-`)K`H%!A0%````````
-M```````````````````("40)%``4!0``````````````````````````;`EL
-M"10`%`4``````````````````````````'$)@`D4`!0%````````````````
-M``````````"%"8H)%``4!0``````````````````````````CPF9"10`%`4`
-M`````````````````````````)X)G@D4`!0%````````````````````````
-M``"C":,)%``4!0````````````0``````(``````HPFC"10`%`4`````````
-M``````````"``````*@)J`D4`!0%````````````!```````@`````"H":@)
-M%``4!0```````````````````(``````M`FT"10`%`4````````````$````
-M``"``````+0)M`D4`!0%````````````````````@```````````"`E$"04&
-M%`4```````````````````````````@)1`D4`!0%````````````````````
-M``````!L":@)!084!0``````````````````````````;`FH"10`%`4`````
-M`````$```````````````&P)J`D>`!0%``````````````````````````!L
-M"9X)&P84!0``````````````````````````;`F>"10`%`4``````````$``
-M`````````````(`)B@D4`!0%``````````````````````````"9":@)%``4
-M!0``````````````````````````T`FL"@4&%`4`````````````````````
-M`````*,)J`D4`!0%```````````@(``````````````("40)%``4!0``````
-M````````````````````;`EL"10`%`4``````````````````````````'$)
-M@`D4`!0%``````````````````````````"%"8H)%``4!0``````````````
-M````````````CPF9"10`%`4``````````````````````````)X)G@D4`!0%
-M``````````````````````````"C":,)%``4!0````````````0``````(``
-M````HPFC"10`%`4```````````````````"``````*@)J`D4`!0%````````
-M````!```````@`````"H":@)%``4!0```````````````````(``````````
-M```````````````````````("40)!08H*```````````````````````````
-MA0F%"04&*"@``````````````````````````(4)A0D4!B@H````````````
-M``````````````"%"84)$@8H*`````````````0`````````````T`FL"@4&
-M*"@`````````````````````````````````````````````````````_P$0
-M``$```````````````````````````(`""```````````````/\`````````
-M````````````$20`````````````````!10```````````````````4"````
-M```````````````3````````````````````4`$0````````````````````
-M```````````````!````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````4`(0``````````````````````````````````0`````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````4`,0
-M````````````````````````````````$`@`````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````4`00````````````````````
-M`````````(```(``````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````4`40`````````````````````````````````$``````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````4`8P
-M``(``````````P```````````````(!``(`````````````````("0``````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````4`@P````````````````````
-M```#````````!``!````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````4`DP``(`````````!``````````#```````$(!``````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````,`$P
-M``(`````````!``````````#``````!`@```"```````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````,`(P``(`````````!```````
-M```#`````$``````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````,`,P``(`````````!``````````#``````!`````"```
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````,`0P
-M``(`````````!``````````#`````$`@````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````,`4P``(`````````!```````
-M```#`````!``````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````,`8P``(`````````!``````````#```````1``$`````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````$`$0
-M`````````````````````````````"```0`"```````````````$$@``````
-M````````````$2``````````````````````````````````````````````
-M````````````````````````````````````(`$0````````````````````
-M```````````"`@`$````````````````````````````````````$B``````
-M````````````````````````````````````````````````````````````
-M````````````````8`$0``$``````````P```````````````""`0``"````
-M``````````#$$```````````````````(00`````````````````````````
-M````````````````````````````````````````````````````````90$0
-M``$``````````P``````````````.```````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````0`%`````````````"```````
-M```"``````0`````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````0`)`````````````$``````````"````QP4`````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````0`-`
-M`````````````(`````````"`````(``````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````0`1```0``````````(``````
-M```"`````(!`````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````0`5```0``````````(`````````"`````(!```(`````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````0`9`
-M````````````"``````````"`````(@`````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````0`=```0`````````"(``````
-M```"`````(1`````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````0`A```0`````````"(`````````"`````(1```(`````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````0`E`
-M`````````````(`````````"````QX$`````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````0`M```0``````````(``````
-M```"````QX%`````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````4`W_````````````````````````````````````````
-M````````````````````````````````````````````````````"@``````
-M``````````````H`````````````````````````````````````````,`K_
-M````````````@``````````#````````````````````````````````````
-M``````````````````````````````````$````````````````````!````
-M```````````````$````````````````````,`LP``````````````$`````
-M```#````````````````````````````````````````````````````````
-M````````````@````````````````````(`````````````````````$````
-M````````````````,`PP``````````````(````````#````````````````
-M````````````````````````````````````````````````````$```````
-M`````````````!`````````````````````$````````````````````$`H0
-M````````````````````````````````````````````````````````````
-M````````````````````````````````(````````````````````"``````
-M```````````````$````````````````````0`I`````````````8'@`````
-M```"````````````````````````````````````````````````````````
-M````````````0`H``````````````````$`$```````````````````$````
-M````````````````4`I`````````````````````````````````````````
-M````````````````````````````````````````````````````"```````
-M``````````````@````````````````````$````````````````````F0$P
-M````````````````````````````````````````````````````````````
-M````````````````````````````````"`````````````````````@`````
-M```````````````$````````````````````8`#_``,```````````0`````
-M```(``````````#@`P``````````````P`(`````````````````````````
-M`````````````,"O``````````````````#P"P`````````````````(````
-M````````````````9@#_``,```````````0````````(``````````#@`P``
-M````````````P`(``````````````````````````````````````,`'````
-M``````````````#P`0`````````````````(````````````````````9P#_
-M``,```````````0````````(``````````#@`P``````````````P`(`````
-M`````````````````````````````````,`O``````````````````#P"P``
-M```````````````(````````````````````:`#_``,```````````0`````
-M```(``````````#@`P``````````````P`(`````````````````````````
-M`````````````,!7``````````````````#P%0`````````````````(````
-M````````````````80#_``,```````````0````````0``````````#@`P``
-M`````````````````````````````````````````````````````,"O````
-M``````````````#P"P`````````````````(````````````````````8@#_
-M``,```````````0````````0``````````#@`P``````````````P`(`````
-M`````````````````````````````````,"O``````````````````#P"P``
-M```````````````(````````````````````8P#_``,```````````0`````
-M```(``````````#@`0``````````````P`(`````````````````````````
-M`````````````,`O``````````````````#P"P`````````````````(````
-M````````````````9`#_``,```````````0````````0``````````@`'```
-M````````````P`(``````````````````````````````````````,`'````
-M``````````````#P`0`````````````````(````````````````````90#_
-M``,```````````0````````0``````````"$"```````````````````````
-M`````````````````````````````````,!7``````````````````#P%0``
-M```````````````(````````````````````:0#_``,```````````0`````
-M```0``````````#``P``````````````P`(`````````````````````````
-M`````````````,`'``````````````````#P`0`````````````````(````
-M````````````````:@#_``,```````````0````````0``````````#``P``
-M`````````````````````````````````````````````````````,`O````
-M``````````````#P"P`````````````````(````````````````````F`'_
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````!``/``\P"(@?``
-M\P!!`(``@P")@8``@P!(`/(`]0"*@?(`]0!#`/8`]P"+@?8`]P!*`/$`]`",
-M@?$`]`!+`($`A`"-@8$`A`!,`((`A0"/@8(`A0````````````````"(`?``
-M\P")`8``@P"*`?(`]0"+`?8`]P",`?$`]`"-`8$`A`"/`8(`A0``````````
-M````````````````````"```````````````````````````````````````
-M`````````0)P%PL`C````````0(H(P\`$@```````0+@+@H`F`(``````0)0
-M1@X`)`(``````0+`70D`L`0``````0*@C`T`2`0``````0*`NP@`8`0`````
-M`0+PT@P`;`0`````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````@`````````````````````````````````````````
-M``````$#<!<+`(P```````$#*",/`!(```````$#X"X*`)@"``````$#4$8.
-M`"0"``````$#P%T)`+`$``````$#H(P-`$@$``````$#@+L(`&`$``````$#
-M\-(,`&P$````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````(````````````````````````````````````````````
-M```!`G`7"P",```````!`B@C#P`2```````!`N`N"@"8`@`````!`E!&#@`D
-M`@`````!`L!="0"P!``````!`J",#0!(!``````!`H"["`!@!``````!`O#2
-M#`!L!```````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````"```````````````````````````````````````````````
-M`0-P%PL`C````````0,H(P\`$@```````0/@+@H`F`(``````0-01@X`)`(`
-M`````0/`70D`L`0``````0.@C`T`2`0``````0.`NP@`8`0``````0/PT@P`
-M;`0`````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````0```````````````````````````````````````````````$`
-MZ`,+`((```````$`T`<*!(0!``````$`?!4)!(L!``````$`^"H(!)8!````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````$H@`````````````(H@``1D8^4$9&/E`,H@``;$&`9&Q!@&00H@``
-M`Z"9`0.@F0$4H@``$-9,!!#63`08H@``0`"`$T``@!,<H@``8`#@&V``X!L@
-MH@``"H!3#`J`4PPDH@``.]\4`#O?%``HH@``M0$``+4!```LH@``(````"``
-M``"<F`````````````"<F`````````````"<F`````````````"<F```````
-M``````"<F`````````````"<F`````````````"<F`````````````"<F```
-M``````````"<F`````````````"<F`````````````"<F`````````````"<
-MF``````X````.`"<F`````````````"<F`````````````"<F```````````
-M``"<F```^0`$`/D`!`#4F`````````0`````````````````````````G)@`
-M````````````G)@`````````````G)@`````````````G)@`````````````
-MG)@`````````````G)@``````!`````0G)@```````0````$G)@`````````
-M````G)@`````````````G)@`````````````G)@````````````*G)@``(``
-M.`"``#@"G)@```8``@`&````G)@``)(```"2````G)@``*````"@````G)@`
-M``<`!``'``0`U)@``!H````:````G)@``$@```!(````G)@``!`````0````
-MG)@```@````(````G)@```\````/````G)@``/(```!B````G)@``$^0``!,
-MD```G)@``%H2``":$@``S)@```X````/````````````````````````````
-M```(```````````````````````````````````````````````!`G`7"P",
-M```````!`B@C#P`2```````!`N`N"@"8`@`````!`E!&#@`D`@`````!`L!=
-M"0"P!``````!`J",#0!(!``````!`H"["`!@!``````!`O#2#`!L!```````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M"````````````````````````````````````````````````0*X"PL`A@``
-M`````0*4$0\`"0```````0)P%PH`C`(``````0(H(PX`$@(``````0+@+@D`
-MF`0``````0)01@T`)`0``````0+`70@`,`0``````0)X:0P`-@0`````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````````````````@`
-M``````````````````````````````````````````````$"W`4+`(,`````
-M``$"R@@/``0```````$"N`L*`(8"``````$"E!$.``D"``````$"<!<)`(P$
-M``````$"*",-`!($``````$"X"X(`!@$``````$"O#0,`!L$````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````````````````````````````````````````'````
-M```````````````````````````````````````````!`W`7"P",```````!
-M`^`N"@"8`@`````!`U!&#@`D`@`````!`\!="0"P`P`````!`Z",#0!(`P``
-M```!`X"["`!@`P`````!`_#2#`!L`P``````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````"```````
-M`````````````````````````````````````````0-P%PL`C````````0,H
-M(P\`$@```````0/@+@H`F`(``````0-01@X`)`(``````0/`70D`L`0`````
-M`0.@C`T`2`0``````0.`NP@`8`0``````0/PT@P`;`0`````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````````````0`````````
-M``````````````````````````````````````$`Z`,;`((```````$`T`<:
-M!(0!``````$`?!49!(L!``````$`^"H8!)8!````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M```````````````````````````````````````````````,````````````
-M```````````````````````````````````!`.@#&P""```````!`-`'&@2$
-M`0`````!`'P5&02+`@`````!`/@J&`26`P```````G`7"P`,!````````B@C
-M#P`2!``````!`N`N"@`8!@`````!`E!&#@`D!@`````!`L!="0`P"``````!
-M`J",#0!("``````!`H"["`!@"``````!`O#2#`!L"```````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````#0``````````````
-M`````````````````````````````````03Z``,`@0!D`F0"`03T`0<`@0#)
-M`<D!`03H`P(`@@'D`.0``030!P8`A`*@`*```02X"P$`A@.,`(P``0)P%PL`
-MC`0\`#P``0(H(P\`$@0\`#P``0+@+@H`F`8P`#```0)01@X`)`8P`#```0+`
-M70D`,`@L`"P``0*@C`T`2`@L`"P``0*`NP@`8`@L`"P``0+PT@P`;`@L`"P`
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M````````````````````````````````````````````````````````````
-M``````````````````````````````````````````!'0T,Z("A'3E4I(#,N
-M-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E
-M94)31%T@,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R965"4T1=(#(P
-M,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```
-M1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U,3@``$=#0SH@*$=.
-M52D@,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT
-M(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)3
-M1%T@,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R965"4T1=(#(P,#4P
-M-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#
-M.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U,3@``$=#0SH@*$=.52D@
-M,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&
-M<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@
-M,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X
-M``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H
-M1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT
-M+C0@6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E
-M0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P
-M-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X``!'
-M0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5
-M*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@
-M6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$
-M72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U
-M,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z
-M("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S
-M+C0N-"!;1G)E94)31%T@,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R
-M965"4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R
-M,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U,3@`
-M`$=#0SH@*$=.52D@,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z("A'
-M3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N
-M-"!;1G)E94)31%T@,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R965"
-M4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U
-M,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U,3@``$=#
-M0SH@*$=.52D@,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I
-M(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;
-M1G)E94)31%T@,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R965"4T1=
-M(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q
-M.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U,3@``$=#0SH@
-M*$=.52D@,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N
-M-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```1T-#.B`H1TY5*2`S+C0N-"!;1G)E
-M94)31%T@,C`P-3`U,3@``$=#0SH@*$=.52D@,RXT+C0@6T9R965"4T1=(#(P
-M,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT(%M&<F5E0E-$72`R,#`U,#4Q.```
-M1T-#.B`H1TY5*2`S+C0N-"!;1G)E94)31%T@,C`P-3`U,3@``$=#0SH@*$=.
-M52D@,RXT+C0@6T9R965"4T1=(#(P,#4P-3$X``!'0T,Z("A'3E4I(#,N-"XT
-M(%M&<F5E0E-$72`R,#`U,#4Q.```+G-Y;71A8@`N<W1R=&%B`"YS:'-T<G1A
-M8@`N<F5L+G1E>'0`+G)E;"YR;V1A=&$`+G)O9&%T82YS='(Q+C$`+G)E;"YD
-M871A`"YB<W,`+F-O;6UE;G0`````````````````````````````````````
-M`````````````````!\````!````!@`````````T````;+`!````````````
-M!``````````;````"0``````````````C,("`&@;```+`````0````0````(
-M````*0````$````"`````````*"P`0!(B0`````````````@`````````"4`
-M```)``````````````#TW0(`6`X```L````#````!`````@````Q`````0``
-M`#(`````````Z#D"`-X```````````````$````!````1`````$````#````
-M`````.`Z`@"$4@`````````````@`````````$`````)``````````````!,
-M[`(`.`````L````&````!`````@```!*````"`````,`````````@(T"`+`!
-M`````````````"``````````3P````$``````````````("-`@"$!P``````
-M```````!`````````!$````#```````````````$E0(`6```````````````
-M`0`````````!`````@``````````````9)<"`&`9```,````!P````0````0
-M````"0````,``````````````,2P`@#%$0`````````````!````````````
-M```````````````````````````````````#``$``````````````````P`#
-M``````````````````,`!0`````````````````#``8`````````````````
-M`P`(``````````````````,`"0`!````%(X``'X````2``$`#````*Q^```&
-M````$@`!`!<```#,_0``QP$``!(``0`B````>&0``'0````2``$`+0```"P3
-M`0`F`@``$@`!`#@```#,T@``-0```!(``0!#````V!T!`$@!```2``$`3@``
-M`$A:``#P````$@`!`%D```!D60$`Y````!(``0!D````0#D``*0!```1``8`
-M;P```-`"`0`C````$@`!`'H```!@7```+P```!(``0"%````R$X``-\````2
-M``$`D````.!)``"D`0``$0`&`)L```"(]P``)0```!(``0"F````9/,``!,`
-M```2``$`L0```)SI```,````$@`!`+P````(T@``O@```!(``0#'````<-T`
-M`.4````2``$`T@```,@*``":````$@`!`-T```"DQ@``D@```!(``0#H````
-MY*\``*`````2``$`\P```+29``!4````$@`!`/X```#8G0``"P```!(``0`)
-M`0``@((``"4````2``$`%`$``,3Z```L````$@`!`!\!``"0T0``!@```!(`
-M`0`J`0``_.8``!<````2``$`-0$``%05`0![````$@`!`$`!``"<!P``2```
-M`!(``0!+`0``E-0``.8````2``$`5@$``$21```&````$@`!`&$!``#<2@$`
-M=0```!(``0!L`0``:(4```8````2``$`=P$``.2=```/````$@`!`((!``"8
-M#@``0@$``!(``0"=`0``H$0``*0!```1``8`J`$``&ST``!T````$@`!`+,!
-M``!T@P``;@```!(``0"^`0``%`,``"P````2``$`R0$``-1,`0!8````$@`!
-M`-0!`````````````!````#U`0``F&$``$$````2``$```(``$SV```D`0``
-M$@`!``L"```$]@``2````!(``0`6`@``0,D``)8````2``$`(0(``)!C```D
-M````$@`!`"P"``",E@``2````!(``0`W`@``")H``'@````2``$`0@(``!3*
-M```Y````$@`!`$T"``"8E```%P```!(``0!8`@``%/4``%0````2``$`8P(`
-M`'R%``!A````$@`!`&X"``#88```,P```!(``0!Y`@``\'X``#D````2``$`
-MA`(``*SO``!T````$@`!`(\"``!\FP``2@```!(``0":`@``X/0``"`````2
-M``$`I0(``.SS``!@````$@`!`+`"``",TP``5P```!(``0"[`@``Y!4!`#<`
-M```2``$`Q@(``%A<```&````$@`!`-$"``!H]0``>````!(``0#<`@``S%(`
-M`.`%```2``$`YP(```R;```R````$@`!`/("``#(\0``,0```!(``0#]`@``
-MP`(``%,````2``$`"`,``$ST```@````$@`!`!,#``",.@$`"@$``!(``0`>
-M`P``%.8``"P````2``$`*0,``*0<`0!_````$@`!`#0#```\8P``&0```!(`
-M`0`_`P``?)$``)L````2``$`2@,``("5``!;````$@`!`%4#``#X?0``(0``
-M`!(``0!@`P``($`!`(@````2``$`:P,``,AS```>`@``$@`!`'8#```D9@``
-M`0```!(``0"!`P``J$`!`$@````2``$`C`,``$B````U`@``$@`!`)<#``!0
-M`0``60$``!(``0"F`P``%"L!``8#```2``$`L0,``%0!`0#T````$@`!`+P#
-M``#4F@``$0```!(``0#'`P``\#T!`(0!```2``$`T@,``-3Y``#O````$@`!
-M`-T#``!4`@$`#P```!(``0#H`P``K`(``!0````2``$`\P,``+"7```.````
-M$@`!`/X#``!0R@``TP```!(``0`)!```V,D``#D````2``$`%`0``'2I``!3
-M````$@`!`!\$``"L6```$````!(``0`J!```6&,``#<````2``$`-00``$`#
-M``#$`0``$@`!`$L$``"P&P$`(0```!(``0!6!```X(4``)H````2``$`800`
-M`%AD```@````$@`!`&P$``#`CP``%@```!(``0!W!```T!4!`!(````2``$`
-M@@0``,RW```J````$@`!`(T$``!@ZP``[@,``!(``0"8!```B.@```L````2
-M``$`HP0``"Q=``"(````$@`!`*X$``"4C@``.````!(``0"Y!```0$\!`#T`
-M```2``$`Q`0``-SI``#X````$@`!`,\$``"XF@```0```!(``0#:!```,&$`
-M`&4````2``$`Y00``"S)```4````$@`!`/`$``#`U0``5`<``!(``0#[!```
-M2#T!`*8````2``$`!@4``%SS```&````$@`!`!$%``!TE```(0```!(``0`<
-M!0``;`,!`%<````2``$`)P4``*1^```&````$@`!`#(%```<20$`/0$``!(`
-M`0`]!0``5)\``$4````2``$`2`4``#1@```_````$@`!`%,%``#@]0``(P``
-M`!(``0!>!0``%-T``%L````2``$`:04``!C0```?````$@`!`'0%```L30$`
-M/@```!(``0!_!0`````````````0````C`4``.A_``!@````$@`!`)<%``!<
-M:@``10```!(``0"B!0``T$H!``P````2``$`K04``-1-`0`+````$@`!`+@%
-M```P\@``=P```!(``0##!0``8`4```@"```2``$`U`4``'!#`0"J`P``$@`!
-M`-\%``"T8P``1````!(``0#J!0``&(0``(\````2``$`]04``*R:```!````
-M$@`!```&``!X\P``$0```!(``0`+!@``2%H!`'$````2``$`%@8``-1I``!7
-M````$@`!`"$&```$XP``B0```!(``0`L!@``3)$``"\````2``$`-P8``("K
-M``!<`0``$@`!`$(&```<?@``AP```!(``0!-!@``Z",!`#T&```2``$`6`8`
-M`$0$`0`X````$@`!`&,&``"4_P``+````!(``0!N!@``G)\``.4````2``$`
-M>08``+#W```C`@``$@`!`(0&``"0F```7````!(``0"/!@``P)H``!,````2
-M``$`F@8``/#Z``#<`@``$@`!`*4&```X00$`3`$``!(``0"P!@``@$\!`#P%
-M```2``$`NP8``$";```Z````$@`!`,8&``"`A@``#@```!(``0#1!@``O%L`
-M``L````2``$`W`8``,R.``#S````$@`!`.<&```@\0``)P```!(``0#R!@``
-MO&8``"0````2``$`_08``)":`0#:````$@`!``@'```89@```0```!(``0`3
-M!P``I/,```L````2``$`'@<``.#R```X````$@`!`"D'``!@30``I`$``!$`
-M!@`T!P``F-```&4````2``$`/P<``-1=`0!.````$@`!`$H'```@90``5```
-M`!(``0!5!P``])T```\````2``$`8`<``*1J```M`0``$@`!`&L'```,$P$`
-M'@```!(``0!V!P``;.\``"$````2``$`@0<``$CQ``"`````$@`!`(P'````
-M3@$`/@$``!(``0"7!P``>'(``!0````2``$`H@<``+QH```/````$@`!`*T'
-M``!`8@``M@```!(``0"X!P``/&H``!T````2``$`PP<``+CP``!H````$@`!
-M`,X'``!,&`$`QP(``!(``0#9!P``M$<!`&<!```2``$`Y`<``,`\``"D`0``
-M$0`&`.\'``"T70``C`$``!(``0#Z!P``'$(``%,````2``$`!0@``+1^```Y
-M````$@`!`!`(```L:@``#@```!(``0`;"``````````````0````.P@``-1K
-M````!@``$@`!`$8(````````"0```!$`!@!6"```(!\!`(0````2``$`80@`
-M`-R5```J````$@`!`&P(``"0KP$`V@```!(``0!W"```6-X``%X````2``$`
-M@@@```SR```B````$@`!`(T(```H9@```0```!(``0"8"```/!P!`&8````2
-M``$`HP@``+":```&````$@`!`*X(``!DG0``%@```!(``0"Y"```&)(``(@`
-M```2``$`Q`@``+#S```R````$@`!`,\(`````````````!````#>"```-)8`
-M`#,````2``$`Z0@``*!+``"D`0``$0`&`/0(```\`0$`%@```!(``0#_"```
-M%.0``#@````2``$`"@D``(2P``!1````$@`!`!4)``!D<@``%````!(``0`@
-M"0``#)D``'0````2``$`*PD``)3H```'`0``$@`!`#8)``!@1@``I`$``!$`
-M!@!!"0``</<``!<````2``$`3`D``'R7```Q````$@`!`%<)``#L`P$`5@``
-M`!(``0!B"0``@%<!`.0!```2``$`;0D``*"2``"X`0``$@`!`'@)``!$:0``
-M%P```!(``0"#"0``%)4``#L````2``$`C@D``%BT```>`0``$@`!`)D)```<
-M>```'P```!(``0"D"0``%`,!`%<````2``$`KPD``"!(``"D`0``$0`&`+H)
-M```(E@``+````!(``0#%"0``_)8``(`````2``$`T`D``/AB```Q````$@`!
-M`-L)```T1P$`'P```!(``0#F"0`````````````0````]0D``)C1```,````
-M$@`!```*``"0[P``'````!(``0`+"@``7%\``"$````2``$`%@H```#U```2
-M````$@`!`"$*``"DF@``!@```!(``0`L"@``7/```%D````2``$`-PH``(`^
-M``"D`0``$0`&`$(*```PGP``#@```!(``0!-"@``V(\``+H````2``$`6`H`
-M`!P!```S````$@`!`&8*````.P``I`$``!$`!@!Q"@``V)X``%<````2``$`
-M?`H``)20```+````$@`!`(<*```@````(````!$`!@"9"@``W&$``!L````2
-M``$`I`H``#1B```,````$@`!`*\*``"HZ0``,@```!(``0"Z"@``[&<``&@`
-M```2``$`Q0H``/Q;`0#8`0``$@`!`-`*``!4:```%@```!(``0#;"@``H)D`
-M`!(````2``$`Y@H``*`"`0`P````$@`!`/$*``#$30``R0```!(``0#\"@``
-M'$<!`!8````2``$`!PL``(">``!7````$@`!`!(+``"`F@``(P```!(``0`=
-M"P``=`(!`"D````2``$`*`L``#C0```>````$@`!`#,+``#P0`$`2````!(`
-M`0`^"P``@)D``"`````2``$`20L``"@J`0"U````$@`!`%0+``"@D```H@``
-M`!(``0!?"P``I-$``&$````2``$`:@L``$!```"D`0``$0`&`'4+```L:0``
-M%P```!(``0"`"P``X$T!`"`````2``$`BPL``%!;``!I````$@`!`)8+``!L
-M:```0P```!(``0"A"P``!,P``/D#```2``$`K`L``&!F``!;````$@`!`+<+
-M```,90``$@```!(``0#""P``3.0``$`!```2``$`S0L``'0_`0"I````$@`!
-M`-@+``!`GP``$@```!(``0#C"P``D$X``#<````2``$`[@L``)CF``!B````
-M$@`!`/D+``#,#0``;P```!(``0`$#```<`@``%<"```2``$`#PP``.CE```J
-M````$@`!`!H,``!T90``>````!(``0`E#```L&@```L````2``$`,`P``.PX
-M`0!V````$@`!`#L,``"L8```+````!(``0!&#```X"H!`#0````2``$`40P`
-M`,P_```L````$@`!`%P,```$!0``6@```!(``0!G#```(/```#L````2``$`
-M<@P`````````````$````((,``#XMP``A`$``!(``0"-#```.%L``!8````2
-M``$`F`P``%Q*`0!T````$@`!`*,,```,80``)````!(``0"N#```U.H``(P`
-M```2``$`N0P``$R8``!$````$@`!`,0,````T0``C@```!(``0#/#```````
-M```````0````[PP``.0'``"*````$@`!`/H,``"@7P``30```!(``0`%#0``
-M\%\``#L````2``$`$`T``%"5```O````$@`!`!L-``"07```FP```!(``0`F
-M#0``U)8``"<````2``$`,0T``+C>```3!```$@`!`#P-``#HF@``%0```!(`
-M`0!'#0``?`0!`"$!```2``$`4@T``!!F```&````$@`!`%T-``!`7P``'```
-M`!(``0!H#0``+&(```8````2``$`<PT`````````````$````($-``!8E```
-M'````!(``0",#0``R`L``+L````2``$`EPT``"QF```R````$@`!`*(-``!@
-MG@``'P```!(``0"M#0``R)L``"P````2``$`N`T```!S``#(````$@`!`,,-
-M``!<:0``'P```!(``0#.#0``^&$``#0````2``$`V0T``%#O```<````$@`!
-M`.0-``!D`@$`#P```!(``0#O#0``I!(!`&<````2``$`^@T``&B6```D````
-M$@`!``4.``!TY@``)````!(``0`0#@``I!\!`$,$```2``$`&PX``"QC```.
-M````$@`!`"8.``!\G0``6P```!(``0`Q#@``P)<``!D````2``$`/`X``*B$
-M``#`````$@`!`$<.``"XE```60```!(``0!2#@``O)H```$````2``$`70X`
-M`"Q_``"[````$@`!`&@.```@3P``I`$``!$`!@!S#@``F%\```8````2``$`
-M?@X``+"4```&````$@`!`(D.```06@``.````!(``0"4#@``R%L``(X````2
-M``$`GPX``$#F```S````$@`!`*H.```\#@``60```!(``0"U#@``N$P!`!L`
-M```2``$`P`X``.3S```&````$@`!`,L.```4F```.````!(``0#6#@``'#@!
-M`,T````2``$`X0X``/R<``!H````$@`!`.P.``"$H```VP@``!(``0#W#@``
-MX%```*0!```1``8``@\``.CB```<````$@`!``T/``!T8```-0```!(``0`8
-M#P``:`<``#(````2``$`(P\``(!?```7````$@`!`"X/``!42P$`8P$``!(`
-M`0`Y#P``^$(!`'8````2``$`1`\``,QH```/````$@`!`$\/``#LF```(```
-M`!(``0!:#P``2`(!``L````2``$`90\``-QH``!-````$@`!`'`/``!860``
-M1@```!(``0![#P``[&0``"`````2``$`A@\``'2+```B````$@`!`)$/``"$
-M#```1P$``!(``0"<#P``R-(```$````2``$`IP\``*B"``!*````$@`!`+(/
-M```PG@``%P```!(``0"]#P``'&8```8````2``$`R`\``)C+``!K````$@`!
-M`-,/``#T`@$`'P```!(``0#>#P``M&T!`+H````2``$`Z0\``.QE```C````
-M$@`!`/0/``"H3P``)P```!(``0#_#P``@$8``$$'```2``$`%1```,0#`0`G
-M````$@`!`"`0``!\:0``5P```!(``0`K$```H`4!``(-```2``$`-A```!3G
-M``!S`0``$@`!`$$0``!8T```/0```!(``0!,$```2)X``!<````2``$`5Q``
-M`/2"``!]````$@`!`&(0``!0/P``?````!(``0!M$```<(4```P````2``$`
-M>!```(QR``!S````$@`!`(,0```$G@``*0```!(``0".$```8*D``!(````2
-M``$`F1```*!9``!M````$@`!`*00``!\A@```0```!(``0"O$```^&,``&``
-M```2``$`NA```+C%```_````$@`!`,40``#4``$`:````!(``0#0$```&/,`
-M`$0````2``$`VQ```-R7```W````$@`!`.80``#HA@``B@0``!(``0#Q$```
-MX'H``+D"```2``$`_!```(SS```5````$@`!``<1````T```%@```!(``0`2
-M$0``3(<!`,(````2``$`'1$``*CR```W````$@`!`"@1``",Y0``60```!(`
-M`0`S$0``'!8!`"X"```2``$`/A$``%1'`0`>````$@`!`$D1``#,C0``1@``
-M`!(``0!4$0``D.,``(,````2``$`7Q$``"Q@```&````$@`!`&H1````FP``
-M"P```!(``0!U$0``Y(,``#,````2``$`@!$``/SQ```.````$@`!`(L1``!`
-M,P$`XP```!(``0"6$0``R*D``+@!```2``$`H1$``+A!``!A````$@`!`+H1
-M``!T1P$`/0```!(``0``>GHP,#5B-3@T-@!Z>C`P,F1B,3%C`'IZ,#)D8F8X
-M-S4`>GHP,F1B8C%B,@!Z>C`R9&(R,#4S`'IZ,#`R9&)A-#(`>GHP9F)B,64S
-M9@!Z>C!B-SEE83DT`'IZ,#5B.&,V-6$`>GHP,#5B-#!A9`!Z>C`U8CDT,F5D
-M`'IZ,&0X9&,V,F,`>GHP,#$Y9C0W,`!Z>C`R9&0Y-#)D`'IZ,#)D8F4W,V0`
-M>GHP,#5B-CDR8@!Z>C!B-F0R,S(U`'IZ,#`U8C@U,V0`>GHP,#$V9#DR90!Z
-M>C!C9F(Q.#<U`'IZ,#`R9&(S,6,`>GHP,F1A8F)A8P!Z>C`R9&)C.#4Q`'IZ
-M,#`P8C9C-C@`>GHP,#!B-F)F.`!Z>C`P8C9C9C5E`'IZ,#$V93%D9F0`>GHP
-M8C9F-3!B.`!Z>C`V93!A-&9E`'IZ,#`V-V0R8C$`>GHP,#)D8F,V,0!Z>C!B
-M-F-A,S(U`'IZ,#`U8C9C9F0`>GHP,39E,&1F9`!Z>C`P,&(V9C8X`&%T:%]H
-M86Q?<')O8V5S<U]N;VES969L;V]R`'IZ,#`U8C0X860`>GHP,F1B9C%B,@!Z
-M>C`P-6(X.&-B`'IZ,#,S96,X8F8`>GHP9&(T,C5C-0!A=&A?:&%L7V1M85]B
-M96%C;VY?<F5S<&]N<V5?=&EM90!Z>C`P8C9F,38Q`'IZ,#9E,#!B.&$`>GHP
-M,F1B9F,Q9`!Z>C!D8S1E,SDP`'IZ,&1A9F5D.#8`>GHP,&(V93(W80!Z>C`R
-M9&)B86(R`'IZ,&(V9#%E9F8`>GHP,39D.3!D9`!Z>C`R9&)E.#4Q`'IZ,#`U
-M8C8T9F0`>GHP,#!B-F0U,@!Z>C!B-F,Y969F`'IZ,#$V93`P9&0`>GHP,F1B
-M9#@W-0!Z>C`R9&(S,6(R`'IZ,#!B-S`Y,C,`>GHP,&(V9#0U,`!Z>C`P,&(V
-M9#%D`'IZ,&(V8S(S,C4`>GHP,F1B9&%B,@!Z>C`P,#5B-C,R`'IZ,#9D961D
-M.3,`>GHP,#$V9&$U,`!Z>C`P,#8W9#,R`'IZ,#!B-F0Y,C,`>GHP,#)D8C4Q
-M8P!Z>C`Q-F1C8F9E`'IZ,#!B-S`Q-#4`>GHP,#$V9&8R8P!Z>C!B-V9A9#-E
-M`'IZ,#$V9#DY,C``>GHP,F1B,6)A8P!Z>C!D8S9E,SDP`'IZ,#5B-S`Q93``
-M>GHP,#!B-F(Q,`!Z>C!B-S`Y969F`'IZ,#$V9&8X.6(`871H7VAA;%]A='1A
-M8V@`>GHP-F4P9F,P9`!Z>C`Q-F1A8C)D`'IZ,#)D8C$S-60`>GHP93`T-C@T
-M8@!Z>C`Q-F4R.3%D`'IZ,#`P8C9F93@`>GHP,&-F8C-E,`!Z>C`P,39D.30X
-M`'IZ,#$V93(P.6(`>GHP8C<P,65F9@!Z>C`P,&(V8SED`'IZ,#`P-6(U83(`
-M>GHP,F1B,3<P80!A=&A?:&%L7V-O;7!U=&5T>'1I;64`>GHP,F1B-6)A8P!Z
-M>C`P-6(X,3-D`'IZ,#!B-F,Y,C,`>GHP8C9B-3!B.`!Z>C`P-6(W9CED`'IZ
-M,&(W,#%D,#(`>GHP-F1F9C0T80!Z>C`R9&(U-S8S`'IZ,#9E96%F-C``>GHP
-M93`P-V-A,0!Z>C`P,F1A9C8R`'IZ,&(X,V%D,V4`>GHP,#!B-F(Y,`!Z>C`Q
-M-F0Y969A`'IZ,#$V9&4P-3$`>GHP,#`U8C9B,@!Z>C`U8C=F,3$T`'IZ,#1A
-M93`S,68`>GHP,F1B9&1F9`!Z>C`P-30W9F5D`'IZ,#!B-F)F-64`>GHP,&(W
-M,3<W9`!Z>C`P8C<P9C-D`'IZ,#$V9#@Y,C``>GHP,F1B,6%B,@!Z>C`P,#5B
-M-C(R`'IZ,#`P8C9F-S@`>GHP8C8Y8C`W8P!A=&A?:&%L7V9R964`>GHP-6(W
-M.6(Q8@!Z>C`P8C<P-S-D`'IZ,#)D8F5B8F0`>GHP8C5E,S$U,@!Z>C`Q-F1F
-M8F8Q`&%T:%]H86Q?;6AZ,FEE964`>GHP,39E,3@Y8@!Z>C!D8S)A-6,U`'IZ
-M,#`R9&,V,&(`>GHP-F1F,&(X80!Z>C`R9&(S,S5D`'IZ,&(V8S4S830`>GHP
-M9C4T9#%B,`!Z>C!B-F9D,S8S`'IZ,&0Y9&,V,F,`>GHP-6(W-#%E,`!Z>C`R
-M9&$Y8F%C`'IZ,&1C,C%D,V$`>GHP,&(W,3<S9`!Z>C`Q-F0Y9#0Q`'IZ,#`U
-M8C@T9F0`>GHP,#5B.&%B9`!Z>C`P8C<P,3(S`'IZ,#`U8C8U,F(`>GHP,F1B
-M,S@W-0!Z>C`Q-F4S,#EB`'IZ,#`U8C8P8C(`>GHP,F1B,3@W-0!Z>C`P,F1B
-M.#0R`'IZ,#)D8C$W-C,`>GHP8C=D96$Y-`!Z>C`P8C<P,38Q`'IZ,#$V9#=D
-M-#$`>GHP,#$V8V0S,@!Z>C`V9&4P8CAA`'IZ,#9D.61D.3,`>GHP9&(S960X
-M-@!Z>C`P-6(T.&5D`'IZ,#`R9&,X,&(`>GHP,#)D8F,T,@!Z>C`R9&)A.#4Q
-M`'IZ,#)D8C,S960`>GHP,#5B.#!F9`!Z>C`P-6(W9C)E`'IZ,#)D8F9D9F0`
-M>GHP,39E-C0X80!Z>C`P,F1A9F8R`'IZ,#`U8C<W.60`>GHP,#!B-F5E.`!Z
-M>C`Q-F4T-#AA`'IZ,#!B-F8V8F,`>GHP,39D83DR,`!Z>C`U8C<X,64P`'IZ
-M,#`R9&-A,&(`>GHP,#5B-#1A9`!Z>C`V9&1F-#1A`'IZ,&9A8S!C.6(`>GHP
-M8C9F.65F9@!Z>C`P8C9C-F)C`&%T:%]H86Q?861D:71I;VYA;%]S=V)A7V)A
-M8VMO9F8`>GHP,#`R9&(Y,@!A=&A?:&%L7W9E<G-I;VX`>GHP,F1B86,R90!Z
-M>C`R9&(W.6%E`'IZ,#`Q-F4U,S(`>GHP8C9C9C`P.0!Z>C`P,39E,3)C`'IZ
-M,#`Q-F0Y930`>GHP,#`R9&%E80!Z>C`P-6(U8V(R`'IZ,#$V9&$R-3$`>GHP
-M-F8V868V,`!Z>C`V9&9D9#DS`&%T:%]H86Q?;6%L;&]C`'IZ,#`P8C9D9#(`
-M>GHP,F1D.3)A9`!Z>C`Q-F1B,C4Q`'IZ,&4Q,#=C83$`>GHP,&(V8S<U90!Z
-M>C`Q-F1D,#4Q`'IZ,#)D8F0Q8C(`>GHP,F1C,3<V,P!Z>C!B-CDP9#9D`'IZ
-M,#$V9&8P-3$`>GHP,#$V9#DU,`!Z>C`P8C<P-F)C`'IZ,#`Q-F0X-S(`>GHP
-M-F1E9C0T80!Z>C`U8CAC,F5D`'IZ,#9F8CDT-V(`>GHP96)B,64S9@!Z>C!B
-M-F8Y9#`R`'IZ,&0Q-&0Q8C``>GHP8C0X,#,Q90!Z>C`Q-F1B8F9E`'IZ,#$V
-M934T.&$`>GHP,#$V9#@U,`!Z>C`P,&(V9F8X`&%T:%]H86Q?;65M8W!Y`'IZ
-M,#)D8F-B8F0`>GHP,39D83!D9`!Z>C`R9&)B9&9D`'IZ,#)D8C(X-3$`>GHP
-M,F1B9&,Q9`!Z>C`V9&(P8V8R`'IZ,#$V96(Y860`>GHP,&(V8V5B8P!Z>C!D
-M.30X-&$Q`&%T:%]H86Q?<')O8F4`>GHP,39E83EA9`!Z>C!F9#1D,6(P`'IZ
-M,#)D8C,W-C,`871H7VAA;%]B=6EL9&]P=',`>GHP,F1A9C,U9`!Z>C`V9&1D
-M9#DS`'IZ,&1A9&,V,F,`>GHP,39D9C(U,0!Z>C`P,&(V8S$P`'IZ,#$V9#DR
-M-3$`>GHP,F1B,#@U,0!Z>C!B-S(Q865D`'IZ,#8W8V9C864`>GHP,#!B-F-F
-M.`!Z>C!C.31D,6(P`'IZ,#)D869A8C(`>GHP-6(Y,F%E9`!Z>C`P-6(X8V-B
-M`'IZ,&(V9#EE9F8`>GHP,F1B,3%B,@!Z>C`R9&)F9F(Q`'IZ,#)D8F8W-C,`
-M>GHP,#5B-CAF9`!Z>C`P-6(T-&5D`'IZ,&(W,3%A960`>GHP8C5E,S$V,`!Z
-M>C!D.#0X-&$Q`'IZ,#$V9#AB,F0`>GHP,39E,#@Y8@!Z>C`R9&)B.#<U`'IZ
-M,#)D864X-3$`>GHP8C@Q96$Y-`!Z>C`Q-F1E8S%F`'IZ,#!B-F9E8F,`>GHP
-M93@Y-#DP-P!Z>C`P8C9E83=A`'IZ,#,S93AF8F8`>GHP8V9A-3@W-0!Z>C`R
-M9&(Y.6%E`'IZ,#)D8CEA8C(`>GHP,#!B-F)E.`!Z>C!D938X,S=F`'IZ,#$V
-M9&%B9F4`>GHP8C<P.60P,@!Z>C`V-V0R-64R`'IZ,#$Y9C-A,#$`>GHP-S`S
-M.30W8@!A=&A?:&%L7VUE;7IE<F\`>GHP-F1F9F,P9`!Z>C!B-C<U,&(X`'IZ
-M,#$V93)D9F0`>GHP,#!B-F0R,@!Z>C`V9F5A9C8P`'IZ,&1C-&$U8S4`>GHP
-M,&(W,&8W9`!A=&A?:&%L7W-W7V)E86-O;E]R97-P;VYS95]T:6UE`'IZ,#EF
-M-C1B-F$`>GHP,#5B-C4W80!Z>C`V9C,Y-#=B`'IZ,#9D83!C9C(`>GHP8C=B
-M860S90!Z>C`P8C9F.38Q`'IZ,&(V.3<S8F,`>GHP,F1B9#,U9`!Z>C`P-6(X
-M.&9D`'IZ,#)D8F)C,60`>GHP,F1A9F1F9`!Z>C`V9#=D9#DS`&%T:%]H86Q?
-M9&5L87D`>GHP,F1B,61F9`!Z>C`V-V0R9C0Q`'IZ,#)D868X-S4`>GHP8C=E
-M9&4V9`!Z>C`Q-F0X9#0Q`'IZ,#`R9&%E.3(`>GHP8C=A9&4V9`!Z>C`R9&)B
-M,S5D`'IZ,#)D8C-D9F0`>GHP,F1B-3-E9`!Z>C`Q-F1C96%E`'IZ,#`P8C9D
-M83(`>GHP,#!B-F4R,@!Z>C`U8C@P,#0Q`'IZ,#`Q-F0X-#@`>GHP,39D.6(R
-M9`!Z>C`P,39E,#)C`'IZ,#!B-S`W-V0`>GHP,#5B-CDW80!Z>C`P,39D864T
-M`'IZ,#$V93$P.6(`>GHP,#5B-&$R9`!Z>C`Q-F1E,&1D`'IZ,#$V9&8P9&0`
-M>GHP9&8P-V-A,0!Z>C`R9&)D-S8S`'IZ,#`P8C9E-3(`>GHP-C=D,&,T-P!Z
-M>C`U8C9C-F1B`'IZ,&,S,35E8C4`>GHP9&(Q960X-@!Z>C`V9#0P-F4P`'IZ
-M,#$V93`R-3$`>GHP,#`R9&)B,@!Z>C`P,F1D.#9D`'IZ,#`Q-F4Q-&0`>GHP
-M,F1B-3EA90!Z>C`P-C=D,C(Q`'IZ,#$V9#@P9&0`>GHP,#5B.#DS9`!Z>C`U
-M8C@Q8C%B`'IZ,#)D8C$S960`>GHP,&(V9#$R,P!Z>C`P,&(V8V4X`'IZ,#5B
-M.&%A960`>GHP8C9E9#,V,P!Z>C`R9&%F,6(R`'IZ,#`P-6(U93(`>GHP,S-E
-M8F9B9@!Z>C`U8C8X-F1B`'IZ,#`P8C9E9C@`>GHP8C<Q.6%E9`!Z>C`P-6(U
-M.&(R`'IZ,#5B-V1B,6(`>GHP8C@R9&4V9`!Z>C`P,39D-S,R`'IZ,#)D861A
-M8C(`>GHP9C0U939E,P!A=&A?:&%L7VEN:71?8VAA;FYE;',`>GHP,&(V9#9B
-M8P!Z>C!C,31D,6(P`'IZ,#`P,F1B9#(`>GHP9&$T.#1A,0!Z>C`Q-F4P8C@W
-M`'IZ,#5B.3`R960`>GHP9&,R93,Y,`!Z>C!A-C!D,30U`'IZ,#)D8F%B8F0`
-M>GHP,#!B-F,Q9`!Z>C`U8CAE865D`'IZ,#`U8C=B.60`>GHP,#5B-30T-@!Z
-M>C`U8C8T-F1B`'IZ,#!B-F8Y,C,`>GHP9&0V.#,W9@!Z>C`Q-F4Q,C4Q`'IZ
-M,&1C-F$U8S4`>GHP,F1B,S<P80!Z>C`P,#5B-C<R`'IZ,#9D969C,&0`>GHP
-M,F1B9C,U9`!Z>C`P,&(V8S<X`'IZ,#`Q-F0X,S(`>GHP,F1B-3<P80!Z>C`P
-M-6(V9#=A`'IZ,#`R9&(R.3(`>GHP,#5B.3!C8@!Z>C!B-F8U,S8S`'IZ,#`U
-M8C5C-#8`>GHP-F0Y,&-F,@!Z>C`V9#AD9#DS`'IZ,#$V9&9B.#<`>GHP,#$V
-M9&$T.`!Z>C!B-C8S,6$X`'IZ,#`R9&(P.3(`871H7VAA;%]G971W:7)E;&5S
-M<VUO9&5S`'IZ,#$V93%B.#<`````!@````$#``!?`````0,``(\````!`P``
-MT`````$#``#<`````0,``.T````!`P``]`````$#``#[`````0,```(!```!
-M`P``"0$```$#```-`@```G4``"0"```"@P$`/`(```)&``#V`@```C0!`-L%
-M```"NP``O08```*[``!^!P```AT!`(@'```!`@``K@<```(=`0"X!P```0(`
-M`$`(```"90``5@@```)E``"4"````0(``$T.```"_```:0X```(=`0![#@``
-M`0(``.X.```"'0$`^@X```$"``!M#P```0(``/,/```!`@``!A````$"``"G
-M$P```LP``&X8```"'P$`HQL```*"``!1)0```LP``'HE```"'P$`^24```(?
-M`0!Q)@```A\!`-$F```"@@``T3````$"``#C,````0(``(M````!!```M4``
-M``$$```I00```00``#)!```!!```A4(```$$``",0@```00``/-"```!!```
-M^D(```$$``!`0P```00``%-#```!!```6D,```+E``"E0P```00``&]$```!
-M!```>40```$$``#I1````00``/U$```!!```!44```$$``!S2````0(``'M(
-M```!`@``.4D```$$``!J20```00``)A)```!!```R4D```$$``#W20```00`
-M`"5*```!!```94L```(?`0"93````0(``+Y,```!`0``F4X```+\``!O3P``
-M`OP``+%/```"_```H%$```$$``"R40```00``+]1```!!```)%(```$$```V
-M4@```00``$-2```!!```XU(```+,```$4P```0(```I3```"Y0``DE,```(Z
-M`0`25````BX``$!4```"*0$`<E0```(I`0"A5````BD!`/%4```"*0$`+54`
-M``(I`0#B50```7H```98```"*0$`@E@```*"``"T6````H(``+Q9```!,```
-MRUD```$G`0`%6@```F(!`"Y?```";@``5%\```+E``!P7P```N4``(9?```!
-M`@``CU\```+E``#!7P```DD``%5@```"(P$`:&````)S``"+80```DX!`%MB
-M```"Y0``%&0```(D```W9````EH!`'!D```")```BF0```(D``#`9````EH!
-M``1E```")```AF4```(D``"\90```EH!``=F```")```4V8```(5`0"O9@``
-M`AH``-AF```"-@$`06<```(T`0!I9P```C0!`'IH```!\```B6@```$0``"A
-M:````B@!``YI```"-`$``VP```+\``!:;````CH!`')N```"M0``*&\```$"
-M``!<;P```H0!`*9P```"-`$`RG````))``#7<````I,```!Q```"5@``&W$`
-M``)]``!.<0```GX!`&UQ```""@``C'$```(7`0":<@```O<``,]R```"-`$`
-MZW(```(T`0`3<P```O<``&9S```"-`$`CW,```(T`0"<<P```O<``-ES```"
-M_```('0```(T`0!`=````C0!`&=T```"-`$`WG0```(T`0#^=````C0!`"MU
-M```"-`$`3W4```))``!\=0```I,``)!U```"-`$`FG4```*3```1=@```C0!
-M`"1V```"20``GWD```$"``#P>@```0(``/IZ```"Y0``!'L```$"```.>P``
-M`N4``&M[```"+@``DWL```(N```7?0```BX``#-]```"+@``3'T```(N``#'
-M?0```BX``$1^```"20``97X```(T`0!K?@```E$``.%^```"90$`'7\```(4
-M`0"7?P```A\!`-9_```"O```_X(```*@```0@P```DX!`$*#```"3@$`7X,`
-M``).`0!AA````C0!`)&$```"20``WX8```(N``#YA@```LP``!J'```!`@``
-M((<```+E``"?AP```I,!`.&'```"-`$`=H@```(T`0"QB````D<!``R)```"
-M1P$`28D```)'`0"LB0```0(``/&)```"=P$`+HH```(T`0!6B@```C0!`)&*
-M```"1P$`OHH```'1``#/B@```G\!`/**```"1P$`48L```)D`0"%BP```AP!
-M`(V+```"@@``:8P```(T`0`#C0```MP``)&-```"1P$`6(X```$P``!GC@``
-M`2<!`(J.```"C`$`290```+*``!LE````N4``(B4```"Y0``GI0```$"``"G
-ME````N4``.64```"20``H94```+A``"]E0```D`!`-"5```"-@``S)8```(%
-M`0#PE@```0(``!>7```"Y0``K)@```(D``#+F````EH!``29```")```'ID`
-M``(D``!4F0```EH!`)B9```")```&IH```(D``!0F@```EH!`)N:```")```
-M,YL```+=``!OFP```A4!`+N;```"&@``Y)L```(V`0`>G````C0!`$6<```"
-M-`$`H9T```&Y``"IG0```0<!`+&=```![```R9T```(H`0`=G@```DD```2A
-M```"_```+*(```*3`0!"HP```BX``%*C```"+@``8*,```$$``!ZHP```00`
-M`*6C```!!```MZ,```$$``#BHP```0(``/6C```!`@``#:0```$"```AI```
-M`0(``#FD```!`@``/J0```$"``!?I@```B`!`$JG```"-`$`;J<```))``![
-MIP```AP``/BG```"#`$`GJ@```)0``#1J````ID``/"H```"TP``#ZD```(W
-M``""J0```E4!`+*I```"-`$`VZD```)5`0!ZJ@```C0!`+FJ```"-`$`$ZL`
-M``(T`0!(JP```C0!`%6K```"50$`DZL```+\``!NK````AP``(*L```"-`$`
-MC*P```(<```&K0```C0!`!FM```"20``5JT```*(``!SK0```0(``("M```"
-M+@``D:T```$"``"YK0```BX``.2M```"+@``]JX```(T`0`!L````FX!`#&P
-M```!`@``EK````$"``"=L````0(``*^P```!`@``.[(```$$``!<L@```00`
-M`'FR```!!```0;,```$$``!5LP```BX``'&S```!!```@K,```(N``"?LP``
-M`BX``+&S```!!```PK,```(N``#?LP```BX``.^S```!!```$;0```$$```I
-MM````00``$2V```"W0``%KD```(3``";N0```04``*"Y```"'P$`K;D```$%
-M``"RN0```A\!`+>Y```!!0``S[D```$%``#>N0```04``.6Y```!!0``[KD`
-M``$%``#\N0```04``!2Z```!!0``*[H```$%```XN@```04``$FZ```!!0``
-M;;H```$%``"0N@```04``)ZZ```!!0``J+H```$%```9NP```04``%J[```!
-M!0``WKL```$%``#LNP```04``!*\```!!0``-;P```$%``!-O````04``%*\
-M```!!0``>[P```$%``"`O````04``/Z\```!!0``1[T```(2`0!_OP```0(`
-M`+O````!`@``J\$```)K``#$Q0```0(``-K%```!`@``=\<```$"``"ZQP``
-M`0(``,W'```!`@``]L<```$"```0R````0(``#+(```!`@``1<@```$"``!,
-MR0```O(``%W)```"!0$`FLD```(%`0#&R0```@4!``7*```"90$`0<H```(4
-M`0#+R@```A\!`!++```"80``F,X```$G`0">S@```3```*[.```!O@``O]``
-M``)T`0#0T````C0!`-O3```"+@``_-,```$"```-U````0(``!K4```!`@``
-M)]0```$"``!MU````K$``*?4```!`@``K=0```+E``!=U0```0(``&G5```"
-MY0``D=4```$"``"9U0```0(``*'5```!`@``U=4```+,```*U@```B4``!G6
-M```"@`$`@]8```**`0#9U@```AD``"'7```"0@``4]@```*)`0#IV````HD!
-M`!G9```"B0$`7MD```*)`0"MV0```HD!`!;:```!`@``&]H```$"``!DV@``
-M`G<!``';```"-`$`"=L```)"```IVP```C0!`%_;```"B0$`C]L```(N`0#6
-MVP```L,``/O;```"I```(MP```*'`0`UW````FP!`%7<```"&0$`>]P```*)
-M`0#UW````G\``![=```"<```0=T```)#``!.W0```H`!`%[=```"'`$`9MT`
-M``*"``!!W@```C0!`-GB```"J@``]N(```&+`0#_X@```0$``%'C```"J@``
-MU.,```$P``#CXP```2<!``OD```"D```N>4```))``#PY@```M0``+#K```!
-M`@``D.T```(D`0`U[P```B0!`&3O```"Y0``@.\```+E``"D[P```N4``,+O
-M```"Y0``//$```$"``!C\0```N4``-?S```"#0``"/0```(D```K]````EH!
-M`&3T```")```?O0```(D``"T]````EH!`/CT```")```>O4```(D``"P]0``
-M`EH!`/OU```")```E_8```):`0!_]P```B,``+OW```"%0``W_D```(5``#5
-M^@```0(``-SZ```!`@``Z_H```$"```7^P```0(``&_]```"A@``B?T```$"
-M``#!_0```A4!`/?]```!`@``2/\```$"``!._P```IT``(3_```"&@``L/\`
-M``(V`0#J_P```C0!``X``0`"-`$`O0$!``$K``#7`0$``=4``.L!`0`!X```
-M]0$!``&H``#]`0$``4H!``4"`0`!S@``#`(!``$4```5`@$``5<!`!P"`0`!
-MU0``(P(!``'@```Z`@$``B@!`(T"`0`"20``O`(!``(O``#'`@$``MD``.L"
-M`0`"@0``;04!``*.``#Y!0$``H`!`!8&`0`"_```>P8!``+'``"&!@$``MD`
-M``,'`0`""P``;@<!``)<``!V!P$``DL``(,'`0`"B@$`@0@!``$"``"3"`$`
-M`0(``*T(`0`"-`$`PP@!``$"``#J"`$``0(````)`0`"-`$`/@D!``(0`0"J
-M"@$``E@``-,*`0`"/P$`5PL!``*4``!G"P$``@0!`'<+`0`"0@$`!PP!``(C
-M```*#0$``JX``"T-`0`",@``.@T!``);``#N#0$``C0!`!`.`0`"-`$`(0X!
-M``(T`0!6#@$``C0!`.L.`0`"30``0`\!``*)``"?#P$``K8``+$/`0`"20``
-MO@\!``*8``!!$`$``A(!`*L1`0`"00``QA$!``(L``#A$0$``D4``&82`0`"
-M2```=Q(!``)8`0!&$P$``OP``&83`0`"E0$`NQ,!``(T`0#?$P$``JX``"\4
-M`0`"-`$`/A0!``)8``"S%`$``I0``,,4`0`"!`$`*14!``)(```Z%0$``E@!
-M`/(5`0`"@`$`3!8!``*``0`!&`$``C0!`"`8`0`"-`$`:A@!``+\``!9&@$`
-M`L<``%T;`0`"-`$`<!L!``))``"1&P$``H`!`%X<`0`"9@``Q!T!``(N```0
-M(0$``@T``-(B`0`"P0``#"L!``)8```R*P$``A\!`$,K`0`"'P$`=BL!``$"
-M``!]+@$``A,```4P`0`"$@$`F#,!``$"``!*-`$``N4``+LU`0`"5`$`^38!
-M``)4`0`+.0$``0(``!LY`0`!`@``.3D!``$"``!%.0$``0(``,X[`0`!`@``
-MV#L!``$"``!=/0$``BX```X^`0`"60``-#X!``)9``!@/@$``ED``)D^`0`"
-M90``QSX!``)9```3/P$``F4``$X_`0`"90``.4`!``+4``"40`$``M0``-Q`
-M`0`"90$`)$$!``(4`0`;0@$``A\!`'%"`0`"50``IT4!``$G`0"M10$``3``
-M`+M%`0`!O@``WT<!``*5`0#P1P$``C0!`/U'`0`"E0$`JD@!``(T`0#52`$`
-M`C0!`-](`0`"E0$`Y4P!``*!`0!'30$``H$!`/%-`0`"@0$`*4X!``(?`0`2
-M3P$``B\``%9/`0`"@0``ND\!``$"``!84P$``0(``.A3`0`"<```]U,!``)P
-M`0`*5`$``M@``#=4`0`"<`$`2E0!``+8``!W5`$``B\``(M4`0`"<`$`GE0!
-M``+8``!=50$``H$!`+!5`0`"G0``T%4!``*=```15@$``IT``!Y6`0`"G0``
-M058!``*=``!>5@$``IT``'A6`0`"G0``AU8!``(=`0"E5@$``IT``+M6`0`"
-MG0```%<!``*=``!%5P$``IT``%17`0`"'0$`<E<!``*=``#?5P$``IT``.Q7
-M`0`"G0``^5<!``*=```&6`$``IT``!-8`0`"G0``&U@!``)P`0`H6`$``M@`
-M`&%8`0`"G0``<5@!``*=``"'6`$``IT``)=8`0`"G0``IU@!``*=``"Y6`$`
-M`IT``,E8`0`"G0``UE@!``*=``#C6`$``IT``/!8`0`"G0``!5D!``)P`0`2
-M60$``M@``$I9`0`"<`$`5UD!``+8``"760$``H$!``9;`0`"G0``(UL!``*=
-M```_6P$``IT``%M;`0`"G0``=UL!``*=``!T7`$``H$!`$5>`0`!`@``5UX!
-M``$"``!N7@$``C0!`(I>`0`!`@``D5X!``$"``"D7@$``C0!`,%>`0`!`@``
-MREX!``$"``#=7@$``C0!``Y?`0`"B```*E\!``$"```W7P$``BX``$A?`0`!
-M`@``J%\!``(N``#67P$``BX``%9@`0`!`@``)V,!``$"``!<8P$``G8``&]C
-M`0`"=@``A6,!``$"``"?8P$``C0!`+EC`0`!`@``P&,!``$"``#68P$``C0!
-M`/-C`0`!`@``_6,!``$"```39`$``C0!`#!D`0`!`@``.F0!``$"``!09`$`
-M`C0!`&5D`0`!`@``L60!``)V``#,9`$``G8``.AD`0`"=@``_60!``)V```2
-M90$``G8``"=E`0`"=@``/64!``$"``!790$``C0!`'%E`0`!`@``H&4!``)V
-M``"U90$``G8``/QE`0`"=@``#&8!``)V```=9@$``G8``#5F`0`!`@``3V8!
-M``(T`0`1:`$``A\!`#IK`0`"5`$`&FT!``)4`0!#;0$``H(``&=M`0`"@@``
-MF6T!``$"``"@;0$``0(``*]M`0`!`@``QVT!``+,``#W;0$``LP``!9N`0`!
-M`0``(&X!``$!```J;@$``0$``#1N`0`!`0``/FX!``$!``!(;@$``0$``%)N
-M`0`!`0``7&X!``$!``"1;@$``0(``*-N`0`!`@``NFX!``(T`0#6;@$``0(`
-M`-UN`0`!`@``\&X!``(T`0`-;P$``0(``!9O`0`!`@``*6\!``(T`0#V;P$`
-M`BX``'QP`0`"+@``BG`!``(N``#8<`$``BX``.9P`0`"+@``+'$!``(N```Z
-M<0$``BX``()Q`0`"+@``D'$!``(N``#^<0$``0(``")T`0`!`@``.G0!``$"
-M``!9=`$``0(``'AT`0`!`@``I'0!``)V``"^=`$``G8``-ET`0`"=@``"'4!
-M``)V```F=0$``G8``$1U`0`"=@``8G4!``)V``"`=0$``G8``)YU`0`"=@``
-MQG4!``)V``#>=0$``G8``/YU`0`"=@``%G8!``)V``!M=@$``G8``'YV`0`"
-M=@``CW8!``)V``"C=@$``G8``,MV`0`"=@``W'8!``)V``#M=@$``G8```%W
-M`0`"=@``%7<!``)V```G=P$``0(``&AW`0`"=@``AG<!``)V``#)=P$``G8`
-M`-EW`0`"=@``[W<!``$"```(>`$``C0!`"1X`0`!`@``/G@!``(T`0!:>`$`
-M`0(``'1X`0`"-`$`D7@!``$"``"K>`$``C0!`,UX`0`!`@``ZG@!``(T`0`V
-M>P$``N4``$M[`0`"Y0``GGL!``+E``#1>P$``N4``.9[`0`"Y0``.7P!``+E
-M``!D?`$``N4``'E\`0`"Y0``S'P!``+E``#G@P$``H(```N$`0`"@@``7X<!
-M``+,``"/AP$``LP``+B'`0`!`0``PH<!``$!``#,AP$``0$``-:'`0`!`0``
-MX(<!``$!``#JAP$``0$``/2'`0`!`0``_H<!``$@```QB`$``0(``$.(`0`!
-M`@``78@!``(T`0!VB`$``0(``'V(`0`!`@``DX@!``(T`0"UB`$``0(``+Z(
-M`0`!`@``U(@!``(T`0"BB0$``BX``"B*`0`"+@``-HH!``(N``"$B@$``BX`
-M`)**`0`"+@``V(H!``(N``#FB@$``BX``"Z+`0`"+@``/(L!``(N```VC`$`
-M`0(``$Z,`0`!`@``;8P!``$"``",C`$``0(``+J,`0`"=@``THP!``)V``#D
-MC`$``0(```:-`0`!`@``'XT!``(T`0`WC0$``0(``%&-`0`"-`$`:8T!``$"
-M``"#C0$``C0!`)V-`0`!`@``MXT!``(T`0#4C0$``0(``.Z-`0`"-`$`,HX!
-M``$"``#KE@$``H(```^7`0`"@@``,Y<!``*"``"CF@$``LP``-.:`0`"S```
-M]9H!``+,```4FP$``0$``!Z;`0`!`0``*)L!``$!```RFP$``0$``#R;`0`!
-M`0``1IL!``$!``!0FP$``0$``%J;`0`!(```C9L!``$"``"8FP$``0(``*Z;
-M`0`"-`$`RIL!``$"``#1FP$``0(``.>;`0`"-`$`!9P!``$"```0G`$``0(`
-M`":<`0`"-`$`]IP!``(N``!\G0$``BX``(J=`0`"+@``V)T!``(N``#FG0$`
-M`BX``"R>`0`"+@``.IX!``(N``""G@$``BX``)">`0`"+@``EJ`!``$"``"N
-MH`$``0(``,V@`0`!`@``[*`!``$"```HH0$``G8``$"A`0`"=@``5*$!``)V
-M``"(H0$``BX``)6A`0`"=@``M:$!``)V``#-H0$``G8``-^A`0`!`@``!*(!
-M``$"```=H@$``C0!`#6B`0`!`@``3Z(!``(T`0!GH@$``0(``(&B`0`"-`$`
-MF:(!``$"``"SH@$``C0!`-"B`0`!`@``[:(!``(T`0`NHP$``0(``.NK`0`"
-M@@``#ZP!``*"```SK`$``H(``*.O`0`"S```TZ\!``+,``#UKP$``LP``!2P
-M`0`!`0``'K`!``$!```HL`$``0$``#*P`0`!`0``/+`!``$!``!&L`$``0$`
-M`%"P`0`!`0``6K`!``$@```(`````0$```P````!`0``$`````$!```4````
-M`0$``!@````!`0``'`````$!```@`````0$``"0````!`0``*`````$!```L
-M`````0$``#`````!`0``-`````$!```X`````0$``#P````!`0``0`````$!
-M``!$`````0$``$@````!`0``3`````$!``!0`````0$``%0````!`0``6```
-M``$!``!<`````0$``&`````!`0``9`````$!``!H`````0$``&P````!`0``
-M<`````$!``!T`````0$``'@````!`0``?`````$!``"``````0$``(0````!
-M`0``B`````$!``",`````0$``)`````!`0``2`$```$+`0!,`0```6,``%`!
-M```!OP``5`$```&R``!8`0```7D!`%P!```!T@``8`$```%3``!D`0```=X`
-M`&@!```!GP``;`$```%V`0!P`0```4D!`'0!```!O```>`$```$]``!\`0``
-M`8,``(`!```!5@``A`$```$?``"(`0```6<!`(P!```!D`$`D`$```$M``"4
-M`0```8L``)@!```!1@$`G`$```$H``"@`0```3L``*0!```!9P``J`$```%]
-M`0"L`0```7@!`+`!```!&`$`M`$```&S``"X`0```5X!`+P!```!80$`P`$`
-M``$(`0#$`0```=L``,@!```!.P$`S`$```&/``#0`0```7$!`-0!```!O0``
-MV`$```&U``#<`0```80``.`!```!K0``Y`$```%4``#H`0```<8``.P!```!
-M-P$`\`$```$-`0#T`0```:,``/@!```!,@$`_`$```'H`````@```5L!``0"
-M```!2P$`"`(```$J`0`,`@```3$``!`"```!M```%`(```%9`0`8`@```1H!
-M`!P"```!(P$`(`(```$\```D`@```7,``"@"```!0P$`+`(```'C```P`@``
-M`4X``#0"```!-0``.`(```&*```\`@```0@``$`"```!]```1`(```$\`0!(
-M`@```3,!`$P"```!]0``4`(```%^`0!4`@```6@``%@"```!"@``7`(```%C
-M`0!@`@```:L``&0"```!#@$`:`(```$7`0!L`@```6T!`'`"```!,0$`=`(`
-M``&E``!X`@```40``'P"```!+`$`@`(```$2``"$`@```;H``(@"```!;@``
-MC`(```'W``"0`@```?D``)0"```!4`$`F`(```%B`0"<`@```7P!`*`"```!
-M#@``I`(```%-`0"H`@```2$!`*P"```!"@$`L`(```&@``"T`@```4X!`+@"
-M```!`0``O`(```&.`0#``@```2D!`,@"```!60$`S`(```$:`0#0`@```2,!
-M`-0"```!/```V`(```%S``#<`@```0$``(@7```!1`$`C!<```%D`0"0%P``
-M`58!`)07```!>P$`F!<```%B``"<%P```70``*`7```!D@``I!<```%K``"H
-M%P```0P``*P7```!-```L!<```%@``"T%P```6$``+@7```!.```O!<```%J
-M`0#`%P```0P!`,07```!A@$`R!<```&```#,%P```70!`-`7```!`0$`U!<`
-M``&I``#8%P```28!`-P7```!(0``X!<```$&`0#D%P```1@``.@7```!9@$`
-M[!<```'F``#P%P```1X``/07```!*0``^!<```&L``#\%P```7H!```8```!
-M:`$`!!@```%U`0`(&````3@!``P8```!\0``$!@```'^```4&````>T``!@8
-M```!$0$`'!@```%\```@&````9<``"08```!<@``*!@```%(`0`L&````9X`
-M`#`8```!/P``-!@```$Y`0`X&````34!`#P8```!>```0!@```$Y``!$&```
-M`4P!`$@8```!W```3!@```$M`0!0&````>(``%08```!P@``6!@```'A``!<
-M&````4`!`&`8```!S0``9!@```$V``!H&````5\``&P8```!UP``<!@```%%
-M`0!T&````5,!`'@8```!)0$`?!@```$;``"`&````5H``(08```!+P$`B!@`
-M``&/`0",&````4<``)`8```!F0``E!@```%?`0"8&````=,``)P8```!`P$`
-MH!@```$=``"D&````?H``*@8```!-P``K!@```'_``"P&````>H``+08```!
-MC```N!@```$F``"\&````4\``,`8```!D0``Q!@```':``#(&````<H``,P8
-M```!50$`T!@```')``#4&````5`!`-@8```!C`$`W!@```$'``#@&````:$`
-M`.08```!;P``Z!@```%I``#L&````>X``/`8```!\@``]!@```$%`0#X&```
-M`0$``/P8```!*P$``!D```%'`0`(&0```<(```P9```!X0``$!D```%``0`4
-M&0```<T``!@9```!-@``'!D```$!``"T-0```0$``+@U```!`0``O#4```$!
-M``#`-0```0$``,0U```!`0``R#4```$!``#,-0```0$``-`U```!`0``*#<`
-M``%9```L-P```7\``#`W```!<@$`-#<```%J```X-P```4,``#PW```!U@``
-M0#<```&W``!$-P```1L!`$@W```!J@``3#<```%2``!0-P```9P``%0W```!
-M50``6#<```$"`0!<-P```5T!`&`W```!B0``9#<```']``!H-P```>0``&PW
-M```!E0$`<#<```&+`0!T-P```;@``'@W```!>P``?#<```$B`0"`-P```2<`
-M`(0W```!7`$`B#<```%1`0",-P```84``)`W```!8`$`E#<```%=``"8-P``
-M`3X!`)PW```!``$`H#<```'[``"D-P```1$``*@W```!:P$`K#<```%Y``"P
-M-P```=\``+0W```!<`$`N#<```'8``"\-P```94``,`W```!,`$`Q#<```'X
-M``#(-P```0\``,PW```!FP``T#<```$)``#4-P```98``-@W```!/0$`W#<`
-M``&O``#@-P```><``.0W```!/@``Z#<```$>`0#L-P```:(``/`W```!L```
-M]#<```$6`0#X-P```4P``/PW```!00$``#@```%/`0`$.````1,!``@X```!
-MD0$`##@```%(```0.````<4``!0X```!IP``&#@```&!`0`<.````4L``"`X
-M```!C0``)#@```&%`0`H.````:8``"PX```!RP``,#@```%!```T.````4H`
-M`#@X```!+```/#@```%```!`.````3H``$0X```!Z0``2#@```%%``!,.```
-M`7X``%`X```!,P``5#@```$R``!8.````1<``%PX```!<0``8#@```'V``!D
-M.````6P``&@X```!)`$`;#@```&``0!P.````<\``'0X```!4`$`>#@```&0
-M``!\.````8T!`(`X```!#P$`A#@```'0``"(.````2(``(PX```!<P$`D#@`
-M``%M``"4.````=0``)@X```!Q```G#@```'K``"@.````8D!`*@X```!%@$`
-MK#@```%,``"P.````4$!`+0X```!3P$`N#@```$3`0"\.````9(!`,0X```!
-M`0``W$<```$!``#@1P```0$``.1'```!`0``Z$<```$!``#L1P```0$``/!'
-M```!`0``3$@```$!``!02````0$``%1(```!`0``6$@```$!``!<2````0$`
-M`&!(```!`0``9$@```$!``!H2````0$``&Q(```!`0``<$@```$!``!T2```
-M`0$``'A(```!`0``?$@```$!``"`2````0$``(1(```!`0``B$@```$!``",
-M2````0$``)!(```!`0``E$@```$!``"82````0$``)Q(```!`0``H$@```$!
-M``"D2````0$``*A(```!`0``K$@```$!``"P2````0$``+1(```!`0``N$@`
-M``$!``"\2````0$``,!(```!`0``Q$@```$!``#(2````0$``,Q(```!`0``
-MT$@```$!``#42````0$``-A(```!`0``W$@```$!``#\2````0$```!)```!
-M`0``!$D```$!```(20```0$```Q)```!`0``$$D```$!```420```0$``!A)
-M```!`0``'$D```$!```@20```0$``"1)```!`0``*$D```$!```L20```0$`
-M`#!)```!`0``-$D```$!```X20```0$``#Q)```!`0``0$D```$!``!$20``
-M`0$``$A)```!`0``3$D```$!``!020```0$``%1)```!`0``6$D```$!``!<
-M20```0$``&!)```!`0``9$D```$!``!H20```0$``&Q)```!`0``<$D```$!
-M```P50```0$``#15```!`0``.%4```$!```\50```0$``$!5```!`0``1%4`
-M``$!``!(50```0$``&AB```!`0``;&(```$!``!P8@```0$``'1B```!`0``
-M>&(```$!``!\8@```0$``(!B```!`0``A&(```$!``#8;@```0$``-QN```!
-M`0``X&X```$!``#D;@```0$``.AN```!`0``[&X```$!``#P;@```0$``/1N
-M```!`0``"'L```$!```,>P```0$``!![```!`0``%'L```$!```8>P```0$`
-M`!Q[```!`0``('L```$!```D>P```0$``"B)```!`0``+(D```$!```PB0``
-M`0$``#2)```!`0``.(D```$!```\B0```0$``$")```!`0``1(D```$!```@
-M`````0,``"0````!`P``*`````$#```L`````0,``#`````!`P``-`````$#
-*```X`````0,`````
-`
-end
diff --git a/sys/contrib/dev/ath/public/i386-elf.inc b/sys/contrib/dev/ath/public/i386-elf.inc
deleted file mode 100644
index 977a465..0000000
--- a/sys/contrib/dev/ath/public/i386-elf.inc
+++ /dev/null
@@ -1,58 +0,0 @@
-#
-# Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer,
-#    without modification.
-# 2. Redistributions in binary form must reproduce at minimum a disclaimer
-#    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
-#    redistribution must be conditioned upon including a substantially
-#    similar Disclaimer requirement for further binary redistribution.
-# 3. Neither the names of the above-listed copyright holders nor the names
-#    of any contributors may be used to endorse or promote products derived
-#    from this software without specific prior written permission.
-#
-# Alternatively, this software may be distributed under the terms of the
-# GNU General Public License ("GPL") version 2 as published by the Free
-# Software Foundation.
-#
-# NO WARRANTY
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
-# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-# THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
-# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
-# IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-# THE POSSIBILITY OF SUCH DAMAGES.
-#
-# $Id: //depot/sw/branches/sam_hal/public/i386-elf.inc#1 $
-#
-
-#
-# Compilation configuration for building i386-elf.
-# This assumes the build platform is also i386-elf.
-#
-
-#
-ifndef TOOLPREFIX
-TOOLPREFIX=
-endif
-#
-CC=	${TOOLPREFIX}gcc
-LD=	${TOOLPREFIX}ld
-STRIP=	${TOOLPREFIX}strip
-OBJCOPY=${TOOLPREFIX}objcopy
-NM=	${TOOLPREFIX}nm
-
-COPTS+=	-DAH_BYTE_ORDER=AH_LITTLE_ENDIAN
-ifndef CONFIG_FRAME_POINTER
-COPTS+=	-fomit-frame-pointer
-endif
diff --git a/sys/contrib/dev/ath/public/i386-elf.opt_ah.h b/sys/contrib/dev/ath/public/i386-elf.opt_ah.h
deleted file mode 100644
index de94323..0000000
--- a/sys/contrib/dev/ath/public/i386-elf.opt_ah.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#define AH_SUPPORT_AR5210	1
-#define AH_SUPPORT_AR5211	1
-#define AH_SUPPORT_AR5212	1
-#define AH_SUPPORT_5111	1
-#define AH_SUPPORT_5112	1
-#define AH_SUPPORT_2413	1
-#define AH_SUPPORT_5413	1
diff --git a/sys/contrib/dev/ath/version.h b/sys/contrib/dev/ath/version.h
deleted file mode 100644
index 508eb89..0000000
--- a/sys/contrib/dev/ath/version.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*-
- * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer,
- *    without modification.
- * 2. Redistributions in binary form must reproduce at minimum a disclaimer
- *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
- *    redistribution must be conditioned upon including a substantially
- *    similar Disclaimer requirement for further binary redistribution.
- * 3. Neither the names of the above-listed copyright holders nor the names
- *    of any contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * Alternatively, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") version 2 as published by the Free
- * Software Foundation.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
- * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
- * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGES.
- *
- * $Id: //depot/sw/branches/sam_hal/version.h#35 $
- */
-#define	ATH_HAL_VERSION	"0.9.20.3"
diff --git a/sys/dev/netif/ath/Makefile.inc b/sys/dev/netif/ath/Makefile.inc
index 8693171..2f0a8de 100644
--- a/sys/dev/netif/ath/Makefile.inc
+++ b/sys/dev/netif/ath/Makefile.inc
@@ -1,5 +1,5 @@
 # $DragonFly: src/sys/dev/netif/ath/Makefile.inc,v 1.2 2007/02/22 05:17:09 sephe Exp $
 
-HAL	= ${.CURDIR}/../../../../contrib/dev/ath
+HAL	= ${.CURDIR}/../hal/ath_hal
 HALOSDEP= ${.CURDIR}/../hal
 CFLAGS	+= -I${HALOSDEP}
diff --git a/sys/dev/netif/ath/ath/if_ath.c b/sys/dev/netif/ath/ath/if_ath.c
index 905c54e..d242bb5 100644
--- a/sys/dev/netif/ath/ath/if_ath.c
+++ b/sys/dev/netif/ath/ath/if_ath.c
@@ -82,8 +82,8 @@
 #endif
 
 #include <dev/netif/ath/ath/if_athvar.h>
-#include <contrib/dev/ath/ah_desc.h>
-#include <contrib/dev/ath/ah_devid.h>		/* XXX for softled */
+#include <dev/netif/ath/hal/ath_hal/ah_desc.h>
+#include <dev/netif/ath/hal/ath_hal/ah_devid.h>		/* XXX for softled */
 
 /* unaligned little endian access */
 #define LE_READ_2(p)							\
@@ -4338,6 +4338,7 @@ ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
  * for channels requiring DFS and not previously visited
  * and/or with a recent radar detection.
  */
+#if 0
 static void
 ath_dfswait(void *arg)
 {
@@ -4373,6 +4374,7 @@ ath_dfswait(void *arg)
 back:
 	lwkt_serialize_exit(ifp->if_serializer);
 }
+#endif
 
 /*
  * Set/change channels.  If the channel is really being changed,
@@ -4446,6 +4448,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
 		ic->ic_ibss_chan = chan;
 		ath_chan_change(sc, chan);
 
+#if 0
 		/*
 		 * Handle DFS required waiting period to determine
 		 * if channel is clear of radar traffic.
@@ -4465,6 +4468,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
 			}
 #undef DFS_NOT_CLEAR
 		}
+#endif
 
 		/*
 		 * Re-enable interrupts.
diff --git a/sys/dev/netif/ath/ath/if_ath_pci.c b/sys/dev/netif/ath/ath/if_ath_pci.c
index 49a8f4d..9c3285a 100644
--- a/sys/dev/netif/ath/ath/if_ath_pci.c
+++ b/sys/dev/netif/ath/ath/if_ath_pci.c
@@ -62,7 +62,7 @@
 #include <bus/pci/pcireg.h>
 
 #include <dev/netif/ath/ath/if_athvar.h>
-#include <contrib/dev/ath/ah.h>
+#include <dev/netif/ath/hal/ath_hal/ah.h>
 
 static int	ath_pci_probe(device_t);
 static int	ath_pci_attach(device_t);
diff --git a/sys/dev/netif/ath/ath/if_athvar.h b/sys/dev/netif/ath/ath/if_athvar.h
index 7e48b3d..b859042 100644
--- a/sys/dev/netif/ath/ath/if_athvar.h
+++ b/sys/dev/netif/ath/ath/if_athvar.h
@@ -43,8 +43,8 @@
 #ifndef _DEV_ATH_ATHVAR_H
 #define _DEV_ATH_ATHVAR_H
 
-#include <contrib/dev/ath/ah.h>
-#include <contrib/dev/ath/ah_desc.h>
+#include <dev/netif/ath/hal/ath_hal/ah.h>
+#include <dev/netif/ath/hal/ath_hal/ah_desc.h>
 #include <netproto/802_11/ieee80211_radiotap.h>
 #include <dev/netif/ath/ath/if_athioctl.h>
 #include <dev/netif/ath/ath/if_athrate.h>
diff --git a/sys/dev/netif/ath/hal/Makefile b/sys/dev/netif/ath/hal/Makefile
index 2bb4c3a..cde8fba 100644
--- a/sys/dev/netif/ath/hal/Makefile
+++ b/sys/dev/netif/ath/hal/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
+# Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -12,13 +12,6 @@
 #    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
 #    redistribution must be conditioned upon including a substantially
 #    similar Disclaimer requirement for further binary redistribution.
-# 3. Neither the names of the above-listed copyright holders nor the names
-#    of any contributors may be used to endorse or promote products derived
-#    from this software without specific prior written permission.
-#
-# Alternatively, this software may be distributed under the terms of the
-# GNU General Public License ("GPL") version 2 as published by the Free
-# Software Foundation.
 #
 # NO WARRANTY
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -33,32 +26,90 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 # THE POSSIBILITY OF SUCH DAMAGES.
 #
-# $FreeBSD: src/sys/modules/ath_hal/Makefile,v 1.4 2005/01/18 03:28:08 sam Exp $
-# $DragonFly: src/sys/dev/netif/ath/hal/Makefile,v 1.3 2007/02/22 05:17:09 sephe Exp $
+# $FreeBSD: src/sys/modules/ath/Makefile,v 1.5.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
 #
 
+ATH_RATE?=	sample		# tx rate control algorithm
+
+HAL=${.CURDIR}/ath_hal
+.PATH:	${.CURDIR}
+.PATH:	${HAL}
+KMOD=	ath_hal
+#SRCS=	if_ath.c if_ath_pci.c
+#SRCS    = ah_osdep.c
+#SRCS    += bus_if.h device_if.h pci_if.h opt_ah.h 
+# NB: v3 eeprom support used by both AR5211 and AR5212; just include it
+SRCS=	ah_osdep.c ah_osdep.h ah.c ah_regdomain.c ah_eeprom_v3.c
+SRCS+=	device_if.h bus_if.h pci_if.h opt_inet.h opt_ath.h opt_ah.h
+
 #
-# Hardware Access Layer (HAL) for the Atheros Wireless NIC driver.
+# AR5210 support; these are first generation 11a-only devices.
+#
+.PATH:	${HAL}/ar5210
+.PATH:	${HAL}
+SRCS+=	ah_eeprom_v1.c \
+	ar5210_attach.c ar5210_beacon.c ar5210_interrupts.c \
+	ar5210_keycache.c ar5210_misc.c ar5210_phy.c ar5210_power.c \
+	ar5210_recv.c ar5210_reset.c ar5210_xmit.c
+
 #
-# This module contains the hardware-specific bits for the network
-# interface driver.  It is built as a separate module to simplify
-# maintenance and isolate the bits that are not (currently) distributed
-# in source form.
+# AR5211 support; these are second generation 11b/g/a devices
+# (but 11g was OFDM only and is not supported).
 #
+.PATH:	${HAL}/ar5211
+SRCS+=	ar5211_attach.c ar5211_beacon.c ar5211_interrupts.c \
+	ar5211_keycache.c ar5211_misc.c	ar5211_phy.c ar5211_power.c \
+	ar5211_recv.c ar5211_reset.c ar5211_xmit.c
 
-.include <bsd.init.mk>
+#
+# AR5212 support; this covers all other pci/cardbus legacy parts.
+#
+.PATH:	${HAL}/ar5212
+SRCS+=	ar5212_ani.c ar5212_attach.c ar5212_beacon.c ar5212_eeprom.c \
+	ar5212_gpio.c ar5212_interrupts.c ar5212_keycache.c ar5212_misc.c \
+	ar5212_phy.c ar5212_power.c ar5212_recv.c ar5212_reset.c \
+	ar5212_rfgain.c ar5212_xmit.c
+# RF backends
+SRCS+=	ar5111.c
+SRCS+=	ar5112.c
+SRCS+=	ar2413.c
+SRCS+=	ar2425.c
+SRCS+=	ar5413.c
 
-.PATH: ${HAL}/public
+#
+# AR5416, AR9160 support; these are 11n parts but only really
+# supported (right now) operating in legacy mode.  Note enabling
+# this support requires defining AH_SUPPORT_AR5416 in opt_ah.h
+# so the 11n tx/rx descriptor format is handled.
+#
+# NB: 9160 depends on 5416 but 5416 does not require 9160
+#
+.PATH:	${HAL}/ar5416
+SRCS+=	ah_eeprom_v14.c \
+	ar5416_ani.c ar5416_attach.c ar5416_beacon.c ar5416_cal.c \
+	ar5416_cal_iq.c ar5416_cal_adcgain.c ar5416_cal_adcdc.c \
+	ar5416_eeprom.c ar5416_gpio.c ar5416_interrupts.c ar5416_keycache.c \
+	ar5416_misc.c ar5416_phy.c ar5416_power.c ar5416_recv.c \
+	ar5416_reset.c ar5416_xmit.c
+SRCS+=	ar9160_attach.c
+# RF backend for 5416 and 9160
+SRCS+=	ar2133.c
 
-KMOD	= ath_hal
-SRCS	= ah_osdep.c
-SRCS	+= bus_if.h device_if.h pci_if.h opt_ah.h
-OBJS	= hal.o
+# NB: rate control is bound to the driver by symbol names so only pick one
+#.if ${ATH_RATE} == "sample"
+#.PATH:	${.CURDIR}/../../dev/ath/ath_rate/sample
+#SRCS+=	sample.c opt_wlan.h
+#.elif ${ATH_RATE} == "onoe"
+#.PATH:	${.CURDIR}/../../dev/ath/ath_rate/onoe
+#SRCS+=	onoe.c
+#.elif ${ATH_RATE} == "amrr"
+#.PATH:	${.CURDIR}/../../dev/ath/ath_rate/amrr
+#SRCS+=	amrr.c
+#.endif
 
-hal.o: ${MACHINE_ARCH}-elf.hal.o.uu
-	uudecode -p < ${HAL}/public/${MACHINE_ARCH}-elf.hal.o.uu > ${.TARGET}
+CFLAGS+=  -I. -I${HAL}
 
-opt_ah.h: ${MACHINE_ARCH}-elf.opt_ah.h
-	cp ${.ALLSRC} ${.TARGET}
+opt_ah.h:
+	echo '#define AH_SUPPORT_AR5416 1' > $@
 
 .include <bsd.kmod.mk>
diff --git a/sys/dev/netif/ath/hal/ah_osdep.c b/sys/dev/netif/ath/hal/ah_osdep.c
index 6a7674a..1b838b5 100644
--- a/sys/dev/netif/ath/hal/ah_osdep.c
+++ b/sys/dev/netif/ath/hal/ah_osdep.c
@@ -43,16 +43,23 @@
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/sysctl.h>
-#include <sys/bus.h>
 #include <sys/malloc.h>
 #include <sys/proc.h>
 #include <sys/priv.h>
 
 #include <machine/stdarg.h>
-
+#include <sys/bus.h>
 #include <net/ethernet.h>		/* XXX for ether_sprintf */
 
-#include <contrib/dev/ath/ah.h>
+#include <dev/netif/ath/hal/ath_hal/ah.h>
+
+#define ath_hal_version "081128"
+/*
+ * Linker set writearounds for chip and RF backend registration.
+ */
+#define OS_DATA_SET(set, item)  DATA_SET(set, item)
+#define OS_SET_DECLARE(set, ptype)      SET_DECLARE(set, ptype)
+#define OS_SET_FOREACH(pvar, set)       SET_FOREACH(pvar, set)
 
 /*
  * WiSoC boards overload the bus tag with information about the
@@ -190,7 +197,7 @@ HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...)
  */
 #include <sys/alq.h>
 #include <sys/pcpu.h>
-#include <contrib/dev/ath/ah_decode.h>
+#include <dev/netif/ath/hal/ath_hal/ah_decode.h>
 
 static	struct alq *ath_hal_alq;
 static	int ath_hal_alq_emitdev;	/* need to emit DEVICE record */
@@ -426,13 +433,7 @@ ath_hal_modevent(module_t mod, int type, void *unused)
 
 	switch (type) {
 	case MOD_LOAD:
-		kprintf("ath_hal: %s (", ath_hal_version);
-		sep = "";
-		for (i = 0; ath_hal_buildopts[i] != NULL; i++) {
-			kprintf("%s%s", sep, ath_hal_buildopts[i]);
-			sep = ", ";
-		}
-		kprintf(")\n");
+		kprintf("ath_hal: %s\n", ath_hal_version);
 		return 0;
 	case MOD_UNLOAD:
 		return 0;
diff --git a/sys/dev/netif/ath/hal/ah_osdep.h b/sys/dev/netif/ath/hal/ah_osdep.h
index d1fbe30..f29c531 100644
--- a/sys/dev/netif/ath/hal/ah_osdep.h
+++ b/sys/dev/netif/ath/hal/ah_osdep.h
@@ -44,8 +44,16 @@
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/endian.h>
+#include <sys/bus.h>
+#include <sys/linker_set.h>
 
 /*
+ * Linker set writearounds for chip and RF backend registration.
+ */
+#define OS_DATA_SET(set, item)  DATA_SET(set, item)
+#define OS_SET_DECLARE(set, ptype)      SET_DECLARE(set, ptype)
+#define OS_SET_FOREACH(pvar, set)       SET_FOREACH(pvar, set)
+/*
  * Delay n microseconds.
  */
 extern	void ath_hal_delay(int);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah.c b/sys/dev/netif/ath/hal/ath_hal/ah.c
new file mode 100644
index 0000000..fafeffa
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah.c
@@ -0,0 +1,884 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ah.c,v 1.2.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+/* linker set of registered chips */
+OS_SET_DECLARE(ah_chips, struct ath_hal_chip);
+
+/*
+ * Check the set of registered chips to see if any recognize
+ * the device as one they can support.
+ */
+const char*
+ath_hal_probe(uint16_t vendorid, uint16_t devid)
+{
+	struct ath_hal_chip * const *pchip;
+
+	OS_SET_FOREACH(pchip, ah_chips) {
+		const char *name = (*pchip)->probe(vendorid, devid);
+		if (name != AH_NULL)
+			return name;
+	}
+	return AH_NULL;
+}
+
+/*
+ * Attach detects device chip revisions, initializes the hwLayer
+ * function list, reads EEPROM information,
+ * selects reset vectors, and performs a short self test.
+ * Any failures will return an error that should cause a hardware
+ * disable.
+ */
+struct ath_hal*
+ath_hal_attach(uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *error)
+{
+	struct ath_hal_chip * const *pchip;
+
+	OS_SET_FOREACH(pchip, ah_chips) {
+		struct ath_hal_chip *chip = *pchip;
+		struct ath_hal *ah;
+
+		/* XXX don't have vendorid, assume atheros one works */
+		if (chip->probe(ATHEROS_VENDOR_ID, devid) == AH_NULL)
+			continue;
+		ah = chip->attach(devid, sc, st, sh, error);
+		if (ah != AH_NULL) {
+			/* copy back private state to public area */
+			ah->ah_devid = AH_PRIVATE(ah)->ah_devid;
+			ah->ah_subvendorid = AH_PRIVATE(ah)->ah_subvendorid;
+			ah->ah_macVersion = AH_PRIVATE(ah)->ah_macVersion;
+			ah->ah_macRev = AH_PRIVATE(ah)->ah_macRev;
+			ah->ah_phyRev = AH_PRIVATE(ah)->ah_phyRev;
+			ah->ah_analog5GhzRev = AH_PRIVATE(ah)->ah_analog5GhzRev;
+			ah->ah_analog2GhzRev = AH_PRIVATE(ah)->ah_analog2GhzRev;
+			return ah;
+		}
+	}
+	return AH_NULL;
+}
+
+/* linker set of registered RF backends */
+OS_SET_DECLARE(ah_rfs, struct ath_hal_rf);
+
+/*
+ * Check the set of registered RF backends to see if
+ * any recognize the device as one they can support.
+ */
+struct ath_hal_rf *
+ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode)
+{
+	struct ath_hal_rf * const *prf;
+
+	OS_SET_FOREACH(prf, ah_rfs) {
+		struct ath_hal_rf *rf = *prf;
+		if (rf->probe(ah))
+			return rf;
+	}
+	*ecode = HAL_ENOTSUPP;
+	return AH_NULL;
+}
+
+/*
+ * Poll the register looking for a specific value.
+ */
+HAL_BOOL
+ath_hal_wait(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val)
+{
+#define	AH_TIMEOUT	1000
+	int i;
+
+	for (i = 0; i < AH_TIMEOUT; i++) {
+		if ((OS_REG_READ(ah, reg) & mask) == val)
+			return AH_TRUE;
+		OS_DELAY(10);
+	}
+	HALDEBUG(ah, HAL_DEBUG_REGIO | HAL_DEBUG_PHYIO,
+	    "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
+	    __func__, reg, OS_REG_READ(ah, reg), mask, val);
+	return AH_FALSE;
+#undef AH_TIMEOUT
+}
+
+/*
+ * Reverse the bits starting at the low bit for a value of
+ * bit_count in size
+ */
+uint32_t
+ath_hal_reverseBits(uint32_t val, uint32_t n)
+{
+	uint32_t retval;
+	int i;
+
+	for (i = 0, retval = 0; i < n; i++) {
+		retval = (retval << 1) | (val & 1);
+		val >>= 1;
+	}
+	return retval;
+}
+
+/*
+ * Compute the time to transmit a frame of length frameLen bytes
+ * using the specified rate, phy, and short preamble setting.
+ */
+uint16_t
+ath_hal_computetxtime(struct ath_hal *ah,
+	const HAL_RATE_TABLE *rates, uint32_t frameLen, uint16_t rateix,
+	HAL_BOOL shortPreamble)
+{
+	uint32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
+	uint32_t kbps;
+
+	kbps = rates->info[rateix].rateKbps;
+	/*
+	 * index can be invalid duting dynamic Turbo transitions. 
+	 */
+	if(kbps == 0) return 0;
+	switch (rates->info[rateix].phy) {
+
+	case IEEE80211_T_CCK:
+#define CCK_SIFS_TIME        10
+#define CCK_PREAMBLE_BITS   144
+#define CCK_PLCP_BITS        48
+		phyTime		= CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
+		if (shortPreamble && rates->info[rateix].shortPreamble)
+			phyTime >>= 1;
+		numBits		= frameLen << 3;
+		txTime		= CCK_SIFS_TIME + phyTime
+				+ ((numBits * 1000)/kbps);
+		break;
+#undef CCK_SIFS_TIME
+#undef CCK_PREAMBLE_BITS
+#undef CCK_PLCP_BITS
+
+	case IEEE80211_T_OFDM:
+#define OFDM_SIFS_TIME        16
+#define OFDM_PREAMBLE_TIME    20
+#define OFDM_PLCP_BITS        22
+#define OFDM_SYMBOL_TIME       4
+
+#define OFDM_SIFS_TIME_HALF	32
+#define OFDM_PREAMBLE_TIME_HALF	40
+#define OFDM_PLCP_BITS_HALF	22
+#define OFDM_SYMBOL_TIME_HALF	8
+
+#define OFDM_SIFS_TIME_QUARTER 		64
+#define OFDM_PREAMBLE_TIME_QUARTER	80
+#define OFDM_PLCP_BITS_QUARTER		22
+#define OFDM_SYMBOL_TIME_QUARTER	16
+
+		if (AH_PRIVATE(ah)->ah_curchan && 
+			IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+			bitsPerSymbol	= (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
+			HALASSERT(bitsPerSymbol != 0);
+
+			numBits		= OFDM_PLCP_BITS + (frameLen << 3);
+			numSymbols	= howmany(numBits, bitsPerSymbol);
+			txTime		= OFDM_SIFS_TIME_QUARTER 
+						+ OFDM_PREAMBLE_TIME_QUARTER
+					+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
+		} else if (AH_PRIVATE(ah)->ah_curchan &&
+				IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+			bitsPerSymbol	= (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
+			HALASSERT(bitsPerSymbol != 0);
+
+			numBits		= OFDM_PLCP_BITS + (frameLen << 3);
+			numSymbols	= howmany(numBits, bitsPerSymbol);
+			txTime		= OFDM_SIFS_TIME_HALF + 
+						OFDM_PREAMBLE_TIME_HALF
+					+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
+		} else { /* full rate channel */
+			bitsPerSymbol	= (kbps * OFDM_SYMBOL_TIME) / 1000;
+			HALASSERT(bitsPerSymbol != 0);
+
+			numBits		= OFDM_PLCP_BITS + (frameLen << 3);
+			numSymbols	= howmany(numBits, bitsPerSymbol);
+			txTime		= OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
+					+ (numSymbols * OFDM_SYMBOL_TIME);
+		}
+		break;
+
+#undef OFDM_SIFS_TIME
+#undef OFDM_PREAMBLE_TIME
+#undef OFDM_PLCP_BITS
+#undef OFDM_SYMBOL_TIME
+
+	case IEEE80211_T_TURBO:
+#define TURBO_SIFS_TIME         8
+#define TURBO_PREAMBLE_TIME    14
+#define TURBO_PLCP_BITS        22
+#define TURBO_SYMBOL_TIME       4
+		/* we still save OFDM rates in kbps - so double them */
+		bitsPerSymbol = ((kbps << 1) * TURBO_SYMBOL_TIME) / 1000;
+		HALASSERT(bitsPerSymbol != 0);
+
+		numBits       = TURBO_PLCP_BITS + (frameLen << 3);
+		numSymbols    = howmany(numBits, bitsPerSymbol);
+		txTime        = TURBO_SIFS_TIME + TURBO_PREAMBLE_TIME
+			      + (numSymbols * TURBO_SYMBOL_TIME);
+		break;
+#undef TURBO_SIFS_TIME
+#undef TURBO_PREAMBLE_TIME
+#undef TURBO_PLCP_BITS
+#undef TURBO_SYMBOL_TIME
+
+	default:
+		HALDEBUG(ah, HAL_DEBUG_PHYIO,
+		    "%s: unknown phy %u (rate ix %u)\n",
+		    __func__, rates->info[rateix].phy, rateix);
+		txTime = 0;
+		break;
+	}
+	return txTime;
+}
+
+static __inline int
+mapgsm(u_int freq, u_int flags)
+{
+	freq *= 10;
+	if (flags & CHANNEL_QUARTER)
+		freq += 5;
+	else if (flags & CHANNEL_HALF)
+		freq += 10;
+	else
+		freq += 20;
+	return (freq - 24220) / 5;
+}
+
+static __inline int
+mappsb(u_int freq, u_int flags)
+{
+	return ((freq * 10) + (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
+}
+
+/*
+ * Convert GHz frequency to IEEE channel number.
+ */
+int
+ath_hal_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags)
+{
+	if (flags & CHANNEL_2GHZ) {	/* 2GHz band */
+		if (freq == 2484)
+			return 14;
+		if (freq < 2484) {
+			if (ath_hal_isgsmsku(ah))
+				return mapgsm(freq, flags);
+			return ((int)freq - 2407) / 5;
+		} else
+			return 15 + ((freq - 2512) / 20);
+	} else if (flags & CHANNEL_5GHZ) {/* 5Ghz band */
+		if (ath_hal_ispublicsafetysku(ah) &&
+		    IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
+			return mappsb(freq, flags);
+		} else if ((flags & CHANNEL_A) && (freq <= 5000)) {
+			return (freq - 4000) / 5;
+		} else {
+			return (freq - 5000) / 5;
+		}
+	} else {			/* either, guess */
+		if (freq == 2484)
+			return 14;
+		if (freq < 2484) {
+			if (ath_hal_isgsmsku(ah))
+				return mapgsm(freq, flags);
+			return ((int)freq - 2407) / 5;
+		}
+		if (freq < 5000) {
+			if (ath_hal_ispublicsafetysku(ah) &&
+			    IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
+				return mappsb(freq, flags);
+			} else if (freq > 4900) {
+				return (freq - 4000) / 5;
+			} else {
+				return 15 + ((freq - 2512) / 20);
+			}
+		}
+		return (freq - 5000) / 5;
+	}
+}
+
+typedef enum {
+	WIRELESS_MODE_11a   = 0,
+	WIRELESS_MODE_TURBO = 1,
+	WIRELESS_MODE_11b   = 2,
+	WIRELESS_MODE_11g   = 3,
+	WIRELESS_MODE_108g  = 4,
+
+	WIRELESS_MODE_MAX
+} WIRELESS_MODE;
+
+static WIRELESS_MODE
+ath_hal_chan2wmode(struct ath_hal *ah, const HAL_CHANNEL *chan)
+{
+	if (IS_CHAN_CCK(chan))
+		return WIRELESS_MODE_11b;
+	if (IS_CHAN_G(chan))
+		return WIRELESS_MODE_11g;
+	if (IS_CHAN_108G(chan))
+		return WIRELESS_MODE_108g;
+	if (IS_CHAN_TURBO(chan))
+		return WIRELESS_MODE_TURBO;
+	return WIRELESS_MODE_11a;
+}
+
+/*
+ * Convert between microseconds and core system clocks.
+ */
+                                     /* 11a Turbo  11b  11g  108g */
+static const uint8_t CLOCK_RATE[]  = { 40,  80,   22,  44,   88  };
+
+u_int
+ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
+{
+	const HAL_CHANNEL *c = (const HAL_CHANNEL *) AH_PRIVATE(ah)->ah_curchan;
+	u_int clks;
+
+	/* NB: ah_curchan may be null when called attach time */
+	if (c != AH_NULL) {
+		clks = usecs * CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
+		if (IS_CHAN_HT40(c))
+			clks <<= 1;
+		else if (IS_CHAN_HALF_RATE(c))
+			clks >>= 1;
+		else if (IS_CHAN_QUARTER_RATE(c))
+			clks >>= 2;
+	} else
+		clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
+	return clks;
+}
+
+u_int
+ath_hal_mac_usec(struct ath_hal *ah, u_int clks)
+{
+	const HAL_CHANNEL *c = (const HAL_CHANNEL *) AH_PRIVATE(ah)->ah_curchan;
+	u_int usec;
+
+	/* NB: ah_curchan may be null when called attach time */
+	if (c != AH_NULL) {
+		usec = clks / CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
+		if (IS_CHAN_HT40(c))
+			usec >>= 1;
+		else if (IS_CHAN_HALF_RATE(c))
+			usec <<= 1;
+		else if (IS_CHAN_QUARTER_RATE(c))
+			usec <<= 2;
+	} else
+		usec = clks / CLOCK_RATE[WIRELESS_MODE_11b];
+	return usec;
+}
+
+/*
+ * Setup a h/w rate table's reverse lookup table and
+ * fill in ack durations.  This routine is called for
+ * each rate table returned through the ah_getRateTable
+ * method.  The reverse lookup tables are assumed to be
+ * initialized to zero (or at least the first entry).
+ * We use this as a key that indicates whether or not
+ * we've previously setup the reverse lookup table.
+ *
+ * XXX not reentrant, but shouldn't matter
+ */
+void
+ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt)
+{
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+	int i;
+
+	if (rt->rateCodeToIndex[0] != 0)	/* already setup */
+		return;
+	for (i = 0; i < N(rt->rateCodeToIndex); i++)
+		rt->rateCodeToIndex[i] = (uint8_t) -1;
+	for (i = 0; i < rt->rateCount; i++) {
+		uint8_t code = rt->info[i].rateCode;
+		uint8_t cix = rt->info[i].controlRate;
+
+		HALASSERT(code < N(rt->rateCodeToIndex));
+		rt->rateCodeToIndex[code] = i;
+		HALASSERT((code | rt->info[i].shortPreamble) <
+		    N(rt->rateCodeToIndex));
+		rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
+		/*
+		 * XXX for 11g the control rate to use for 5.5 and 11 Mb/s
+		 *     depends on whether they are marked as basic rates;
+		 *     the static tables are setup with an 11b-compatible
+		 *     2Mb/s rate which will work but is suboptimal
+		 */
+		rt->info[i].lpAckDuration = ath_hal_computetxtime(ah, rt,
+			WLAN_CTRL_FRAME_SIZE, cix, AH_FALSE);
+		rt->info[i].spAckDuration = ath_hal_computetxtime(ah, rt,
+			WLAN_CTRL_FRAME_SIZE, cix, AH_TRUE);
+	}
+#undef N
+}
+
+HAL_STATUS
+ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+	uint32_t capability, uint32_t *result)
+{
+	const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+
+	switch (type) {
+	case HAL_CAP_REG_DMN:		/* regulatory domain */
+		*result = AH_PRIVATE(ah)->ah_currentRD;
+		return HAL_OK;
+	case HAL_CAP_CIPHER:		/* cipher handled in hardware */
+	case HAL_CAP_TKIP_MIC:		/* handle TKIP MIC in hardware */
+		return HAL_ENOTSUPP;
+	case HAL_CAP_TKIP_SPLIT:	/* hardware TKIP uses split keys */
+		return HAL_ENOTSUPP;
+	case HAL_CAP_PHYCOUNTERS:	/* hardware PHY error counters */
+		return pCap->halHwPhyCounterSupport ? HAL_OK : HAL_ENXIO;
+	case HAL_CAP_WME_TKIPMIC:   /* hardware can do TKIP MIC when WMM is turned on */
+		return HAL_ENOTSUPP;
+	case HAL_CAP_DIVERSITY:		/* hardware supports fast diversity */
+		return HAL_ENOTSUPP;
+	case HAL_CAP_KEYCACHE_SIZE:	/* hardware key cache size */
+		*result =  pCap->halKeyCacheSize;
+		return HAL_OK;
+	case HAL_CAP_NUM_TXQUEUES:	/* number of hardware tx queues */
+		*result = pCap->halTotalQueues;
+		return HAL_OK;
+	case HAL_CAP_VEOL:		/* hardware supports virtual EOL */
+		return pCap->halVEOLSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_PSPOLL:		/* hardware PS-Poll support works */
+		return pCap->halPSPollBroken ? HAL_ENOTSUPP : HAL_OK;
+	case HAL_CAP_COMPRESSION:
+		return pCap->halCompressSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_BURST:
+		return pCap->halBurstSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_FASTFRAME:
+		return pCap->halFastFramesSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_DIAG:		/* hardware diagnostic support */
+		*result = AH_PRIVATE(ah)->ah_diagreg;
+		return HAL_OK;
+	case HAL_CAP_TXPOW:		/* global tx power limit  */
+		switch (capability) {
+		case 0:			/* facility is supported */
+			return HAL_OK;
+		case 1:			/* current limit */
+			*result = AH_PRIVATE(ah)->ah_powerLimit;
+			return HAL_OK;
+		case 2:			/* current max tx power */
+			*result = AH_PRIVATE(ah)->ah_maxPowerLevel;
+			return HAL_OK;
+		case 3:			/* scale factor */
+			*result = AH_PRIVATE(ah)->ah_tpScale;
+			return HAL_OK;
+		}
+		return HAL_ENOTSUPP;
+	case HAL_CAP_BSSIDMASK:		/* hardware supports bssid mask */
+		return pCap->halBssIdMaskSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_MCAST_KEYSRCH:	/* multicast frame keycache search */
+		return pCap->halMcastKeySrchSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_TSF_ADJUST:	/* hardware has beacon tsf adjust */
+		return HAL_ENOTSUPP;
+	case HAL_CAP_RFSILENT:		/* rfsilent support  */
+		switch (capability) {
+		case 0:			/* facility is supported */
+			return pCap->halRfSilentSupport ? HAL_OK : HAL_ENOTSUPP;
+		case 1:			/* current setting */
+			return AH_PRIVATE(ah)->ah_rfkillEnabled ?
+				HAL_OK : HAL_ENOTSUPP;
+		case 2:			/* rfsilent config */
+			*result = AH_PRIVATE(ah)->ah_rfsilent;
+			return HAL_OK;
+		}
+		return HAL_ENOTSUPP;
+	case HAL_CAP_11D:
+#ifdef AH_SUPPORT_11D
+		return HAL_OK;
+#else
+		return HAL_ENOTSUPP;
+#endif
+	case HAL_CAP_RXORN_FATAL:	/* HAL_INT_RXORN treated as fatal  */
+		return AH_PRIVATE(ah)->ah_rxornIsFatal ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_HT:
+		return pCap->halHTSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_TX_CHAINMASK:	/* mask of TX chains supported */
+		*result = pCap->halTxChainMask;
+		return HAL_OK;
+	case HAL_CAP_RX_CHAINMASK:	/* mask of RX chains supported */
+		*result = pCap->halRxChainMask;
+		return HAL_OK;
+	case HAL_CAP_RXTSTAMP_PREC:	/* rx desc tstamp precision (bits) */
+		*result = pCap->halTstampPrecision;
+		return HAL_OK;
+	default:
+		return HAL_EINVAL;
+	}
+}
+
+HAL_BOOL
+ath_hal_setcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+	uint32_t capability, uint32_t setting, HAL_STATUS *status)
+{
+
+	switch (type) {
+	case HAL_CAP_TXPOW:
+		switch (capability) {
+		case 3:
+			if (setting <= HAL_TP_SCALE_MIN) {
+				AH_PRIVATE(ah)->ah_tpScale = setting;
+				return AH_TRUE;
+			}
+			break;
+		}
+		break;
+	case HAL_CAP_RFSILENT:		/* rfsilent support  */
+		/*
+		 * NB: allow even if halRfSilentSupport is false
+		 *     in case the EEPROM is misprogrammed.
+		 */
+		switch (capability) {
+		case 1:			/* current setting */
+			AH_PRIVATE(ah)->ah_rfkillEnabled = (setting != 0);
+			return AH_TRUE;
+		case 2:			/* rfsilent config */
+			/* XXX better done per-chip for validation? */
+			AH_PRIVATE(ah)->ah_rfsilent = setting;
+			return AH_TRUE;
+		}
+		break;
+	case HAL_CAP_REG_DMN:		/* regulatory domain */
+		AH_PRIVATE(ah)->ah_currentRD = setting;
+		return AH_TRUE;
+	case HAL_CAP_RXORN_FATAL:	/* HAL_INT_RXORN treated as fatal  */
+		AH_PRIVATE(ah)->ah_rxornIsFatal = setting;
+		return AH_TRUE;
+	default:
+		break;
+	}
+	if (status)
+		*status = HAL_EINVAL;
+	return AH_FALSE;
+}
+
+/* 
+ * Common support for getDiagState method.
+ */
+
+static u_int
+ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs,
+	void *dstbuf, int space)
+{
+	uint32_t *dp = dstbuf;
+	int i;
+
+	for (i = 0; space >= 2*sizeof(uint32_t); i++) {
+		u_int r = regs[i].start;
+		u_int e = regs[i].end;
+		*dp++ = (r<<16) | e;
+		space -= sizeof(uint32_t);
+		do {
+			*dp++ = OS_REG_READ(ah, r);
+			r += sizeof(uint32_t);
+			space -= sizeof(uint32_t);
+		} while (r <= e && space >= sizeof(uint32_t));
+	}
+	return (char *) dp - (char *) dstbuf;
+}
+
+HAL_BOOL
+ath_hal_getdiagstate(struct ath_hal *ah, int request,
+	const void *args, uint32_t argsize,
+	void **result, uint32_t *resultsize)
+{
+	switch (request) {
+	case HAL_DIAG_REVS:
+		*result = &AH_PRIVATE(ah)->ah_devid;
+		*resultsize = sizeof(HAL_REVS);
+		return AH_TRUE;
+	case HAL_DIAG_REGS:
+		*resultsize = ath_hal_getregdump(ah, args, *result,*resultsize);
+		return AH_TRUE;
+	case HAL_DIAG_FATALERR:
+		*result = &AH_PRIVATE(ah)->ah_fatalState[0];
+		*resultsize = sizeof(AH_PRIVATE(ah)->ah_fatalState);
+		return AH_TRUE;
+	case HAL_DIAG_EEREAD:
+		if (argsize != sizeof(uint16_t))
+			return AH_FALSE;
+		if (!ath_hal_eepromRead(ah, *(const uint16_t *)args, *result))
+			return AH_FALSE;
+		*resultsize = sizeof(uint16_t);
+		return AH_TRUE;
+#ifdef AH_PRIVATE_DIAG
+	case HAL_DIAG_SETKEY: {
+		const HAL_DIAG_KEYVAL *dk;
+
+		if (argsize != sizeof(HAL_DIAG_KEYVAL))
+			return AH_FALSE;
+		dk = (const HAL_DIAG_KEYVAL *)args;
+		return ah->ah_setKeyCacheEntry(ah, dk->dk_keyix,
+			&dk->dk_keyval, dk->dk_mac, dk->dk_xor);
+	}
+	case HAL_DIAG_RESETKEY:
+		if (argsize != sizeof(uint16_t))
+			return AH_FALSE;
+		return ah->ah_resetKeyCacheEntry(ah, *(const uint16_t *)args);
+#ifdef AH_SUPPORT_WRITE_EEPROM
+	case HAL_DIAG_EEWRITE: {
+		const HAL_DIAG_EEVAL *ee;
+		if (argsize != sizeof(HAL_DIAG_EEVAL))
+			return AH_FALSE;
+		ee = (const HAL_DIAG_EEVAL *)args;
+		return ath_hal_eepromWrite(ah, ee->ee_off, ee->ee_data);
+	}
+#endif /* AH_SUPPORT_WRITE_EEPROM */
+#endif /* AH_PRIVATE_DIAG */
+	case HAL_DIAG_11NCOMPAT:
+		if (argsize == 0) {
+			*resultsize = sizeof(uint32_t);
+			*((uint32_t *)(*result)) =
+				AH_PRIVATE(ah)->ah_11nCompat;
+		} else if (argsize == sizeof(uint32_t)) {
+			AH_PRIVATE(ah)->ah_11nCompat = *(const uint32_t *)args;
+		} else
+			return AH_FALSE;
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Set the properties of the tx queue with the parameters
+ * from qInfo.
+ */
+HAL_BOOL
+ath_hal_setTxQProps(struct ath_hal *ah,
+	HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo)
+{
+	uint32_t cw;
+
+	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
+		    "%s: inactive queue\n", __func__);
+		return AH_FALSE;
+	}
+	/* XXX validate parameters */
+	qi->tqi_ver = qInfo->tqi_ver;
+	qi->tqi_subtype = qInfo->tqi_subtype;
+	qi->tqi_qflags = qInfo->tqi_qflags;
+	qi->tqi_priority = qInfo->tqi_priority;
+	if (qInfo->tqi_aifs != HAL_TXQ_USEDEFAULT)
+		qi->tqi_aifs = AH_MIN(qInfo->tqi_aifs, 255);
+	else
+		qi->tqi_aifs = INIT_AIFS;
+	if (qInfo->tqi_cwmin != HAL_TXQ_USEDEFAULT) {
+		cw = AH_MIN(qInfo->tqi_cwmin, 1024);
+		/* make sure that the CWmin is of the form (2^n - 1) */
+		qi->tqi_cwmin = 1;
+		while (qi->tqi_cwmin < cw)
+			qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
+	} else
+		qi->tqi_cwmin = qInfo->tqi_cwmin;
+	if (qInfo->tqi_cwmax != HAL_TXQ_USEDEFAULT) {
+		cw = AH_MIN(qInfo->tqi_cwmax, 1024);
+		/* make sure that the CWmax is of the form (2^n - 1) */
+		qi->tqi_cwmax = 1;
+		while (qi->tqi_cwmax < cw)
+			qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
+	} else
+		qi->tqi_cwmax = INIT_CWMAX;
+	/* Set retry limit values */
+	if (qInfo->tqi_shretry != 0)
+		qi->tqi_shretry = AH_MIN(qInfo->tqi_shretry, 15);
+	else
+		qi->tqi_shretry = INIT_SH_RETRY;
+	if (qInfo->tqi_lgretry != 0)
+		qi->tqi_lgretry = AH_MIN(qInfo->tqi_lgretry, 15);
+	else
+		qi->tqi_lgretry = INIT_LG_RETRY;
+	qi->tqi_cbrPeriod = qInfo->tqi_cbrPeriod;
+	qi->tqi_cbrOverflowLimit = qInfo->tqi_cbrOverflowLimit;
+	qi->tqi_burstTime = qInfo->tqi_burstTime;
+	qi->tqi_readyTime = qInfo->tqi_readyTime;
+
+	switch (qInfo->tqi_subtype) {
+	case HAL_WME_UPSD:
+		if (qi->tqi_type == HAL_TX_QUEUE_DATA)
+			qi->tqi_intFlags = HAL_TXQ_USE_LOCKOUT_BKOFF_DIS;
+		break;
+	default:
+		break;		/* NB: silence compiler */
+	}
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ath_hal_getTxQProps(struct ath_hal *ah,
+	HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi)
+{
+	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
+		    "%s: inactive queue\n", __func__);
+		return AH_FALSE;
+	}
+
+	qInfo->tqi_qflags = qi->tqi_qflags;
+	qInfo->tqi_ver = qi->tqi_ver;
+	qInfo->tqi_subtype = qi->tqi_subtype;
+	qInfo->tqi_qflags = qi->tqi_qflags;
+	qInfo->tqi_priority = qi->tqi_priority;
+	qInfo->tqi_aifs = qi->tqi_aifs;
+	qInfo->tqi_cwmin = qi->tqi_cwmin;
+	qInfo->tqi_cwmax = qi->tqi_cwmax;
+	qInfo->tqi_shretry = qi->tqi_shretry;
+	qInfo->tqi_lgretry = qi->tqi_lgretry;
+	qInfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
+	qInfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
+	qInfo->tqi_burstTime = qi->tqi_burstTime;
+	qInfo->tqi_readyTime = qi->tqi_readyTime;
+	return AH_TRUE;
+}
+
+                                     /* 11a Turbo  11b  11g  108g */
+static const int16_t NOISE_FLOOR[] = { -96, -93,  -98, -96,  -93 };
+
+/*
+ * Read the current channel noise floor and return.
+ * If nf cal hasn't finished, channel noise floor should be 0
+ * and we return a nominal value based on band and frequency.
+ *
+ * NB: This is a private routine used by per-chip code to
+ *     implement the ah_getChanNoise method.
+ */
+int16_t
+ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	HAL_CHANNEL_INTERNAL *ichan;
+
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		return 0;
+	}
+	if (ichan->rawNoiseFloor == 0) {
+		WIRELESS_MODE mode = ath_hal_chan2wmode(ah, chan);
+
+		HALASSERT(mode < WIRELESS_MODE_MAX);
+		return NOISE_FLOOR[mode] + ath_hal_getNfAdjust(ah, ichan);
+	} else
+		return ichan->rawNoiseFloor + ichan->noiseFloorAdjust;
+}
+
+/*
+ * Process all valid raw noise floors into the dBm noise floor values.
+ * Though our device has no reference for a dBm noise floor, we perform
+ * a relative minimization of NF's based on the lowest NF found across a
+ * channel scan.
+ */
+void
+ath_hal_process_noisefloor(struct ath_hal *ah)
+{
+	HAL_CHANNEL_INTERNAL *c;
+	int16_t correct2, correct5;
+	int16_t lowest2, lowest5;
+	int i;
+
+	/* 
+	 * Find the lowest 2GHz and 5GHz noise floor values after adjusting
+	 * for statistically recorded NF/channel deviation.
+	 */
+	correct2 = lowest2 = 0;
+	correct5 = lowest5 = 0;
+	for (i = 0; i < AH_PRIVATE(ah)->ah_nchan; i++) {
+		WIRELESS_MODE mode;
+		int16_t nf;
+
+		c = &AH_PRIVATE(ah)->ah_channels[i];
+		if (c->rawNoiseFloor >= 0)
+			continue;
+		mode = ath_hal_chan2wmode(ah, (HAL_CHANNEL *) c);
+		HALASSERT(mode < WIRELESS_MODE_MAX);
+		nf = c->rawNoiseFloor + NOISE_FLOOR[mode] +
+			ath_hal_getNfAdjust(ah, c);
+		if (IS_CHAN_5GHZ(c)) {
+			if (nf < lowest5) { 
+				lowest5 = nf;
+				correct5 = NOISE_FLOOR[mode] -
+				    (c->rawNoiseFloor + ath_hal_getNfAdjust(ah, c));
+			}
+		} else {
+			if (nf < lowest2) { 
+				lowest2 = nf;
+				correct2 = NOISE_FLOOR[mode] -
+				    (c->rawNoiseFloor + ath_hal_getNfAdjust(ah, c));
+			}
+		}
+	}
+
+	/* Correct the channels to reach the expected NF value */
+	for (i = 0; i < AH_PRIVATE(ah)->ah_nchan; i++) {
+		c = &AH_PRIVATE(ah)->ah_channels[i];
+		if (c->rawNoiseFloor >= 0)
+			continue;
+		/* Apply correction factor */
+		c->noiseFloorAdjust = ath_hal_getNfAdjust(ah, c) +
+			(IS_CHAN_5GHZ(c) ? correct5 : correct2);
+		HALDEBUG(ah, HAL_DEBUG_NFCAL, "%u/0x%x raw nf %d adjust %d\n",
+		    c->channel, c->channelFlags, c->rawNoiseFloor,
+		    c->noiseFloorAdjust);
+	}
+}
+
+/*
+ * INI support routines.
+ */
+
+int
+ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+	int col, int regWr)
+{
+	int r;
+
+	for (r = 0; r < ia->rows; r++) {
+		OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0),
+		    HAL_INI_VAL(ia, r, col));
+		DMA_YIELD(regWr);
+	}
+	return regWr;
+}
+
+void
+ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, int col)
+{
+	int r;
+
+	for (r = 0; r < ia->rows; r++)
+		data[r] = HAL_INI_VAL(ia, r, col);
+}
+
+int
+ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+	const uint32_t data[], int regWr)
+{
+	int r;
+
+	for (r = 0; r < ia->rows; r++) {
+		OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0), data[r]);
+		DMA_YIELD(regWr);
+	}
+	return regWr;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah.h b/sys/dev/netif/ath/hal/ath_hal/ah.h
new file mode 100644
index 0000000..709a100
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah.h
@@ -0,0 +1,908 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah.h,v 1.15 2008/11/15 03:43:50 sam Exp $
+ */
+
+#ifndef _ATH_AH_H_
+#define _ATH_AH_H_
+/*
+ * Atheros Hardware Access Layer
+ *
+ * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
+ * structure for use with the device.  Hardware-related operations that
+ * follow must call back into the HAL through interface, supplying the
+ * reference as the first parameter.
+ */
+/*
+ * Bus i/o type definitions.  We define a platform-independent
+ * set of types that are mapped to platform-dependent data for
+ * register read/write operations.  We use types that are large
+ * enough to hold a pointer; smaller data should fit and only
+ * require type coercion to work.  Larger data can be stored
+ * elsewhere and a reference passed for the bus tag and/or handle.
+ */
+typedef void* HAL_SOFTC;                /* pointer to driver/OS state */
+typedef void* HAL_BUS_TAG;              /* opaque bus i/o id tag */
+typedef void* HAL_BUS_HANDLE;           /* opaque bus i/o handle */
+#include "ah_osdep.h"
+/*
+ * __ahdecl is analogous to _cdecl; it defines the calling
+ * convention used within the HAL.  For most systems this
+ * can just default to be empty and the compiler will (should)
+ * use _cdecl.  For systems where _cdecl is not compatible this
+ * must be defined.  See linux/ah_osdep.h for an example.
+ */
+#ifndef __ahdecl
+#define __ahdecl
+#endif
+
+/*
+ * Status codes that may be returned by the HAL.  Note that
+ * interfaces that return a status code set it only when an
+ * error occurs--i.e. you cannot check it for success.
+ */
+typedef enum {
+	HAL_OK		= 0,	/* No error */
+	HAL_ENXIO	= 1,	/* No hardware present */
+	HAL_ENOMEM	= 2,	/* Memory allocation failed */
+	HAL_EIO		= 3,	/* Hardware didn't respond as expected */
+	HAL_EEMAGIC	= 4,	/* EEPROM magic number invalid */
+	HAL_EEVERSION	= 5,	/* EEPROM version invalid */
+	HAL_EELOCKED	= 6,	/* EEPROM unreadable */
+	HAL_EEBADSUM	= 7,	/* EEPROM checksum invalid */
+	HAL_EEREAD	= 8,	/* EEPROM read problem */
+	HAL_EEBADMAC	= 9,	/* EEPROM mac address invalid */
+	HAL_EESIZE	= 10,	/* EEPROM size not supported */
+	HAL_EEWRITE	= 11,	/* Attempt to change write-locked EEPROM */
+	HAL_EINVAL	= 12,	/* Invalid parameter to function */
+	HAL_ENOTSUPP	= 13,	/* Hardware revision not supported */
+	HAL_ESELFTEST	= 14,	/* Hardware self-test failed */
+	HAL_EINPROGRESS	= 15,	/* Operation incomplete */
+} HAL_STATUS;
+
+typedef enum {
+	AH_FALSE = 0,		/* NB: lots of code assumes false is zero */
+	AH_TRUE  = 1,
+} HAL_BOOL;
+
+typedef enum {
+	HAL_CAP_REG_DMN		= 0,	/* current regulatory domain */
+	HAL_CAP_CIPHER		= 1,	/* hardware supports cipher */
+	HAL_CAP_TKIP_MIC	= 2,	/* handle TKIP MIC in hardware */
+	HAL_CAP_TKIP_SPLIT	= 3,	/* hardware TKIP uses split keys */
+	HAL_CAP_PHYCOUNTERS	= 4,	/* hardware PHY error counters */
+	HAL_CAP_DIVERSITY	= 5,	/* hardware supports fast diversity */
+	HAL_CAP_KEYCACHE_SIZE	= 6,	/* number of entries in key cache */
+	HAL_CAP_NUM_TXQUEUES	= 7,	/* number of hardware xmit queues */
+	HAL_CAP_VEOL		= 9,	/* hardware supports virtual EOL */
+	HAL_CAP_PSPOLL		= 10,	/* hardware has working PS-Poll support */
+	HAL_CAP_DIAG		= 11,	/* hardware diagnostic support */
+	HAL_CAP_COMPRESSION	= 12,	/* hardware supports compression */
+	HAL_CAP_BURST		= 13,	/* hardware supports packet bursting */
+	HAL_CAP_FASTFRAME	= 14,	/* hardware supoprts fast frames */
+	HAL_CAP_TXPOW		= 15,	/* global tx power limit  */
+	HAL_CAP_TPC		= 16,	/* per-packet tx power control  */
+	HAL_CAP_PHYDIAG		= 17,	/* hardware phy error diagnostic */
+	HAL_CAP_BSSIDMASK	= 18,	/* hardware supports bssid mask */
+	HAL_CAP_MCAST_KEYSRCH	= 19,	/* hardware has multicast key search */
+	HAL_CAP_TSF_ADJUST	= 20,	/* hardware has beacon tsf adjust */
+	/* 21 was HAL_CAP_XR */
+	HAL_CAP_WME_TKIPMIC 	= 22,   /* hardware can support TKIP MIC when WMM is turned on */
+	/* 23 was HAL_CAP_CHAN_HALFRATE */
+	/* 24 was HAL_CAP_CHAN_QUARTERRATE */
+	HAL_CAP_RFSILENT	= 25,	/* hardware has rfsilent support  */
+	HAL_CAP_TPC_ACK		= 26,	/* ack txpower with per-packet tpc */
+	HAL_CAP_TPC_CTS		= 27,	/* cts txpower with per-packet tpc */
+	HAL_CAP_11D		= 28,   /* 11d beacon support for changing cc */
+	HAL_CAP_INTMIT		= 29,	/* interference mitigation */
+	HAL_CAP_RXORN_FATAL	= 30,	/* HAL_INT_RXORN treated as fatal */
+	HAL_CAP_HT		= 31,   /* hardware can support HT */
+	HAL_CAP_TX_CHAINMASK	= 32,	/* mask of TX chains supported */
+	HAL_CAP_RX_CHAINMASK	= 33,	/* mask of RX chains supported */
+	HAL_CAP_RXTSTAMP_PREC	= 34,	/* rx desc tstamp precision (bits) */
+	HAL_CAP_BB_HANG		= 35,	/* can baseband hang */
+	HAL_CAP_MAC_HANG	= 36,	/* can MAC hang */
+} HAL_CAPABILITY_TYPE;
+
+/* 
+ * "States" for setting the LED.  These correspond to
+ * the possible 802.11 operational states and there may
+ * be a many-to-one mapping between these states and the
+ * actual hardware state for the LED's (i.e. the hardware
+ * may have fewer states).
+ */
+typedef enum {
+	HAL_LED_INIT	= 0,
+	HAL_LED_SCAN	= 1,
+	HAL_LED_AUTH	= 2,
+	HAL_LED_ASSOC	= 3,
+	HAL_LED_RUN	= 4
+} HAL_LED_STATE;
+
+/*
+ * Transmit queue types/numbers.  These are used to tag
+ * each transmit queue in the hardware and to identify a set
+ * of transmit queues for operations such as start/stop dma.
+ */
+typedef enum {
+	HAL_TX_QUEUE_INACTIVE	= 0,		/* queue is inactive/unused */
+	HAL_TX_QUEUE_DATA	= 1,		/* data xmit q's */
+	HAL_TX_QUEUE_BEACON	= 2,		/* beacon xmit q */
+	HAL_TX_QUEUE_CAB	= 3,		/* "crap after beacon" xmit q */
+	HAL_TX_QUEUE_UAPSD	= 4,		/* u-apsd power save xmit q */
+} HAL_TX_QUEUE;
+
+#define	HAL_NUM_TX_QUEUES	10		/* max possible # of queues */
+
+/*
+ * Transmit queue subtype.  These map directly to
+ * WME Access Categories (except for UPSD).  Refer
+ * to Table 5 of the WME spec.
+ */
+typedef enum {
+	HAL_WME_AC_BK	= 0,			/* background access category */
+	HAL_WME_AC_BE	= 1, 			/* best effort access category*/
+	HAL_WME_AC_VI	= 2,			/* video access category */
+	HAL_WME_AC_VO	= 3,			/* voice access category */
+	HAL_WME_UPSD	= 4,			/* uplink power save */
+} HAL_TX_QUEUE_SUBTYPE;
+
+/*
+ * Transmit queue flags that control various
+ * operational parameters.
+ */
+typedef enum {
+	/*
+	 * Per queue interrupt enables.  When set the associated
+	 * interrupt may be delivered for packets sent through
+	 * the queue.  Without these enabled no interrupts will
+	 * be delivered for transmits through the queue.
+	 */
+	HAL_TXQ_TXOKINT_ENABLE	   = 0x0001,	/* enable TXOK interrupt */
+	HAL_TXQ_TXERRINT_ENABLE	   = 0x0001,	/* enable TXERR interrupt */
+	HAL_TXQ_TXDESCINT_ENABLE   = 0x0002,	/* enable TXDESC interrupt */
+	HAL_TXQ_TXEOLINT_ENABLE	   = 0x0004,	/* enable TXEOL interrupt */
+	HAL_TXQ_TXURNINT_ENABLE	   = 0x0008,	/* enable TXURN interrupt */
+	/*
+	 * Enable hardware compression for packets sent through
+	 * the queue.  The compression buffer must be setup and
+	 * packets must have a key entry marked in the tx descriptor.
+	 */
+	HAL_TXQ_COMPRESSION_ENABLE  = 0x0010,	/* enable h/w compression */
+	/*
+	 * Disable queue when veol is hit or ready time expires.
+	 * By default the queue is disabled only on reaching the
+	 * physical end of queue (i.e. a null link ptr in the
+	 * descriptor chain).
+	 */
+	HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
+	/*
+	 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
+	 * event.  Frames will be transmitted only when this timer
+	 * fires, e.g to transmit a beacon in ap or adhoc modes.
+	 */
+	HAL_TXQ_DBA_GATED	    = 0x0040,	/* schedule based on DBA */
+	/*
+	 * Each transmit queue has a counter that is incremented
+	 * each time the queue is enabled and decremented when
+	 * the list of frames to transmit is traversed (or when
+	 * the ready time for the queue expires).  This counter
+	 * must be non-zero for frames to be scheduled for
+	 * transmission.  The following controls disable bumping
+	 * this counter under certain conditions.  Typically this
+	 * is used to gate frames based on the contents of another
+	 * queue (e.g. CAB traffic may only follow a beacon frame).
+	 * These are meaningful only when frames are scheduled
+	 * with a non-ASAP policy (e.g. DBA-gated).
+	 */
+	HAL_TXQ_CBR_DIS_QEMPTY	    = 0x0080,	/* disable on this q empty */
+	HAL_TXQ_CBR_DIS_BEMPTY	    = 0x0100,	/* disable on beacon q empty */
+
+	/*
+	 * Fragment burst backoff policy.  Normally the no backoff
+	 * is done after a successful transmission, the next fragment
+	 * is sent at SIFS.  If this flag is set backoff is done
+	 * after each fragment, regardless whether it was ack'd or
+	 * not, after the backoff count reaches zero a normal channel
+	 * access procedure is done before the next transmit (i.e.
+	 * wait AIFS instead of SIFS).
+	 */
+	HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
+	/*
+	 * Disable post-tx backoff following each frame.
+	 */
+	HAL_TXQ_BACKOFF_DISABLE	    = 0x00010000, /* disable post backoff  */
+	/*
+	 * DCU arbiter lockout control.  This controls how
+	 * lower priority tx queues are handled with respect to
+	 * to a specific queue when multiple queues have frames
+	 * to send.  No lockout means lower priority queues arbitrate
+	 * concurrently with this queue.  Intra-frame lockout
+	 * means lower priority queues are locked out until the
+	 * current frame transmits (e.g. including backoffs and bursting).
+	 * Global lockout means nothing lower can arbitrary so
+	 * long as there is traffic activity on this queue (frames,
+	 * backoff, etc).
+	 */
+	HAL_TXQ_ARB_LOCKOUT_INTRA   = 0x00020000, /* intra-frame lockout */
+	HAL_TXQ_ARB_LOCKOUT_GLOBAL  = 0x00040000, /* full lockout s */
+
+	HAL_TXQ_IGNORE_VIRTCOL	    = 0x00080000, /* ignore virt collisions */
+	HAL_TXQ_SEQNUM_INC_DIS	    = 0x00100000, /* disable seqnum increment */
+} HAL_TX_QUEUE_FLAGS;
+
+typedef struct {
+	uint32_t	tqi_ver;		/* hal TXQ version */
+	HAL_TX_QUEUE_SUBTYPE tqi_subtype;	/* subtype if applicable */
+	HAL_TX_QUEUE_FLAGS tqi_qflags;		/* flags (see above) */
+	uint32_t	tqi_priority;		/* (not used) */
+	uint32_t	tqi_aifs;		/* aifs */
+	uint32_t	tqi_cwmin;		/* cwMin */
+	uint32_t	tqi_cwmax;		/* cwMax */
+	uint16_t	tqi_shretry;		/* rts retry limit */
+	uint16_t	tqi_lgretry;		/* long retry limit (not used)*/
+	uint32_t	tqi_cbrPeriod;		/* CBR period (us) */
+	uint32_t	tqi_cbrOverflowLimit;	/* threshold for CBROVF int */
+	uint32_t	tqi_burstTime;		/* max burst duration (us) */
+	uint32_t	tqi_readyTime;		/* frame schedule time (us) */
+	uint32_t	tqi_compBuf;		/* comp buffer phys addr */
+} HAL_TXQ_INFO;
+
+#define HAL_TQI_NONVAL 0xffff
+
+/* token to use for aifs, cwmin, cwmax */
+#define	HAL_TXQ_USEDEFAULT	((uint32_t) -1)
+
+/* compression definitions */
+#define HAL_COMP_BUF_MAX_SIZE           9216            /* 9K */
+#define HAL_COMP_BUF_ALIGN_SIZE         512
+
+/*
+ * Transmit packet types.  This belongs in ah_desc.h, but
+ * is here so we can give a proper type to various parameters
+ * (and not require everyone include the file).
+ *
+ * NB: These values are intentionally assigned for
+ *     direct use when setting up h/w descriptors.
+ */
+typedef enum {
+	HAL_PKT_TYPE_NORMAL	= 0,
+	HAL_PKT_TYPE_ATIM	= 1,
+	HAL_PKT_TYPE_PSPOLL	= 2,
+	HAL_PKT_TYPE_BEACON	= 3,
+	HAL_PKT_TYPE_PROBE_RESP	= 4,
+	HAL_PKT_TYPE_CHIRP	= 5,
+	HAL_PKT_TYPE_GRP_POLL	= 6,
+	HAL_PKT_TYPE_AMPDU	= 7,
+} HAL_PKT_TYPE;
+
+/* Rx Filter Frame Types */
+typedef enum {
+	HAL_RX_FILTER_UCAST	= 0x00000001,	/* Allow unicast frames */
+	HAL_RX_FILTER_MCAST	= 0x00000002,	/* Allow multicast frames */
+	HAL_RX_FILTER_BCAST	= 0x00000004,	/* Allow broadcast frames */
+	HAL_RX_FILTER_CONTROL	= 0x00000008,	/* Allow control frames */
+	HAL_RX_FILTER_BEACON	= 0x00000010,	/* Allow beacon frames */
+	HAL_RX_FILTER_PROM	= 0x00000020,	/* Promiscuous mode */
+	HAL_RX_FILTER_PROBEREQ	= 0x00000080,	/* Allow probe request frames */
+	HAL_RX_FILTER_PHYERR	= 0x00000100,	/* Allow phy errors */
+	HAL_RX_FILTER_PHYRADAR	= 0x00000200,	/* Allow phy radar errors */
+	HAL_RX_FILTER_COMPBAR	= 0x00000400,	/* Allow compressed BAR */
+} HAL_RX_FILTER;
+
+typedef enum {
+	HAL_PM_AWAKE		= 0,
+	HAL_PM_FULL_SLEEP	= 1,
+	HAL_PM_NETWORK_SLEEP	= 2,
+	HAL_PM_UNDEFINED	= 3
+} HAL_POWER_MODE;
+
+/*
+ * NOTE WELL:
+ * These are mapped to take advantage of the common locations for many of
+ * the bits on all of the currently supported MAC chips. This is to make
+ * the ISR as efficient as possible, while still abstracting HW differences.
+ * When new hardware breaks this commonality this enumerated type, as well
+ * as the HAL functions using it, must be modified. All values are directly
+ * mapped unless commented otherwise.
+ */
+typedef enum {
+	HAL_INT_RX	= 0x00000001,	/* Non-common mapping */
+	HAL_INT_RXDESC	= 0x00000002,
+	HAL_INT_RXNOFRM	= 0x00000008,
+	HAL_INT_RXEOL	= 0x00000010,
+	HAL_INT_RXORN	= 0x00000020,
+	HAL_INT_TX	= 0x00000040,	/* Non-common mapping */
+	HAL_INT_TXDESC	= 0x00000080,
+	HAL_INT_TXURN	= 0x00000800,
+	HAL_INT_MIB	= 0x00001000,
+	HAL_INT_RXPHY	= 0x00004000,
+	HAL_INT_RXKCM	= 0x00008000,
+	HAL_INT_SWBA	= 0x00010000,
+	HAL_INT_BMISS	= 0x00040000,
+	HAL_INT_BNR	= 0x00100000,	/* Non-common mapping */
+	HAL_INT_TIM	= 0x00200000,	/* Non-common mapping */
+	HAL_INT_DTIM	= 0x00400000,	/* Non-common mapping */
+	HAL_INT_DTIMSYNC= 0x00800000,	/* Non-common mapping */
+	HAL_INT_GPIO	= 0x01000000,
+	HAL_INT_CABEND	= 0x02000000,	/* Non-common mapping */
+	HAL_INT_TSFOOR	= 0x04000000,	/* Non-common mapping */
+	HAL_INT_CST	= 0x10000000,	/* Non-common mapping */
+	HAL_INT_GTT	= 0x20000000,	/* Non-common mapping */
+	HAL_INT_FATAL	= 0x40000000,	/* Non-common mapping */
+#define	HAL_INT_GLOBAL	0x80000000	/* Set/clear IER */
+	HAL_INT_BMISC	= HAL_INT_TIM
+			| HAL_INT_DTIM
+			| HAL_INT_DTIMSYNC
+			| HAL_INT_CABEND,
+
+	/* Interrupt bits that map directly to ISR/IMR bits */
+	HAL_INT_COMMON  = HAL_INT_RXNOFRM
+			| HAL_INT_RXDESC
+			| HAL_INT_RXEOL
+			| HAL_INT_RXORN
+			| HAL_INT_TXURN
+			| HAL_INT_TXDESC
+			| HAL_INT_MIB
+			| HAL_INT_RXPHY
+			| HAL_INT_RXKCM
+			| HAL_INT_SWBA
+			| HAL_INT_BMISS
+			| HAL_INT_GPIO,
+} HAL_INT;
+
+typedef enum {
+	HAL_RFGAIN_INACTIVE		= 0,
+	HAL_RFGAIN_READ_REQUESTED	= 1,
+	HAL_RFGAIN_NEED_CHANGE		= 2
+} HAL_RFGAIN;
+
+/*
+ * Channels are specified by frequency.
+ */
+typedef struct {
+	uint32_t	channelFlags;	/* see below */
+	uint16_t	channel;	/* setting in Mhz */
+	uint8_t		privFlags;
+	int8_t		maxRegTxPower;	/* max regulatory tx power in dBm */
+	int8_t		maxTxPower;	/* max true tx power in 0.5 dBm */
+	int8_t		minTxPower;	/* min true tx power in 0.5 dBm */
+} HAL_CHANNEL;
+
+/* channelFlags */
+#define	CHANNEL_CW_INT	0x00002	/* CW interference detected on channel */
+#define	CHANNEL_TURBO	0x00010	/* Turbo Channel */
+#define	CHANNEL_CCK	0x00020	/* CCK channel */
+#define	CHANNEL_OFDM	0x00040	/* OFDM channel */
+#define	CHANNEL_2GHZ	0x00080	/* 2 GHz spectrum channel */
+#define	CHANNEL_5GHZ	0x00100	/* 5 GHz spectrum channel */
+#define	CHANNEL_PASSIVE	0x00200	/* Only passive scan allowed in the channel */
+#define	CHANNEL_DYN	0x00400	/* dynamic CCK-OFDM channel */
+#define	CHANNEL_STURBO	0x02000	/* Static turbo, no 11a-only usage */
+#define	CHANNEL_HALF    0x04000 /* Half rate channel */
+#define	CHANNEL_QUARTER 0x08000 /* Quarter rate channel */
+#define	CHANNEL_HT20	0x10000 /* 11n 20MHZ channel */ 
+#define	CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ channel w/ ext chan above */
+#define	CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ channel w/ ext chan below */
+
+/* privFlags */
+#define CHANNEL_INTERFERENCE   	0x01 /* Software use: channel interference 
+				        used for as AR as well as RADAR 
+				        interference detection */
+#define CHANNEL_DFS		0x02 /* DFS required on channel */
+#define CHANNEL_4MS_LIMIT	0x04 /* 4msec packet limit on this channel */
+#define CHANNEL_DFS_CLEAR	0x08 /* if channel has been checked for DFS */
+
+#define	CHANNEL_A	(CHANNEL_5GHZ|CHANNEL_OFDM)
+#define	CHANNEL_B	(CHANNEL_2GHZ|CHANNEL_CCK)
+#define	CHANNEL_PUREG	(CHANNEL_2GHZ|CHANNEL_OFDM)
+#ifdef notdef
+#define	CHANNEL_G	(CHANNEL_2GHZ|CHANNEL_DYN)
+#else
+#define	CHANNEL_G	(CHANNEL_2GHZ|CHANNEL_OFDM)
+#endif
+#define	CHANNEL_T	(CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define CHANNEL_ST	(CHANNEL_T|CHANNEL_STURBO)
+#define	CHANNEL_108G	(CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define	CHANNEL_108A	CHANNEL_T
+#define	CHANNEL_G_HT20		(CHANNEL_G|CHANNEL_HT20)
+#define	CHANNEL_A_HT20		(CHANNEL_A|CHANNEL_HT20)
+#define	CHANNEL_G_HT40PLUS	(CHANNEL_G|CHANNEL_HT40PLUS)
+#define	CHANNEL_G_HT40MINUS	(CHANNEL_G|CHANNEL_HT40MINUS)
+#define	CHANNEL_A_HT40PLUS	(CHANNEL_A|CHANNEL_HT40PLUS)
+#define	CHANNEL_A_HT40MINUS	(CHANNEL_A|CHANNEL_HT40MINUS)
+#define	CHANNEL_ALL \
+	(CHANNEL_OFDM | CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | \
+	 CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
+#define	CHANNEL_ALL_NOTURBO 	(CHANNEL_ALL &~ CHANNEL_TURBO)
+
+#define HAL_ANTENNA_MIN_MODE  0
+#define HAL_ANTENNA_FIXED_A   1
+#define HAL_ANTENNA_FIXED_B   2
+#define HAL_ANTENNA_MAX_MODE  3
+
+typedef struct {
+	uint32_t	ackrcv_bad;
+	uint32_t	rts_bad;
+	uint32_t	rts_good;
+	uint32_t	fcs_bad;
+	uint32_t	beacons;
+} HAL_MIB_STATS;
+
+typedef uint16_t HAL_CTRY_CODE;		/* country code */
+typedef uint16_t HAL_REG_DOMAIN;		/* regulatory domain code */
+
+enum {
+	CTRY_DEBUG	= 0x1ff,		/* debug country code */
+	CTRY_DEFAULT	= 0			/* default country code */
+};
+
+enum {
+	HAL_MODE_11A	= 0x001,		/* 11a channels */
+	HAL_MODE_TURBO	= 0x002,		/* 11a turbo-only channels */
+	HAL_MODE_11B	= 0x004,		/* 11b channels */
+	HAL_MODE_PUREG	= 0x008,		/* 11g channels (OFDM only) */
+#ifdef notdef
+	HAL_MODE_11G	= 0x010,		/* 11g channels (OFDM/CCK) */
+#else
+	HAL_MODE_11G	= 0x008,		/* XXX historical */
+#endif
+	HAL_MODE_108G	= 0x020,		/* 11g+Turbo channels */
+	HAL_MODE_108A	= 0x040,		/* 11a+Turbo channels */
+	HAL_MODE_11A_HALF_RATE = 0x200,		/* 11a half width channels */
+	HAL_MODE_11A_QUARTER_RATE = 0x400,	/* 11a quarter width channels */
+	HAL_MODE_11G_HALF_RATE = 0x800,		/* 11g half width channels */
+	HAL_MODE_11G_QUARTER_RATE = 0x1000,	/* 11g quarter width channels */
+	HAL_MODE_11NG_HT20	= 0x008000,
+	HAL_MODE_11NA_HT20  	= 0x010000,
+	HAL_MODE_11NG_HT40PLUS	= 0x020000,
+	HAL_MODE_11NG_HT40MINUS	= 0x040000,
+	HAL_MODE_11NA_HT40PLUS	= 0x080000,
+	HAL_MODE_11NA_HT40MINUS	= 0x100000,
+	HAL_MODE_ALL	= 0xffffff
+};
+
+typedef struct {
+	int		rateCount;		/* NB: for proper padding */
+	uint8_t		rateCodeToIndex[144];	/* back mapping */
+	struct {
+		uint8_t	valid;		/* valid for rate control use */
+		uint8_t	phy;		/* CCK/OFDM/XR */
+		uint32_t	rateKbps;	/* transfer rate in kbs */
+		uint8_t		rateCode;	/* rate for h/w descriptors */
+		uint8_t		shortPreamble;	/* mask for enabling short
+						 * preamble in CCK rate code */
+		uint8_t		dot11Rate;	/* value for supported rates
+						 * info element of MLME */
+		uint8_t		controlRate;	/* index of next lower basic
+						 * rate; used for dur. calcs */
+		uint16_t	lpAckDuration;	/* long preamble ACK duration */
+		uint16_t	spAckDuration;	/* short preamble ACK duration*/
+	} info[32];
+} HAL_RATE_TABLE;
+
+typedef struct {
+	u_int		rs_count;		/* number of valid entries */
+	uint8_t	rs_rates[32];		/* rates */
+} HAL_RATE_SET;
+
+/*
+ * 802.11n specific structures and enums
+ */
+typedef enum {
+	HAL_CHAINTYPE_TX	= 1,	/* Tx chain type */
+	HAL_CHAINTYPE_RX	= 2,	/* RX chain type */
+} HAL_CHAIN_TYPE;
+
+typedef struct {
+	u_int	Tries;
+	u_int	Rate;
+	u_int	PktDuration;
+	u_int	ChSel;
+	u_int	RateFlags;
+#define	HAL_RATESERIES_RTS_CTS		0x0001	/* use rts/cts w/this series */
+#define	HAL_RATESERIES_2040		0x0002	/* use ext channel for series */
+#define	HAL_RATESERIES_HALFGI		0x0004	/* use half-gi for series */
+} HAL_11N_RATE_SERIES;
+
+typedef enum {
+	HAL_HT_MACMODE_20	= 0,	/* 20 MHz operation */
+	HAL_HT_MACMODE_2040	= 1,	/* 20/40 MHz operation */
+} HAL_HT_MACMODE;
+
+typedef enum {
+	HAL_HT_PHYMODE_20	= 0,	/* 20 MHz operation */
+	HAL_HT_PHYMODE_2040	= 1,	/* 20/40 MHz operation */
+} HAL_HT_PHYMODE;
+
+typedef enum {
+	HAL_HT_EXTPROTSPACING_20 = 0,	/* 20 MHz spacing */
+	HAL_HT_EXTPROTSPACING_25 = 1,	/* 25 MHz spacing */
+} HAL_HT_EXTPROTSPACING;
+
+
+typedef enum {
+	HAL_RX_CLEAR_CTL_LOW	= 0x1,	/* force control channel to appear busy */
+	HAL_RX_CLEAR_EXT_LOW	= 0x2,	/* force extension channel to appear busy */
+} HAL_HT_RXCLEAR;
+
+/*
+ * Antenna switch control.  By default antenna selection
+ * enables multiple (2) antenna use.  To force use of the
+ * A or B antenna only specify a fixed setting.  Fixing
+ * the antenna will also disable any diversity support.
+ */
+typedef enum {
+	HAL_ANT_VARIABLE = 0,			/* variable by programming */
+	HAL_ANT_FIXED_A	 = 1,			/* fixed antenna A */
+	HAL_ANT_FIXED_B	 = 2,			/* fixed antenna B */
+} HAL_ANT_SETTING;
+
+typedef enum {
+	HAL_M_STA	= 1,			/* infrastructure station */
+	HAL_M_IBSS	= 0,			/* IBSS (adhoc) station */
+	HAL_M_HOSTAP	= 6,			/* Software Access Point */
+	HAL_M_MONITOR	= 8			/* Monitor mode */
+} HAL_OPMODE;
+
+typedef struct {
+	uint8_t		kv_type;		/* one of HAL_CIPHER */
+	uint8_t		kv_pad;
+	uint16_t	kv_len;			/* length in bits */
+	uint8_t		kv_val[16];		/* enough for 128-bit keys */
+	uint8_t		kv_mic[8];		/* TKIP MIC key */
+	uint8_t		kv_txmic[8];		/* TKIP TX MIC key (optional) */
+} HAL_KEYVAL;
+
+typedef enum {
+	HAL_CIPHER_WEP		= 0,
+	HAL_CIPHER_AES_OCB	= 1,
+	HAL_CIPHER_AES_CCM	= 2,
+	HAL_CIPHER_CKIP		= 3,
+	HAL_CIPHER_TKIP		= 4,
+	HAL_CIPHER_CLR		= 5,		/* no encryption */
+
+	HAL_CIPHER_MIC		= 127		/* TKIP-MIC, not a cipher */
+} HAL_CIPHER;
+
+enum {
+	HAL_SLOT_TIME_6	 = 6,			/* NB: for turbo mode */
+	HAL_SLOT_TIME_9	 = 9,
+	HAL_SLOT_TIME_20 = 20,
+};
+
+/*
+ * Per-station beacon timer state.  Note that the specified
+ * beacon interval (given in TU's) can also include flags
+ * to force a TSF reset and to enable the beacon xmit logic.
+ * If bs_cfpmaxduration is non-zero the hardware is setup to
+ * coexist with a PCF-capable AP.
+ */
+typedef struct {
+	uint32_t	bs_nexttbtt;		/* next beacon in TU */
+	uint32_t	bs_nextdtim;		/* next DTIM in TU */
+	uint32_t	bs_intval;		/* beacon interval+flags */
+#define	HAL_BEACON_PERIOD	0x0000ffff	/* beacon interval period */
+#define	HAL_BEACON_ENA		0x00800000	/* beacon xmit enable */
+#define	HAL_BEACON_RESET_TSF	0x01000000	/* clear TSF */
+	uint32_t	bs_dtimperiod;
+	uint16_t	bs_cfpperiod;		/* CFP period in TU */
+	uint16_t	bs_cfpmaxduration;	/* max CFP duration in TU */
+	uint32_t	bs_cfpnext;		/* next CFP in TU */
+	uint16_t	bs_timoffset;		/* byte offset to TIM bitmap */
+	uint16_t	bs_bmissthreshold;	/* beacon miss threshold */
+	uint32_t	bs_sleepduration;	/* max sleep duration */
+} HAL_BEACON_STATE;
+
+/*
+ * Like HAL_BEACON_STATE but for non-station mode setup.
+ * NB: see above flag definitions for bt_intval. 
+ */
+typedef struct {
+	uint32_t	bt_intval;		/* beacon interval+flags */
+	uint32_t	bt_nexttbtt;		/* next beacon in TU */
+	uint32_t	bt_nextatim;		/* next ATIM in TU */
+	uint32_t	bt_nextdba;		/* next DBA in 1/8th TU */
+	uint32_t	bt_nextswba;		/* next SWBA in 1/8th TU */
+	uint32_t	bt_flags;		/* timer enables */
+#define HAL_BEACON_TBTT_EN	0x00000001
+#define HAL_BEACON_DBA_EN	0x00000002
+#define HAL_BEACON_SWBA_EN	0x00000004
+} HAL_BEACON_TIMERS;
+
+/*
+ * Per-node statistics maintained by the driver for use in
+ * optimizing signal quality and other operational aspects.
+ */
+typedef struct {
+	uint32_t	ns_avgbrssi;	/* average beacon rssi */
+	uint32_t	ns_avgrssi;	/* average data rssi */
+	uint32_t	ns_avgtxrssi;	/* average tx rssi */
+} HAL_NODE_STATS;
+
+#define	HAL_RSSI_EP_MULTIPLIER	(1<<7)	/* pow2 to optimize out * and / */
+
+struct ath_desc;
+struct ath_tx_status;
+struct ath_rx_status;
+
+/*
+ * Hardware Access Layer (HAL) API.
+ *
+ * Clients of the HAL call ath_hal_attach to obtain a reference to an
+ * ath_hal structure for use with the device.  Hardware-related operations
+ * that follow must call back into the HAL through interface, supplying
+ * the reference as the first parameter.  Note that before using the
+ * reference returned by ath_hal_attach the caller should verify the
+ * ABI version number.
+ */
+struct ath_hal {
+	uint32_t	ah_magic;	/* consistency check magic number */
+	uint32_t	ah_abi;		/* HAL ABI version */
+#define	HAL_ABI_VERSION	0x08112800	/* YYMMDDnn */
+	uint16_t	ah_devid;	/* PCI device ID */
+	uint16_t	ah_subvendorid;	/* PCI subvendor ID */
+	HAL_SOFTC	ah_sc;		/* back pointer to driver/os state */
+	HAL_BUS_TAG	ah_st;		/* params for register r+w */
+	HAL_BUS_HANDLE	ah_sh;
+	HAL_CTRY_CODE	ah_countryCode;
+
+	uint32_t	ah_macVersion;	/* MAC version id */
+	uint16_t	ah_macRev;	/* MAC revision */
+	uint16_t	ah_phyRev;	/* PHY revision */
+	/* NB: when only one radio is present the rev is in 5Ghz */
+	uint16_t	ah_analog5GhzRev;/* 5GHz radio revision */
+	uint16_t	ah_analog2GhzRev;/* 2GHz radio revision */
+
+	const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
+				u_int mode);
+	void	  __ahdecl(*ah_detach)(struct ath_hal*);
+
+	/* Reset functions */
+	HAL_BOOL  __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
+				HAL_CHANNEL *, HAL_BOOL bChannelChange,
+				HAL_STATUS *status);
+	HAL_BOOL  __ahdecl(*ah_phyDisable)(struct ath_hal *);
+	HAL_BOOL  __ahdecl(*ah_disable)(struct ath_hal *);
+	void	  __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
+	HAL_BOOL  __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *,
+			HAL_BOOL *);
+	HAL_BOOL  __ahdecl(*ah_perCalibrationN)(struct ath_hal *, HAL_CHANNEL *,
+			u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
+	HAL_BOOL  __ahdecl(*ah_resetCalValid)(struct ath_hal *, HAL_CHANNEL *);
+	HAL_BOOL  __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
+
+	/* Transmit functions */
+	HAL_BOOL  __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
+				HAL_BOOL incTrigLevel);
+	int	  __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
+				const HAL_TXQ_INFO *qInfo);
+	HAL_BOOL  __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 
+				const HAL_TXQ_INFO *qInfo);
+	HAL_BOOL  __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 
+				HAL_TXQ_INFO *qInfo);
+	HAL_BOOL  __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
+	HAL_BOOL  __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
+	uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
+	HAL_BOOL  __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
+	uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
+	HAL_BOOL  __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
+	HAL_BOOL  __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
+	HAL_BOOL  __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
+				u_int pktLen, u_int hdrLen,
+				HAL_PKT_TYPE type, u_int txPower,
+				u_int txRate0, u_int txTries0,
+				u_int keyIx, u_int antMode, u_int flags,
+				u_int rtsctsRate, u_int rtsctsDuration,
+				u_int compicvLen, u_int compivLen,
+				u_int comp);
+	HAL_BOOL  __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
+				u_int txRate1, u_int txTries1,
+				u_int txRate2, u_int txTries2,
+				u_int txRate3, u_int txTries3);
+	HAL_BOOL  __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
+				u_int segLen, HAL_BOOL firstSeg,
+				HAL_BOOL lastSeg, const struct ath_desc *);
+	HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
+				struct ath_desc *, struct ath_tx_status *);
+	void	   __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
+	void	   __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
+
+	/* Receive Functions */
+	uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
+	void	  __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
+	void	  __ahdecl(*ah_enableReceive)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
+	void	  __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
+	void	  __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
+	void	  __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
+				uint32_t filter0, uint32_t filter1);
+	HAL_BOOL  __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
+				uint32_t index);
+	HAL_BOOL  __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
+				uint32_t index);
+	uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
+	void	  __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
+	HAL_BOOL  __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
+				uint32_t size, u_int flags);
+	HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
+				struct ath_desc *, uint32_t phyAddr,
+				struct ath_desc *next, uint64_t tsf,
+				struct ath_rx_status *);
+	void	  __ahdecl(*ah_rxMonitor)(struct ath_hal *,
+				const HAL_NODE_STATS *, HAL_CHANNEL *);
+	void	  __ahdecl(*ah_procMibEvent)(struct ath_hal *,
+				const HAL_NODE_STATS *);
+
+	/* Misc Functions */
+	HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
+				HAL_CAPABILITY_TYPE, uint32_t capability,
+				uint32_t *result);
+	HAL_BOOL   __ahdecl(*ah_setCapability)(struct ath_hal *,
+				HAL_CAPABILITY_TYPE, uint32_t capability,
+				uint32_t setting, HAL_STATUS *);
+	HAL_BOOL   __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
+				const void *args, uint32_t argsize,
+				void **result, uint32_t *resultsize);
+	void	  __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
+	HAL_BOOL  __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
+	void	  __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
+	HAL_BOOL  __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
+	HAL_BOOL  __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
+				uint16_t, HAL_STATUS *);
+	void	  __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
+	void	  __ahdecl(*ah_writeAssocid)(struct ath_hal*,
+				const uint8_t *bssid, uint16_t assocId);
+	HAL_BOOL  __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
+	HAL_BOOL  __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
+	uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
+	HAL_BOOL  __ahdecl(*ah_gpioSet)(struct ath_hal *,
+				uint32_t gpio, uint32_t val);
+	void	  __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
+	uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
+	uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
+	void	  __ahdecl(*ah_resetTsf)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
+	void	  __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
+				HAL_MIB_STATS*);
+	HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
+	u_int	  __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
+	void	  __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
+	HAL_ANT_SETTING	 __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
+				HAL_ANT_SETTING);
+	HAL_BOOL  __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
+	u_int	  __ahdecl(*ah_getSifsTime)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
+	u_int	  __ahdecl(*ah_getSlotTime)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
+	u_int	  __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
+	u_int	  __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
+	u_int	  __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
+	void	  __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
+
+	/* Key Cache Functions */
+	uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
+	HAL_BOOL  __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
+				uint16_t);
+	HAL_BOOL  __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
+				uint16_t, const HAL_KEYVAL *,
+				const uint8_t *, int);
+	HAL_BOOL  __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
+				uint16_t, const uint8_t *);
+
+	/* Power Management Functions */
+	HAL_BOOL  __ahdecl(*ah_setPowerMode)(struct ath_hal*,
+				HAL_POWER_MODE mode, int setChip);
+	HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
+	int16_t   __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
+
+	/* Beacon Management Functions */
+	void	  __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
+				const HAL_BEACON_TIMERS *);
+	/* NB: deprecated, use ah_setBeaconTimers instead */
+	void	  __ahdecl(*ah_beaconInit)(struct ath_hal *,
+				uint32_t nexttbtt, uint32_t intval);
+	void	  __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
+				const HAL_BEACON_STATE *);
+	void	  __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
+
+	/* Interrupt functions */
+	HAL_BOOL  __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
+	HAL_BOOL  __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
+	HAL_INT	  __ahdecl(*ah_getInterrupts)(struct ath_hal*);
+	HAL_INT	  __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
+};
+
+/* 
+ * Check the PCI vendor ID and device ID against Atheros' values
+ * and return a printable description for any Atheros hardware.
+ * AH_NULL is returned if the ID's do not describe Atheros hardware.
+ */
+extern	const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
+
+/*
+ * Attach the HAL for use with the specified device.  The device is
+ * defined by the PCI device ID.  The caller provides an opaque pointer
+ * to an upper-layer data structure (HAL_SOFTC) that is stored in the
+ * HAL state block for later use.  Hardware register accesses are done
+ * using the specified bus tag and handle.  On successful return a
+ * reference to a state block is returned that must be supplied in all
+ * subsequent HAL calls.  Storage associated with this reference is
+ * dynamically allocated and must be freed by calling the ah_detach
+ * method when the client is done.  If the attach operation fails a
+ * null (AH_NULL) reference will be returned and a status code will
+ * be returned if the status parameter is non-zero.
+ */
+extern	struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
+		HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);
+
+/*
+ * Return a list of channels available for use with the hardware.
+ * The list is based on what the hardware is capable of, the specified
+ * country code, the modeSelect mask, and whether or not outdoor
+ * channels are to be permitted.
+ *
+ * The channel list is returned in the supplied array.  maxchans
+ * defines the maximum size of this array.  nchans contains the actual
+ * number of channels returned.  If a problem occurred or there were
+ * no channels that met the criteria then AH_FALSE is returned.
+ */
+extern	HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *,
+		HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
+		uint8_t *regclassids, u_int maxregids, u_int *nregids,
+		HAL_CTRY_CODE cc, u_int modeSelect,
+		HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
+
+/*
+ * Calibrate noise floor data following a channel scan or similar.
+ * This must be called prior retrieving noise floor data.
+ */
+extern	void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
+
+/*
+ * Return bit mask of wireless modes supported by the hardware.
+ */
+extern	u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
+
+/*
+ * Calculate the transmit duration of a frame.
+ */
+extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
+		const HAL_RATE_TABLE *rates, uint32_t frameLen,
+		uint16_t rateix, HAL_BOOL shortPreamble);
+
+/*
+ * Return if device is public safety.
+ */
+extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *);
+
+/*
+ * Return if device is operating in 900 MHz band.
+ */
+extern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *);
+
+/*
+ * Convert between IEEE channel number and channel frequency
+ * using the specified channel flags; e.g. CHANNEL_2GHZ.
+ */
+extern	int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags);
+#endif /* _ATH_AH_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_debug.h b/sys/dev/netif/ath/hal/ath_hal/ah_debug.h
new file mode 100644
index 0000000..e3b15ad
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_debug.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_debug.h,v 1.1 2008/10/12 16:44:34 sam Exp $
+ */
+#ifndef _ATH_AH_DEBUG_H_
+#define _ATH_AH_DEBUG_H_
+/*
+ * Atheros Device Hardware Access Layer (HAL).
+ *
+ * Debug mask definitions.
+ */
+enum {
+	HAL_DEBUG_REGDOMAIN	= 0x00000001,	/* regulatory handling */
+	HAL_DEBUG_ATTACH	= 0x00000002,	/* work done in attach */
+	HAL_DEBUG_RESET		= 0x00000004,	/* reset work */
+	HAL_DEBUG_NFCAL		= 0x00000008,	/* noise floor calibration */
+	HAL_DEBUG_PERCAL	= 0x00000010,	/* periodic calibration */
+	HAL_DEBUG_ANI		= 0x00000020,	/* ANI operation */
+	HAL_DEBUG_PHYIO		= 0x00000040,	/* phy i/o operations */
+	HAL_DEBUG_REGIO		= 0x00000080,	/* register i/o operations */
+	HAL_DEBUG_RFPARAM	= 0x00000100,
+	HAL_DEBUG_TXQUEUE	= 0x00000200,	/* tx queue handling */
+	HAL_DEBUG_TX		= 0x00000400,
+	HAL_DEBUG_TXDESC	= 0x00000800,
+	HAL_DEBUG_RX		= 0x00001000,
+	HAL_DEBUG_RXDESC	= 0x00002000,
+	HAL_DEBUG_KEYCACHE	= 0x00004000,	/* keycache handling */
+	HAL_DEBUG_EEPROM	= 0x00008000,
+	HAL_DEBUG_BEACON	= 0x00010000,	/* beacon setup work */
+	HAL_DEBUG_POWER		= 0x00020000,	/* power management */
+	HAL_DEBUG_INTERRUPT	= 0x00000080,	/* interrupt handling */
+
+	HAL_DEBUG_ANY		= 0xffffffff
+};
+#endif /* _ATH_AH_DEBUG_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_decode.h b/sys/dev/netif/ath/hal/ath_hal/ah_decode.h
new file mode 100644
index 0000000..bd595ae
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_decode.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_decode.h,v 1.4 2008/11/10 04:08:00 sam Exp $
+ */
+#ifndef _ATH_AH_DECODE_H_
+#define _ATH_AH_DECODE_H_
+/*
+ * Register tracing support.
+ *
+ * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
+ * writes to the file /tmp/ath_hal.log.  The file format is a simple
+ * fixed-size array of records.  When done logging set hw.ath.hal.alq=0
+ * and then decode the file with the arcode program (that is part of the
+ * HAL).  If you start+stop tracing the data will be appended to an
+ * existing file.
+ */
+struct athregrec {
+	uint32_t	op	: 8,
+			reg	: 24;
+	uint32_t	val;
+};
+
+enum {
+	OP_READ		= 0,		/* register read */
+	OP_WRITE	= 1,		/* register write */
+	OP_DEVICE	= 2,		/* device identification */
+	OP_MARK		= 3,		/* application marker */
+};
+
+enum {
+	AH_MARK_RESET,			/* ar*Reset entry, bChannelChange */
+	AH_MARK_RESET_LINE,		/* ar*_reset.c, line %d */
+	AH_MARK_RESET_DONE,		/* ar*Reset exit, error code */
+	AH_MARK_CHIPRESET,		/* ar*ChipReset, channel num */
+	AH_MARK_PERCAL,			/* ar*PerCalibration, channel num */
+	AH_MARK_SETCHANNEL,		/* ar*SetChannel, channel num */
+	AH_MARK_ANI_RESET,		/* ar*AniReset, opmode */
+	AH_MARK_ANI_POLL,		/* ar*AniReset, listen time */
+	AH_MARK_ANI_CONTROL,		/* ar*AniReset, cmd */
+};
+#endif /* _ATH_AH_DECODE_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_desc.h b/sys/dev/netif/ath/hal/ath_hal/ah_desc.h
new file mode 100644
index 0000000..6cfad06
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_desc.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_desc.h,v 1.5 2008/11/10 04:08:00 sam Exp $
+ */
+
+#ifndef _DEV_ATH_DESC_H
+#define _DEV_ATH_DESC_H
+
+#include "opt_ah.h"		/* NB: required for AH_SUPPORT_AR5416 */
+
+/*
+ * Transmit descriptor status.  This structure is filled
+ * in only after the tx descriptor process method finds a
+ * ``done'' descriptor; at which point it returns something
+ * other than HAL_EINPROGRESS.
+ *
+ * Note that ts_antenna may not be valid for all h/w.  It
+ * should be used only if non-zero.
+ */
+struct ath_tx_status {
+	uint16_t	ts_seqnum;	/* h/w assigned sequence number */
+	uint16_t	ts_tstamp;	/* h/w assigned timestamp */
+	uint8_t		ts_status;	/* frame status, 0 => xmit ok */
+	uint8_t		ts_rate;	/* h/w transmit rate index */
+#define	HAL_TXSTAT_ALTRATE	0x80	/* alternate xmit rate used */
+	int8_t		ts_rssi;	/* tx ack RSSI */
+	uint8_t		ts_shortretry;	/* # short retries */
+	uint8_t		ts_longretry;	/* # long retries */
+	uint8_t		ts_virtcol;	/* virtual collision count */
+	uint8_t		ts_antenna;	/* antenna information */
+	uint8_t		ts_finaltsi;	/* final transmit series index */
+#ifdef AH_SUPPORT_AR5416
+					/* 802.11n status */
+	uint8_t    	ts_flags;   	/* misc flags */
+	int8_t      	ts_rssi_ctl[3];	/* tx ack RSSI [ctl, chain 0-2] */
+	int8_t      	ts_rssi_ext[3];	/* tx ack RSSI [ext, chain 0-2] */
+/* #define ts_rssi ts_rssi_combined */
+	uint32_t   	ts_ba_low;	/* blockack bitmap low */
+	uint32_t   	ts_ba_high;	/* blockack bitmap high */
+	uint32_t  	ts_evm0;	/* evm bytes */
+	uint32_t   	ts_evm1;
+	uint32_t   	ts_evm2;
+#endif /* AH_SUPPORT_AR5416 */
+};
+
+/* bits found in ts_status */
+#define	HAL_TXERR_XRETRY	0x01	/* excessive retries */
+#define	HAL_TXERR_FILT		0x02	/* blocked by tx filtering */
+#define	HAL_TXERR_FIFO		0x04	/* fifo underrun */
+#define	HAL_TXERR_XTXOP		0x08	/* txop exceeded */
+#define	HAL_TXERR_TIMER_EXPIRED	0x10	/* Tx timer expired */
+
+/* bits found in ts_flags */
+#define	HAL_TX_BA		0x01	/* Block Ack seen */
+#define	HAL_TX_AGGR		0x02	/* Aggregate */ 
+#define	HAL_TX_DESC_CFG_ERR	0x10	/* Error in 20/40 desc config */
+#define	HAL_TX_DATA_UNDERRUN	0x20	/* Tx buffer underrun */
+#define	HAL_TX_DELIM_UNDERRUN	0x40	/* Tx delimiter underrun */
+
+/*
+ * Receive descriptor status.  This structure is filled
+ * in only after the rx descriptor process method finds a
+ * ``done'' descriptor; at which point it returns something
+ * other than HAL_EINPROGRESS.
+ *
+ * If rx_status is zero, then the frame was received ok;
+ * otherwise the error information is indicated and rs_phyerr
+ * contains a phy error code if HAL_RXERR_PHY is set.  In general
+ * the frame contents is undefined when an error occurred thought
+ * for some errors (e.g. a decryption error), it may be meaningful.
+ *
+ * Note that the receive timestamp is expanded using the TSF to
+ * at least 15 bits (regardless of what the h/w provides directly).
+ * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
+ * find out if the hardware is capable.
+ *
+ * rx_rssi is in units of dbm above the noise floor.  This value
+ * is measured during the preamble and PLCP; i.e. with the initial
+ * 4us of detection.  The noise floor is typically a consistent
+ * -96dBm absolute power in a 20MHz channel.
+ */
+struct ath_rx_status {
+	uint16_t	rs_datalen;	/* rx frame length */
+	uint8_t		rs_status;	/* rx status, 0 => recv ok */
+	uint8_t		rs_phyerr;	/* phy error code */
+	int8_t		rs_rssi;	/* rx frame RSSI (combined for 11n) */
+	uint8_t		rs_keyix;	/* key cache index */
+	uint8_t		rs_rate;	/* h/w receive rate index */
+	uint8_t		rs_more;	/* more descriptors follow */
+	uint32_t	rs_tstamp;	/* h/w assigned timestamp */
+	uint32_t	rs_antenna;	/* antenna information */
+#ifdef AH_SUPPORT_AR5416
+					/* 802.11n status */
+	int8_t		rs_rssi_ctl[3];	/* rx frame RSSI [ctl, chain 0-2] */
+	int8_t		rs_rssi_ext[3];	/* rx frame RSSI [ext, chain 0-2] */
+	uint8_t		rs_isaggr;	/* is part of the aggregate */
+	uint8_t		rs_moreaggr;	/* more frames in aggr to follow */
+	uint8_t		rs_num_delims;	/* number of delims in aggr */
+	uint8_t		rs_flags;	/* misc flags */
+	uint32_t	rs_evm0;	/* evm bytes */
+	uint32_t	rs_evm1;
+	uint32_t	rs_evm2;	
+#endif /* AH_SUPPORT_AR5416 */
+};
+
+/* bits found in rs_status */
+#define	HAL_RXERR_CRC		0x01	/* CRC error on frame */
+#define	HAL_RXERR_PHY		0x02	/* PHY error, rs_phyerr is valid */
+#define	HAL_RXERR_FIFO		0x04	/* fifo overrun */
+#define	HAL_RXERR_DECRYPT	0x08	/* non-Michael decrypt error */
+#define	HAL_RXERR_MIC		0x10	/* Michael MIC decrypt error */
+
+/* bits found in rs_flags */
+#define	HAL_RX_MORE		0x01	/* more descriptors follow */
+#define	HAL_RX_MORE_AGGR	0x02	/* more frames in aggr */
+#define	HAL_RX_GI		0x04	/* full gi */
+#define	HAL_RX_2040		0x08	/* 40 Mhz */
+#define	HAL_RX_DELIM_CRC_PRE	0x10	/* crc error in delimiter pre */
+#define	HAL_RX_DELIM_CRC_POST	0x20	/* crc error in delim after */
+#define	HAL_RX_DECRYPT_BUSY	0x40	/* decrypt was too slow */
+#define	HAL_RX_HI_RX_CHAIN	0x80	/* SM power save: hi Rx chain control */
+
+enum {
+	HAL_PHYERR_UNDERRUN		= 0,	/* Transmit underrun */
+	HAL_PHYERR_TIMING		= 1,	/* Timing error */
+	HAL_PHYERR_PARITY		= 2,	/* Illegal parity */
+	HAL_PHYERR_RATE			= 3,	/* Illegal rate */
+	HAL_PHYERR_LENGTH		= 4,	/* Illegal length */
+	HAL_PHYERR_RADAR		= 5,	/* Radar detect */
+	HAL_PHYERR_SERVICE		= 6,	/* Illegal service */
+	HAL_PHYERR_TOR			= 7,	/* Transmit override receive */
+	/* NB: these are specific to the 5212 */
+	HAL_PHYERR_OFDM_TIMING		= 17,	/* */
+	HAL_PHYERR_OFDM_SIGNAL_PARITY	= 18,	/* */
+	HAL_PHYERR_OFDM_RATE_ILLEGAL	= 19,	/* */
+	HAL_PHYERR_OFDM_LENGTH_ILLEGAL	= 20,	/* */
+	HAL_PHYERR_OFDM_POWER_DROP	= 21,	/* */
+	HAL_PHYERR_OFDM_SERVICE		= 22,	/* */
+	HAL_PHYERR_OFDM_RESTART		= 23,	/* */
+	HAL_PHYERR_CCK_TIMING		= 25,	/* */
+	HAL_PHYERR_CCK_HEADER_CRC	= 26,	/* */
+	HAL_PHYERR_CCK_RATE_ILLEGAL	= 27,	/* */
+	HAL_PHYERR_CCK_SERVICE		= 30,	/* */
+	HAL_PHYERR_CCK_RESTART		= 31,	/* */
+};
+
+/* value found in rs_keyix to mark invalid entries */
+#define	HAL_RXKEYIX_INVALID	((uint8_t) -1)
+/* value used to specify no encryption key for xmit */
+#define	HAL_TXKEYIX_INVALID	((u_int) -1)
+
+/* XXX rs_antenna definitions */
+
+/*
+ * Definitions for the software frame/packet descriptors used by
+ * the Atheros HAL.  This definition obscures hardware-specific
+ * details from the driver.  Drivers are expected to fillin the
+ * portions of a descriptor that are not opaque then use HAL calls
+ * to complete the work.  Status for completed frames is returned
+ * in a device-independent format.
+ */
+#ifdef AH_SUPPORT_AR5416
+#define	HAL_DESC_HW_SIZE	20
+#else
+#define	HAL_DESC_HW_SIZE	4
+#endif /* AH_SUPPORT_AR5416 */
+
+struct ath_desc {
+	/*
+	 * The following definitions are passed directly
+	 * the hardware and managed by the HAL.  Drivers
+	 * should not touch those elements marked opaque.
+	 */
+	uint32_t	ds_link;	/* phys address of next descriptor */
+	uint32_t	ds_data;	/* phys address of data buffer */
+	uint32_t	ds_ctl0;	/* opaque DMA control 0 */
+	uint32_t	ds_ctl1;	/* opaque DMA control 1 */
+	uint32_t	ds_hw[HAL_DESC_HW_SIZE];	/* opaque h/w region */
+};
+
+struct ath_desc_status {
+	union {
+		struct ath_tx_status tx;/* xmit status */
+		struct ath_rx_status rx;/* recv status */
+	} ds_us;
+};
+
+#define	ds_txstat	ds_us.tx
+#define	ds_rxstat	ds_us.rx
+
+/* flags passed to tx descriptor setup methods */
+#define	HAL_TXDESC_CLRDMASK	0x0001	/* clear destination filter mask */
+#define	HAL_TXDESC_NOACK	0x0002	/* don't wait for ACK */
+#define	HAL_TXDESC_RTSENA	0x0004	/* enable RTS */
+#define	HAL_TXDESC_CTSENA	0x0008	/* enable CTS */
+#define	HAL_TXDESC_INTREQ	0x0010	/* enable per-descriptor interrupt */
+#define	HAL_TXDESC_VEOL		0x0020	/* mark virtual EOL */
+/* NB: this only affects frame, not any RTS/CTS */
+#define	HAL_TXDESC_DURENA	0x0040	/* enable h/w write of duration field */
+#define	HAL_TXDESC_EXT_ONLY	0x0080	/* send on ext channel only (11n) */
+#define	HAL_TXDESC_EXT_AND_CTL	0x0100	/* send on ext + ctl channels (11n) */
+#define	HAL_TXDESC_VMF		0x0200	/* virtual more frag */
+
+/* flags passed to rx descriptor setup methods */
+#define	HAL_RXDESC_INTREQ	0x0020	/* enable per-descriptor interrupt */
+#endif /* _DEV_ATH_DESC_H */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_devid.h b/sys/dev/netif/ath/hal/ath_hal/ah_devid.h
new file mode 100644
index 0000000..0844c77
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_devid.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_devid.h,v 1.4 2008/10/06 18:32:46 sam Exp $
+ */
+
+#ifndef _DEV_ATH_DEVID_H_
+#define _DEV_ATH_DEVID_H_
+
+#define ATHEROS_VENDOR_ID	0x168c		/* Atheros PCI vendor ID */
+/*
+ * NB: all Atheros-based devices should have a PCI vendor ID
+ *     of 0x168c, but some vendors, in their infinite wisdom
+ *     do not follow this so we must handle them specially.
+ */
+#define	ATHEROS_3COM_VENDOR_ID	0xa727		/* 3Com 3CRPAG175 vendor ID */
+#define	ATHEROS_3COM2_VENDOR_ID	0x10b7		/* 3Com 3CRDAG675 vendor ID */
+
+/* AR5210 (for reference) */
+#define AR5210_DEFAULT          0x1107          /* No eeprom HW default */
+#define AR5210_PROD             0x0007          /* Final device ID */
+#define AR5210_AP               0x0207          /* Early AP11s */
+
+/* AR5211 */
+#define AR5211_DEFAULT          0x1112          /* No eeprom HW default */
+#define AR5311_DEVID            0x0011          /* Final ar5311 devid */
+#define AR5211_DEVID            0x0012          /* Final ar5211 devid */
+#define AR5211_LEGACY           0xff12          /* Original emulation board */
+#define AR5211_FPGA11B          0xf11b          /* 11b emulation board */
+
+/* AR5212 */
+#define AR5212_DEFAULT          0x1113          /* No eeprom HW default */
+#define AR5212_DEVID            0x0013          /* Final ar5212 devid */
+#define AR5212_FPGA             0xf013          /* Emulation board */
+#define	AR5212_DEVID_IBM	0x1014          /* IBM minipci ID */
+#define AR5212_AR5312_REV2      0x0052          /* AR5312 WMAC (AP31) */
+#define AR5212_AR5312_REV7      0x0057          /* AR5312 WMAC (AP30-040) */
+#define AR5212_AR2313_REV8      0x0058          /* AR2313 WMAC (AP43-030) */
+#define AR5212_AR2315_REV6      0x0086          /* AR2315 WMAC (AP51-Light) */
+#define AR5212_AR2315_REV7      0x0087          /* AR2315 WMAC (AP51-Full) */
+#define AR5212_AR2317_REV1      0x0090          /* AR2317 WMAC (AP61-Light) */
+#define AR5212_AR2317_REV2      0x0091          /* AR2317 WMAC (AP61-Full) */
+
+/* AR5212 compatible devid's also attach to 5212 */
+#define	AR5212_DEVID_0014	0x0014
+#define	AR5212_DEVID_0015	0x0015
+#define	AR5212_DEVID_0016	0x0016
+#define	AR5212_DEVID_0017	0x0017
+#define	AR5212_DEVID_0018	0x0018
+#define	AR5212_DEVID_0019	0x0019
+#define AR5212_AR2413      	0x001a          /* AR2413 aka Griffin-lite */
+#define AR5212_AR5413		0x001b          /* Eagle */
+#define AR5212_AR5424		0x001c          /* Condor (PCI express) */
+#define AR5212_AR2417		0x001d          /* Nala, PCI */
+#define AR5212_DEVID_FF19	0xff19          /* XXX PCI express */
+
+/* AR5213 */
+#define	AR5213_SREV_1_0		0x0055
+#define	AR5213_SREV_REG		0x4020
+
+/* AR5416 compatible devid's  */
+#define AR5416_DEVID_PCI	0x0023          /* AR5416 PCI (MB/CB) Owl */
+#define AR5416_DEVID_PCIE	0x0024          /* AR5416 PCI-E (XB) Owl */
+#define AR9160_DEVID_PCI	0x0027          /* AR9160 PCI Sowl */
+#define AR9280_DEVID_PCI	0x0029          /* AR9280 PCI Merlin */
+#define AR9280_DEVID_PCIE	0x002a          /* AR9280 PCI-E Merlin */
+#define AR9285_DEVID_PCIE	0x002b          /* AR9285 PCI-E Kite */
+
+#define	AR_SUBVENDOR_ID_NOG	0x0e11		/* No 11G subvendor ID */
+#define AR_SUBVENDOR_ID_NEW_A	0x7065		/* Update device to new RD */
+#endif /* _DEV_ATH_DEVID_H */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_eeprom.h b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom.h
new file mode 100644
index 0000000..0adfcd1
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_eeprom.h,v 1.11 2008/11/27 22:32:48 sam Exp $
+ */
+#ifndef _ATH_AH_EEPROM_H_
+#define _ATH_AH_EEPROM_H_
+
+#define	AR_EEPROM_VER1		0x1000	/* Version 1.0; 5210 only */
+/*
+ * Version 3 EEPROMs are all 16K.
+ * 3.1 adds turbo limit, antenna gain, 16 CTL's, 11g info,
+ *	and 2.4Ghz ob/db for B & G
+ * 3.2 has more accurate pcdac intercepts and analog chip
+ *	calibration.
+ * 3.3 adds ctl in-band limit, 32 ctl's, and frequency
+ *	expansion
+ * 3.4 adds xr power, gainI, and 2.4 turbo params
+ */
+#define	AR_EEPROM_VER3		0x3000	/* Version 3.0; start of 16k EEPROM */
+#define	AR_EEPROM_VER3_1	0x3001	/* Version 3.1 */
+#define	AR_EEPROM_VER3_2	0x3002	/* Version 3.2 */
+#define	AR_EEPROM_VER3_3	0x3003	/* Version 3.3 */
+#define	AR_EEPROM_VER3_4	0x3004	/* Version 3.4 */
+#define	AR_EEPROM_VER4		0x4000	/* Version 4.x */
+#define	AR_EEPROM_VER4_0	0x4000	/* Version 4.0 */
+#define	AR_EEPROM_VER4_1	0x4001	/* Version 4.0 */
+#define	AR_EEPROM_VER4_2	0x4002	/* Version 4.0 */
+#define	AR_EEPROM_VER4_3	0x4003	/* Version 4.0 */
+#define	AR_EEPROM_VER4_6	0x4006	/* Version 4.0 */
+#define	AR_EEPROM_VER4_7	0x3007	/* Version 4.7 */
+#define	AR_EEPROM_VER4_9	0x4009	/* EEPROM EAR futureproofing */
+#define	AR_EEPROM_VER5		0x5000	/* Version 5.x */
+#define	AR_EEPROM_VER5_0	0x5000	/* Adds new 2413 cal powers and added params */
+#define	AR_EEPROM_VER5_1	0x5001	/* Adds capability values */
+#define	AR_EEPROM_VER5_3	0x5003	/* Adds spur mitigation table */
+#define	AR_EEPROM_VER5_4	0x5004
+/*
+ * Version 14 EEPROMs came in with AR5416.
+ * 14.2 adds txFrameToPaOn, txFrameToDataStart, ht40PowerInc
+ * 14.3 adds bswAtten, bswMargin, swSettle, and base OpFlags for HT20/40
+ */
+#define	AR_EEPROM_VER14		0xE000	/* Version 14.x */
+#define	AR_EEPROM_VER14_1	0xE001	/* Adds 11n support */
+#define	AR_EEPROM_VER14_2	0xE002
+#define	AR_EEPROM_VER14_3	0xE003
+#define	AR_EEPROM_VER14_7	0xE007
+#define	AR_EEPROM_VER14_9	0xE009
+#define	AR_EEPROM_VER14_16	0xE010
+#define	AR_EEPROM_VER14_17	0xE011
+#define	AR_EEPROM_VER14_19	0xE013
+
+enum {
+	AR_EEP_RFKILL,		/* use ath_hal_eepromGetFlag */
+	AR_EEP_AMODE,		/* use ath_hal_eepromGetFlag */
+	AR_EEP_BMODE,		/* use ath_hal_eepromGetFlag */
+	AR_EEP_GMODE,		/* use ath_hal_eepromGetFlag */
+	AR_EEP_TURBO5DISABLE,	/* use ath_hal_eepromGetFlag */
+	AR_EEP_TURBO2DISABLE,	/* use ath_hal_eepromGetFlag */
+	AR_EEP_ISTALON,		/* use ath_hal_eepromGetFlag */
+	AR_EEP_32KHZCRYSTAL,	/* use ath_hal_eepromGetFlag */
+	AR_EEP_MACADDR,		/* uint8_t* */
+	AR_EEP_COMPRESS,	/* use ath_hal_eepromGetFlag */
+	AR_EEP_FASTFRAME,	/* use ath_hal_eepromGetFlag */
+	AR_EEP_AES,		/* use ath_hal_eepromGetFlag */
+	AR_EEP_BURST,		/* use ath_hal_eepromGetFlag */
+	AR_EEP_MAXQCU,		/* uint16_t* */
+	AR_EEP_KCENTRIES,	/* uint16_t* */
+	AR_EEP_NFTHRESH_5,	/* int16_t* */
+	AR_EEP_NFTHRESH_2,	/* int16_t* */
+	AR_EEP_REGDMN_0,	/* uint16_t* */
+	AR_EEP_REGDMN_1,	/* uint16_t* */
+	AR_EEP_OPCAP,		/* uint16_t* */
+	AR_EEP_OPMODE,		/* uint16_t* */
+	AR_EEP_RFSILENT,	/* uint16_t* */
+	AR_EEP_OB_5,		/* uint8_t* */
+	AR_EEP_DB_5,		/* uint8_t* */
+	AR_EEP_OB_2,		/* uint8_t* */
+	AR_EEP_DB_2,		/* uint8_t* */
+	AR_EEP_TXMASK,		/* uint8_t* */
+	AR_EEP_RXMASK,		/* uint8_t* */
+	AR_EEP_RXGAIN_TYPE,	/* uint8_t* */
+	AR_EEP_TXGAIN_TYPE,	/* uint8_t* */
+	AR_EEP_OL_PWRCTRL,	/* use ath_hal_eepromGetFlag */
+	AR_EEP_FSTCLK_5G,	/* use ath_hal_eepromGetFlag */
+	AR_EEP_ANTGAINMAX_5,	/* int8_t* */
+	AR_EEP_ANTGAINMAX_2,	/* int8_t* */
+	AR_EEP_WRITEPROTECT,	/* use ath_hal_eepromGetFlag */
+};
+
+typedef struct {
+	uint16_t	rdEdge;
+	uint16_t	twice_rdEdgePower;
+	HAL_BOOL	flag;
+} RD_EDGES_POWER;
+
+/* XXX should probably be version-dependent */
+#define	SD_NO_CTL		0xf0
+#define	NO_CTL			0xff
+#define	CTL_MODE_M		0x0f
+#define	CTL_11A			0
+#define	CTL_11B			1
+#define	CTL_11G			2
+#define	CTL_TURBO		3
+#define	CTL_108G		4
+#define	CTL_2GHT20		5
+#define	CTL_5GHT20		6
+#define	CTL_2GHT40		7
+#define	CTL_5GHT40		8
+
+#define	AR_NO_SPUR		0x8000
+
+/* XXX exposed to chip code */
+#define	MAX_RATE_POWER	63
+
+HAL_STATUS	ath_hal_v1EepromAttach(struct ath_hal *ah);
+HAL_STATUS	ath_hal_legacyEepromAttach(struct ath_hal *ah);
+HAL_STATUS	ath_hal_v14EepromAttach(struct ath_hal *ah);
+HAL_STATUS	ath_hal_v4kEepromAttach(struct ath_hal *ah);
+#endif /* _ATH_AH_EEPROM_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v1.c b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v1.c
new file mode 100644
index 0000000..91f895c
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v1.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_eeprom_v1.c,v 1.1 2008/11/11 02:40:11 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_eeprom_v1.h"
+
+static HAL_STATUS
+v1EepromGet(struct ath_hal *ah, int param, void *val)
+{
+	HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint32_t sum;
+	uint16_t eeval;
+	uint8_t *macaddr;
+	int i;
+
+	switch (param) {
+        case AR_EEP_MACADDR:		/* Get MAC Address */
+		sum = 0;
+		macaddr = val;
+		for (i = 0; i < 3; i++) {
+			if (!ath_hal_eepromRead(ah, AR_EEPROM_MAC(i), &eeval)) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+				    "%s: cannot read EEPROM location %u\n",
+				    __func__, i);
+				return HAL_EEREAD;
+			}
+			sum += eeval;
+			macaddr[2*i + 0] = eeval >> 8;
+			macaddr[2*i + 1] = eeval & 0xff;
+		}
+		if (sum == 0 || sum == 0xffff*3) {
+			HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",
+			    __func__, ath_hal_ether_sprintf(macaddr));
+			return HAL_EEBADMAC;
+		}
+		return HAL_OK;
+        case AR_EEP_REGDMN_0:
+		*(uint16_t *) val = ee->ee_regDomain[0];
+		return HAL_OK;
+        case AR_EEP_RFKILL:
+		HALASSERT(val == AH_NULL);
+		return ee->ee_rfKill ? HAL_OK : HAL_EIO;
+	case AR_EEP_WRITEPROTECT:
+		HALASSERT(val == AH_NULL);
+		return (ee->ee_protect & AR_EEPROM_PROTOTECT_WP_128_191) ?
+		    HAL_OK : HAL_EIO;
+        default:
+		HALASSERT(0);
+		return HAL_EINVAL;
+	}
+}
+
+static HAL_BOOL
+v1EepromSet(struct ath_hal *ah, int param, int v)
+{
+	return HAL_EINVAL;
+}
+
+static HAL_BOOL
+v1EepromDiag(struct ath_hal *ah, int request,
+     const void *args, uint32_t argsize, void **result, uint32_t *resultsize)
+{
+	HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	switch (request) {
+	case HAL_DIAG_EEPROM:
+		*result = ee;
+		*resultsize = sizeof(*ee);
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+static uint16_t 
+v1EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)
+{ 
+	return AR_NO_SPUR;
+}
+
+/*
+ * Reclaim any EEPROM-related storage.
+ */
+static void
+v1EepromDetach(struct ath_hal *ah)
+{
+	HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	ath_hal_free(ee);
+	AH_PRIVATE(ah)->ah_eeprom = AH_NULL;
+}
+
+HAL_STATUS
+ath_hal_v1EepromAttach(struct ath_hal *ah)
+{
+	HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t athvals[AR_EEPROM_ATHEROS_MAX];	/* XXX off stack */
+	uint16_t protect, version, eeval;
+	uint32_t sum;
+	int i, loc;
+
+	HALASSERT(ee == AH_NULL);
+
+	if (!ath_hal_eepromRead(ah, AR_EEPROM_MAGIC, &eeval)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot read EEPROM magic number\n", __func__);
+		return HAL_EEREAD;
+	}
+	if (eeval != 0x5aa5) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid EEPROM magic number 0x%x\n", __func__, eeval);
+		return HAL_EEMAGIC;
+	}
+
+	if (!ath_hal_eepromRead(ah, AR_EEPROM_PROTECT, &protect)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot read EEPROM protection bits; read locked?\n",
+		    __func__);
+		return HAL_EEREAD;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "EEPROM protect 0x%x\n", protect);
+	/* XXX check proper access before continuing */
+
+	if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, &version)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: unable to read EEPROM version\n", __func__);
+		return HAL_EEREAD;
+	}
+	if (((version>>12) & 0xf) != 1) {
+		/*
+		 * This code only groks the version 1 EEPROM layout.
+		 */
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: unsupported EEPROM version 0x%x found\n",
+		    __func__, version);
+		return HAL_EEVERSION;
+	}
+
+	/*
+	 * Read the Atheros EEPROM entries and calculate the checksum.
+	 */
+	sum = 0;
+	for (i = 0; i < AR_EEPROM_ATHEROS_MAX; i++) {
+		if (!ath_hal_eepromRead(ah, AR_EEPROM_ATHEROS(i), &athvals[i]))
+			return HAL_EEREAD;
+		sum ^= athvals[i];
+	}
+	if (sum != 0xffff) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad EEPROM checksum 0x%x\n",
+		    __func__, sum);
+		return HAL_EEBADSUM;
+	}
+
+	/*
+	 * Valid checksum, fetch the regulatory domain and save values.
+	 */
+	if (!ath_hal_eepromRead(ah, AR_EEPROM_REG_DOMAIN, &eeval)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot read regdomain from EEPROM\n", __func__);
+		return HAL_EEREAD;
+	}
+
+	ee = ath_hal_malloc(sizeof(HAL_EEPROM_v1));
+	if (ee == AH_NULL) {
+		/* XXX message */
+		return HAL_ENOMEM;
+	}
+
+	ee->ee_version		= version;
+	ee->ee_protect		= protect;
+	ee->ee_antenna		= athvals[2];
+	ee->ee_biasCurrents	= athvals[3];
+	ee->ee_thresh62	= athvals[4] & 0xff;
+	ee->ee_xlnaOn		= (athvals[4] >> 8) & 0xff;
+	ee->ee_xpaOn		= athvals[5] & 0xff;
+	ee->ee_xpaOff		= (athvals[5] >> 8) & 0xff;
+	ee->ee_regDomain[0]	= (athvals[6] >> 8) & 0xff;
+	ee->ee_regDomain[1]	= athvals[6] & 0xff;
+	ee->ee_regDomain[2]	= (athvals[7] >> 8) & 0xff;
+	ee->ee_regDomain[3]	= athvals[7] & 0xff;
+	ee->ee_rfKill		= athvals[8] & 0x1;
+	ee->ee_devType		= (athvals[8] >> 1) & 0x7;
+
+	for (i = 0, loc = AR_EEPROM_ATHEROS_TP_SETTINGS; i < AR_CHANNELS_MAX; i++, loc += AR_TP_SETTINGS_SIZE) {
+		struct tpcMap *chan = &ee->ee_tpc[i];
+
+		/* Copy pcdac and gain_f values from EEPROM */
+		chan->pcdac[0]	= (athvals[loc] >> 10) & 0x3F;
+		chan->gainF[0]	= (athvals[loc] >> 4) & 0x3F;
+		chan->pcdac[1]	= ((athvals[loc] << 2) & 0x3C)
+				| ((athvals[loc+1] >> 14) & 0x03);
+		chan->gainF[1]	= (athvals[loc+1] >> 8) & 0x3F;
+		chan->pcdac[2]	= (athvals[loc+1] >> 2) & 0x3F;
+		chan->gainF[2]	= ((athvals[loc+1] << 4) & 0x30)
+				| ((athvals[loc+2] >> 12) & 0x0F);
+		chan->pcdac[3]	= (athvals[loc+2] >> 6) & 0x3F;
+		chan->gainF[3]	= athvals[loc+2] & 0x3F;
+		chan->pcdac[4]	= (athvals[loc+3] >> 10) & 0x3F;
+		chan->gainF[4]	= (athvals[loc+3] >> 4) & 0x3F;
+		chan->pcdac[5]	= ((athvals[loc+3] << 2) & 0x3C)
+				| ((athvals[loc+4] >> 14) & 0x03);
+		chan->gainF[5]	= (athvals[loc+4] >> 8) & 0x3F;
+		chan->pcdac[6]	= (athvals[loc+4] >> 2) & 0x3F;
+		chan->gainF[6]	= ((athvals[loc+4] << 4) & 0x30)
+				| ((athvals[loc+5] >> 12) & 0x0F);
+		chan->pcdac[7]	= (athvals[loc+5] >> 6) & 0x3F;
+		chan->gainF[7]	= athvals[loc+5] & 0x3F;
+		chan->pcdac[8]	= (athvals[loc+6] >> 10) & 0x3F;
+		chan->gainF[8]	= (athvals[loc+6] >> 4) & 0x3F;
+		chan->pcdac[9]	= ((athvals[loc+6] << 2) & 0x3C)
+				| ((athvals[loc+7] >> 14) & 0x03);
+		chan->gainF[9]	= (athvals[loc+7] >> 8) & 0x3F;
+		chan->pcdac[10]	= (athvals[loc+7] >> 2) & 0x3F;
+		chan->gainF[10]	= ((athvals[loc+7] << 4) & 0x30)
+				| ((athvals[loc+8] >> 12) & 0x0F);
+
+		/* Copy Regulatory Domain and Rate Information from EEPROM */
+		chan->rate36	= (athvals[loc+8] >> 6) & 0x3F;
+		chan->rate48	= athvals[loc+8] & 0x3F;
+		chan->rate54	= (athvals[loc+9] >> 10) & 0x3F;
+		chan->regdmn[0]	= (athvals[loc+9] >> 4) & 0x3F;
+		chan->regdmn[1]	= ((athvals[loc+9] << 2) & 0x3C)
+				| ((athvals[loc+10] >> 14) & 0x03);
+		chan->regdmn[2]	= (athvals[loc+10] >> 8) & 0x3F;
+		chan->regdmn[3]	= (athvals[loc+10] >> 2) & 0x3F;
+	}
+
+	AH_PRIVATE(ah)->ah_eeprom = ee;
+	AH_PRIVATE(ah)->ah_eeversion = version;
+	AH_PRIVATE(ah)->ah_eepromDetach = v1EepromDetach;
+	AH_PRIVATE(ah)->ah_eepromGet = v1EepromGet;
+	AH_PRIVATE(ah)->ah_eepromSet = v1EepromSet;
+	AH_PRIVATE(ah)->ah_getSpurChan = v1EepromGetSpurChan;
+	AH_PRIVATE(ah)->ah_eepromDiag = v1EepromDiag;
+	return HAL_OK;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v1.h b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v1.h
new file mode 100644
index 0000000..2c23589
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v1.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_eeprom_v1.h,v 1.1 2008/11/11 02:40:11 sam Exp $
+ */
+#ifndef _ATH_AH_EEPROM_V1_H_
+#define _ATH_AH_EEPROM_V1_H_
+
+#include "ah_eeprom.h"
+
+/*
+ * EEPROM defines for Version 1 Crete EEPROM.
+ *
+ * The EEPROM is segmented into three sections:
+ *
+ *    PCI/Cardbus default configuration settings
+ *    Cardbus CIS tuples and vendor-specific data
+ *    Atheros-specific data
+ *
+ * EEPROM entries are read 32-bits at a time through the PCI bus
+ * interface but are all 16-bit values.
+ *
+ * Access to the Atheros-specific data is controlled by protection
+ * bits and the data is checksum'd.  The driver reads the Atheros
+ * data from the EEPROM at attach and caches it in its private state.
+ * This data includes the local regulatory domain, channel calibration
+ * settings, and phy-related configuration settings.
+ */
+#define	AR_EEPROM_MAC(i)	(0x1f-(i))/* MAC address word */
+#define	AR_EEPROM_MAGIC		0x3d	/* magic number */
+#define AR_EEPROM_PROTECT	0x3f	/* Atheros segment protect register */
+#define	AR_EEPROM_PROTOTECT_WP_128_191	0x80
+#define AR_EEPROM_REG_DOMAIN	0xbf	/* Current regulatory domain register */
+#define AR_EEPROM_ATHEROS_BASE	0xc0	/* Base of Atheros-specific data */
+#define AR_EEPROM_ATHEROS_MAX	64	/* 64x2=128 bytes of EEPROM settings */
+#define	AR_EEPROM_ATHEROS(n)	(AR_EEPROM_ATHEROS_BASE+(n))
+#define	AR_EEPROM_VERSION	AR_EEPROM_ATHEROS(1)
+#define AR_EEPROM_ATHEROS_TP_SETTINGS	0x09	/* Transmit power settings */
+#define AR_REG_DOMAINS_MAX	4	/* # of Regulatory Domains */
+#define AR_CHANNELS_MAX		5	/* # of Channel calibration groups */
+#define AR_TP_SETTINGS_SIZE	11	/* # locations/Channel group */
+#define AR_TP_SCALING_ENTRIES	11	/* # entries in transmit power dBm->pcdac */
+
+/*
+ * NB: we store the rfsilent select+polarity data packed
+ *     with the encoding used in later parts so values
+ *     returned to applications are consistent.
+ */
+#define AR_EEPROM_RFSILENT_GPIO_SEL	0x001c
+#define AR_EEPROM_RFSILENT_GPIO_SEL_S	2
+#define AR_EEPROM_RFSILENT_POLARITY	0x0002
+#define AR_EEPROM_RFSILENT_POLARITY_S	1
+
+#define AR_I2DBM(x)	((uint8_t)((x * 2) + 3))
+
+/*
+ * Transmit power and channel calibration settings.
+ */
+struct tpcMap {
+	uint8_t		pcdac[AR_TP_SCALING_ENTRIES];
+	uint8_t		gainF[AR_TP_SCALING_ENTRIES];
+	uint8_t		rate36;
+	uint8_t		rate48;
+	uint8_t		rate54;
+	uint8_t		regdmn[AR_REG_DOMAINS_MAX];
+};
+
+/*
+ * Information retrieved from EEPROM.
+ */
+typedef struct {
+	uint16_t	ee_version;		/* Version field */
+	uint16_t	ee_protect;		/* EEPROM protect field */
+	uint16_t	ee_antenna;		/* Antenna Settings */
+	uint16_t	ee_biasCurrents;	/* OB, DB */
+	uint8_t		ee_thresh62;		/* thresh62 */
+	uint8_t		ee_xlnaOn;		/* External LNA timing */
+	uint8_t		ee_xpaOff;		/* Extern output stage timing */
+	uint8_t		ee_xpaOn;		/* Extern output stage timing */
+	uint8_t		ee_rfKill;		/* Single low bit signalling if RF Kill is implemented */
+	uint8_t		ee_devType;		/* Type: PCI, miniPCI, CB */
+	uint8_t		ee_regDomain[AR_REG_DOMAINS_MAX];
+						/* calibrated reg domains */
+	struct tpcMap	ee_tpc[AR_CHANNELS_MAX];
+} HAL_EEPROM_v1;
+#endif /* _ATH_AH_EEPROM_V1_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v14.c b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v14.c
new file mode 100644
index 0000000..0340323
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v14.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ah_eeprom_v14.c,v 1.3.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_eeprom_v14.h"
+
+static HAL_STATUS
+v14EepromGet(struct ath_hal *ah, int param, void *val)
+{
+#define	CHAN_A_IDX	0
+#define	CHAN_B_IDX	1
+#define	IS_VERS(op, v)	((pBase->version & AR5416_EEP_VER_MINOR_MASK) op (v))
+	HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const MODAL_EEP_HEADER *pModal = ee->ee_base.modalHeader;
+	const BASE_EEP_HEADER  *pBase  = &ee->ee_base.baseEepHeader;
+	uint32_t sum;
+	uint8_t *macaddr;
+	int i;
+
+	switch (param) {
+        case AR_EEP_NFTHRESH_5:
+		*(int16_t *)val = pModal[0].noiseFloorThreshCh[0];
+		return HAL_OK;
+        case AR_EEP_NFTHRESH_2:
+		*(int16_t *)val = pModal[1].noiseFloorThreshCh[0];
+		return HAL_OK;
+        case AR_EEP_MACADDR:		/* Get MAC Address */
+		sum = 0;
+		macaddr = val;
+		for (i = 0; i < 6; i++) {
+			macaddr[i] = pBase->macAddr[i];
+			sum += pBase->macAddr[i];
+		}
+		if (sum == 0 || sum == 0xffff*3) {
+			HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",
+			    __func__, ath_hal_ether_sprintf(macaddr));
+			return HAL_EEBADMAC;
+		}
+		return HAL_OK;
+        case AR_EEP_REGDMN_0:
+		return pBase->regDmn[0];
+        case AR_EEP_REGDMN_1:
+		return pBase->regDmn[1];
+        case AR_EEP_OPCAP:
+		return pBase->deviceCap;
+        case AR_EEP_OPMODE:
+		return pBase->opCapFlags;
+        case AR_EEP_RFSILENT:
+		return pBase->rfSilent;
+	case AR_EEP_OB_5:
+		return pModal[CHAN_A_IDX].ob;
+    	case AR_EEP_DB_5:
+		return pModal[CHAN_A_IDX].db;
+    	case AR_EEP_OB_2:
+		return pModal[CHAN_B_IDX].ob;
+    	case AR_EEP_DB_2:
+		return pModal[CHAN_B_IDX].db;
+	case AR_EEP_TXMASK:
+		return pBase->txMask;
+	case AR_EEP_RXMASK:
+		return pBase->rxMask;
+	case AR_EEP_RXGAIN_TYPE:
+		return IS_VERS(>=, AR5416_EEP_MINOR_VER_17) ?
+		    pBase->rxGainType : AR5416_EEP_RXGAIN_ORIG;
+	case AR_EEP_TXGAIN_TYPE:
+		return IS_VERS(>=, AR5416_EEP_MINOR_VER_19) ?
+		    pBase->txGainType : AR5416_EEP_TXGAIN_ORIG;
+	case AR_EEP_FSTCLK_5G:
+		return IS_VERS(>, AR5416_EEP_MINOR_VER_16) ?
+		    pBase->fastClk5g : AH_TRUE;
+	case AR_EEP_OL_PWRCTRL:
+		HALASSERT(val == AH_NULL);
+		return pBase->openLoopPwrCntl ?  HAL_OK : HAL_EIO;
+	case AR_EEP_AMODE:
+		HALASSERT(val == AH_NULL);
+		return pBase->opCapFlags & AR5416_OPFLAGS_11A ?
+		    HAL_OK : HAL_EIO;
+	case AR_EEP_BMODE:
+	case AR_EEP_GMODE:
+		HALASSERT(val == AH_NULL);
+		return pBase->opCapFlags & AR5416_OPFLAGS_11G ?
+		    HAL_OK : HAL_EIO;
+	case AR_EEP_32KHZCRYSTAL:
+	case AR_EEP_COMPRESS:
+	case AR_EEP_FASTFRAME:		/* XXX policy decision, h/w can do it */
+	case AR_EEP_WRITEPROTECT:	/* NB: no write protect bit */
+		HALASSERT(val == AH_NULL);
+		/* fall thru... */
+	case AR_EEP_MAXQCU:		/* NB: not in opCapFlags */
+	case AR_EEP_KCENTRIES:		/* NB: not in opCapFlags */
+		return HAL_EIO;
+	case AR_EEP_AES:
+	case AR_EEP_BURST:
+        case AR_EEP_RFKILL:
+	case AR_EEP_TURBO5DISABLE:
+	case AR_EEP_TURBO2DISABLE:
+		HALASSERT(val == AH_NULL);
+		return HAL_OK;
+	case AR_EEP_ANTGAINMAX_2:
+		*(int8_t *) val = ee->ee_antennaGainMax[1];
+		return HAL_OK;
+	case AR_EEP_ANTGAINMAX_5:
+		*(int8_t *) val = ee->ee_antennaGainMax[0];
+		return HAL_OK;
+        default:
+		HALASSERT(0);
+		return HAL_EINVAL;
+	}
+#undef IS_VERS
+#undef CHAN_A_IDX
+#undef CHAN_B_IDX
+}
+
+static HAL_BOOL
+v14EepromSet(struct ath_hal *ah, int param, int v)
+{
+	HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	switch (param) {
+	case AR_EEP_ANTGAINMAX_2:
+		ee->ee_antennaGainMax[1] = (int8_t) v;
+		return HAL_OK;
+	case AR_EEP_ANTGAINMAX_5:
+		ee->ee_antennaGainMax[0] = (int8_t) v;
+		return HAL_OK;
+	}
+	return HAL_EINVAL;
+}
+
+static HAL_BOOL
+v14EepromDiag(struct ath_hal *ah, int request,
+     const void *args, uint32_t argsize, void **result, uint32_t *resultsize)
+{
+	HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	switch (request) {
+	case HAL_DIAG_EEPROM:
+		*result = &ee->ee_base;
+		*resultsize = sizeof(ee->ee_base);
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/* Do structure specific swaps if Eeprom format is non native to host */
+static void
+eepromSwap(struct ar5416eeprom *ee)
+{
+	uint32_t integer, i, j;
+	uint16_t word;
+	MODAL_EEP_HEADER *pModal;
+
+	/* convert Base Eep header */
+	word = __bswap16(ee->baseEepHeader.length);
+	ee->baseEepHeader.length = word;
+
+	word = __bswap16(ee->baseEepHeader.checksum);
+	ee->baseEepHeader.checksum = word;
+
+	word = __bswap16(ee->baseEepHeader.version);
+	ee->baseEepHeader.version = word;
+
+	word = __bswap16(ee->baseEepHeader.regDmn[0]);
+	ee->baseEepHeader.regDmn[0] = word;
+
+	word = __bswap16(ee->baseEepHeader.regDmn[1]);
+	ee->baseEepHeader.regDmn[1] = word;
+
+	word = __bswap16(ee->baseEepHeader.rfSilent);
+	ee->baseEepHeader.rfSilent = word;
+
+	word = __bswap16(ee->baseEepHeader.blueToothOptions);
+	ee->baseEepHeader.blueToothOptions = word; 
+
+	word = __bswap16(ee->baseEepHeader.deviceCap);
+	ee->baseEepHeader.deviceCap = word;
+
+	/* convert Modal Eep header */
+	for (j = 0; j < 2; j++) {
+		pModal = &ee->modalHeader[j];
+
+		/* XXX linux/ah_osdep.h only defines __bswap32 for BE */
+		integer = __bswap32(pModal->antCtrlCommon);
+		pModal->antCtrlCommon = integer;
+
+		for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+			integer = __bswap32(pModal->antCtrlChain[i]);
+			pModal->antCtrlChain[i] = integer;
+		}
+
+		for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+			word = __bswap16(pModal->spurChans[i].spurChan);
+			pModal->spurChans[i].spurChan = word;
+		}
+	}
+}
+
+static uint16_t 
+v14EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)
+{ 
+	HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+	
+	HALASSERT(0 <= ix && ix <  AR5416_EEPROM_MODAL_SPURS);
+	return ee->ee_base.modalHeader[is2GHz].spurChans[ix].spurChan;
+}
+
+/**************************************************************************
+ * fbin2freq
+ *
+ * Get channel value from binary representation held in eeprom
+ * RETURNS: the frequency in MHz
+ */
+static uint16_t
+fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
+{
+	/*
+	 * Reserved value 0xFF provides an empty definition both as
+	 * an fbin and as a frequency - do not convert
+	 */
+	if (fbin == AR5416_BCHAN_UNUSED)
+		return fbin;
+	return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
+}
+
+/*
+ * Copy EEPROM Conformance Testing Limits contents 
+ * into the allocated space
+ */
+/* USE CTLS from chain zero */ 
+#define CTL_CHAIN	0 
+
+static void
+v14EepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v14 *ee)
+{
+	RD_EDGES_POWER *rep = ee->ee_rdEdgesPower;
+	int i, j;
+	
+	HALASSERT(AR5416_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES);
+
+	for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_NUM_CTLS; i++) {
+		for (j = 0; j < NUM_EDGES; j ++) {
+			/* XXX Confirm this is the right thing to do when an invalid channel is stored */
+			if (ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].bChannel == AR5416_BCHAN_UNUSED) {
+				rep[j].rdEdge = 0;
+				rep[j].twice_rdEdgePower = 0;
+				rep[j].flag = 0;
+			} else {
+				rep[j].rdEdge = fbin2freq(
+				    ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].bChannel,
+				    (ee->ee_base.ctlIndex[i] & CTL_MODE_M) != CTL_11A);
+				rep[j].twice_rdEdgePower = MS(ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].tPowerFlag, CAL_CTL_EDGES_POWER);
+				rep[j].flag = MS(ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].tPowerFlag, CAL_CTL_EDGES_FLAG) != 0;
+			}
+		}
+		rep += NUM_EDGES;
+	}
+	ee->ee_numCtls = i;
+	HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
+	    "%s Numctls = %u\n",__func__,i);
+}
+
+/*
+ * Reclaim any EEPROM-related storage.
+ */
+static void
+v14EepromDetach(struct ath_hal *ah)
+{
+	HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	ath_hal_free(ee);
+	AH_PRIVATE(ah)->ah_eeprom = AH_NULL;
+}
+
+#define owl_get_eep_ver(_ee)   \
+    (((_ee)->ee_base.baseEepHeader.version >> 12) & 0xF)
+#define owl_get_eep_rev(_ee)   \
+    (((_ee)->ee_base.baseEepHeader.version) & 0xFFF)
+
+HAL_STATUS
+ath_hal_v14EepromAttach(struct ath_hal *ah)
+{
+#define	NW(a)	(sizeof(a) / sizeof(uint16_t))
+	HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t *eep_data, magic;
+	HAL_BOOL need_swap;
+	u_int w, off, len;
+	uint32_t sum;
+
+	HALASSERT(ee == AH_NULL);
+ 
+	if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s Error reading Eeprom MAGIC\n", __func__);
+		return HAL_EEREAD;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",
+	    __func__, magic);
+	if (magic != AR5416_EEPROM_MAGIC) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");
+		return HAL_EEMAGIC;
+	}
+
+	ee = ath_hal_malloc(sizeof(HAL_EEPROM_v14));
+	if (ee == AH_NULL) {
+		/* XXX message */
+		return HAL_ENOMEM;
+	}
+
+	eep_data = (uint16_t *)&ee->ee_base;
+	for (w = 0; w < NW(struct ar5416eeprom); w++) {
+		off = owl_eep_start_loc + w;	/* NB: AP71 starts at 0 */
+		if (!ath_hal_eepromRead(ah, off, &eep_data[w])) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s eeprom read error at offset 0x%x\n",
+			    __func__, off);
+			return HAL_EEREAD;
+		}
+	}
+	/* Convert to eeprom native eeprom endian format */
+	if (isBigEndian()) {
+		for (w = 0; w < NW(struct ar5416eeprom); w++)
+			eep_data[w] = __bswap16(eep_data[w]);
+	}
+
+	/*
+	 * At this point, we're in the native eeprom endian format
+	 * Now, determine the eeprom endian by looking at byte 26??
+	 */
+	need_swap = ((ee->ee_base.baseEepHeader.eepMisc & AR5416_EEPMISC_BIG_ENDIAN) != 0) ^ isBigEndian();
+	if (need_swap) {
+		HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
+		    "Byte swap EEPROM contents.\n");
+		len = __bswap16(ee->ee_base.baseEepHeader.length);
+	} else {
+		len = ee->ee_base.baseEepHeader.length;
+	}
+	len = AH_MIN(len, sizeof(struct ar5416eeprom)) / sizeof(uint16_t);
+	
+	/* Apply the checksum, done in native eeprom format */
+	/* XXX - Need to check to make sure checksum calculation is done
+	 * in the correct endian format.  Right now, it seems it would
+	 * cast the raw data to host format and do the calculation, which may
+	 * not be correct as the calculation may need to be done in the native
+	 * eeprom format 
+	 */
+	sum = 0;
+	for (w = 0; w < len; w++)
+		sum ^= eep_data[w];
+	/* Check CRC - Attach should fail on a bad checksum */
+	if (sum != 0xffff) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "Bad EEPROM checksum 0x%x (Len=%u)\n", sum, len);
+		return HAL_EEBADSUM;
+	}
+
+	if (need_swap)
+		eepromSwap(&ee->ee_base);	/* byte swap multi-byte data */
+
+	/* swap words 0+2 so version is at the front */
+	magic = eep_data[0];
+	eep_data[0] = eep_data[2];
+	eep_data[2] = magic;
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
+	    "%s Eeprom Version %u.%u\n", __func__,
+	    owl_get_eep_ver(ee), owl_get_eep_rev(ee));
+
+	/* NB: must be after all byte swapping */
+	if (owl_get_eep_ver(ee) != AR5416_EEP_VER) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "Bad EEPROM version 0x%x\n", owl_get_eep_ver(ee));
+		return HAL_EEBADSUM;
+	}
+
+	v14EepromReadCTLInfo(ah, ee);		/* Get CTLs */
+
+	AH_PRIVATE(ah)->ah_eeprom = ee;
+	AH_PRIVATE(ah)->ah_eeversion = ee->ee_base.baseEepHeader.version;
+	AH_PRIVATE(ah)->ah_eepromDetach = v14EepromDetach;
+	AH_PRIVATE(ah)->ah_eepromGet = v14EepromGet;
+	AH_PRIVATE(ah)->ah_eepromSet = v14EepromSet;
+	AH_PRIVATE(ah)->ah_getSpurChan = v14EepromGetSpurChan;
+	AH_PRIVATE(ah)->ah_eepromDiag = v14EepromDiag;
+	return HAL_OK;
+#undef NW
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v14.h b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v14.h
new file mode 100644
index 0000000..90e2c74
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v14.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_eeprom_v14.h,v 1.3 2008/11/10 04:08:00 sam Exp $
+ */
+#ifndef _AH_EEPROM_V14_H_
+#define _AH_EEPROM_V14_H_
+
+#include "ah_eeprom.h"
+
+/* reg_off = 4 * (eep_off) */
+#define AR5416_EEPROM_S			2
+#define AR5416_EEPROM_OFFSET		0x2000
+#define AR5416_EEPROM_START_ADDR	0x503f1200
+#define AR5416_EEPROM_MAX		0xae0 /* Ignore for the moment used only on the flash implementations */
+#define AR5416_EEPROM_MAGIC		0xa55a
+#define AR5416_EEPROM_MAGIC_OFFSET	0x0
+
+#define owl_get_ntxchains(_txchainmask) \
+    (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
+
+#ifdef __LINUX_ARM_ARCH__ /* AP71 */
+#define owl_eep_start_loc		0
+#else
+#define owl_eep_start_loc		256
+#endif
+
+/* End temp defines */
+
+#define AR5416_EEP_NO_BACK_VER       	0x1
+#define AR5416_EEP_VER               	0xE
+#define AR5416_EEP_VER_MINOR_MASK	0xFFF
+// Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc
+#define AR5416_EEP_MINOR_VER_2		0x2
+// Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable
+#define AR5416_EEP_MINOR_VER_3		0x3
+#define AR5416_EEP_MINOR_VER_7		0x7
+#define AR5416_EEP_MINOR_VER_9		0x9
+#define AR5416_EEP_MINOR_VER_16		0x10
+#define AR5416_EEP_MINOR_VER_17		0x11
+#define AR5416_EEP_MINOR_VER_19		0x13
+
+// 16-bit offset location start of calibration struct
+#define AR5416_EEP_START_LOC         	256
+#define AR5416_NUM_5G_CAL_PIERS      	8
+#define AR5416_NUM_2G_CAL_PIERS      	4
+#define AR5416_NUM_5G_20_TARGET_POWERS  8
+#define AR5416_NUM_5G_40_TARGET_POWERS  8
+#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
+#define AR5416_NUM_2G_20_TARGET_POWERS  4
+#define AR5416_NUM_2G_40_TARGET_POWERS  4
+#define AR5416_NUM_CTLS              	24
+#define AR5416_NUM_BAND_EDGES        	8
+#define AR5416_NUM_PD_GAINS          	4
+#define AR5416_PD_GAINS_IN_MASK      	4
+#define AR5416_PD_GAIN_ICEPTS        	5
+#define AR5416_EEPROM_MODAL_SPURS    	5
+#define AR5416_MAX_RATE_POWER        	63
+#define AR5416_NUM_PDADC_VALUES      	128
+#define AR5416_NUM_RATES             	16
+#define AR5416_BCHAN_UNUSED          	0xFF
+#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
+#define AR5416_EEPMISC_BIG_ENDIAN    	0x01
+#define FREQ2FBIN(x,y) 			((y) ? ((x) - 2300) : (((x) - 4800) / 5))
+#define AR5416_MAX_CHAINS            	3
+#define AR5416_ANT_16S               	25
+
+#define AR5416_NUM_ANT_CHAIN_FIELDS     7
+#define AR5416_NUM_ANT_COMMON_FIELDS    4
+#define AR5416_SIZE_ANT_CHAIN_FIELD     3
+#define AR5416_SIZE_ANT_COMMON_FIELD    4
+#define AR5416_ANT_CHAIN_MASK           0x7
+#define AR5416_ANT_COMMON_MASK          0xf
+#define AR5416_CHAIN_0_IDX              0
+#define AR5416_CHAIN_1_IDX              1
+#define AR5416_CHAIN_2_IDX              2
+
+#define	AR5416_OPFLAGS_11A		0x01
+#define	AR5416_OPFLAGS_11G		0x02
+#define	AR5416_OPFLAGS_5G_HT40		0x04
+#define	AR5416_OPFLAGS_2G_HT40		0x08
+#define	AR5416_OPFLAGS_5G_HT20		0x10
+#define	AR5416_OPFLAGS_2G_HT20		0x20
+
+/* RF silent fields in EEPROM */
+#define	EEP_RFSILENT_ENABLED		0x0001	/* enabled/disabled */
+#define	EEP_RFSILENT_ENABLED_S		0
+#define	EEP_RFSILENT_POLARITY		0x0002	/* polarity */
+#define	EEP_RFSILENT_POLARITY_S		1
+#define	EEP_RFSILENT_GPIO_SEL		0x001c	/* gpio PIN */
+#define	EEP_RFSILENT_GPIO_SEL_S		2
+
+/* Rx gain type values */
+#define	AR5416_EEP_RXGAIN_23dB_BACKOFF	0
+#define	AR5416_EEP_RXGAIN_13dB_BACKOFF	1
+#define	AR5416_EEP_RXGAIN_ORIG		2
+
+/* Tx gain type values */
+#define	AR5416_EEP_TXGAIN_ORIG		0
+#define	AR5416_EEP_TXGAIN_HIGH_POWER	1
+
+typedef struct spurChanStruct {
+	uint16_t	spurChan;
+	uint8_t		spurRangeLow;
+	uint8_t		spurRangeHigh;
+} __packed SPUR_CHAN;
+
+typedef struct CalTargetPowerLegacy {
+	uint8_t		bChannel;
+	uint8_t		tPow2x[4];
+} __packed CAL_TARGET_POWER_LEG;
+
+typedef struct CalTargetPowerHt {
+	uint8_t		bChannel;
+	uint8_t		tPow2x[8];
+} __packed CAL_TARGET_POWER_HT;
+
+typedef struct CalCtlEdges {
+	uint8_t		bChannel;
+	uint8_t		tPowerFlag;	/* [0..5] tPower [6..7] flag */
+#define	CAL_CTL_EDGES_POWER	0x3f
+#define	CAL_CTL_EDGES_POWER_S	0
+#define	CAL_CTL_EDGES_FLAG	0xc0
+#define	CAL_CTL_EDGES_FLAG_S	6
+} __packed CAL_CTL_EDGES;
+
+/*
+ * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
+ * and length are swapped).  We reverse their position after reading
+ * the data into host memory so the version field is at the same
+ * offset as in previous EEPROM layouts.  This makes utilities that
+ * inspect the EEPROM contents work without looking at the PCI device
+ * id which may or may not be reliable.
+ */
+typedef struct BaseEepHeader {
+	uint16_t	version;	/* NB: length in EEPROM */
+	uint16_t	checksum;
+	uint16_t	length;		/* NB: version in EEPROM */
+	uint8_t		opCapFlags;
+	uint8_t		eepMisc;
+	uint16_t	regDmn[2];
+	uint8_t		macAddr[6];
+	uint8_t		rxMask;
+	uint8_t		txMask;
+	uint16_t	rfSilent;
+	uint16_t	blueToothOptions;
+	uint16_t	deviceCap;
+	uint32_t	binBuildNumber;
+	uint8_t		deviceType;
+	uint8_t		pwdclkind;
+	uint8_t		fastClk5g;
+	uint8_t		divChain;  
+	uint8_t		rxGainType;
+	uint8_t		dacHiPwrMode;	/* use the DAC high power mode (MB91) */
+	uint8_t		openLoopPwrCntl;/* 1: use open loop power control,
+					   0: use closed loop power control */
+	uint8_t		dacLpMode;
+	uint8_t		txGainType;	/* high power tx gain table support */
+	uint8_t		rcChainMask;	/* "1" if the card is an HB93 1x2 */
+	uint8_t		futureBase[24];
+} __packed BASE_EEP_HEADER; // 64 B
+
+typedef struct ModalEepHeader {
+	uint32_t	antCtrlChain[AR5416_MAX_CHAINS];	// 12
+	uint32_t	antCtrlCommon;				// 4
+	int8_t		antennaGainCh[AR5416_MAX_CHAINS];	// 3
+	uint8_t		switchSettling;				// 1
+	uint8_t		txRxAttenCh[AR5416_MAX_CHAINS];		// 3
+	uint8_t		rxTxMarginCh[AR5416_MAX_CHAINS];	// 3
+	uint8_t		adcDesiredSize;				// 1
+	int8_t		pgaDesiredSize;				// 1
+	uint8_t		xlnaGainCh[AR5416_MAX_CHAINS];		// 3
+	uint8_t		txEndToXpaOff;				// 1
+	uint8_t		txEndToRxOn;				// 1
+	uint8_t		txFrameToXpaOn;				// 1
+	uint8_t		thresh62;				// 1
+	uint8_t		noiseFloorThreshCh[AR5416_MAX_CHAINS];	// 3
+	uint8_t		xpdGain;				// 1
+	uint8_t		xpd;					// 1
+	int8_t		iqCalICh[AR5416_MAX_CHAINS];		// 1
+	int8_t		iqCalQCh[AR5416_MAX_CHAINS];		// 1
+	uint8_t		pdGainOverlap;				// 1
+	uint8_t		ob;					// 1
+	uint8_t		db;					// 1
+	uint8_t		xpaBiasLvl;				// 1
+	uint8_t		pwrDecreaseFor2Chain;			// 1
+	uint8_t		pwrDecreaseFor3Chain;			// 1 -> 48 B
+	uint8_t		txFrameToDataStart;			// 1
+	uint8_t		txFrameToPaOn;				// 1
+	uint8_t		ht40PowerIncForPdadc;			// 1
+	uint8_t		bswAtten[AR5416_MAX_CHAINS];		// 3
+	uint8_t		bswMargin[AR5416_MAX_CHAINS];		// 3
+	uint8_t		swSettleHt40;				// 1	
+	uint8_t		xatten2Db[AR5416_MAX_CHAINS];    	// 3 -> New for AR9280 (0xa20c/b20c 11:6)
+	uint8_t		xatten2Margin[AR5416_MAX_CHAINS];	// 3 -> New for AR9280 (0xa20c/b20c 21:17)
+	uint8_t		ob_ch1;				// 1 -> ob and db become chain specific from AR9280
+	uint8_t		db_ch1;				// 1
+	uint8_t		flagBits;			// 1
+#define	AR5416_EEP_FLAG_USEANT1		0x01	/* +1 configured antenna */
+#define	AR5416_EEP_FLAG_FORCEXPAON	0x02	/* force XPA bit for 5G */
+#define	AR5416_EEP_FLAG_LOCALBIAS	0x04	/* enable local bias */
+#define	AR5416_EEP_FLAG_FEMBANDSELECT	0x08	/* FEM band select used */
+#define	AR5416_EEP_FLAG_XLNABUFIN	0x10
+#define	AR5416_EEP_FLAG_XLNAISEL	0x60
+#define	AR5416_EEP_FLAG_XLNAISEL_S	5
+#define	AR5416_EEP_FLAG_XLNABUFMODE	0x80
+	uint8_t		miscBits;			// [0..1]: bb_tx_dac_scale_cck
+	uint16_t	xpaBiasLvlFreq[3];		// 3
+	uint8_t		futureModal[6];			// 6
+
+	SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS];	// 20 B
+} __packed MODAL_EEP_HEADER;				// == 100 B    
+
+typedef struct calDataPerFreqOpLoop {
+	uint8_t		pwrPdg[2][5]; /* power measurement */
+	uint8_t		vpdPdg[2][5]; /* pdadc voltage at power measurement */
+	uint8_t		pcdac[2][5];  /* pcdac used for power measurement */
+	uint8_t		empty[2][5];  /* future use */
+} __packed CAL_DATA_PER_FREQ_OP_LOOP;
+
+typedef struct CalCtlData {
+	CAL_CTL_EDGES		ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
+} __packed CAL_CTL_DATA;
+
+typedef struct calDataPerFreq {
+	uint8_t		pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+	uint8_t		vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+} __packed CAL_DATA_PER_FREQ;
+
+struct ar5416eeprom {
+	BASE_EEP_HEADER		baseEepHeader;         // 64 B
+	uint8_t			custData[64];          // 64 B
+	MODAL_EEP_HEADER	modalHeader[2];        // 200 B
+	uint8_t			calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
+	uint8_t			calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
+	CAL_DATA_PER_FREQ	calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
+	CAL_DATA_PER_FREQ	calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
+	CAL_TARGET_POWER_LEG	calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
+	CAL_TARGET_POWER_HT	calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
+	CAL_TARGET_POWER_HT	calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
+	CAL_TARGET_POWER_LEG	calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
+	CAL_TARGET_POWER_LEG	calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
+	CAL_TARGET_POWER_HT	calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
+	CAL_TARGET_POWER_HT	calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
+	uint8_t			ctlIndex[AR5416_NUM_CTLS];
+	CAL_CTL_DATA		ctlData[AR5416_NUM_CTLS];
+	uint8_t			padding;			
+} __packed;
+
+typedef struct {
+	struct ar5416eeprom ee_base;
+#define NUM_EDGES	 8
+	uint16_t	ee_numCtls;
+	RD_EDGES_POWER	ee_rdEdgesPower[NUM_EDGES*AR5416_NUM_CTLS];
+	/* XXX these are dynamically calculated for use by shared code */
+	int8_t		ee_antennaGainMax[2];
+} HAL_EEPROM_v14;
+#endif /* _AH_EEPROM_V14_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v3.c b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v3.c
new file mode 100644
index 0000000..dbee989
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v3.c
@@ -0,0 +1,1876 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ah_eeprom_v3.c,v 1.2.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_eeprom_v3.h"
+
+static void
+getPcdacInterceptsFromPcdacMinMax(HAL_EEPROM *ee,
+	uint16_t pcdacMin, uint16_t pcdacMax, uint16_t *vp)
+{
+	static const uint16_t intercepts3[] =
+		{ 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
+	static const uint16_t intercepts3_2[] =
+		{ 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
+	const uint16_t *ip = ee->ee_version < AR_EEPROM_VER3_2 ?
+		intercepts3 : intercepts3_2;
+	int i;
+
+	/* loop for the percentages in steps or 5 */
+	for (i = 0; i < NUM_INTERCEPTS; i++ )
+		*vp++ = (ip[i] * pcdacMax + (100 - ip[i]) * pcdacMin) / 100;
+}
+
+/*
+ * Get channel value from binary representation held in eeprom
+ */
+static uint16_t
+fbin2freq(HAL_EEPROM *ee, uint16_t fbin)
+{
+	if (fbin == CHANNEL_UNUSED)	/* reserved value, don't convert */
+		return fbin;
+	return ee->ee_version <= AR_EEPROM_VER3_2 ?
+		(fbin > 62 ? 5100 + 10*62 + 5*(fbin-62) : 5100 + 10*fbin) :
+		4800 + 5*fbin;
+}
+
+static uint16_t
+fbin2freq_2p4(HAL_EEPROM *ee, uint16_t fbin)
+{
+	if (fbin == CHANNEL_UNUSED)	/* reserved value, don't convert */
+		return fbin;
+	return ee->ee_version <= AR_EEPROM_VER3_2 ?
+		2400 + fbin :
+		2300 + fbin;
+}
+
+/*
+ * Now copy EEPROM frequency pier contents into the allocated space
+ */
+static HAL_BOOL
+readEepromFreqPierInfo(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+#define	EEREAD(_off) do {				\
+	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
+		return AH_FALSE;			\
+} while (0)
+	uint16_t eeval, off;
+	int i;
+
+	if (ee->ee_version >= AR_EEPROM_VER4_0 &&
+	    ee->ee_eepMap && !ee->ee_Amode) {
+		/*
+		 * V4.0 EEPROMs with map type 1 have frequency pier
+		 * data only when 11a mode is supported.
+		 */
+		return AH_TRUE;
+	}
+	if (ee->ee_version >= AR_EEPROM_VER3_3) {
+		off = GROUPS_OFFSET3_3 + GROUP1_OFFSET;
+		for (i = 0; i < ee->ee_numChannels11a; i += 2) {
+			EEREAD(off++);
+			ee->ee_channels11a[i]   = (eeval >> 8) & FREQ_MASK_3_3;
+			ee->ee_channels11a[i+1] = eeval & FREQ_MASK_3_3;
+		} 
+	} else {
+		off = GROUPS_OFFSET3_2 + GROUP1_OFFSET;
+
+		EEREAD(off++);
+		ee->ee_channels11a[0] = (eeval >> 9) & FREQ_MASK;
+		ee->ee_channels11a[1] = (eeval >> 2) & FREQ_MASK;
+		ee->ee_channels11a[2] = (eeval << 5) & FREQ_MASK;
+
+		EEREAD(off++);
+		ee->ee_channels11a[2] |= (eeval >> 11) & 0x1f;
+		ee->ee_channels11a[3]  = (eeval >>  4) & FREQ_MASK;
+		ee->ee_channels11a[4]  = (eeval <<  3) & FREQ_MASK;
+
+		EEREAD(off++);
+		ee->ee_channels11a[4] |= (eeval >> 13) & 0x7;
+		ee->ee_channels11a[5]  = (eeval >>  6) & FREQ_MASK;
+		ee->ee_channels11a[6]  = (eeval <<  1) & FREQ_MASK;
+
+		EEREAD(off++);
+		ee->ee_channels11a[6] |= (eeval >> 15) & 0x1;
+		ee->ee_channels11a[7]  = (eeval >>  8) & FREQ_MASK;
+		ee->ee_channels11a[8]  = (eeval >>  1) & FREQ_MASK;
+		ee->ee_channels11a[9]  = (eeval <<  6) & FREQ_MASK;
+
+		EEREAD(off++);
+		ee->ee_channels11a[9] |= (eeval >> 10) & 0x3f;
+	}
+
+	for (i = 0; i < ee->ee_numChannels11a; i++)
+		ee->ee_channels11a[i] = fbin2freq(ee, ee->ee_channels11a[i]);
+
+	return AH_TRUE;
+#undef EEREAD
+}
+
+/*
+ * Rev 4 Eeprom 5112 Power Extract Functions
+ */
+
+/*
+ * Allocate the power information based on the number of channels
+ * recorded by the calibration.  These values are then initialized.
+ */
+static HAL_BOOL
+eepromAllocExpnPower5112(struct ath_hal *ah,
+	const EEPROM_POWER_5112 *pCalDataset,
+	EEPROM_POWER_EXPN_5112 *pPowerExpn)
+{
+	uint16_t numChannels = pCalDataset->numChannels;
+	const uint16_t *pChanList = pCalDataset->pChannels;
+	void *data;
+	int i, j;
+
+	/* Allocate the channel and Power Data arrays together */
+	data = ath_hal_malloc(
+		roundup(sizeof(uint16_t) * numChannels, sizeof(uint32_t)) +
+		sizeof(EXPN_DATA_PER_CHANNEL_5112) * numChannels);
+	if (data == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s unable to allocate raw data struct (gen3)\n", __func__);
+		return AH_FALSE;
+	}
+	pPowerExpn->pChannels = data;
+	pPowerExpn->pDataPerChannel = (void *)(((char *)data) +
+		roundup(sizeof(uint16_t) * numChannels, sizeof(uint32_t)));
+
+	pPowerExpn->numChannels = numChannels;
+	for (i = 0; i < numChannels; i++) {
+		pPowerExpn->pChannels[i] =
+			pPowerExpn->pDataPerChannel[i].channelValue =
+				pChanList[i];
+		for (j = 0; j < NUM_XPD_PER_CHANNEL; j++) {
+			pPowerExpn->pDataPerChannel[i].pDataPerXPD[j].xpd_gain = j;
+			pPowerExpn->pDataPerChannel[i].pDataPerXPD[j].numPcdacs = 0;
+		}
+		pPowerExpn->pDataPerChannel[i].pDataPerXPD[0].numPcdacs = 4;
+		pPowerExpn->pDataPerChannel[i].pDataPerXPD[3].numPcdacs = 3;
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Expand the dataSet from the calibration information into the
+ * final power structure for 5112
+ */
+static HAL_BOOL
+eepromExpandPower5112(struct ath_hal *ah,
+	const EEPROM_POWER_5112 *pCalDataset,
+	EEPROM_POWER_EXPN_5112 *pPowerExpn)
+{
+	int ii, jj, kk;
+	int16_t maxPower_t4;
+	EXPN_DATA_PER_XPD_5112 *pExpnXPD;
+	/* ptr to array of info held per channel */
+	const EEPROM_DATA_PER_CHANNEL_5112 *pCalCh;
+	uint16_t xgainList[2], xpdMask;
+
+	pPowerExpn->xpdMask = pCalDataset->xpdMask;
+
+	xgainList[0] = 0xDEAD;
+	xgainList[1] = 0xDEAD;
+
+	kk = 0;
+	xpdMask = pPowerExpn->xpdMask;
+	for (jj = 0; jj < NUM_XPD_PER_CHANNEL; jj++) {
+		if (((xpdMask >> jj) & 1) > 0) {
+			if (kk > 1) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+				    "%s: too many xpdGains in dataset: %u\n",
+				    __func__, kk);
+				return AH_FALSE;
+			}
+			xgainList[kk++] = jj;
+		}
+	}
+
+	pPowerExpn->numChannels = pCalDataset->numChannels;
+	if (pPowerExpn->numChannels == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: no channels\n", __func__);
+		return AH_FALSE;
+	}
+
+	for (ii = 0; ii < pPowerExpn->numChannels; ii++) {
+		pCalCh = &pCalDataset->pDataPerChannel[ii];
+		pPowerExpn->pDataPerChannel[ii].channelValue =
+			pCalCh->channelValue;
+		pPowerExpn->pDataPerChannel[ii].maxPower_t4 =
+			pCalCh->maxPower_t4;
+		maxPower_t4 = pPowerExpn->pDataPerChannel[ii].maxPower_t4;
+
+		for (jj = 0; jj < NUM_XPD_PER_CHANNEL; jj++)
+			pPowerExpn->pDataPerChannel[ii].pDataPerXPD[jj].numPcdacs = 0;
+		if (xgainList[1] == 0xDEAD) {
+			jj = xgainList[0];
+			pExpnXPD = &pPowerExpn->pDataPerChannel[ii].pDataPerXPD[jj];
+			pExpnXPD->numPcdacs = 4;
+			pExpnXPD->pcdac[0] = pCalCh->pcd1_xg0;
+			pExpnXPD->pcdac[1] = (uint16_t)
+				(pExpnXPD->pcdac[0] + pCalCh->pcd2_delta_xg0);
+			pExpnXPD->pcdac[2] = (uint16_t)
+				(pExpnXPD->pcdac[1] + pCalCh->pcd3_delta_xg0);
+			pExpnXPD->pcdac[3] = (uint16_t)
+				(pExpnXPD->pcdac[2] + pCalCh->pcd4_delta_xg0);
+
+			pExpnXPD->pwr_t4[0] = pCalCh->pwr1_xg0;
+			pExpnXPD->pwr_t4[1] = pCalCh->pwr2_xg0;
+			pExpnXPD->pwr_t4[2] = pCalCh->pwr3_xg0;
+			pExpnXPD->pwr_t4[3] = pCalCh->pwr4_xg0;
+
+		} else {
+			pPowerExpn->pDataPerChannel[ii].pDataPerXPD[xgainList[0]].pcdac[0] = pCalCh->pcd1_xg0;
+			pPowerExpn->pDataPerChannel[ii].pDataPerXPD[xgainList[1]].pcdac[0] = 20;
+			pPowerExpn->pDataPerChannel[ii].pDataPerXPD[xgainList[1]].pcdac[1] = 35;
+			pPowerExpn->pDataPerChannel[ii].pDataPerXPD[xgainList[1]].pcdac[2] = 63;
+
+			jj = xgainList[0];
+			pExpnXPD = &pPowerExpn->pDataPerChannel[ii].pDataPerXPD[jj];
+			pExpnXPD->numPcdacs = 4;
+			pExpnXPD->pcdac[1] = (uint16_t)
+				(pExpnXPD->pcdac[0] + pCalCh->pcd2_delta_xg0);
+			pExpnXPD->pcdac[2] = (uint16_t)
+				(pExpnXPD->pcdac[1] + pCalCh->pcd3_delta_xg0);
+			pExpnXPD->pcdac[3] = (uint16_t)
+				(pExpnXPD->pcdac[2] + pCalCh->pcd4_delta_xg0);
+			pExpnXPD->pwr_t4[0] = pCalCh->pwr1_xg0;
+			pExpnXPD->pwr_t4[1] = pCalCh->pwr2_xg0;
+			pExpnXPD->pwr_t4[2] = pCalCh->pwr3_xg0;
+			pExpnXPD->pwr_t4[3] = pCalCh->pwr4_xg0;
+
+			jj = xgainList[1];
+			pExpnXPD = &pPowerExpn->pDataPerChannel[ii].pDataPerXPD[jj];
+			pExpnXPD->numPcdacs = 3;
+
+			pExpnXPD->pwr_t4[0] = pCalCh->pwr1_xg3;
+			pExpnXPD->pwr_t4[1] = pCalCh->pwr2_xg3;
+			pExpnXPD->pwr_t4[2] = pCalCh->pwr3_xg3;
+		}
+	}
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+readEepromRawPowerCalInfo5112(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+#define	EEREAD(_off) do {				\
+	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
+		return AH_FALSE;			\
+} while (0)
+	const uint16_t dbmmask		 = 0xff;
+	const uint16_t pcdac_delta_mask = 0x1f;
+	const uint16_t pcdac_mask	 = 0x3f;
+	const uint16_t freqmask	 = 0xff;
+
+	int i, mode, numPiers;
+	uint32_t off;
+	uint16_t eeval;
+	uint16_t freq[NUM_11A_EEPROM_CHANNELS];
+        EEPROM_POWER_5112 eePower;
+
+	HALASSERT(ee->ee_version >= AR_EEPROM_VER4_0);
+	off = GROUPS_OFFSET3_3;
+	for (mode = headerInfo11A; mode <= headerInfo11G; mode++) {
+		numPiers = 0;
+		switch (mode) {
+		case headerInfo11A:
+			if (!ee->ee_Amode)	/* no 11a calibration data */
+				continue;
+			while (numPiers < NUM_11A_EEPROM_CHANNELS) {
+				EEREAD(off++);
+				if ((eeval & freqmask) == 0)
+					break;
+				freq[numPiers++] = fbin2freq(ee,
+					eeval & freqmask);
+
+				if (((eeval >> 8) & freqmask) == 0)
+					break;
+				freq[numPiers++] = fbin2freq(ee,
+					(eeval>>8) & freqmask);
+			}
+			break;
+		case headerInfo11B:
+			if (!ee->ee_Bmode)	/* no 11b calibration data */
+				continue;
+			for (i = 0; i < NUM_2_4_EEPROM_CHANNELS; i++)
+				if (ee->ee_calPier11b[i] != CHANNEL_UNUSED)
+					freq[numPiers++] = ee->ee_calPier11b[i];
+			break;
+		case headerInfo11G:
+			if (!ee->ee_Gmode)	/* no 11g calibration data */
+				continue;
+			for (i = 0; i < NUM_2_4_EEPROM_CHANNELS; i++)
+				if (ee->ee_calPier11g[i] != CHANNEL_UNUSED)
+					freq[numPiers++] = ee->ee_calPier11g[i];
+			break;
+		default:
+			HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",
+			    __func__, mode);
+			return AH_FALSE;
+		}
+
+		OS_MEMZERO(&eePower, sizeof(eePower));
+		eePower.numChannels = numPiers;
+
+		for (i = 0; i < numPiers; i++) {
+			eePower.pChannels[i] = freq[i];
+			eePower.pDataPerChannel[i].channelValue = freq[i];
+
+			EEREAD(off++);
+			eePower.pDataPerChannel[i].pwr1_xg0 = (int16_t)
+				((eeval & dbmmask) - ((eeval >> 7) & 0x1)*256);
+			eePower.pDataPerChannel[i].pwr2_xg0 = (int16_t)
+				(((eeval >> 8) & dbmmask) - ((eeval >> 15) & 0x1)*256);
+
+			EEREAD(off++);
+			eePower.pDataPerChannel[i].pwr3_xg0 = (int16_t)
+				((eeval & dbmmask) - ((eeval >> 7) & 0x1)*256);
+			eePower.pDataPerChannel[i].pwr4_xg0 = (int16_t)
+				(((eeval >> 8) & dbmmask) - ((eeval >> 15) & 0x1)*256);
+
+			EEREAD(off++);
+			eePower.pDataPerChannel[i].pcd2_delta_xg0 = (uint16_t)
+				(eeval & pcdac_delta_mask);
+			eePower.pDataPerChannel[i].pcd3_delta_xg0 = (uint16_t)
+				((eeval >> 5) & pcdac_delta_mask);
+			eePower.pDataPerChannel[i].pcd4_delta_xg0 = (uint16_t)
+				((eeval >> 10) & pcdac_delta_mask);
+
+			EEREAD(off++);
+			eePower.pDataPerChannel[i].pwr1_xg3 = (int16_t)
+				((eeval & dbmmask) - ((eeval >> 7) & 0x1)*256);
+			eePower.pDataPerChannel[i].pwr2_xg3 = (int16_t)
+				(((eeval >> 8) & dbmmask) - ((eeval >> 15) & 0x1)*256);
+
+			EEREAD(off++);
+			eePower.pDataPerChannel[i].pwr3_xg3 = (int16_t)
+				((eeval & dbmmask) - ((eeval >> 7) & 0x1)*256);
+			if (ee->ee_version >= AR_EEPROM_VER4_3) {
+				eePower.pDataPerChannel[i].maxPower_t4 =
+					eePower.pDataPerChannel[i].pwr4_xg0;     
+				eePower.pDataPerChannel[i].pcd1_xg0 = (uint16_t)
+					((eeval >> 8) & pcdac_mask);
+			} else {
+				eePower.pDataPerChannel[i].maxPower_t4 = (int16_t)
+					(((eeval >> 8) & dbmmask) -
+					 ((eeval >> 15) & 0x1)*256);
+				eePower.pDataPerChannel[i].pcd1_xg0 = 1;
+			}
+		}
+		eePower.xpdMask = ee->ee_xgain[mode];
+
+		if (!eepromAllocExpnPower5112(ah, &eePower, &ee->ee_modePowerArray5112[mode])) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: did not allocate power struct\n", __func__);
+			return AH_FALSE;
+                }
+                if (!eepromExpandPower5112(ah, &eePower, &ee->ee_modePowerArray5112[mode])) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: did not expand power struct\n", __func__);
+			return AH_FALSE;
+		}
+	}
+	return AH_TRUE;
+#undef EEREAD
+}
+
+static void
+freeEepromRawPowerCalInfo5112(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+	int mode;
+	void *data;
+
+	for (mode = headerInfo11A; mode <= headerInfo11G; mode++) {
+		EEPROM_POWER_EXPN_5112 *pPowerExpn =
+			&ee->ee_modePowerArray5112[mode];
+		data = pPowerExpn->pChannels;
+		if (data != AH_NULL) {
+			pPowerExpn->pChannels = AH_NULL;
+			ath_hal_free(data);
+		}
+	}
+}
+
+static void
+ar2413SetupEEPROMDataset(EEPROM_DATA_STRUCT_2413 *pEEPROMDataset2413,
+	uint16_t myNumRawChannels, uint16_t *pMyRawChanList)
+{
+	uint16_t i, channelValue;
+	uint32_t xpd_mask;
+	uint16_t numPdGainsUsed;
+
+	pEEPROMDataset2413->numChannels = myNumRawChannels;
+
+	xpd_mask = pEEPROMDataset2413->xpd_mask;
+	numPdGainsUsed = 0;
+	if ((xpd_mask >> 0) & 0x1) numPdGainsUsed++;
+	if ((xpd_mask >> 1) & 0x1) numPdGainsUsed++;
+	if ((xpd_mask >> 2) & 0x1) numPdGainsUsed++;
+	if ((xpd_mask >> 3) & 0x1) numPdGainsUsed++;
+
+	for (i = 0; i < myNumRawChannels; i++) {
+		channelValue = pMyRawChanList[i];
+		pEEPROMDataset2413->pChannels[i] = channelValue;
+		pEEPROMDataset2413->pDataPerChannel[i].channelValue = channelValue;
+		pEEPROMDataset2413->pDataPerChannel[i].numPdGains = numPdGainsUsed;
+	}
+}
+
+static HAL_BOOL
+ar2413ReadCalDataset(struct ath_hal *ah, HAL_EEPROM *ee,
+	EEPROM_DATA_STRUCT_2413 *pCalDataset,
+	uint32_t start_offset, uint32_t maxPiers, uint8_t mode)
+{
+#define	EEREAD(_off) do {				\
+	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
+		return AH_FALSE;			\
+} while (0)
+	const uint16_t dbm_I_mask = 0x1F;	/* 5-bits. 1dB step. */
+	const uint16_t dbm_delta_mask = 0xF;	/* 4-bits. 0.5dB step. */
+	const uint16_t Vpd_I_mask = 0x7F;	/* 7-bits. 0-128 */
+	const uint16_t Vpd_delta_mask = 0x3F;	/* 6-bits. 0-63 */
+	const uint16_t freqmask = 0xff;
+
+	uint16_t ii, eeval;
+	uint16_t idx, numPiers;
+	uint16_t freq[NUM_11A_EEPROM_CHANNELS];
+
+	idx = start_offset;
+    for (numPiers = 0; numPiers < maxPiers;) {
+        EEREAD(idx++);
+        if ((eeval & freqmask) == 0)
+            break;
+        if (mode == headerInfo11A)
+            freq[numPiers++] = fbin2freq(ee, (eeval & freqmask));
+        else
+            freq[numPiers++] = fbin2freq_2p4(ee, (eeval & freqmask));
+                                                                                          
+        if (((eeval >> 8) & freqmask) == 0)
+            break;
+        if (mode == headerInfo11A)
+            freq[numPiers++] = fbin2freq(ee, (eeval >> 8) & freqmask);
+        else
+            freq[numPiers++] = fbin2freq_2p4(ee, (eeval >> 8) & freqmask);
+    }
+	ar2413SetupEEPROMDataset(pCalDataset, numPiers, &freq[0]);
+
+	idx = start_offset + (maxPiers / 2);
+	for (ii = 0; ii < pCalDataset->numChannels; ii++) {
+		EEPROM_DATA_PER_CHANNEL_2413 *currCh =
+			&(pCalDataset->pDataPerChannel[ii]);
+
+		if (currCh->numPdGains > 0) {
+			/*
+			 * Read the first NUM_POINTS_OTHER_PDGAINS pwr
+			 * and Vpd values for pdgain_0
+			 */
+			EEREAD(idx++);
+			currCh->pwr_I[0] = eeval & dbm_I_mask;
+			currCh->Vpd_I[0] = (eeval >> 5) & Vpd_I_mask;
+			currCh->pwr_delta_t2[0][0] =
+				(eeval >> 12) & dbm_delta_mask;
+			
+			EEREAD(idx++);
+			currCh->Vpd_delta[0][0] = eeval & Vpd_delta_mask;
+			currCh->pwr_delta_t2[1][0] =
+				(eeval >> 6) & dbm_delta_mask;
+			currCh->Vpd_delta[1][0] =
+				(eeval >> 10) & Vpd_delta_mask;
+			
+			EEREAD(idx++);
+			currCh->pwr_delta_t2[2][0] = eeval & dbm_delta_mask;
+			currCh->Vpd_delta[2][0] = (eeval >> 4) & Vpd_delta_mask;
+		}
+		
+		if (currCh->numPdGains > 1) {
+			/*
+			 * Read the first NUM_POINTS_OTHER_PDGAINS pwr
+			 * and Vpd values for pdgain_1
+			 */
+			currCh->pwr_I[1] = (eeval >> 10) & dbm_I_mask;
+			currCh->Vpd_I[1] = (eeval >> 15) & 0x1;
+			
+			EEREAD(idx++);
+			/* upper 6 bits */
+			currCh->Vpd_I[1] |= (eeval & 0x3F) << 1;
+			currCh->pwr_delta_t2[0][1] =
+				(eeval >> 6) & dbm_delta_mask;
+			currCh->Vpd_delta[0][1] =
+				(eeval >> 10) & Vpd_delta_mask;
+			
+			EEREAD(idx++);
+			currCh->pwr_delta_t2[1][1] = eeval & dbm_delta_mask;
+			currCh->Vpd_delta[1][1] = (eeval >> 4) & Vpd_delta_mask;
+			currCh->pwr_delta_t2[2][1] =
+				(eeval >> 10) & dbm_delta_mask;
+			currCh->Vpd_delta[2][1] = (eeval >> 14) & 0x3;
+			
+			EEREAD(idx++);
+			/* upper 4 bits */
+			currCh->Vpd_delta[2][1] |= (eeval & 0xF) << 2;
+		} else if (currCh->numPdGains == 1) {
+			/*
+			 * Read the last pwr and Vpd values for pdgain_0
+			 */
+			currCh->pwr_delta_t2[3][0] =
+				(eeval >> 10) & dbm_delta_mask;
+			currCh->Vpd_delta[3][0] = (eeval >> 14) & 0x3;
+
+			EEREAD(idx++);
+			/* upper 4 bits */
+			currCh->Vpd_delta[3][0] |= (eeval & 0xF) << 2;
+
+			/* 4 words if numPdGains == 1 */
+		}
+
+		if (currCh->numPdGains > 2) {
+			/*
+			 * Read the first NUM_POINTS_OTHER_PDGAINS pwr
+			 * and Vpd values for pdgain_2
+			 */
+			currCh->pwr_I[2] = (eeval >> 4) & dbm_I_mask;
+			currCh->Vpd_I[2] = (eeval >> 9) & Vpd_I_mask;
+			
+			EEREAD(idx++);
+			currCh->pwr_delta_t2[0][2] =
+				(eeval >> 0) & dbm_delta_mask;
+			currCh->Vpd_delta[0][2] = (eeval >> 4) & Vpd_delta_mask;
+			currCh->pwr_delta_t2[1][2] =
+				(eeval >> 10) & dbm_delta_mask;
+			currCh->Vpd_delta[1][2] = (eeval >> 14) & 0x3;
+			
+			EEREAD(idx++);
+			/* upper 4 bits */
+			currCh->Vpd_delta[1][2] |= (eeval & 0xF) << 2;
+			currCh->pwr_delta_t2[2][2] =
+				(eeval >> 4) & dbm_delta_mask;
+			currCh->Vpd_delta[2][2] = (eeval >> 8) & Vpd_delta_mask;
+		} else if (currCh->numPdGains == 2) {
+			/*
+			 * Read the last pwr and Vpd values for pdgain_1
+			 */
+			currCh->pwr_delta_t2[3][1] =
+				(eeval >> 4) & dbm_delta_mask;
+			currCh->Vpd_delta[3][1] = (eeval >> 8) & Vpd_delta_mask;
+
+			/* 6 words if numPdGains == 2 */
+		}
+
+		if (currCh->numPdGains > 3) {
+			/*
+			 * Read the first NUM_POINTS_OTHER_PDGAINS pwr
+			 * and Vpd values for pdgain_3
+			 */
+			currCh->pwr_I[3] = (eeval >> 14) & 0x3;
+			
+			EEREAD(idx++);
+			/* upper 3 bits */
+			currCh->pwr_I[3] |= ((eeval >> 0) & 0x7) << 2;
+			currCh->Vpd_I[3] = (eeval >> 3) & Vpd_I_mask;
+			currCh->pwr_delta_t2[0][3] =
+				(eeval >> 10) & dbm_delta_mask;
+			currCh->Vpd_delta[0][3] = (eeval >> 14) & 0x3;
+			
+			EEREAD(idx++);
+			/* upper 4 bits */
+			currCh->Vpd_delta[0][3] |= (eeval & 0xF) << 2;
+			currCh->pwr_delta_t2[1][3] =
+				(eeval >> 4) & dbm_delta_mask;
+			currCh->Vpd_delta[1][3] = (eeval >> 8) & Vpd_delta_mask;
+			currCh->pwr_delta_t2[2][3] = (eeval >> 14) & 0x3;
+			
+			EEREAD(idx++);
+			/* upper 2 bits */
+			currCh->pwr_delta_t2[2][3] |= ((eeval >> 0) & 0x3) << 2;
+			currCh->Vpd_delta[2][3] = (eeval >> 2) & Vpd_delta_mask;
+			currCh->pwr_delta_t2[3][3] =
+				(eeval >> 8) & dbm_delta_mask;
+			currCh->Vpd_delta[3][3] = (eeval >> 12) & 0xF;
+			
+			EEREAD(idx++);
+			/* upper 2 bits */
+			currCh->Vpd_delta[3][3] |= ((eeval >> 0) & 0x3) << 4;
+
+			/* 12 words if numPdGains == 4 */
+		} else if (currCh->numPdGains == 3) {
+			/* read the last pwr and Vpd values for pdgain_2 */
+			currCh->pwr_delta_t2[3][2] = (eeval >> 14) & 0x3;
+			
+			EEREAD(idx++);
+			/* upper 2 bits */
+			currCh->pwr_delta_t2[3][2] |= ((eeval >> 0) & 0x3) << 2;
+			currCh->Vpd_delta[3][2] = (eeval >> 2) & Vpd_delta_mask;
+
+			/* 9 words if numPdGains == 3 */
+		}
+	}
+	return AH_TRUE;
+#undef EEREAD
+}
+
+static void
+ar2413SetupRawDataset(RAW_DATA_STRUCT_2413 *pRaw, EEPROM_DATA_STRUCT_2413 *pCal)
+{
+	uint16_t i, j, kk, channelValue;
+	uint16_t xpd_mask;
+	uint16_t numPdGainsUsed;
+
+	pRaw->numChannels = pCal->numChannels;
+
+	xpd_mask = pRaw->xpd_mask;
+	numPdGainsUsed = 0;
+	if ((xpd_mask >> 0) & 0x1) numPdGainsUsed++;
+	if ((xpd_mask >> 1) & 0x1) numPdGainsUsed++;
+	if ((xpd_mask >> 2) & 0x1) numPdGainsUsed++;
+	if ((xpd_mask >> 3) & 0x1) numPdGainsUsed++;
+
+	for (i = 0; i < pCal->numChannels; i++) {
+		channelValue = pCal->pChannels[i];
+
+		pRaw->pChannels[i] = channelValue;
+
+		pRaw->pDataPerChannel[i].channelValue = channelValue;
+		pRaw->pDataPerChannel[i].numPdGains = numPdGainsUsed;
+
+		kk = 0;
+		for (j = 0; j < MAX_NUM_PDGAINS_PER_CHANNEL; j++) {
+			pRaw->pDataPerChannel[i].pDataPerPDGain[j].pd_gain = j;
+			if ((xpd_mask >> j) & 0x1) {
+				pRaw->pDataPerChannel[i].pDataPerPDGain[j].numVpd = NUM_POINTS_OTHER_PDGAINS;
+				kk++;
+				if (kk == 1) {
+					/* 
+					 * lowest pd_gain corresponds
+					 *  to highest power and thus,
+					 *  has one more point
+					 */
+					pRaw->pDataPerChannel[i].pDataPerPDGain[j].numVpd = NUM_POINTS_LAST_PDGAIN;
+				}
+			} else {
+				pRaw->pDataPerChannel[i].pDataPerPDGain[j].numVpd = 0;
+			}
+		}
+	}
+}
+
+static HAL_BOOL
+ar2413EepromToRawDataset(struct ath_hal *ah,
+	EEPROM_DATA_STRUCT_2413 *pCal, RAW_DATA_STRUCT_2413 *pRaw)
+{
+	uint16_t ii, jj, kk, ss;
+	RAW_DATA_PER_PDGAIN_2413 *pRawXPD;
+	/* ptr to array of info held per channel */
+	EEPROM_DATA_PER_CHANNEL_2413 *pCalCh;
+	uint16_t xgain_list[MAX_NUM_PDGAINS_PER_CHANNEL];
+	uint16_t xpd_mask;
+	uint32_t numPdGainsUsed;
+
+	HALASSERT(pRaw->xpd_mask == pCal->xpd_mask);
+
+	xgain_list[0] = 0xDEAD;
+	xgain_list[1] = 0xDEAD;
+	xgain_list[2] = 0xDEAD;
+	xgain_list[3] = 0xDEAD;
+
+	numPdGainsUsed = 0;
+	xpd_mask = pRaw->xpd_mask;
+	for (jj = 0; jj < MAX_NUM_PDGAINS_PER_CHANNEL; jj++) {
+		if ((xpd_mask >> (MAX_NUM_PDGAINS_PER_CHANNEL-jj-1)) & 1)
+			xgain_list[numPdGainsUsed++] = MAX_NUM_PDGAINS_PER_CHANNEL-jj-1;
+	}
+
+	pRaw->numChannels = pCal->numChannels;
+	for (ii = 0; ii < pRaw->numChannels; ii++) {
+		pCalCh = &(pCal->pDataPerChannel[ii]);
+		pRaw->pDataPerChannel[ii].channelValue = pCalCh->channelValue;
+
+		/* numVpd has already been setup appropriately for the relevant pdGains */
+		for (jj = 0; jj < numPdGainsUsed; jj++) {
+			/* use jj for calDataset and ss for rawDataset */
+			ss = xgain_list[jj];
+			pRawXPD = &(pRaw->pDataPerChannel[ii].pDataPerPDGain[ss]);
+			HALASSERT(pRawXPD->numVpd >= 1);
+
+			pRawXPD->pwr_t4[0] = (uint16_t)(4*pCalCh->pwr_I[jj]);
+			pRawXPD->Vpd[0]    = pCalCh->Vpd_I[jj];
+
+			for (kk = 1; kk < pRawXPD->numVpd; kk++) {
+				pRawXPD->pwr_t4[kk] = (int16_t)(pRawXPD->pwr_t4[kk-1] + 2*pCalCh->pwr_delta_t2[kk-1][jj]);
+				pRawXPD->Vpd[kk] = (uint16_t)(pRawXPD->Vpd[kk-1] + pCalCh->Vpd_delta[kk-1][jj]);
+			}
+			/* loop over Vpds */
+		}
+		/* loop over pd_gains */
+	}
+	/* loop over channels */
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+readEepromRawPowerCalInfo2413(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+	/* NB: index is 1 less than numPdgains */
+	static const uint16_t wordsForPdgains[] = { 4, 6, 9, 12 };
+	EEPROM_DATA_STRUCT_2413 *pCal = AH_NULL;
+	RAW_DATA_STRUCT_2413 *pRaw;
+	int numEEPROMWordsPerChannel;
+	uint32_t off;
+	HAL_BOOL ret = AH_FALSE;
+	
+	HALASSERT(ee->ee_version >= AR_EEPROM_VER5_0);
+	HALASSERT(ee->ee_eepMap == 2);
+	
+	pCal = ath_hal_malloc(sizeof(EEPROM_DATA_STRUCT_2413));
+	if (pCal == AH_NULL)
+		goto exit;
+	
+	off = ee->ee_eepMap2PowerCalStart;
+	if (ee->ee_Amode) {
+		OS_MEMZERO(pCal, sizeof(EEPROM_DATA_STRUCT_2413));
+		pCal->xpd_mask = ee->ee_xgain[headerInfo11A];
+		if (!ar2413ReadCalDataset(ah, ee, pCal, off,
+			NUM_11A_EEPROM_CHANNELS_2413, headerInfo11A)) {
+			goto exit;
+		}
+		pRaw = &ee->ee_rawDataset2413[headerInfo11A];
+		pRaw->xpd_mask = ee->ee_xgain[headerInfo11A];
+		ar2413SetupRawDataset(pRaw, pCal);
+		if (!ar2413EepromToRawDataset(ah, pCal, pRaw)) {
+			goto exit;
+		}
+		/* setup offsets for mode_11a next */
+		numEEPROMWordsPerChannel = wordsForPdgains[
+			pCal->pDataPerChannel[0].numPdGains - 1];
+		off += pCal->numChannels * numEEPROMWordsPerChannel + 5;
+	}
+	if (ee->ee_Bmode) {
+		OS_MEMZERO(pCal, sizeof(EEPROM_DATA_STRUCT_2413));
+		pCal->xpd_mask = ee->ee_xgain[headerInfo11B];
+		if (!ar2413ReadCalDataset(ah, ee, pCal, off,
+			NUM_2_4_EEPROM_CHANNELS_2413 , headerInfo11B)) {
+			goto exit;
+		}
+		pRaw = &ee->ee_rawDataset2413[headerInfo11B];
+		pRaw->xpd_mask = ee->ee_xgain[headerInfo11B];
+		ar2413SetupRawDataset(pRaw, pCal);
+		if (!ar2413EepromToRawDataset(ah, pCal, pRaw)) {
+			goto exit;
+		}
+		/* setup offsets for mode_11g next */
+		numEEPROMWordsPerChannel = wordsForPdgains[
+			pCal->pDataPerChannel[0].numPdGains - 1];
+		off += pCal->numChannels * numEEPROMWordsPerChannel + 2;
+	}
+	if (ee->ee_Gmode) {
+		OS_MEMZERO(pCal, sizeof(EEPROM_DATA_STRUCT_2413));
+		pCal->xpd_mask = ee->ee_xgain[headerInfo11G];
+		if (!ar2413ReadCalDataset(ah, ee, pCal, off,
+			NUM_2_4_EEPROM_CHANNELS_2413, headerInfo11G)) {
+			goto exit;
+		}
+		pRaw = &ee->ee_rawDataset2413[headerInfo11G];
+		pRaw->xpd_mask = ee->ee_xgain[headerInfo11G];
+		ar2413SetupRawDataset(pRaw, pCal);
+		if (!ar2413EepromToRawDataset(ah, pCal, pRaw)) {
+			goto exit;
+		}
+	}
+	ret = AH_TRUE;
+ exit:
+	if (pCal != AH_NULL)
+		ath_hal_free(pCal);
+	return ret;
+}
+
+/*
+ * Now copy EEPROM Raw Power Calibration per frequency contents 
+ * into the allocated space
+ */
+static HAL_BOOL
+readEepromRawPowerCalInfo(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+#define	EEREAD(_off) do {				\
+	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
+		return AH_FALSE;			\
+} while (0)
+	uint16_t eeval, nchan;
+	uint32_t off;
+	int i, j, mode;
+
+        if (ee->ee_version >= AR_EEPROM_VER4_0 && ee->ee_eepMap == 1)
+		return readEepromRawPowerCalInfo5112(ah, ee);
+	if (ee->ee_version >= AR_EEPROM_VER5_0 && ee->ee_eepMap == 2)
+		return readEepromRawPowerCalInfo2413(ah, ee);
+
+	/*
+	 * Group 2:  read raw power data for all frequency piers
+	 *
+	 * NOTE: Group 2 contains the raw power calibration
+	 *	 information for each of the channels that
+	 *	 we recorded above.
+	 */
+	for (mode = headerInfo11A; mode <= headerInfo11G; mode++) {
+		uint16_t *pChannels = AH_NULL;
+		DATA_PER_CHANNEL *pChannelData = AH_NULL;
+
+		off = ee->ee_version >= AR_EEPROM_VER3_3 ? 
+			GROUPS_OFFSET3_3 : GROUPS_OFFSET3_2;
+		switch (mode) {
+		case headerInfo11A:
+			off      	+= GROUP2_OFFSET;
+			nchan		= ee->ee_numChannels11a;
+			pChannelData	= ee->ee_dataPerChannel11a;
+			pChannels	= ee->ee_channels11a;
+			break;
+		case headerInfo11B:
+			if (!ee->ee_Bmode)
+				continue;
+			off		+= GROUP3_OFFSET;
+			nchan		= ee->ee_numChannels2_4;
+			pChannelData	= ee->ee_dataPerChannel11b;
+			pChannels	= ee->ee_channels11b;
+			break;
+		case headerInfo11G:
+			if (!ee->ee_Gmode)
+				continue;
+			off		+= GROUP4_OFFSET;
+			nchan		= ee->ee_numChannels2_4;
+			pChannelData	= ee->ee_dataPerChannel11g;
+			pChannels	= ee->ee_channels11g;
+			break;
+		default:
+			HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",
+			    __func__, mode);
+			return AH_FALSE;
+		}
+		for (i = 0; i < nchan; i++) {
+			pChannelData->channelValue = pChannels[i];
+
+			EEREAD(off++);
+			pChannelData->pcdacMax     = (uint16_t)((eeval >> 10) & PCDAC_MASK);
+			pChannelData->pcdacMin     = (uint16_t)((eeval >> 4) & PCDAC_MASK);
+			pChannelData->PwrValues[0] = (uint16_t)((eeval << 2) & POWER_MASK);
+
+			EEREAD(off++);
+			pChannelData->PwrValues[0] |= (uint16_t)((eeval >> 14) & 0x3);
+			pChannelData->PwrValues[1] = (uint16_t)((eeval >> 8) & POWER_MASK);
+			pChannelData->PwrValues[2] = (uint16_t)((eeval >> 2) & POWER_MASK);
+			pChannelData->PwrValues[3] = (uint16_t)((eeval << 4) & POWER_MASK);
+
+			EEREAD(off++);
+			pChannelData->PwrValues[3] |= (uint16_t)((eeval >> 12) & 0xf);
+			pChannelData->PwrValues[4] = (uint16_t)((eeval >> 6) & POWER_MASK);
+			pChannelData->PwrValues[5] = (uint16_t)(eeval  & POWER_MASK);
+
+			EEREAD(off++);
+			pChannelData->PwrValues[6] = (uint16_t)((eeval >> 10) & POWER_MASK);
+			pChannelData->PwrValues[7] = (uint16_t)((eeval >> 4) & POWER_MASK);
+			pChannelData->PwrValues[8] = (uint16_t)((eeval << 2) & POWER_MASK);
+
+			EEREAD(off++);
+			pChannelData->PwrValues[8] |= (uint16_t)((eeval >> 14) & 0x3);
+			pChannelData->PwrValues[9] = (uint16_t)((eeval >> 8) & POWER_MASK);
+			pChannelData->PwrValues[10] = (uint16_t)((eeval >> 2) & POWER_MASK);
+
+			getPcdacInterceptsFromPcdacMinMax(ee,
+				pChannelData->pcdacMin, pChannelData->pcdacMax,
+				pChannelData->PcdacValues) ;
+
+			for (j = 0; j < pChannelData->numPcdacValues; j++) {
+				pChannelData->PwrValues[j] = (uint16_t)(
+					PWR_STEP * pChannelData->PwrValues[j]);
+				/* Note these values are scaled up. */
+			}
+			pChannelData++;
+		}
+	}
+	return AH_TRUE;
+#undef EEREAD
+}
+
+/*
+ * Copy EEPROM Target Power Calbration per rate contents 
+ * into the allocated space
+ */
+static HAL_BOOL
+readEepromTargetPowerCalInfo(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+#define	EEREAD(_off) do {				\
+	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
+		return AH_FALSE;			\
+} while (0)
+	uint16_t eeval, enable24;
+	uint32_t off;
+	int i, mode, nchan;
+
+	enable24 = ee->ee_Bmode || ee->ee_Gmode;
+	for (mode = headerInfo11A; mode <= headerInfo11G; mode++) {
+		TRGT_POWER_INFO *pPowerInfo;
+		uint16_t *pNumTrgtChannels;
+
+		off = ee->ee_version >= AR_EEPROM_VER4_0 ?
+				ee->ee_targetPowersStart - GROUP5_OFFSET :
+		      ee->ee_version >= AR_EEPROM_VER3_3 ?
+				GROUPS_OFFSET3_3 : GROUPS_OFFSET3_2;
+		switch (mode) {
+		case headerInfo11A:
+			off += GROUP5_OFFSET;
+			nchan = NUM_TEST_FREQUENCIES;
+			pPowerInfo = ee->ee_trgtPwr_11a;
+			pNumTrgtChannels = &ee->ee_numTargetPwr_11a;
+			break;
+		case headerInfo11B:
+			if (!enable24)
+				continue;
+			off += GROUP6_OFFSET;
+			nchan = 2;
+			pPowerInfo = ee->ee_trgtPwr_11b;
+			pNumTrgtChannels = &ee->ee_numTargetPwr_11b;
+			break;
+		case headerInfo11G:
+			if (!enable24)
+				continue;
+			off += GROUP7_OFFSET;
+			nchan = 3;
+			pPowerInfo = ee->ee_trgtPwr_11g;
+			pNumTrgtChannels = &ee->ee_numTargetPwr_11g;
+			break;
+		default:
+			HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",
+			    __func__, mode);
+			return AH_FALSE;
+		}
+		*pNumTrgtChannels = 0;
+		for (i = 0; i < nchan; i++) {
+			EEREAD(off++);
+			if (ee->ee_version >= AR_EEPROM_VER3_3) {
+				pPowerInfo->testChannel = (eeval >> 8) & 0xff;
+			} else {
+				pPowerInfo->testChannel = (eeval >> 9) & 0x7f;
+			}
+
+			if (pPowerInfo->testChannel != 0) {
+				/* get the channel value and read rest of info */
+				if (mode == headerInfo11A) {
+					pPowerInfo->testChannel = fbin2freq(ee, pPowerInfo->testChannel);
+				} else {
+					pPowerInfo->testChannel = fbin2freq_2p4(ee, pPowerInfo->testChannel);
+				}
+
+				if (ee->ee_version >= AR_EEPROM_VER3_3) {
+					pPowerInfo->twicePwr6_24 = (eeval >> 2) & POWER_MASK;
+					pPowerInfo->twicePwr36   = (eeval << 4) & POWER_MASK;
+				} else {
+					pPowerInfo->twicePwr6_24 = (eeval >> 3) & POWER_MASK;
+					pPowerInfo->twicePwr36   = (eeval << 3) & POWER_MASK;
+				}
+
+				EEREAD(off++);
+				if (ee->ee_version >= AR_EEPROM_VER3_3) {
+					pPowerInfo->twicePwr36 |= (eeval >> 12) & 0xf;
+					pPowerInfo->twicePwr48 = (eeval >> 6) & POWER_MASK;
+					pPowerInfo->twicePwr54 =  eeval & POWER_MASK;
+				} else {
+					pPowerInfo->twicePwr36 |= (eeval >> 13) & 0x7;
+					pPowerInfo->twicePwr48 = (eeval >> 7) & POWER_MASK;
+					pPowerInfo->twicePwr54 = (eeval >> 1) & POWER_MASK;
+				}
+				(*pNumTrgtChannels)++;
+			}
+			pPowerInfo++;
+		}
+	}
+	return AH_TRUE;
+#undef EEREAD
+}
+
+/*
+ * Now copy EEPROM Coformance Testing Limits contents 
+ * into the allocated space
+ */
+static HAL_BOOL
+readEepromCTLInfo(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+#define	EEREAD(_off) do {				\
+	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
+		return AH_FALSE;			\
+} while (0)
+	RD_EDGES_POWER *rep;
+	uint16_t eeval;
+	uint32_t off;
+	int i, j;
+
+	rep = ee->ee_rdEdgesPower;
+
+	off = GROUP8_OFFSET +
+		(ee->ee_version >= AR_EEPROM_VER4_0 ?
+			ee->ee_targetPowersStart - GROUP5_OFFSET :
+	         ee->ee_version >= AR_EEPROM_VER3_3 ?
+			GROUPS_OFFSET3_3 : GROUPS_OFFSET3_2);
+	for (i = 0; i < ee->ee_numCtls; i++) {
+		if (ee->ee_ctl[i] == 0) {
+			/* Move offset and edges */
+			off += (ee->ee_version >= AR_EEPROM_VER3_3 ? 8 : 7);
+			rep += NUM_EDGES;
+			continue;
+		}
+		if (ee->ee_version >= AR_EEPROM_VER3_3) {
+			for (j = 0; j < NUM_EDGES; j += 2) {
+				EEREAD(off++);
+				rep[j].rdEdge = (eeval >> 8) & FREQ_MASK_3_3;
+				rep[j+1].rdEdge = eeval & FREQ_MASK_3_3;
+			}
+			for (j = 0; j < NUM_EDGES; j += 2) {
+				EEREAD(off++);
+				rep[j].twice_rdEdgePower = 
+					(eeval >> 8) & POWER_MASK;
+				rep[j].flag = (eeval >> 14) & 1;
+				rep[j+1].twice_rdEdgePower = eeval & POWER_MASK;
+				rep[j+1].flag = (eeval >> 6) & 1;
+			}
+		} else { 
+			EEREAD(off++);
+			rep[0].rdEdge = (eeval >> 9) & FREQ_MASK;
+			rep[1].rdEdge = (eeval >> 2) & FREQ_MASK;
+			rep[2].rdEdge = (eeval << 5) & FREQ_MASK;
+
+			EEREAD(off++);
+			rep[2].rdEdge |= (eeval >> 11) & 0x1f;
+			rep[3].rdEdge = (eeval >> 4) & FREQ_MASK;
+			rep[4].rdEdge = (eeval << 3) & FREQ_MASK;
+
+			EEREAD(off++);
+			rep[4].rdEdge |= (eeval >> 13) & 0x7;
+			rep[5].rdEdge = (eeval >> 6) & FREQ_MASK;
+			rep[6].rdEdge = (eeval << 1) & FREQ_MASK;
+
+			EEREAD(off++);
+			rep[6].rdEdge |= (eeval >> 15) & 0x1;
+			rep[7].rdEdge = (eeval >> 8) & FREQ_MASK;
+
+			rep[0].twice_rdEdgePower = (eeval >> 2) & POWER_MASK;
+			rep[1].twice_rdEdgePower = (eeval << 4) & POWER_MASK;
+
+			EEREAD(off++);
+			rep[1].twice_rdEdgePower |= (eeval >> 12) & 0xf;
+			rep[2].twice_rdEdgePower = (eeval >> 6) & POWER_MASK;
+			rep[3].twice_rdEdgePower = eeval & POWER_MASK;
+
+			EEREAD(off++);
+			rep[4].twice_rdEdgePower = (eeval >> 10) & POWER_MASK;
+			rep[5].twice_rdEdgePower = (eeval >> 4) & POWER_MASK;
+			rep[6].twice_rdEdgePower = (eeval << 2) & POWER_MASK;
+
+			EEREAD(off++);
+			rep[6].twice_rdEdgePower |= (eeval >> 14) & 0x3;
+			rep[7].twice_rdEdgePower = (eeval >> 8) & POWER_MASK;
+		}
+
+		for (j = 0; j < NUM_EDGES; j++ ) {
+			if (rep[j].rdEdge != 0 || rep[j].twice_rdEdgePower != 0) {
+				if ((ee->ee_ctl[i] & CTL_MODE_M) == CTL_11A ||
+				    (ee->ee_ctl[i] & CTL_MODE_M) == CTL_TURBO) {
+					rep[j].rdEdge = fbin2freq(ee, rep[j].rdEdge);
+				} else {
+					rep[j].rdEdge = fbin2freq_2p4(ee, rep[j].rdEdge);
+				}
+			}
+		}
+		rep += NUM_EDGES;
+	}
+	return AH_TRUE;
+#undef EEREAD
+}
+
+/*
+ * Read the individual header fields for a Rev 3 EEPROM
+ */
+static HAL_BOOL
+readHeaderInfo(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+#define	EEREAD(_off) do {				\
+	if (!ath_hal_eepromRead(ah, _off, &eeval))	\
+		return AH_FALSE;			\
+} while (0)
+	static const uint32_t headerOffset3_0[] = {
+		0x00C2, /* 0 - Mode bits, device type, max turbo power */
+		0x00C4, /* 1 - 2.4 and 5 antenna gain */
+		0x00C5, /* 2 - Begin 11A modal section */
+		0x00D0, /* 3 - Begin 11B modal section */
+		0x00DA, /* 4 - Begin 11G modal section */
+		0x00E4  /* 5 - Begin CTL section */
+	};
+	static const uint32_t headerOffset3_3[] = {
+		0x00C2, /* 0 - Mode bits, device type, max turbo power */
+		0x00C3, /* 1 - 2.4 and 5 antenna gain */
+		0x00D4, /* 2 - Begin 11A modal section */
+		0x00F2, /* 3 - Begin 11B modal section */
+		0x010D, /* 4 - Begin 11G modal section */
+		0x0128  /* 5 - Begin CTL section */
+	};
+
+	static const uint32_t regCapOffsetPre4_0 = 0x00CF;
+	static const uint32_t regCapOffsetPost4_0 = 0x00CA; 
+
+	const uint32_t *header;
+	uint32_t off;
+	uint16_t eeval;
+	int i;
+
+	/* initialize cckOfdmGainDelta for < 4.2 eeprom */
+	ee->ee_cckOfdmGainDelta = CCK_OFDM_GAIN_DELTA;
+	ee->ee_scaledCh14FilterCckDelta = TENX_CH14_FILTER_CCK_DELTA_INIT;
+
+	if (ee->ee_version >= AR_EEPROM_VER3_3) {
+		header = headerOffset3_3;
+		ee->ee_numCtls = NUM_CTLS_3_3;
+	} else {
+		header = headerOffset3_0;
+		ee->ee_numCtls = NUM_CTLS;
+	}
+	HALASSERT(ee->ee_numCtls <= NUM_CTLS_MAX);
+
+	EEREAD(header[0]);
+	ee->ee_turbo5Disable	= (eeval >> 15) & 0x01;
+	ee->ee_rfKill		= (eeval >> 14) & 0x01;
+	ee->ee_deviceType	= (eeval >> 11) & 0x07;
+	ee->ee_turbo2WMaxPower5	= (eeval >> 4) & 0x7F;
+	if (ee->ee_version >= AR_EEPROM_VER4_0)
+		ee->ee_turbo2Disable	= (eeval >> 3) & 0x01;
+	else
+		ee->ee_turbo2Disable	= 1;
+	ee->ee_Gmode		= (eeval >> 2) & 0x01;
+	ee->ee_Bmode		= (eeval >> 1) & 0x01;
+	ee->ee_Amode		= (eeval & 0x01);
+
+	off = header[1];
+	EEREAD(off++);
+	ee->ee_antennaGainMax[0] = (int8_t)((eeval >> 8) & 0xFF);
+	ee->ee_antennaGainMax[1] = (int8_t)(eeval & 0xFF);
+	if (ee->ee_version >= AR_EEPROM_VER4_0) {
+		EEREAD(off++);
+		ee->ee_eepMap		 = (eeval>>14) & 0x3;
+		ee->ee_disableXr5	 = (eeval>>13) & 0x1;
+		ee->ee_disableXr2	 = (eeval>>12) & 0x1;
+		ee->ee_earStart		 = eeval & 0xfff;
+
+		EEREAD(off++);
+		ee->ee_targetPowersStart = eeval & 0xfff;
+		ee->ee_exist32kHzCrystal = (eeval>>14) & 0x1;
+
+		if (ee->ee_version >= AR_EEPROM_VER5_0) {
+			off += 2;
+			EEREAD(off);
+			ee->ee_eepMap2PowerCalStart = (eeval >> 4) & 0xfff;
+			/* Properly cal'ed 5.0 devices should be non-zero */
+		}
+	}
+
+	/* Read the moded sections of the EEPROM header in the order A, B, G */
+	for (i = headerInfo11A; i <= headerInfo11G; i++) {
+		/* Set the offset via the index */
+		off = header[2 + i];
+
+		EEREAD(off++);
+		ee->ee_switchSettling[i] = (eeval >> 8) & 0x7f;
+		ee->ee_txrxAtten[i] = (eeval >> 2) & 0x3f;
+		ee->ee_antennaControl[0][i] = (eeval << 4) & 0x3f;
+
+		EEREAD(off++);
+		ee->ee_antennaControl[0][i] |= (eeval >> 12) & 0x0f;
+		ee->ee_antennaControl[1][i] = (eeval >> 6) & 0x3f;
+		ee->ee_antennaControl[2][i] = eeval & 0x3f;
+
+		EEREAD(off++);
+		ee->ee_antennaControl[3][i] = (eeval >> 10)  & 0x3f;
+		ee->ee_antennaControl[4][i] = (eeval >> 4)  & 0x3f;
+		ee->ee_antennaControl[5][i] = (eeval << 2)  & 0x3f;
+
+		EEREAD(off++);
+		ee->ee_antennaControl[5][i] |= (eeval >> 14)  & 0x03;
+		ee->ee_antennaControl[6][i] = (eeval >> 8)  & 0x3f;
+		ee->ee_antennaControl[7][i] = (eeval >> 2)  & 0x3f;
+		ee->ee_antennaControl[8][i] = (eeval << 4)  & 0x3f;
+
+		EEREAD(off++);
+		ee->ee_antennaControl[8][i] |= (eeval >> 12)  & 0x0f;
+		ee->ee_antennaControl[9][i] = (eeval >> 6)  & 0x3f;
+		ee->ee_antennaControl[10][i] = eeval & 0x3f;
+
+		EEREAD(off++);
+		ee->ee_adcDesiredSize[i] = (int8_t)((eeval >> 8)  & 0xff);
+		switch (i) {
+		case headerInfo11A:
+			ee->ee_ob4 = (eeval >> 5)  & 0x07;
+			ee->ee_db4 = (eeval >> 2)  & 0x07;
+			ee->ee_ob3 = (eeval << 1)  & 0x07;
+			break;
+		case headerInfo11B:
+			ee->ee_obFor24 = (eeval >> 4)  & 0x07;
+			ee->ee_dbFor24 = eeval & 0x07;
+			break;
+		case headerInfo11G:
+			ee->ee_obFor24g = (eeval >> 4)  & 0x07;
+			ee->ee_dbFor24g = eeval & 0x07;
+			break;
+		}
+
+		if (i == headerInfo11A) {
+			EEREAD(off++);
+			ee->ee_ob3 |= (eeval >> 15)  & 0x01;
+			ee->ee_db3 = (eeval >> 12)  & 0x07;
+			ee->ee_ob2 = (eeval >> 9)  & 0x07;
+			ee->ee_db2 = (eeval >> 6)  & 0x07;
+			ee->ee_ob1 = (eeval >> 3)  & 0x07;
+			ee->ee_db1 = eeval & 0x07;
+		}
+
+		EEREAD(off++);
+		ee->ee_txEndToXLNAOn[i] = (eeval >> 8)  & 0xff;
+		ee->ee_thresh62[i] = eeval & 0xff;
+
+		EEREAD(off++);
+		ee->ee_txEndToXPAOff[i] = (eeval >> 8)  & 0xff;
+		ee->ee_txFrameToXPAOn[i] = eeval  & 0xff;
+
+		EEREAD(off++);
+		ee->ee_pgaDesiredSize[i] = (int8_t)((eeval >> 8)  & 0xff);
+		ee->ee_noiseFloorThresh[i] = eeval  & 0xff;
+		if (ee->ee_noiseFloorThresh[i] & 0x80) {
+			ee->ee_noiseFloorThresh[i] = 0 -
+				((ee->ee_noiseFloorThresh[i] ^ 0xff) + 1);
+		}
+
+		EEREAD(off++);
+		ee->ee_xlnaGain[i] = (eeval >> 5)  & 0xff;
+		ee->ee_xgain[i] = (eeval >> 1)  & 0x0f;
+		ee->ee_xpd[i] = eeval  & 0x01;
+		if (ee->ee_version >= AR_EEPROM_VER4_0) {
+			switch (i) {
+			case headerInfo11A:
+				ee->ee_fixedBias5 = (eeval >> 13) & 0x1;
+				break;
+			case headerInfo11G:
+				ee->ee_fixedBias2 = (eeval >> 13) & 0x1;
+				break;
+			}
+		}
+
+		if (ee->ee_version >= AR_EEPROM_VER3_3) {
+			EEREAD(off++);
+			ee->ee_falseDetectBackoff[i] = (eeval >> 6) & 0x7F;
+			switch (i) {
+			case headerInfo11B:
+				ee->ee_ob2GHz[0] = eeval & 0x7;
+				ee->ee_db2GHz[0] = (eeval >> 3) & 0x7;
+				break;
+			case headerInfo11G:
+				ee->ee_ob2GHz[1] = eeval & 0x7;
+				ee->ee_db2GHz[1] = (eeval >> 3) & 0x7;
+				break;
+			case headerInfo11A:
+				ee->ee_xrTargetPower5 = eeval & 0x3f;
+				break;
+			}
+		}
+		if (ee->ee_version >= AR_EEPROM_VER3_4) {
+			ee->ee_gainI[i] = (eeval >> 13) & 0x07;
+
+			EEREAD(off++);
+			ee->ee_gainI[i] |= (eeval << 3) & 0x38;
+			if (i == headerInfo11G) {
+				ee->ee_cckOfdmPwrDelta = (eeval >> 3) & 0xFF;
+				if (ee->ee_version >= AR_EEPROM_VER4_6)
+					ee->ee_scaledCh14FilterCckDelta =
+						(eeval >> 11) & 0x1f;
+			}
+			if (i == headerInfo11A &&
+			    ee->ee_version >= AR_EEPROM_VER4_0) {
+				ee->ee_iqCalI[0] = (eeval >> 8 ) & 0x3f;
+				ee->ee_iqCalQ[0] = (eeval >> 3 ) & 0x1f;
+			}
+		} else {
+			ee->ee_gainI[i] = 10;
+			ee->ee_cckOfdmPwrDelta = TENX_OFDM_CCK_DELTA_INIT;
+		}
+		if (ee->ee_version >= AR_EEPROM_VER4_0) {
+			switch (i) {
+			case headerInfo11B:
+				EEREAD(off++);
+				ee->ee_calPier11b[0] =
+					fbin2freq_2p4(ee, eeval&0xff);
+				ee->ee_calPier11b[1] =
+					fbin2freq_2p4(ee, (eeval >> 8)&0xff);
+				EEREAD(off++);
+				ee->ee_calPier11b[2] =
+					fbin2freq_2p4(ee, eeval&0xff);
+				if (ee->ee_version >= AR_EEPROM_VER4_1)
+					ee->ee_rxtxMargin[headerInfo11B] =
+						(eeval >> 8) & 0x3f;
+				break;
+			case headerInfo11G:
+				EEREAD(off++);
+				ee->ee_calPier11g[0] =
+					fbin2freq_2p4(ee, eeval & 0xff);
+				ee->ee_calPier11g[1] =
+					fbin2freq_2p4(ee, (eeval >> 8) & 0xff);
+
+				EEREAD(off++);
+				ee->ee_turbo2WMaxPower2 = eeval & 0x7F;
+				ee->ee_xrTargetPower2 = (eeval >> 7) & 0x3f;
+
+				EEREAD(off++);
+				ee->ee_calPier11g[2] =
+					fbin2freq_2p4(ee, eeval & 0xff);
+				if (ee->ee_version >= AR_EEPROM_VER4_1)
+					 ee->ee_rxtxMargin[headerInfo11G] =
+						(eeval >> 8) & 0x3f;
+
+				EEREAD(off++);
+				ee->ee_iqCalI[1] = (eeval >> 5) & 0x3F;
+				ee->ee_iqCalQ[1] = eeval & 0x1F;
+
+				if (ee->ee_version >= AR_EEPROM_VER4_2) {
+					EEREAD(off++);
+					ee->ee_cckOfdmGainDelta =
+						(uint8_t)(eeval & 0xFF);
+					if (ee->ee_version >= AR_EEPROM_VER5_0) {
+						ee->ee_switchSettlingTurbo[1] =
+							(eeval >> 8) & 0x7f;
+						ee->ee_txrxAttenTurbo[1] =
+							(eeval >> 15) & 0x1;
+						EEREAD(off++);
+						ee->ee_txrxAttenTurbo[1] |=
+							(eeval & 0x1F) << 1;
+						ee->ee_rxtxMarginTurbo[1] =
+							(eeval >> 5) & 0x3F;
+						ee->ee_adcDesiredSizeTurbo[1] =
+							(eeval >> 11) & 0x1F;
+						EEREAD(off++);
+						ee->ee_adcDesiredSizeTurbo[1] |=
+							(eeval & 0x7) << 5;
+						ee->ee_pgaDesiredSizeTurbo[1] =
+							(eeval >> 3) & 0xFF;
+					}
+				}
+				break;
+			case headerInfo11A:
+				if (ee->ee_version >= AR_EEPROM_VER4_1) {
+					EEREAD(off++);
+					ee->ee_rxtxMargin[headerInfo11A] =
+						eeval & 0x3f;
+					if (ee->ee_version >= AR_EEPROM_VER5_0) {
+						ee->ee_switchSettlingTurbo[0] =
+							(eeval >> 6) & 0x7f;
+						ee->ee_txrxAttenTurbo[0] =
+							(eeval >> 13) & 0x7;
+						EEREAD(off++);
+						ee->ee_txrxAttenTurbo[0] |=
+							(eeval & 0x7) << 3;
+						ee->ee_rxtxMarginTurbo[0] =
+							(eeval >> 3) & 0x3F;
+						ee->ee_adcDesiredSizeTurbo[0] =
+							(eeval >> 9) & 0x7F;
+						EEREAD(off++);
+						ee->ee_adcDesiredSizeTurbo[0] |=
+							(eeval & 0x1) << 7;
+						ee->ee_pgaDesiredSizeTurbo[0] =
+							(eeval >> 1) & 0xFF;
+					}
+				}
+				break;
+			}
+		}
+	}
+	if (ee->ee_version < AR_EEPROM_VER3_3) {
+		/* Version 3.1+ specific parameters */
+		EEREAD(0xec);
+		ee->ee_ob2GHz[0] = eeval & 0x7;
+		ee->ee_db2GHz[0] = (eeval >> 3) & 0x7;
+
+		EEREAD(0xed);
+		ee->ee_ob2GHz[1] = eeval & 0x7;
+		ee->ee_db2GHz[1] = (eeval >> 3) & 0x7;
+	}
+
+	/* Initialize corner cal (thermal tx gain adjust parameters) */
+	ee->ee_cornerCal.clip = 4;
+	ee->ee_cornerCal.pd90 = 1;
+	ee->ee_cornerCal.pd84 = 1;
+	ee->ee_cornerCal.gSel = 0;
+
+	/*
+	* Read the conformance test limit identifiers
+	* These are used to match regulatory domain testing needs with
+	* the RD-specific tests that have been calibrated in the EEPROM.
+	*/
+	off = header[5];
+	for (i = 0; i < ee->ee_numCtls; i += 2) {
+		EEREAD(off++);
+		ee->ee_ctl[i] = (eeval >> 8) & 0xff;
+		ee->ee_ctl[i+1] = eeval & 0xff;
+	}
+
+	if (ee->ee_version < AR_EEPROM_VER5_3) {
+		/* XXX only for 5413? */
+		ee->ee_spurChans[0][1] = AR_SPUR_5413_1;
+		ee->ee_spurChans[1][1] = AR_SPUR_5413_2;
+		ee->ee_spurChans[2][1] = AR_NO_SPUR;
+		ee->ee_spurChans[0][0] = AR_NO_SPUR;
+	} else {
+		/* Read spur mitigation data */
+		for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+			EEREAD(off);
+			ee->ee_spurChans[i][0] = eeval;
+			EEREAD(off+AR_EEPROM_MODAL_SPURS);
+			ee->ee_spurChans[i][1] = eeval;
+			off++;
+		}
+	}
+
+	/* for recent changes to NF scale */
+	if (ee->ee_version <= AR_EEPROM_VER3_2) {
+		ee->ee_noiseFloorThresh[headerInfo11A] = -54;
+		ee->ee_noiseFloorThresh[headerInfo11B] = -1;
+		ee->ee_noiseFloorThresh[headerInfo11G] = -1;
+	}
+	/* to override thresh62 for better 2.4 and 5 operation */
+	if (ee->ee_version <= AR_EEPROM_VER3_2) {
+		ee->ee_thresh62[headerInfo11A] = 15;	/* 11A */
+		ee->ee_thresh62[headerInfo11B] = 28;	/* 11B */
+		ee->ee_thresh62[headerInfo11G] = 28;	/* 11G */
+	}
+
+	/* Check for regulatory capabilities */
+	if (ee->ee_version >= AR_EEPROM_VER4_0) {
+		EEREAD(regCapOffsetPost4_0);
+	} else {
+		EEREAD(regCapOffsetPre4_0);
+	}
+
+	ee->ee_regCap = eeval;
+
+	if (ee->ee_Amode == 0) {
+		/* Check for valid Amode in upgraded h/w */
+		if (ee->ee_version >= AR_EEPROM_VER4_0) {
+			ee->ee_Amode = (ee->ee_regCap & AR_EEPROM_EEREGCAP_EN_KK_NEW_11A)?1:0;
+		} else {
+			ee->ee_Amode = (ee->ee_regCap & AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0)?1:0;
+		}
+	}
+
+	if (ee->ee_version >= AR_EEPROM_VER5_1)
+		EEREAD(AR_EEPROM_CAPABILITIES_OFFSET);
+	else
+		eeval = 0;
+	ee->ee_opCap = eeval;
+
+	EEREAD(AR_EEPROM_REG_DOMAIN);
+	ee->ee_regdomain = eeval;
+
+	return AH_TRUE;
+#undef EEREAD
+}
+
+/*
+ * Now verify and copy EEPROM contents into the allocated space
+ */
+static HAL_BOOL
+legacyEepromReadContents(struct ath_hal *ah, HAL_EEPROM *ee)
+{
+	/* Read the header information here */
+	if (!readHeaderInfo(ah, ee))
+		return AH_FALSE;
+#if 0
+	/* Require 5112 devices to have EEPROM 4.0 EEP_MAP set */
+	if (IS_5112(ah) && !ee->ee_eepMap) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: 5112 devices must have EEPROM 4.0 with the "
+		    "EEP_MAP set\n", __func__);
+		return AH_FALSE;
+	}
+#endif
+	/*
+	 * Group 1: frequency pier locations readback
+	 * check that the structure has been populated
+	 * with enough space to hold the channels
+	 *
+	 * NOTE: Group 1 contains the 5 GHz channel numbers
+	 *	 that have dBm->pcdac calibrated information.
+	 */
+	if (!readEepromFreqPierInfo(ah, ee))
+		return AH_FALSE;
+
+	/*
+	 * Group 2:  readback data for all frequency piers
+	 *
+	 * NOTE: Group 2 contains the raw power calibration
+	 *	 information for each of the channels that we
+	 *	 recorded above.
+	 */
+	if (!readEepromRawPowerCalInfo(ah, ee))
+		return AH_FALSE;
+
+	/*
+	 * Group 5: target power values per rate
+	 *
+	 * NOTE: Group 5 contains the recorded maximum power
+	 *	 in dB that can be attained for the given rate.
+	 */
+	/* Read the power per rate info for test channels */
+	if (!readEepromTargetPowerCalInfo(ah, ee))
+		return AH_FALSE;
+
+	/*
+	 * Group 8: Conformance Test Limits information
+	 *
+	 * NOTE: Group 8 contains the values to limit the
+	 *	 maximum transmit power value based on any
+	 *	 band edge violations.
+	 */
+	/* Read the RD edge power limits */
+	return readEepromCTLInfo(ah, ee);
+}
+
+static HAL_STATUS
+legacyEepromGet(struct ath_hal *ah, int param, void *val)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint8_t *macaddr;
+	uint16_t eeval;
+	uint32_t sum;
+	int i;
+
+	switch (param) {
+	case AR_EEP_OPCAP:
+		*(uint16_t *) val = ee->ee_opCap;
+		return HAL_OK;
+	case AR_EEP_REGDMN_0:
+		*(uint16_t *) val = ee->ee_regdomain;
+		return HAL_OK;
+	case AR_EEP_RFSILENT:
+		if (!ath_hal_eepromRead(ah, AR_EEPROM_RFSILENT, &eeval))
+			return HAL_EEREAD;
+		*(uint16_t *) val = eeval;
+		return HAL_OK;
+	case AR_EEP_MACADDR:
+		sum = 0;
+		macaddr = val;
+		for (i = 0; i < 3; i++) {
+			if (!ath_hal_eepromRead(ah, AR_EEPROM_MAC(2-i), &eeval)) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+				    "%s: cannot read EEPROM location %u\n",
+				    __func__, i);
+				return HAL_EEREAD;
+			}
+			sum += eeval;
+			macaddr[2*i] = eeval >> 8;
+			macaddr[2*i + 1] = eeval & 0xff;
+		}
+		if (sum == 0 || sum == 0xffff*3) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: mac address read failed: %s\n", __func__,
+			    ath_hal_ether_sprintf(macaddr));
+			return HAL_EEBADMAC;
+		}
+		return HAL_OK;
+	case AR_EEP_RFKILL:
+		HALASSERT(val == AH_NULL);
+		return ee->ee_rfKill ? HAL_OK : HAL_EIO;
+	case AR_EEP_AMODE:
+		HALASSERT(val == AH_NULL);
+		return ee->ee_Amode ? HAL_OK : HAL_EIO;
+	case AR_EEP_BMODE:
+		HALASSERT(val == AH_NULL);
+		return ee->ee_Bmode ? HAL_OK : HAL_EIO;
+	case AR_EEP_GMODE:
+		HALASSERT(val == AH_NULL);
+		return ee->ee_Gmode ? HAL_OK : HAL_EIO;
+	case AR_EEP_TURBO5DISABLE:
+		HALASSERT(val == AH_NULL);
+		return ee->ee_turbo5Disable ? HAL_OK : HAL_EIO;
+	case AR_EEP_TURBO2DISABLE:
+		HALASSERT(val == AH_NULL);
+		return ee->ee_turbo2Disable ? HAL_OK : HAL_EIO;
+	case AR_EEP_ISTALON:		/* Talon detect */
+		HALASSERT(val == AH_NULL);
+		return (ee->ee_version >= AR_EEPROM_VER5_4 &&
+		    ath_hal_eepromRead(ah, 0x0b, &eeval) && eeval == 1) ?
+			HAL_OK : HAL_EIO;
+	case AR_EEP_32KHZCRYSTAL:
+		HALASSERT(val == AH_NULL);
+		return ee->ee_exist32kHzCrystal ? HAL_OK : HAL_EIO;
+	case AR_EEP_COMPRESS:
+		HALASSERT(val == AH_NULL);
+		return (ee->ee_opCap & AR_EEPROM_EEPCAP_COMPRESS_DIS) == 0 ?
+		    HAL_OK : HAL_EIO;
+	case AR_EEP_FASTFRAME:
+		HALASSERT(val == AH_NULL);
+		return (ee->ee_opCap & AR_EEPROM_EEPCAP_FASTFRAME_DIS) == 0 ?
+		    HAL_OK : HAL_EIO;
+	case AR_EEP_AES:
+		HALASSERT(val == AH_NULL);
+		return (ee->ee_opCap & AR_EEPROM_EEPCAP_AES_DIS) == 0 ?
+		    HAL_OK : HAL_EIO;
+	case AR_EEP_BURST:
+		HALASSERT(val == AH_NULL);
+		return (ee->ee_opCap & AR_EEPROM_EEPCAP_BURST_DIS) == 0 ?
+		    HAL_OK : HAL_EIO;
+	case AR_EEP_MAXQCU:
+		if (ee->ee_opCap & AR_EEPROM_EEPCAP_MAXQCU) {
+			*(uint16_t *) val =
+			    MS(ee->ee_opCap, AR_EEPROM_EEPCAP_MAXQCU);
+			return HAL_OK;
+		} else
+			return HAL_EIO;
+	case AR_EEP_KCENTRIES:
+		if (ee->ee_opCap & AR_EEPROM_EEPCAP_KC_ENTRIES) {
+			*(uint16_t *) val =
+			    1 << MS(ee->ee_opCap, AR_EEPROM_EEPCAP_KC_ENTRIES);
+			return HAL_OK;
+		} else
+			return HAL_EIO;
+	case AR_EEP_ANTGAINMAX_5:
+		*(int8_t *) val = ee->ee_antennaGainMax[0];
+		return HAL_OK;
+	case AR_EEP_ANTGAINMAX_2:
+		*(int8_t *) val = ee->ee_antennaGainMax[1];
+		return HAL_OK;
+	case AR_EEP_WRITEPROTECT:
+		HALASSERT(val == AH_NULL);
+		return (ee->ee_protect & AR_EEPROM_PROTECT_WP_128_191) ?
+		    HAL_OK : HAL_EIO;
+	}
+	return HAL_EINVAL;
+}
+
+static HAL_BOOL
+legacyEepromSet(struct ath_hal *ah, int param, int v)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	switch (param) {
+	case AR_EEP_AMODE:
+		ee->ee_Amode = v;
+		return HAL_OK;
+	case AR_EEP_BMODE:
+		ee->ee_Bmode = v;
+		return HAL_OK;
+	case AR_EEP_GMODE:
+		ee->ee_Gmode = v;
+		return HAL_OK;
+	case AR_EEP_TURBO5DISABLE:
+		ee->ee_turbo5Disable = v;
+		return HAL_OK;
+	case AR_EEP_TURBO2DISABLE:
+		ee->ee_turbo2Disable = v;
+		return HAL_OK;
+	case AR_EEP_COMPRESS:
+		if (v)
+			ee->ee_opCap &= ~AR_EEPROM_EEPCAP_COMPRESS_DIS;
+		else
+			ee->ee_opCap |= AR_EEPROM_EEPCAP_COMPRESS_DIS;
+		return HAL_OK;
+	case AR_EEP_FASTFRAME:
+		if (v)
+			ee->ee_opCap &= ~AR_EEPROM_EEPCAP_FASTFRAME_DIS;
+		else
+			ee->ee_opCap |= AR_EEPROM_EEPCAP_FASTFRAME_DIS;
+		return HAL_OK;
+	case AR_EEP_AES:
+		if (v)
+			ee->ee_opCap &= ~AR_EEPROM_EEPCAP_AES_DIS;
+		else
+			ee->ee_opCap |= AR_EEPROM_EEPCAP_AES_DIS;
+		return HAL_OK;
+	case AR_EEP_BURST:
+		if (v)
+			ee->ee_opCap &= ~AR_EEPROM_EEPCAP_BURST_DIS;
+		else
+			ee->ee_opCap |= AR_EEPROM_EEPCAP_BURST_DIS;
+		return HAL_OK;
+	}
+	return HAL_EINVAL;
+}
+
+static HAL_BOOL
+legacyEepromDiag(struct ath_hal *ah, int request,
+     const void *args, uint32_t argsize, void **result, uint32_t *resultsize)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const EEPROM_POWER_EXPN_5112 *pe;
+
+	switch (request) {
+	case HAL_DIAG_EEPROM:
+		*result = ee;
+		*resultsize = sizeof(*ee);
+		return AH_TRUE;
+	case HAL_DIAG_EEPROM_EXP_11A:
+	case HAL_DIAG_EEPROM_EXP_11B:
+	case HAL_DIAG_EEPROM_EXP_11G:
+		pe = &ee->ee_modePowerArray5112[
+		    request - HAL_DIAG_EEPROM_EXP_11A];
+		*result = pe->pChannels;
+		*resultsize = (*result == AH_NULL) ? 0 :
+			roundup(sizeof(uint16_t) * pe->numChannels,
+				sizeof(uint32_t)) +
+			sizeof(EXPN_DATA_PER_CHANNEL_5112) * pe->numChannels;
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+static uint16_t
+legacyEepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	HALASSERT(0 <= ix && ix < AR_EEPROM_MODAL_SPURS);
+	return ee->ee_spurChans[ix][is2GHz];
+}
+
+/*
+ * Reclaim any EEPROM-related storage.
+ */
+static void
+legacyEepromDetach(struct ath_hal *ah)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+        if (ee->ee_version >= AR_EEPROM_VER4_0 && ee->ee_eepMap == 1)
+		return freeEepromRawPowerCalInfo5112(ah, ee);
+	ath_hal_free(ee);
+	AH_PRIVATE(ah)->ah_eeprom = AH_NULL;
+}
+
+/*
+ * These are not valid 2.4 channels, either we change 'em
+ * or we need to change the coding to accept them.
+ */
+static const uint16_t channels11b[] = { 2412, 2447, 2484 };
+static const uint16_t channels11g[] = { 2312, 2412, 2484 };
+
+HAL_STATUS
+ath_hal_legacyEepromAttach(struct ath_hal *ah)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint32_t sum, eepMax;
+	uint16_t eeversion, eeprotect, eeval;
+	u_int i;
+
+	HALASSERT(ee == AH_NULL);
+
+	if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, &eeversion)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: unable to read EEPROM version\n", __func__);
+		return HAL_EEREAD;
+	}
+	if (eeversion < AR_EEPROM_VER3) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unsupported EEPROM version "
+		    "%u (0x%x) found\n", __func__, eeversion, eeversion);
+		return HAL_EEVERSION;
+	}
+
+	if (!ath_hal_eepromRead(ah, AR_EEPROM_PROTECT, &eeprotect)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cannot read EEPROM protection "
+		    "bits; read locked?\n", __func__);
+		return HAL_EEREAD;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "EEPROM protect 0x%x\n", eeprotect);
+	/* XXX check proper access before continuing */
+
+	/*
+	 * Read the Atheros EEPROM entries and calculate the checksum.
+	 */
+	if (!ath_hal_eepromRead(ah, AR_EEPROM_SIZE_UPPER, &eeval)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot read EEPROM upper size\n" , __func__);
+		return HAL_EEREAD;
+	}
+	if (eeval != 0)	{
+		eepMax = (eeval & AR_EEPROM_SIZE_UPPER_MASK) <<
+			AR_EEPROM_SIZE_ENDLOC_SHIFT;
+		if (!ath_hal_eepromRead(ah, AR_EEPROM_SIZE_LOWER, &eeval)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: cannot read EEPROM lower size\n" , __func__);
+			return HAL_EEREAD;
+		}
+		eepMax = (eepMax | eeval) - AR_EEPROM_ATHEROS_BASE;
+	} else
+		eepMax = AR_EEPROM_ATHEROS_MAX;
+	sum = 0;
+	for (i = 0; i < eepMax; i++) {
+		if (!ath_hal_eepromRead(ah, AR_EEPROM_ATHEROS(i), &eeval)) {
+			return HAL_EEREAD;
+		}
+		sum ^= eeval;
+	}
+	if (sum != 0xffff) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad EEPROM checksum 0x%x\n",
+		    __func__, sum);
+		return HAL_EEBADSUM;
+	}
+
+	ee = ath_hal_malloc(sizeof(HAL_EEPROM));
+	if (ee == AH_NULL) {
+		/* XXX message */
+		return HAL_ENOMEM;
+	}
+
+	ee->ee_protect = eeprotect;
+	ee->ee_version = eeversion;
+
+	ee->ee_numChannels11a = NUM_11A_EEPROM_CHANNELS;
+	ee->ee_numChannels2_4 = NUM_2_4_EEPROM_CHANNELS;
+
+	for (i = 0; i < NUM_11A_EEPROM_CHANNELS; i ++)
+		ee->ee_dataPerChannel11a[i].numPcdacValues = NUM_PCDAC_VALUES;
+
+	/* the channel list for 2.4 is fixed, fill this in here */
+	for (i = 0; i < NUM_2_4_EEPROM_CHANNELS; i++) {
+		ee->ee_channels11b[i] = channels11b[i];
+		/* XXX 5211 requires a hack though we don't support 11g */
+		if (ah->ah_magic == 0x19570405)
+			ee->ee_channels11g[i] = channels11b[i];
+		else
+			ee->ee_channels11g[i] = channels11g[i];
+		ee->ee_dataPerChannel11b[i].numPcdacValues = NUM_PCDAC_VALUES;
+		ee->ee_dataPerChannel11g[i].numPcdacValues = NUM_PCDAC_VALUES;
+	}
+
+	if (!legacyEepromReadContents(ah, ee)) {
+		/* XXX message */
+		ath_hal_free(ee);
+		return HAL_EEREAD;	/* XXX */
+	}
+
+	AH_PRIVATE(ah)->ah_eeprom = ee;
+	AH_PRIVATE(ah)->ah_eeversion = eeversion;
+	AH_PRIVATE(ah)->ah_eepromDetach = legacyEepromDetach;
+	AH_PRIVATE(ah)->ah_eepromGet = legacyEepromGet;
+	AH_PRIVATE(ah)->ah_eepromSet = legacyEepromSet;
+	AH_PRIVATE(ah)->ah_getSpurChan = legacyEepromGetSpurChan;
+	AH_PRIVATE(ah)->ah_eepromDiag = legacyEepromDiag;
+	return HAL_OK;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v3.h b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v3.h
new file mode 100644
index 0000000..9f30c72
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_eeprom_v3.h
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_eeprom_v3.h,v 1.2 2008/11/10 04:08:00 sam Exp $
+ */
+#ifndef _ATH_AH_EEPROM_V3_H_
+#define _ATH_AH_EEPROM_V3_H_
+
+#include "ah_eeprom.h"
+
+/* EEPROM defines for Version 2 & 3 AR5211 chips */
+#define	AR_EEPROM_RFSILENT	0x0f	/* RF Silent/Clock Run Enable */
+#define	AR_EEPROM_MAC(i)	(0x1d+(i)) /* MAC address word */
+#define	AR_EEPROM_MAGIC		0x3d	/* magic number */
+#define	AR_EEPROM_PROTECT	0x3f	/* EEPROM protect bits */
+#define	AR_EEPROM_PROTECT_PCIE	0x01	/* EEPROM protect bits for Condor/Swan*/
+#define	AR_EEPROM_REG_DOMAIN	0xbf	/* current regulatory domain */
+#define	AR_EEPROM_ATHEROS_BASE	0xc0	/* Base of Atheros-specific data */
+#define	AR_EEPROM_ATHEROS(i)	(AR_EEPROM_ATHEROS_BASE+(i))
+#define	AR_EEPROM_ATHEROS_MAX	(0x400-AR_EEPROM_ATHEROS_BASE)
+#define	AR_EEPROM_VERSION	AR_EEPROM_ATHEROS(1)
+
+/* FLASH(EEPROM) Defines for AR531X chips */
+#define AR_EEPROM_SIZE_LOWER    0x1b    /* size info -- lower */
+#define AR_EEPROM_SIZE_UPPER    0x1c    /* size info -- upper */
+#define AR_EEPROM_SIZE_UPPER_MASK 0xfff0
+#define AR_EEPROM_SIZE_UPPER_SHIFT 4
+#define	AR_EEPROM_SIZE_ENDLOC_SHIFT 12
+#define AR_EEPROM_ATHEROS_MAX_LOC 0x400
+#define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE)
+
+/* regulatory capabilities offsets */
+#define AR_EEPROM_REG_CAPABILITIES_OFFSET		0xCA
+#define AR_EEPROM_REG_CAPABILITIES_OFFSET_PRE4_0	0xCF /* prior to 4.0 */
+
+/* regulatory capabilities */
+#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND	0x0040
+#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN	0x0080
+#define AR_EEPROM_EEREGCAP_EN_KK_U2		0x0100
+#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND	0x0200
+#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD		0x0400
+#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A	0x0800
+
+/* regulatory capabilities prior to eeprom version 4.0 */
+#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0	0x4000
+#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0	0x8000
+
+/*
+ * AR2413 (includes AR5413)
+ */
+#define AR_EEPROM_SERIAL_NUM_OFFSET     0xB0    /* EEPROM serial number */
+#define AR_EEPROM_SERIAL_NUM_SIZE       12      /* EEPROM serial number size */
+#define AR_EEPROM_CAPABILITIES_OFFSET   0xC9    /* EEPROM Location of capabilities */
+
+#define AR_EEPROM_EEPCAP_COMPRESS_DIS	0x0001
+#define AR_EEPROM_EEPCAP_AES_DIS	0x0002
+#define AR_EEPROM_EEPCAP_FASTFRAME_DIS	0x0004
+#define AR_EEPROM_EEPCAP_BURST_DIS	0x0008
+#define AR_EEPROM_EEPCAP_MAXQCU		0x01F0
+#define AR_EEPROM_EEPCAP_MAXQCU_S	4
+#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN	0x0200
+#define AR_EEPROM_EEPCAP_KC_ENTRIES	0xF000
+#define AR_EEPROM_EEPCAP_KC_ENTRIES_S	12
+
+/* XXX used to index various EEPROM-derived data structures */
+enum {
+	headerInfo11A	= 0,
+	headerInfo11B	= 1,
+	headerInfo11G	= 2,
+};
+
+#define GROUPS_OFFSET3_2	0x100	/* groups offset for ver3.2 and earlier */
+#define GROUPS_OFFSET3_3	0x150	/* groups offset for ver3.3 */
+/* relative offset of GROUPi to GROUPS_OFFSET */
+#define GROUP1_OFFSET		0x0
+#define GROUP2_OFFSET		0x5
+#define GROUP3_OFFSET		0x37
+#define GROUP4_OFFSET		0x46
+#define GROUP5_OFFSET		0x55
+#define GROUP6_OFFSET		0x65
+#define GROUP7_OFFSET		0x69
+#define GROUP8_OFFSET		0x6f
+
+/* RF silent fields in EEPROM */
+#define AR_EEPROM_RFSILENT_GPIO_SEL	0x001c
+#define AR_EEPROM_RFSILENT_GPIO_SEL_S	2
+#define AR_EEPROM_RFSILENT_POLARITY	0x0002
+#define AR_EEPROM_RFSILENT_POLARITY_S	1
+
+/* Protect Bits RP is read protect, WP is write protect */
+#define	AR_EEPROM_PROTECT_RP_0_31	0x0001
+#define	AR_EEPROM_PROTECT_WP_0_31	0x0002
+#define	AR_EEPROM_PROTECT_RP_32_63	0x0004
+#define	AR_EEPROM_PROTECT_WP_32_63	0x0008
+#define	AR_EEPROM_PROTECT_RP_64_127	0x0010
+#define	AR_EEPROM_PROTECT_WP_64_127	0x0020
+#define	AR_EEPROM_PROTECT_RP_128_191	0x0040
+#define	AR_EEPROM_PROTECT_WP_128_191	0x0080
+#define	AR_EEPROM_PROTECT_RP_192_207	0x0100
+#define	AR_EEPROM_PROTECT_WP_192_207	0x0200
+#define	AR_EEPROM_PROTECT_RP_208_223	0x0400
+#define	AR_EEPROM_PROTECT_WP_208_223	0x0800
+#define	AR_EEPROM_PROTECT_RP_224_239	0x1000
+#define	AR_EEPROM_PROTECT_WP_224_239	0x2000
+#define	AR_EEPROM_PROTECT_RP_240_255	0x4000
+#define	AR_EEPROM_PROTECT_WP_240_255	0x8000
+
+#define	AR_EEPROM_MODAL_SPURS		5
+#define	AR_SPUR_5413_1			1640	/* Freq 2464 */
+#define	AR_SPUR_5413_2			1200	/* Freq 2420 */
+
+/*
+ * EEPROM fixed point conversion scale factors.
+ * NB: if you change one be sure to keep the other in sync.
+ */
+#define EEP_SCALE	100		/* conversion scale to avoid fp arith */
+#define EEP_DELTA	10		/* SCALE/10, to avoid arith divide */
+
+#define PWR_MIN		0
+#define PWR_MAX		3150		/* 31.5 * SCALE */
+#define PWR_STEP	50		/* 0.5 * SCALE */
+/* Keep 2 above defines together */
+
+#define NUM_11A_EEPROM_CHANNELS	10
+#define NUM_2_4_EEPROM_CHANNELS	3
+#define NUM_PCDAC_VALUES	11
+#define NUM_TEST_FREQUENCIES	8
+#define NUM_EDGES	 	8
+#define NUM_INTERCEPTS	 	11
+#define FREQ_MASK		0x7f
+#define FREQ_MASK_3_3		0xff	/* expanded in version 3.3 */
+#define PCDAC_MASK		0x3f
+#define POWER_MASK		0x3f
+#define	NON_EDGE_FLAG_MASK	0x40
+#define CHANNEL_POWER_INFO	8
+#define OBDB_UNSET		0xffff
+#define	CHANNEL_UNUSED		0xff
+#define	SCALE_OC_DELTA(_x)	(((_x) * 2) / 10)
+
+/* Used during pcdac table construction */
+#define PCDAC_START	1
+#define PCDAC_STOP	63
+#define PCDAC_STEP	1
+#define PWR_TABLE_SIZE	64
+#define	MAX_RATE_POWER	63
+
+/* Used during power/rate table construction */
+#define NUM_CTLS	16
+#define	NUM_CTLS_3_3	32		/* expanded in version 3.3 */
+#define	NUM_CTLS_MAX	NUM_CTLS_3_3
+
+typedef struct fullPcdacStruct {
+	uint16_t	channelValue;
+	uint16_t	pcdacMin;
+	uint16_t	pcdacMax;
+	uint16_t	numPcdacValues;
+	uint16_t	PcdacValues[64];
+	/* power is 32bit since in dest it is scaled */
+	int16_t		PwrValues[64];
+} FULL_PCDAC_STRUCT;
+
+typedef struct dataPerChannel {
+	uint16_t	channelValue;
+	uint16_t	pcdacMin;
+	uint16_t	pcdacMax;
+	uint16_t	numPcdacValues;
+	uint16_t	PcdacValues[NUM_PCDAC_VALUES];
+	/* NB: power is 32bit since in dest it is scaled */
+	int16_t		PwrValues[NUM_PCDAC_VALUES];
+} DATA_PER_CHANNEL;
+
+/* points to the appropriate pcdac structs in the above struct based on mode */
+typedef struct pcdacsEeprom {
+	const uint16_t	*pChannelList;
+	uint16_t	numChannels;
+	const DATA_PER_CHANNEL *pDataPerChannel;
+} PCDACS_EEPROM;
+
+typedef struct trgtPowerInfo {
+	uint16_t	twicePwr54;
+	uint16_t	twicePwr48;
+	uint16_t	twicePwr36;
+	uint16_t	twicePwr6_24;
+	uint16_t	testChannel;
+} TRGT_POWER_INFO;
+
+typedef struct trgtPowerAllModes {
+	uint16_t	numTargetPwr_11a;
+	TRGT_POWER_INFO trgtPwr_11a[NUM_TEST_FREQUENCIES];
+	uint16_t	numTargetPwr_11g;
+	TRGT_POWER_INFO trgtPwr_11g[3];
+	uint16_t	numTargetPwr_11b;
+	TRGT_POWER_INFO trgtPwr_11b[2];
+} TRGT_POWER_ALL_MODES;
+
+typedef struct cornerCalInfo {
+	uint16_t	gSel;
+	uint16_t	pd84;
+	uint16_t	pd90;
+	uint16_t	clip;
+} CORNER_CAL_INFO;
+
+/*
+ * EEPROM version 4 definitions
+ */
+#define NUM_XPD_PER_CHANNEL      4
+#define NUM_POINTS_XPD0          4
+#define NUM_POINTS_XPD3          3
+#define IDEAL_10dB_INTERCEPT_2G  35
+#define IDEAL_10dB_INTERCEPT_5G  55
+
+#define	TENX_OFDM_CCK_DELTA_INIT	15		/* power 1.5 dbm */
+#define	TENX_CH14_FILTER_CCK_DELTA_INIT	15		/* power 1.5 dbm */
+#define	CCK_OFDM_GAIN_DELTA		15
+
+#define NUM_TARGET_POWER_LOCATIONS_11B  4
+#define NUM_TARGET_POWER_LOCATIONS_11G  6
+
+
+typedef struct {
+	uint16_t	xpd_gain;
+	uint16_t	numPcdacs;
+	uint16_t	pcdac[NUM_POINTS_XPD0];
+	int16_t		pwr_t4[NUM_POINTS_XPD0];	/* or gainF */
+} EXPN_DATA_PER_XPD_5112;
+
+typedef struct {
+	uint16_t	channelValue;
+	int16_t		maxPower_t4;                
+	EXPN_DATA_PER_XPD_5112	pDataPerXPD[NUM_XPD_PER_CHANNEL];
+} EXPN_DATA_PER_CHANNEL_5112;
+
+typedef struct {
+	uint16_t	*pChannels;
+	uint16_t	numChannels;
+	uint16_t 	xpdMask;	/* mask of permitted xpd_gains */
+	EXPN_DATA_PER_CHANNEL_5112 *pDataPerChannel;
+} EEPROM_POWER_EXPN_5112;
+
+typedef struct {
+	uint16_t	channelValue;
+	uint16_t	pcd1_xg0;
+	int16_t		pwr1_xg0;
+	uint16_t	pcd2_delta_xg0;
+	int16_t		pwr2_xg0;
+	uint16_t	pcd3_delta_xg0;
+	int16_t		pwr3_xg0;
+	uint16_t	pcd4_delta_xg0;
+	int16_t		pwr4_xg0;
+	int16_t		maxPower_t4;
+	int16_t		pwr1_xg3;	/* pcdac = 20 */
+	int16_t		pwr2_xg3;	/* pcdac = 35 */
+	int16_t		pwr3_xg3;	/* pcdac = 63 */
+	/* XXX - Should be pwr1_xg2, etc to agree with documentation */
+} EEPROM_DATA_PER_CHANNEL_5112;
+
+typedef struct {
+	uint16_t	pChannels[NUM_11A_EEPROM_CHANNELS];
+	uint16_t	numChannels;
+	uint16_t	xpdMask;	/* mask of permitted xpd_gains */
+	EEPROM_DATA_PER_CHANNEL_5112 pDataPerChannel[NUM_11A_EEPROM_CHANNELS];
+} EEPROM_POWER_5112;
+
+/*
+ * EEPROM version 5 definitions (Griffin, et. al.).
+ */
+#define NUM_2_4_EEPROM_CHANNELS_2413	4
+#define NUM_11A_EEPROM_CHANNELS_2413    10
+#define PWR_TABLE_SIZE_2413		128
+
+/* Used during pdadc construction */
+#define	MAX_NUM_PDGAINS_PER_CHANNEL	4
+#define	NUM_PDGAINS_PER_CHANNEL		2
+#define	NUM_POINTS_LAST_PDGAIN		5
+#define	NUM_POINTS_OTHER_PDGAINS	4
+#define	XPD_GAIN1_GEN5			3
+#define	XPD_GAIN2_GEN5			1
+#define	MAX_PWR_RANGE_IN_HALF_DB	64
+#define	PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB	4
+
+typedef struct {
+	uint16_t	pd_gain;
+	uint16_t	numVpd;
+	uint16_t	Vpd[NUM_POINTS_LAST_PDGAIN];
+	int16_t		pwr_t4[NUM_POINTS_LAST_PDGAIN];	/* or gainF */
+} RAW_DATA_PER_PDGAIN_2413;
+
+typedef struct {
+	uint16_t	channelValue;
+	int16_t		maxPower_t4;    
+	uint16_t	numPdGains;	/* # Pd Gains per channel */
+	RAW_DATA_PER_PDGAIN_2413 pDataPerPDGain[MAX_NUM_PDGAINS_PER_CHANNEL];
+} RAW_DATA_PER_CHANNEL_2413;
+
+/* XXX: assumes NUM_11A_EEPROM_CHANNELS_2413 >= NUM_2_4_EEPROM_CHANNELS_2413 ??? */
+typedef struct {
+	uint16_t	pChannels[NUM_11A_EEPROM_CHANNELS_2413];
+	uint16_t	numChannels;
+	uint16_t	xpd_mask;	/* mask of permitted xpd_gains */
+	RAW_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413];
+} RAW_DATA_STRUCT_2413;
+
+typedef struct {
+	uint16_t	channelValue;
+	uint16_t	numPdGains;
+	uint16_t	Vpd_I[MAX_NUM_PDGAINS_PER_CHANNEL];
+	int16_t		pwr_I[MAX_NUM_PDGAINS_PER_CHANNEL];
+	uint16_t	Vpd_delta[NUM_POINTS_LAST_PDGAIN]
+				[MAX_NUM_PDGAINS_PER_CHANNEL];
+	int16_t		pwr_delta_t2[NUM_POINTS_LAST_PDGAIN]
+				[MAX_NUM_PDGAINS_PER_CHANNEL];
+	int16_t		maxPower_t4;
+} EEPROM_DATA_PER_CHANNEL_2413;
+
+typedef struct {
+	uint16_t	pChannels[NUM_11A_EEPROM_CHANNELS_2413];
+	uint16_t	numChannels;
+	uint16_t	xpd_mask;	/* mask of permitted xpd_gains */
+	EEPROM_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413];
+} EEPROM_DATA_STRUCT_2413;
+
+/*
+ * Information retrieved from EEPROM.
+ */
+typedef struct {
+	uint16_t	ee_version;		/* Version field */
+	uint16_t	ee_protect;		/* EEPROM protect field */
+	uint16_t	ee_regdomain;		/* Regulatory domain */
+
+	/* General Device Parameters */
+	uint16_t	ee_turbo5Disable;
+	uint16_t	ee_turbo2Disable;
+	uint16_t	ee_rfKill;
+	uint16_t	ee_deviceType;
+	uint16_t	ee_turbo2WMaxPower5;
+	uint16_t	ee_turbo2WMaxPower2;
+	uint16_t	ee_xrTargetPower5;
+	uint16_t	ee_xrTargetPower2;
+	uint16_t	ee_Amode;
+	uint16_t	ee_regCap;
+	uint16_t	ee_Bmode;
+	uint16_t	ee_Gmode;
+	int8_t		ee_antennaGainMax[2];
+	uint16_t	ee_xtnd5GSupport;
+	uint8_t		ee_cckOfdmPwrDelta;
+	uint8_t		ee_exist32kHzCrystal;
+	uint16_t	ee_targetPowersStart;
+	uint16_t	ee_fixedBias5;
+	uint16_t	ee_fixedBias2;
+	uint16_t	ee_cckOfdmGainDelta;
+	uint16_t	ee_scaledCh14FilterCckDelta;
+	uint16_t	ee_eepMap;
+	uint16_t	ee_earStart;
+
+	/* 5 GHz / 2.4 GHz CKK / 2.4 GHz OFDM common parameters */
+	uint16_t	ee_switchSettling[3];
+	uint16_t	ee_txrxAtten[3];
+	uint16_t	ee_txEndToXLNAOn[3];
+	uint16_t	ee_thresh62[3];
+	uint16_t	ee_txEndToXPAOff[3];
+	uint16_t	ee_txFrameToXPAOn[3];
+	int8_t		ee_adcDesiredSize[3];	 /* 8-bit signed value */
+	int8_t		ee_pgaDesiredSize[3];	 /* 8-bit signed value */
+	int16_t		ee_noiseFloorThresh[3];
+	uint16_t	ee_xlnaGain[3];
+	uint16_t	ee_xgain[3];
+	uint16_t	ee_xpd[3];
+	uint16_t	ee_antennaControl[11][3];
+	uint16_t	ee_falseDetectBackoff[3];
+	uint16_t	ee_gainI[3];
+	uint16_t	ee_rxtxMargin[3];
+
+	/* new parameters added for the AR2413 */
+	HAL_BOOL	ee_disableXr5;
+	HAL_BOOL	ee_disableXr2;
+	uint16_t	ee_eepMap2PowerCalStart;
+	uint16_t	ee_capField;
+
+	uint16_t	ee_switchSettlingTurbo[2];
+	uint16_t	ee_txrxAttenTurbo[2];
+	int8_t		ee_adcDesiredSizeTurbo[2];
+	int8_t		ee_pgaDesiredSizeTurbo[2];
+	uint16_t	ee_rxtxMarginTurbo[2];
+
+	/* 5 GHz parameters */
+	uint16_t	ee_ob1;
+	uint16_t	ee_db1;
+	uint16_t	ee_ob2;
+	uint16_t	ee_db2;
+	uint16_t	ee_ob3;
+	uint16_t	ee_db3;
+	uint16_t	ee_ob4;
+	uint16_t	ee_db4;
+
+	/* 2.4 GHz parameters */
+	uint16_t	ee_obFor24;
+	uint16_t	ee_dbFor24;
+	uint16_t	ee_obFor24g;
+	uint16_t	ee_dbFor24g;
+	uint16_t	ee_ob2GHz[2];
+	uint16_t	ee_db2GHz[2];
+	uint16_t	ee_numCtls;
+	uint16_t	ee_ctl[NUM_CTLS_MAX];
+	uint16_t	ee_iqCalI[2];
+	uint16_t	ee_iqCalQ[2];
+	uint16_t	ee_calPier11g[NUM_2_4_EEPROM_CHANNELS];
+	uint16_t	ee_calPier11b[NUM_2_4_EEPROM_CHANNELS];
+
+	/* corner calibration information */
+	CORNER_CAL_INFO	ee_cornerCal;
+
+	uint16_t	ee_opCap;
+
+	/* 11a info */
+	uint16_t	ee_channels11a[NUM_11A_EEPROM_CHANNELS];
+	uint16_t	ee_numChannels11a;
+	DATA_PER_CHANNEL ee_dataPerChannel11a[NUM_11A_EEPROM_CHANNELS];
+
+	uint16_t	ee_numChannels2_4;
+	uint16_t	ee_channels11g[NUM_2_4_EEPROM_CHANNELS];
+	uint16_t	ee_channels11b[NUM_2_4_EEPROM_CHANNELS];
+	uint16_t	ee_spurChans[AR_EEPROM_MODAL_SPURS][2];
+
+	/* 11g info */
+	DATA_PER_CHANNEL ee_dataPerChannel11g[NUM_2_4_EEPROM_CHANNELS];
+
+	/* 11b info */
+	DATA_PER_CHANNEL ee_dataPerChannel11b[NUM_2_4_EEPROM_CHANNELS];
+
+	TRGT_POWER_ALL_MODES ee_tpow;
+
+	RD_EDGES_POWER	ee_rdEdgesPower[NUM_EDGES*NUM_CTLS_MAX];
+
+	union {
+		EEPROM_POWER_EXPN_5112  eu_modePowerArray5112[3];
+		RAW_DATA_STRUCT_2413	eu_rawDataset2413[3];
+	} ee_u;
+} HAL_EEPROM;
+
+/* write-around defines */
+#define	ee_numTargetPwr_11a	ee_tpow.numTargetPwr_11a
+#define	ee_trgtPwr_11a		ee_tpow.trgtPwr_11a
+#define	ee_numTargetPwr_11g	ee_tpow.numTargetPwr_11g
+#define	ee_trgtPwr_11g		ee_tpow.trgtPwr_11g
+#define	ee_numTargetPwr_11b	ee_tpow.numTargetPwr_11b
+#define	ee_trgtPwr_11b		ee_tpow.trgtPwr_11b
+#define	ee_modePowerArray5112	ee_u.eu_modePowerArray5112
+#define	ee_rawDataset2413	ee_u.eu_rawDataset2413
+#endif /* _ATH_AH_EEPROM_V3_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_internal.h b/sys/dev/netif/ath/hal/ath_hal/ah_internal.h
new file mode 100644
index 0000000..fabfd1c
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_internal.h
@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ah_internal.h,v 1.2.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#ifndef _ATH_AH_INTERAL_H_
+#define _ATH_AH_INTERAL_H_
+/*
+ * Atheros Device Hardware Access Layer (HAL).
+ *
+ * Internal definitions.
+ */
+#define	AH_NULL	0
+#define	AH_MIN(a,b)	((a)<(b)?(a):(b))
+#define	AH_MAX(a,b)	((a)>(b)?(a):(b))
+
+#ifndef NBBY
+#define	NBBY	8			/* number of bits/byte */
+#endif
+
+#ifndef roundup
+#define	roundup(x, y)	((((x)+((y)-1))/(y))*(y))  /* to any y */
+#endif
+#ifndef howmany
+#define	howmany(x, y)	(((x)+((y)-1))/(y))
+#endif
+
+#ifndef offsetof
+#define	offsetof(type, field)	((size_t)(&((type *)0)->field))
+#endif
+
+typedef struct {
+	uint16_t	start;		/* first register */
+	uint16_t	end;		/* ending register or zero */
+} HAL_REGRANGE;
+
+/*
+ * Transmit power scale factor.
+ *
+ * NB: This is not public because we want to discourage the use of
+ *     scaling; folks should use the tx power limit interface.
+ */
+typedef enum {
+	HAL_TP_SCALE_MAX	= 0,		/* no scaling (default) */
+	HAL_TP_SCALE_50		= 1,		/* 50% of max (-3 dBm) */
+	HAL_TP_SCALE_25		= 2,		/* 25% of max (-6 dBm) */
+	HAL_TP_SCALE_12		= 3,		/* 12% of max (-9 dBm) */
+	HAL_TP_SCALE_MIN	= 4,		/* min, but still on */
+} HAL_TP_SCALE;
+
+typedef enum {
+ 	HAL_CAP_RADAR		= 0,		/* Radar capability */
+ 	HAL_CAP_AR		= 1,		/* AR capability */
+} HAL_PHYDIAG_CAPS;
+
+/*
+ * Each chip or class of chips registers to offer support.
+ */
+struct ath_hal_chip {
+	const char	*name;
+	const char	*(*probe)(uint16_t vendorid, uint16_t devid);
+	struct ath_hal	*(*attach)(uint16_t devid, HAL_SOFTC,
+			    HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error);
+};
+#ifndef AH_CHIP
+#define	AH_CHIP(_name, _probe, _attach)				\
+static struct ath_hal_chip name##_chip = {			\
+	.name		= #_name,				\
+	.probe		= _probe,				\
+	.attach		= _attach				\
+};								\
+OS_DATA_SET(ah_chips, name##_chip)
+#endif
+
+/*
+ * Each RF backend registers to offer support; this is mostly
+ * used by multi-chip 5212 solutions.  Single-chip solutions
+ * have a fixed idea about which RF to use.
+ */
+struct ath_hal_rf {
+	const char	*name;
+	HAL_BOOL	(*probe)(struct ath_hal *ah);
+	HAL_BOOL	(*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
+};
+#ifndef AH_RF
+#define	AH_RF(_name, _probe, _attach)				\
+static struct ath_hal_rf _name##_rf = {				\
+	.name		= __STRING(_name),			\
+	.probe		= _probe,				\
+	.attach		= _attach				\
+};								\
+OS_DATA_SET(ah_rfs, _name##_rf)
+#endif
+
+struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
+
+/*
+ * Internal form of a HAL_CHANNEL.  Note that the structure
+ * must be defined such that you can cast references to a
+ * HAL_CHANNEL so don't shuffle the first two members.
+ */
+typedef struct {
+	uint32_t	channelFlags;
+	uint16_t	channel;	/* NB: must be first for casting */
+	uint8_t		privFlags;
+	int8_t		maxRegTxPower;
+	int8_t		maxTxPower;
+	int8_t		minTxPower;	/* as above... */
+
+	HAL_BOOL	bssSendHere;
+	uint8_t		gainI;
+	HAL_BOOL	iqCalValid;
+	uint8_t		calValid;		/* bitmask of cal types */
+	int8_t		iCoff;
+	int8_t		qCoff;
+	int16_t		rawNoiseFloor;
+	int16_t		noiseFloorAdjust;
+	int8_t		antennaMax;
+	uint32_t	regDmnFlags;		/* Flags for channel use in reg */
+	uint32_t	conformanceTestLimit;	/* conformance test limit from reg domain */
+	uint16_t	mainSpur;		/* cached spur value for this cahnnel */
+} HAL_CHANNEL_INTERNAL;
+
+typedef struct {
+	uint32_t	halChanSpreadSupport 		: 1,
+			halSleepAfterBeaconBroken	: 1,
+			halCompressSupport		: 1,
+			halBurstSupport			: 1,
+			halFastFramesSupport		: 1,
+			halChapTuningSupport		: 1,
+			halTurboGSupport		: 1,
+			halTurboPrimeSupport		: 1,
+			halMicAesCcmSupport		: 1,
+			halMicCkipSupport		: 1,
+			halMicTkipSupport		: 1,
+			halTkipMicTxRxKeySupport	: 1,
+			halCipherAesCcmSupport		: 1,
+			halCipherCkipSupport		: 1,
+			halCipherTkipSupport		: 1,
+			halPSPollBroken			: 1,
+			halVEOLSupport			: 1,
+			halBssIdMaskSupport		: 1,
+			halMcastKeySrchSupport		: 1,
+			halTsfAddSupport		: 1,
+			halChanHalfRate			: 1,
+			halChanQuarterRate		: 1,
+			halHTSupport			: 1,
+			halRfSilentSupport		: 1,
+			halHwPhyCounterSupport		: 1,
+			halWowSupport			: 1,
+			halWowMatchPatternExact		: 1,
+			halAutoSleepSupport		: 1,
+			halFastCCSupport		: 1,
+			halBtCoexSupport		: 1;
+	uint32_t	halRxStbcSupport		: 1,
+			halTxStbcSupport		: 1,
+			halGTTSupport			: 1,
+			halCSTSupport			: 1,
+			halRifsRxSupport		: 1,
+			halRifsTxSupport		: 1,
+			halExtChanDfsSupport		: 1,
+			halForcePpmSupport		: 1,
+			halEnhancedPmSupport		: 1,
+			halMbssidAggrSupport		: 1;
+	uint32_t	halWirelessModes;
+	uint16_t	halTotalQueues;
+	uint16_t	halKeyCacheSize;
+	uint16_t	halLow5GhzChan, halHigh5GhzChan;
+	uint16_t	halLow2GhzChan, halHigh2GhzChan;
+	int		halTstampPrecision;
+	int		halRtsAggrLimit;
+	uint8_t		halTxChainMask;
+	uint8_t		halRxChainMask;
+	uint8_t		halNumGpioPins;
+	uint8_t		halNumAntCfg2GHz;
+	uint8_t		halNumAntCfg5GHz;
+} HAL_CAPABILITIES;
+
+/*
+ * The ``private area'' follows immediately after the ``public area''
+ * in the data structure returned by ath_hal_attach.  Private data are
+ * used by device-independent code such as the regulatory domain support.
+ * In general, code within the HAL should never depend on data in the
+ * public area.  Instead any public data needed internally should be
+ * shadowed here.
+ *
+ * When declaring a device-specific ath_hal data structure this structure
+ * is assumed to at the front; e.g.
+ *
+ *	struct ath_hal_5212 {
+ *		struct ath_hal_private	ah_priv;
+ *		...
+ *	};
+ *
+ * It might be better to manage the method pointers in this structure
+ * using an indirect pointer to a read-only data structure but this would
+ * disallow class-style method overriding.
+ */
+struct ath_hal_private {
+	struct ath_hal	h;			/* public area */
+
+	/* NB: all methods go first to simplify initialization */
+	HAL_BOOL	(*ah_getChannelEdges)(struct ath_hal*,
+				uint16_t channelFlags,
+				uint16_t *lowChannel, uint16_t *highChannel);
+	u_int		(*ah_getWirelessModes)(struct ath_hal*);
+	HAL_BOOL	(*ah_eepromRead)(struct ath_hal *, u_int off,
+				uint16_t *data);
+	HAL_BOOL	(*ah_eepromWrite)(struct ath_hal *, u_int off,
+				uint16_t data);
+	HAL_BOOL	(*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
+	HAL_BOOL	(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
+	uint32_t	(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
+	HAL_BOOL	(*ah_gpioSet)(struct ath_hal *,
+				uint32_t gpio, uint32_t val);
+	void		(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
+	HAL_BOOL	(*ah_getChipPowerLimits)(struct ath_hal *,
+				HAL_CHANNEL *, uint32_t);
+	int16_t		(*ah_getNfAdjust)(struct ath_hal *,
+				const HAL_CHANNEL_INTERNAL*);
+	void		(*ah_getNoiseFloor)(struct ath_hal *,
+				int16_t nfarray[]);
+
+	void		*ah_eeprom;		/* opaque EEPROM state */
+	uint16_t	ah_eeversion;		/* EEPROM version */
+	void		(*ah_eepromDetach)(struct ath_hal *);
+	HAL_STATUS	(*ah_eepromGet)(struct ath_hal *, int, void *);
+	HAL_BOOL	(*ah_eepromSet)(struct ath_hal *, int, int);
+	uint16_t	(*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
+	HAL_BOOL	(*ah_eepromDiag)(struct ath_hal *, int request,
+			    const void *args, uint32_t argsize,
+			    void **result, uint32_t *resultsize);
+
+	/*
+	 * Device revision information.
+	 */
+	uint16_t	ah_devid;		/* PCI device ID */
+	uint16_t	ah_subvendorid;		/* PCI subvendor ID */
+	uint32_t	ah_macVersion;		/* MAC version id */
+	uint16_t	ah_macRev;		/* MAC revision */
+	uint16_t	ah_phyRev;		/* PHY revision */
+	uint16_t	ah_analog5GhzRev;	/* 2GHz radio revision */
+	uint16_t	ah_analog2GhzRev;	/* 5GHz radio revision */
+
+
+	HAL_OPMODE	ah_opmode;		/* operating mode from reset */
+	HAL_CAPABILITIES ah_caps;		/* device capabilities */
+	uint32_t	ah_diagreg;		/* user-specified AR_DIAG_SW */
+	int16_t		ah_powerLimit;		/* tx power cap */
+	uint16_t	ah_maxPowerLevel;	/* calculated max tx power */
+	u_int		ah_tpScale;		/* tx power scale factor */
+	uint32_t	ah_11nCompat;		/* 11n compat controls */
+
+	/*
+	 * State for regulatory domain handling.
+	 */
+	HAL_REG_DOMAIN	ah_currentRD;		/* Current regulatory domain */
+	HAL_CTRY_CODE	ah_countryCode;		/* current country code */
+	HAL_CHANNEL_INTERNAL ah_channels[256];	/* calculated channel list */
+	u_int		ah_nchan;		/* valid channels in list */
+	HAL_CHANNEL_INTERNAL *ah_curchan;	/* current channel */
+
+	uint8_t    	ah_coverageClass;   	/* coverage class */
+	HAL_BOOL    	ah_regdomainUpdate;     /* regdomain is updated? */
+	/*
+	 * RF Silent handling; setup according to the EEPROM.
+	 */
+	uint16_t	ah_rfsilent;		/* GPIO pin + polarity */
+	HAL_BOOL	ah_rfkillEnabled;	/* enable/disable RfKill */
+	/*
+	 * Diagnostic support for discriminating HIUERR reports.
+	 */
+	uint32_t	ah_fatalState[6];	/* AR_ISR+shadow regs */
+	int		ah_rxornIsFatal;	/* how to treat HAL_INT_RXORN */
+};
+
+#define	AH_PRIVATE(_ah)	((struct ath_hal_private *)(_ah))
+
+#define	ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
+	AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
+#define	ath_hal_getWirelessModes(_ah) \
+	AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
+#define	ath_hal_eepromRead(_ah, _off, _data) \
+	AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
+#define	ath_hal_eepromWrite(_ah, _off, _data) \
+	AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
+#define	ath_hal_gpioCfgOutput(_ah, _gpio) \
+	AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio)
+#define	ath_hal_gpioCfgInput(_ah, _gpio) \
+	AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio)
+#define	ath_hal_gpioGet(_ah, _gpio) \
+	AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio)
+#define	ath_hal_gpioSet(_ah, _gpio, _val) \
+	AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val)
+#define	ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
+	AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
+#define	ath_hal_getpowerlimits(_ah, _chans, _nchan) \
+	AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan)
+#define ath_hal_getNfAdjust(_ah, _c) \
+	AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
+#define	ath_hal_getNoiseFloor(_ah, _nfArray) \
+	AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
+
+#define	ath_hal_eepromDetach(_ah) \
+	AH_PRIVATE(_ah)->ah_eepromDetach(_ah)
+#define	ath_hal_eepromGet(_ah, _param, _val) \
+	AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
+#define	ath_hal_eepromSet(_ah, _param, _val) \
+	AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
+#define	ath_hal_eepromGetFlag(_ah, _param) \
+	(AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
+#define ath_hal_getSpurChan(_ah, _ix, _is2G) \
+	AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
+#define	ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
+	AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize,  _r, _rsize)
+
+#if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_)
+/*
+ * Stuff that would naturally come from _ieee80211.h
+ */
+#define	IEEE80211_ADDR_LEN		6
+
+#define	IEEE80211_WEP_KEYLEN			5	/* 40bit */
+#define	IEEE80211_WEP_IVLEN			3	/* 24bit */
+#define	IEEE80211_WEP_KIDLEN			1	/* 1 octet */
+#define	IEEE80211_WEP_CRCLEN			4	/* CRC-32 */
+
+#define	IEEE80211_CRC_LEN			4
+
+#define	IEEE80211_MTU				1500
+#define	IEEE80211_MAX_LEN			(2300 + IEEE80211_CRC_LEN + \
+    (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
+
+enum {
+	IEEE80211_T_DS,			/* direct sequence spread spectrum */
+	IEEE80211_T_FH,			/* frequency hopping */
+	IEEE80211_T_OFDM,		/* frequency division multiplexing */
+	IEEE80211_T_TURBO,		/* high rate DS */
+	IEEE80211_T_HT,			/* HT - full GI */
+};
+#define	IEEE80211_T_CCK	IEEE80211_T_DS	/* more common nomenclatur */
+#endif /* _NET_IF_IEEE80211_H_ */
+
+/* NB: these are defined privately until XR support is announced */
+enum {
+	ATHEROS_T_XR	= IEEE80211_T_HT+1,	/* extended range */
+};
+
+#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS	0x00000001
+
+#define INIT_AIFS		2
+#define INIT_CWMIN		15
+#define INIT_CWMIN_11B		31
+#define INIT_CWMAX		1023
+#define INIT_SH_RETRY		10
+#define INIT_LG_RETRY		10
+#define INIT_SSH_RETRY		32
+#define INIT_SLG_RETRY		32
+
+typedef struct {
+	uint32_t	tqi_ver;		/* HAL TXQ verson */
+	HAL_TX_QUEUE	tqi_type;		/* hw queue type*/
+	HAL_TX_QUEUE_SUBTYPE tqi_subtype;	/* queue subtype, if applicable */
+	HAL_TX_QUEUE_FLAGS tqi_qflags;		/* queue flags */
+	uint32_t	tqi_priority;
+	uint32_t	tqi_aifs;		/* aifs */
+	uint32_t	tqi_cwmin;		/* cwMin */
+	uint32_t	tqi_cwmax;		/* cwMax */
+	uint16_t	tqi_shretry;		/* frame short retry limit */
+	uint16_t	tqi_lgretry;		/* frame long retry limit */
+	uint32_t	tqi_cbrPeriod;
+	uint32_t	tqi_cbrOverflowLimit;
+	uint32_t	tqi_burstTime;
+	uint32_t	tqi_readyTime;
+	uint32_t	tqi_physCompBuf;
+	uint32_t	tqi_intFlags;		/* flags for internal use */
+} HAL_TX_QUEUE_INFO;
+
+extern	HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
+		HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
+extern	HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
+		HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
+
+typedef enum {
+	HAL_ANI_PRESENT,			/* is ANI support present */
+	HAL_ANI_NOISE_IMMUNITY_LEVEL,		/* set level */
+	HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,	/* enable/disable */
+	HAL_ANI_CCK_WEAK_SIGNAL_THR,		/* enable/disable */
+	HAL_ANI_FIRSTEP_LEVEL,			/* set level */
+	HAL_ANI_SPUR_IMMUNITY_LEVEL,		/* set level */
+	HAL_ANI_MODE = 6,	/* 0 => manual, 1 => auto (XXX do not change) */
+	HAL_ANI_PHYERR_RESET,			/* reset phy error stats */
+} HAL_ANI_CMD;
+
+#define	HAL_SPUR_VAL_MASK		0x3FFF
+#define	HAL_SPUR_CHAN_WIDTH		87
+#define	HAL_BIN_WIDTH_BASE_100HZ	3125
+#define	HAL_BIN_WIDTH_TURBO_100HZ	6250
+#define	HAL_MAX_BINS_ALLOWED		28
+
+/*
+ * A    = 5GHZ|OFDM
+ * T    = 5GHZ|OFDM|TURBO
+ *
+ * IS_CHAN_A(T) will return TRUE.  This is probably
+ * not the default behavior we want.  We should migrate to a better mask --
+ * perhaps CHANNEL_ALL.
+ *
+ * For now, IS_CHAN_G() masks itself with CHANNEL_108G.
+ *
+ */
+
+#define	IS_CHAN_A(_c)	(((_c)->channelFlags & CHANNEL_A) == CHANNEL_A)
+#define	IS_CHAN_B(_c)	(((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
+#define	IS_CHAN_G(_c)	(((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G)
+#define	IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G)
+#define	IS_CHAN_T(_c)	(((_c)->channelFlags & CHANNEL_T) == CHANNEL_T)
+#define	IS_CHAN_PUREG(_c) \
+	(((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
+
+#define	IS_CHAN_TURBO(_c)	(((_c)->channelFlags & CHANNEL_TURBO) != 0)
+#define	IS_CHAN_CCK(_c)		(((_c)->channelFlags & CHANNEL_CCK) != 0)
+#define	IS_CHAN_OFDM(_c)	(((_c)->channelFlags & CHANNEL_OFDM) != 0)
+#define	IS_CHAN_5GHZ(_c)	(((_c)->channelFlags & CHANNEL_5GHZ) != 0)
+#define	IS_CHAN_2GHZ(_c)	(((_c)->channelFlags & CHANNEL_2GHZ) != 0)
+#define	IS_CHAN_PASSIVE(_c)	(((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
+#define	IS_CHAN_HALF_RATE(_c)	(((_c)->channelFlags & CHANNEL_HALF) != 0)
+#define	IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
+
+#define	IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
+
+#define	CHANNEL_HT40		(CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
+#define	CHANNEL_HT		(CHANNEL_HT20 | CHANNEL_HT40)
+#define	IS_CHAN_HT(_c)		(((_c)->channelFlags & CHANNEL_HT) != 0)
+#define	IS_CHAN_HT20(_c)	(((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20)
+#define	IS_CHAN_HT40(_c)	(((_c)->channelFlags & CHANNEL_HT40) != 0)
+
+/*
+ * Deduce if the host cpu has big- or litt-endian byte order.
+ */
+static __inline__ int
+isBigEndian(void)
+{
+	union {
+		int32_t i;
+		char c[4];
+	} u;
+	u.i = 1;
+	return (u.c[0] == 0);
+}
+
+/* unalligned little endian access */     
+#define LE_READ_2(p)							\
+	((uint16_t)							\
+	 ((((const uint8_t *)(p))[0]    ) | (((const uint8_t *)(p))[1]<< 8)))
+#define LE_READ_4(p)							\
+	((uint32_t)							\
+	 ((((const uint8_t *)(p))[0]    ) | (((const uint8_t *)(p))[1]<< 8) |\
+	  (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
+
+/*
+ * Register manipulation macros that expect bit field defines
+ * to follow the convention that an _S suffix is appended for
+ * a shift count, while the field mask has no suffix.
+ */
+#define	SM(_v, _f)	(((_v) << _f##_S) & (_f))
+#define	MS(_v, _f)	(((_v) & (_f)) >> _f##_S)
+#define	OS_REG_RMW_FIELD(_a, _r, _f, _v) \
+	OS_REG_WRITE(_a, _r, \
+		(OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
+#define	OS_REG_SET_BIT(_a, _r, _f) \
+	OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
+#define	OS_REG_CLR_BIT(_a, _r, _f) \
+	OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
+
+/* 
+ * Regulatory domain support.
+ */
+
+/*
+ * Return the max allowed antenna gain based on the current
+ * regulatory domain.
+ */
+extern	u_int ath_hal_getantennareduction(struct ath_hal *,
+		HAL_CHANNEL *, u_int twiceGain);
+/*
+ * Return the test group for the specific channel based on
+ * the current regulator domain.
+ */
+extern	u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *);
+/*
+ * Return whether or not a noise floor check is required
+ * based on the current regulatory domain for the specified
+ * channel.
+ */
+extern	u_int ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *);
+
+/*
+ * Map a public channel definition to the corresponding
+ * internal data structure.  This implicitly specifies
+ * whether or not the specified channel is ok to use
+ * based on the current regulatory domain constraints.
+ */
+extern	HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
+		const HAL_CHANNEL *);
+
+/* system-configurable parameters */
+extern	int ath_hal_dma_beacon_response_time;	/* in TU's */
+extern	int ath_hal_sw_beacon_response_time;	/* in TU's */
+extern	int ath_hal_additional_swba_backoff;	/* in TU's */
+
+/* wait for the register contents to have the specified value */
+extern	HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
+		uint32_t mask, uint32_t val);
+
+/* return the first n bits in val reversed */
+extern	uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
+
+/* printf interfaces */
+extern	void ath_hal_printf(struct ath_hal *, const char*, ...)
+		__printflike(2,3);
+extern	void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
+		__printflike(2, 0);
+extern	const char* ath_hal_ether_sprintf(const uint8_t *mac);
+
+/* allocate and free memory */
+extern	void *ath_hal_malloc(size_t);
+extern	void ath_hal_free(void *);
+
+/* common debugging interfaces */
+#ifdef AH_DEBUG
+#include "ah_debug.h"
+extern	int ath_hal_debug;
+extern	void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
+	__printflike(3,4);
+#else
+#define HALDEBUG(_ah, __m, _fmt, ...)
+#endif /* AH_DEBUG */
+
+/*
+ * Register logging definitions shared with ardecode.
+ */
+#include "ah_decode.h"
+
+/*
+ * Common assertion interface.  Note: it is a bad idea to generate
+ * an assertion failure for any recoverable event.  Instead catch
+ * the violation and, if possible, fix it up or recover from it; either
+ * with an error return value or a diagnostic messages.  System software
+ * does not panic unless the situation is hopeless.
+ */
+#ifdef AH_ASSERT
+extern	void ath_hal_assert_failed(const char* filename,
+		int lineno, const char* msg);
+
+#define	HALASSERT(_x) do {					\
+	if (!(_x)) {						\
+		ath_hal_assert_failed(__FILE__, __LINE__, #_x);	\
+	}							\
+} while (0)
+#else
+#define	HALASSERT(_x)
+#endif /* AH_ASSERT */
+
+/*
+ * Convert between microseconds and core system clocks.
+ */
+extern	u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
+extern	u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
+
+/*
+ * Generic get/set capability support.  Each chip overrides
+ * this routine to support chip-specific capabilities.
+ */
+extern	HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
+		HAL_CAPABILITY_TYPE type, uint32_t capability,
+		uint32_t *result);
+extern	HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
+		HAL_CAPABILITY_TYPE type, uint32_t capability,
+		uint32_t setting, HAL_STATUS *status);
+
+/*
+ * Diagnostic interface.  This is an open-ended interface that
+ * is opaque to applications.  Diagnostic programs use this to
+ * retrieve internal data structures, etc.  There is no guarantee
+ * that calling conventions for calls other than HAL_DIAG_REVS
+ * are stable between HAL releases; a diagnostic application must
+ * use the HAL revision information to deal with ABI/API differences.
+ *
+ * NB: do not renumber these, certain codes are publicly used.
+ */
+enum {
+	HAL_DIAG_REVS		= 0,	/* MAC/PHY/Radio revs */
+	HAL_DIAG_EEPROM		= 1,	/* EEPROM contents */
+	HAL_DIAG_EEPROM_EXP_11A	= 2,	/* EEPROM 5112 power exp for 11a */
+	HAL_DIAG_EEPROM_EXP_11B	= 3,	/* EEPROM 5112 power exp for 11b */
+	HAL_DIAG_EEPROM_EXP_11G	= 4,	/* EEPROM 5112 power exp for 11g */
+	HAL_DIAG_ANI_CURRENT	= 5,	/* ANI current channel state */
+	HAL_DIAG_ANI_OFDM	= 6,	/* ANI OFDM timing error stats */
+	HAL_DIAG_ANI_CCK	= 7,	/* ANI CCK timing error stats */
+	HAL_DIAG_ANI_STATS	= 8,	/* ANI statistics */
+	HAL_DIAG_RFGAIN		= 9,	/* RfGain GAIN_VALUES */
+	HAL_DIAG_RFGAIN_CURSTEP	= 10,	/* RfGain GAIN_OPTIMIZATION_STEP */
+	HAL_DIAG_PCDAC		= 11,	/* PCDAC table */
+	HAL_DIAG_TXRATES	= 12,	/* Transmit rate table */
+	HAL_DIAG_REGS		= 13,	/* Registers */
+	HAL_DIAG_ANI_CMD	= 14,	/* ANI issue command (XXX do not change!) */
+	HAL_DIAG_SETKEY		= 15,	/* Set keycache backdoor */
+	HAL_DIAG_RESETKEY	= 16,	/* Reset keycache backdoor */
+	HAL_DIAG_EEREAD		= 17,	/* Read EEPROM word */
+	HAL_DIAG_EEWRITE	= 18,	/* Write EEPROM word */
+	/* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */
+	HAL_DIAG_REGREAD        = 24,   /* Reg reads */
+	HAL_DIAG_REGWRITE       = 25,   /* Reg writes */
+	HAL_DIAG_GET_REGBASE    = 26,   /* Get register base */
+	HAL_DIAG_RDWRITE	= 27,	/* Write regulatory domain */
+	HAL_DIAG_RDREAD		= 28,	/* Get regulatory domain */
+	HAL_DIAG_FATALERR	= 29,	/* Read cached interrupt state */
+	HAL_DIAG_11NCOMPAT	= 30,	/* 11n compatibility tweaks */
+	HAL_DIAG_ANI_PARAMS	= 31,	/* ANI noise immunity parameters */
+	HAL_DIAG_CHECK_HANGS	= 32,	/* check h/w hangs */
+};
+
+enum {
+    HAL_BB_HANG_DFS		= 0x0001,
+    HAL_BB_HANG_RIFS		= 0x0002,
+    HAL_BB_HANG_RX_CLEAR	= 0x0004,
+    HAL_BB_HANG_UNKNOWN		= 0x0080,
+
+    HAL_MAC_HANG_SIG1		= 0x0100,
+    HAL_MAC_HANG_SIG2		= 0x0200,
+    HAL_MAC_HANG_UNKNOWN	= 0x8000,
+
+    HAL_BB_HANGS = HAL_BB_HANG_DFS
+		 | HAL_BB_HANG_RIFS
+		 | HAL_BB_HANG_RX_CLEAR
+		 | HAL_BB_HANG_UNKNOWN,
+    HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
+		 | HAL_MAC_HANG_SIG2
+		 | HAL_MAC_HANG_UNKNOWN,
+};
+
+/*
+ * Device revision information.
+ */
+typedef struct {
+	uint16_t	ah_devid;		/* PCI device ID */
+	uint16_t	ah_subvendorid;		/* PCI subvendor ID */
+	uint32_t	ah_macVersion;		/* MAC version id */
+	uint16_t	ah_macRev;		/* MAC revision */
+	uint16_t	ah_phyRev;		/* PHY revision */
+	uint16_t	ah_analog5GhzRev;	/* 2GHz radio revision */
+	uint16_t	ah_analog2GhzRev;	/* 5GHz radio revision */
+} HAL_REVS;
+
+/*
+ * Argument payload for HAL_DIAG_SETKEY.
+ */
+typedef struct {
+	HAL_KEYVAL	dk_keyval;
+	uint16_t	dk_keyix;	/* key index */
+	uint8_t		dk_mac[IEEE80211_ADDR_LEN];
+	int		dk_xor;		/* XOR key data */
+} HAL_DIAG_KEYVAL;
+
+/*
+ * Argument payload for HAL_DIAG_EEWRITE.
+ */
+typedef struct {
+	uint16_t	ee_off;		/* eeprom offset */
+	uint16_t	ee_data;	/* write data */
+} HAL_DIAG_EEVAL;
+
+
+typedef struct {
+	u_int offset;		/* reg offset */
+	uint32_t val;		/* reg value  */
+} HAL_DIAG_REGVAL;
+
+/*
+ * 11n compatibility tweaks.
+ */
+#define	HAL_DIAG_11N_SERVICES	0x00000003
+#define	HAL_DIAG_11N_SERVICES_S	0
+#define	HAL_DIAG_11N_TXSTOMP	0x0000000c
+#define	HAL_DIAG_11N_TXSTOMP_S	2
+
+typedef struct {
+	int		maxNoiseImmunityLevel;	/* [0..4] */
+	int		totalSizeDesired[5];
+	int		coarseHigh[5];
+	int		coarseLow[5];
+	int		firpwr[5];
+
+	int		maxSpurImmunityLevel;	/* [0..7] */
+	int		cycPwrThr1[8];
+
+	int		maxFirstepLevel;	/* [0..2] */
+	int		firstep[3];
+
+	uint32_t	ofdmTrigHigh;
+	uint32_t	ofdmTrigLow;
+	int32_t		cckTrigHigh;
+	int32_t		cckTrigLow;
+	int32_t		rssiThrLow;
+	int32_t		rssiThrHigh;
+
+	int		period;			/* update listen period */
+} HAL_ANI_PARAMS;
+
+extern	HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
+			const void *args, uint32_t argsize,
+			void **result, uint32_t *resultsize);
+
+/*
+ * Setup a h/w rate table for use.
+ */
+extern	void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
+
+/*
+ * Common routine for implementing getChanNoise api.
+ */
+extern	int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan);
+
+/*
+ * Initialization support.
+ */
+typedef struct {
+	const uint32_t	*data;
+	int		rows, cols;
+} HAL_INI_ARRAY;
+
+#define	HAL_INI_INIT(_ia, _data, _cols) do {			\
+	(_ia)->data = (const uint32_t *)(_data);		\
+	(_ia)->rows = sizeof(_data) / sizeof((_data)[0]);	\
+	(_ia)->cols = (_cols);					\
+} while (0)
+#define	HAL_INI_VAL(_ia, _r, _c) \
+	((_ia)->data[((_r)*(_ia)->cols) + (_c)])
+
+/*
+ * OS_DELAY() does a PIO READ on the PCI bus which allows
+ * other cards' DMA reads to complete in the middle of our reset.
+ */
+#define DMA_YIELD(x) do {		\
+	if ((++(x) % 64) == 0)		\
+		OS_DELAY(1);		\
+} while (0)
+
+#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do {             	\
+	int r;								\
+	for (r = 0; r < N(regArray); r++) {				\
+		OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]);	\
+		DMA_YIELD(regWr);					\
+	}								\
+} while (0)
+
+#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do {		\
+	int r;								\
+	for (r = 0; r < N(regArray); r++) {				\
+		OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]);	\
+		DMA_YIELD(regWr);					\
+	}								\
+} while (0)
+
+extern	int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+		int col, int regWr);
+extern	void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
+		int col);
+extern	int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+		const uint32_t data[], int regWr);
+
+#define	WLAN_CTRL_FRAME_SIZE	(2+2+6+4)	/* ACK+FCS */
+#endif /* _ATH_AH_INTERAL_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_regdomain.c b/sys/dev/netif/ath/hal/ath_hal/ah_regdomain.c
new file mode 100644
index 0000000..d021c28
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_regdomain.c
@@ -0,0 +1,2861 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2005-2006 Atheros Communications, Inc.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_regdomain.c,v 1.24 2008/11/27 22:29:27 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_eeprom.h"
+#include "ah_devid.h"
+
+/*
+ * XXX this code needs a audit+review
+ */
+
+/* used throughout this file... */
+#define	N(a)	(sizeof (a) / sizeof (a[0]))
+
+#define HAL_MODE_11A_TURBO	HAL_MODE_108A
+#define HAL_MODE_11G_TURBO	HAL_MODE_108G
+
+/* 10MHz is half the 11A bandwidth used to determine upper edge freq
+   of the outdoor channel */
+#define HALF_MAXCHANBW		10
+
+/* 
+ * BMLEN defines the size of the bitmask used to hold frequency
+ * band specifications.  Note this must agree with the BM macro
+ * definition that's used to setup initializers.  See also further
+ * comments below.
+ */
+#define BMLEN 2		/* 2 x 64 bits in each channel bitmask */
+typedef uint64_t chanbmask_t[BMLEN];
+
+#define	W0(_a) \
+	(((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0))
+#define	W1(_a) \
+	(((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0))
+#define BM1(_fa)	{ W0(_fa), W1(_fa) }
+#define BM2(_fa, _fb)	{ W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) }
+#define BM3(_fa, _fb, _fc) \
+	{ W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) }
+#define BM4(_fa, _fb, _fc, _fd)						\
+	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd),			\
+	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) }
+#define BM5(_fa, _fb, _fc, _fd, _fe)					\
+	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe),		\
+	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) }
+#define BM6(_fa, _fb, _fc, _fd, _fe, _ff)				\
+	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff),	\
+	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) }
+#define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg)	\
+	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) |	\
+	  W0(_fg),\
+	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) |	\
+	  W1(_fg) }
+#define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh)	\
+	{ W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) |	\
+	  W0(_fg) | W0(_fh) ,	\
+	  W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) |	\
+	  W1(_fg) | W1(_fh) }
+
+/*
+ * Country/Region Codes
+ * Numbering from ISO 3166
+ */
+enum {
+    CTRY_ALBANIA              = 8,       /* Albania */
+    CTRY_ALGERIA              = 12,      /* Algeria */
+    CTRY_ARGENTINA            = 32,      /* Argentina */
+    CTRY_ARMENIA              = 51,      /* Armenia */
+    CTRY_AUSTRALIA            = 36,      /* Australia */
+    CTRY_AUSTRIA              = 40,      /* Austria */
+    CTRY_AZERBAIJAN           = 31,      /* Azerbaijan */
+    CTRY_BAHRAIN              = 48,      /* Bahrain */
+    CTRY_BELARUS              = 112,     /* Belarus */
+    CTRY_BELGIUM              = 56,      /* Belgium */
+    CTRY_BELIZE               = 84,      /* Belize */
+    CTRY_BOLIVIA              = 68,      /* Bolivia */
+    CTRY_BRAZIL               = 76,      /* Brazil */
+    CTRY_BRUNEI_DARUSSALAM    = 96,      /* Brunei Darussalam */
+    CTRY_BULGARIA             = 100,     /* Bulgaria */
+    CTRY_CANADA               = 124,     /* Canada */
+    CTRY_CHILE                = 152,     /* Chile */
+    CTRY_CHINA                = 156,     /* People's Republic of China */
+    CTRY_COLOMBIA             = 170,     /* Colombia */
+    CTRY_COSTA_RICA           = 188,     /* Costa Rica */
+    CTRY_CROATIA              = 191,     /* Croatia */
+    CTRY_CYPRUS               = 196,
+    CTRY_CZECH                = 203,     /* Czech Republic */
+    CTRY_DENMARK              = 208,     /* Denmark */
+    CTRY_DOMINICAN_REPUBLIC   = 214,     /* Dominican Republic */
+    CTRY_ECUADOR              = 218,     /* Ecuador */
+    CTRY_EGYPT                = 818,     /* Egypt */
+    CTRY_EL_SALVADOR          = 222,     /* El Salvador */
+    CTRY_ESTONIA              = 233,     /* Estonia */
+    CTRY_FAEROE_ISLANDS       = 234,     /* Faeroe Islands */
+    CTRY_FINLAND              = 246,     /* Finland */
+    CTRY_FRANCE               = 250,     /* France */
+    CTRY_FRANCE2              = 255,     /* France2 */
+    CTRY_GEORGIA              = 268,     /* Georgia */
+    CTRY_GERMANY              = 276,     /* Germany */
+    CTRY_GREECE               = 300,     /* Greece */
+    CTRY_GUATEMALA            = 320,     /* Guatemala */
+    CTRY_HONDURAS             = 340,     /* Honduras */
+    CTRY_HONG_KONG            = 344,     /* Hong Kong S.A.R., P.R.C. */
+    CTRY_HUNGARY              = 348,     /* Hungary */
+    CTRY_ICELAND              = 352,     /* Iceland */
+    CTRY_INDIA                = 356,     /* India */
+    CTRY_INDONESIA            = 360,     /* Indonesia */
+    CTRY_IRAN                 = 364,     /* Iran */
+    CTRY_IRAQ                 = 368,     /* Iraq */
+    CTRY_IRELAND              = 372,     /* Ireland */
+    CTRY_ISRAEL               = 376,     /* Israel */
+    CTRY_ITALY                = 380,     /* Italy */
+    CTRY_JAMAICA              = 388,     /* Jamaica */
+    CTRY_JAPAN                = 392,     /* Japan */
+    CTRY_JAPAN1               = 393,     /* Japan (JP1) */
+    CTRY_JAPAN2               = 394,     /* Japan (JP0) */
+    CTRY_JAPAN3               = 395,     /* Japan (JP1-1) */
+    CTRY_JAPAN4               = 396,     /* Japan (JE1) */
+    CTRY_JAPAN5               = 397,     /* Japan (JE2) */
+    CTRY_JAPAN6               = 399,     /* Japan (JP6) */
+
+    CTRY_JAPAN7		      = 4007,	 /* Japan (J7) */
+    CTRY_JAPAN8		      = 4008,	 /* Japan (J8) */
+    CTRY_JAPAN9		      = 4009,	 /* Japan (J9) */
+
+    CTRY_JAPAN10	      = 4010,	 /* Japan (J10) */
+    CTRY_JAPAN11	      = 4011,	 /* Japan (J11) */
+    CTRY_JAPAN12	      = 4012,	 /* Japan (J12) */
+
+    CTRY_JAPAN13	      = 4013,	 /* Japan (J13) */
+    CTRY_JAPAN14	      = 4014,	 /* Japan (J14) */
+    CTRY_JAPAN15	      = 4015,	 /* Japan (J15) */
+
+    CTRY_JAPAN16	      = 4016,	 /* Japan (J16) */
+    CTRY_JAPAN17	      = 4017,	 /* Japan (J17) */
+    CTRY_JAPAN18	      = 4018,	 /* Japan (J18) */
+
+    CTRY_JAPAN19	      = 4019,	 /* Japan (J19) */
+    CTRY_JAPAN20	      = 4020,	 /* Japan (J20) */
+    CTRY_JAPAN21	      = 4021,	 /* Japan (J21) */
+
+    CTRY_JAPAN22	      = 4022,	 /* Japan (J22) */
+    CTRY_JAPAN23	      = 4023,	 /* Japan (J23) */
+    CTRY_JAPAN24	      = 4024,	 /* Japan (J24) */
+ 
+    CTRY_JORDAN               = 400,     /* Jordan */
+    CTRY_KAZAKHSTAN           = 398,     /* Kazakhstan */
+    CTRY_KENYA                = 404,     /* Kenya */
+    CTRY_KOREA_NORTH          = 408,     /* North Korea */
+    CTRY_KOREA_ROC            = 410,     /* South Korea */
+    CTRY_KOREA_ROC2           = 411,     /* South Korea */
+    CTRY_KOREA_ROC3           = 412,     /* South Korea */
+    CTRY_KUWAIT               = 414,     /* Kuwait */
+    CTRY_LATVIA               = 428,     /* Latvia */
+    CTRY_LEBANON              = 422,     /* Lebanon */
+    CTRY_LIBYA                = 434,     /* Libya */
+    CTRY_LIECHTENSTEIN        = 438,     /* Liechtenstein */
+    CTRY_LITHUANIA            = 440,     /* Lithuania */
+    CTRY_LUXEMBOURG           = 442,     /* Luxembourg */
+    CTRY_MACAU                = 446,     /* Macau */
+    CTRY_MACEDONIA            = 807,     /* the Former Yugoslav Republic of Macedonia */
+    CTRY_MALAYSIA             = 458,     /* Malaysia */
+    CTRY_MALTA		      = 470,	 /* Malta */
+    CTRY_MEXICO               = 484,     /* Mexico */
+    CTRY_MONACO               = 492,     /* Principality of Monaco */
+    CTRY_MOROCCO              = 504,     /* Morocco */
+    CTRY_NETHERLANDS          = 528,     /* Netherlands */
+    CTRY_NEW_ZEALAND          = 554,     /* New Zealand */
+    CTRY_NICARAGUA            = 558,     /* Nicaragua */
+    CTRY_NORWAY               = 578,     /* Norway */
+    CTRY_OMAN                 = 512,     /* Oman */
+    CTRY_PAKISTAN             = 586,     /* Islamic Republic of Pakistan */
+    CTRY_PANAMA               = 591,     /* Panama */
+    CTRY_PARAGUAY             = 600,     /* Paraguay */
+    CTRY_PERU                 = 604,     /* Peru */
+    CTRY_PHILIPPINES          = 608,     /* Republic of the Philippines */
+    CTRY_POLAND               = 616,     /* Poland */
+    CTRY_PORTUGAL             = 620,     /* Portugal */
+    CTRY_PUERTO_RICO          = 630,     /* Puerto Rico */
+    CTRY_QATAR                = 634,     /* Qatar */
+    CTRY_ROMANIA              = 642,     /* Romania */
+    CTRY_RUSSIA               = 643,     /* Russia */
+    CTRY_SAUDI_ARABIA         = 682,     /* Saudi Arabia */
+    CTRY_SINGAPORE            = 702,     /* Singapore */
+    CTRY_SLOVAKIA             = 703,     /* Slovak Republic */
+    CTRY_SLOVENIA             = 705,     /* Slovenia */
+    CTRY_SOUTH_AFRICA         = 710,     /* South Africa */
+    CTRY_SPAIN                = 724,     /* Spain */
+    CTRY_SR9                  = 5000,    /* Ubiquiti SR9 (900MHz/GSM) */
+    CTRY_SWEDEN               = 752,     /* Sweden */
+    CTRY_SWITZERLAND          = 756,     /* Switzerland */
+    CTRY_SYRIA                = 760,     /* Syria */
+    CTRY_TAIWAN               = 158,     /* Taiwan */
+    CTRY_THAILAND             = 764,     /* Thailand */
+    CTRY_TRINIDAD_Y_TOBAGO    = 780,     /* Trinidad y Tobago */
+    CTRY_TUNISIA              = 788,     /* Tunisia */
+    CTRY_TURKEY               = 792,     /* Turkey */
+    CTRY_UAE                  = 784,     /* U.A.E. */
+    CTRY_UKRAINE              = 804,     /* Ukraine */
+    CTRY_UNITED_KINGDOM       = 826,     /* United Kingdom */
+    CTRY_UNITED_STATES        = 840,     /* United States */
+    CTRY_UNITED_STATES_FCC49  = 842,     /* United States (Public Safety)*/
+    CTRY_URUGUAY              = 858,     /* Uruguay */
+    CTRY_UZBEKISTAN           = 860,     /* Uzbekistan */
+    CTRY_VENEZUELA            = 862,     /* Venezuela */
+    CTRY_VIET_NAM             = 704,     /* Viet Nam */
+    CTRY_XR9                  = 5001,    /* Ubiquiti XR9 (900MHz/GSM) */
+    CTRY_GZ901                = 5002,    /* Zcomax GZ-901 (900MHz/GSM) */
+    CTRY_YEMEN                = 887,     /* Yemen */
+    CTRY_ZIMBABWE             = 716      /* Zimbabwe */
+};
+
+
+/*
+ * Mask to check whether a domain is a multidomain or a single domain
+ */
+#define MULTI_DOMAIN_MASK 0xFF00
+
+/*
+ * Enumerated Regulatory Domain Information 8 bit values indicate that
+ * the regdomain is really a pair of unitary regdomains.  12 bit values
+ * are the real unitary regdomains and are the only ones which have the
+ * frequency bitmasks and flags set.
+ */
+enum {
+	/*
+	 * The following regulatory domain definitions are
+	 * found in the EEPROM. Each regulatory domain
+	 * can operate in either a 5GHz or 2.4GHz wireless mode or
+	 * both 5GHz and 2.4GHz wireless modes.
+	 * In general, the value holds no special
+	 * meaning and is used to decode into either specific
+	 * 2.4GHz or 5GHz wireless mode for that particular
+	 * regulatory domain.
+	 */
+	NO_ENUMRD	= 0x00,
+	NULL1_WORLD	= 0x03,		/* For 11b-only countries (no 11a allowed) */
+	NULL1_ETSIB	= 0x07,		/* Israel */
+	NULL1_ETSIC	= 0x08,
+	FCC1_FCCA	= 0x10,		/* USA */
+	FCC1_WORLD	= 0x11,		/* Hong Kong */
+	FCC4_FCCA	= 0x12,		/* USA - Public Safety */
+	FCC5_FCCB	= 0x13,		/* USA w/ 1/2 and 1/4 width channels */
+
+	FCC2_FCCA	= 0x20,		/* Canada */
+	FCC2_WORLD	= 0x21,		/* Australia & HK */
+	FCC2_ETSIC	= 0x22,
+	FRANCE_RES	= 0x31,		/* Legacy France for OEM */
+	FCC3_FCCA	= 0x3A,		/* USA & Canada w/5470 band, 11h, DFS enabled */
+	FCC3_WORLD	= 0x3B,		/* USA & Canada w/5470 band, 11h, DFS enabled */
+
+	ETSI1_WORLD	= 0x37,
+	ETSI3_ETSIA	= 0x32,		/* France (optional) */
+	ETSI2_WORLD	= 0x35,		/* Hungary & others */
+	ETSI3_WORLD	= 0x36,		/* France & others */
+	ETSI4_WORLD	= 0x30,
+	ETSI4_ETSIC	= 0x38,
+	ETSI5_WORLD	= 0x39,
+	ETSI6_WORLD	= 0x34,		/* Bulgaria */
+	ETSI_RESERVED	= 0x33,		/* Reserved (Do not used) */
+
+	MKK1_MKKA	= 0x40,		/* Japan (JP1) */
+	MKK1_MKKB	= 0x41,		/* Japan (JP0) */
+	APL4_WORLD	= 0x42,		/* Singapore */
+	MKK2_MKKA	= 0x43,		/* Japan with 4.9G channels */
+	APL_RESERVED	= 0x44,		/* Reserved (Do not used)  */
+	APL2_WORLD	= 0x45,		/* Korea */
+	APL2_APLC	= 0x46,
+	APL3_WORLD	= 0x47,
+	MKK1_FCCA	= 0x48,		/* Japan (JP1-1) */
+	APL2_APLD	= 0x49,		/* Korea with 2.3G channels */
+	MKK1_MKKA1	= 0x4A,		/* Japan (JE1) */
+	MKK1_MKKA2	= 0x4B,		/* Japan (JE2) */
+	MKK1_MKKC	= 0x4C,		/* Japan (MKK1_MKKA,except Ch14) */
+
+	APL3_FCCA       = 0x50,
+	APL1_WORLD	= 0x52,		/* Latin America */
+	APL1_FCCA	= 0x53,
+	APL1_APLA	= 0x54,
+	APL1_ETSIC	= 0x55,
+	APL2_ETSIC	= 0x56,		/* Venezuela */
+	APL5_WORLD	= 0x58,		/* Chile */
+	APL6_WORLD	= 0x5B,		/* Singapore */
+	APL7_FCCA   = 0x5C,     /* Taiwan 5.47 Band */
+	APL8_WORLD  = 0x5D,     /* Malaysia 5GHz */
+	APL9_WORLD  = 0x5E,     /* Korea 5GHz */
+
+	/*
+	 * World mode SKUs
+	 */
+	WOR0_WORLD	= 0x60,		/* World0 (WO0 SKU) */
+	WOR1_WORLD	= 0x61,		/* World1 (WO1 SKU) */
+	WOR2_WORLD	= 0x62,		/* World2 (WO2 SKU) */
+	WOR3_WORLD	= 0x63,		/* World3 (WO3 SKU) */
+	WOR4_WORLD	= 0x64,		/* World4 (WO4 SKU) */	
+	WOR5_ETSIC	= 0x65,		/* World5 (WO5 SKU) */    
+
+	WOR01_WORLD	= 0x66,		/* World0-1 (WW0-1 SKU) */
+	WOR02_WORLD	= 0x67,		/* World0-2 (WW0-2 SKU) */
+	EU1_WORLD	= 0x68,		/* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */
+
+	WOR9_WORLD	= 0x69,		/* World9 (WO9 SKU) */	
+	WORA_WORLD	= 0x6A,		/* WorldA (WOA SKU) */	
+
+	MKK3_MKKB	= 0x80,		/* Japan UNI-1 even + MKKB */
+	MKK3_MKKA2	= 0x81,		/* Japan UNI-1 even + MKKA2 */
+	MKK3_MKKC	= 0x82,		/* Japan UNI-1 even + MKKC */
+
+	MKK4_MKKB	= 0x83,		/* Japan UNI-1 even + UNI-2 + MKKB */
+	MKK4_MKKA2	= 0x84,		/* Japan UNI-1 even + UNI-2 + MKKA2 */
+	MKK4_MKKC	= 0x85,		/* Japan UNI-1 even + UNI-2 + MKKC */
+
+	MKK5_MKKB	= 0x86,		/* Japan UNI-1 even + UNI-2 + mid-band + MKKB */
+	MKK5_MKKA2	= 0x87,		/* Japan UNI-1 even + UNI-2 + mid-band + MKKA2 */
+	MKK5_MKKC	= 0x88,		/* Japan UNI-1 even + UNI-2 + mid-band + MKKC */
+
+	MKK6_MKKB	= 0x89,		/* Japan UNI-1 even + UNI-1 odd MKKB */
+	MKK6_MKKA2	= 0x8A,		/* Japan UNI-1 even + UNI-1 odd + MKKA2 */
+	MKK6_MKKC	= 0x8B,		/* Japan UNI-1 even + UNI-1 odd + MKKC */
+
+	MKK7_MKKB	= 0x8C,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKB */
+	MKK7_MKKA2	= 0x8D,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA2 */
+	MKK7_MKKC	= 0x8E,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKC */
+
+	MKK8_MKKB	= 0x8F,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKB */
+	MKK8_MKKA2	= 0x90,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKA2 */
+	MKK8_MKKC	= 0x91,		/* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKC */
+
+	/* Following definitions are used only by s/w to map old
+ 	 * Japan SKUs.
+	 */
+	MKK3_MKKA       = 0xF0,         /* Japan UNI-1 even + MKKA */
+	MKK3_MKKA1      = 0xF1,         /* Japan UNI-1 even + MKKA1 */
+	MKK3_FCCA       = 0xF2,         /* Japan UNI-1 even + FCCA */
+	MKK4_MKKA       = 0xF3,         /* Japan UNI-1 even + UNI-2 + MKKA */
+	MKK4_MKKA1      = 0xF4,         /* Japan UNI-1 even + UNI-2 + MKKA1 */
+	MKK4_FCCA       = 0xF5,         /* Japan UNI-1 even + UNI-2 + FCCA */
+	MKK9_MKKA       = 0xF6,         /* Japan UNI-1 even + 4.9GHz */
+	MKK10_MKKA      = 0xF7,         /* Japan UNI-1 even + UNI-2 + 4.9GHz */
+
+	/*
+	 * Regulator domains ending in a number (e.g. APL1,
+	 * MK1, ETSI4, etc) apply to 5GHz channel and power
+	 * information.  Regulator domains ending in a letter
+	 * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and
+	 * power information.
+	 */
+	APL1		= 0x0150,	/* LAT & Asia */
+	APL2		= 0x0250,	/* LAT & Asia */
+	APL3		= 0x0350,	/* Taiwan */
+	APL4		= 0x0450,	/* Jordan */
+	APL5		= 0x0550,	/* Chile */
+	APL6		= 0x0650,	/* Singapore */
+	APL8		= 0x0850,	/* Malaysia */
+	APL9		= 0x0950,	/* Korea (South) ROC 3 */
+
+	ETSI1		= 0x0130,	/* Europe & others */
+	ETSI2		= 0x0230,	/* Europe & others */
+	ETSI3		= 0x0330,	/* Europe & others */
+	ETSI4		= 0x0430,	/* Europe & others */
+	ETSI5		= 0x0530,	/* Europe & others */
+	ETSI6		= 0x0630,	/* Europe & others */
+	ETSIA		= 0x0A30,	/* France */
+	ETSIB		= 0x0B30,	/* Israel */
+	ETSIC		= 0x0C30,	/* Latin America */
+
+	FCC1		= 0x0110,	/* US & others */
+	FCC2		= 0x0120,	/* Canada, Australia & New Zealand */
+	FCC3		= 0x0160,	/* US w/new middle band & DFS */    
+	FCC4          	= 0x0165,     	/* US Public Safety */
+	FCC5          	= 0x0166,     	/* US w/ 1/2 and 1/4 width channels */
+	FCCA		= 0x0A10,	 
+	FCCB		= 0x0A11,	/* US w/ 1/2 and 1/4 width channels */
+
+	APLD		= 0x0D50,	/* South Korea */
+
+	MKK1		= 0x0140,	/* Japan (UNI-1 odd)*/
+	MKK2		= 0x0240,	/* Japan (4.9 GHz + UNI-1 odd) */
+	MKK3		= 0x0340,	/* Japan (UNI-1 even) */
+	MKK4		= 0x0440,	/* Japan (UNI-1 even + UNI-2) */
+	MKK5		= 0x0540,	/* Japan (UNI-1 even + UNI-2 + mid-band) */
+	MKK6		= 0x0640,	/* Japan (UNI-1 odd + UNI-1 even) */
+	MKK7		= 0x0740,	/* Japan (UNI-1 odd + UNI-1 even + UNI-2 */
+	MKK8		= 0x0840,	/* Japan (UNI-1 odd + UNI-1 even + UNI-2 + mid-band) */
+	MKK9            = 0x0940,       /* Japan (UNI-1 even + 4.9 GHZ) */
+	MKK10           = 0x0B40,       /* Japan (UNI-1 even + UNI-2 + 4.9 GHZ) */
+	MKKA		= 0x0A40,	/* Japan */
+	MKKC		= 0x0A50,
+
+	NULL1		= 0x0198,
+	WORLD		= 0x0199,
+	SR9_WORLD	= 0x0298,
+	XR9_WORLD	= 0x0299,
+	GZ901_WORLD	= 0x029a,
+	DEBUG_REG_DMN	= 0x01ff,
+};
+
+#define	WORLD_SKU_MASK		0x00F0
+#define	WORLD_SKU_PREFIX	0x0060
+
+enum {					/* conformance test limits */
+	FCC	= 0x10,
+	MKK	= 0x40,
+	ETSI	= 0x30,
+};
+
+/*
+ * The following are flags for different requirements per reg domain.
+ * These requirements are either inhereted from the reg domain pair or
+ * from the unitary reg domain if the reg domain pair flags value is 0
+ */
+enum {
+	NO_REQ			= 0x00000000,	/* NB: must be zero */
+	DISALLOW_ADHOC_11A	= 0x00000001,
+	DISALLOW_ADHOC_11A_TURB	= 0x00000002,
+	NEED_NFC		= 0x00000004,
+	ADHOC_PER_11D		= 0x00000008,  /* Start Ad-Hoc mode */
+	ADHOC_NO_11A		= 0x00000010,
+	LIMIT_FRAME_4MS 	= 0x00000020, 	/* 4msec limit on frame length*/
+	NO_HOSTAP		= 0x00000040,	/* No HOSTAP mode opereation */
+};
+
+/*
+ * The following describe the bit masks for different passive scan
+ * capability/requirements per regdomain.
+ */
+#define	NO_PSCAN	0x0ULL			/* NB: must be zero */
+#define	PSCAN_FCC	0x0000000000000001ULL
+#define	PSCAN_FCC_T	0x0000000000000002ULL
+#define	PSCAN_ETSI	0x0000000000000004ULL
+#define	PSCAN_MKK1	0x0000000000000008ULL
+#define	PSCAN_MKK2	0x0000000000000010ULL
+#define	PSCAN_MKKA	0x0000000000000020ULL
+#define	PSCAN_MKKA_G	0x0000000000000040ULL
+#define	PSCAN_ETSIA	0x0000000000000080ULL
+#define	PSCAN_ETSIB	0x0000000000000100ULL
+#define	PSCAN_ETSIC	0x0000000000000200ULL
+#define	PSCAN_WWR	0x0000000000000400ULL
+#define	PSCAN_MKKA1	0x0000000000000800ULL
+#define	PSCAN_MKKA1_G	0x0000000000001000ULL
+#define	PSCAN_MKKA2	0x0000000000002000ULL
+#define	PSCAN_MKKA2_G	0x0000000000004000ULL
+#define	PSCAN_MKK3	0x0000000000008000ULL
+#define	PSCAN_DEFER	0x7FFFFFFFFFFFFFFFULL
+#define	IS_ECM_CHAN	0x8000000000000000ULL
+
+/*
+ * THE following table is the mapping of regdomain pairs specified by
+ * an 8 bit regdomain value to the individual unitary reg domains
+ */
+typedef struct {
+	HAL_REG_DOMAIN regDmnEnum;	/* 16 bit reg domain pair */
+	HAL_REG_DOMAIN regDmn5GHz;	/* 5GHz reg domain */
+	HAL_REG_DOMAIN regDmn2GHz;	/* 2GHz reg domain */
+	uint32_t flags5GHz;		/* Requirements flags (AdHoc
+					   disallow, noise floor cal needed,
+					   etc) */
+	uint32_t flags2GHz;		/* Requirements flags (AdHoc
+					   disallow, noise floor cal needed,
+					   etc) */
+	uint64_t pscanMask;		/* Passive Scan flags which
+					   can override unitary domain
+					   passive scan flags.  This
+					   value is used as a mask on
+					   the unitary flags*/
+	uint16_t singleCC;		/* Country code of single country if
+					   a one-on-one mapping exists */
+}  REG_DMN_PAIR_MAPPING;
+
+static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
+	{NO_ENUMRD,	DEBUG_REG_DMN,	DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{NULL1_WORLD,	NULL1,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{NULL1_ETSIB,	NULL1,		ETSIB,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{NULL1_ETSIC,	NULL1,		ETSIC,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+
+	{FCC2_FCCA,	FCC2,		FCCA,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{FCC2_WORLD,	FCC2,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{FCC2_ETSIC,	FCC2,		ETSIC,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{FCC3_FCCA,	FCC3,		FCCA,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{FCC3_WORLD,	FCC3,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{FCC4_FCCA,	FCC4,		FCCA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{FCC5_FCCB,	FCC5,		FCCB,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+
+	{ETSI1_WORLD,	ETSI1,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{ETSI2_WORLD,	ETSI2,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{ETSI3_WORLD,	ETSI3,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{ETSI4_WORLD,	ETSI4,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{ETSI5_WORLD,	ETSI5,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{ETSI6_WORLD,	ETSI6,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+
+	{ETSI3_ETSIA,	ETSI3,		WORLD,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{FRANCE_RES,	ETSI3,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+
+	{FCC1_WORLD,	FCC1,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{FCC1_FCCA,	FCC1,		FCCA,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL1_WORLD,	APL1,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL2_WORLD,	APL2,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL3_WORLD,	APL3,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL4_WORLD,	APL4,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL5_WORLD,	APL5,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL6_WORLD,	APL6,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL8_WORLD,	APL8,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL9_WORLD,	APL9,		WORLD,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+
+	{APL3_FCCA,	APL3,		FCCA,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL1_ETSIC,	APL1,		ETSIC,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL2_ETSIC,	APL2,		ETSIC,		NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{APL2_APLD,	APL2,		APLD,		NO_REQ, NO_REQ, PSCAN_DEFER,  },
+
+	{MKK1_MKKA,	MKK1,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN },
+	{MKK1_MKKB,	MKK1,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 },
+	{MKK1_FCCA,	MKK1,		FCCA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 },
+	{MKK1_MKKA1,	MKK1,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 },
+	{MKK1_MKKA2,	MKK1,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 },
+	{MKK1_MKKC,	MKK1,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 },
+
+	/* MKK2 */
+	{MKK2_MKKA,	MKK2,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 },
+
+	/* MKK3 */
+	{MKK3_MKKA,	MKK3,	MKKA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC , PSCAN_MKKA, 0 },
+	{MKK3_MKKB,	MKK3,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 },
+	{MKK3_MKKA1,	MKK3,	MKKA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, 0 },
+	{MKK3_MKKA2,MKK3,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 },
+	{MKK3_MKKC,	MKK3,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 },
+	{MKK3_FCCA,	MKK3,	FCCA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, 0 },
+
+	/* MKK4 */
+	{MKK4_MKKB,	MKK4,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 },
+	{MKK4_MKKA1,	MKK4,	MKKA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, 0 },
+	{MKK4_MKKA2,	MKK4,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 |PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 },
+	{MKK4_MKKC,	MKK4,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 },
+	{MKK4_FCCA,	MKK4,	FCCA,	DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, 0 },
+
+	/* MKK5 */
+	{MKK5_MKKB,	MKK5,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 },
+	{MKK5_MKKA2,MKK5,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 },
+	{MKK5_MKKC,	MKK5,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 },
+
+	/* MKK6 */
+	{MKK6_MKKB,	MKK6,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 },
+	{MKK6_MKKA2,	MKK6,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 },
+	{MKK6_MKKC,	MKK6,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 },
+
+	/* MKK7 */
+	{MKK7_MKKB,	MKK7,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 },
+	{MKK7_MKKA2, MKK7,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 },
+	{MKK7_MKKC,	MKK7,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 },
+
+	/* MKK8 */
+	{MKK8_MKKB,	MKK8,		MKKA,		DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 },
+	{MKK8_MKKA2,MKK8,		MKKA,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 },
+	{MKK8_MKKC,	MKK8,		MKKC,		DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 },
+
+	{MKK9_MKKA,	MKK9,	MKKA,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 0 },
+	{MKK10_MKKA,	MKK10,	MKKA,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, 0 },
+
+		/* These are super domains */
+	{WOR0_WORLD,	WOR0_WORLD,	WOR0_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{WOR1_WORLD,	WOR1_WORLD,	WOR1_WORLD,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{WOR2_WORLD,	WOR2_WORLD,	WOR2_WORLD,	DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{WOR3_WORLD,	WOR3_WORLD,	WOR3_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{WOR4_WORLD,	WOR4_WORLD,	WOR4_WORLD,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{WOR5_ETSIC,	WOR5_ETSIC,	WOR5_ETSIC,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{WOR01_WORLD,	WOR01_WORLD,	WOR01_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{WOR02_WORLD,	WOR02_WORLD,	WOR02_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{EU1_WORLD,	EU1_WORLD,	EU1_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
+	{WOR9_WORLD,	WOR9_WORLD,	WOR9_WORLD,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{WORA_WORLD,	WORA_WORLD,	WORA_WORLD,	DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
+	{SR9_WORLD,	NULL1,		SR9_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_SR9 },
+	{XR9_WORLD,	NULL1,		XR9_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_XR9 },
+	{GZ901_WORLD,	NULL1,		GZ901_WORLD,	NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_GZ901 },
+};
+
+/* 
+ * The following tables are the master list for all different freqeuncy
+ * bands with the complete matrix of all possible flags and settings
+ * for each band if it is used in ANY reg domain.
+ */
+
+#define DEF_REGDMN		FCC1_FCCA
+#define	DEF_DMN_5		FCC1
+#define	DEF_DMN_2		FCCA
+#define	COUNTRY_ERD_FLAG        0x8000
+#define WORLDWIDE_ROAMING_FLAG  0x4000
+#define	SUPER_DOMAIN_MASK	0x0fff
+#define	COUNTRY_CODE_MASK	0x3fff
+
+#define	YES	AH_TRUE
+#define	NO	AH_FALSE
+
+typedef struct {
+	HAL_CTRY_CODE		countryCode;	   
+	HAL_REG_DOMAIN		regDmnEnum;
+	HAL_BOOL		allow11g;
+	HAL_BOOL		allow11aTurbo;
+	HAL_BOOL		allow11gTurbo;
+	HAL_BOOL		allow11ng20;
+	HAL_BOOL		allow11ng40;
+	HAL_BOOL		allow11na20;
+	HAL_BOOL		allow11na40;
+	uint16_t		outdoorChanStart;
+} COUNTRY_CODE_TO_ENUM_RD;
+
+static COUNTRY_CODE_TO_ENUM_RD allCountries[] = {
+    {CTRY_DEBUG,       NO_ENUMRD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_DEFAULT,     DEF_REGDMN,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_ALBANIA,     NULL1_WORLD,	YES,  NO, YES, YES, NO,  NO, NO, 7000 },
+    {CTRY_ALGERIA,     NULL1_WORLD,	YES,  NO, YES, YES, NO,  NO, NO, 7000 },
+    {CTRY_ARGENTINA,   APL3_WORLD,	 NO,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_ARMENIA,     ETSI4_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_AUSTRALIA,   FCC2_WORLD,      YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_AUSTRIA,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_AZERBAIJAN,  ETSI4_WORLD,     YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_BAHRAIN,     APL6_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_BELARUS,     NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_BELGIUM,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_BELIZE,      APL1_ETSIC,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_BOLIVIA,     APL1_ETSIC,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_BRAZIL,      FCC3_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
+    {CTRY_BRUNEI_DARUSSALAM,APL1_WORLD, YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_BULGARIA,    ETSI6_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_CANADA,      FCC2_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_CHILE,       APL6_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_CHINA,       APL1_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_COLOMBIA,    FCC1_FCCA,       YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_COSTA_RICA,  NULL1_WORLD,     YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_CROATIA,     ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_CYPRUS,      ETSI1_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_CZECH,       ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_DENMARK,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_ECUADOR,     NULL1_WORLD,	NO,   NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_EGYPT,       ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_EL_SALVADOR, NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_ESTONIA,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_FINLAND,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_FRANCE,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_FRANCE2,     ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_GEORGIA,     ETSI4_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_GERMANY,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_GREECE,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_GUATEMALA,   FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_GZ901,       GZ901_WORLD,     YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_HONDURAS,    NULL1_WORLD,	YES, NO,  YES, YES,YES, YES, NO, 7000 },
+    {CTRY_HONG_KONG,   FCC2_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_HUNGARY,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_ICELAND,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_INDIA,       APL6_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_INDONESIA,   APL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_IRAN,        APL1_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_IRELAND,     ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_ISRAEL,      NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_ITALY,       ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_JAPAN,       MKK1_MKKA,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
+    {CTRY_JAPAN1,      MKK1_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN2,      MKK1_FCCA,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN3,      MKK2_MKKA,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN4,      MKK1_MKKA1,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN5,      MKK1_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN6,      MKK1_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+
+    {CTRY_JAPAN7,      MKK3_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN8,      MKK3_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN9,      MKK3_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+
+    {CTRY_JAPAN10,     MKK4_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN11,     MKK4_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN12,     MKK4_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+
+    {CTRY_JAPAN13,     MKK5_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN14,     MKK5_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN15,     MKK5_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+
+    {CTRY_JAPAN16,     MKK6_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN17,     MKK6_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN18,     MKK6_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+
+    {CTRY_JAPAN19,     MKK7_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN20,     MKK7_MKKA2,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
+    {CTRY_JAPAN21,     MKK7_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+
+    {CTRY_JAPAN22,     MKK8_MKKB,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN23,     MKK8_MKKA2,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_JAPAN24,     MKK8_MKKC,	YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+
+    {CTRY_JORDAN,      APL4_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_KAZAKHSTAN,  NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_KOREA_NORTH, APL2_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_KOREA_ROC,   APL2_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
+    {CTRY_KOREA_ROC2,  APL2_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
+    {CTRY_KOREA_ROC3,  APL9_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
+    {CTRY_KUWAIT,      NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_LATVIA,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_LEBANON,     NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_LIECHTENSTEIN,ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_LITHUANIA,   ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_LUXEMBOURG,  ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_MACAU,       FCC2_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_MACEDONIA,   NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_MALAYSIA,    APL8_WORLD,	YES,  NO,  NO, YES, NO, YES, NO, 7000 },
+    {CTRY_MALTA,       ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_MEXICO,      FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_MONACO,      ETSI4_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_MOROCCO,     NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_NETHERLANDS, ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_NEW_ZEALAND, FCC2_ETSIC,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_NORWAY,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_OMAN,        APL6_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_PAKISTAN,    NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_PANAMA,      FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_PERU,        APL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_PHILIPPINES, FCC3_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_POLAND,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_PORTUGAL,    ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_PUERTO_RICO, FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_QATAR,       NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_ROMANIA,     NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_RUSSIA,      NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_SAUDI_ARABIA,FCC2_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_SINGAPORE,   APL6_WORLD,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_SLOVAKIA,    ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_SLOVENIA,    ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_SOUTH_AFRICA,FCC3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_SPAIN,       ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_SR9,         SR9_WORLD,       YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_SWEDEN,      ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_SWITZERLAND, ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_SYRIA,       NULL1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_TAIWAN,      APL3_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_THAILAND,    NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD,YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_TUNISIA,     ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_TURKEY,      ETSI3_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_UKRAINE,     NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_UAE,         NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_UNITED_KINGDOM, ETSI1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_UNITED_STATES, FCC1_FCCA,	YES, YES, YES, YES,YES, YES,YES, 5825 },
+    {CTRY_UNITED_STATES_FCC49,FCC4_FCCA,YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_URUGUAY,     FCC1_WORLD,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_UZBEKISTAN,  FCC3_FCCA,	YES, YES, YES, YES,YES, YES,YES, 7000 },
+    {CTRY_VENEZUELA,   APL2_ETSIC,	YES,  NO, YES, YES,YES, YES, NO, 7000 },
+    {CTRY_VIET_NAM,    NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_XR9,         XR9_WORLD,       YES,  NO,  NO,  NO, NO,  NO, NO, 7000 },
+    {CTRY_YEMEN,       NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 },
+    {CTRY_ZIMBABWE,    NULL1_WORLD,	YES,  NO, YES, YES,YES,  NO, NO, 7000 }
+};
+
+/* Bit masks for DFS per regdomain */
+enum {
+	NO_DFS   = 0x0000000000000000ULL,	/* NB: must be zero */
+	DFS_FCC3 = 0x0000000000000001ULL,
+	DFS_ETSI = 0x0000000000000002ULL,
+	DFS_MKK4 = 0x0000000000000004ULL,
+};
+
+#define	AFTER(x)	((x)+1)
+
+/*
+ * Frequency band collections are defined using bitmasks.  Each bit
+ * in a mask is the index of an entry in one of the following tables.
+ * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit
+ * vectors must be enlarged or the tables split somehow (e.g. split
+ * 1/2 and 1/4 rate channels into a separate table).
+ *
+ * Beware of ordering; the indices are defined relative to the preceding
+ * entry so if things get off there will be confusion.  A good way to
+ * check the indices is to collect them in a switch statement in a stub
+ * function so the compiler checks for duplicates.
+ */
+
+typedef struct {
+	uint16_t	lowChannel;	/* Low channel center in MHz */
+	uint16_t	highChannel;	/* High Channel center in MHz */
+	uint8_t		powerDfs;	/* Max power (dBm) for channel
+					   range when using DFS */
+	uint8_t		antennaMax;	/* Max allowed antenna gain */
+	uint8_t		channelBW;	/* Bandwidth of the channel */
+	uint8_t		channelSep;	/* Channel separation within
+					   the band */
+	uint64_t	useDfs;		/* Use DFS in the RegDomain
+					   if corresponding bit is set */
+	uint64_t	usePassScan;	/* Use Passive Scan in the RegDomain
+					   if corresponding bit is set */
+	uint8_t		regClassId;	/* Regulatory class id */
+} REG_DMN_FREQ_BAND;
+
+/*
+ * 5GHz 11A channel tags
+ */
+static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
+	{ 4915, 4925, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2, 16 },
+#define	F1_4915_4925	0
+	{ 4935, 4945, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2, 16 },
+#define	F1_4935_4945	AFTER(F1_4915_4925)
+	{ 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7 },
+#define	F1_4920_4980	AFTER(F1_4935_4945)
+	{ 4942, 4987, 27, 6,  5,  5, NO_DFS, PSCAN_FCC, 0 },
+#define	F1_4942_4987	AFTER(F1_4920_4980)
+	{ 4945, 4985, 30, 6, 10,  5, NO_DFS, PSCAN_FCC, 0 },
+#define	F1_4945_4985	AFTER(F1_4942_4987)
+	{ 4950, 4980, 33, 6, 20,  5, NO_DFS, PSCAN_FCC, 0 },
+#define	F1_4950_4980	AFTER(F1_4945_4985)
+	{ 5035, 5040, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2, 12 },
+#define	F1_5035_5040	AFTER(F1_4950_4980)
+	{ 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2 },
+#define	F1_5040_5080	AFTER(F1_5035_5040)
+	{ 5055, 5055, 23, 0, 10,  5, NO_DFS, PSCAN_MKK2, 12 },
+#define	F1_5055_5055	AFTER(F1_5040_5080)
+
+	{ 5120, 5240, 5,  6, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F1_5120_5240	AFTER(F1_5055_5055)
+	{ 5120, 5240, 5,  6, 10, 10, NO_DFS, NO_PSCAN, 0 },
+#define	F2_5120_5240	AFTER(F1_5120_5240)
+	{ 5120, 5240, 5,  6,  5,  5, NO_DFS, NO_PSCAN, 0 },
+#define	F3_5120_5240	AFTER(F2_5120_5240)
+
+	{ 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1 },
+#define	F1_5170_5230	AFTER(F3_5120_5240)
+	{ 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1 },
+#define	F2_5170_5230	AFTER(F1_5170_5230)
+
+	{ 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F1_5180_5240	AFTER(F2_5170_5230)
+	{ 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC, 1 },
+#define	F2_5180_5240	AFTER(F1_5180_5240)
+	{ 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F3_5180_5240	AFTER(F2_5180_5240)
+	{ 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F4_5180_5240	AFTER(F3_5180_5240)
+	{ 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F5_5180_5240	AFTER(F4_5180_5240)
+	{ 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0 },
+#define	F6_5180_5240	AFTER(F5_5180_5240)
+	{ 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC, 1 },
+#define	F7_5180_5240	AFTER(F6_5180_5240)
+	{ 5180, 5240, 17, 6, 20,  5, NO_DFS, PSCAN_FCC, 1 },
+#define	F8_5180_5240	AFTER(F7_5180_5240)
+
+	{ 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
+#define	F1_5180_5320	AFTER(F8_5180_5240)
+
+	{ 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F1_5240_5280	AFTER(F1_5180_5320)
+
+	{ 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F1_5260_5280	AFTER(F1_5240_5280)
+
+	{ 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F1_5260_5320	AFTER(F1_5260_5280)
+
+	{ 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 , 0 },
+#define	F2_5260_5320	AFTER(F1_5260_5320)
+
+	{ 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
+#define	F3_5260_5320	AFTER(F2_5260_5320)
+	{ 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
+#define	F4_5260_5320	AFTER(F3_5260_5320)
+	{ 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 },
+#define	F5_5260_5320	AFTER(F4_5260_5320)
+	{ 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F6_5260_5320	AFTER(F5_5260_5320)
+	{ 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
+#define	F7_5260_5320	AFTER(F6_5260_5320)
+	{ 5260, 5320, 23, 6, 20,  5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2 },
+#define	F8_5260_5320	AFTER(F7_5260_5320)
+
+	{ 5260, 5700, 5,  6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
+#define	F1_5260_5700	AFTER(F8_5260_5320)
+	{ 5260, 5700, 5,  6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
+#define	F2_5260_5700	AFTER(F1_5260_5700)
+	{ 5260, 5700, 5,  6,  5,  5, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0 },
+#define	F3_5260_5700	AFTER(F2_5260_5700)
+
+	{ 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0 },
+#define	F1_5280_5320	AFTER(F3_5260_5700)
+
+	{ 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
+#define	F1_5500_5620	AFTER(F1_5280_5320)
+
+	{ 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4 },
+#define	F1_5500_5700	AFTER(F1_5500_5620)
+	{ 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F2_5500_5700	AFTER(F1_5500_5700)
+	{ 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0 },
+#define	F3_5500_5700	AFTER(F2_5500_5700)
+	{ 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0 },
+#define	F4_5500_5700	AFTER(F3_5500_5700)
+
+	{ 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F1_5745_5805	AFTER(F4_5500_5700)
+	{ 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F2_5745_5805	AFTER(F1_5745_5805)
+	{ 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0 },
+#define	F3_5745_5805	AFTER(F2_5745_5805)
+	{ 5745, 5825, 5,  6, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F1_5745_5825	AFTER(F3_5745_5805)
+	{ 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F2_5745_5825	AFTER(F1_5745_5825)
+	{ 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F3_5745_5825	AFTER(F2_5745_5825)
+	{ 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F4_5745_5825	AFTER(F3_5745_5825)
+	{ 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3 },
+#define	F5_5745_5825	AFTER(F4_5745_5825)
+	{ 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0 },
+#define	F6_5745_5825	AFTER(F5_5745_5825)
+	{ 5745, 5825, 5,  6, 10, 10, NO_DFS, NO_PSCAN, 0 },
+#define	F7_5745_5825	AFTER(F6_5745_5825)
+	{ 5745, 5825, 5,  6,  5,  5, NO_DFS, NO_PSCAN, 0 },
+#define	F8_5745_5825	AFTER(F7_5745_5825)
+	{ 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN, 3 },
+#define	F9_5745_5825	AFTER(F8_5745_5825)
+	{ 5745, 5825, 30, 6, 20,  5, NO_DFS, NO_PSCAN, 3 },
+#define	F10_5745_5825	AFTER(F9_5745_5825)
+
+	/*
+	 * Below are the world roaming channels
+	 * All WWR domains have no power limit, instead use the card's CTL
+	 * or max power settings.
+	 */
+	{ 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
+#define	W1_4920_4980	AFTER(F10_5745_5825)
+	{ 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
+#define	W1_5040_5080	AFTER(W1_4920_4980)
+	{ 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
+#define	W1_5170_5230	AFTER(W1_5040_5080)
+	{ 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
+#define	W1_5180_5240	AFTER(W1_5170_5230)
+	{ 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
+#define	W1_5260_5320	AFTER(W1_5180_5240)
+	{ 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
+#define	W1_5745_5825	AFTER(W1_5260_5320)
+	{ 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0 },
+#define	W1_5500_5700	AFTER(W1_5745_5825)
+	{ 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN,  0 },
+#define	W2_5260_5320	AFTER(W1_5500_5700)
+	{ 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN,  0 },
+#define	W2_5180_5240	AFTER(W2_5260_5320)
+	{ 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 },
+#define	W2_5825_5825	AFTER(W2_5180_5240)
+};
+
+/*
+ * 5GHz Turbo (dynamic & static) tags
+ */
+static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = {
+	{ 5130, 5210, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_5130_5210	0
+	{ 5250, 5330, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
+#define	T1_5250_5330	AFTER(T1_5130_5210)
+	{ 5370, 5490, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_5370_5490	AFTER(T1_5250_5330)
+	{ 5530, 5650, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
+#define	T1_5530_5650	AFTER(T1_5370_5490)
+
+	{ 5150, 5190, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_5150_5190	AFTER(T1_5530_5650)
+	{ 5230, 5310, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
+#define	T1_5230_5310	AFTER(T1_5150_5190)
+	{ 5350, 5470, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_5350_5470	AFTER(T1_5230_5310)
+	{ 5510, 5670, 5,  6, 40, 40, DFS_FCC3, NO_PSCAN, 0},
+#define	T1_5510_5670	AFTER(T1_5350_5470)
+
+	{ 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_5200_5240	AFTER(T1_5510_5670)
+	{ 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T2_5200_5240	AFTER(T1_5200_5240)
+	{ 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_5210_5210	AFTER(T2_5200_5240)
+	{ 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T2_5210_5210	AFTER(T1_5210_5210)
+
+	{ 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+#define	T1_5280_5280	AFTER(T2_5210_5210)
+	{ 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+#define	T2_5280_5280	AFTER(T1_5280_5280)
+	{ 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+#define	T1_5250_5250	AFTER(T2_5280_5280)
+	{ 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+#define	T1_5290_5290	AFTER(T1_5250_5250)
+	{ 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+#define	T1_5250_5290	AFTER(T1_5290_5290)
+	{ 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+#define	T2_5250_5290	AFTER(T1_5250_5290)
+
+	{ 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T, 0},
+#define	T1_5540_5660	AFTER(T2_5250_5290)
+	{ 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_5760_5800	AFTER(T1_5540_5660)
+	{ 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T2_5760_5800	AFTER(T1_5760_5800)
+
+	{ 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_5765_5805	AFTER(T2_5760_5800)
+
+	/*
+	 * Below are the WWR frequencies
+	 */
+	{ 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
+#define	WT1_5210_5250	AFTER(T1_5765_5805)
+	{ 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
+#define	WT1_5290_5290	AFTER(WT1_5210_5250)
+	{ 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0},
+#define	WT1_5540_5660	AFTER(WT1_5290_5290)
+	{ 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR, 0},
+#define	WT1_5760_5800	AFTER(WT1_5540_5660)
+};
+
+/*
+ * 2GHz 11b channel tags
+ */
+static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = {
+	{ 2312, 2372, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F1_2312_2372	0
+	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F2_2312_2372	AFTER(F1_2312_2372)
+
+	{ 2412, 2472, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F1_2412_2472	AFTER(F2_2312_2372)
+	{ 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},
+#define	F2_2412_2472	AFTER(F1_2412_2472)
+	{ 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F3_2412_2472	AFTER(F2_2412_2472)
+
+	{ 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F1_2412_2462	AFTER(F3_2412_2472)
+	{ 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA, 0},
+#define	F2_2412_2462	AFTER(F1_2412_2462)
+
+	{ 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F1_2432_2442	AFTER(F2_2412_2462)
+
+	{ 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F1_2457_2472	AFTER(F1_2432_2442)
+
+	{ 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0},
+#define	F1_2467_2472	AFTER(F1_2457_2472)
+
+	{ 2484, 2484, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F1_2484_2484	AFTER(F1_2467_2472)
+	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2, 0},
+#define	F2_2484_2484	AFTER(F1_2484_2484)
+
+	{ 2512, 2732, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	F1_2512_2732	AFTER(F2_2484_2484)
+
+	/*
+	 * WWR have powers opened up to 20dBm.
+	 * Limits should often come from CTL/Max powers
+	 */
+	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	W1_2312_2372	AFTER(F1_2512_2732)
+	{ 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	W1_2412_2412	AFTER(W1_2312_2372)
+	{ 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	W1_2417_2432	AFTER(W1_2412_2412)
+	{ 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	W1_2437_2442	AFTER(W1_2417_2432)
+	{ 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	W1_2447_2457	AFTER(W1_2437_2442)
+	{ 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	W1_2462_2462	AFTER(W1_2447_2457)
+	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+#define	W1_2467_2467	AFTER(W1_2462_2462)
+	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+#define	W2_2467_2467	AFTER(W1_2467_2467)
+	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+#define	W1_2472_2472	AFTER(W2_2467_2467)
+	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+#define	W2_2472_2472	AFTER(W1_2472_2472)
+	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+#define	W1_2484_2484	AFTER(W2_2472_2472)
+	{ 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+#define	W2_2484_2484	AFTER(W1_2484_2484)
+};
+
+/*
+ * 2GHz 11g channel tags
+ */
+static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = {
+	{ 2312, 2372, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	G1_2312_2372	0
+	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	G2_2312_2372	AFTER(G1_2312_2372)
+	{ 2312, 2372, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},
+#define	G3_2312_2372	AFTER(G2_2312_2372)
+	{ 2312, 2372, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},
+#define	G4_2312_2372	AFTER(G3_2312_2372)
+
+	{ 2412, 2472, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	G1_2412_2472	AFTER(G4_2312_2372)
+	{ 2412, 2472, 20, 0, 20, 5,  NO_DFS, PSCAN_MKKA_G, 0},
+#define	G2_2412_2472	AFTER(G1_2412_2472)
+	{ 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	G3_2412_2472	AFTER(G2_2412_2472)
+	{ 2412, 2472, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},
+#define	G4_2412_2472	AFTER(G3_2412_2472)
+	{ 2412, 2472, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},
+#define	G5_2412_2472	AFTER(G4_2412_2472)
+
+	{ 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	G1_2412_2462	AFTER(G5_2412_2472)
+	{ 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0},
+#define	G2_2412_2462	AFTER(G1_2412_2462)
+	{ 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN, 0},
+#define	G3_2412_2462	AFTER(G2_2412_2462)
+	{ 2412, 2462, 27, 6,  5, 5, NO_DFS, NO_PSCAN, 0},
+#define	G4_2412_2462	AFTER(G3_2412_2462)
+	
+	{ 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	G1_2432_2442	AFTER(G4_2412_2462)
+
+	{ 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	G1_2457_2472	AFTER(G1_2432_2442)
+
+	{ 2512, 2732, 5,  6, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	G1_2512_2732	AFTER(G1_2457_2472)
+	{ 2512, 2732, 5,  6, 10, 5, NO_DFS, NO_PSCAN, 0},
+#define	G2_2512_2732	AFTER(G1_2512_2732)
+	{ 2512, 2732, 5,  6,  5, 5, NO_DFS, NO_PSCAN, 0},
+#define	G3_2512_2732	AFTER(G2_2512_2732)
+
+	{ 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0 },
+#define	G1_2467_2472	AFTER(G3_2512_2732)
+
+	/*
+	 * WWR open up the power to 20dBm
+	 */
+	{ 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	WG1_2312_2372	AFTER(G1_2467_2472)
+	{ 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	WG1_2412_2412	AFTER(WG1_2312_2372)
+	{ 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	WG1_2417_2432	AFTER(WG1_2412_2412)
+	{ 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	WG1_2437_2442	AFTER(WG1_2417_2432)
+	{ 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	WG1_2447_2457	AFTER(WG1_2437_2442)
+	{ 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0},
+#define	WG1_2462_2462	AFTER(WG1_2447_2457)
+	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+#define	WG1_2467_2467	AFTER(WG1_2462_2462)
+	{ 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+#define	WG2_2467_2467	AFTER(WG1_2467_2467)
+	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0},
+#define	WG1_2472_2472	AFTER(WG2_2467_2467)
+	{ 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0},
+#define	WG2_2472_2472	AFTER(WG1_2472_2472)
+
+	/*
+	 * Mapping for 900MHz cards like Ubiquiti SR9 and XR9
+	 * and ZComax GZ-901.
+	 */
+	{ 2422, 2437, 30, 0,  5, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S1_907_922_5	AFTER(WG2_2472_2472)
+	{ 2422, 2437, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S1_907_922_10	AFTER(S1_907_922_5)
+	{ 2427, 2432, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S1_912_917	AFTER(S1_907_922_10)
+	{ 2427, 2442, 30, 0,  5, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S2_907_922_5	AFTER(S1_912_917)
+	{ 2427, 2442, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S2_907_922_10	AFTER(S2_907_922_5)
+	{ 2432, 2437, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S2_912_917	AFTER(S2_907_922_10)
+	{ 2452, 2467, 30, 0,  5, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S1_908_923_5	AFTER(S2_912_917)
+	{ 2457, 2467, 30, 0, 10, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S1_913_918_10	AFTER(S1_908_923_5)
+	{ 2457, 2467, 30, 0, 20, 5, NO_DFS, PSCAN_FCC, 0 },
+#define	S1_913_918	AFTER(S1_913_918_10)
+};
+
+/*
+ * 2GHz Dynamic turbo tags
+ */
+static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = {
+	{ 2312, 2372, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_2312_2372	0
+	{ 2437, 2437, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_2437_2437	AFTER(T1_2312_2372)
+	{ 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T2_2437_2437	AFTER(T1_2437_2437)
+	{ 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR, 0},
+#define	T3_2437_2437	AFTER(T2_2437_2437)
+	{ 2512, 2732, 5,  6, 40, 40, NO_DFS, NO_PSCAN, 0},
+#define	T1_2512_2732	AFTER(T3_2437_2437)
+};
+
+typedef struct regDomain {
+	uint16_t regDmnEnum;		/* value from EnumRd table */
+	uint8_t conformanceTestLimit;
+	uint32_t flags;			/* Requirement flags (AdHoc disallow,
+					   noise floor cal needed, etc) */
+	uint64_t dfsMask;		/* DFS bitmask for 5Ghz tables */
+	uint64_t pscan;			/* Bitmask for passive scan */
+	chanbmask_t chan11a;		/* 11a channels */
+	chanbmask_t chan11a_turbo;	/* 11a static turbo channels */
+	chanbmask_t chan11a_dyn_turbo;	/* 11a dynamic turbo channels */
+	chanbmask_t chan11a_half;	/* 11a 1/2 width channels */
+	chanbmask_t chan11a_quarter;	/* 11a 1/4 width channels */
+	chanbmask_t chan11b;		/* 11b channels */
+	chanbmask_t chan11g;		/* 11g channels */
+	chanbmask_t chan11g_turbo;	/* 11g dynamic turbo channels */
+	chanbmask_t chan11g_half;	/* 11g 1/2 width channels */
+	chanbmask_t chan11g_quarter;	/* 11g 1/4 width channels */
+} REG_DOMAIN;
+
+static REG_DOMAIN regDomains[] = {
+
+	{.regDmnEnum		= DEBUG_REG_DMN,
+	 .conformanceTestLimit	= FCC,
+	 .dfsMask		= DFS_FCC3,
+	 .chan11a		= BM3(F1_5120_5240, F1_5260_5700, F1_5745_5825),
+	 .chan11a_half		= BM3(F2_5120_5240, F2_5260_5700, F7_5745_5825),
+	 .chan11a_quarter	= BM3(F3_5120_5240, F3_5260_5700, F8_5745_5825),
+	 .chan11a_turbo		= BM8(T1_5130_5210,
+				      T1_5250_5330,
+				      T1_5370_5490,
+				      T1_5530_5650,
+				      T1_5150_5190,
+				      T1_5230_5310,
+				      T1_5350_5470,
+				      T1_5510_5670),
+	 .chan11a_dyn_turbo	= BM4(T1_5200_5240,
+				      T1_5280_5280,
+				      T1_5540_5660,
+				      T1_5765_5805),
+	 .chan11b		= BM4(F1_2312_2372,
+				      F1_2412_2472,
+				      F1_2484_2484,
+				      F1_2512_2732),
+	 .chan11g		= BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732),
+	 .chan11g_turbo		= BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732),
+	 .chan11g_half		= BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732),
+	 .chan11g_quarter	= BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732),
+	},
+
+	{.regDmnEnum		= APL1,
+	 .conformanceTestLimit	= FCC,
+	 .chan11a		= BM1(F4_5745_5825),
+	},
+
+	{.regDmnEnum		= APL2,
+	 .conformanceTestLimit	= FCC,
+	 .chan11a		= BM1(F1_5745_5805),
+	},
+
+	{.regDmnEnum		= APL3,
+	 .conformanceTestLimit	= FCC,
+	 .chan11a		= BM2(F1_5280_5320, F2_5745_5805),
+	},
+
+	{.regDmnEnum		= APL4,
+	 .conformanceTestLimit	= FCC,
+	 .chan11a		= BM2(F4_5180_5240, F3_5745_5825),
+	},
+
+	{.regDmnEnum		= APL5,
+	 .conformanceTestLimit	= FCC,
+	 .chan11a		= BM1(F2_5745_5825),
+	},
+
+	{.regDmnEnum		= APL6,
+	 .conformanceTestLimit	= ETSI,
+	 .dfsMask		= DFS_ETSI,
+	 .pscan			= PSCAN_FCC_T | PSCAN_FCC,
+	 .chan11a		= BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825),
+	 .chan11a_turbo		= BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800),
+	},
+
+	{.regDmnEnum		= APL8,
+	 .conformanceTestLimit	= ETSI,
+	 .flags			= DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM2(F6_5260_5320, F4_5745_5825),
+	},
+
+	{.regDmnEnum		= APL9,
+	 .conformanceTestLimit	= ETSI,
+	 .dfsMask		= DFS_ETSI,
+	 .pscan			= PSCAN_ETSI,
+	 .flags			= DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805),
+	},
+
+	{.regDmnEnum		= ETSI1,
+	 .conformanceTestLimit	= ETSI,
+	 .dfsMask		= DFS_ETSI,
+	 .pscan			= PSCAN_ETSI,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700),
+	},
+
+	{.regDmnEnum		= ETSI2,
+	 .conformanceTestLimit	= ETSI,
+	 .dfsMask		= DFS_ETSI,
+	 .pscan			= PSCAN_ETSI,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM1(F3_5180_5240),
+	},
+
+	{.regDmnEnum		= ETSI3,
+	 .conformanceTestLimit	= ETSI,
+	 .dfsMask		= DFS_ETSI,
+	 .pscan			= PSCAN_ETSI,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM2(W2_5180_5240, F2_5260_5320),
+	},
+
+	{.regDmnEnum		= ETSI4,
+	 .conformanceTestLimit	= ETSI,
+	 .dfsMask		= DFS_ETSI,
+	 .pscan			= PSCAN_ETSI,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM2(F3_5180_5240, F1_5260_5320),
+	},
+
+	{.regDmnEnum		= ETSI5,
+	 .conformanceTestLimit	= ETSI,
+	 .dfsMask		= DFS_ETSI,
+	 .pscan			= PSCAN_ETSI,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM1(F1_5180_5240),
+	},
+
+	{.regDmnEnum		= ETSI6,
+	 .conformanceTestLimit	= ETSI,
+	 .dfsMask		= DFS_ETSI,
+	 .pscan			= PSCAN_ETSI,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700),
+	},
+
+	{.regDmnEnum		= FCC1,
+	 .conformanceTestLimit	= FCC,
+	 .chan11a		= BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825),
+	 .chan11a_turbo		= BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800),
+	 .chan11a_dyn_turbo	= BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805),
+	},
+
+	{.regDmnEnum		= FCC2,
+	 .conformanceTestLimit	= FCC,
+	 .chan11a		= BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825),
+	 .chan11a_dyn_turbo	= BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805),
+	},
+
+	{.regDmnEnum		= FCC3,
+	 .conformanceTestLimit	= FCC,
+	 .dfsMask		= DFS_FCC3,
+	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
+	 .chan11a		= BM4(F2_5180_5240,
+				      F3_5260_5320,
+				      F1_5500_5700,
+				      F5_5745_5825),
+	 .chan11a_turbo		= BM4(T1_5210_5210,
+				      T1_5250_5250,
+				      T1_5290_5290,
+				      T2_5760_5800),
+	 .chan11a_dyn_turbo	= BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660),
+	},
+
+	{.regDmnEnum		= FCC4,
+	 .conformanceTestLimit	= FCC,
+	 .dfsMask		= DFS_FCC3,
+	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
+	 .chan11a		= BM1(F1_4950_4980),
+	 .chan11a_half		= BM1(F1_4945_4985),
+	 .chan11a_quarter	= BM1(F1_4942_4987),
+	},
+
+	/* FCC1 w/ 1/2 and 1/4 width channels */
+	{.regDmnEnum		= FCC5,
+	 .conformanceTestLimit	= FCC,
+	 .chan11a		= BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825),
+	 .chan11a_turbo		= BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800),
+	 .chan11a_dyn_turbo	= BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805),
+	 .chan11a_half		= BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825),
+	 .chan11a_quarter	= BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825),
+	},
+
+	{.regDmnEnum		= MKK1,
+	 .conformanceTestLimit	= MKK,
+	 .pscan			= PSCAN_MKK1,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM1(F1_5170_5230),
+	},
+
+	{.regDmnEnum		= MKK2,
+	 .conformanceTestLimit	= MKK,
+	 .pscan			= PSCAN_MKK2,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230),
+	.chan11a_half		= BM4(F1_4915_4925,
+				      F1_4935_4945,
+				      F1_5035_5040,
+				      F1_5055_5055),
+	},
+
+	/* UNI-1 even */
+	{.regDmnEnum		= MKK3,
+	 .conformanceTestLimit	= MKK,
+	 .pscan			= PSCAN_MKK3,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM1(F4_5180_5240),
+	},
+
+	/* UNI-1 even + UNI-2 */
+	{.regDmnEnum		= MKK4,
+	 .conformanceTestLimit	= MKK,
+	 .dfsMask		= DFS_MKK4,
+	 .pscan			= PSCAN_MKK3,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM2(F4_5180_5240, F2_5260_5320),
+	},
+
+	/* UNI-1 even + UNI-2 + mid-band */
+	{.regDmnEnum		= MKK5,
+	 .conformanceTestLimit	= MKK,
+	 .dfsMask		= DFS_MKK4,
+	 .pscan			= PSCAN_MKK3,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700),
+	},
+
+	/* UNI-1 odd + even */
+	{.regDmnEnum		= MKK6,
+	 .conformanceTestLimit	= MKK,
+	 .pscan			= PSCAN_MKK1,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM2(F2_5170_5230, F4_5180_5240),
+	},
+
+	/* UNI-1 odd + UNI-1 even + UNI-2 */
+	{.regDmnEnum		= MKK7,
+	 .conformanceTestLimit	= MKK,
+	 .dfsMask		= DFS_MKK4,
+	 .pscan			= PSCAN_MKK1 | PSCAN_MKK3,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320),
+	},
+
+	/* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */
+	{.regDmnEnum		= MKK8,
+	 .conformanceTestLimit	= MKK,
+	 .dfsMask		= DFS_MKK4,
+	 .pscan			= PSCAN_MKK1 | PSCAN_MKK3,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11a		= BM4(F1_5170_5230,
+				      F4_5180_5240,
+				      F2_5260_5320,
+				      F4_5500_5700),
+	},
+
+        /* UNI-1 even + 4.9 GHZ */
+        {.regDmnEnum		= MKK9,
+	 .conformanceTestLimit	= MKK,
+	 .pscan			= PSCAN_MKK3,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+         .chan11a		= BM7(F1_4915_4925,
+				      F1_4935_4945,
+				      F1_4920_4980,
+				      F1_5035_5040,
+				      F1_5055_5055,
+				      F1_5040_5080,
+				      F4_5180_5240),
+        },
+
+        /* UNI-1 even + UNI-2 + 4.9 GHZ */
+        {.regDmnEnum		= MKK10,
+	 .conformanceTestLimit	= MKK,
+	 .dfsMask		= DFS_MKK4,
+	 .pscan			= PSCAN_MKK3,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+         .chan11a		= BM8(F1_4915_4925,
+				      F1_4935_4945,
+				      F1_4920_4980,
+				      F1_5035_5040,
+				      F1_5055_5055,
+				      F1_5040_5080,
+				      F4_5180_5240,
+				      F2_5260_5320),
+        },
+
+	/* Defined here to use when 2G channels are authorised for country K2 */
+	{.regDmnEnum		= APLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .chan11b		= BM2(F2_2312_2372,F2_2412_2472),
+	 .chan11g		= BM2(G2_2312_2372,G2_2412_2472),
+	},
+
+	{.regDmnEnum		= ETSIA,
+	 .conformanceTestLimit	= NO_CTL,
+	 .pscan			= PSCAN_ETSIA,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11b		= BM1(F1_2457_2472),
+	 .chan11g		= BM1(G1_2457_2472),
+	 .chan11g_turbo		= BM1(T2_2437_2437)
+	},
+
+	{.regDmnEnum		= ETSIB,
+	 .conformanceTestLimit	= ETSI,
+	 .pscan			= PSCAN_ETSIB,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11b		= BM1(F1_2432_2442),
+	 .chan11g		= BM1(G1_2432_2442),
+	 .chan11g_turbo		= BM1(T2_2437_2437)
+	},
+
+	{.regDmnEnum		= ETSIC,
+	 .conformanceTestLimit	= ETSI,
+	 .pscan			= PSCAN_ETSIC,
+	 .flags			= DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
+	 .chan11b		= BM1(F3_2412_2472),
+	 .chan11g		= BM1(G3_2412_2472),
+	 .chan11g_turbo		= BM1(T2_2437_2437)
+	},
+
+	{.regDmnEnum		= FCCA,
+	 .conformanceTestLimit	= FCC,
+	 .chan11b		= BM1(F1_2412_2462),
+	 .chan11g		= BM1(G1_2412_2462),
+	 .chan11g_turbo		= BM1(T2_2437_2437),
+	},
+
+	/* FCCA w/ 1/2 and 1/4 width channels */
+	{.regDmnEnum		= FCCB,
+	 .conformanceTestLimit	= FCC,
+	 .chan11b		= BM1(F1_2412_2462),
+	 .chan11g		= BM1(G1_2412_2462),
+	 .chan11g_turbo		= BM1(T2_2437_2437),
+	 .chan11g_half		= BM1(G3_2412_2462),
+	 .chan11g_quarter	= BM1(G4_2412_2462),
+	},
+
+	{.regDmnEnum		= MKKA,
+	 .conformanceTestLimit	= MKK,
+	 .pscan			= PSCAN_MKKA | PSCAN_MKKA_G
+				| PSCAN_MKKA1 | PSCAN_MKKA1_G
+				| PSCAN_MKKA2 | PSCAN_MKKA2_G,
+	 .flags			= DISALLOW_ADHOC_11A_TURB,
+	 .chan11b		= BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484),
+	 .chan11g		= BM2(G2_2412_2462, G1_2467_2472),
+	 .chan11g_turbo		= BM1(T2_2437_2437)
+	},
+
+	{.regDmnEnum		= MKKC,
+	 .conformanceTestLimit	= MKK,
+	 .chan11b		= BM1(F2_2412_2472),
+	 .chan11g		= BM1(G2_2412_2472),
+	 .chan11g_turbo		= BM1(T2_2437_2437)
+	},
+
+	{.regDmnEnum		= WORLD,
+	 .conformanceTestLimit	= ETSI,
+	 .chan11b		= BM1(F2_2412_2472),
+	 .chan11g		= BM1(G2_2412_2472),
+	 .chan11g_turbo		= BM1(T2_2437_2437)
+	},
+
+	{.regDmnEnum		= WOR0_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_PER_11D,
+	 .chan11a		= BM5(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5170_5230,
+				      W1_5745_5825,
+				      W1_5500_5700),
+	 .chan11a_turbo		= BM3(WT1_5210_5250,
+				      WT1_5290_5290,
+				      WT1_5760_5800),
+	 .chan11b		= BM8(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2472_2472,
+				      W1_2417_2432,
+				      W1_2447_2457,
+				      W1_2467_2467,
+				      W1_2484_2484),
+	 .chan11g		= BM7(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2472_2472,
+				      WG1_2417_2432,
+				      WG1_2447_2457,
+				      WG1_2467_2467),
+	 .chan11g_turbo		= BM1(T3_2437_2437)
+	},
+
+	{.regDmnEnum		= WOR01_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_PER_11D,
+	 .chan11a		= BM5(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5170_5230,
+				      W1_5745_5825,
+				      W1_5500_5700),
+	 .chan11a_turbo		= BM3(WT1_5210_5250,
+				      WT1_5290_5290,
+				      WT1_5760_5800),
+	 .chan11b		= BM5(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2417_2432,
+				      W1_2447_2457),
+	 .chan11g		= BM5(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2417_2432,
+				      WG1_2447_2457),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= WOR02_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_PER_11D,
+	 .chan11a		= BM5(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5170_5230,
+				      W1_5745_5825,
+				      W1_5500_5700),
+	 .chan11a_turbo		= BM3(WT1_5210_5250,
+				      WT1_5290_5290,
+				      WT1_5760_5800),
+	 .chan11b		= BM7(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2472_2472,
+				      W1_2417_2432,
+				      W1_2447_2457,
+				      W1_2467_2467),
+	 .chan11g		= BM7(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2472_2472,
+				      WG1_2417_2432,
+				      WG1_2447_2457,
+				      WG1_2467_2467),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= EU1_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_PER_11D,
+	 .chan11a		= BM5(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5170_5230,
+				      W1_5745_5825,
+				      W1_5500_5700),
+	 .chan11a_turbo		= BM3(WT1_5210_5250,
+				      WT1_5290_5290,
+				      WT1_5760_5800),
+	 .chan11b		= BM7(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W2_2472_2472,
+				      W1_2417_2432,
+				      W1_2447_2457,
+				      W2_2467_2467),
+	 .chan11g		= BM7(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG2_2472_2472,
+				      WG1_2417_2432,
+				      WG1_2447_2457,
+				      WG2_2467_2467),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= WOR1_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_NO_11A,
+	 .chan11a		= BM5(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5170_5230,
+				      W1_5745_5825,
+				      W1_5500_5700),
+	 .chan11b		= BM8(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2472_2472,
+				      W1_2417_2432,
+				      W1_2447_2457,
+				      W1_2467_2467,
+				      W1_2484_2484),
+	 .chan11g		= BM7(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2472_2472,
+				      WG1_2417_2432,
+				      WG1_2447_2457,
+				      WG1_2467_2467),
+	 .chan11g_turbo		= BM1(T3_2437_2437)
+	},
+
+	{.regDmnEnum		= WOR2_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_NO_11A,
+	 .chan11a		= BM5(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5170_5230,
+				      W1_5745_5825,
+				      W1_5500_5700),
+	 .chan11a_turbo		= BM3(WT1_5210_5250,
+				      WT1_5290_5290,
+				      WT1_5760_5800),
+	 .chan11b		= BM8(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2472_2472,
+				      W1_2417_2432,
+				      W1_2447_2457,
+				      W1_2467_2467,
+				      W1_2484_2484),
+	 .chan11g		= BM7(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2472_2472,
+				      WG1_2417_2432,
+				      WG1_2447_2457,
+				      WG1_2467_2467),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= WOR3_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_PER_11D,
+	 .chan11a		= BM4(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5170_5230,
+				      W1_5745_5825),
+	 .chan11a_turbo		= BM3(WT1_5210_5250,
+				      WT1_5290_5290,
+				      WT1_5760_5800),
+	 .chan11b		= BM7(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2472_2472,
+				      W1_2417_2432,
+				      W1_2447_2457,
+				      W1_2467_2467),
+	 .chan11g		= BM7(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2472_2472,
+				      WG1_2417_2432,
+				      WG1_2447_2457,
+				      WG1_2467_2467),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= WOR4_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_NO_11A,
+	 .chan11a		= BM4(W2_5260_5320,
+				      W2_5180_5240,
+				      F2_5745_5805,
+				      W2_5825_5825),
+	 .chan11a_turbo		= BM3(WT1_5210_5250,
+				      WT1_5290_5290,
+				      WT1_5760_5800),
+	 .chan11b		= BM5(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2417_2432,
+				      W1_2447_2457),
+	 .chan11g		= BM5(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2417_2432,
+				      WG1_2447_2457),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= WOR5_ETSIC,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_NO_11A,
+	 .chan11a		= BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825),
+	 .chan11b		= BM7(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W2_2472_2472,
+				      W1_2417_2432,
+				      W1_2447_2457,
+				      W2_2467_2467),
+	 .chan11g		= BM7(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG2_2472_2472,
+				      WG1_2417_2432,
+				      WG1_2447_2457,
+				      WG2_2467_2467),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= WOR9_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_NO_11A,
+	 .chan11a		= BM4(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5745_5825,
+				      W1_5500_5700),
+	 .chan11a_turbo		= BM3(WT1_5210_5250,
+				      WT1_5290_5290,
+				      WT1_5760_5800),
+	 .chan11b		= BM5(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2417_2432,
+				      W1_2447_2457),
+	 .chan11g		= BM5(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2417_2432,
+				      WG1_2447_2457),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= WORA_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .dfsMask		= DFS_FCC3 | DFS_ETSI,
+	 .pscan			= PSCAN_WWR,
+	 .flags			= ADHOC_NO_11A,
+	 .chan11a		= BM4(W1_5260_5320,
+				      W1_5180_5240,
+				      W1_5745_5825,
+				      W1_5500_5700),
+	 .chan11b		= BM7(W1_2412_2412,
+				      W1_2437_2442,
+				      W1_2462_2462,
+				      W1_2472_2472,
+				      W1_2417_2432,
+				      W1_2447_2457,
+				      W1_2467_2467),
+	 .chan11g		= BM7(WG1_2412_2412,
+				      WG1_2437_2442,
+				      WG1_2462_2462,
+				      WG1_2472_2472,
+				      WG1_2417_2432,
+				      WG1_2447_2457,
+				      WG1_2467_2467),
+	 .chan11g_turbo		= BM1(T3_2437_2437)},
+
+	{.regDmnEnum		= SR9_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
+	 .chan11g		= BM1(S1_912_917),
+	 .chan11g_half		= BM1(S1_907_922_10),
+	 .chan11g_quarter	= BM1(S1_907_922_5),
+	},
+
+	{.regDmnEnum		= XR9_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
+	 .chan11g		= BM1(S2_912_917),
+	 .chan11g_half		= BM1(S2_907_922_10),
+	 .chan11g_quarter	= BM1(S2_907_922_5),
+	},
+
+	{.regDmnEnum		= GZ901_WORLD,
+	 .conformanceTestLimit	= NO_CTL,
+	 .pscan			= PSCAN_FCC | PSCAN_FCC_T,
+	 .chan11g		= BM1(S1_913_918),
+	 .chan11g_half		= BM1(S1_913_918_10),
+	 .chan11g_quarter	= BM1(S1_908_923_5),
+	},
+
+	{.regDmnEnum		= NULL1,
+	 .conformanceTestLimit	= NO_CTL,
+	}
+};
+
+struct cmode {
+	u_int	mode;
+	u_int	flags;
+};
+
+static const struct cmode modes[] = {
+	{ HAL_MODE_TURBO,	CHANNEL_ST},	/* NB: 11a Static Turbo */
+	{ HAL_MODE_11A,		CHANNEL_A},
+	{ HAL_MODE_11B,		CHANNEL_B},
+	{ HAL_MODE_11G,		CHANNEL_G},
+	{ HAL_MODE_11G_TURBO,	CHANNEL_108G},
+	{ HAL_MODE_11A_TURBO,	CHANNEL_108A},
+	{ HAL_MODE_11A_QUARTER_RATE,	CHANNEL_A | CHANNEL_QUARTER},
+	{ HAL_MODE_11A_HALF_RATE,	CHANNEL_A | CHANNEL_HALF},
+	{ HAL_MODE_11G_QUARTER_RATE,	CHANNEL_G | CHANNEL_QUARTER},
+	{ HAL_MODE_11G_HALF_RATE,	CHANNEL_G | CHANNEL_HALF},
+	{ HAL_MODE_11NG_HT20,	CHANNEL_G_HT20},
+	{ HAL_MODE_11NG_HT40PLUS,	CHANNEL_G_HT40PLUS},
+	{ HAL_MODE_11NG_HT40MINUS,	CHANNEL_G_HT40MINUS},
+	{ HAL_MODE_11NA_HT20,	CHANNEL_A_HT20},
+	{ HAL_MODE_11NA_HT40PLUS,	CHANNEL_A_HT40PLUS},
+	{ HAL_MODE_11NA_HT40MINUS,	CHANNEL_A_HT40MINUS},
+};
+
+static int
+chansort(const void *a, const void *b)
+{
+#define CHAN_FLAGS	(CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
+	const HAL_CHANNEL_INTERNAL *ca = a;
+	const HAL_CHANNEL_INTERNAL *cb = b;
+
+	return (ca->channel == cb->channel) ?
+		(ca->channelFlags & CHAN_FLAGS) -
+			(cb->channelFlags & CHAN_FLAGS) :
+		ca->channel - cb->channel;
+#undef CHAN_FLAGS
+}
+typedef int ath_hal_cmp_t(const void *, const void *);
+static	void ath_hal_sort(void *a, size_t n, size_t es, ath_hal_cmp_t *cmp);
+static COUNTRY_CODE_TO_ENUM_RD* findCountry(HAL_CTRY_CODE countryCode);
+static HAL_BOOL getWmRD(struct ath_hal *ah, COUNTRY_CODE_TO_ENUM_RD *country, uint16_t channelFlag, REG_DOMAIN *rd);
+
+
+static uint16_t
+getEepromRD(struct ath_hal *ah)
+{
+	return AH_PRIVATE(ah)->ah_currentRD &~ WORLDWIDE_ROAMING_FLAG;
+}
+
+/*
+ * Test to see if the bitmask array is all zeros
+ */
+static HAL_BOOL
+isChanBitMaskZero(const uint64_t *bitmask)
+{
+#if BMLEN > 2
+#error	"add more cases"
+#endif
+#if BMLEN > 1
+	if (bitmask[1] != 0)
+		return AH_FALSE;
+#endif
+	return (bitmask[0] == 0);
+}
+
+/*
+ * Return whether or not the regulatory domain/country in EEPROM
+ * is acceptable.
+ */
+static HAL_BOOL
+isEepromValid(struct ath_hal *ah)
+{
+	uint16_t rd = getEepromRD(ah);
+	int i;
+
+	if (rd & COUNTRY_ERD_FLAG) {
+		uint16_t cc = rd &~ COUNTRY_ERD_FLAG;
+		for (i = 0; i < N(allCountries); i++)
+			if (allCountries[i].countryCode == cc)
+				return AH_TRUE;
+	} else {
+		for (i = 0; i < N(regDomainPairs); i++)
+			if (regDomainPairs[i].regDmnEnum == rd)
+				return AH_TRUE;
+	}
+	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+	    "%s: invalid regulatory domain/country code 0x%x\n", __func__, rd);
+	return AH_FALSE;
+}
+
+/*
+ * Returns whether or not the specified country code
+ * is allowed by the EEPROM setting
+ */
+static HAL_BOOL
+isCountryCodeValid(struct ath_hal *ah, HAL_CTRY_CODE cc)
+{
+	uint16_t rd;
+
+	/* Default setting requires no checks */
+	if (cc == CTRY_DEFAULT)
+		return AH_TRUE;
+#ifdef AH_DEBUG_COUNTRY
+	if (cc == CTRY_DEBUG)
+		return AH_TRUE;
+#endif
+	rd = getEepromRD(ah);
+	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: EEPROM regdomain 0x%x\n",
+	    __func__, rd);
+
+	if (rd & COUNTRY_ERD_FLAG) {
+		/* EEP setting is a country - config shall match */
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: EEPROM setting is country code %u\n", __func__,
+		    rd &~ COUNTRY_ERD_FLAG);
+		return (cc == (rd & ~COUNTRY_ERD_FLAG));
+	} else if (rd == DEBUG_REG_DMN || rd == NO_ENUMRD) {
+		/* Set to Debug or AllowAnyCountry mode - allow any setting */
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: rd %d allowed\n",
+		    __func__, rd);
+		return AH_TRUE;
+#ifdef AH_SUPPORT_11D
+	} else	if ((rd & WORLD_SKU_MASK) == WORLD_SKU_PREFIX) {
+		int i;
+		for (i=0; i < N(allCountries); i++) {
+			if (cc == allCountries[i].countryCode)
+				return AH_TRUE;
+		}
+#endif
+	} else {
+		int i;
+		for (i = 0; i < N(allCountries); i++) {
+			if (cc == allCountries[i].countryCode &&
+			    allCountries[i].regDmnEnum == rd)
+				return AH_TRUE;
+		}
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Return the mask of available modes based on the hardware
+ * capabilities and the specified country code and reg domain.
+ */
+static u_int
+ath_hal_getwmodesnreg(struct ath_hal *ah,
+    const COUNTRY_CODE_TO_ENUM_RD *country, const REG_DOMAIN *rd5GHz)
+{
+#define	HAL_MODE_11G_ALL \
+	(HAL_MODE_11G | HAL_MODE_11G_TURBO | HAL_MODE_11G_QUARTER_RATE | \
+	 HAL_MODE_11G_HALF_RATE)
+#define	HAL_MODE_11A_ALL \
+	(HAL_MODE_11A | HAL_MODE_11A_TURBO | HAL_MODE_TURBO | \
+	 HAL_MODE_11A_QUARTER_RATE | HAL_MODE_11A_HALF_RATE)
+	u_int modesAvail;
+
+	/* Get modes that HW is capable of */
+	modesAvail = ath_hal_getWirelessModes(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+	    "%s: wireless modes 0x%x cc %u rd %u\n",
+	    __func__, modesAvail, country->countryCode, country->regDmnEnum);
+
+	/* Check country regulations for allowed modes */
+	if (!country->allow11g && (modesAvail & HAL_MODE_11G_ALL)) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow all 11g\n", __func__);
+		modesAvail &= ~HAL_MODE_11G_ALL;
+	}
+	if (isChanBitMaskZero(rd5GHz->chan11a) &&
+	    (modesAvail & HAL_MODE_11A_ALL)) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow all 11a\n", __func__);
+		modesAvail &= ~HAL_MODE_11A_ALL;
+	}
+	if ((modesAvail & (HAL_MODE_11A_TURBO | HAL_MODE_TURBO)) &&
+	    !country->allow11aTurbo) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow 11aTurbo\n", __func__);
+		modesAvail &= ~(HAL_MODE_11A_TURBO | HAL_MODE_TURBO);
+	}
+	if ((modesAvail & HAL_MODE_11G_TURBO) && !country->allow11gTurbo) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow 11gTurbo\n", __func__);
+		modesAvail &= ~HAL_MODE_11G_TURBO;
+	}
+
+	/* Check 11n operation */
+	if ((modesAvail & HAL_MODE_11NG_HT20) && !country->allow11ng20) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow 11g HT20\n", __func__);
+		modesAvail &= ~HAL_MODE_11NG_HT20;
+	}
+	if ((modesAvail & HAL_MODE_11NA_HT20) && !country->allow11na20) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow 11a HT20\n", __func__);
+		modesAvail &= ~HAL_MODE_11NA_HT20;
+	}
+	if ((modesAvail & HAL_MODE_11NG_HT40PLUS) && !country->allow11ng40) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow 11g HT40+\n", __func__);
+		modesAvail &= ~HAL_MODE_11NG_HT40PLUS;
+	}
+	if ((modesAvail & HAL_MODE_11NG_HT40MINUS) && !country->allow11ng40) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow 11g HT40-\n", __func__);
+		modesAvail &= ~HAL_MODE_11NG_HT40MINUS;
+	}
+	if ((modesAvail & HAL_MODE_11NA_HT40PLUS) && !country->allow11na40) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow 11a HT40+\n", __func__);
+		modesAvail &= ~HAL_MODE_11NA_HT40PLUS;
+	}
+	if ((modesAvail & HAL_MODE_11NA_HT40MINUS) && !country->allow11na40) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: disallow 11a HT40-\n", __func__);
+		modesAvail &= ~HAL_MODE_11NA_HT40MINUS;
+	}
+
+	return modesAvail;
+#undef HAL_MODE_11A_ALL
+#undef HAL_MODE_11G_ALL
+}
+
+/*
+ * Return the mask of available modes based on the hardware
+ * capabilities and the specified country code.
+ */
+
+u_int
+ath_hal_getwirelessmodes(struct ath_hal *ah, HAL_CTRY_CODE cc)
+{
+	COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
+	u_int mode = 0;
+	REG_DOMAIN rd;
+	
+	country = findCountry(cc);
+	if (country != AH_NULL) {
+		if (getWmRD(ah, country, ~CHANNEL_2GHZ, &rd))
+			mode = ath_hal_getwmodesnreg(ah, country, &rd);
+	}
+	return mode;
+}
+
+/*
+ * Return if device is public safety.
+ */
+HAL_BOOL
+ath_hal_ispublicsafetysku(struct ath_hal *ah)
+{
+	uint16_t rd = getEepromRD(ah);
+
+	switch (rd) {
+	case FCC4_FCCA:
+	case CTRY_UNITED_STATES_FCC49 | COUNTRY_ERD_FLAG:
+		return AH_TRUE;
+	case DEBUG_REG_DMN:
+	case NO_ENUMRD:
+		if (AH_PRIVATE(ah)->ah_countryCode == CTRY_UNITED_STATES_FCC49)
+			return AH_TRUE;
+		break;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Return if device is actually operating in 900 MHz band.
+ */
+HAL_BOOL
+ath_hal_isgsmsku(struct ath_hal *ah)
+{
+	uint16_t rd = getEepromRD(ah);
+
+	switch (rd) {
+	case SR9_WORLD:
+	case XR9_WORLD:
+	case GZ901_WORLD:
+	case CTRY_SR9 | COUNTRY_ERD_FLAG:
+	case CTRY_XR9 | COUNTRY_ERD_FLAG:
+	case CTRY_GZ901 | COUNTRY_ERD_FLAG:
+		return AH_TRUE;
+	case DEBUG_REG_DMN:
+	case NO_ENUMRD:
+		return AH_PRIVATE(ah)->ah_countryCode == CTRY_SR9
+		       || AH_PRIVATE(ah)->ah_countryCode == CTRY_XR9
+		       || AH_PRIVATE(ah)->ah_countryCode == CTRY_GZ901
+		       ;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Find the pointer to the country element in the country table
+ * corresponding to the country code
+ */
+static COUNTRY_CODE_TO_ENUM_RD*
+findCountry(HAL_CTRY_CODE countryCode)
+{
+	int i;
+
+	for (i = 0; i < N(allCountries); i++) {
+		if (allCountries[i].countryCode == countryCode)
+			return &allCountries[i];
+	}
+	return AH_NULL;		/* Not found */
+}
+
+/*
+ * Calculate a default country based on the EEPROM setting.
+ */
+static HAL_CTRY_CODE
+getDefaultCountry(struct ath_hal *ah)
+{
+	uint16_t rd;
+	int i;
+
+	rd = getEepromRD(ah);
+	if (rd & COUNTRY_ERD_FLAG) {
+		COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
+		uint16_t cc = rd & ~COUNTRY_ERD_FLAG;
+		
+		country = findCountry(cc);
+		if (country != AH_NULL)
+			return cc;
+	}
+	/*
+	 * Check reg domains that have only one country
+	 */
+	for (i = 0; i < N(regDomainPairs); i++)
+		if (regDomainPairs[i].regDmnEnum == rd) {
+			if (regDomainPairs[i].singleCC != 0)
+				return regDomainPairs[i].singleCC;
+			else
+				i = N(regDomainPairs);
+		}
+	return CTRY_DEFAULT;
+}
+
+static HAL_BOOL
+isValidRegDmn(int regDmn, REG_DOMAIN *rd)
+{
+	int i;
+
+	for (i = 0; i < N(regDomains); i++) {
+		if (regDomains[i].regDmnEnum == regDmn) {
+			if (rd != AH_NULL) {
+				OS_MEMCPY(rd, &regDomains[i],
+					  sizeof(REG_DOMAIN));
+			}
+			return AH_TRUE;
+		}
+	}
+	return AH_FALSE;
+}
+
+static HAL_BOOL
+isValidRegDmnPair(int regDmnPair)
+{
+	int i;
+
+	if (regDmnPair == NO_ENUMRD)
+		return AH_FALSE;
+	for (i = 0; i < N(regDomainPairs); i++) {
+		if (regDomainPairs[i].regDmnEnum == regDmnPair)
+			return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Return the Wireless Mode Regulatory Domain based
+ * on the country code and the wireless mode.
+ */
+static HAL_BOOL
+getWmRD(struct ath_hal *ah, COUNTRY_CODE_TO_ENUM_RD *country,
+	uint16_t channelFlag, REG_DOMAIN *rd)
+{
+	int regDmn;
+	REG_DMN_PAIR_MAPPING *regPair;
+	uint64_t flags;
+
+	if (country->countryCode == CTRY_DEFAULT) {
+		uint16_t rdnum = getEepromRD(ah);
+
+		if ((rdnum & COUNTRY_ERD_FLAG) == 0) {
+			if (isValidRegDmn(rdnum, AH_NULL) ||
+			    isValidRegDmnPair(rdnum))
+				regDmn = rdnum;
+			else
+				regDmn = country->regDmnEnum;
+		} else
+			regDmn = country->regDmnEnum;
+	} else
+		regDmn = country->regDmnEnum;
+	regPair = AH_NULL;
+	flags = NO_REQ;
+	if ((regDmn & MULTI_DOMAIN_MASK) == 0) {
+		int i;
+
+		for (i = 0; i < N(regDomainPairs); i++) {
+			if (regDomainPairs[i].regDmnEnum == regDmn) {
+				regPair = &regDomainPairs[i];
+				break;
+			}
+		}
+		if (regPair == AH_NULL) {
+			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+			    "%s: Failed to find reg domain pair %u\n",
+			    __func__, regDmn);
+			return AH_FALSE;
+		}
+		if (channelFlag & CHANNEL_2GHZ) {
+			regDmn = regPair->regDmn2GHz;
+			flags = regPair->flags2GHz;
+		} else {
+			regDmn = regPair->regDmn5GHz;
+			flags = regPair->flags5GHz;
+		}
+	}
+
+	/*
+	 * We either started with a unitary reg domain or we've found the 
+	 * unitary reg domain of the pair
+	 */
+	if (isValidRegDmn(regDmn, rd)) {
+		if (regPair != AH_NULL)
+			rd->pscan &= regPair->pscanMask;
+		if ((country->regDmnEnum & MULTI_DOMAIN_MASK) == 0 &&
+		    flags != NO_REQ)
+			rd->flags = flags;
+		return AH_TRUE;
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: Failed to find unitary reg domain %u\n", __func__,
+		    country->regDmnEnum);
+		return AH_FALSE;
+	}
+}
+
+static HAL_BOOL
+IS_BIT_SET(int bit, const uint64_t bitmask[])
+{
+	int byteOffset, bitnum;
+	uint64_t val;
+
+	byteOffset = bit/64;
+	bitnum = bit - byteOffset*64;
+	val = ((uint64_t) 1) << bitnum;
+	return (bitmask[byteOffset] & val) != 0;
+}
+	
+/* Add given regclassid into regclassids array upto max of maxregids */
+static void
+ath_add_regclassid(uint8_t *regclassids, u_int maxregids,
+	u_int *nregids, uint8_t regclassid)
+{
+	int i;
+
+	/* Is regclassid valid? */
+	if (regclassid == 0)
+		return;
+
+	for (i = 0; i < maxregids; i++) {
+		if (regclassids[i] == regclassid)	/* already present */
+			return;
+		if (regclassids[i] == 0) {		/* free slot */
+			regclassids[i] = regclassid;
+			(*nregids)++;
+			return;
+		}
+	}
+}
+
+/*
+ * Setup the channel list based on the information in the EEPROM and
+ * any supplied country code.  Note that we also do a bunch of EEPROM
+ * verification here and setup certain regulatory-related access
+ * control data used later on.
+ */
+
+HAL_BOOL
+ath_hal_init_channels(struct ath_hal *ah,
+		      HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
+		      uint8_t *regclassids, u_int maxregids, u_int *nregids,
+		      HAL_CTRY_CODE cc, u_int modeSelect,
+		      HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels)
+{
+#define CHANNEL_HALF_BW		10
+#define CHANNEL_QUARTER_BW	5
+	u_int modesAvail;
+	uint16_t maxChan;
+	COUNTRY_CODE_TO_ENUM_RD *country = AH_NULL;
+	REG_DOMAIN rd5GHz, rd2GHz;
+	const struct cmode *cm;
+	HAL_CHANNEL_INTERNAL *ichans = &AH_PRIVATE(ah)->ah_channels[0];
+	int next, b;
+	uint8_t ctl;
+
+	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u mode 0x%x%s%s\n",
+	    __func__, cc, modeSelect, enableOutdoor? " Enable outdoor" : " ",
+	    enableExtendedChannels ? " Enable ecm" : "");
+
+	/*
+	 * Validate the EEPROM setting and setup defaults
+	 */
+	if (!isEepromValid(ah)) {
+		/*
+		 * Don't return any channels if the EEPROM has an
+		 * invalid regulatory domain/country code setting.
+		 */
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: invalid EEPROM contents\n",__func__);
+		return AH_FALSE;
+	}
+
+	AH_PRIVATE(ah)->ah_countryCode = getDefaultCountry(ah);
+
+#ifndef AH_SUPPORT_11D
+	if (AH_PRIVATE(ah)->ah_countryCode == CTRY_DEFAULT) {
+#endif
+		/* 
+		 * We now have enough state to validate any country code
+		 * passed in by the caller.
+		 */
+		if (!isCountryCodeValid(ah, cc)) {
+			/* NB: Atheros silently ignores invalid country codes */
+			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+			    "%s: invalid country code %d\n", __func__, cc);
+			return AH_FALSE;
+		}
+		AH_PRIVATE(ah)->ah_countryCode = cc & COUNTRY_CODE_MASK;
+#ifndef AH_SUPPORT_11D
+	}
+#endif
+
+	/* Get pointers to the country element and the reg domain elements */
+	country = findCountry(AH_PRIVATE(ah)->ah_countryCode);
+	
+	if (country == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "NULL Country!, cc= %d\n",
+		    AH_PRIVATE(ah)->ah_countryCode);
+		return AH_FALSE;
+	}
+
+	if (!getWmRD(ah, country, ~CHANNEL_2GHZ, &rd5GHz)) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: no unitary 5GHz regdomain for country %u\n",
+		     __func__, AH_PRIVATE(ah)->ah_countryCode);
+		return AH_FALSE;
+	}
+	if (!getWmRD(ah, country, CHANNEL_2GHZ, &rd2GHz)) {
+		HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+		    "%s: no unitary 2GHz regdomain for country %u\n",
+		    __func__, AH_PRIVATE(ah)->ah_countryCode);
+		return AH_FALSE;
+	}
+
+	modesAvail = ath_hal_getwmodesnreg(ah, country, &rd5GHz);
+	maxChan = !enableOutdoor ? country->outdoorChanStart : 7000;
+
+	if (maxchans > N(AH_PRIVATE(ah)->ah_channels))
+		maxchans = N(AH_PRIVATE(ah)->ah_channels);
+	next = 0;
+	for (cm = modes; cm < &modes[N(modes)]; cm++) {
+		uint16_t c, c_hi, c_lo;
+		uint64_t *channelBM = AH_NULL;
+		REG_DOMAIN *rd = AH_NULL;
+		REG_DMN_FREQ_BAND *fband = AH_NULL,*freqs;
+		int low_adj, hi_adj, channelSep, lastc;
+
+		if ((cm->mode & modeSelect) == 0) {
+			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+			    "%s: skip mode 0x%x flags 0x%x\n",
+			    __func__, cm->mode, cm->flags);
+			continue;
+		}
+		if ((cm->mode & modesAvail) == 0) {
+			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+			    "%s: !avail mode 0x%x (0x%x) flags 0x%x\n",
+			    __func__, modesAvail, cm->mode, cm->flags);
+			continue;
+		}
+		if (!ath_hal_getChannelEdges(ah, cm->flags, &c_lo, &c_hi)) {
+			/* channel not supported by hardware, skip it */
+			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+			    "%s: channels 0x%x not supported by hardware\n",
+			    __func__,cm->flags);
+			continue;
+		}
+		switch (cm->mode) {
+		case HAL_MODE_TURBO:
+			rd = &rd5GHz;
+			channelBM = rd->chan11a_turbo;
+			freqs = &regDmn5GhzTurboFreq[0];
+			ctl = rd->conformanceTestLimit | CTL_TURBO;
+			break;
+		case HAL_MODE_11A:
+		case HAL_MODE_11A_HALF_RATE:
+		case HAL_MODE_11A_QUARTER_RATE:
+		case HAL_MODE_11NA_HT20:
+		case HAL_MODE_11NA_HT40PLUS:
+		case HAL_MODE_11NA_HT40MINUS:
+			rd = &rd5GHz;
+			if (cm->mode == HAL_MODE_11A_HALF_RATE)
+				channelBM = rd->chan11a_half;
+			else if (cm->mode == HAL_MODE_11A_QUARTER_RATE)
+				channelBM = rd->chan11a_quarter;
+			else
+				channelBM = rd->chan11a;
+			freqs = &regDmn5GhzFreq[0];
+			ctl = rd->conformanceTestLimit;
+			break;
+		case HAL_MODE_11B:
+			rd = &rd2GHz;
+			channelBM = rd->chan11b;
+			freqs = &regDmn2GhzFreq[0];
+			ctl = rd->conformanceTestLimit | CTL_11B;
+			break;
+		case HAL_MODE_11G:
+		case HAL_MODE_11G_HALF_RATE:
+		case HAL_MODE_11G_QUARTER_RATE:
+		case HAL_MODE_11NG_HT20:
+		case HAL_MODE_11NG_HT40PLUS:
+		case HAL_MODE_11NG_HT40MINUS:
+			rd = &rd2GHz;
+			if (cm->mode == HAL_MODE_11G_HALF_RATE)
+				channelBM = rd->chan11g_half;
+			else if (cm->mode == HAL_MODE_11G_QUARTER_RATE)
+				channelBM = rd->chan11g_quarter;
+			else
+				channelBM = rd->chan11g;
+			freqs = &regDmn2Ghz11gFreq[0];
+			ctl = rd->conformanceTestLimit | CTL_11G;
+			break;
+		case HAL_MODE_11G_TURBO:
+			rd = &rd2GHz;
+			channelBM = rd->chan11g_turbo;
+			freqs = &regDmn2Ghz11gTurboFreq[0];
+			ctl = rd->conformanceTestLimit | CTL_108G;
+			break;
+		case HAL_MODE_11A_TURBO:
+			rd = &rd5GHz;
+			channelBM = rd->chan11a_dyn_turbo;
+			freqs = &regDmn5GhzTurboFreq[0];
+			ctl = rd->conformanceTestLimit | CTL_108G;
+			break;
+		default:
+			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+			    "%s: Unkonwn HAL mode 0x%x\n", __func__, cm->mode);
+			continue;
+		}
+		if (isChanBitMaskZero(channelBM))
+			continue;
+		/*
+		 * Setup special handling for HT40 channels; e.g.
+		 * 5G HT40 channels require 40Mhz channel separation.
+		 */
+		hi_adj = (cm->mode == HAL_MODE_11NA_HT40PLUS ||
+		    cm->mode == HAL_MODE_11NG_HT40PLUS) ? -20 : 0;
+		low_adj = (cm->mode == HAL_MODE_11NA_HT40MINUS || 
+		    cm->mode == HAL_MODE_11NG_HT40MINUS) ? 20 : 0;
+		channelSep = (cm->mode == HAL_MODE_11NA_HT40PLUS ||
+		    cm->mode == HAL_MODE_11NA_HT40MINUS) ? 40 : 0;
+
+		for (b = 0; b < 64*BMLEN; b++) {
+			if (!IS_BIT_SET(b, channelBM))
+				continue;
+			fband = &freqs[b];
+			lastc = 0;
+
+			ath_add_regclassid(regclassids, maxregids, 
+					nregids, fband->regClassId);
+
+			for (c = fband->lowChannel + low_adj;
+			     c <= fband->highChannel + hi_adj;
+			     c += fband->channelSep) {
+				HAL_CHANNEL_INTERNAL icv;
+				
+				if (!(c_lo <= c && c <= c_hi)) {
+					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+					    "%s: c %u out of range [%u..%u]\n",
+					    __func__, c, c_lo, c_hi);
+					continue;
+				}
+				if (((c+fband->channelSep)/2) > (maxChan+HALF_MAXCHANBW)) {
+					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+					    "%s: c %u > maxChan %u\n",
+					    __func__, c, maxChan);
+					continue;
+				}
+				if (next >= maxchans){
+					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+					    "%s: too many channels for channel table\n",
+					    __func__);
+					goto done;
+				}
+				if ((fband->usePassScan & IS_ECM_CHAN) &&
+				    !enableExtendedChannels) {
+					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+					    "Skipping ecm channel\n");
+					continue;
+				}
+				/* XXX needs to be in ath_hal_checkchannel */
+				if ((rd->flags & NO_HOSTAP) && 
+				    (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP)) {
+					HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+					    "Skipping HOSTAP channel\n");
+					continue;
+				}
+				/*
+				 * Make sure that channel separation
+				 * meets the requirement.
+				 */
+				if (lastc && channelSep &&
+				    (c-lastc) < channelSep)
+					continue;
+
+				OS_MEMZERO(&icv, sizeof(icv));
+				icv.channel = c;
+				icv.channelFlags = cm->flags;
+				icv.maxRegTxPower = fband->powerDfs;
+				icv.antennaMax = fband->antennaMax;
+				icv.regDmnFlags = rd->flags;
+				icv.conformanceTestLimit = ctl;
+				if (fband->usePassScan & rd->pscan)
+					icv.channelFlags |= CHANNEL_PASSIVE;
+				else
+					icv.channelFlags &= ~CHANNEL_PASSIVE;
+				lastc = c;
+				if (fband->useDfs & rd->dfsMask) {
+					/* DFS and HT40 don't mix */
+					if (cm->mode == HAL_MODE_11NA_HT40PLUS ||
+					    cm->mode == HAL_MODE_11NA_HT40MINUS)
+						continue;
+					icv.privFlags = CHANNEL_DFS;
+				} else
+					icv.privFlags = 0;
+				if (rd->flags & LIMIT_FRAME_4MS)
+					icv.privFlags |= CHANNEL_4MS_LIMIT;
+
+				ichans[next++] = icv;
+			}
+		}
+	}
+done:
+	if (next != 0) {
+		int i;
+
+		/* XXX maxchans set above so this cannot happen? */
+		if (next > N(AH_PRIVATE(ah)->ah_channels)) {
+			HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
+			    "%s: too many channels %u; truncating to %u\n",
+			    __func__, next,
+			    (int) N(AH_PRIVATE(ah)->ah_channels));
+			next = N(AH_PRIVATE(ah)->ah_channels);
+		}
+
+		/*
+		 * Keep a private copy of the channel list so we can
+		 * constrain future requests to only these channels
+		 */
+		ath_hal_sort(ichans, next, sizeof(HAL_CHANNEL_INTERNAL),
+		    chansort);
+		AH_PRIVATE(ah)->ah_nchan = next;
+
+		/*
+		 * Copy the channel list to the public channel list
+		 */
+		for (i = 0; i < next; i++) {
+			chans[i].channel = ichans[i].channel;
+			chans[i].channelFlags = ichans[i].channelFlags;
+			chans[i].privFlags = ichans[i].privFlags;
+			chans[i].maxRegTxPower = ichans[i].maxRegTxPower;
+		}
+		/*
+		 * Retrieve power limits.
+		 */
+		ath_hal_getpowerlimits(ah, chans, next);
+		for (i = 0; i < next; i++) {
+			ichans[i].maxTxPower = chans[i].maxTxPower;
+			ichans[i].minTxPower = chans[i].minTxPower;
+		}
+	}
+	*nchans = next;
+	/* XXX copy private setting to public area */
+	ah->ah_countryCode = AH_PRIVATE(ah)->ah_countryCode;
+	return (next != 0);
+#undef CHANNEL_HALF_BW
+#undef CHANNEL_QUARTER_BW
+}
+
+/*
+ * Return whether or not the specified channel is ok to use
+ * based on the current regulatory domain constraints and 
+ * DFS interference.
+ */
+HAL_CHANNEL_INTERNAL *
+ath_hal_checkchannel(struct ath_hal *ah, const HAL_CHANNEL *c)
+{
+#define CHAN_FLAGS	(CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER)
+	HAL_CHANNEL_INTERNAL *base, *cc;
+	/* NB: be wary of user-specified channel flags */
+	int flags = c->channelFlags & CHAN_FLAGS;
+	int n, lim, d;
+
+	/*
+	 * Check current channel to avoid the lookup.
+	 */
+	cc = AH_PRIVATE(ah)->ah_curchan;
+	if (cc != AH_NULL && cc->channel == c->channel &&
+	    (cc->channelFlags & CHAN_FLAGS) == flags) {
+		if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
+		    (cc->channelFlags & CHANNEL_DFS))
+			return AH_NULL;
+		else
+			return cc;
+	}
+
+	/* binary search based on known sorting order */
+	base = AH_PRIVATE(ah)->ah_channels;
+	n = AH_PRIVATE(ah)->ah_nchan;
+	/* binary search based on known sorting order */
+	for (lim = n; lim != 0; lim >>= 1) {
+		cc = &base[lim>>1];
+		d = c->channel - cc->channel;
+		if (d == 0) {
+			if ((cc->channelFlags & CHAN_FLAGS) == flags) {
+				if ((cc->privFlags & CHANNEL_INTERFERENCE) &&
+				    (cc->channelFlags & CHANNEL_DFS))
+					return AH_NULL;
+				else
+					return cc;
+			}
+			d = flags - (cc->channelFlags & CHAN_FLAGS);
+		}
+		if (d > 0) {
+			base = cc + 1;
+			lim--;
+		}
+	}
+	HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: no match for %u/0x%x\n",
+	   __func__, c->channel, c->channelFlags);
+	return AH_NULL;
+#undef CHAN_FLAGS
+}
+
+/*
+ * Return the max allowed antenna gain and apply any regulatory
+ * domain specific changes.
+ *
+ * NOTE: a negative reduction is possible in RD's that only
+ * measure radiated power (e.g., ETSI) which would increase
+ * that actual conducted output power (though never beyond
+ * the calibrated target power).
+ */
+u_int
+ath_hal_getantennareduction(struct ath_hal *ah, HAL_CHANNEL *chan, u_int twiceGain)
+{
+	HAL_CHANNEL_INTERNAL *ichan=AH_NULL;
+	int8_t antennaMax;
+
+	if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) {
+		antennaMax = twiceGain - ichan->antennaMax*2;
+		return (antennaMax < 0) ? 0 : antennaMax;
+	} else {
+		/* Failed to find the correct index - may be a debug channel */
+		return 0;
+	}
+}
+
+
+/* XXX - maybe move ctl decision into channel set area or
+ into the tables so no decision is needed in the code */
+
+#define isWwrSKU(_ah) \
+	((getEepromRD((_ah)) & WORLD_SKU_MASK) == WORLD_SKU_PREFIX || \
+	  getEepromRD(_ah) == WORLD)
+
+
+/*
+ * Return the test group from the specified channel from
+ * the regulatory table.
+ *
+ * TODO: CTL for 11B CommonMode when regulatory domain is unknown
+ */
+u_int
+ath_hal_getctl(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	u_int ctl = NO_CTL;
+	HAL_CHANNEL_INTERNAL *ichan;
+
+	/* Special CTL to signify WWR SKU without a known country */
+	if (AH_PRIVATE(ah)->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) {
+		if (IS_CHAN_B(chan)) {
+			ctl = SD_NO_CTL | CTL_11B;
+		} else if (IS_CHAN_G(chan)) {
+			ctl = SD_NO_CTL | CTL_11G;
+		} else if (IS_CHAN_108G(chan)) {
+			ctl = SD_NO_CTL | CTL_108G;
+		} else if (IS_CHAN_T(chan)) {
+			ctl = SD_NO_CTL | CTL_TURBO;
+		} else {
+			ctl = SD_NO_CTL | CTL_11A;
+		}
+	} else {
+		if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL) {
+			ctl = ichan->conformanceTestLimit;
+			/* limit 11G OFDM power */
+			if (IS_CHAN_PUREG(chan) &&
+			    (ctl & CTL_MODE_M) == CTL_11B)
+				ctl = (ctl &~ CTL_MODE_M) | CTL_11G;
+		}
+	}
+	return ctl;
+}
+
+/*
+ * Return whether or not a noise floor check is required in
+ * the current regulatory domain for the specified channel.
+ */
+HAL_BOOL
+ath_hal_getnfcheckrequired(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	HAL_CHANNEL_INTERNAL *ichan;
+
+	if ((ichan = ath_hal_checkchannel(ah, chan)) != AH_NULL)
+		return ((ichan->regDmnFlags & NEED_NFC) ? AH_TRUE : AH_FALSE);
+	return AH_FALSE;
+}
+
+/*
+ * Insertion sort.
+ */
+#define swap(_a, _b, _size) {			\
+	uint8_t *s = _b;			\
+	int i = _size;				\
+	do {					\
+		uint8_t tmp = *_a;		\
+		*_a++ = *s;			\
+		*s++ = tmp;			\
+	} while (--i);				\
+	_a -= _size;				\
+}
+
+static void
+ath_hal_sort(void *a, size_t n, size_t size, ath_hal_cmp_t *cmp)
+{
+	uint8_t *aa = a;
+	uint8_t *ai, *t;
+
+	for (ai = aa+size; --n >= 1; ai += size)
+		for (t = ai; t > aa; t -= size) {
+			uint8_t *u = t - size;
+			if (cmp(u, t) <= 0)
+				break;
+			swap(u, t, size);
+		}
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ah_soc.h b/sys/dev/netif/ath/hal/ath_hal/ah_soc.h
new file mode 100644
index 0000000..50fbc62
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ah_soc.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_soc.h,v 1.4 2008/11/10 04:08:00 sam Exp $
+ */
+#ifndef _ATH_AH_SOC_H_
+#define _ATH_AH_SOC_H_
+/*
+ * Atheros System on Chip (SoC) public definitions.
+ */
+
+/*
+ * This is board-specific data that is stored in a "known"
+ * location in flash.  To find the start of this data search
+ * back from the (aliased) end of flash by 0x1000 bytes at a
+ * time until you find the string "5311", which marks the
+ * start of Board Configuration.  Typically one gives up if
+ * more than 500KB is searched.
+ */
+struct ar531x_boarddata {
+	uint32_t magic;             /* board data is valid */
+#define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
+	uint16_t cksum;             /* checksum (starting with BD_REV 2) */
+	uint16_t rev;               /* revision of this struct */
+#define BD_REV  4
+	char   boardName[64];        /* Name of board */
+	uint16_t major;             /* Board major number */
+	uint16_t minor;             /* Board minor number */
+	uint32_t config;            /* Board configuration */
+#define BD_ENET0        0x00000001   /* ENET0 is stuffed */
+#define BD_ENET1        0x00000002   /* ENET1 is stuffed */
+#define BD_UART1        0x00000004   /* UART1 is stuffed */
+#define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
+#define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
+#define BD_SYSLED       0x00000020   /* System LED stuffed */
+#define BD_EXTUARTCLK   0x00000040   /* External UART clock */
+#define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
+#define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
+#define BD_WLAN0        0x00000200   /* Enable WLAN0 */
+#define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
+#define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
+#define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
+#define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
+#define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
+#define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
+#define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
+#define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
+	uint16_t resetConfigGpio;   /* Reset factory GPIO pin */
+	uint16_t sysLedGpio;        /* System LED GPIO pin */
+	
+	uint32_t cpuFreq;           /* CPU core frequency in Hz */
+	uint32_t sysFreq;           /* System frequency in Hz */
+	uint32_t cntFreq;           /* Calculated C0_COUNT frequency */
+	
+	uint8_t  wlan0Mac[6];
+	uint8_t  enet0Mac[6];
+	uint8_t  enet1Mac[6];
+	
+	uint16_t pciId;             /* Pseudo PCIID for common code */
+	uint16_t memCap;            /* cap bank1 in MB */
+	
+	/* version 3 */
+	uint8_t  wlan1Mac[6];       /* (ar5212) */
+};
+
+/*
+ * Board support data.  The driver is required to locate
+ * and fill-in this information before passing a reference to
+ * this structure as the HAL_BUS_TAG parameter supplied to
+ * ath_hal_attach.
+ */
+struct ar531x_config {
+	const struct ar531x_boarddata *board;	/* board config data */
+	const char	*radio;			/* radio config data */
+	int		unit;			/* unit number [0, 1] */
+	void		*tag;			/* bus space tag */
+};
+#endif	/* _ATH_AH_SOC_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210.h b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210.h
new file mode 100644
index 0000000..857cf3c
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210.h
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210.h,v 1.8 2008/11/11 02:40:13 sam Exp $
+ */
+#ifndef _ATH_AR5210_H_
+#define _ATH_AR5210_H_
+
+#define	AR5210_MAGIC	0x19980124
+
+#if 0
+/*
+ * RTS_ENABLE includes LONG_PKT because they essentially
+ * imply the same thing, and are set or not set together
+ * for this chip
+ */
+#define AR5210_TXD_CTRL_A_HDR_LEN(_val)         (((_val)      ) & 0x0003f)
+#define AR5210_TXD_CTRL_A_TX_RATE(_val)         (((_val) <<  6) & 0x003c0)
+#define AR5210_TXD_CTRL_A_RTS_ENABLE            (                 0x00c00)
+#define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
+#define AR5210_TXD_CTRL_A_ANT_MODE(_val)        (((_val) << 13) & 0x02000)
+#define AR5210_TXD_CTRL_A_PKT_TYPE(_val)        (((_val) << 14) & 0x1c000)
+#define AR5210_TXD_CTRL_A_INT_REQ               (                 0x20000)
+#define AR5210_TXD_CTRL_A_KEY_VALID             (                 0x40000)
+#define AR5210_TXD_CTRL_B_KEY_ID(_val)          (((_val)      ) & 0x0003f)
+#define AR5210_TXD_CTRL_B_RTS_DURATION(_val)    (((_val) <<  6) & 0x7ffc0)
+#endif
+
+#define INIT_CONFIG_STATUS              0x00000000
+#define INIT_ACKTOPS                    0x00000008
+#define INIT_BCON_CNTRL_REG             0x00000000
+#define INIT_SLOT_TIME                  0x00000168
+#define INIT_SLOT_TIME_TURBO            0x000001e0 /* More aggressive turbo slot timing = 6 us */
+#define INIT_ACK_CTS_TIMEOUT            0x04000400
+#define INIT_ACK_CTS_TIMEOUT_TURBO      0x08000800
+
+#define INIT_USEC                       0x27
+#define INIT_USEC_TURBO                 0x4f
+#define INIT_USEC_32                    0x1f
+#define INIT_TX_LATENCY                 0x36
+#define INIT_RX_LATENCY                 0x1D
+#define INIT_TRANSMIT_LATENCY \
+	((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
+	 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
+	 (INIT_USEC_32 << 7) | INIT_USEC )
+#define INIT_TRANSMIT_LATENCY_TURBO  \
+	((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
+	 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
+	 (INIT_USEC_32 << 7) | INIT_USEC_TURBO)
+
+#define INIT_SIFS                       0x230 /* = 16 us - 2 us */
+#define INIT_SIFS_TURBO                 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */
+
+/*
+ * Various fifo fill before Tx start, in 64-byte units
+ * i.e. put the frame in the air while still DMAing
+ */
+#define MIN_TX_FIFO_THRESHOLD           0x1
+#define MAX_TX_FIFO_THRESHOLD           ((IEEE80211_MAX_LEN / 64) + 1)
+
+#define INIT_NEXT_CFP_START             0xffffffff
+
+#define INIT_BEACON_PERIOD              0xffff
+#define INIT_BEACON_EN                  0 /* this should be set by AP only when it's ready */
+#define INIT_BEACON_CONTROL \
+	((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
+	 (INIT_TIM_OFFSET<<16)  | INIT_BEACON_PERIOD)
+
+#define INIT_RSSI_THR                   0x00000700 /* Missed beacon counter initialized to max value of 7 */
+#define INIT_ProgIFS                    0x398      /* PIFS - 2us */
+#define INIT_ProgIFS_TURBO              0x3C0
+#define INIT_EIFS                       0xd70
+#define INIT_EIFS_TURBO                 0x1ae0
+#define INIT_CARR_SENSE_EN              1
+#define INIT_PROTO_TIME_CNTRL           ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \
+                                          (INIT_ProgIFS) )
+#define INIT_PROTO_TIME_CNTRL_TURBO     ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \
+                                          (INIT_ProgIFS_TURBO) )
+
+#define	AR5210_MAX_RATE_POWER	60
+
+#undef HAL_NUM_TX_QUEUES	/* from ah.h */
+#define	HAL_NUM_TX_QUEUES	3
+
+struct ath_hal_5210 {
+	struct ath_hal_private ah_priv;	/* base definitions */
+
+	uint8_t		ah_macaddr[IEEE80211_ADDR_LEN];
+	/*
+	 * Runtime state.
+	 */
+	uint32_t	ah_maskReg;		/* shadow of IMR+IER regs */
+	uint32_t	ah_txOkInterruptMask;
+	uint32_t	ah_txErrInterruptMask;
+	uint32_t	ah_txDescInterruptMask;
+	uint32_t	ah_txEolInterruptMask;
+	uint32_t	ah_txUrnInterruptMask;
+	HAL_POWER_MODE	ah_powerMode;
+	uint8_t		ah_bssid[IEEE80211_ADDR_LEN];
+	HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
+	/*
+	 * Station mode support.
+	 */
+	uint32_t	ah_staId1Defaults;	/* STA_ID1 default settings */
+	uint32_t	ah_rssiThr;		/* RSSI_THR settings */
+
+	u_int		ah_sifstime;		/* user-specified sifs time */
+	u_int		ah_slottime;		/* user-specified slot time */
+	u_int		ah_acktimeout;		/* user-specified ack timeout */
+	u_int		ah_ctstimeout;		/* user-specified cts timeout */
+};
+#define	AH5210(ah)	((struct ath_hal_5210 *)(ah))
+
+struct ath_hal;
+
+extern	void ar5210Detach(struct ath_hal *ah);
+extern	HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
+		HAL_CHANNEL *, HAL_BOOL bChannelChange, HAL_STATUS *);
+extern	void ar5210SetPCUConfig(struct ath_hal *);
+extern	HAL_BOOL ar5210PhyDisable(struct ath_hal *);
+extern	HAL_BOOL ar5210Disable(struct ath_hal *);
+extern	HAL_BOOL ar5210ChipReset(struct ath_hal *, HAL_CHANNEL *);
+extern	HAL_BOOL ar5210PerCalibration(struct ath_hal *, HAL_CHANNEL *, HAL_BOOL *);
+extern	HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
+		u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
+extern	HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
+extern	int16_t ar5210GetNoiseFloor(struct ath_hal *);
+extern	int16_t ar5210GetNfAdjust(struct ath_hal *,
+		const HAL_CHANNEL_INTERNAL *);
+extern	HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);
+extern	HAL_BOOL ar5210SetTransmitPower(struct ath_hal *, HAL_CHANNEL *);
+extern	HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+extern	HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);
+
+extern  HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,
+		const HAL_TXQ_INFO *qInfo);
+extern	HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,
+		HAL_TXQ_INFO *qInfo);
+extern	int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
+		const HAL_TXQ_INFO *qInfo);
+extern	HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);
+extern	HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);
+extern	uint32_t ar5210GetTxDP(struct ath_hal *, u_int);
+extern	HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp);
+extern	HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);
+extern	uint32_t ar5210NumTxPending(struct ath_hal *, u_int);
+extern	HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int);
+extern	HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int);
+extern	HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *,
+		u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
+		u_int txRate0, u_int txRetries0,
+		u_int keyIx, u_int antMode, u_int flags,
+		u_int rtsctsRate, u_int rtsctsDuration,
+                u_int compicvLen, u_int compivLen, u_int comp);
+extern	HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,
+		u_int txRate1, u_int txRetries1,
+		u_int txRate2, u_int txRetries2,
+		u_int txRate3, u_int txRetries3);
+extern	HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,
+		u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
+		const struct ath_desc *ds0);
+extern	HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,
+		struct ath_desc *, struct ath_tx_status *);
+extern  void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
+extern  void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
+
+extern	uint32_t ar5210GetRxDP(struct ath_hal *);
+extern	void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp);
+extern	void ar5210EnableReceive(struct ath_hal *);
+extern	HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);
+extern	void ar5210StartPcuReceive(struct ath_hal *);
+extern	void ar5210StopPcuReceive(struct ath_hal *);
+extern	void ar5210SetMulticastFilter(struct ath_hal *,
+		uint32_t filter0, uint32_t filter1);
+extern	HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t);
+extern	HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t);
+extern	uint32_t ar5210GetRxFilter(struct ath_hal *);
+extern	void ar5210SetRxFilter(struct ath_hal *, uint32_t);
+extern	HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *,
+		uint32_t, u_int flags);
+extern	HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *,
+		uint32_t, struct ath_desc *, uint64_t,
+		struct ath_rx_status *);
+
+extern	void ar5210GetMacAddress(struct ath_hal *, uint8_t *);
+extern	HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);
+extern	void ar5210GetBssIdMask(struct ath_hal *, uint8_t *);
+extern	HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *);
+extern	HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data);
+extern	HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data);
+extern	HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
+		uint16_t, HAL_STATUS *);
+extern	u_int ar5210GetWirelessModes(struct ath_hal *ah);
+extern	void ar5210EnableRfKill(struct ath_hal *);
+extern	HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern	uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
+extern	void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);
+extern	void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE);
+extern	u_int ar5210GetDefAntenna(struct ath_hal *);
+extern	void ar5210SetDefAntenna(struct ath_hal *, u_int);
+extern	HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *);
+extern	HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
+extern	void ar5210WriteAssocid(struct ath_hal *,
+		const uint8_t *bssid, uint16_t assocId);
+extern	uint32_t ar5210GetTsf32(struct ath_hal *);
+extern	uint64_t ar5210GetTsf64(struct ath_hal *);
+extern	void ar5210ResetTsf(struct ath_hal *);
+extern	uint32_t ar5210GetRandomSeed(struct ath_hal *);
+extern	HAL_BOOL ar5210DetectCardPresent(struct ath_hal *);
+extern	void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);
+extern	void ar5210EnableHwEncryption(struct ath_hal *);
+extern	void ar5210DisableHwEncryption(struct ath_hal *);
+extern	HAL_RFGAIN ar5210GetRfgain(struct ath_hal *);
+extern	HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int);
+extern	u_int ar5210GetSifsTime(struct ath_hal *);
+extern	HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int);
+extern	u_int ar5210GetSlotTime(struct ath_hal *);
+extern	HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int);
+extern	u_int ar5210GetAckTimeout(struct ath_hal *);
+extern	HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int);
+extern	u_int ar5210GetAckCTSRate(struct ath_hal *);
+extern	HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int);
+extern	u_int ar5210GetCTSTimeout(struct ath_hal *);
+extern  HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int);
+void 	ar5210SetCoverageClass(struct ath_hal *, uint8_t, int);
+extern	HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
+		uint32_t, uint32_t *);
+extern	HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
+		uint32_t, uint32_t, HAL_STATUS *);
+extern	HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
+		const void *args, uint32_t argsize,
+		void **result, uint32_t *resultsize);
+
+extern	u_int ar5210GetKeyCacheSize(struct ath_hal *);
+extern	HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
+extern	HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);
+extern	HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
+                       const HAL_KEYVAL *, const uint8_t *mac, int xorKey);
+extern	HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,
+			uint16_t, const uint8_t *);
+
+extern	HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest,
+		int setChip);
+extern	HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);
+
+extern	void ar5210SetBeaconTimers(struct ath_hal *,
+		const HAL_BEACON_TIMERS *);
+extern	void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t);
+extern	void ar5210SetStaBeaconTimers(struct ath_hal *,
+		const HAL_BEACON_STATE *);
+extern	void ar5210ResetStaBeaconTimers(struct ath_hal *);
+
+extern	HAL_BOOL ar5210IsInterruptPending(struct ath_hal *);
+extern	HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *);
+extern	HAL_INT ar5210GetInterrupts(struct ath_hal *);
+extern	HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);
+
+extern	const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);
+
+extern	HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );
+extern	void ar5210AniPoll(struct ath_hal *, const HAL_NODE_STATS *, HAL_CHANNEL *);
+extern	void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
+#endif /* _ATH_AR5210_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_attach.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_attach.c
new file mode 100644
index 0000000..7259f09
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_attach.c
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_attach.c,v 1.9 2008/11/11 02:40:13 sam Exp $
+ */
+#include <sys/bus.h>
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+#include "ar5210/ar5210phy.h"
+
+#include "ah_eeprom_v1.h"
+
+static	HAL_BOOL ar5210GetChannelEdges(struct ath_hal *,
+		uint16_t flags, uint16_t *low, uint16_t *high);
+static	HAL_BOOL ar5210GetChipPowerLimits(struct ath_hal *ah,
+		HAL_CHANNEL *chans, uint32_t nchans);
+
+static const struct ath_hal_private ar5210hal = {{
+	.ah_magic			= AR5210_MAGIC,
+	.ah_abi				= HAL_ABI_VERSION,
+	.ah_countryCode			= CTRY_DEFAULT,
+
+	.ah_getRateTable		= ar5210GetRateTable,
+	.ah_detach			= ar5210Detach,
+
+	/* Reset Functions */
+	.ah_reset			= ar5210Reset,
+	.ah_phyDisable			= ar5210PhyDisable,
+	.ah_disable			= ar5210Disable,
+	.ah_setPCUConfig		= ar5210SetPCUConfig,
+	.ah_perCalibration		= ar5210PerCalibration,
+	.ah_perCalibrationN		= ar5210PerCalibrationN,
+	.ah_resetCalValid		= ar5210ResetCalValid,
+	.ah_setTxPowerLimit		= ar5210SetTxPowerLimit,
+	.ah_getChanNoise		= ath_hal_getChanNoise,
+
+	/* Transmit functions */
+	.ah_updateTxTrigLevel		= ar5210UpdateTxTrigLevel,
+	.ah_setupTxQueue		= ar5210SetupTxQueue,
+	.ah_setTxQueueProps             = ar5210SetTxQueueProps,
+	.ah_getTxQueueProps             = ar5210GetTxQueueProps,
+	.ah_releaseTxQueue		= ar5210ReleaseTxQueue,
+	.ah_resetTxQueue		= ar5210ResetTxQueue,
+	.ah_getTxDP			= ar5210GetTxDP,
+	.ah_setTxDP			= ar5210SetTxDP,
+	.ah_numTxPending		= ar5210NumTxPending,
+	.ah_startTxDma			= ar5210StartTxDma,
+	.ah_stopTxDma			= ar5210StopTxDma,
+	.ah_setupTxDesc			= ar5210SetupTxDesc,
+	.ah_setupXTxDesc		= ar5210SetupXTxDesc,
+	.ah_fillTxDesc			= ar5210FillTxDesc,
+	.ah_procTxDesc			= ar5210ProcTxDesc,
+	.ah_getTxIntrQueue		= ar5210GetTxIntrQueue,
+	.ah_reqTxIntrDesc 		= ar5210IntrReqTxDesc,
+
+	/* RX Functions */
+	.ah_getRxDP			= ar5210GetRxDP,
+	.ah_setRxDP			= ar5210SetRxDP,
+	.ah_enableReceive		= ar5210EnableReceive,
+	.ah_stopDmaReceive		= ar5210StopDmaReceive,
+	.ah_startPcuReceive		= ar5210StartPcuReceive,
+	.ah_stopPcuReceive		= ar5210StopPcuReceive,
+	.ah_setMulticastFilter		= ar5210SetMulticastFilter,
+	.ah_setMulticastFilterIndex	= ar5210SetMulticastFilterIndex,
+	.ah_clrMulticastFilterIndex	= ar5210ClrMulticastFilterIndex,
+	.ah_getRxFilter			= ar5210GetRxFilter,
+	.ah_setRxFilter			= ar5210SetRxFilter,
+	.ah_setupRxDesc			= ar5210SetupRxDesc,
+	.ah_procRxDesc			= ar5210ProcRxDesc,
+	.ah_rxMonitor			= ar5210AniPoll,
+	.ah_procMibEvent		= ar5210MibEvent,
+
+	/* Misc Functions */
+	.ah_getCapability		= ar5210GetCapability,
+	.ah_setCapability		= ar5210SetCapability,
+	.ah_getDiagState		= ar5210GetDiagState,
+	.ah_getMacAddress		= ar5210GetMacAddress,
+	.ah_setMacAddress		= ar5210SetMacAddress,
+	.ah_getBssIdMask		= ar5210GetBssIdMask,
+	.ah_setBssIdMask		= ar5210SetBssIdMask,
+	.ah_setRegulatoryDomain		= ar5210SetRegulatoryDomain,
+	.ah_setLedState			= ar5210SetLedState,
+	.ah_writeAssocid		= ar5210WriteAssocid,
+	.ah_gpioCfgInput		= ar5210GpioCfgInput,
+	.ah_gpioCfgOutput		= ar5210GpioCfgOutput,
+	.ah_gpioGet			= ar5210GpioGet,
+	.ah_gpioSet			= ar5210GpioSet,
+	.ah_gpioSetIntr			= ar5210Gpio0SetIntr,
+	.ah_getTsf32			= ar5210GetTsf32,
+	.ah_getTsf64			= ar5210GetTsf64,
+	.ah_resetTsf			= ar5210ResetTsf,
+	.ah_detectCardPresent		= ar5210DetectCardPresent,
+	.ah_updateMibCounters		= ar5210UpdateMibCounters,
+	.ah_getRfGain			= ar5210GetRfgain,
+	.ah_getDefAntenna		= ar5210GetDefAntenna,
+	.ah_setDefAntenna		= ar5210SetDefAntenna,
+	.ah_getAntennaSwitch		= ar5210GetAntennaSwitch,
+	.ah_setAntennaSwitch		= ar5210SetAntennaSwitch,
+	.ah_setSifsTime			= ar5210SetSifsTime,
+	.ah_getSifsTime			= ar5210GetSifsTime,
+	.ah_setSlotTime			= ar5210SetSlotTime,
+	.ah_getSlotTime			= ar5210GetSlotTime,
+	.ah_setAckTimeout		= ar5210SetAckTimeout,
+	.ah_getAckTimeout		= ar5210GetAckTimeout,
+	.ah_setAckCTSRate		= ar5210SetAckCTSRate,
+	.ah_getAckCTSRate		= ar5210GetAckCTSRate,
+	.ah_setCTSTimeout		= ar5210SetCTSTimeout,
+	.ah_getCTSTimeout		= ar5210GetCTSTimeout,
+	.ah_setDecompMask               = ar5210SetDecompMask,
+	.ah_setCoverageClass            = ar5210SetCoverageClass,
+
+	/* Key Cache Functions */
+	.ah_getKeyCacheSize		= ar5210GetKeyCacheSize,
+	.ah_resetKeyCacheEntry		= ar5210ResetKeyCacheEntry,
+	.ah_isKeyCacheEntryValid	= ar5210IsKeyCacheEntryValid,
+	.ah_setKeyCacheEntry		= ar5210SetKeyCacheEntry,
+	.ah_setKeyCacheEntryMac		= ar5210SetKeyCacheEntryMac,
+
+	/* Power Management Functions */
+	.ah_setPowerMode		= ar5210SetPowerMode,
+	.ah_getPowerMode		= ar5210GetPowerMode,
+
+	/* Beacon Functions */
+	.ah_setBeaconTimers		= ar5210SetBeaconTimers,
+	.ah_beaconInit			= ar5210BeaconInit,
+	.ah_setStationBeaconTimers	= ar5210SetStaBeaconTimers,
+	.ah_resetStationBeaconTimers	= ar5210ResetStaBeaconTimers,
+
+	/* Interrupt Functions */
+	.ah_isInterruptPending		= ar5210IsInterruptPending,
+	.ah_getPendingInterrupts	= ar5210GetPendingInterrupts,
+	.ah_getInterrupts		= ar5210GetInterrupts,
+	.ah_setInterrupts		= ar5210SetInterrupts },
+
+	.ah_getChannelEdges		= ar5210GetChannelEdges,
+	.ah_getWirelessModes		= ar5210GetWirelessModes,
+	.ah_eepromRead			= ar5210EepromRead,
+#ifdef AH_SUPPORT_WRITE_EEPROM
+	.ah_eepromWrite			= ar5210EepromWrite,
+#endif
+	.ah_gpioCfgInput		= ar5210GpioCfgInput,
+	.ah_gpioCfgOutput		= ar5210GpioCfgOutput,
+	.ah_gpioGet			= ar5210GpioGet,
+	.ah_gpioSet			= ar5210GpioSet,
+	.ah_gpioSetIntr			= ar5210Gpio0SetIntr,
+	.ah_getChipPowerLimits		= ar5210GetChipPowerLimits,
+};
+
+static HAL_BOOL ar5210FillCapabilityInfo(struct ath_hal *ah);
+
+/*
+ * Attach for an AR5210 part.
+ */
+static struct ath_hal *
+ar5210Attach(uint16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh,
+	HAL_STATUS *status)
+{
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+	struct ath_hal_5210 *ahp;
+	struct ath_hal *ah;
+	uint32_t revid, pcicfg;
+	uint16_t eeval;
+	HAL_STATUS ecode;
+	int i;
+
+	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH,
+	    "%s: devid 0x%x sc %p st %p sh %p\n", __func__, devid,
+	    sc, (void*) st, (void*) sh);
+
+	/* NB: memory is returned zero'd */
+	ahp = ath_hal_malloc(sizeof (struct ath_hal_5210));
+	if (ahp == AH_NULL) {
+		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+		    "%s: no memory for state block\n", __func__);
+		ecode = HAL_ENOMEM;
+		goto bad;
+	}
+	ah = &ahp->ah_priv.h;
+	/* set initial values */
+	OS_MEMCPY(&ahp->ah_priv, &ar5210hal, sizeof(struct ath_hal_private));
+	ah->ah_sc = sc;
+	ah->ah_st = st;
+	ah->ah_sh = sh;
+
+	ah->ah_devid = devid;			/* NB: for AH_DEBUG_ALQ */
+	AH_PRIVATE(ah)->ah_devid = devid;
+	AH_PRIVATE(ah)->ah_subvendorid = 0;	/* XXX */
+
+	AH_PRIVATE(ah)->ah_powerLimit = AR5210_MAX_RATE_POWER;
+	AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX;	/* no scaling */
+
+	ahp->ah_powerMode = HAL_PM_UNDEFINED;
+	ahp->ah_staId1Defaults = 0;
+	ahp->ah_rssiThr = INIT_RSSI_THR;
+	ahp->ah_sifstime = (u_int) -1;
+	ahp->ah_slottime = (u_int) -1;
+	ahp->ah_acktimeout = (u_int) -1;
+	ahp->ah_ctstimeout = (u_int) -1;
+
+	if (!ar5210ChipReset(ah, AH_NULL)) {	/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
+		    __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+	/* Read Revisions from Chips */
+	AH_PRIVATE(ah)->ah_macVersion = 1;
+	AH_PRIVATE(ah)->ah_macRev = OS_REG_READ(ah, AR_SREV) & 0xff;
+	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIPID);
+	AH_PRIVATE(ah)->ah_analog2GhzRev = 0;
+
+	/* Read Radio Chip Rev Extract */
+	OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);
+	for (i = 0; i < 4; i++)
+		OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);
+	revid = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 28) & 0xf;
+
+	/* Chip labelling is 1 greater than revision register for AR5110 */
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ath_hal_reverseBits(revid, 4) + 1;
+
+	/*
+	 * Read all the settings from the EEPROM and stash
+	 * ones we'll use later.
+	 */
+	pcicfg = OS_REG_READ(ah, AR_PCICFG);
+	OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL);
+	ecode = ath_hal_v1EepromAttach(ah);
+	if (ecode != HAL_OK) {
+		goto eebad;
+	}
+	ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot read regulatory domain from EEPROM\n",
+		    __func__);
+		goto eebad;
+        }
+	AH_PRIVATE(ah)->ah_currentRD = eeval;
+	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error getting mac address from EEPROM\n", __func__);
+		goto eebad;
+        }
+	OS_REG_WRITE(ah, AR_PCICFG, pcicfg);	/* disable EEPROM access */
+
+	AH_PRIVATE(ah)->ah_getNfAdjust = ar5210GetNfAdjust;
+
+	/*
+	 * Got everything we need now to setup the capabilities.
+	 */
+	(void) ar5210FillCapabilityInfo(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
+
+	return ah;
+eebad:
+	OS_REG_WRITE(ah, AR_PCICFG, pcicfg);	/* disable EEPROM access */
+bad:
+	if (ahp)
+		ath_hal_free(ahp);
+	if (status)
+		*status = ecode;
+	return AH_NULL;
+#undef N
+}
+
+void
+ar5210Detach(struct ath_hal *ah)
+{
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
+
+	HALASSERT(ah != AH_NULL);
+	HALASSERT(ah->ah_magic == AR5210_MAGIC);
+
+	ath_hal_eepromDetach(ah);
+	ath_hal_free(ah);
+}
+
+/*
+ * Store the channel edges for the requested operational mode
+ */
+static HAL_BOOL
+ar5210GetChannelEdges(struct ath_hal *ah,
+	uint16_t flags, uint16_t *low, uint16_t *high)
+{
+	if (flags & CHANNEL_5GHZ) {
+		*low = 5120;
+		*high = 5430;
+		return AH_TRUE;
+	} else {
+		return AH_FALSE;
+	}
+}
+
+static HAL_BOOL
+ar5210GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans)
+{
+	HAL_CHANNEL *chan;
+	int i;
+
+	/* XXX fill in, this is just a placeholder */
+	for (i = 0; i < nchans; i++) {
+		chan = &chans[i];
+		HALDEBUG(ah, HAL_DEBUG_ATTACH,
+		    "%s: no min/max power for %u/0x%x\n",
+		    __func__, chan->channel, chan->channelFlags);
+		chan->maxTxPower = AR5210_MAX_RATE_POWER;
+		chan->minTxPower = 0;
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Fill all software cached or static hardware state information.
+ */
+static HAL_BOOL
+ar5210FillCapabilityInfo(struct ath_hal *ah)
+{
+	struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
+	HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
+
+	pCap->halWirelessModes |= HAL_MODE_11A;
+
+	pCap->halLow5GhzChan = 5120;
+	pCap->halHigh5GhzChan = 5430;
+
+	pCap->halSleepAfterBeaconBroken = AH_TRUE;
+	pCap->halPSPollBroken = AH_FALSE;
+
+	pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
+	pCap->halKeyCacheSize = 64;
+
+	/* XXX not needed */
+	pCap->halChanHalfRate = AH_FALSE;
+	pCap->halChanQuarterRate = AH_FALSE;
+
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL)) {
+		/*
+		 * Setup initial rfsilent settings based on the EEPROM
+		 * contents.  Pin 0, polarity 0 is fixed; record this
+		 * using the EEPROM format found in later parts.
+		 */
+		ahpriv->ah_rfsilent = SM(0, AR_EEPROM_RFSILENT_GPIO_SEL)
+				    | SM(0, AR_EEPROM_RFSILENT_POLARITY);
+		ahpriv->ah_rfkillEnabled = AH_TRUE;
+		pCap->halRfSilentSupport = AH_TRUE;
+	}
+
+	pCap->halTstampPrecision = 15;		/* NB: s/w extended from 13 */
+
+	ahpriv->ah_rxornIsFatal = AH_TRUE;
+	return AH_TRUE;
+}
+
+static const char*
+ar5210Probe(uint16_t vendorid, uint16_t devid)
+{
+	if (vendorid == ATHEROS_VENDOR_ID &&
+	    (devid == AR5210_PROD || devid == AR5210_DEFAULT))
+		return "Atheros 5210";
+	return AH_NULL;
+}
+AH_CHIP(AR5210, ar5210Probe, ar5210Attach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_beacon.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_beacon.c
new file mode 100644
index 0000000..680e2de
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_beacon.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_beacon.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_desc.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+#include "ar5210/ar5210desc.h"
+
+/*
+ * Initialize all of the hardware registers used to send beacons.
+ */
+void
+ar5210SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
+{
+
+	OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
+	OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
+	OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
+	OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
+	/*
+	 * Set the Beacon register after setting all timers.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
+}
+
+/*
+ * Legacy api to Initialize all of the beacon registers.
+ */
+void
+ar5210BeaconInit(struct ath_hal *ah,
+	uint32_t next_beacon, uint32_t beacon_period)
+{
+	HAL_BEACON_TIMERS bt;
+
+	bt.bt_nexttbtt = next_beacon;
+
+	if (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) {
+		bt.bt_nextdba = (next_beacon -
+			ath_hal_dma_beacon_response_time) << 3;	/* 1/8 TU */
+		bt.bt_nextswba = (next_beacon -
+			ath_hal_sw_beacon_response_time) << 3;	/* 1/8 TU */
+		/*
+		 * The SWBA interrupt is not used for beacons in ad hoc mode
+		 * as we don't yet support ATIMs. So since the beacon never
+		 * changes, the beacon descriptor is set up once and read
+		 * into a special HW buffer, from which it will be
+		 * automagically retrieved at each DMA Beacon Alert (DBA).
+		 */
+
+		/* Set the ATIM window */
+		bt.bt_nextatim = next_beacon + 0;	/* NB: no ATIMs */
+	} else {
+		bt.bt_nextdba = ~0;
+		bt.bt_nextswba = ~0;
+		bt.bt_nextatim = 1;
+	}
+	bt.bt_intval = beacon_period &
+		(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
+	ar5210SetBeaconTimers(ah, &bt);
+}
+
+void
+ar5210ResetStaBeaconTimers(struct ath_hal *ah)
+{
+	uint32_t val;
+
+	OS_REG_WRITE(ah, AR_TIMER0, 0);		/* no beacons */
+	val = OS_REG_READ(ah, AR_STA_ID1);
+	val |= AR_STA_ID1_NO_PSPOLL;		/* XXX */
+	/* tell the h/w that the associated AP is not PCF capable */
+	OS_REG_WRITE(ah, AR_STA_ID1,
+		val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
+	OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
+}
+
+/*
+ * Set all the beacon related bits on the h/w for stations
+ * i.e. initializes the corresponding h/w timers;
+ * also tells the h/w whether to anticipate PCF beacons
+ *
+ * dtim_count and cfp_count from the current beacon - their current
+ * values aren't necessarily maintained in the device struct
+ */
+void
+ar5210SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
+
+	HALASSERT(bs->bs_intval != 0);
+	/* if the AP will do PCF */
+	if (bs->bs_cfpmaxduration != 0) {
+		/* tell the h/w that the associated AP is PCF capable */
+		OS_REG_WRITE(ah, AR_STA_ID1,
+			(OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA)
+			| AR_STA_ID1_PCF);
+
+		/* set CFP_PERIOD(1.024ms) register */
+		OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
+
+		/* set CFP_DUR(1.024ms) register to max cfp duration */
+		OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
+
+		/* set TIMER2(128us) to anticipated time of next CFP */
+		OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
+	} else {
+		/* tell the h/w that the associated AP is not PCF capable */
+		OS_REG_WRITE(ah, AR_STA_ID1,
+			OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
+	}
+
+	/*
+	 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
+	 */
+	OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
+
+	/*
+	 * Start the beacon timers by setting the BEACON register
+	 * to the beacon interval; also write the tim offset which
+	 * we should know by now.  The code, in ar5211WriteAssocid,
+	 * also sets the tim offset once the AID is known which can
+	 * be left as such for now.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON, 
+		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
+		| SM(bs->bs_intval, AR_BEACON_PERIOD)
+		| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
+	);
+
+	/*
+	 * Configure the BMISS interrupt.  Note that we
+	 * assume the caller blocks interrupts while enabling
+	 * the threshold.
+	 */
+
+	/*
+	 * Interrupt works only on Crete.
+	 */
+	if (AH_PRIVATE(ah)->ah_macRev < AR_SREV_CRETE)
+		return;
+	/*
+	 * Counter is only 3-bits.
+	 * Count of 0 with BMISS interrupt enabled will hang the system
+	 * with too many interrupts
+	 */
+	if (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_CRETE &&
+	    (bs->bs_bmissthreshold&7) == 0) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s: invalid beacon miss threshold %u\n",
+			__func__, bs->bs_bmissthreshold);
+#endif
+		return;
+	}
+#define	BMISS_MAX	(AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S)
+	/*
+	 * Configure the BMISS interrupt.  Note that we
+	 * assume the caller blocks interrupts while enabling
+	 * the threshold.
+	 *
+	 * NB: the beacon miss count field is only 3 bits which
+	 *     is much smaller than what's found on later parts;
+	 *     clamp overflow values as a safeguard.
+	 */
+	ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
+			| SM(bs->bs_bmissthreshold > BMISS_MAX ?
+				BMISS_MAX : bs->bs_bmissthreshold,
+			     AR_RSSI_THR_BM_THR);
+	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
+#undef BMISS_MAX
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_interrupts.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_interrupts.c
new file mode 100644
index 0000000..ccc2332
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_interrupts.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_interrupts.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+
+/*
+ * Return non-zero if an interrupt is pending.
+ */
+HAL_BOOL
+ar5210IsInterruptPending(struct ath_hal *ah)
+{
+	return (OS_REG_READ(ah, AR_INTPEND) ? AH_TRUE : AH_FALSE);
+}
+
+/*
+ * Read the Interrupt Status Register value and return
+ * an abstracted bitmask of the data found in the ISR.
+ * Note that reading the ISR clear pending interrupts.
+ */
+HAL_BOOL
+ar5210GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
+{
+#define	AR_FATAL_INT \
+    (AR_ISR_MCABT_INT | AR_ISR_SSERR_INT | AR_ISR_DPERR_INT | AR_ISR_RXORN_INT)
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	uint32_t isr;
+
+	isr = OS_REG_READ(ah, AR_ISR);
+	if (isr == 0xffffffff) {
+		*masked = 0;
+		return AH_FALSE;
+	}
+
+	/*
+	 * Mask interrupts that have no device-independent
+	 * representation; these are added back below.  We
+	 * also masked with the abstracted IMR to insure no
+	 * status bits leak through that weren't requested
+	 * (e.g. RXNOFRM) and that might confuse the caller.
+	 */
+	*masked = (isr & HAL_INT_COMMON) & ahp->ah_maskReg;
+
+	if (isr & AR_FATAL_INT)
+		*masked |= HAL_INT_FATAL;
+	if (isr & (AR_ISR_RXOK_INT | AR_ISR_RXERR_INT))
+		*masked |= HAL_INT_RX;
+	if (isr & (AR_ISR_TXOK_INT | AR_ISR_TXDESC_INT | AR_ISR_TXERR_INT | AR_ISR_TXEOL_INT))
+		*masked |= HAL_INT_TX;
+
+	/*
+	 * On fatal errors collect ISR state for debugging.
+	 */
+	if (*masked & HAL_INT_FATAL) {
+		AH_PRIVATE(ah)->ah_fatalState[0] = isr;
+	}
+
+	return AH_TRUE;
+#undef AR_FATAL_INT
+}
+
+HAL_INT
+ar5210GetInterrupts(struct ath_hal *ah)
+{
+	return AH5210(ah)->ah_maskReg;
+}
+
+HAL_INT
+ar5210SetInterrupts(struct ath_hal *ah, HAL_INT ints)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	uint32_t omask = ahp->ah_maskReg;
+	uint32_t mask;
+
+	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
+	    __func__, omask, ints);
+
+	/*
+	 * Disable interrupts here before reading & modifying
+	 * the mask so that the ISR does not modify the mask
+	 * out from under us.
+	 */
+	if (omask & HAL_INT_GLOBAL) {
+		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
+		OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+	}
+
+	mask = ints & HAL_INT_COMMON;
+	if (ints & HAL_INT_RX)
+		mask |= AR_IMR_RXOK_INT | AR_IMR_RXERR_INT;
+	if (ints & HAL_INT_TX) {
+		if (ahp->ah_txOkInterruptMask)
+			mask |= AR_IMR_TXOK_INT;
+		if (ahp->ah_txErrInterruptMask)
+			mask |= AR_IMR_TXERR_INT;
+		if (ahp->ah_txDescInterruptMask)
+			mask |= AR_IMR_TXDESC_INT;
+		if (ahp->ah_txEolInterruptMask)
+			mask |= AR_IMR_TXEOL_INT;
+	}
+
+	/* Write the new IMR and store off our SW copy. */
+	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
+	OS_REG_WRITE(ah, AR_IMR, mask);
+	ahp->ah_maskReg = ints;
+
+	/* Re-enable interrupts as appropriate. */
+	if (ints & HAL_INT_GLOBAL) {
+		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
+		OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+	}
+
+	return omask;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_keycache.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_keycache.c
new file mode 100644
index 0000000..9594ce3
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_keycache.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_keycache.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+
+#define	AR_KEYTABLE_SIZE	64
+#define	KEY_XOR			0xaa
+
+/*
+ * Return the size of the hardware key cache.
+ */
+u_int
+ar5210GetKeyCacheSize(struct ath_hal *ah)
+{
+	return AR_KEYTABLE_SIZE;
+}
+
+/*
+ * Return the size of the hardware key cache.
+ */
+HAL_BOOL
+ar5210IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)
+{
+	if (entry < AR_KEYTABLE_SIZE) {
+		uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
+		if (val & AR_KEYTABLE_VALID)
+			return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Clear the specified key cache entry.
+ */
+HAL_BOOL
+ar5210ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)
+{
+	if (entry < AR_KEYTABLE_SIZE) {
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Sets the mac part of the specified key cache entry and mark it valid.
+ */
+HAL_BOOL
+ar5210SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
+{
+	uint32_t macHi, macLo;
+
+	if (entry < AR_KEYTABLE_SIZE) {
+		/*
+		 * Set MAC address -- shifted right by 1.  MacLo is
+		 * the 4 MSBs, and MacHi is the 2 LSBs.
+		 */
+		if (mac != AH_NULL) {
+			macHi = (mac[5] << 8) | mac[4];
+			macLo = (mac[3] << 24)| (mac[2] << 16)
+			      | (mac[1] << 8) | mac[0];
+			macLo >>= 1;
+			macLo |= (macHi & 1) << 31;	/* carry */
+			macHi >>= 1;
+		} else {
+			macLo = macHi = 0;
+		}
+
+		OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
+		OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry),
+			macHi | AR_KEYTABLE_VALID);
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Sets the contents of the specified key cache entry.
+ */
+HAL_BOOL
+ar5210SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
+                       const HAL_KEYVAL *k, const uint8_t *mac, int xorKey)
+{
+	uint32_t key0, key1, key2, key3, key4;
+	uint32_t keyType;
+	uint32_t xorMask= xorKey ?
+		(KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0;
+
+	if (entry >= AR_KEYTABLE_SIZE)
+		return AH_FALSE;
+	if (k->kv_type != HAL_CIPHER_WEP) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",
+		    __func__, k->kv_type);
+		return AH_FALSE;
+	}
+
+	/* NB: only WEP supported */
+	if (k->kv_len < 40 / NBBY)
+		return AH_FALSE;
+	if (k->kv_len <= 40 / NBBY)
+		keyType = AR_KEYTABLE_TYPE_40;
+	else if (k->kv_len <= 104 / NBBY)
+		keyType = AR_KEYTABLE_TYPE_104;
+	else
+		keyType = AR_KEYTABLE_TYPE_128;
+
+	key0 = LE_READ_4(k->kv_val+0) ^ xorMask;
+	key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff;
+	key2 = LE_READ_4(k->kv_val+6) ^ xorMask;
+	key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff;
+	key4 = LE_READ_4(k->kv_val+12) ^ xorMask;
+	if (k->kv_len <= 104 / NBBY)
+		key4 &= 0xff;
+
+	/*
+	 * Note: WEP key cache hardware requires that each double-word
+	 * pair be written in even/odd order (since the destination is
+	 * a 64-bit register).  Don't reorder these writes w/o
+	 * understanding this!
+	 */
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
+	OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
+	return ar5210SetKeyCacheEntryMac(ah, entry, mac);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_misc.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_misc.c
new file mode 100644
index 0000000..a673917
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_misc.c
@@ -0,0 +1,642 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_misc.c,v 1.6 2008/11/27 22:29:37 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+#include "ar5210/ar5210phy.h"
+
+#include "ah_eeprom_v1.h"
+
+#define	AR_NUM_GPIO	6		/* 6 GPIO bits */
+#define	AR_GPIOD_MASK	0x2f		/* 6-bit mask */
+
+void
+ar5210GetMacAddress(struct ath_hal *ah, uint8_t *mac)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
+}
+
+HAL_BOOL
+ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
+	return AH_TRUE;
+}
+
+void
+ar5210GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
+{
+	static const uint8_t ones[IEEE80211_ADDR_LEN] =
+		{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+	OS_MEMCPY(mask, ones, IEEE80211_ADDR_LEN);
+}
+
+HAL_BOOL
+ar5210SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
+{
+	return AH_FALSE;
+}
+
+/*
+ * Read 16 bits of data from the specified EEPROM offset.
+ */
+HAL_BOOL
+ar5210EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
+{
+	(void) OS_REG_READ(ah, AR_EP_AIR(off));	/* activate read op */
+	if (!ath_hal_wait(ah, AR_EP_STA,
+	    AR_EP_STA_RDCMPLT | AR_EP_STA_RDERR, AR_EP_STA_RDCMPLT)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n",
+		    __func__, AR_EP_AIR(off));
+		return AH_FALSE;
+	}
+	*data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff;
+	return AH_TRUE;
+}
+
+#ifdef AH_SUPPORT_WRITE_EEPROM
+/*
+ * Write 16 bits of data to the specified EEPROM offset.
+ */
+HAL_BOOL
+ar5210EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)
+{
+	return AH_FALSE;
+}
+#endif /* AH_SUPPORT_WRITE_EEPROM */
+
+/*
+ * Attempt to change the cards operating regulatory domain to the given value
+ */
+HAL_BOOL
+ar5210SetRegulatoryDomain(struct ath_hal *ah,
+	uint16_t regDomain, HAL_STATUS *status)
+{
+	HAL_STATUS ecode;
+
+	if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
+		ecode = HAL_EINVAL;
+		goto bad;
+	}
+	/*
+	 * Check if EEPROM is configured to allow this; must
+	 * be a proper version and the protection bits must
+	 * permit re-writing that segment of the EEPROM.
+	 */
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
+		ecode = HAL_EEWRITE;
+		goto bad;
+	}
+	ecode = HAL_EIO;		/* disallow all writes */
+bad:
+	if (status)
+		*status = ecode;
+	return AH_FALSE;
+}
+
+/*
+ * Return the wireless modes (a,b,g,t) supported by hardware.
+ *
+ * This value is what is actually supported by the hardware
+ * and is unaffected by regulatory/country code settings.
+ *
+ */
+u_int
+ar5210GetWirelessModes(struct ath_hal *ah)
+{
+	/* XXX could enable turbo mode but can't do all rates */
+	return HAL_MODE_11A;
+}
+
+/*
+ * Called if RfKill is supported (according to EEPROM).  Set the interrupt and
+ * GPIO values so the ISR and can disable RF on a switch signal
+ */
+void
+ar5210EnableRfKill(struct ath_hal *ah)
+{
+	uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
+	int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
+	int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
+
+	/*
+	 * If radio disable switch connection to GPIO bit 0 is enabled
+	 * program GPIO interrupt.
+	 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
+	 * verified that it is a later version of eeprom, it has a place for
+	 * rfkill bit and it is set to 1, indicating that GPIO bit 0 hardware
+	 * connection is present.
+	 */
+	ar5210Gpio0SetIntr(ah, select, (ar5210GpioGet(ah, select) == polarity));
+}
+
+/*
+ * Configure GPIO Output lines
+ */
+HAL_BOOL
+ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+{
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	OS_REG_WRITE(ah, AR_GPIOCR, 
+		  (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
+		| AR_GPIOCR_OUT1(gpio));
+
+	return AH_TRUE;
+}
+
+/*
+ * Configure GPIO Input lines
+ */
+HAL_BOOL
+ar5210GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
+{
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	OS_REG_WRITE(ah, AR_GPIOCR, 
+		  (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
+		| AR_GPIOCR_IN(gpio));
+
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - set output lines
+ */
+HAL_BOOL
+ar5210GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
+{
+	uint32_t reg;
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	reg =  OS_REG_READ(ah, AR_GPIODO);
+	reg &= ~(1 << gpio);
+	reg |= (val&1) << gpio;
+
+	OS_REG_WRITE(ah, AR_GPIODO, reg);
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - get input lines
+ */
+uint32_t
+ar5210GpioGet(struct ath_hal *ah, uint32_t gpio)
+{
+	if (gpio < AR_NUM_GPIO) {
+		uint32_t val = OS_REG_READ(ah, AR_GPIODI);
+		val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
+		return val;
+	} else  {
+		return 0xffffffff;
+	}
+}
+
+/*
+ * Set the GPIO 0 Interrupt
+ */
+void
+ar5210Gpio0SetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
+{
+	uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
+
+	/* Clear the bits that we will modify. */
+	val &= ~(AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_SELH | AR_GPIOCR_INT_ENA |
+			AR_GPIOCR_ALL(gpio));
+
+	val |= AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_ENA;
+	if (ilevel)
+		val |= AR_GPIOCR_INT_SELH;
+
+	/* Don't need to change anything for low level interrupt. */
+	OS_REG_WRITE(ah, AR_GPIOCR, val);
+
+	/* Change the interrupt mask. */
+	ar5210SetInterrupts(ah, AH5210(ah)->ah_maskReg | HAL_INT_GPIO);
+}
+
+/*
+ * Change the LED blinking pattern to correspond to the connectivity
+ */
+void
+ar5210SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
+{
+	uint32_t val;
+
+	val = OS_REG_READ(ah, AR_PCICFG);
+	switch (state) {
+	case HAL_LED_INIT:
+		val &= ~(AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT);
+		break;
+	case HAL_LED_RUN:
+		/* normal blink when connected */
+		val &= ~AR_PCICFG_LED_PEND;
+		val |= AR_PCICFG_LED_ACT;
+		break;
+	default:
+		val |= AR_PCICFG_LED_PEND;
+		val &= ~AR_PCICFG_LED_ACT;
+		break;
+	}
+	OS_REG_WRITE(ah, AR_PCICFG, val);
+}
+
+/*
+ * Return 1 or 2 for the corresponding antenna that is in use
+ */
+u_int
+ar5210GetDefAntenna(struct ath_hal *ah)
+{
+	uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
+	return (val & AR_STA_ID1_DEFAULT_ANTENNA ?  2 : 1);
+}
+
+void
+ar5210SetDefAntenna(struct ath_hal *ah, u_int antenna)
+{
+	uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
+
+	if (antenna != (val & AR_STA_ID1_DEFAULT_ANTENNA ?  2 : 1)) {
+		/*
+		 * Antenna change requested, force a toggle of the default.
+		 */
+		OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA);
+	}
+}
+
+HAL_ANT_SETTING
+ar5210GetAntennaSwitch(struct ath_hal *ah)
+{
+	return HAL_ANT_VARIABLE;
+}
+
+HAL_BOOL
+ar5210SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
+{
+	/* XXX not sure how to fix antenna */
+	return (settings == HAL_ANT_VARIABLE);
+}
+
+/*
+ * Change association related fields programmed into the hardware.
+ * Writing a valid BSSID to the hardware effectively enables the hardware
+ * to synchronize its TSF to the correct beacons and receive frames coming
+ * from that BSSID. It is called by the SME JOIN operation.
+ */
+void
+ar5210WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	/* XXX save bssid for possible re-use on reset */
+	OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
+	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
+	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
+				     ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
+	if (assocId == 0)
+		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);
+	else
+		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);
+}
+
+/*
+ * Get the current hardware tsf for stamlme.
+ */
+uint64_t
+ar5210GetTsf64(struct ath_hal *ah)
+{
+	uint32_t low1, low2, u32;
+
+	/* sync multi-word read */
+	low1 = OS_REG_READ(ah, AR_TSF_L32);
+	u32 = OS_REG_READ(ah, AR_TSF_U32);
+	low2 = OS_REG_READ(ah, AR_TSF_L32);
+	if (low2 < low1) {	/* roll over */
+		/*
+		 * If we are not preempted this will work.  If we are
+		 * then we re-reading AR_TSF_U32 does no good as the
+		 * low bits will be meaningless.  Likewise reading
+		 * L32, U32, U32, then comparing the last two reads
+		 * to check for rollover doesn't help if preempted--so
+		 * we take this approach as it costs one less PCI
+		 * read which can be noticeable when doing things
+		 * like timestamping packets in monitor mode.
+		 */
+		u32++;
+	}
+	return (((uint64_t) u32) << 32) | ((uint64_t) low2);
+}
+
+/*
+ * Get the current hardware tsf for stamlme.
+ */
+uint32_t
+ar5210GetTsf32(struct ath_hal *ah)
+{
+	return OS_REG_READ(ah, AR_TSF_L32);
+}
+
+/*
+ * Reset the current hardware tsf for stamlme
+ */
+void
+ar5210ResetTsf(struct ath_hal *ah)
+{
+	uint32_t val = OS_REG_READ(ah, AR_BEACON);
+
+	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
+}
+
+/*
+ * Grab a semi-random value from hardware registers - may not
+ * change often
+ */
+uint32_t
+ar5210GetRandomSeed(struct ath_hal *ah)
+{
+	uint32_t nf;
+
+	nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;
+	if (nf & 0x100)
+		nf = 0 - ((nf ^ 0x1ff) + 1);
+	return (OS_REG_READ(ah, AR_TSF_U32) ^
+		OS_REG_READ(ah, AR_TSF_L32) ^ nf);
+}
+
+/*
+ * Detect if our card is present
+ */
+HAL_BOOL
+ar5210DetectCardPresent(struct ath_hal *ah)
+{
+	/*
+	 * Read the Silicon Revision register and compare that
+	 * to what we read at attach time.  If the same, we say
+	 * a card/device is present.
+	 */
+	return (AH_PRIVATE(ah)->ah_macRev == (OS_REG_READ(ah, AR_SREV) & 0xff));
+}
+
+/*
+ * Update MIB Counters
+ */
+void
+ar5210UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)
+{
+	stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
+	stats->rts_bad	  += OS_REG_READ(ah, AR_RTS_FAIL);
+	stats->fcs_bad	  += OS_REG_READ(ah, AR_FCS_FAIL);
+	stats->rts_good	  += OS_REG_READ(ah, AR_RTS_OK);
+	stats->beacons	  += OS_REG_READ(ah, AR_BEACON_CNT);
+}
+
+HAL_BOOL
+ar5210SetSifsTime(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	if (us > ath_hal_mac_usec(ah, 0x7ff)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
+		    __func__, us);
+		ahp->ah_sifstime = (u_int) -1;	/* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS,
+		    ath_hal_mac_clks(ah, us));
+		ahp->ah_sifstime = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5210GetSifsTime(struct ath_hal *ah)
+{
+	u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff;
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+HAL_BOOL
+ar5210SetSlotTime(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
+		    __func__, us);
+		ahp->ah_slottime = (u_int) -1;	/* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_WRITE(ah, AR_SLOT_TIME, ath_hal_mac_clks(ah, us));
+		ahp->ah_slottime = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5210GetSlotTime(struct ath_hal *ah)
+{
+	u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff;
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+HAL_BOOL
+ar5210SetAckTimeout(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
+		    __func__, us);
+		ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
+			AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
+		ahp->ah_acktimeout = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5210GetAckTimeout(struct ath_hal *ah)
+{
+	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+u_int
+ar5210GetAckCTSRate(struct ath_hal *ah)
+{
+	return ((AH5210(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
+}
+
+HAL_BOOL
+ar5210SetAckCTSRate(struct ath_hal *ah, u_int high)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	if (high) {
+		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
+		ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
+	} else {
+		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
+		ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
+	}
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5210SetCTSTimeout(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
+		    __func__, us);
+		ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
+			AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
+		ahp->ah_ctstimeout = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5210GetCTSTimeout(struct ath_hal *ah)
+{
+	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+HAL_BOOL
+ar5210SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
+{
+	/* nothing to do */
+        return AH_TRUE;
+}
+
+void
+ar5210SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
+{
+}
+
+/*
+ * Control Adaptive Noise Immunity Parameters
+ */
+HAL_BOOL
+ar5210AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
+{
+	return AH_FALSE;
+}
+
+void
+ar5210AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats, HAL_CHANNEL *chan)
+{
+}
+
+void
+ar5210MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
+{
+}
+
+#define	AR_DIAG_SW_DIS_CRYPTO	(AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC)
+
+HAL_STATUS
+ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+	uint32_t capability, uint32_t *result)
+{
+
+	switch (type) {
+	case HAL_CAP_CIPHER:		/* cipher handled in hardware */
+		return (capability == HAL_CIPHER_WEP ? HAL_OK : HAL_ENOTSUPP);
+	default:
+		return ath_hal_getcapability(ah, type, capability, result);
+	}
+}
+
+HAL_BOOL
+ar5210SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+	uint32_t capability, uint32_t setting, HAL_STATUS *status)
+{
+
+	switch (type) {
+	case HAL_CAP_DIAG:		/* hardware diagnostic support */
+		/*
+		 * NB: could split this up into virtual capabilities,
+		 *     (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
+		 *     seems worth the additional complexity.
+		 */
+#ifdef AH_DEBUG
+		AH_PRIVATE(ah)->ah_diagreg = setting;
+#else
+		AH_PRIVATE(ah)->ah_diagreg = setting & 0x6;	/* ACK+CTS */
+#endif
+		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
+		return AH_TRUE;
+	case HAL_CAP_RXORN_FATAL:	/* HAL_INT_RXORN treated as fatal  */
+		return AH_FALSE;	/* NB: disallow */
+	default:
+		return ath_hal_setcapability(ah, type, capability,
+			setting, status);
+	}
+}
+
+HAL_BOOL
+ar5210GetDiagState(struct ath_hal *ah, int request,
+	const void *args, uint32_t argsize,
+	void **result, uint32_t *resultsize)
+{
+#ifdef AH_PRIVATE_DIAG
+	uint32_t pcicfg;
+	HAL_BOOL ok;
+
+	switch (request) {
+	case HAL_DIAG_EEPROM:
+		/* XXX */
+		break;
+	case HAL_DIAG_EEREAD:
+		if (argsize != sizeof(uint16_t))
+			return AH_FALSE;
+		pcicfg = OS_REG_READ(ah, AR_PCICFG);
+		OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL);
+		ok = ath_hal_eepromRead(ah, *(const uint16_t *)args, *result);
+		OS_REG_WRITE(ah, AR_PCICFG, pcicfg);
+		if (ok)
+			*resultsize = sizeof(uint16_t);
+		return ok;
+	}
+#endif
+	return ath_hal_getdiagstate(ah, request,
+		args, argsize, result, resultsize);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_phy.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_phy.c
new file mode 100644
index 0000000..14dc384
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_phy.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_phy.c,v 1.3 2008/11/10 01:19:37 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5210/ar5210.h"
+
+/* shorthands to compact tables for readability */
+#define	OFDM	IEEE80211_T_OFDM
+#define	TURBO	IEEE80211_T_TURBO
+
+HAL_RATE_TABLE ar5210_11a_table = {
+	8,  /* number of rates */
+	{ 0 },
+	{
+/*                                                  short            ctrl  */
+/*                valid                 rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, OFDM,    6000,     0x0b,    0x00, (0x80|12),   0 },
+/*   9 Mb */ {  AH_TRUE, OFDM,    9000,     0x0f,    0x00,        18,   0 },
+/*  12 Mb */ {  AH_TRUE, OFDM,   12000,     0x0a,    0x00, (0x80|24),   2 },
+/*  18 Mb */ {  AH_TRUE, OFDM,   18000,     0x0e,    0x00,        36,   2 },
+/*  24 Mb */ {  AH_TRUE, OFDM,   24000,     0x09,    0x00, (0x80|48),   4 },
+/*  36 Mb */ {  AH_TRUE, OFDM,   36000,     0x0d,    0x00,        72,   4 },
+/*  48 Mb */ {  AH_TRUE, OFDM,   48000,     0x08,    0x00,        96,   4 },
+/*  54 Mb */ {  AH_TRUE, OFDM,   54000,     0x0c,    0x00,       108,   4 }
+	},
+};
+
+HAL_RATE_TABLE ar5210_turbo_table = {
+	8,  /* number of rates */
+	{ 0 },
+	{
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, TURBO,   6000,    0x0b,    0x00, (0x80|12),   0 },
+/*   9 Mb */ {  AH_TRUE, TURBO,   9000,    0x0f,    0x00,        18,   0 },
+/*  12 Mb */ {  AH_TRUE, TURBO,  12000,    0x0a,    0x00, (0x80|24),   2 },
+/*  18 Mb */ {  AH_TRUE, TURBO,  18000,    0x0e,    0x00,        36,   2 },
+/*  24 Mb */ {  AH_TRUE, TURBO,  24000,    0x09,    0x00, (0x80|48),   4 },
+/*  36 Mb */ {  AH_TRUE, TURBO,  36000,    0x0d,    0x00,        72,   4 },
+/*  48 Mb */ {  AH_TRUE, TURBO,  48000,    0x08,    0x00,        96,   4 },
+/*  54 Mb */ {  AH_TRUE, TURBO,  54000,    0x0c,    0x00,       108,   4 }
+	},
+};
+
+#undef	OFDM
+#undef	TURBO
+
+const HAL_RATE_TABLE *
+ar5210GetRateTable(struct ath_hal *ah, u_int mode)
+{
+	HAL_RATE_TABLE *rt;
+	switch (mode) {
+	case HAL_MODE_11A:
+		rt = &ar5210_11a_table;
+		break;
+	case HAL_MODE_TURBO:
+		rt =  &ar5210_turbo_table;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",
+		    __func__, mode);
+		return AH_NULL;
+	}
+	ath_hal_setupratetable(ah, rt);
+	return rt;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_power.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_power.c
new file mode 100644
index 0000000..c2771f2
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_power.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_power.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+
+/*
+ * Notify Power Mgt is disabled in self-generated frames.
+ * If requested, set Power Mode of chip to auto/normal.
+ */
+static void
+ar5210SetPowerModeAuto(struct ath_hal *ah, int setChip)
+{
+	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);
+	if (setChip)
+		OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_ALLOW);
+}
+
+/*
+ * Notify Power Mgt is enabled in self-generated frames.
+ * If requested, force chip awake.
+ *
+ * Returns A_OK if chip is awake or successfully forced awake.
+ *
+ * WARNING WARNING WARNING
+ * There is a problem with the chip where sometimes it will not wake up.
+ */
+static HAL_BOOL
+ar5210SetPowerModeAwake(struct ath_hal *ah, int setChip)
+{
+#define	POWER_UP_TIME	2000
+	uint32_t val;
+	int i;
+
+	if (setChip) {
+		OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE);
+		OS_DELAY(2000);	/* Give chip the chance to awake */
+
+		for (i = POWER_UP_TIME / 200; i != 0; i--) {
+			val = OS_REG_READ(ah, AR_PCICFG);
+			if ((val & AR_PCICFG_SPWR_DN) == 0)
+				break;
+			OS_DELAY(200);
+			OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE,
+				AR_SCR_SLE_WAKE);
+		}
+		if (i == 0) {
+#ifdef AH_DEBUG
+			ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",
+				__func__, POWER_UP_TIME/20);
+#endif
+			return AH_FALSE;
+		}
+	} 
+
+	OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);
+	return AH_TRUE;
+#undef POWER_UP_TIME
+}
+
+/*
+ * Notify Power Mgt is disabled in self-generated frames.
+ * If requested, force chip to sleep.
+ */
+static void
+ar5210SetPowerModeSleep(struct ath_hal *ah, int setChip)
+{
+	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);
+	if (setChip)
+		OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
+}
+
+HAL_BOOL
+ar5210SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+#ifdef AH_DEBUG
+	static const char* modes[] = {
+		"AWAKE",
+		"FULL-SLEEP",
+		"NETWORK SLEEP",
+		"UNDEFINED"
+	};
+#endif
+	int status = AH_TRUE;
+
+	HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
+		modes[ahp->ah_powerMode], modes[mode],
+		setChip ? "set chip " : "");
+	switch (mode) {
+	case HAL_PM_AWAKE:
+		status = ar5210SetPowerModeAwake(ah, setChip);
+		break;
+	case HAL_PM_FULL_SLEEP:
+		ar5210SetPowerModeSleep(ah, setChip);
+		break;
+	case HAL_PM_NETWORK_SLEEP:
+		ar5210SetPowerModeAuto(ah, setChip);
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",
+		    __func__, mode);
+		return AH_FALSE;
+	}
+	ahp->ah_powerMode = mode;
+	return status; 
+}
+
+HAL_POWER_MODE
+ar5210GetPowerMode(struct ath_hal *ah)
+{
+	/* Just so happens the h/w maps directly to the abstracted value */
+	return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_recv.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_recv.c
new file mode 100644
index 0000000..489c55a
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_recv.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_recv.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_desc.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+#include "ar5210/ar5210desc.h"
+
+/*
+ * Get the RXDP.
+ */
+uint32_t
+ar5210GetRxDP(struct ath_hal *ah)
+{
+	return OS_REG_READ(ah, AR_RXDP);
+}
+
+/*
+ * Set the RxDP.
+ */
+void
+ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp)
+{
+	OS_REG_WRITE(ah, AR_RXDP, rxdp);
+}
+
+
+/*
+ * Set Receive Enable bits.
+ */
+void
+ar5210EnableReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
+}
+
+/*
+ * Stop Receive at the DMA engine
+ */
+HAL_BOOL
+ar5210StopDmaReceive(struct ath_hal *ah)
+{
+	int i;
+
+	OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);	/* Set receive disable bit */
+	for (i = 0; i < 1000; i++) {
+		if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
+			return AH_TRUE;
+		OS_DELAY(10);
+	}
+#ifdef AH_DEBUG
+	ath_hal_printf(ah, "ar5210: dma receive failed to stop in 10ms\n");
+	ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
+	ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW));
+#endif
+	return AH_FALSE;
+}
+
+/*
+ * Start Transmit at the PCU engine (unpause receive)
+ */
+void
+ar5210StartPcuReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_DIAG_SW,
+		OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
+}
+
+/*
+ * Stop Transmit at the PCU engine (pause receive)
+ */
+void
+ar5210StopPcuReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_DIAG_SW,
+		OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
+}
+
+/*
+ * Set multicast filter 0 (lower 32-bits)
+ *			   filter 1 (upper 32-bits)
+ */
+void
+ar5210SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
+{
+	OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
+	OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
+}
+
+/*
+ * Clear multicast filter by index
+ */
+HAL_BOOL
+ar5210ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
+{
+	uint32_t val;
+
+	if (ix >= 64)
+		return AH_FALSE;
+	if (ix >= 32) {
+		val = OS_REG_READ(ah, AR_MCAST_FIL1);
+		OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
+	} else {
+		val = OS_REG_READ(ah, AR_MCAST_FIL0);
+		OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Set multicast filter by index
+ */
+HAL_BOOL
+ar5210SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
+{
+	uint32_t val;
+
+	if (ix >= 64)
+		return AH_FALSE;
+	if (ix >= 32) {
+		val = OS_REG_READ(ah, AR_MCAST_FIL1);
+		OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
+	} else {
+		val = OS_REG_READ(ah, AR_MCAST_FIL0);
+		OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Return the receive packet filter.
+ */
+uint32_t
+ar5210GetRxFilter(struct ath_hal *ah)
+{
+	/* XXX can't be sure if promiscuous mode is set because of PHYRADAR */
+	return OS_REG_READ(ah, AR_RX_FILTER);
+}
+
+/*
+ * Turn off/on bits in the receive packet filter.
+ */
+void
+ar5210SetRxFilter(struct ath_hal *ah, uint32_t bits)
+{
+	if (bits & HAL_RX_FILTER_PHYRADAR) {
+		/* must enable promiscuous mode to get radar */
+		bits = (bits &~ HAL_RX_FILTER_PHYRADAR) | AR_RX_FILTER_PROMISCUOUS;
+	}
+	OS_REG_WRITE(ah, AR_RX_FILTER, bits);
+}
+
+/*
+ * Initialize RX descriptor, by clearing the status and clearing
+ * the size.  This is not strictly HW dependent, but we want the
+ * control and status words to be opaque above the hal.
+ */
+HAL_BOOL
+ar5210SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	uint32_t size, u_int flags)
+{
+	struct ar5210_desc *ads = AR5210DESC(ds);
+
+	(void) flags;
+
+	ads->ds_ctl0 = 0;
+	ads->ds_ctl1 = size & AR_BufLen;
+	if (ads->ds_ctl1 != size) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
+		    __func__, size);
+		return AH_FALSE;
+	}
+	if (flags & HAL_RXDESC_INTREQ)
+		ads->ds_ctl1 |= AR_RxInterReq;
+	ads->ds_status0 = ads->ds_status1 = 0;
+
+	return AH_TRUE;
+}
+
+/*
+ * Process an RX descriptor, and return the status to the caller.
+ * Copy some hardware specific items into the software portion
+ * of the descriptor.
+ *
+ * NB: the caller is responsible for validating the memory contents
+ *     of the descriptor (e.g. flushing any cached copy).
+ */
+HAL_STATUS
+ar5210ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	uint32_t pa, struct ath_desc *nds, uint64_t tsf,
+	struct ath_rx_status *rs)
+{
+	struct ar5210_desc *ads = AR5210DESC(ds);
+	struct ar5210_desc *ands = AR5210DESC(nds);
+	uint32_t now, rstamp;
+
+	if ((ads->ds_status1 & AR_Done) == 0)
+		return HAL_EINPROGRESS;
+	/*
+	 * Given the use of a self-linked tail be very sure that the hw is
+	 * done with this descriptor; the hw may have done this descriptor
+	 * once and picked it up again...make sure the hw has moved on.
+	 */
+	if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
+		return HAL_EINPROGRESS;
+
+	rs->rs_datalen = ads->ds_status0 & AR_DataLen;
+	rstamp = MS(ads->ds_status1, AR_RcvTimestamp);
+	/*
+	 * Convert timestamp.  The value in the
+	 * descriptor is bits [10..22] of the TSF.
+	 */
+	now = (OS_REG_READ(ah, AR_TSF_L32) >> 10) & 0xffff;
+	if ((now & 0x1fff) < rstamp)
+		rstamp |= (now - 0x2000) & 0xffff;
+	else
+		rstamp |= now;
+	/* NB: keep only 15 bits for consistency w/ other chips */
+	rs->rs_tstamp = rstamp & 0x7fff;
+	rs->rs_status = 0;
+	if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
+		if (ads->ds_status1 & AR_CRCErr)
+			rs->rs_status |= HAL_RXERR_CRC;
+		else if (ads->ds_status1 & AR_DecryptCRCErr)
+			rs->rs_status |= HAL_RXERR_DECRYPT;
+		else if (ads->ds_status1 & AR_FIFOOverrun)
+			rs->rs_status |= HAL_RXERR_FIFO;
+		else {
+			rs->rs_status |= HAL_RXERR_PHY;
+			rs->rs_phyerr =
+				(ads->ds_status1 & AR_PHYErr) >> AR_PHYErr_S;
+		}
+	}
+	/* XXX what about KeyCacheMiss? */
+	rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
+	if (ads->ds_status1 & AR_KeyIdxValid)
+		rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
+	else
+		rs->rs_keyix = HAL_RXKEYIX_INVALID;
+	/* NB: caller expected to do rate table mapping */
+	rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
+	rs->rs_antenna  = (ads->ds_status0 & AR_RcvAntenna) ? 1 : 0;
+	rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;
+
+	return HAL_OK;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_reset.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_reset.c
new file mode 100644
index 0000000..40c6768
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_reset.c
@@ -0,0 +1,1003 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_reset.c,v 1.8 2008/11/11 17:25:16 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+#include "ar5210/ar5210phy.h"
+
+#include "ah_eeprom_v1.h"
+
+typedef struct {
+	uint32_t	Offset;
+	uint32_t	Value;
+} REGISTER_VAL;
+
+static const REGISTER_VAL ar5k0007_init[] = {
+#include "ar5210/ar5k_0007.ini"
+};
+
+/* Default Power Settings for channels outside of EEPROM range */
+static const uint8_t ar5k0007_pwrSettings[17] = {
+/*	gain delta			pc dac */
+/* 54  48  36  24  18  12   9   54  48  36  24  18  12   9   6  ob  db	  */
+    9,  9,  0,  0,  0,  0,  0,   2,  2,  6,  6,  6,  6,  6,  6,  2,  2
+};
+
+/*
+ * The delay, in usecs, between writing AR_RC with a reset
+ * request and waiting for the chip to settle.  If this is
+ * too short then the chip does not come out of sleep state.
+ * Note this value was empirically derived and may be dependent
+ * on the host machine (don't know--the problem was identified
+ * on an IBM 570e laptop; 10us delays worked on other systems).
+ */
+#define	AR_RC_SETTLE_TIME	20000
+
+static HAL_BOOL ar5210SetResetReg(struct ath_hal *,
+		uint32_t resetMask, u_int delay);
+static HAL_BOOL ar5210SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+static void ar5210SetOperatingMode(struct ath_hal *, int opmode);
+
+/*
+ * Places the device in and out of reset and then places sane
+ * values in the registers based on EEPROM config, initialization
+ * vectors (as determined by the mode), and station configuration
+ *
+ * bChannelChange is used to preserve DMA/PCU registers across
+ * a HW Reset during channel change.
+ */
+HAL_BOOL
+ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
+	HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+{
+#define	N(a)	(sizeof (a) /sizeof (a[0]))
+#define	FAIL(_code)	do { ecode = _code; goto bad; } while (0)
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
+	HAL_CHANNEL_INTERNAL *ichan;
+	HAL_STATUS ecode;
+	uint32_t ledstate;
+	int i, q;
+
+	HALDEBUG(ah, HAL_DEBUG_RESET,
+	    "%s: opmode %u channel %u/0x%x %s channel\n", __func__,
+	    opmode, chan->channel, chan->channelFlags,
+	    bChannelChange ? "change" : "same");
+
+	if ((chan->channelFlags & CHANNEL_5GHZ) == 0) {
+		/* Only 11a mode */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5Ghz\n", __func__);
+		FAIL(HAL_EINVAL);
+	}
+	/*
+	 * Map public channel to private.
+	 */
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+	switch (opmode) {
+	case HAL_M_STA:
+	case HAL_M_IBSS:
+	case HAL_M_HOSTAP:
+	case HAL_M_MONITOR:
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
+		    __func__, opmode);
+		FAIL(HAL_EINVAL);
+		break;
+	}
+
+	ledstate = OS_REG_READ(ah, AR_PCICFG) &
+		(AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT);
+
+	if (!ar5210ChipReset(ah, chan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
+		    __func__);
+		FAIL(HAL_EIO);
+	}
+
+	OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
+	OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4));
+	ar5210SetOperatingMode(ah, opmode);
+
+	switch (opmode) {
+	case HAL_M_HOSTAP:
+		OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
+		OS_REG_WRITE(ah, AR_PCICFG,
+			AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL);
+		break;
+	case HAL_M_IBSS:
+		OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD);
+		OS_REG_WRITE(ah, AR_PCICFG,
+			AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL);
+		break;
+	case HAL_M_STA:
+		OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
+		OS_REG_WRITE(ah, AR_PCICFG,
+			AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL);
+		break;
+	case HAL_M_MONITOR:
+		OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
+		OS_REG_WRITE(ah, AR_PCICFG,
+			AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL);
+		break;
+	}
+
+	/* Restore previous led state */
+	OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
+
+	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
+	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
+
+	OS_REG_WRITE(ah, AR_TXDP0, 0);
+	OS_REG_WRITE(ah, AR_TXDP1, 0);
+	OS_REG_WRITE(ah, AR_RXDP, 0);
+
+	/*
+	 * Initialize interrupt state.
+	 */
+	(void) OS_REG_READ(ah, AR_ISR);		/* cleared on read */
+	OS_REG_WRITE(ah, AR_IMR, 0);
+	OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+	ahp->ah_maskReg = 0;
+
+	(void) OS_REG_READ(ah, AR_BSR);		/* cleared on read */
+	OS_REG_WRITE(ah, AR_TXCFG, AR_DMASIZE_128B);
+	OS_REG_WRITE(ah, AR_RXCFG, AR_DMASIZE_128B);
+
+	OS_REG_WRITE(ah, AR_TOPS, 8);		/* timeout prescale */
+	OS_REG_WRITE(ah, AR_RXNOFRM, 8);	/* RX no frame timeout */
+	OS_REG_WRITE(ah, AR_RPGTO, 0);		/* RX frame gap timeout */
+	OS_REG_WRITE(ah, AR_TXNOFRM, 0);	/* TX no frame timeout */
+
+	OS_REG_WRITE(ah, AR_SFR, 0);
+	OS_REG_WRITE(ah, AR_MIBC, 0);		/* unfreeze ctrs + clr state */
+	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
+	OS_REG_WRITE(ah, AR_CFP_DUR, 0);
+
+	ar5210SetRxFilter(ah, 0);		/* nothing for now */
+	OS_REG_WRITE(ah, AR_MCAST_FIL0, 0);	/* multicast filter */
+	OS_REG_WRITE(ah, AR_MCAST_FIL1, 0);	/* XXX was 2 */
+
+	OS_REG_WRITE(ah, AR_TX_MASK0, 0);
+	OS_REG_WRITE(ah, AR_TX_MASK1, 0);
+	OS_REG_WRITE(ah, AR_CLR_TMASK, 1);
+	OS_REG_WRITE(ah, AR_TRIG_LEV, 1);	/* minimum */
+
+	OS_REG_WRITE(ah, AR_DIAG_SW, 0);
+
+	OS_REG_WRITE(ah, AR_CFP_PERIOD, 0);
+	OS_REG_WRITE(ah, AR_TIMER0, 0);		/* next beacon time */
+	OS_REG_WRITE(ah, AR_TSF_L32, 0);	/* local clock */
+	OS_REG_WRITE(ah, AR_TIMER1, ~0);	/* next DMA beacon alert */
+	OS_REG_WRITE(ah, AR_TIMER2, ~0);	/* next SW beacon alert */
+	OS_REG_WRITE(ah, AR_TIMER3, 1);		/* next ATIM window */
+
+	/* Write the INI values for PHYreg initialization */
+	for (i = 0; i < N(ar5k0007_init); i++) {
+		uint32_t reg = ar5k0007_init[i].Offset;
+		/* On channel change, don't reset the PCU registers */
+		if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))
+			OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value);
+	}
+
+	/* Setup the transmit power values for cards since 0x0[0-2]05 */
+	if (!ar5210SetTransmitPower(ah, chan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error init'ing transmit power\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	OS_REG_WRITE(ah, AR_PHY(10),
+		(OS_REG_READ(ah, AR_PHY(10)) & 0xFFFF00FF) |
+		(ee->ee_xlnaOn << 8));
+	OS_REG_WRITE(ah, AR_PHY(13),
+		(ee->ee_xpaOff << 24) | (ee->ee_xpaOff << 16) |
+		(ee->ee_xpaOn << 8) | ee->ee_xpaOn);
+	OS_REG_WRITE(ah, AR_PHY(17),
+		(OS_REG_READ(ah, AR_PHY(17)) & 0xFFFFC07F) |
+		((ee->ee_antenna >> 1) & 0x3F80));
+	OS_REG_WRITE(ah, AR_PHY(18),
+		(OS_REG_READ(ah, AR_PHY(18)) & 0xFFFC0FFF) |
+		((ee->ee_antenna << 10) & 0x3F000));
+	OS_REG_WRITE(ah, AR_PHY(25),
+		(OS_REG_READ(ah, AR_PHY(25)) & 0xFFF80FFF) |
+		((ee->ee_thresh62 << 12) & 0x7F000));
+	OS_REG_WRITE(ah, AR_PHY(68),
+		(OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) |
+		(ee->ee_antenna & 0x3));
+
+	if (!ar5210SetChannel(ah, ichan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
+		    __func__);
+		FAIL(HAL_EIO);
+	}
+	if (bChannelChange) {
+		if (!(ichan->privFlags & CHANNEL_DFS)) 
+			ichan->privFlags &= ~CHANNEL_INTERFERENCE;
+		chan->channelFlags = ichan->channelFlags;
+		chan->privFlags = ichan->privFlags;
+	}
+
+	/* Activate the PHY */
+	OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ENABLE);
+
+	OS_DELAY(1000);		/* Wait a bit (1 msec) */
+
+	/* calibrate the HW and poll the bit going to 0 for completion */
+	OS_REG_WRITE(ah, AR_PHY_AGCCTL,
+		OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
+	(void) ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0);
+
+	/* Perform noise floor calibration and set status */
+	if (!ar5210CalNoiseFloor(ah, ichan)) {
+		chan->channelFlags |= CHANNEL_CW_INT;
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: noise floor calibration failed\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	for (q = 0; q < HAL_NUM_TX_QUEUES; q++)
+		ar5210ResetTxQueue(ah, q);
+
+	if (AH_PRIVATE(ah)->ah_rfkillEnabled)
+		ar5210EnableRfKill(ah);
+
+	/*
+	 * Writing to AR_BEACON will start timers. Hence it should be
+	 * the last register to be written. Do not reset tsf, do not
+	 * enable beacons at this point, but preserve other values
+	 * like beaconInterval.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON,
+		(OS_REG_READ(ah, AR_BEACON) &
+			~(AR_BEACON_EN | AR_BEACON_RESET_TSF)));
+
+	/* Restore user-specified slot time and timeouts */
+	if (ahp->ah_sifstime != (u_int) -1)
+		ar5210SetSifsTime(ah, ahp->ah_sifstime);
+	if (ahp->ah_slottime != (u_int) -1)
+		ar5210SetSlotTime(ah, ahp->ah_slottime);
+	if (ahp->ah_acktimeout != (u_int) -1)
+		ar5210SetAckTimeout(ah, ahp->ah_acktimeout);
+	if (ahp->ah_ctstimeout != (u_int) -1)
+		ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout);
+	if (AH_PRIVATE(ah)->ah_diagreg != 0)
+		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
+
+	AH_PRIVATE(ah)->ah_opmode = opmode;	/* record operating mode */
+
+	HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
+
+	return AH_TRUE;
+bad:
+	if (*status)
+		*status = ecode;
+	return AH_FALSE;
+#undef FAIL
+#undef N
+}
+
+static void
+ar5210SetOperatingMode(struct ath_hal *ah, int opmode)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	uint32_t val;
+
+	val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;
+	switch (opmode) {
+	case HAL_M_HOSTAP:
+		OS_REG_WRITE(ah, AR_STA_ID1, val
+			| AR_STA_ID1_AP
+			| AR_STA_ID1_NO_PSPOLL
+			| AR_STA_ID1_DESC_ANTENNA
+			| ahp->ah_staId1Defaults);
+		break;
+	case HAL_M_IBSS:
+		OS_REG_WRITE(ah, AR_STA_ID1, val
+			| AR_STA_ID1_ADHOC
+			| AR_STA_ID1_NO_PSPOLL
+			| AR_STA_ID1_DESC_ANTENNA
+			| ahp->ah_staId1Defaults);
+		break;
+	case HAL_M_STA:
+		OS_REG_WRITE(ah, AR_STA_ID1, val
+			| AR_STA_ID1_NO_PSPOLL
+			| AR_STA_ID1_PWR_SV
+			| ahp->ah_staId1Defaults);
+		break;
+	case HAL_M_MONITOR:
+		OS_REG_WRITE(ah, AR_STA_ID1, val
+			| AR_STA_ID1_NO_PSPOLL
+			| ahp->ah_staId1Defaults);
+		break;
+	}
+}
+
+void
+ar5210SetPCUConfig(struct ath_hal *ah)
+{
+	ar5210SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
+}
+
+/*
+ * Places the PHY and Radio chips into reset.  A full reset
+ * must be called to leave this state.  The PCI/MAC/PCU are
+ * not placed into reset as we must receive interrupt to
+ * re-enable the hardware.
+ */
+HAL_BOOL
+ar5210PhyDisable(struct ath_hal *ah)
+{
+	return ar5210SetResetReg(ah, AR_RC_RPHY, 10);
+}
+
+/*
+ * Places all of hardware into reset
+ */
+HAL_BOOL
+ar5210Disable(struct ath_hal *ah)
+{
+#define	AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
+	if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+
+	/*
+	 * Reset the HW - PCI must be reset after the rest of the
+	 * device has been reset
+	 */
+	if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))
+		return AH_FALSE;
+	OS_DELAY(1000);
+	(void) ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME);
+	OS_DELAY(2100);   /* 8245 @ 96Mhz hangs with 2000us. */
+
+	return AH_TRUE;
+#undef AR_RC_HW
+}
+
+/*
+ * Places the hardware into reset and then pulls it out of reset
+ */
+HAL_BOOL
+ar5210ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+#define	AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
+
+	HALDEBUG(ah, HAL_DEBUG_RESET, "%s turbo %s\n", __func__,
+		chan && IS_CHAN_TURBO(chan) ? "enabled" : "disabled");
+
+	if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+
+	/* Place chip in turbo before reset to cleanly reset clocks */
+	OS_REG_WRITE(ah, AR_PHY_FRCTL,
+		chan && IS_CHAN_TURBO(chan) ? AR_PHY_TURBO_MODE : 0);
+
+	/*
+	 * Reset the HW.
+	 * PCI must be reset after the rest of the device has been reset.
+	 */
+	if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))
+		return AH_FALSE;
+	OS_DELAY(1000);
+	if (!ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME))
+		return AH_FALSE;
+	OS_DELAY(2100);   /* 8245 @ 96Mhz hangs with 2000us. */
+
+	/*
+	 * Bring out of sleep mode (AGAIN)
+	 *
+	 * WARNING WARNING WARNING
+	 *
+	 * There is a problem with the chip where it doesn't always indicate
+	 * that it's awake, so initializePowerUp() will fail.
+	 */
+	if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+
+	/* Clear warm reset reg */
+	return ar5210SetResetReg(ah, 0, 10);
+#undef AR_RC_HW
+}
+
+enum {
+	FIRPWR_M	= 0x03fc0000,
+	FIRPWR_S	= 18,
+	KCOARSEHIGH_M   = 0x003f8000,
+	KCOARSEHIGH_S   = 15,
+	KCOARSELOW_M	= 0x00007f80,
+	KCOARSELOW_S	= 7,
+	ADCSAT_ICOUNT_M	= 0x0001f800,
+	ADCSAT_ICOUNT_S	= 11,
+	ADCSAT_THRESH_M	= 0x000007e0,
+	ADCSAT_THRESH_S	= 5
+};
+
+/*
+ * Recalibrate the lower PHY chips to account for temperature/environment
+ * changes.
+ */
+HAL_BOOL
+ar5210PerCalibrationN(struct ath_hal *ah,  HAL_CHANNEL *chan, u_int chainMask,
+	HAL_BOOL longCal, HAL_BOOL *isCalDone)
+{
+	uint32_t regBeacon;
+	uint32_t reg9858, reg985c, reg9868;
+	HAL_CHANNEL_INTERNAL *ichan;
+
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		return AH_FALSE;
+	}
+	/* Disable tx and rx */
+	OS_REG_WRITE(ah, AR_DIAG_SW,
+		OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
+
+	/* Disable Beacon Enable */
+	regBeacon = OS_REG_READ(ah, AR_BEACON);
+	OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN);
+
+	/* Delay 4ms to ensure that all tx and rx activity has ceased */
+	OS_DELAY(4000);
+
+	/* Disable AGC to radio traffic */
+	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
+	/* Wait for the AGC traffic to cease. */
+	OS_DELAY(10);
+
+	/* Change Channel to relock synth */
+	if (!ar5210SetChannel(ah, ichan))
+		return AH_FALSE;
+
+	/* wait for the synthesizer lock to stabilize */
+	OS_DELAY(1000);
+
+	/* Re-enable AGC to radio traffic */
+	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));
+
+	/*
+	 * Configure the AGC so that it is highly unlikely (if not
+	 * impossible) for it to send any gain changes to the analog
+	 * chip.  We store off the current values so that they can
+	 * be rewritten below. Setting the following values:
+	 * firpwr	 = -1
+	 * Kcoursehigh   = -1
+	 * Kcourselow	 = -127
+	 * ADCsat_icount = 2
+	 * ADCsat_thresh = 12
+	 */
+	reg9858 = OS_REG_READ(ah, 0x9858);
+	reg985c = OS_REG_READ(ah, 0x985c);
+	reg9868 = OS_REG_READ(ah, 0x9868);
+
+	OS_REG_WRITE(ah, 0x9858, (reg9858 & ~FIRPWR_M) |
+					 ((-1 << FIRPWR_S) & FIRPWR_M));
+	OS_REG_WRITE(ah, 0x985c,
+		 (reg985c & ~(KCOARSEHIGH_M | KCOARSELOW_M)) |
+		 ((-1 << KCOARSEHIGH_S) & KCOARSEHIGH_M) |
+		 ((-127 << KCOARSELOW_S) & KCOARSELOW_M));
+	OS_REG_WRITE(ah, 0x9868,
+		 (reg9868 & ~(ADCSAT_ICOUNT_M | ADCSAT_THRESH_M)) |
+		 ((2 << ADCSAT_ICOUNT_S) & ADCSAT_ICOUNT_M) |
+		 ((12 << ADCSAT_THRESH_S) & ADCSAT_THRESH_M));
+
+	/* Wait for AGC changes to be enacted */
+	OS_DELAY(20);
+
+	/*
+	 * We disable RF mix/gain stages for the PGA to avoid a
+	 * race condition that will occur with receiving a frame
+	 * and performing the AGC calibration.  This will be
+	 * re-enabled at the end of offset cal.  We turn off AGC
+	 * writes during this write as it will go over the analog bus.
+	 */
+	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
+	OS_DELAY(10);		 /* wait for the AGC traffic to cease */
+	OS_REG_WRITE(ah, 0x98D4, 0x21);
+	OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));
+
+	/* wait to make sure that additional AGC traffic has quiesced */
+	OS_DELAY(1000);
+
+	/* AGC calibration (this was added to make the NF threshold check work) */
+	OS_REG_WRITE(ah, AR_PHY_AGCCTL,
+		 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
+	if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0))
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n",
+		    __func__);
+
+	/* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */
+	OS_REG_WRITE(ah, 0x9858, reg9858);
+	OS_REG_WRITE(ah, 0x985c, reg985c);
+	OS_REG_WRITE(ah, 0x9868, reg9868);
+
+	/* Perform noise floor and set status */
+	if (!ar5210CalNoiseFloor(ah, ichan)) {
+		/*
+		 * Delay 5ms before retrying the noise floor -
+		 * just to make sure.  We're in an error
+		 * condition here
+		 */
+		HALDEBUG(ah, HAL_DEBUG_NFCAL | HAL_DEBUG_PERCAL,
+		    "%s: Performing 2nd Noise Cal\n", __func__);
+		OS_DELAY(5000);
+		if (!ar5210CalNoiseFloor(ah, ichan))
+			chan->channelFlags |= CHANNEL_CW_INT;
+	}
+
+	/* Clear tx and rx disable bit */
+	OS_REG_WRITE(ah, AR_DIAG_SW,
+		 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
+
+	/* Re-enable Beacons */
+	OS_REG_WRITE(ah, AR_BEACON, regBeacon);
+
+	*isCalDone = AH_TRUE;
+
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5210PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
+{
+	return ar5210PerCalibrationN(ah,  chan, 0x1, AH_TRUE, isIQdone);
+}
+
+HAL_BOOL
+ar5210ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	return AH_TRUE;
+}
+
+/*
+ * Writes the given reset bit mask into the reset register
+ */
+static HAL_BOOL
+ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay)
+{
+	uint32_t mask = resetMask ? resetMask : ~0;
+	HAL_BOOL rt;
+
+	OS_REG_WRITE(ah, AR_RC, resetMask);
+	/* need to wait at least 128 clocks when reseting PCI before read */
+	OS_DELAY(delay);
+
+	resetMask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
+	mask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
+	rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
+        if ((resetMask & AR_RC_RMAC) == 0) {
+		if (isBigEndian()) {
+			/*
+			 * Set CFG, little-endian for register
+			 * and descriptor accesses.
+			 */
+			mask = INIT_CONFIG_STATUS |
+				AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG;
+			OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
+		} else
+			OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
+	}
+	return rt;
+}
+
+
+/*
+ * Returns: the pcdac value
+ */
+static uint8_t
+getPcdac(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t dBm)
+{
+	int32_t	 i;
+	int useNextEntry = AH_FALSE;
+	uint32_t interp;
+
+	for (i = AR_TP_SCALING_ENTRIES - 1; i >= 0; i--) {
+		/* Check for exact entry */
+		if (dBm == AR_I2DBM(i)) {
+			if (pRD->pcdac[i] != 63)
+				return pRD->pcdac[i];
+			useNextEntry = AH_TRUE;
+		} else if (dBm + 1 == AR_I2DBM(i) && i > 0) {
+			/* Interpolate for between entry with a logish scale */
+			if (pRD->pcdac[i] != 63 && pRD->pcdac[i-1] != 63) {
+				interp = (350 * (pRD->pcdac[i] - pRD->pcdac[i-1])) + 999;
+				interp = (interp / 1000) + pRD->pcdac[i-1];
+				return interp;
+			}
+			useNextEntry = AH_TRUE;
+		} else if (useNextEntry == AH_TRUE) {
+			/* Grab the next lowest */
+			if (pRD->pcdac[i] != 63)
+				return pRD->pcdac[i];
+		}
+	}
+
+	/* Return the lowest Entry if we haven't returned */
+	for (i = 0; i < AR_TP_SCALING_ENTRIES; i++)
+		if (pRD->pcdac[i] != 63)
+			return pRD->pcdac[i];
+
+	/* No value to return from table */
+#ifdef AH_DEBUG
+	ath_hal_printf(ah, "%s: empty transmit power table?\n", __func__);
+#endif
+	return 1;
+}
+
+/*
+ * Find or interpolates the gainF value from the table ptr.
+ */
+static uint8_t
+getGainF(struct ath_hal *ah, const struct tpcMap *pRD,
+	uint8_t pcdac, uint8_t *dBm)
+{
+	uint32_t interp;
+	int low, high, i;
+
+	low = high = -1;
+
+	for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) {
+		if(pRD->pcdac[i] == 63)
+			continue;
+		if (pcdac == pRD->pcdac[i]) {
+			*dBm = AR_I2DBM(i);
+			return pRD->gainF[i];  /* Exact Match */
+		}
+		if (pcdac > pRD->pcdac[i])
+			low = i;
+		if (pcdac < pRD->pcdac[i]) {
+			high = i;
+			if (low == -1) {
+				*dBm = AR_I2DBM(i);
+				/* PCDAC is lower than lowest setting */
+				return pRD->gainF[i];
+			}
+			break;
+		}
+	}
+	if (i >= AR_TP_SCALING_ENTRIES && low == -1) {
+		/* No settings were found */
+#ifdef AH_DEBUG
+		ath_hal_printf(ah,
+			"%s: no valid entries in the pcdac table: %d\n",
+			__func__, pcdac);
+#endif
+		return 63;
+	}
+	if (i >= AR_TP_SCALING_ENTRIES) {
+		/* PCDAC setting was above the max setting in the table */
+		*dBm = AR_I2DBM(low);
+		return pRD->gainF[low];
+	}
+	/* Only exact if table has no missing entries */
+	*dBm = (low + high) + 3;
+
+	/*
+	 * Perform interpolation between low and high values to find gainF
+	 * linearly scale the pcdac between low and high
+	 */
+	interp = ((pcdac - pRD->pcdac[low]) * 1000) /
+		  (pRD->pcdac[high] - pRD->pcdac[low]);
+	/*
+	 * Multiply the scale ratio by the gainF difference
+	 * (plus a rnd up factor)
+	 */
+	interp = ((interp * (pRD->gainF[high] - pRD->gainF[low])) + 999) / 1000;
+
+	/* Add ratioed gain_f to low gain_f value */
+	return interp + pRD->gainF[low];
+}
+
+HAL_BOOL
+ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
+{
+	AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, AR5210_MAX_RATE_POWER);
+	/* XXX flush to h/w */
+	return AH_TRUE;
+}
+
+/*
+ * Get TXPower values and set them in the radio
+ */
+static HAL_BOOL
+setupPowerSettings(struct ath_hal *ah, HAL_CHANNEL *chan, uint8_t cp[17])
+{
+	const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint8_t gainFRD, gainF36, gainF48, gainF54;
+	uint8_t dBmRD, dBm36, dBm48, dBm54, dontcare;
+	uint32_t rd, group;
+	const struct tpcMap  *pRD;
+
+	/* Set OB/DB Values regardless of channel */
+	cp[15] = (ee->ee_biasCurrents >> 4) & 0x7;
+	cp[16] = ee->ee_biasCurrents & 0x7;
+
+	if (chan->channel < 5170 || chan->channel > 5320) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u\n",
+		    __func__, chan->channel);
+		return AH_FALSE;
+	}
+
+	HALASSERT(ee->ee_version >= AR_EEPROM_VER1 &&
+	    ee->ee_version < AR_EEPROM_VER3);
+
+	/* Match regulatory domain */
+	for (rd = 0; rd < AR_REG_DOMAINS_MAX; rd++)
+		if (AH_PRIVATE(ah)->ah_currentRD == ee->ee_regDomain[rd])
+			break;
+	if (rd == AR_REG_DOMAINS_MAX) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah,
+			"%s: no calibrated regulatory domain matches the "
+			"current regularly domain (0x%0x)\n", __func__, 
+			AH_PRIVATE(ah)->ah_currentRD);
+#endif
+		return AH_FALSE;
+	}
+	group = ((chan->channel - 5170) / 10);
+
+	if (group > 11) {
+		/* Pull 5.29 into the 5.27 group */
+		group--;
+	}
+
+	/* Integer divide will set group from 0 to 4 */
+	group = group / 3;
+	pRD   = &ee->ee_tpc[group];
+
+	/* Set PC DAC Values */
+	cp[14] = pRD->regdmn[rd];
+	cp[9]  = AH_MIN(pRD->regdmn[rd], pRD->rate36);
+	cp[8]  = AH_MIN(pRD->regdmn[rd], pRD->rate48);
+	cp[7]  = AH_MIN(pRD->regdmn[rd], pRD->rate54);
+
+	/* Find Corresponding gainF values for RD, 36, 48, 54 */
+	gainFRD = getGainF(ah, pRD, pRD->regdmn[rd], &dBmRD);
+	gainF36 = getGainF(ah, pRD, cp[9], &dBm36);
+	gainF48 = getGainF(ah, pRD, cp[8], &dBm48);
+	gainF54 = getGainF(ah, pRD, cp[7], &dBm54);
+
+	/* Power Scale if requested */
+	if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) {
+		static const uint16_t tpcScaleReductionTable[5] =
+			{ 0, 3, 6, 9, AR5210_MAX_RATE_POWER };
+		uint16_t tpScale;
+
+		tpScale = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
+		if (dBmRD < tpScale+3)
+			dBmRD = 3;		/* min */
+		else
+			dBmRD -= tpScale;
+		cp[14]  = getPcdac(ah, pRD, dBmRD);
+		gainFRD = getGainF(ah, pRD, cp[14], &dontcare);
+		dBm36   = AH_MIN(dBm36, dBmRD);
+		cp[9]   = getPcdac(ah, pRD, dBm36);
+		gainF36 = getGainF(ah, pRD, cp[9], &dontcare);
+		dBm48   = AH_MIN(dBm48, dBmRD);
+		cp[8]   = getPcdac(ah, pRD, dBm48);
+		gainF48 = getGainF(ah, pRD, cp[8], &dontcare);
+		dBm54   = AH_MIN(dBm54, dBmRD);
+		cp[7]   = getPcdac(ah, pRD, dBm54);
+		gainF54 = getGainF(ah, pRD, cp[7], &dontcare);
+	}
+	/* Record current dBm at rate 6 */
+	AH_PRIVATE(ah)->ah_maxPowerLevel = 2*dBmRD;
+
+	cp[13] = cp[12] = cp[11] = cp[10] = cp[14];
+
+	/* Set GainF Values */
+	cp[0] = gainFRD - gainF54;
+	cp[1] = gainFRD - gainF48;
+	cp[2] = gainFRD - gainF36;
+	/* 9, 12, 18, 24 have no gain_delta from 6 */
+	cp[3] = cp[4] = cp[5] = cp[6] = 0;
+	return AH_TRUE;
+}
+
+/*
+ * Places the device in and out of reset and then places sane
+ * values in the registers based on EEPROM config, initialization
+ * vectors (as determined by the mode), and station configuration
+ */
+HAL_BOOL
+ar5210SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+#define	N(a)	(sizeof (a) / sizeof (a[0]))
+	static const uint32_t pwr_regs_start[17] = {
+		0x00000000, 0x00000000, 0x00000000,
+		0x00000000, 0x00000000, 0xf0000000,
+		0xcc000000, 0x00000000, 0x00000000,
+		0x00000000, 0x0a000000, 0x000000e2,
+		0x0a000020, 0x01000002, 0x01000018,
+		0x40000000, 0x00000418
+	};
+	uint16_t i;
+	uint8_t cp[sizeof(ar5k0007_pwrSettings)];
+	uint32_t pwr_regs[17];
+
+	OS_MEMCPY(pwr_regs, pwr_regs_start, sizeof(pwr_regs));
+	OS_MEMCPY(cp, ar5k0007_pwrSettings, sizeof(cp));
+
+	/* Check the EEPROM tx power calibration settings */
+	if (!setupPowerSettings(ah, chan, cp)) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s: unable to setup power settings\n",
+			__func__);
+#endif
+		return AH_FALSE;
+	}
+	if (cp[15] < 1 || cp[15] > 5) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s: OB out of range (%u)\n",
+			__func__, cp[15]);
+#endif
+		return AH_FALSE;
+	}
+	if (cp[16] < 1 || cp[16] > 5) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s: DB out of range (%u)\n",
+			__func__, cp[16]);
+#endif
+		return AH_FALSE;
+	}
+
+	/* reverse bits of the transmit power array */
+	for (i = 0; i < 7; i++)
+		cp[i] = ath_hal_reverseBits(cp[i], 5);
+	for (i = 7; i < 15; i++)
+		cp[i] = ath_hal_reverseBits(cp[i], 6);
+
+	/* merge transmit power values into the register - quite gross */
+	pwr_regs[0] |= ((cp[1] << 5) & 0xE0) | (cp[0] & 0x1F);
+	pwr_regs[1] |= ((cp[3] << 7) & 0x80) | ((cp[2] << 2) & 0x7C) | 
+			((cp[1] >> 3) & 0x03);
+	pwr_regs[2] |= ((cp[4] << 4) & 0xF0) | ((cp[3] >> 1) & 0x0F);
+	pwr_regs[3] |= ((cp[6] << 6) & 0xC0) | ((cp[5] << 1) & 0x3E) |
+		       ((cp[4] >> 4) & 0x01);
+	pwr_regs[4] |= ((cp[7] << 3) & 0xF8) | ((cp[6] >> 2) & 0x07);
+	pwr_regs[5] |= ((cp[9] << 7) & 0x80) | ((cp[8] << 1) & 0x7E) |
+			((cp[7] >> 5) & 0x01);
+	pwr_regs[6] |= ((cp[10] << 5) & 0xE0) | ((cp[9] >> 1) & 0x1F);
+	pwr_regs[7] |= ((cp[11] << 3) & 0xF8) | ((cp[10] >> 3) & 0x07);
+	pwr_regs[8] |= ((cp[12] << 1) & 0x7E) | ((cp[11] >> 5) & 0x01);
+	pwr_regs[9] |= ((cp[13] << 5) & 0xE0);
+	pwr_regs[10] |= ((cp[14] << 3) & 0xF8) | ((cp[13] >> 3) & 0x07);
+	pwr_regs[11] |= ((cp[14] >> 5) & 0x01);
+
+	/* Set OB */
+	pwr_regs[8] |=  (ath_hal_reverseBits(cp[15], 3) << 7) & 0x80;
+	pwr_regs[9] |=  (ath_hal_reverseBits(cp[15], 3) >> 1) & 0x03;
+
+	/* Set DB */
+	pwr_regs[9] |=  (ath_hal_reverseBits(cp[16], 3) << 2) & 0x1C;
+
+	/* Write the registers */
+	for (i = 0; i < N(pwr_regs)-1; i++)
+		OS_REG_WRITE(ah, 0x0000989c, pwr_regs[i]);
+	/* last write is a flush */
+	OS_REG_WRITE(ah, 0x000098d4, pwr_regs[i]);
+
+	return AH_TRUE;
+#undef N
+}
+
+/*
+ * Takes the MHz channel value and sets the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus before AGC is active
+ *   or by disabling the AGC.
+ */
+static HAL_BOOL
+ar5210SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t data;
+
+	/* Set the Channel */
+	data = ath_hal_reverseBits((chan->channel - 5120)/10, 5);
+	data = (data << 1) | 0x41;
+	OS_REG_WRITE(ah, AR_PHY(0x27), data);
+	OS_REG_WRITE(ah, AR_PHY(0x30), 0);
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+}
+
+int16_t
+ar5210GetNoiseFloor(struct ath_hal *ah)
+{
+	int16_t nf;
+
+	nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
+	if (nf & 0x100)
+		nf = 0 - ((nf ^ 0x1ff) + 1);
+	return nf;
+}
+
+#define NORMAL_NF_THRESH (-72)
+/*
+ * Peform the noisefloor calibration and check for
+ * any constant channel interference
+ *
+ * Returns: TRUE for a successful noise floor calibration; else FALSE
+ */
+HAL_BOOL
+ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+	int32_t nf, nfLoops;
+
+	/* Calibrate the noise floor */
+	OS_REG_WRITE(ah, AR_PHY_AGCCTL,
+		OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_NF);
+
+	/* Do not read noise floor until it has done the first update */
+	if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_NF, 0)) {
+#ifdef ATH_HAL_DEBUG
+		ath_hal_printf(ah, " -PHY NF Reg state: 0x%x\n",
+			OS_REG_READ(ah, AR_PHY_AGCCTL));
+		ath_hal_printf(ah, " -MAC Reset Reg state: 0x%x\n",
+			OS_REG_READ(ah, AR_RC));
+		ath_hal_printf(ah, " -PHY Active Reg state: 0x%x\n",
+			OS_REG_READ(ah, AR_PHY_ACTIVE));
+#endif /* ATH_HAL_DEBUG */
+		return AH_FALSE;
+	}
+
+	nf = 0;
+	/* Keep checking until the floor is below the threshold or the nf is done */
+	for (nfLoops = 0; ((nfLoops < 21) && (nf > NORMAL_NF_THRESH)); nfLoops++) {
+		OS_DELAY(1000); /* Sleep for 1 ms */
+		nf = ar5210GetNoiseFloor(ah);
+	}
+
+	if (nf > NORMAL_NF_THRESH) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Bad noise cal %d\n",
+		    __func__, nf);
+		chan->rawNoiseFloor = 0;
+		return AH_FALSE;
+	}
+	chan->rawNoiseFloor = nf;
+	return AH_TRUE;
+}
+
+/*
+ * Adjust NF based on statistical values for 5GHz frequencies.
+ */
+int16_t
+ar5210GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
+{
+	return 0;
+}
+
+HAL_RFGAIN
+ar5210GetRfgain(struct ath_hal *ah)
+{
+	return HAL_RFGAIN_INACTIVE;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_xmit.c b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_xmit.c
new file mode 100644
index 0000000..7ce9c83
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210_xmit.c
@@ -0,0 +1,623 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210_xmit.c,v 1.5 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_desc.h"
+
+#include "ar5210/ar5210.h"
+#include "ar5210/ar5210reg.h"
+#include "ar5210/ar5210phy.h"
+#include "ar5210/ar5210desc.h"
+
+/*
+ * Set the properties of the tx queue with the parameters
+ * from qInfo.  The queue must previously have been setup
+ * with a call to ar5210SetupTxQueue.
+ */
+HAL_BOOL
+ar5210SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	if (q >= HAL_NUM_TX_QUEUES) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);
+}
+
+/*
+ * Return the properties for the specified tx queue.
+ */
+HAL_BOOL
+ar5210GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+
+	if (q >= HAL_NUM_TX_QUEUES) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);
+}
+
+/*
+ * Allocate and initialize a tx DCU/QCU combination.
+ */
+int
+ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
+	const HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	HAL_TX_QUEUE_INFO *qi;
+	int q;
+
+	switch (type) {
+	case HAL_TX_QUEUE_BEACON:
+		q = 2;
+		break;
+	case HAL_TX_QUEUE_CAB:
+		q = 1;
+		break;
+	case HAL_TX_QUEUE_DATA:
+		q = 0;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad tx queue type %u\n",
+		    __func__, type);
+		return -1;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
+
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
+		    __func__, q);
+		return -1;
+	}
+	OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
+	qi->tqi_type = type;
+	if (qInfo == AH_NULL) {
+		/* by default enable OK+ERR+DESC+URN interrupts */
+		qi->tqi_qflags =
+			  HAL_TXQ_TXOKINT_ENABLE
+			| HAL_TXQ_TXERRINT_ENABLE
+			| HAL_TXQ_TXDESCINT_ENABLE
+			| HAL_TXQ_TXURNINT_ENABLE
+			;
+		qi->tqi_aifs = INIT_AIFS;
+		qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;	/* NB: do at reset */
+		qi->tqi_shretry = INIT_SH_RETRY;
+		qi->tqi_lgretry = INIT_LG_RETRY;
+	} else
+		(void) ar5210SetTxQueueProps(ah, q, qInfo);
+	/* NB: must be followed by ar5210ResetTxQueue */
+	return q;
+}
+
+/*
+ * Free a tx DCU/QCU combination.
+ */
+HAL_BOOL
+ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	HAL_TX_QUEUE_INFO *qi;
+
+	if (q >= HAL_NUM_TX_QUEUES) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);
+
+	qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
+	ahp->ah_txOkInterruptMask &= ~(1 << q);
+	ahp->ah_txErrInterruptMask &= ~(1 << q);
+	ahp->ah_txDescInterruptMask &= ~(1 << q);
+	ahp->ah_txEolInterruptMask &= ~(1 << q);
+	ahp->ah_txUrnInterruptMask &= ~(1 << q);
+
+	return AH_TRUE;
+#undef N
+}
+
+HAL_BOOL
+ar5210ResetTxQueue(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	HAL_TX_QUEUE_INFO *qi;
+	uint32_t cwMin;
+
+	if (q >= HAL_NUM_TX_QUEUES) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+
+	/*
+	 * Ignore any non-data queue(s).
+	 */
+	if (qi->tqi_type != HAL_TX_QUEUE_DATA)
+		return AH_TRUE;
+
+	/* Set turbo mode / base mode parameters on or off */
+	if (IS_CHAN_TURBO(chan)) {
+		OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME_TURBO);
+		OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT_TURBO);
+		OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY_TURBO);
+		OS_REG_WRITE(ah, AR_IFS0, 
+			((INIT_SIFS_TURBO + qi->tqi_aifs * INIT_SLOT_TIME_TURBO)
+				<< AR_IFS0_DIFS_S)
+			| INIT_SIFS_TURBO);
+		OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL_TURBO);
+		OS_REG_WRITE(ah, AR_PHY(17),
+			(OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x38);
+		OS_REG_WRITE(ah, AR_PHY_FRCTL,
+			AR_PHY_SERVICE_ERR | AR_PHY_TXURN_ERR |
+			AR_PHY_ILLLEN_ERR | AR_PHY_ILLRATE_ERR |
+			AR_PHY_PARITY_ERR | AR_PHY_TIMING_ERR |
+			0x2020 |
+			AR_PHY_TURBO_MODE | AR_PHY_TURBO_SHORT);
+	} else {
+		OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME);
+		OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT);
+		OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY);
+		OS_REG_WRITE(ah, AR_IFS0, 
+			((INIT_SIFS + qi->tqi_aifs * INIT_SLOT_TIME)
+				<< AR_IFS0_DIFS_S)
+			| INIT_SIFS);
+		OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL);
+		OS_REG_WRITE(ah, AR_PHY(17),
+			(OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x1C);
+		OS_REG_WRITE(ah, AR_PHY_FRCTL,
+			AR_PHY_SERVICE_ERR | AR_PHY_TXURN_ERR |
+			AR_PHY_ILLLEN_ERR | AR_PHY_ILLRATE_ERR |
+			AR_PHY_PARITY_ERR | AR_PHY_TIMING_ERR | 0x1020);
+	}
+
+	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT)
+		cwMin = INIT_CWMIN;
+	else
+		cwMin = qi->tqi_cwmin;
+
+	/* Set cwmin and retry limit values */
+	OS_REG_WRITE(ah, AR_RETRY_LMT, 
+		  (cwMin << AR_RETRY_LMT_CW_MIN_S)
+		 | SM(INIT_SLG_RETRY, AR_RETRY_LMT_SLG_RETRY)
+		 | SM(INIT_SSH_RETRY, AR_RETRY_LMT_SSH_RETRY)
+		 | SM(qi->tqi_lgretry, AR_RETRY_LMT_LG_RETRY)
+		 | SM(qi->tqi_shretry, AR_RETRY_LMT_SH_RETRY)
+	);
+
+	if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
+		ahp->ah_txOkInterruptMask |= 1 << q;
+	else
+		ahp->ah_txOkInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
+		ahp->ah_txErrInterruptMask |= 1 << q;
+	else
+		ahp->ah_txErrInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
+		ahp->ah_txDescInterruptMask |= 1 << q;
+	else
+		ahp->ah_txDescInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
+		ahp->ah_txEolInterruptMask |= 1 << q;
+	else
+		ahp->ah_txEolInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
+		ahp->ah_txUrnInterruptMask |= 1 << q;
+	else
+		ahp->ah_txUrnInterruptMask &= ~(1 << q);
+
+	return AH_TRUE;
+}
+
+/*
+ * Get the TXDP for the "main" data queue.  Needs to be extended
+ * for multiple Q functionality
+ */
+uint32_t
+ar5210GetTxDP(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	HAL_TX_QUEUE_INFO *qi;
+
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+
+	qi = &ahp->ah_txq[q];
+	switch (qi->tqi_type) {
+	case HAL_TX_QUEUE_DATA:
+		return OS_REG_READ(ah, AR_TXDP0);
+	case HAL_TX_QUEUE_INACTIVE:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
+		    __func__, q);
+		/* fall thru... */
+	default:
+		break;
+	}
+	return 0xffffffff;
+}
+
+/*
+ * Set the TxDP for the "main" data queue.
+ */
+HAL_BOOL
+ar5210SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	HAL_TX_QUEUE_INFO *qi;
+
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u 0x%x\n",
+	    __func__, q, txdp);
+	qi = &ahp->ah_txq[q];
+	switch (qi->tqi_type) {
+	case HAL_TX_QUEUE_DATA:
+#ifdef AH_DEBUG
+		/*
+		 * Make sure that TXE is deasserted before setting the
+		 * TXDP.  If TXE is still asserted, setting TXDP will
+		 * have no effect.
+		 */
+		if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0)
+			ath_hal_printf(ah, "%s: TXE asserted; AR_CR=0x%x\n",
+				__func__, OS_REG_READ(ah, AR_CR));
+#endif
+		OS_REG_WRITE(ah, AR_TXDP0, txdp);
+		break;
+	case HAL_TX_QUEUE_BEACON:
+	case HAL_TX_QUEUE_CAB:
+		OS_REG_WRITE(ah, AR_TXDP1, txdp);
+		break;
+	case HAL_TX_QUEUE_INACTIVE:
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
+		    __func__, q);
+		/* fall thru... */
+	default:
+		return AH_FALSE;
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Update Tx FIFO trigger level.
+ *
+ * Set bIncTrigLevel to TRUE to increase the trigger level.
+ * Set bIncTrigLevel to FALSE to decrease the trigger level.
+ *
+ * Returns TRUE if the trigger level was updated
+ */
+HAL_BOOL
+ar5210UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
+{
+	uint32_t curTrigLevel;
+	HAL_INT ints = ar5210GetInterrupts(ah);
+
+	/*
+	 * Disable chip interrupts. This is because halUpdateTxTrigLevel
+	 * is called from both ISR and non-ISR contexts.
+	 */
+	(void) ar5210SetInterrupts(ah, ints &~ HAL_INT_GLOBAL);
+	curTrigLevel = OS_REG_READ(ah, AR_TRIG_LEV);
+	if (bIncTrigLevel){
+		/* increase the trigger level */
+		curTrigLevel = curTrigLevel +
+			((MAX_TX_FIFO_THRESHOLD - curTrigLevel) / 2);
+	} else {
+		/* decrease the trigger level if not already at the minimum */
+		if (curTrigLevel > MIN_TX_FIFO_THRESHOLD) {
+			/* decrease the trigger level */
+			curTrigLevel--;
+		} else {
+			/* no update to the trigger level */
+			/* re-enable chip interrupts */
+			ar5210SetInterrupts(ah, ints);
+			return AH_FALSE;
+		}
+	}
+	/* Update the trigger level */
+	OS_REG_WRITE(ah, AR_TRIG_LEV, curTrigLevel);
+	/* re-enable chip interrupts */
+	ar5210SetInterrupts(ah, ints);
+	return AH_TRUE;
+}
+
+/*
+ * Set Transmit Enable bits for the specified queues.
+ */
+HAL_BOOL
+ar5210StartTxDma(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	HAL_TX_QUEUE_INFO *qi;
+
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
+	qi = &ahp->ah_txq[q];
+	switch (qi->tqi_type) {
+	case HAL_TX_QUEUE_DATA:
+		OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0);
+		break;
+	case HAL_TX_QUEUE_CAB:
+		OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1);	/* enable altq xmit */
+		OS_REG_WRITE(ah, AR_BCR,
+			AR_BCR_TQ1V | AR_BCR_BDMAE | AR_BCR_TQ1FV);
+		break;
+	case HAL_TX_QUEUE_BEACON:
+		/* XXX add CR_BCR_BCMD if IBSS mode */
+		OS_REG_WRITE(ah, AR_BCR, AR_BCR_TQ1V | AR_BCR_BDMAE);
+		break;
+	case HAL_TX_QUEUE_INACTIVE:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
+		    __func__, q);
+		/* fal thru... */
+	default:
+		return AH_FALSE;
+	}
+	return AH_TRUE;
+}
+
+uint32_t
+ar5210NumTxPending(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	HAL_TX_QUEUE_INFO *qi;
+	uint32_t v;
+
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
+	qi = &ahp->ah_txq[q];
+	switch (qi->tqi_type) {
+	case HAL_TX_QUEUE_DATA:
+		v = OS_REG_READ(ah, AR_CFG);
+		return MS(v, AR_CFG_TXCNT);
+	case HAL_TX_QUEUE_INACTIVE:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
+		    __func__, q);
+		/* fall thru... */
+	default:
+		break;
+	}
+	return 0;
+}
+
+/*
+ * Stop transmit on the specified queue
+ */
+HAL_BOOL
+ar5210StopTxDma(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5210 *ahp = AH5210(ah);
+	HAL_TX_QUEUE_INFO *qi;
+
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
+	qi = &ahp->ah_txq[q];
+	switch (qi->tqi_type) {
+	case HAL_TX_QUEUE_DATA: {
+		int i;
+		OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0);
+		for (i = 0; i < 1000; i++) {
+			if ((OS_REG_READ(ah, AR_CFG) & AR_CFG_TXCNT) == 0)
+				break;
+			OS_DELAY(10);
+		}
+		OS_REG_WRITE(ah, AR_CR, 0);
+		return (i < 1000);
+	}
+	case HAL_TX_QUEUE_BEACON:
+		return ath_hal_wait(ah, AR_BSR, AR_BSR_TXQ1F, 0);
+	case HAL_TX_QUEUE_INACTIVE:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
+		    __func__, q);
+		/* fall thru... */
+	default:
+		break;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Descriptor Access Functions
+ */
+
+#define	VALID_PKT_TYPES \
+	((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
+	 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
+	 (1<<HAL_PKT_TYPE_BEACON))
+#define	isValidPktType(_t)	((1<<(_t)) & VALID_PKT_TYPES)
+#define	VALID_TX_RATES \
+	((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
+	 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
+	 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
+#define	isValidTxRate(_r)	((1<<(_r)) & VALID_TX_RATES)
+
+HAL_BOOL
+ar5210SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int pktLen,
+	u_int hdrLen,
+	HAL_PKT_TYPE type,
+	u_int txPower,
+	u_int txRate0, u_int txTries0,
+	u_int keyIx,
+	u_int antMode,
+	u_int flags,
+	u_int rtsctsRate,
+	u_int rtsctsDuration,
+        u_int compicvLen,
+	u_int compivLen,
+	u_int comp)
+{
+	struct ar5210_desc *ads = AR5210DESC(ds);
+	uint32_t frtype;
+
+	(void) txPower;
+	(void) rtsctsDuration;
+
+	HALASSERT(txTries0 != 0);
+	HALASSERT(isValidPktType(type));
+	HALASSERT(isValidTxRate(txRate0));
+
+	if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP)
+		frtype = AR_Frm_NoDelay;
+	else
+		frtype = type << 26;
+	ads->ds_ctl0 = (pktLen & AR_FrameLen)
+		     | (txRate0 << AR_XmitRate_S)
+		     | ((hdrLen << AR_HdrLen_S) & AR_HdrLen)
+		     | frtype
+		     | (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
+		     | (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
+		     | (antMode ? AR_AntModeXmit : 0)
+		     ;
+	if (keyIx != HAL_TXKEYIX_INVALID) {
+		ads->ds_ctl1 = (keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
+		ads->ds_ctl0 |= AR_EncryptKeyValid;
+	} else
+		ads->ds_ctl1 = 0;
+	if (flags & HAL_TXDESC_RTSENA) {
+		ads->ds_ctl0 |= AR_RTSCTSEnable;
+		ads->ds_ctl1 |= rtsctsDuration & AR_RTSDuration;
+	}
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5210SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int txRate1, u_int txTries1,
+	u_int txRate2, u_int txTries2,
+	u_int txRate3, u_int txTries3)
+{
+	(void) ah; (void) ds;
+	(void) txRate1; (void) txTries1;
+	(void) txRate2; (void) txTries2;
+	(void) txRate3; (void) txTries3;
+	return AH_FALSE;
+}
+
+void
+ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
+{
+	struct ar5210_desc *ads = AR5210DESC(ds);
+
+	ads->ds_ctl0 |= AR_TxInterReq;
+}
+
+HAL_BOOL
+ar5210FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
+	const struct ath_desc *ds0)
+{
+	struct ar5210_desc *ads = AR5210DESC(ds);
+
+	HALASSERT((segLen &~ AR_BufLen) == 0);
+
+	if (firstSeg) {
+		/*
+		 * First descriptor, don't clobber xmit control data
+		 * setup by ar5210SetupTxDesc.
+		 */
+		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
+	} else if (lastSeg) {		/* !firstSeg && lastSeg */
+		/*
+		 * Last descriptor in a multi-descriptor frame,
+		 * copy the transmit parameters from the first
+		 * frame for processing on completion. 
+		 */
+		ads->ds_ctl0 = AR5210DESC_CONST(ds0)->ds_ctl0;
+		ads->ds_ctl1 = segLen;
+	} else {			/* !firstSeg && !lastSeg */
+		/*
+		 * Intermediate descriptor in a multi-descriptor frame.
+		 */
+		ads->ds_ctl0 = 0;
+		ads->ds_ctl1 = segLen | AR_More;
+	}
+	ads->ds_status0 = ads->ds_status1 = 0;
+	return AH_TRUE;
+}
+
+/*
+ * Processing of HW TX descriptor.
+ */
+HAL_STATUS
+ar5210ProcTxDesc(struct ath_hal *ah,
+	struct ath_desc *ds, struct ath_tx_status *ts)
+{
+	struct ar5210_desc *ads = AR5210DESC(ds);
+
+	if ((ads->ds_status1 & AR_Done) == 0)
+		return HAL_EINPROGRESS;
+
+	/* Update software copies of the HW status */
+	ts->ts_seqnum = ads->ds_status1 & AR_SeqNum;
+	ts->ts_tstamp = MS(ads->ds_status0, AR_SendTimestamp);
+	ts->ts_status = 0;
+	if ((ads->ds_status0 & AR_FrmXmitOK) == 0) {
+		if (ads->ds_status0 & AR_ExcessiveRetries)
+			ts->ts_status |= HAL_TXERR_XRETRY;
+		if (ads->ds_status0 & AR_Filtered)
+			ts->ts_status |= HAL_TXERR_FILT;
+		if (ads->ds_status0  & AR_FIFOUnderrun)
+			ts->ts_status |= HAL_TXERR_FIFO;
+	}
+	ts->ts_rate = MS(ads->ds_ctl0, AR_XmitRate);
+	ts->ts_rssi = MS(ads->ds_status1, AR_AckSigStrength);
+	ts->ts_shortretry = MS(ads->ds_status0, AR_ShortRetryCnt);
+	ts->ts_longretry = MS(ads->ds_status0, AR_LongRetryCnt);
+	ts->ts_antenna = 0;		/* NB: don't know */
+	ts->ts_finaltsi = 0;
+
+	return HAL_OK;
+}
+
+/*
+ * Determine which tx queues need interrupt servicing.
+ * STUB.
+ */
+void
+ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
+{
+	return;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210desc.h b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210desc.h
new file mode 100644
index 0000000..d7d382c
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210desc.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210desc.h,v 1.5 2008/11/10 04:08:02 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5210DESC_H
+#define _DEV_ATH_AR5210DESC_H
+
+#include "ah_desc.h"
+
+/*
+ * Defintions for the DMA descriptors used by the Atheros
+ * AR5210/AR5211 and AR5110 Wireless Lan controller parts.
+ */
+
+/* DMA descriptors */
+struct ar5210_desc {
+	uint32_t	ds_link;	/* link pointer */
+	uint32_t	ds_data;	/* data buffer pointer */
+	uint32_t	ds_ctl0;	/* DMA control 0 */
+	uint32_t	ds_ctl1;	/* DMA control 1 */
+	uint32_t	ds_status0;	/* DMA status 0 */
+	uint32_t	ds_status1;	/* DMA status 1 */
+} __packed;
+#define	AR5210DESC(_ds)	((struct ar5210_desc *)(_ds))
+#define	AR5210DESC_CONST(_ds)	((const struct ar5210_desc *)(_ds))
+
+/* TX ds_ctl0 */
+#define	AR_FrameLen		0x00000fff	/* frame length */
+#define	AR_HdrLen		0x0003f000	/* header length */
+#define	AR_HdrLen_S		12
+#define	AR_XmitRate		0x003c0000	/* txrate */
+#define	AR_XmitRate_S		18
+#define	AR_Rate_6M		0xb
+#define	AR_Rate_9M		0xf
+#define	AR_Rate_12M		0xa
+#define	AR_Rate_18M		0xe
+#define	AR_Rate_24M		0x9
+#define	AR_Rate_36M		0xd
+#define	AR_Rate_48M		0x8
+#define	AR_Rate_54M		0xc
+#define	AR_RTSCTSEnable		0x00400000	/* RTS/CTS enable */
+#define	AR_LongPkt		0x00800000	/* long packet indication */
+#define	AR_ClearDestMask	0x01000000	/* Clear destination mask bit */
+#define	AR_AntModeXmit		0x02000000	/* TX antenna seslection */
+#define	AR_FrmType		0x1c000000	/* frame type indication */
+#define	AR_Frm_Normal		0x00000000	/* normal frame */
+#define	AR_Frm_ATIM		0x04000000	/* ATIM frame */
+#define	AR_Frm_PSPOLL		0x08000000	/* PS poll frame */
+#define	AR_Frm_NoDelay		0x0c000000	/* no delay data */
+#define	AR_Frm_PIFS		0x10000000	/* PIFS data */
+#define	AR_TxInterReq		0x20000000	/* TX interrupt request */
+#define	AR_EncryptKeyValid	0x40000000	/* EncryptKeyIdx is valid */
+
+/* TX ds_ctl1 */
+#define	AR_BufLen		0x00000fff	/* data buffer length */
+#define	AR_More			0x00001000	/* more desc in this frame */
+#define	AR_EncryptKeyIdx	0x0007e000	/* ecnrypt key table index */
+#define	AR_EncryptKeyIdx_S	13
+#define	AR_RTSDuration		0xfff80000	/* lower 13bit of duration */
+
+/* RX ds_ctl1 */
+/*	AR_BufLen		0x00000fff	   data buffer length */
+#define	AR_RxInterReq		0x00002000	/* RX interrupt request */
+
+/* TX ds_status0 */
+#define	AR_FrmXmitOK		0x00000001	/* TX success */
+#define	AR_ExcessiveRetries	0x00000002	/* excessive retries */
+#define	AR_FIFOUnderrun		0x00000004	/* TX FIFO underrun */
+#define	AR_Filtered		0x00000008	/* TX filter indication */
+/* NB: the spec has the Short+Long retry counts reversed */
+#define	AR_LongRetryCnt		0x000000f0	/* long retry count */
+#define	AR_LongRetryCnt_S	4
+#define	AR_ShortRetryCnt	0x00000f00	/* short retry count */
+#define	AR_ShortRetryCnt_S	8
+#define	AR_SendTimestamp	0xffff0000	/* TX timestamp */
+#define	AR_SendTimestamp_S	16
+
+/* RX ds_status0 */
+#define	AR_DataLen		0x00000fff	/* RX data length */
+/*	AR_More			0x00001000	   more desc in this frame */
+#define	AR_RcvAntenna		0x00004000	/* received on ant 1 */
+#define	AR_RcvRate		0x00078000	/* reception rate */
+#define	AR_RcvRate_S		15
+#define	AR_RcvSigStrength	0x07f80000	/* receive signal strength */
+#define	AR_RcvSigStrength_S	19
+
+/* TX ds_status1 */
+#define	AR_Done			0x00000001	/* descripter complete */
+#define	AR_SeqNum		0x00001ffe	/* TX sequence number */
+#define	AR_AckSigStrength	0x001fe000	/* strength of ACK */
+#define	AR_AckSigStrength_S	13
+
+/* RX ds_status1 */
+/*	AR_Done			0x00000001	   descripter complete */
+#define	AR_FrmRcvOK		0x00000002	/* frame reception success */
+#define	AR_CRCErr		0x00000004	/* CRC error */
+#define	AR_FIFOOverrun		0x00000008	/* RX FIFO overrun */
+#define	AR_DecryptCRCErr	0x00000010	/* Decryption CRC fiailure */
+#define	AR_PHYErr		0x000000e0	/* PHY error */
+#define	AR_PHYErr_S		5
+#define	AR_PHYErr_NoErr		0x00000000	/* No error */
+#define	AR_PHYErr_Tim		0x00000020	/* Timing error */
+#define	AR_PHYErr_Par		0x00000040	/* Parity error */
+#define	AR_PHYErr_Rate		0x00000060	/* Illegal rate */
+#define	AR_PHYErr_Len		0x00000080	/* Illegal length */
+#define	AR_PHYErr_QAM		0x000000a0	/* 64 QAM rate */
+#define	AR_PHYErr_Srv		0x000000c0	/* Service bit error */
+#define	AR_PHYErr_TOR		0x000000e0	/* Transmit override receive */
+#define	AR_KeyIdxValid		0x00000100	/* decryption key index valid */
+#define	AR_KeyIdx		0x00007e00	/* Decryption key index */
+#define	AR_KeyIdx_S		9
+#define	AR_RcvTimestamp		0x0fff8000	/* timestamp */
+#define	AR_RcvTimestamp_S	15
+#define	AR_KeyCacheMiss		0x10000000	/* key cache miss indication */
+
+#endif /* _DEV_ATH_AR5210DESC_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210phy.h b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210phy.h
new file mode 100644
index 0000000..6211613
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210phy.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210phy.h,v 1.4 2008/11/10 01:19:37 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5210PHY_H
+#define _DEV_ATH_AR5210PHY_H
+
+/*
+ * Definitions for the PHY on the Atheros AR5210 parts.
+ */
+
+/* PHY Registers */
+#define	AR_PHY_BASE		0x9800		/* PHY register base */
+#define	AR_PHY(_n)		(AR_PHY_BASE + ((_n)<<2))
+
+#define	AR_PHY_FRCTL		0x9804		/* PHY frame control */
+#define	AR_PHY_TURBO_MODE	0x00000001	/* PHY turbo mode */
+#define	AR_PHY_TURBO_SHORT	0x00000002	/* PHY turbo short symbol */
+#define	AR_PHY_TIMING_ERR	0x01000000	/* Detect PHY timing error */
+#define	AR_PHY_PARITY_ERR	0x02000000	/* Detect signal parity err */
+#define	AR_PHY_ILLRATE_ERR	0x04000000	/* Detect PHY illegal rate */
+#define	AR_PHY_ILLLEN_ERR	0x08000000	/* Detect PHY illegal length */
+#define	AR_PHY_SERVICE_ERR	0x20000000	/* Detect PHY nonzero service */
+#define	AR_PHY_TXURN_ERR	0x40000000	/* DetectPHY TX underrun */
+#define	AR_PHY_FRCTL_BITS \
+	"\20\1TURBO_MODE\2TURBO_SHORT\30TIMING_ERR\31PARITY_ERR\32ILLRATE_ERR"\
+	"\33ILLEN_ERR\35SERVICE_ERR\36TXURN_ERR"
+
+#define	AR_PHY_AGC		0x9808		/* PHY AGC command */
+#define	AR_PHY_AGC_DISABLE	0x08000000	/* Disable PHY AGC */
+#define	AR_PHY_AGC_BITS	"\20\33DISABLE"
+
+#define	AR_PHY_CHIPID		0x9818		/* PHY chip revision */
+
+#define	AR_PHY_ACTIVE		0x981c		/* PHY activation */
+#define	AR_PHY_ENABLE		0x00000001	/* activate PHY */
+#define	AR_PHY_DISABLE		0x00000002	/* deactivate PHY */
+#define	AR_PHY_ACTIVE_BITS	"\20\1ENABLE\2DISABLE"
+
+#define	AR_PHY_AGCCTL		0x9860		/* PHY calibration and noise floor */
+#define	AR_PHY_AGC_CAL		0x00000001	/* PHY internal calibration */
+#define	AR_PHY_AGC_NF		0x00000002	/* calc PHY noise-floor */
+#define	AR_PHY_AGCCTL_BITS	"\20\1CAL\2NF"
+
+#endif /* _DEV_ATH_AR5210PHY_H */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210reg.h b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210reg.h
new file mode 100644
index 0000000..dc49fcd
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5210reg.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5210reg.h,v 1.4 2008/11/10 01:19:37 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5210REG_H
+#define _DEV_ATH_AR5210REG_H
+
+/*
+ * Register defintions for the Atheros AR5210/5110 MAC/Basedband
+ * Processor for IEEE 802.11a 5-GHz Wireless LANs.
+ */
+
+#ifndef PCI_VENDOR_ATHEROS
+#define	PCI_VENDOR_ATHEROS		0x168c
+#endif
+#define	PCI_PRODUCT_ATHEROS_AR5210	0x0007
+#define	PCI_PRODUCT_ATHEROS_AR5210_OLD	0x0004
+
+/* DMA Registers */
+#define	AR_TXDP0	0x0000		/* TX queue pointer 0 register */
+#define	AR_TXDP1	0x0004		/* TX queue pointer 1 register */
+#define	AR_CR		0x0008		/* Command register */
+#define	AR_RXDP		0x000c		/* RX queue descriptor ptr register */
+#define	AR_CFG		0x0014		/* Configuration and status register */
+#define	AR_ISR		0x001c		/* Interrupt status register */
+#define	AR_IMR		0x0020		/* Interrupt mask register */
+#define	AR_IER		0x0024		/* Interrupt global enable register */
+#define	AR_BCR		0x0028		/* Beacon control register */
+#define	AR_BSR		0x002c		/* Beacon status register */
+#define	AR_TXCFG	0x0030		/* TX configuration register */
+#define	AR_RXCFG	0x0034		/* RX configuration register */
+#define	AR_MIBC		0x0040		/* MIB control register */
+#define	AR_TOPS		0x0044		/* Timeout prescale register */
+#define	AR_RXNOFRM	0x0048		/* RX no frame timeout register */
+#define	AR_TXNOFRM	0x004c		/* TX no frame timeout register */
+#define	AR_RPGTO	0x0050		/* RX frame gap timeout register */
+#define	AR_RFCNT	0x0054		/* RX frame count limit register */
+#define	AR_MISC		0x0058		/* Misc control and status register */
+#define	AR_RC		0x4000		/* Reset control */
+#define	AR_SCR		0x4004		/* Sleep control */
+#define	AR_INTPEND	0x4008		/* Interrupt pending */
+#define	AR_SFR		0x400c		/* Force sleep */
+#define	AR_PCICFG	0x4010		/* PCI configuration */
+#define	AR_GPIOCR	0x4014		/* GPIO configuration */
+#define	AR_GPIODO	0x4018		/* GPIO data output */
+#define	AR_GPIODI	0x401c		/* GPIO data input */
+#define	AR_SREV		0x4020		/* Silicon revision */
+/* EEPROM Access Registers */
+#define	AR_EP_AIR_BASE	0x6000		/* EEPROM access initiation regs base */
+#define	AR_EP_AIR(n)	(AR_EP_AIR_BASE + (n)*4)
+#define	AR_EP_RDATA	0x6800		/* EEPROM read data register */
+#define	AR_EP_STA	0x6c00		/* EEPROM access status register */
+/* PCU Registers */
+#define	AR_STA_ID0	0x8000		/* Lower 32bits of MAC address */
+#define	AR_STA_ID1	0x8004		/* Upper 16bits of MAC address */
+#define	AR_BSS_ID0	0x8008		/* Lower 32bits of BSSID */
+#define	AR_BSS_ID1	0x800c		/* Upper 16bits of BSSID */
+#define	AR_SLOT_TIME	0x8010		/* Length of a back-off */
+#define	AR_TIME_OUT	0x8014		/* Timeout to wait for ACK and CTS */
+#define	AR_RSSI_THR	0x8018		/* Beacon RSSI warning threshold */
+#define	AR_RETRY_LMT	0x801c		/* Short and long frame retry limit */
+#define	AR_USEC		0x8020		/* Transmit latency */
+#define	AR_BEACON	0x8024		/* Beacon control */
+#define	AR_CFP_PERIOD	0x8028		/* CFP period */
+#define	AR_TIMER0	0x802c		/* Next beacon time */
+#define	AR_TIMER1	0x8030		/* Next DMA beacon alert time */
+#define	AR_TIMER2	0x8034		/* Next software beacon alert time */
+#define	AR_TIMER3	0x8038		/* Next ATIM window time */
+#define	AR_IFS0		0x8040		/* Protocol timers */
+#define	AR_IFS1		0x8044		/* Protocol time and control */
+#define	AR_CFP_DUR	0x8048		/* Maximum CFP duration */
+#define	AR_RX_FILTER	0x804c		/* Receive filter */
+#define	AR_MCAST_FIL0	0x8050		/* Lower 32bits of mcast filter mask */
+#define	AR_MCAST_FIL1	0x8054		/* Upper 16bits of mcast filter mask */
+#define	AR_TX_MASK0	0x8058		/* Lower 32bits of TX mask */
+#define	AR_TX_MASK1	0x805c		/* Upper 16bits of TX mask */
+#define	AR_CLR_TMASK	0x8060		/* Clear TX mask */
+#define	AR_TRIG_LEV	0x8064		/* Minimum FIFO fill level before TX */
+#define	AR_DIAG_SW	0x8068		/* PCU control */
+#define	AR_TSF_L32	0x806c		/* Lower 32bits of local clock */
+#define	AR_TSF_U32	0x8070		/* Upper 32bits of local clock */
+#define	AR_LAST_TSTP	0x8080		/* Lower 32bits of last beacon tstamp */
+#define	AR_RETRY_CNT	0x8084		/* Current short or long retry cnt */
+#define	AR_BACKOFF	0x8088		/* Back-off status */
+#define	AR_NAV		0x808c		/* Current NAV value */
+#define	AR_RTS_OK	0x8090		/* RTS success counter */
+#define	AR_RTS_FAIL	0x8094		/* RTS failure counter */
+#define	AR_ACK_FAIL	0x8098		/* ACK failure counter */
+#define	AR_FCS_FAIL	0x809c		/* FCS failure counter */
+#define	AR_BEACON_CNT	0x80a0		/* Valid beacon counter */
+#define	AR_KEYTABLE_0	0x9000		/* Encryption key table */
+#define	AR_KEYTABLE(n)	(AR_KEYTABLE_0 + ((n)*32))
+
+#define	AR_CR_TXE0		0x00000001	/* TX queue 0 enable */
+#define	AR_CR_TXE1		0x00000002	/* TX queue 1 enable */
+#define	AR_CR_RXE		0x00000004	/* RX enable */
+#define	AR_CR_TXD0		0x00000008	/* TX queue 0 disable */
+#define	AR_CR_TXD1		0x00000010	/* TX queue 1 disable */
+#define	AR_CR_RXD		0x00000020	/* RX disable */
+#define	AR_CR_SWI		0x00000040	/* software interrupt */
+#define	AR_CR_BITS \
+	"\20\1TXE0\2TXE1\3RXE\4TXD0\5TXD1\6RXD\7SWI"
+
+#define	AR_CFG_SWTD		0x00000001	/* BE for TX desc */
+#define	AR_CFG_SWTB		0x00000002	/* BE for TX data */
+#define	AR_CFG_SWRD		0x00000004	/* BE for RX desc */
+#define	AR_CFG_SWRB		0x00000008	/* BE for RX data */
+#define	AR_CFG_SWRG		0x00000010	/* BE for registers */
+#define	AR_CFG_EEBS		0x00000200	/* EEPROM busy */
+#define	AR_CFG_TXCNT		0x00007800	/* number of TX desc in Q */
+#define	AR_CFG_TXCNT_S		11
+#define	AR_CFG_TXFSTAT		0x00008000	/* TX DMA status */
+#define	AR_CFG_TXFSTRT		0x00010000	/* re-enable TX DMA */
+#define	AR_CFG_BITS \
+	"\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\14EEBS\17TXFSTAT\20TXFSTRT"
+
+#define	AR_ISR_RXOK_INT		0x00000001	/* RX frame OK */
+#define	AR_ISR_RXDESC_INT	0x00000002	/* RX intr request */
+#define	AR_ISR_RXERR_INT	0x00000004	/* RX error */
+#define	AR_ISR_RXNOFRM_INT	0x00000008	/* no frame received */
+#define	AR_ISR_RXEOL_INT	0x00000010	/* RX desc empty */
+#define	AR_ISR_RXORN_INT	0x00000020	/* RX fifo overrun */
+#define	AR_ISR_TXOK_INT		0x00000040	/* TX frame OK */
+#define	AR_ISR_TXDESC_INT	0x00000080	/* TX intr request */
+#define	AR_ISR_TXERR_INT	0x00000100	/* TX error */
+#define	AR_ISR_TXNOFRM_INT	0x00000200	/* no frame transmitted */
+#define	AR_ISR_TXEOL_INT	0x00000400	/* TX desc empty */
+#define	AR_ISR_TXURN_INT	0x00000800	/* TX fifo underrun */
+#define	AR_ISR_MIB_INT		0x00001000	/* MIB interrupt */
+#define	AR_ISR_SWI_INT		0x00002000	/* software interrupt */
+#define	AR_ISR_RXPHY_INT	0x00004000	/* PHY RX error */
+#define	AR_ISR_RXKCM_INT	0x00008000	/* Key cache miss */
+#define	AR_ISR_SWBA_INT		0x00010000	/* software beacon alert */
+#define	AR_ISR_BRSSI_INT	0x00020000	/* beacon threshold */
+#define	AR_ISR_BMISS_INT	0x00040000	/* beacon missed */
+#define	AR_ISR_MCABT_INT	0x00100000	/* master cycle abort */
+#define	AR_ISR_SSERR_INT	0x00200000	/* SERR on PCI */
+#define	AR_ISR_DPERR_INT	0x00400000	/* Parity error on PCI */
+#define	AR_ISR_GPIO_INT		0x01000000	/* GPIO interrupt */
+#define	AR_ISR_BITS \
+	"\20\1RXOK\2RXDESC\3RXERR\4RXNOFM\5RXEOL\6RXORN\7TXOK\10TXDESC"\
+	"\11TXERR\12TXNOFRM\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"\
+	"\21SWBA\22BRSSI\23BMISS\24MCABT\25SSERR\26DPERR\27GPIO"
+
+#define	AR_IMR_RXOK_INT		0x00000001	/* RX frame OK */
+#define	AR_IMR_RXDESC_INT	0x00000002	/* RX intr request */
+#define	AR_IMR_RXERR_INT	0x00000004	/* RX error */
+#define	AR_IMR_RXNOFRM_INT	0x00000008	/* no frame received */
+#define	AR_IMR_RXEOL_INT	0x00000010	/* RX desc empty */
+#define	AR_IMR_RXORN_INT	0x00000020	/* RX fifo overrun */
+#define	AR_IMR_TXOK_INT		0x00000040	/* TX frame OK */
+#define	AR_IMR_TXDESC_INT	0x00000080	/* TX intr request */
+#define	AR_IMR_TXERR_INT	0x00000100	/* TX error */
+#define	AR_IMR_TXNOFRM_INT	0x00000200	/* no frame transmitted */
+#define	AR_IMR_TXEOL_INT	0x00000400	/* TX desc empty */
+#define	AR_IMR_TXURN_INT	0x00000800	/* TX fifo underrun */
+#define	AR_IMR_MIB_INT		0x00001000	/* MIB interrupt */
+#define	AR_IMR_SWI_INT		0x00002000	/* software interrupt */
+#define	AR_IMR_RXPHY_INT	0x00004000	/* PHY RX error */
+#define	AR_IMR_RXKCM_INT	0x00008000	/* Key cache miss */
+#define	AR_IMR_SWBA_INT		0x00010000	/* software beacon alert */
+#define	AR_IMR_BRSSI_INT	0x00020000	/* beacon threshold */
+#define	AR_IMR_BMISS_INT	0x00040000	/* beacon missed */
+#define	AR_IMR_MCABT_INT	0x00100000	/* master cycle abort */
+#define	AR_IMR_SSERR_INT	0x00200000	/* SERR on PCI */
+#define	AR_IMR_DPERR_INT	0x00400000	/* Parity error on PCI */
+#define	AR_IMR_GPIO_INT		0x01000000	/* GPIO interrupt */
+#define	AR_IMR_BITS	AR_ISR_BITS
+
+#define	AR_IER_DISABLE		0x00000000	/* pseudo-flag */
+#define	AR_IER_ENABLE		0x00000001	/* global interrupt enable */
+#define	AR_IER_BITS	"\20\1ENABLE"
+
+#define	AR_BCR_BCMD		0x00000001	/* ad hoc beacon mode */
+#define	AR_BCR_BDMAE		0x00000002	/* beacon DMA enable */
+#define	AR_BCR_TQ1FV		0x00000004	/* use TXQ1 for non-beacon */
+#define	AR_BCR_TQ1V		0x00000008	/* TXQ1 valid for beacon */
+#define	AR_BCR_BCGET		0x00000010	/* force a beacon fetch */
+#define	AR_BCR_BITS	"\20\1BCMD\2BDMAE\3TQ1FV\4TQ1V\5BCGET"
+
+#define	AR_BSR_BDLYSW		0x00000001	/* software beacon delay */
+#define	AR_BSR_BDLYDMA		0x00000002	/* DMA beacon delay */
+#define	AR_BSR_TXQ1F		0x00000004	/* TXQ1 fetch */
+#define	AR_BSR_ATIMDLY		0x00000008	/* ATIM delay */
+#define	AR_BSR_SNPBCMD		0x00000100	/* snapshot of BCMD */
+#define	AR_BSR_SNPBDMAE		0x00000200	/* snapshot of BDMAE */
+#define	AR_BSR_SNPTQ1FV		0x00000400	/* snapshot of TQ1FV */
+#define	AR_BSR_SNPTQ1V		0x00000800	/* snapshot of TQ1V */
+#define	AR_BSR_SNAPPEDBCRVALID	0x00001000	/* snapshot of BCR are valid */
+#define	AR_BSR_SWBA_CNT		0x00ff0000	/* software beacon alert cnt */
+#define	AR_BSR_BITS \
+	"\20\1BDLYSW\2BDLYDMA\3TXQ1F\4ATIMDLY\11SNPBCMD\12SNPBDMAE"\
+	"\13SNPTQ1FV\14SNPTQ1V\15SNAPPEDBCRVALID"
+
+#define	AR_TXCFG_SDMAMR		0x00000007	/* DMA burst size 2^(2+x) */
+#define	AR_TXCFG_TXFSTP		0x00000008	/* Stop TX DMA on filtered */
+#define	AR_TXCFG_TXFULL		0x00000070	/* TX DMA desc Q full thresh */
+#define	AR_TXCFG_TXCONT_EN	0x00000080	/* Enable continuous TX mode */
+#define	AR_TXCFG_BITS	"\20\3TXFSTP\7TXCONT_EN"
+
+#define	AR_RXCFG_SDMAMW		0x00000007	/* DMA burst size 2^(2+x) */
+#define	AR_RXCFG_ZLFDMA		0x00000010	/* enable zero length DMA */
+
+/* DMA sizes used for both AR_TXCFG_SDMAMR and AR_RXCFG_SDMAMW */
+#define	AR_DMASIZE_4B		0		/* DMA size 4 bytes */
+#define	AR_DMASIZE_8B		1		/* DMA size 8 bytes */
+#define	AR_DMASIZE_16B		2		/* DMA size 16 bytes */
+#define	AR_DMASIZE_32B		3		/* DMA size 32 bytes */
+#define	AR_DMASIZE_64B		4		/* DMA size 64 bytes */
+#define	AR_DMASIZE_128B		5		/* DMA size 128 bytes */
+#define	AR_DMASIZE_256B		6		/* DMA size 256 bytes */
+#define	AR_DMASIZE_512B		7		/* DMA size 512 bytes */
+
+#define	AR_MIBC_COW		0x00000001	/* counter overflow warning */
+#define	AR_MIBC_FMC		0x00000002	/* freeze MIB counters */
+#define	AR_MIBC_CMC		0x00000004	/* clear MIB counters */
+#define	AR_MIBC_MCS		0x00000008	/* MIB counter strobe */
+
+#define	AR_RFCNT_RFCL		0x0000000f	/* RX frame count limit */
+
+#define	AR_MISC_LED_DECAY	0x001c0000	/* LED decay rate */
+#define	AR_MISC_LED_BLINK	0x00e00000	/* LED blink rate */
+
+#define	AR_RC_RPCU		0x00000001	/* PCU Warm Reset */
+#define	AR_RC_RDMA		0x00000002	/* DMA Warm Reset */
+#define	AR_RC_RMAC		0x00000004	/* MAC Warm Reset */
+#define	AR_RC_RPHY		0x00000008	/* PHY Warm Reset */
+#define	AR_RC_RPCI		0x00000010	/* PCI Core Warm Reset */
+#define	AR_RC_BITS	"\20\1RPCU\2RDMA\3RMAC\4RPHY\5RPCI"
+
+#define	AR_SCR_SLDUR		0x0000ffff	/* sleep duration */
+#define	AR_SCR_SLE		0x00030000	/* sleep enable */
+#define	AR_SCR_SLE_S		16
+#define	AR_SCR_SLE_WAKE		0x00000000	/* force wake */
+#define	AR_SCR_SLE_SLP		0x00010000	/* force sleep */
+#define	AR_SCR_SLE_ALLOW	0x00020000	/* allow to control sleep */
+#define	AR_SCR_BITS	"\20\20SLE_SLP\21SLE_ALLOW"
+
+#define	AR_INTPEND_IP		0x00000001	/* interrupt pending */
+#define	AR_INTPEND_BITS	"\20\1IP"
+
+#define	AR_SFR_SF		0x00000001	/* force sleep immediately */
+
+#define	AR_PCICFG_EEPROMSEL	0x00000001	/* EEPROM access enable */
+#define	AR_PCICFG_CLKRUNEN	0x00000004	/* CLKRUN enable */
+#define	AR_PCICFG_LED_PEND	0x00000020	/* LED for assoc pending */
+#define	AR_PCICFG_LED_ACT	0x00000040	/* LED for assoc active */
+#define	AR_PCICFG_SL_INTEN	0x00000800	/* Enable sleep intr */
+#define	AR_PCICFG_LED_BCTL	0x00001000	/* LED blink for local act */
+#define	AR_PCICFG_SL_INPEN	0x00002800	/* sleep even intr pending */
+#define	AR_PCICFG_SPWR_DN	0x00010000	/* sleep indication */
+#define	AR_PCICFG_BITS \
+	"\20\1EEPROMSEL\3CLKRUNEN\5LED_PEND\6LED_ACT\13SL_INTEN"\
+	"\14LED_BCTL\20SPWR_DN"
+
+#define	AR_GPIOCR_IN(n)		(0<<((n)*2))	/* input-only */
+#define	AR_GPIOCR_OUT0(n)	(1<<((n)*2))	/* output-only if GPIODO = 0 */
+#define	AR_GPIOCR_OUT1(n)	(2<<((n)*2))	/* output-only if GPIODO = 1 */
+#define	AR_GPIOCR_OUT(n)	(3<<((n)*2))	/* always output */
+#define	AR_GPIOCR_ALL(n)	(3<<((n)*2))	/* all bits for pin */
+#define	AR_GPIOCR_INT_SEL(n)	((n)<<12)	/* GPIO interrupt pin select */
+#define	AR_GPIOCR_INT_ENA	0x00008000	/* Enable GPIO interrupt */
+#define	AR_GPIOCR_INT_SELL	0x00000000	/* Interrupt if pin is low */
+#define	AR_GPIOCR_INT_SELH	0x00010000	/* Interrupt if pin is high */
+
+#define	AR_SREV_CRETE		4		/* Crete 1st version */
+#define	AR_SREV_CRETE_MS	5		/* Crete FCS version */
+#define	AR_SREV_CRETE_23	8		/* Crete version 2.3 */
+
+#define	AR_EP_STA_RDERR		0x00000001	/* read error */
+#define	AR_EP_STA_RDCMPLT	0x00000002	/* read complete */
+#define	AR_EP_STA_WRERR		0x00000004	/* write error */
+#define	AR_EP_STA_WRCMPLT	0x00000008	/* write complete */
+#define	AR_EP_STA_BITS \
+	"\20\1RDERR\2RDCMPLT\3WRERR\4WRCMPLT"
+
+#define	AR_STA_ID1_AP		0x00010000	/* Access Point Operation */
+#define	AR_STA_ID1_ADHOC	0x00020000	/* ad hoc Operation */
+#define	AR_STA_ID1_PWR_SV	0x00040000	/* power save report enable */
+#define	AR_STA_ID1_NO_KEYSRCH	0x00080000	/* key table search disable */
+#define	AR_STA_ID1_NO_PSPOLL	0x00100000	/* auto PS-POLL disable */
+#define	AR_STA_ID1_PCF		0x00200000	/* PCF observation enable */
+#define	AR_STA_ID1_DESC_ANTENNA 0x00400000	/* use antenna in TX desc */
+#define	AR_STA_ID1_DEFAULT_ANTENNA 0x00800000	/* toggle default antenna */
+#define	AR_STA_ID1_ACKCTS_6MB	0x01000000	/* use 6Mbps for ACK/CTS */
+#define	AR_STA_ID1_BITS \
+	"\20\20AP\21ADHOC\22PWR_SV\23NO_KEYSRCH\24NO_PSPOLL\25PCF"\
+	"\26DESC_ANTENNA\27DEFAULT_ANTENNA\30ACKCTS_6MB"
+
+#define	AR_BSS_ID1_AID		0xffff0000	/* association ID */
+#define	AR_BSS_ID1_AID_S	16
+
+#define	AR_TIME_OUT_ACK		0x00001fff	/* ACK timeout */
+#define	AR_TIME_OUT_ACK_S	0
+#define	AR_TIME_OUT_CTS		0x1fff0000	/* CTS timeout */
+#define	AR_TIME_OUT_CTS_S	16
+
+#define	AR_RSSI_THR_BM_THR	0x00000700	/* missed beacon threshold */
+#define	AR_RSSI_THR_BM_THR_S	8
+
+#define	AR_RETRY_LMT_SH_RETRY	0x0000000f	/* short frame retry limit */
+#define	AR_RETRY_LMT_SH_RETRY_S	0
+#define	AR_RETRY_LMT_LG_RETRY	0x000000f0	/* long frame retry limit */
+#define	AR_RETRY_LMT_LG_RETRY_S	4
+#define	AR_RETRY_LMT_SSH_RETRY	0x00003f00	/* short station retry limit */
+#define	AR_RETRY_LMT_SSH_RETRY_S	8
+#define	AR_RETRY_LMT_SLG_RETRY	0x000fc000	/* long station retry limit */
+#define	AR_RETRY_LMT_SLG_RETRY_S	14
+#define	AR_RETRY_LMT_CW_MIN	0x3ff00000	/* minimum contention window */
+#define	AR_RETRY_LMT_CW_MIN_S		20
+
+#define	AR_USEC_1		0x0000007f	/* number of clk in 1us */
+#define	AR_USEC_1_S		0
+#define	AR_USEC_32		0x00003f80	/* number of 32MHz clk in 1us */
+#define	AR_USEC_32_S		7
+#define	AR_USEC_TX_LATENCY	0x000fc000	/* transmit latency in us */
+#define	AR_USEC_TX_LATENCY_S	14
+#define	AR_USEC_RX_LATENCY	0x03f00000	/* receive latency in us */
+#define	AR_USEC_RX_LATENCY_S	20
+
+#define	AR_BEACON_PERIOD	0x0000ffff	/* beacon period in TU/ms */
+#define	AR_BEACON_PERIOD_S	0
+#define	AR_BEACON_TIM 		0x007f0000	/* byte offset */
+#define	AR_BEACON_TIM_S	16
+#define	AR_BEACON_EN		0x00800000	/* beacon transmission enable */
+#define	AR_BEACON_RESET_TSF 	0x01000000	/* TSF reset oneshot */
+#define	AR_BEACON_BITS	"\20\27ENABLE\30RESET_TSF"
+
+#define	AR_IFS0_SIFS		0x000007ff	/* SIFS in core clock cycles */
+#define	AR_IFS0_SIFS_S		0
+#define	AR_IFS0_DIFS		0x007ff800	/* DIFS in core clock cycles */
+#define	AR_IFS0_DIFS_S		11
+
+#define	AR_IFS1_PIFS		0x00000fff	/* Programmable IFS */
+#define	AR_IFS1_PIFS_S		0
+#define	AR_IFS1_EIFS		0x03fff000	/* EIFS in core clock cycles */
+#define	AR_IFS1_EIFS_S		12
+#define	AR_IFS1_CS_EN		0x04000000	/* carrier sense enable */
+
+#define	AR_RX_FILTER_UNICAST	0x00000001	/* unicast frame enable */
+#define	AR_RX_FILTER_MULTICAST	0x00000002	/* multicast frame enable */
+#define	AR_RX_FILTER_BROADCAST	0x00000004	/* broadcast frame enable */
+#define	AR_RX_FILTER_CONTROL	0x00000008	/* control frame enable */
+#define	AR_RX_FILTER_BEACON	0x00000010	/* beacon frame enable */
+#define	AR_RX_FILTER_PROMISCUOUS 0x00000020	/* promiscuous receive enable */
+#define	AR_RX_FILTER_BITS \
+	"\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC"
+
+#define	AR_DIAG_SW_DIS_WEP_ACK	0x00000001	/* disable ACK if no key found*/
+#define	AR_DIAG_SW_DIS_ACK	0x00000002	/* disable ACK generation */
+#define	AR_DIAG_SW_DIS_CTS	0x00000004	/* disable CTS generation */
+#define	AR_DIAG_SW_DIS_ENC	0x00000008	/* encryption disable */
+#define	AR_DIAG_SW_DIS_DEC	0x00000010	/* decryption disable */
+#define	AR_DIAG_SW_DIS_TX	0x00000020	/* TX disable */
+#define	AR_DIAG_SW_DIS_RX	0x00000040	/* RX disable */
+#define	AR_DIAG_SW_LOOP_BACK	0x00000080	/* TX data loopback enable */
+#define	AR_DIAG_SW_CORR_FCS	0x00000100	/* corrupt FCS enable */
+#define	AR_DIAG_SW_CHAN_INFO	0x00000200	/* channel information enable */
+#define	AR_DIAG_SW_EN_SCRAM_SEED 0x00000400	/* use fixed scrambler seed */
+#define	AR_DIAG_SW_SCVRAM_SEED	0x0003f800	/* fixed scrambler seed */
+#define	AR_DIAG_SW_DIS_SEQ_INC	0x00040000	/* seq increment disable */
+#define	AR_DIAG_SW_FRAME_NV0	0x00080000	/* accept frame vers != 0 */
+#define	AR_DIAG_SW_BITS \
+	"\20\1DIS_WEP_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_TX"\
+	"\7DIS_RX\10LOOP_BACK\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED"\
+	"\22DIS_SEQ_INC\24FRAME_NV0"
+
+#define	AR_RETRY_CNT_SSH	0x0000003f	/* current short retry count */
+#define	AR_RETRY_CNT_SLG	0x00000fc0	/* current long retry count */
+
+#define	AR_BACKOFF_CW		0x000003ff	/* current contention window */
+#define	AR_BACKOFF_CNT		0x03ff0000	/* backoff count */
+
+#define	AR_KEYTABLE_KEY0(n)	(AR_KEYTABLE(n) + 0)	/* key bit 0-31 */
+#define	AR_KEYTABLE_KEY1(n)	(AR_KEYTABLE(n) + 4)	/* key bit 32-47 */
+#define	AR_KEYTABLE_KEY2(n)	(AR_KEYTABLE(n) + 8)	/* key bit 48-79 */
+#define	AR_KEYTABLE_KEY3(n)	(AR_KEYTABLE(n) + 12)	/* key bit 80-95 */
+#define	AR_KEYTABLE_KEY4(n)	(AR_KEYTABLE(n) + 16)	/* key bit 96-127 */
+#define	AR_KEYTABLE_TYPE(n)	(AR_KEYTABLE(n) + 20)	/* key type */
+#define	AR_KEYTABLE_TYPE_40	0x00000000	/* 40 bit key */
+#define	AR_KEYTABLE_TYPE_104	0x00000001	/* 104 bit key */
+#define	AR_KEYTABLE_TYPE_128	0x00000003	/* 128 bit key */
+#define	AR_KEYTABLE_MAC0(n)	(AR_KEYTABLE(n) + 24)	/* MAC address 1-32 */
+#define	AR_KEYTABLE_MAC1(n)	(AR_KEYTABLE(n) + 28)	/* MAC address 33-47 */
+#define	AR_KEYTABLE_VALID	0x00008000	/* key and MAC address valid */
+
+#endif /* _DEV_ATH_AR5210REG_H */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5k_0007.ini b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5k_0007.ini
new file mode 100644
index 0000000..b0285e9
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5210/ar5k_0007.ini
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5k_0007.ini,v 1.2 2008/11/10 01:19:37 sam Exp $
+ */
+
+    /* crete register init */
+    { 0x00009800, 0x00000047 },
+    { 0x00009808, 0x00000000 },
+    { 0x0000980c, 0x09848ea6 },
+    { 0x00009810, 0x3d32e000 },
+    { 0x00009814, 0x0000076b },
+    { 0x0000981c, 0x00000000 },
+    { 0x00009820, 0x02020200 },
+    { 0x00009824, 0x00000e0e },
+    { 0x00009828, 0x0a020201 },
+    { 0x0000982c, 0x00036ffc },
+    { 0x00009830, 0x00000000 },
+    { 0x00009834, 0x00000e0e },
+    { 0x00009838, 0x00000007 },
+    { 0x0000983c, 0x00020100 },
+    { 0x00009840, 0x89630000 },
+    { 0x00009844, 0x1372169c },
+    { 0x00009848, 0x0018b633 },
+    { 0x0000984c, 0x1284613c },
+    { 0x00009850, 0x0de8b8e0 },
+    { 0x00009854, 0x00074859 },
+    { 0x00009858, 0x7e80beba },
+    { 0x0000985c, 0x313a665e },
+    { 0x00009860, 0x00001d08 },
+    { 0x00009864, 0x0001ce00 },
+    { 0x00009868, 0x409a4190 },
+    { 0x00009870, 0x0000000f },
+    { 0x00009874, 0x00000080 },
+    { 0x00009878, 0x00000004 },
+    { 0x00009900, 0x00000000 },
+    { 0x00009904, 0x00000000 },
+    { 0x00009908, 0x00000000 },
+    { 0x0000990c, 0x00800000 },
+    { 0x00009910, 0x00000003 },
+
+
+    /* bb gain table */
+    { 0x00009b00, 0x00000000 },
+    { 0x00009b04, 0x00000020 },
+    { 0x00009b08, 0x00000010 },
+    { 0x00009b0c, 0x00000030 },
+    { 0x00009b10, 0x00000008 },
+    { 0x00009b14, 0x00000028 },
+    { 0x00009b18, 0x00000028 },
+    { 0x00009b1c, 0x00000004 },
+    { 0x00009b20, 0x00000024 },
+    { 0x00009b24, 0x00000014 },
+    { 0x00009b28, 0x00000034 },
+    { 0x00009b2c, 0x0000000c },
+    { 0x00009b30, 0x0000002c },
+    { 0x00009b34, 0x00000002 },
+    { 0x00009b38, 0x00000022 },
+    { 0x00009b3c, 0x00000012 },
+    { 0x00009b40, 0x00000032 },
+    { 0x00009b44, 0x0000000a },
+    { 0x00009b48, 0x0000002a },
+    { 0x00009b4c, 0x00000001 },
+    { 0x00009b50, 0x00000021 },
+    { 0x00009b54, 0x00000011 },
+    { 0x00009b58, 0x00000031 },
+    { 0x00009b5c, 0x00000009 },
+    { 0x00009b60, 0x00000029 },
+    { 0x00009b64, 0x00000005 },
+    { 0x00009b68, 0x00000025 },
+    { 0x00009b6c, 0x00000015 },
+    { 0x00009b70, 0x00000035 },
+    { 0x00009b74, 0x0000000d },
+    { 0x00009b78, 0x0000002d },
+    { 0x00009b7c, 0x00000003 },
+    { 0x00009b80, 0x00000023 },
+    { 0x00009b84, 0x00000013 },
+    { 0x00009b88, 0x00000033 },
+    { 0x00009b8c, 0x0000000b },
+    { 0x00009b90, 0x0000002b },
+    { 0x00009b94, 0x00000007 },
+    { 0x00009b98, 0x00000027 },
+    { 0x00009b9c, 0x00000017 },
+    { 0x00009ba0, 0x00000037 },
+    { 0x00009ba4, 0x0000000f },
+    { 0x00009ba8, 0x0000002f },
+    { 0x00009bac, 0x0000002f },
+    { 0x00009bb0, 0x0000002f },
+    { 0x00009bb4, 0x0000002f },
+    { 0x00009bb8, 0x0000002f },
+    { 0x00009bbc, 0x0000002f },
+    { 0x00009bc0, 0x0000002f },
+    { 0x00009bc4, 0x0000002f },
+    { 0x00009bc8, 0x0000002f },
+    { 0x00009bcc, 0x0000002f },
+    { 0x00009bd0, 0x0000002f },
+    { 0x00009bd4, 0x0000002f },
+    { 0x00009bd8, 0x0000002f },
+    { 0x00009bdc, 0x0000002f },
+    { 0x00009be0, 0x0000002f },
+    { 0x00009be4, 0x0000002f },
+    { 0x00009be8, 0x0000002f },
+    { 0x00009bec, 0x0000002f },
+    { 0x00009bf0, 0x0000002f },
+    { 0x00009bf4, 0x0000002f },
+    { 0x00009bf8, 0x0000002f },
+    { 0x00009bfc, 0x0000002f },
+
+    /* rf gain table */
+    { 0x00009a00, 0x0000001d },
+    { 0x00009a04, 0x0000005d },
+    { 0x00009a08, 0x0000009d },
+    { 0x00009a0c, 0x000000dd },
+    { 0x00009a10, 0x0000011d },
+    { 0x00009a14, 0x00000021 },
+    { 0x00009a18, 0x00000061 },
+    { 0x00009a1c, 0x000000a1 },
+    { 0x00009a20, 0x000000e1 },
+    { 0x00009a24, 0x00000031 },
+    { 0x00009a28, 0x00000071 },
+    { 0x00009a2c, 0x000000b1 },
+    { 0x00009a30, 0x0000001c },
+    { 0x00009a34, 0x0000005c },
+    { 0x00009a38, 0x00000029 },
+    { 0x00009a3c, 0x00000069 },
+    { 0x00009a40, 0x000000a9 },
+    { 0x00009a44, 0x00000020 },
+    { 0x00009a48, 0x00000019 },
+    { 0x00009a4c, 0x00000059 },
+    { 0x00009a50, 0x00000099 },
+    { 0x00009a54, 0x00000030 },
+    { 0x00009a58, 0x00000005 },
+    { 0x00009a5c, 0x00000025 },
+    { 0x00009a60, 0x00000065 },
+    { 0x00009a64, 0x000000a5 },
+    { 0x00009a68, 0x00000028 },
+    { 0x00009a6c, 0x00000068 },
+    { 0x00009a70, 0x0000001f },
+    { 0x00009a74, 0x0000001e },
+    { 0x00009a78, 0x00000018 },
+    { 0x00009a7c, 0x00000058 },
+    { 0x00009a80, 0x00000098 },
+    { 0x00009a84, 0x00000003 },
+    { 0x00009a88, 0x00000004 },
+    { 0x00009a8c, 0x00000044 },
+    { 0x00009a90, 0x00000084 },
+    { 0x00009a94, 0x00000013 },
+    { 0x00009a98, 0x00000012 },
+    { 0x00009a9c, 0x00000052 },
+    { 0x00009aa0, 0x00000092 },
+    { 0x00009aa4, 0x000000d2 },
+    { 0x00009aa8, 0x0000002b },
+    { 0x00009aac, 0x0000002a },
+    { 0x00009ab0, 0x0000006a },
+    { 0x00009ab4, 0x000000aa },
+    { 0x00009ab8, 0x0000001b },
+    { 0x00009abc, 0x0000001a },
+    { 0x00009ac0, 0x0000005a },
+    { 0x00009ac4, 0x0000009a },
+    { 0x00009ac8, 0x000000da },
+    { 0x00009acc, 0x00000006 },
+    { 0x00009ad0, 0x00000006 },
+    { 0x00009ad4, 0x00000006 },
+    { 0x00009ad8, 0x00000006 },
+    { 0x00009adc, 0x00000006 },
+    { 0x00009ae0, 0x00000006 },
+    { 0x00009ae4, 0x00000006 },
+    { 0x00009ae8, 0x00000006 },
+    { 0x00009aec, 0x00000006 },
+    { 0x00009af0, 0x00000006 },
+    { 0x00009af4, 0x00000006 },
+    { 0x00009af8, 0x00000006 },
+    { 0x00009afc, 0x00000006 },
+
+    /* fez register init */
+    { 0x000098d4, 0x00000020 },
+    { 0x000098cc, 0x00000004 },
+    { 0x000098c8, 0x00060106 },
+    { 0x0000989c, 0x0000006d },
+    { 0x000098c0, 0x00000000 },
+    { 0x000098d0, 0x00000014 },
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211.h b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211.h
new file mode 100644
index 0000000..e71d78c
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211.h
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211.h,v 1.8 2008/11/10 22:08:47 sam Exp $
+ */
+#ifndef _ATH_AR5211_H_
+#define _ATH_AR5211_H_
+
+#include "ah_eeprom.h"
+
+#define	AR5211_MAGIC	0x19570405
+
+/* Classes for WME streams */
+#define	AC_BK	0
+#define	AC_BE	1
+#define	AC_VI	2
+#define	AC_VO	3
+
+/* DCU Transmit Filter macros */
+#define CALC_MMR(dcu, idx) \
+	( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
+#define TXBLK_FROM_MMR(mmr) \
+	(AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
+#define CALC_TXBLK_ADDR(dcu, idx)	(TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
+#define CALC_TXBLK_VALUE(idx)		(1 << (idx & 0x1f))
+
+/* MAC register values */
+
+#define INIT_INTERRUPT_MASK \
+	( AR_IMR_TXERR  | AR_IMR_TXOK | AR_IMR_RXORN | \
+	  AR_IMR_RXERR  | AR_IMR_RXOK | AR_IMR_TXURN | \
+	  AR_IMR_HIUERR )
+#define INIT_BEACON_CONTROL \
+	( (INIT_RESET_TSF << 24)  | (INIT_BEACON_EN << 23) | \
+	  (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD )
+
+#define INIT_CONFIG_STATUS	0x00000000
+#define INIT_RSSI_THR		0x00000700	/* Missed beacon counter initialized to 0x7 (max is 0xff) */
+#define INIT_IQCAL_LOG_COUNT_MAX	0xF
+#define INIT_BCON_CNTRL_REG	0x00000000
+
+#define INIT_BEACON_PERIOD	0xffff
+#define INIT_TIM_OFFSET		0
+#define INIT_BEACON_EN		0		/* this should be set by AP only when it's ready */
+#define INIT_RESET_TSF		0
+
+/*
+ * Various fifo fill before Tx start, in 64-byte units
+ * i.e. put the frame in the air while still DMAing
+ */
+#define MIN_TX_FIFO_THRESHOLD	   0x1
+#define MAX_TX_FIFO_THRESHOLD	   ((IEEE80211_MAX_LEN / 64) + 1)
+#define INIT_TX_FIFO_THRESHOLD	  MIN_TX_FIFO_THRESHOLD
+
+/*
+ * Gain support.
+ */
+typedef struct _gainOptStep {
+	int16_t	paramVal[4];
+	int32_t	stepGain;
+	int8_t	stepName[16];
+} GAIN_OPTIMIZATION_STEP;
+
+typedef struct {
+	uint32_t	numStepsInLadder;
+	uint32_t	defaultStepNum;
+	GAIN_OPTIMIZATION_STEP optStep[10];
+} GAIN_OPTIMIZATION_LADDER;
+
+typedef struct {
+	uint32_t	currStepNum;
+	uint32_t	currGain;
+	uint32_t	targetGain;
+	uint32_t	loTrig;
+	uint32_t	hiTrig;
+	uint32_t	active;
+	const GAIN_OPTIMIZATION_STEP *currStep;
+} GAIN_VALUES;
+
+enum {
+	RFGAIN_INACTIVE,
+	RFGAIN_READ_REQUESTED,
+	RFGAIN_NEED_CHANGE
+};
+
+/*
+ * Header Info - general parameters and
+ * values set for each chipset board solution
+ * that are programmed every reset
+ */
+struct ath_hal_5211 {
+	struct ath_hal_private	ah_priv;	/* base class */
+
+	GAIN_VALUES	ah_gainValues;
+
+	uint8_t		ah_macaddr[IEEE80211_ADDR_LEN];
+	uint8_t		ah_bssid[IEEE80211_ADDR_LEN];
+
+	/*
+	 * Runtime state.
+	 */
+	uint32_t	ah_maskReg;		/* copy of AR_IMR */
+	uint32_t	ah_txOkInterruptMask;
+	uint32_t	ah_txErrInterruptMask;
+	uint32_t	ah_txDescInterruptMask;
+	uint32_t	ah_txEolInterruptMask;
+	uint32_t	ah_txUrnInterruptMask;
+	HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
+	HAL_POWER_MODE	ah_powerMode;
+	HAL_ANT_SETTING ah_diversityControl;	/* antenna setting */
+	uint32_t	ah_calibrationTime;
+	HAL_BOOL	ah_bIQCalibration;
+	HAL_CHANNEL	ah_curchan;		/* XXX */
+	int		ah_rfgainState;
+	uint32_t	ah_tx6PowerInHalfDbm;	/* power output for 6Mb tx */
+	uint32_t	ah_staId1Defaults;	/* STA_ID1 default settings */
+	uint32_t	ah_beaconInterval;
+	uint32_t	ah_rssiThr;		/* RSSI_THR settings */
+
+	u_int		ah_sifstime;		/* user-specified sifs time */
+	u_int		ah_slottime;		/* user-specified slot time */
+	u_int		ah_acktimeout;		/* user-specified ack timeout */
+	u_int		ah_ctstimeout;		/* user-specified cts timeout */
+	/*
+	 * RF Silent handling.
+	 */
+	uint32_t	ah_gpioSelect;		/* GPIO pin to use */
+	uint32_t	ah_polarity;		/* polarity to disable RF */
+	uint32_t	ah_gpioBit;		/* after init, prev value */
+};
+#define	AH5211(ah)	((struct ath_hal_5211 *)(ah))
+
+struct ath_hal;
+
+extern	struct ath_hal *ar5211Attach(uint16_t, HAL_SOFTC,
+	HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *);
+extern	void ar5211Detach(struct ath_hal *);
+
+extern	HAL_BOOL ar5211Reset(struct ath_hal *, HAL_OPMODE,
+		HAL_CHANNEL *, HAL_BOOL bChannelChange, HAL_STATUS *);
+extern	HAL_BOOL ar5211PhyDisable(struct ath_hal *);
+extern	HAL_BOOL ar5211Disable(struct ath_hal *);
+extern	HAL_BOOL ar5211ChipReset(struct ath_hal *, uint16_t);
+extern	HAL_BOOL ar5211PerCalibration(struct ath_hal *, HAL_CHANNEL *, HAL_BOOL *);
+extern	HAL_BOOL ar5211PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
+		u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
+extern	HAL_BOOL ar5211ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
+extern	HAL_BOOL ar5211SetTxPowerLimit(struct ath_hal *, uint32_t limit);
+extern	HAL_BOOL ar5211SetTransmitPower(struct ath_hal *, HAL_CHANNEL *);
+extern	HAL_BOOL ar5211CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+extern	HAL_BOOL ar5211SetAntennaSwitchInternal(struct ath_hal *,
+		HAL_ANT_SETTING, const HAL_CHANNEL *);
+extern	int16_t ar5211GetNfAdjust(struct ath_hal *,
+		const HAL_CHANNEL_INTERNAL *);
+extern	HAL_BOOL ar5211ResetDma(struct ath_hal *, HAL_OPMODE);
+extern	void ar5211InitializeGainValues(struct ath_hal *);
+extern	HAL_RFGAIN ar5211GetRfgain(struct ath_hal *);
+extern	void ar5211SetPCUConfig(struct ath_hal *);
+
+extern  HAL_BOOL ar5211SetTxQueueProps(struct ath_hal *ah, int q,
+		const HAL_TXQ_INFO *qInfo);
+extern	HAL_BOOL ar5211GetTxQueueProps(struct ath_hal *ah, int q,
+		HAL_TXQ_INFO *qInfo);
+extern	int ar5211SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
+		const HAL_TXQ_INFO *qInfo);
+extern	HAL_BOOL ar5211ReleaseTxQueue(struct ath_hal *ah, u_int q);
+extern	HAL_BOOL ar5211ResetTxQueue(struct ath_hal *ah, u_int q);
+extern	uint32_t ar5211GetTxDP(struct ath_hal *, u_int);
+extern	HAL_BOOL ar5211SetTxDP(struct ath_hal *, u_int, uint32_t txdp);
+extern	HAL_BOOL ar5211UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);
+extern	HAL_BOOL ar5211StartTxDma(struct ath_hal *, u_int);
+extern	HAL_BOOL ar5211StopTxDma(struct ath_hal *, u_int);
+extern	uint32_t ar5211NumTxPending(struct ath_hal *, u_int qnum);
+extern	HAL_BOOL ar5211IsTxQueueStopped(struct ath_hal *, u_int);
+extern	HAL_BOOL ar5211GetTransmitFilterIndex(struct ath_hal *, uint32_t);
+extern	HAL_BOOL ar5211SetupTxDesc(struct ath_hal *, struct ath_desc *,
+		u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
+		u_int txRate0, u_int txTries0,
+		u_int keyIx, u_int antMode, u_int flags,
+		u_int rtsctsRate, u_int rtsctsDuration,
+                u_int compicvLen, u_int compivLen, u_int comp);
+extern	HAL_BOOL ar5211SetupXTxDesc(struct ath_hal *, struct ath_desc *,
+		u_int txRate1, u_int txRetries1,
+		u_int txRate2, u_int txRetries2,
+		u_int txRate3, u_int txRetries3);
+extern	HAL_BOOL ar5211FillTxDesc(struct ath_hal *, struct ath_desc *,
+		u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
+		const struct ath_desc *ds0);
+extern	HAL_STATUS ar5211ProcTxDesc(struct ath_hal *,
+		struct ath_desc *, struct ath_tx_status *);
+extern  void ar5211GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
+extern  void ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
+
+extern	uint32_t ar5211GetRxDP(struct ath_hal *);
+extern	void ar5211SetRxDP(struct ath_hal *, uint32_t rxdp);
+extern	void ar5211EnableReceive(struct ath_hal *);
+extern	HAL_BOOL ar5211StopDmaReceive(struct ath_hal *);
+extern	void ar5211StartPcuReceive(struct ath_hal *);
+extern	void ar5211StopPcuReceive(struct ath_hal *);
+extern	void ar5211SetMulticastFilter(struct ath_hal *,
+		uint32_t filter0, uint32_t filter1);
+extern	HAL_BOOL ar5211ClrMulticastFilterIndex(struct ath_hal *, uint32_t);
+extern	HAL_BOOL ar5211SetMulticastFilterIndex(struct ath_hal *, uint32_t);
+extern	uint32_t ar5211GetRxFilter(struct ath_hal *);
+extern	void ar5211SetRxFilter(struct ath_hal *, uint32_t);
+extern	HAL_BOOL ar5211SetupRxDesc(struct ath_hal *, struct ath_desc *,
+		uint32_t, u_int flags);
+extern	HAL_STATUS ar5211ProcRxDesc(struct ath_hal *, struct ath_desc *,
+		uint32_t, struct ath_desc *, uint64_t,
+		struct ath_rx_status *);
+
+extern	void ar5211GetMacAddress(struct ath_hal *, uint8_t *);
+extern	HAL_BOOL ar5211SetMacAddress(struct ath_hal *ah, const uint8_t *);
+extern	void ar5211GetBssIdMask(struct ath_hal *, uint8_t *);
+extern	HAL_BOOL ar5211SetBssIdMask(struct ath_hal *, const uint8_t *);
+extern	HAL_BOOL ar5211EepromRead(struct ath_hal *, u_int off, uint16_t *data);
+extern	HAL_BOOL ar5211EepromWrite(struct ath_hal *, u_int off, uint16_t data);
+extern	HAL_BOOL ar5211SetRegulatoryDomain(struct ath_hal *,
+		uint16_t, HAL_STATUS *);
+extern	u_int ar5211GetWirelessModes(struct ath_hal *);
+extern	void ar5211EnableRfKill(struct ath_hal *);
+extern	uint32_t ar5211GpioGet(struct ath_hal *, uint32_t gpio);
+extern	void ar5211GpioSetIntr(struct ath_hal *, u_int, uint32_t ilevel);
+extern	HAL_BOOL ar5211GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5211GpioCfgInput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5211GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
+extern	void ar5211SetLedState(struct ath_hal *, HAL_LED_STATE);
+extern	u_int ar5211AntennaGet(struct ath_hal *);
+extern	void ar5211WriteAssocid(struct ath_hal *,
+		const uint8_t *bssid, uint16_t assocId);
+extern	uint64_t ar5211GetTsf64(struct ath_hal *);
+extern	uint32_t ar5211GetTsf32(struct ath_hal *);
+extern	void ar5211ResetTsf(struct ath_hal *);
+extern	uint32_t ar5211GetMaxTurboRate(struct ath_hal *);
+extern	uint32_t ar5211GetRandomSeed(struct ath_hal *);
+extern	HAL_BOOL ar5211DetectCardPresent(struct ath_hal *);
+extern	void ar5211UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);
+extern	void ar5211EnableHwEncryption(struct ath_hal *);
+extern	void ar5211DisableHwEncryption(struct ath_hal *);
+extern	HAL_BOOL ar5211SetSlotTime(struct ath_hal *, u_int);
+extern	u_int ar5211GetSlotTime(struct ath_hal *);
+extern	HAL_BOOL ar5211SetAckTimeout(struct ath_hal *, u_int);
+extern	u_int ar5211GetAckTimeout(struct ath_hal *);
+extern	HAL_BOOL ar5211SetAckCTSRate(struct ath_hal *, u_int);
+extern	u_int ar5211GetAckCTSRate(struct ath_hal *);
+extern	HAL_BOOL ar5211SetCTSTimeout(struct ath_hal *, u_int);
+extern	u_int ar5211GetCTSTimeout(struct ath_hal *);
+extern	HAL_BOOL ar5211SetSifsTime(struct ath_hal *, u_int);
+extern	u_int ar5211GetSifsTime(struct ath_hal *);
+extern  HAL_BOOL ar5211SetDecompMask(struct ath_hal *, uint16_t, int);
+extern	void ar5211SetCoverageClass(struct ath_hal *, uint8_t, int);
+extern	uint32_t ar5211GetCurRssi(struct ath_hal *);
+extern	u_int ar5211GetDefAntenna(struct ath_hal *);
+extern	void ar5211SetDefAntenna(struct ath_hal *ah, u_int antenna);
+extern	HAL_ANT_SETTING ar5211GetAntennaSwitch(struct ath_hal *);
+extern	HAL_BOOL ar5211SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
+extern	HAL_STATUS ar5211GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
+		uint32_t, uint32_t *);
+extern	HAL_BOOL ar5211SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
+		uint32_t, uint32_t, HAL_STATUS *);
+extern	HAL_BOOL ar5211GetDiagState(struct ath_hal *ah, int request,
+		const void *args, uint32_t argsize,
+		void **result, uint32_t *resultsize);
+
+extern	u_int ar5211GetKeyCacheSize(struct ath_hal *);
+extern	HAL_BOOL ar5211IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
+extern	HAL_BOOL ar5211ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);
+extern	HAL_BOOL ar5211SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
+                       const HAL_KEYVAL *, const uint8_t *mac,
+                       int xorKey);
+extern	HAL_BOOL ar5211SetKeyCacheEntryMac(struct ath_hal *,
+			uint16_t, const uint8_t *);
+
+extern	HAL_BOOL ar5211SetPowerMode(struct ath_hal *, uint32_t powerRequest,
+		int setChip);
+extern	HAL_POWER_MODE ar5211GetPowerMode(struct ath_hal *);
+
+extern	void ar5211SetBeaconTimers(struct ath_hal *,
+		const HAL_BEACON_TIMERS *);
+extern	void ar5211BeaconInit(struct ath_hal *, uint32_t, uint32_t);
+extern	void ar5211SetStaBeaconTimers(struct ath_hal *,
+		const HAL_BEACON_STATE *);
+extern	void ar5211ResetStaBeaconTimers(struct ath_hal *);
+
+extern	HAL_BOOL ar5211IsInterruptPending(struct ath_hal *);
+extern	HAL_BOOL ar5211GetPendingInterrupts(struct ath_hal *, HAL_INT *);
+extern	HAL_INT ar5211GetInterrupts(struct ath_hal *);
+extern	HAL_INT ar5211SetInterrupts(struct ath_hal *, HAL_INT ints);
+
+extern	const HAL_RATE_TABLE *ar5211GetRateTable(struct ath_hal *, u_int mode);
+
+extern	HAL_BOOL ar5211AniControl(struct ath_hal *, HAL_ANI_CMD, int );
+extern	void ar5211AniPoll(struct ath_hal *, const HAL_NODE_STATS *, HAL_CHANNEL *);
+extern	void ar5211MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
+#endif /* _ATH_AR5211_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_attach.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_attach.c
new file mode 100644
index 0000000..74b139b
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_attach.c
@@ -0,0 +1,516 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_attach.c,v 1.11 2008/11/27 22:29:52 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+#include "ar5211/ar5211phy.h"
+
+#include "ah_eeprom_v3.h"
+
+static HAL_BOOL ar5211GetChannelEdges(struct ath_hal *ah,
+		uint16_t flags, uint16_t *low, uint16_t *high);
+static HAL_BOOL ar5211GetChipPowerLimits(struct ath_hal *ah,
+		HAL_CHANNEL *chans, uint32_t nchans);
+
+static const struct ath_hal_private ar5211hal = {{
+	.ah_magic			= AR5211_MAGIC,
+	.ah_abi				= HAL_ABI_VERSION,
+	.ah_countryCode			= CTRY_DEFAULT,
+
+	.ah_getRateTable		= ar5211GetRateTable,
+	.ah_detach			= ar5211Detach,
+
+	/* Reset Functions */
+	.ah_reset			= ar5211Reset,
+	.ah_phyDisable			= ar5211PhyDisable,
+	.ah_disable			= ar5211Disable,
+	.ah_setPCUConfig		= ar5211SetPCUConfig,
+	.ah_perCalibration		= ar5211PerCalibration,
+	.ah_perCalibrationN		= ar5211PerCalibrationN,
+	.ah_resetCalValid		= ar5211ResetCalValid,
+	.ah_setTxPowerLimit		= ar5211SetTxPowerLimit,
+	.ah_getChanNoise		= ath_hal_getChanNoise,
+
+	/* Transmit functions */
+	.ah_updateTxTrigLevel		= ar5211UpdateTxTrigLevel,
+	.ah_setupTxQueue		= ar5211SetupTxQueue,
+	.ah_setTxQueueProps             = ar5211SetTxQueueProps,
+	.ah_getTxQueueProps             = ar5211GetTxQueueProps,
+	.ah_releaseTxQueue		= ar5211ReleaseTxQueue,
+	.ah_resetTxQueue		= ar5211ResetTxQueue,
+	.ah_getTxDP			= ar5211GetTxDP,
+	.ah_setTxDP			= ar5211SetTxDP,
+	.ah_numTxPending		= ar5211NumTxPending,
+	.ah_startTxDma			= ar5211StartTxDma,
+	.ah_stopTxDma			= ar5211StopTxDma,
+	.ah_setupTxDesc			= ar5211SetupTxDesc,
+	.ah_setupXTxDesc		= ar5211SetupXTxDesc,
+	.ah_fillTxDesc			= ar5211FillTxDesc,
+	.ah_procTxDesc			= ar5211ProcTxDesc,
+	.ah_getTxIntrQueue		= ar5211GetTxIntrQueue,
+	.ah_reqTxIntrDesc 		= ar5211IntrReqTxDesc,
+
+	/* RX Functions */
+	.ah_getRxDP			= ar5211GetRxDP,
+	.ah_setRxDP			= ar5211SetRxDP,
+	.ah_enableReceive		= ar5211EnableReceive,
+	.ah_stopDmaReceive		= ar5211StopDmaReceive,
+	.ah_startPcuReceive		= ar5211StartPcuReceive,
+	.ah_stopPcuReceive		= ar5211StopPcuReceive,
+	.ah_setMulticastFilter		= ar5211SetMulticastFilter,
+	.ah_setMulticastFilterIndex	= ar5211SetMulticastFilterIndex,
+	.ah_clrMulticastFilterIndex	= ar5211ClrMulticastFilterIndex,
+	.ah_getRxFilter			= ar5211GetRxFilter,
+	.ah_setRxFilter			= ar5211SetRxFilter,
+	.ah_setupRxDesc			= ar5211SetupRxDesc,
+	.ah_procRxDesc			= ar5211ProcRxDesc,
+	.ah_rxMonitor			= ar5211AniPoll,
+	.ah_procMibEvent		= ar5211MibEvent,
+
+	/* Misc Functions */
+	.ah_getCapability		= ar5211GetCapability,
+	.ah_setCapability		= ar5211SetCapability,
+	.ah_getDiagState		= ar5211GetDiagState,
+	.ah_getMacAddress		= ar5211GetMacAddress,
+	.ah_setMacAddress		= ar5211SetMacAddress,
+	.ah_getBssIdMask		= ar5211GetBssIdMask,
+	.ah_setBssIdMask		= ar5211SetBssIdMask,
+	.ah_setRegulatoryDomain		= ar5211SetRegulatoryDomain,
+	.ah_setLedState			= ar5211SetLedState,
+	.ah_writeAssocid		= ar5211WriteAssocid,
+	.ah_gpioCfgInput		= ar5211GpioCfgInput,
+	.ah_gpioCfgOutput		= ar5211GpioCfgOutput,
+	.ah_gpioGet			= ar5211GpioGet,
+	.ah_gpioSet			= ar5211GpioSet,
+	.ah_gpioSetIntr			= ar5211GpioSetIntr,
+	.ah_getTsf32			= ar5211GetTsf32,
+	.ah_getTsf64			= ar5211GetTsf64,
+	.ah_resetTsf			= ar5211ResetTsf,
+	.ah_detectCardPresent		= ar5211DetectCardPresent,
+	.ah_updateMibCounters		= ar5211UpdateMibCounters,
+	.ah_getRfGain			= ar5211GetRfgain,
+	.ah_getDefAntenna		= ar5211GetDefAntenna,
+	.ah_setDefAntenna		= ar5211SetDefAntenna,
+	.ah_getAntennaSwitch		= ar5211GetAntennaSwitch,
+	.ah_setAntennaSwitch		= ar5211SetAntennaSwitch,
+	.ah_setSifsTime			= ar5211SetSifsTime,
+	.ah_getSifsTime			= ar5211GetSifsTime,
+	.ah_setSlotTime			= ar5211SetSlotTime,
+	.ah_getSlotTime			= ar5211GetSlotTime,
+	.ah_setAckTimeout		= ar5211SetAckTimeout,
+	.ah_getAckTimeout		= ar5211GetAckTimeout,
+	.ah_setAckCTSRate		= ar5211SetAckCTSRate,
+	.ah_getAckCTSRate		= ar5211GetAckCTSRate,
+	.ah_setCTSTimeout		= ar5211SetCTSTimeout,
+	.ah_getCTSTimeout		= ar5211GetCTSTimeout,
+	.ah_setDecompMask               = ar5211SetDecompMask,
+	.ah_setCoverageClass            = ar5211SetCoverageClass,
+
+	/* Key Cache Functions */
+	.ah_getKeyCacheSize		= ar5211GetKeyCacheSize,
+	.ah_resetKeyCacheEntry		= ar5211ResetKeyCacheEntry,
+	.ah_isKeyCacheEntryValid	= ar5211IsKeyCacheEntryValid,
+	.ah_setKeyCacheEntry		= ar5211SetKeyCacheEntry,
+	.ah_setKeyCacheEntryMac		= ar5211SetKeyCacheEntryMac,
+
+	/* Power Management Functions */
+	.ah_setPowerMode		= ar5211SetPowerMode,
+	.ah_getPowerMode		= ar5211GetPowerMode,
+
+	/* Beacon Functions */
+	.ah_setBeaconTimers		= ar5211SetBeaconTimers,
+	.ah_beaconInit			= ar5211BeaconInit,
+	.ah_setStationBeaconTimers	= ar5211SetStaBeaconTimers,
+	.ah_resetStationBeaconTimers	= ar5211ResetStaBeaconTimers,
+
+	/* Interrupt Functions */
+	.ah_isInterruptPending		= ar5211IsInterruptPending,
+	.ah_getPendingInterrupts	= ar5211GetPendingInterrupts,
+	.ah_getInterrupts		= ar5211GetInterrupts,
+	.ah_setInterrupts		= ar5211SetInterrupts },
+
+	.ah_getChannelEdges		= ar5211GetChannelEdges,
+	.ah_getWirelessModes		= ar5211GetWirelessModes,
+	.ah_eepromRead			= ar5211EepromRead,
+#ifdef AH_SUPPORT_WRITE_EEPROM
+	.ah_eepromWrite			= ar5211EepromWrite,
+#endif
+	.ah_gpioCfgInput		= ar5211GpioCfgInput,
+	.ah_gpioCfgOutput		= ar5211GpioCfgOutput,
+	.ah_gpioGet			= ar5211GpioGet,
+	.ah_gpioSet			= ar5211GpioSet,
+	.ah_gpioSetIntr			= ar5211GpioSetIntr,
+	.ah_getChipPowerLimits		= ar5211GetChipPowerLimits,
+};
+
+static HAL_BOOL ar5211ChipTest(struct ath_hal *);
+static HAL_BOOL ar5211FillCapabilityInfo(struct ath_hal *ah);
+
+/*
+ * Return the revsion id for the radio chip.  This
+ * fetched via the PHY.
+ */
+static uint32_t
+ar5211GetRadioRev(struct ath_hal *ah)
+{
+	uint32_t val;
+	int i;
+
+	OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);
+	for (i = 0; i < 8; i++)
+		OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);
+	val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff;
+	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
+	return ath_hal_reverseBits(val, 8);
+}
+
+/*
+ * Attach for an AR5211 part.
+ */
+struct ath_hal *
+ar5211Attach(uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+	struct ath_hal_5211 *ahp;
+	struct ath_hal *ah;
+	uint32_t val;
+	uint16_t eeval;
+	HAL_STATUS ecode;
+
+	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
+	    __func__, sc, (void*) st, (void*) sh);
+
+	/* NB: memory is returned zero'd */
+	ahp = ath_hal_malloc(sizeof (struct ath_hal_5211));
+	if (ahp == AH_NULL) {
+		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+		    "%s: cannot allocate memory for state block\n", __func__);
+		ecode = HAL_ENOMEM;
+		goto bad;
+	}
+	ah = &ahp->ah_priv.h;
+	/* set initial values */
+	OS_MEMCPY(&ahp->ah_priv, &ar5211hal, sizeof(struct ath_hal_private));
+	ah->ah_sc = sc;
+	ah->ah_st = st;
+	ah->ah_sh = sh;
+
+	ah->ah_devid = devid;			/* NB: for AH_DEBUG_ALQ */
+	AH_PRIVATE(ah)->ah_devid = devid;
+	AH_PRIVATE(ah)->ah_subvendorid = 0;	/* XXX */
+
+	AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
+	AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX;	/* no scaling */
+
+	ahp->ah_diversityControl = HAL_ANT_VARIABLE;
+	ahp->ah_staId1Defaults = 0;
+	ahp->ah_rssiThr = INIT_RSSI_THR;
+	ahp->ah_sifstime = (u_int) -1;
+	ahp->ah_slottime = (u_int) -1;
+	ahp->ah_acktimeout = (u_int) -1;
+	ahp->ah_ctstimeout = (u_int) -1;
+
+	if (!ar5211ChipReset(ah, AH_FALSE)) {	/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+	if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B) {
+		/* set it back to OFDM mode to be able to read analog rev id */
+		OS_REG_WRITE(ah, AR5211_PHY_MODE, AR5211_PHY_MODE_OFDM);
+		OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
+		OS_DELAY(1000);
+	}
+
+	/* Read Revisions from Chips */
+	val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M;
+	AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
+	AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION_M;
+
+	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_MAUI_2 ||
+	    AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_OAHU) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: Mac Chip Rev 0x%x is not supported by this driver\n",
+		    __func__, AH_PRIVATE(ah)->ah_macVersion);
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+	}
+
+	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
+
+	if (!ar5211ChipTest(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
+		    __func__);
+		ecode = HAL_ESELFTEST;
+		goto bad;
+	}
+
+	/* Set correct Baseband to analog shift setting to access analog chips. */
+	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
+		OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
+	} else {
+		OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
+	}
+	OS_DELAY(2000);
+
+	/* Read Radio Chip Rev Extract */
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5211GetRadioRev(ah);
+	if ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xf0) != RAD5_SREV_MAJOR) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: 5G Radio Chip Rev 0x%02X is not supported by this "
+		    "driver\n", __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+	}
+
+	val = (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_EEPROM_SIZE_M) >>
+               AR_PCICFG_EEPROM_SIZE_S;
+	if (val != AR_PCICFG_EEPROM_SIZE_16K) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unsupported EEPROM size "
+		    "%u (0x%x) found\n", __func__, val, val);
+		ecode = HAL_EESIZE;
+		goto bad;
+	}
+	ecode = ath_hal_legacyEepromAttach(ah);
+	if (ecode != HAL_OK) {
+		goto bad;
+	}
+
+        /* If Bmode and AR5211, verify 2.4 analog exists */
+	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU &&
+	    ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) {
+		/* Set correct Baseband to analog shift setting to access analog chips. */
+		OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007);
+		OS_DELAY(2000);
+		AH_PRIVATE(ah)->ah_analog2GhzRev = ar5211GetRadioRev(ah);
+
+		/* Set baseband for 5GHz chip */
+		OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
+		OS_DELAY(2000);
+		if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != RAD2_SREV_MAJOR) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: 2G Radio Chip Rev 0x%x is not supported by "
+			    "this driver\n", __func__,
+			    AH_PRIVATE(ah)->ah_analog2GhzRev);
+			ecode = HAL_ENOTSUPP;
+			goto bad;
+		}
+	} else {
+		ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_FALSE);
+        }
+
+	ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot read regulatory domain from EEPROM\n",
+		    __func__);
+		goto bad;
+        }
+	AH_PRIVATE(ah)->ah_currentRD = eeval;
+	AH_PRIVATE(ah)->ah_getNfAdjust = ar5211GetNfAdjust;
+
+	/*
+	 * Got everything we need now to setup the capabilities.
+	 */
+	(void) ar5211FillCapabilityInfo(ah);
+
+	/* Initialize gain ladder thermal calibration structure */
+	ar5211InitializeGainValues(ah);
+
+	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error getting mac address from EEPROM\n", __func__);
+		goto bad;
+        }
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
+
+	return ah;
+bad:
+	if (ahp)
+		ar5211Detach((struct ath_hal *) ahp);
+	if (status)
+		*status = ecode;
+	return AH_NULL;
+#undef N
+}
+
+void
+ar5211Detach(struct ath_hal *ah)
+{
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
+
+	HALASSERT(ah != AH_NULL);
+	HALASSERT(ah->ah_magic == AR5211_MAGIC);
+
+	ath_hal_eepromDetach(ah);
+	ath_hal_free(ah);
+}
+
+static HAL_BOOL
+ar5211ChipTest(struct ath_hal *ah)
+{
+	uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
+	uint32_t regHold[2];
+	uint32_t patternData[4] =
+	    { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
+	int i, j;
+
+	/* Test PHY & MAC registers */
+	for (i = 0; i < 2; i++) {
+		uint32_t addr = regAddr[i];
+		uint32_t wrData, rdData;
+
+		regHold[i] = OS_REG_READ(ah, addr);
+		for (j = 0; j < 0x100; j++) {
+			wrData = (j << 16) | j;
+			OS_REG_WRITE(ah, addr, wrData);
+			rdData = OS_REG_READ(ah, addr);
+			if (rdData != wrData) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+				__func__, addr, wrData, rdData);
+				return AH_FALSE;
+			}
+		}
+		for (j = 0; j < 4; j++) {
+			wrData = patternData[j];
+			OS_REG_WRITE(ah, addr, wrData);
+			rdData = OS_REG_READ(ah, addr);
+			if (wrData != rdData) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+					__func__, addr, wrData, rdData);
+				return AH_FALSE;
+			}
+		}
+		OS_REG_WRITE(ah, regAddr[i], regHold[i]);
+	}
+	OS_DELAY(100);
+	return AH_TRUE;
+}
+
+/*
+ * Store the channel edges for the requested operational mode
+ */
+static HAL_BOOL
+ar5211GetChannelEdges(struct ath_hal *ah,
+	uint16_t flags, uint16_t *low, uint16_t *high)
+{
+	if (flags & CHANNEL_5GHZ) {
+		*low = 4920;
+		*high = 6100;
+		return AH_TRUE;
+	}
+	if (flags & CHANNEL_2GHZ && ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) {
+		*low = 2312;
+		*high = 2732;
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+static HAL_BOOL
+ar5211GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans)
+{
+	HAL_CHANNEL *chan;
+	int i;
+
+	/* XXX fill in, this is just a placeholder */
+	for (i = 0; i < nchans; i++) {
+		chan = &chans[i];
+		HALDEBUG(ah, HAL_DEBUG_ATTACH,
+		    "%s: no min/max power for %u/0x%x\n",
+		    __func__, chan->channel, chan->channelFlags);
+		chan->maxTxPower = MAX_RATE_POWER;
+		chan->minTxPower = 0;
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Fill all software cached or static hardware state information.
+ */
+static HAL_BOOL
+ar5211FillCapabilityInfo(struct ath_hal *ah)
+{
+	struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
+	HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
+
+	/* Construct wireless mode from EEPROM */
+	pCap->halWirelessModes = 0;
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
+		pCap->halWirelessModes |= HAL_MODE_11A;
+		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
+			pCap->halWirelessModes |= HAL_MODE_TURBO;
+	}
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
+		pCap->halWirelessModes |= HAL_MODE_11B;
+
+	pCap->halLow2GhzChan = 2312;
+	pCap->halHigh2GhzChan = 2732;
+	pCap->halLow5GhzChan = 4920;
+	pCap->halHigh5GhzChan = 6100;
+
+	pCap->halChanSpreadSupport = AH_TRUE;
+	pCap->halSleepAfterBeaconBroken = AH_TRUE;
+	pCap->halPSPollBroken = AH_TRUE;
+	pCap->halVEOLSupport = AH_TRUE;
+
+	pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
+	pCap->halKeyCacheSize = 128;
+
+	/* XXX not needed */
+	pCap->halChanHalfRate = AH_FALSE;
+	pCap->halChanQuarterRate = AH_FALSE;
+
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
+	    ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
+		/* NB: enabled by default */
+		ahpriv->ah_rfkillEnabled = AH_TRUE;
+		pCap->halRfSilentSupport = AH_TRUE;
+	}
+
+	pCap->halTstampPrecision = 13;
+
+	/* XXX might be ok w/ some chip revs */
+	ahpriv->ah_rxornIsFatal = AH_TRUE;
+	return AH_TRUE;
+}
+
+static const char*
+ar5211Probe(uint16_t vendorid, uint16_t devid)
+{
+	if (vendorid == ATHEROS_VENDOR_ID) {
+		if (devid == AR5211_DEVID || devid == AR5311_DEVID ||
+		    devid == AR5211_DEFAULT)
+			return "Atheros 5211";
+		if (devid == AR5211_FPGA11B)
+			return "Atheros 5211 (FPGA)";
+	}
+	return AH_NULL;
+}
+AH_CHIP(AR5211, ar5211Probe, ar5211Attach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_beacon.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_beacon.c
new file mode 100644
index 0000000..74207a3
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_beacon.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_beacon.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+#include "ar5211/ar5211desc.h"
+
+/*
+ * Routines used to initialize and generated beacons for the AR5211/AR5311.
+ */
+
+/*
+ * Initialize all of the hardware registers used to send beacons.
+ */
+void
+ar5211SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
+{
+
+	OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
+	OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
+	OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
+	OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
+	/*
+	 * Set the Beacon register after setting all timers.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
+}
+
+/*
+ * Legacy api to initialize all of the beacon registers.
+ */
+void
+ar5211BeaconInit(struct ath_hal *ah,
+	uint32_t next_beacon, uint32_t beacon_period)
+{
+	HAL_BEACON_TIMERS bt;
+
+	bt.bt_nexttbtt = next_beacon;
+	/* 
+	 * TIMER1: in AP/adhoc mode this controls the DMA beacon
+	 * alert timer; otherwise it controls the next wakeup time.
+	 * TIMER2: in AP mode, it controls the SBA beacon alert
+	 * interrupt; otherwise it sets the start of the next CFP.
+	 */
+	switch (AH_PRIVATE(ah)->ah_opmode) {
+	case HAL_M_STA:
+	case HAL_M_MONITOR:
+		bt.bt_nextdba = 0xffff;
+		bt.bt_nextswba = 0x7ffff;
+		break;
+	case HAL_M_IBSS:
+	case HAL_M_HOSTAP:
+		bt.bt_nextdba = (next_beacon -
+			ath_hal_dma_beacon_response_time) << 3;	/* 1/8 TU */
+		bt.bt_nextswba = (next_beacon -
+			ath_hal_sw_beacon_response_time) << 3;	/* 1/8 TU */
+		break;
+	}
+	/*
+	 * Set the ATIM window 
+	 * Our hardware does not support an ATIM window of 0
+	 * (beacons will not work).  If the ATIM windows is 0,
+	 * force it to 1.
+	 */
+	bt.bt_nextatim = next_beacon + 1;
+	bt.bt_intval = beacon_period &
+		(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
+	ar5211SetBeaconTimers(ah, &bt);
+}
+
+void
+ar5211ResetStaBeaconTimers(struct ath_hal *ah)
+{
+	uint32_t val;
+
+	OS_REG_WRITE(ah, AR_TIMER0, 0);		/* no beacons */
+	val = OS_REG_READ(ah, AR_STA_ID1);
+	val |= AR_STA_ID1_PWR_SAV;		/* XXX */
+	/* tell the h/w that the associated AP is not PCF capable */
+	OS_REG_WRITE(ah, AR_STA_ID1,
+		val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
+	OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
+}
+
+/*
+ * Set all the beacon related bits on the h/w for stations
+ * i.e. initializes the corresponding h/w timers;
+ * also tells the h/w whether to anticipate PCF beacons
+ */
+void
+ar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
+
+	HALASSERT(bs->bs_intval != 0);
+	/* if the AP will do PCF */
+	if (bs->bs_cfpmaxduration != 0) {
+		/* tell the h/w that the associated AP is PCF capable */
+		OS_REG_WRITE(ah, AR_STA_ID1,
+			OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
+
+		/* set CFP_PERIOD(1.024ms) register */
+		OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
+
+		/* set CFP_DUR(1.024ms) register to max cfp duration */
+		OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
+
+		/* set TIMER2(128us) to anticipated time of next CFP */
+		OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
+	} else {
+		/* tell the h/w that the associated AP is not PCF capable */
+		OS_REG_WRITE(ah, AR_STA_ID1,
+			OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
+	}
+
+	/*
+	 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
+	 */
+	OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
+
+	/*
+	 * Start the beacon timers by setting the BEACON register
+	 * to the beacon interval; also write the tim offset which
+	 * we should know by now.  The code, in ar5211WriteAssocid,
+	 * also sets the tim offset once the AID is known which can
+	 * be left as such for now.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON, 
+		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
+		| SM(bs->bs_intval, AR_BEACON_PERIOD)
+		| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
+	);
+
+	/*
+	 * Configure the BMISS interrupt.  Note that we
+	 * assume the caller blocks interrupts while enabling
+	 * the threshold.
+	 */
+	HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
+	ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
+			| SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
+	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
+
+	/*
+	 * Set the sleep duration in 1/8 TU's.
+	 */
+#define	SLEEP_SLOP	3
+	OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,
+		(bs->bs_sleepduration - SLEEP_SLOP) << 3);
+#undef SLEEP_SLOP
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_interrupts.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_interrupts.c
new file mode 100644
index 0000000..26035b8
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_interrupts.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_interrupts.c,v 1.6 2008/11/27 22:29:52 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+
+/*
+ * Checks to see if an interrupt is pending on our NIC
+ *
+ * Returns: TRUE    if an interrupt is pending
+ *          FALSE   if not
+ */
+HAL_BOOL
+ar5211IsInterruptPending(struct ath_hal *ah)
+{
+	return OS_REG_READ(ah, AR_INTPEND) != 0;
+}
+
+/*
+ * Reads the Interrupt Status Register value from the NIC, thus deasserting
+ * the interrupt line, and returns both the masked and unmasked mapped ISR
+ * values.  The value returned is mapped to abstract the hw-specific bit
+ * locations in the Interrupt Status Register.
+ *
+ * Returns: A hardware-abstracted bitmap of all non-masked-out
+ *          interrupts pending, as well as an unmasked value
+ */
+HAL_BOOL
+ar5211GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
+{
+	uint32_t isr;
+
+	isr = OS_REG_READ(ah, AR_ISR_RAC);
+	if (isr == 0xffffffff) {
+		*masked = 0;
+		return AH_FALSE;
+	}
+
+	*masked = isr & HAL_INT_COMMON;
+
+	if (isr & AR_ISR_HIUERR)
+		*masked |= HAL_INT_FATAL;
+	if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
+		*masked |= HAL_INT_RX;
+	if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL))
+		*masked |= HAL_INT_TX;
+	/*
+	 * Receive overrun is usually non-fatal on Oahu/Spirit.
+	 * BUT on some parts rx could fail and the chip must be reset.
+	 * So we force a hardware reset in all cases.
+	 */
+	if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: receive FIFO overrun interrupt\n", __func__);
+		*masked |= HAL_INT_FATAL;
+	}
+
+	/*
+	 * On fatal errors collect ISR state for debugging.
+	 */
+	if (*masked & HAL_INT_FATAL) {
+		AH_PRIVATE(ah)->ah_fatalState[0] = isr;
+		AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
+		AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
+		AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
+		AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);
+		AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n",
+		    __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]);
+	}
+	return AH_TRUE;
+}
+
+HAL_INT
+ar5211GetInterrupts(struct ath_hal *ah)
+{
+	return AH5211(ah)->ah_maskReg;
+}
+
+/*
+ * Atomically enables NIC interrupts.  Interrupts are passed in
+ * via the enumerated bitmask in ints.
+ */
+HAL_INT
+ar5211SetInterrupts(struct ath_hal *ah, HAL_INT ints)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	uint32_t omask = ahp->ah_maskReg;
+	uint32_t mask;
+
+	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
+	    __func__, omask, ints);
+
+	/*
+	 * Disable interrupts here before reading & modifying
+	 * the mask so that the ISR does not modify the mask
+	 * out from under us.
+	 */
+	if (omask & HAL_INT_GLOBAL) {
+		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
+		OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+		/* XXX??? */
+		(void) OS_REG_READ(ah, AR_IER);	/* flush write to HW */
+	}
+
+	mask = ints & HAL_INT_COMMON;
+	if (ints & HAL_INT_TX) {
+		if (ahp->ah_txOkInterruptMask)
+			mask |= AR_IMR_TXOK;
+		if (ahp->ah_txErrInterruptMask)
+			mask |= AR_IMR_TXERR;
+		if (ahp->ah_txDescInterruptMask)
+			mask |= AR_IMR_TXDESC;
+		if (ahp->ah_txEolInterruptMask)
+			mask |= AR_IMR_TXEOL;
+	}
+	if (ints & HAL_INT_RX)
+		mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
+	if (ints & HAL_INT_FATAL) {
+		/*
+		 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
+		 *     so enabling HIUERR enables delivery.
+		 */
+		mask |= AR_IMR_HIUERR;
+	}
+
+	/* Write the new IMR and store off our SW copy. */
+	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
+	OS_REG_WRITE(ah, AR_IMR, mask);
+	ahp->ah_maskReg = ints;
+
+	/* Re-enable interrupts as appropriate. */
+	if (ints & HAL_INT_GLOBAL) {
+		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
+		OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+	}
+
+	return omask;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_keycache.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_keycache.c
new file mode 100644
index 0000000..61f579a
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_keycache.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_keycache.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+
+/*
+ *  Chips-specific key cache routines.
+ */
+
+#define	AR_KEYTABLE_SIZE	128
+#define	KEY_XOR			0xaa
+
+/*
+ * Return the size of the hardware key cache.
+ */
+uint32_t
+ar5211GetKeyCacheSize(struct ath_hal *ah)
+{
+	return AR_KEYTABLE_SIZE;
+}
+
+/*
+ * Return true if the specific key cache entry is valid.
+ */
+HAL_BOOL
+ar5211IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)
+{
+	if (entry < AR_KEYTABLE_SIZE) {
+		uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
+		if (val & AR_KEYTABLE_VALID)
+			return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Clear the specified key cache entry
+ */
+HAL_BOOL
+ar5211ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)
+{
+	if (entry < AR_KEYTABLE_SIZE) {
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Sets the mac part of the specified key cache entry and mark it valid.
+ */
+HAL_BOOL
+ar5211SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
+{
+	uint32_t macHi, macLo;
+
+	if (entry >= AR_KEYTABLE_SIZE) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
+		    __func__, entry);
+		return AH_FALSE;
+	}
+
+	/*
+	 * Set MAC address -- shifted right by 1.  MacLo is
+	 * the 4 MSBs, and MacHi is the 2 LSBs.
+	 */
+	if (mac != AH_NULL) {
+		macHi = (mac[5] << 8) | mac[4];
+		macLo = (mac[3] << 24)| (mac[2] << 16)
+		      | (mac[1] << 8) | mac[0];
+		macLo >>= 1;
+		macLo |= (macHi & 1) << 31;	/* carry */
+		macHi >>= 1;
+	} else {
+		macLo = macHi = 0;
+	}
+
+	OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
+	OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
+	return AH_TRUE;
+}
+
+/*
+ * Sets the contents of the specified key cache entry.
+ */
+HAL_BOOL
+ar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
+                       const HAL_KEYVAL *k, const uint8_t *mac,
+                       int xorKey)
+{
+	uint32_t key0, key1, key2, key3, key4;
+	uint32_t keyType;
+	uint32_t xorMask= xorKey ?
+		(KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0;
+
+	if (entry >= AR_KEYTABLE_SIZE) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
+		    __func__, entry);
+		return AH_FALSE;
+	}
+	switch (k->kv_type) {
+	case HAL_CIPHER_AES_OCB:
+		keyType = AR_KEYTABLE_TYPE_AES;
+		break;
+	case HAL_CIPHER_WEP:
+		if (k->kv_len < 40 / NBBY) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: WEP key length %u too small\n",
+			    __func__, k->kv_len);
+			return AH_FALSE;
+		}
+		if (k->kv_len <= 40 / NBBY)
+			keyType = AR_KEYTABLE_TYPE_40;
+		else if (k->kv_len <= 104 / NBBY)
+			keyType = AR_KEYTABLE_TYPE_104;
+		else
+			keyType = AR_KEYTABLE_TYPE_128;
+		break;
+	case HAL_CIPHER_CLR:
+		keyType = AR_KEYTABLE_TYPE_CLR;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",
+			__func__, k->kv_type);
+		return AH_FALSE;
+	}
+
+	key0 = LE_READ_4(k->kv_val+0) ^ xorMask;
+	key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff;
+	key2 = LE_READ_4(k->kv_val+6) ^ xorMask;
+	key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff;
+	key4 = LE_READ_4(k->kv_val+12) ^ xorMask;
+	if (k->kv_len <= 104 / NBBY)
+		key4 &= 0xff;
+
+
+	/*
+	 * Note: WEP key cache hardware requires that each double-word
+	 * pair be written in even/odd order (since the destination is
+	 * a 64-bit register).  Don't reorder these writes w/o
+	 * understanding this!
+	 */
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
+	OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
+	return ar5211SetKeyCacheEntryMac(ah, entry, mac);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_misc.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_misc.c
new file mode 100644
index 0000000..5197212
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_misc.c
@@ -0,0 +1,685 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_misc.c,v 1.7 2008/11/27 22:29:52 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+#include "ar5211/ar5211phy.h"
+
+#include "ah_eeprom_v3.h"
+
+#define	AR_NUM_GPIO	6		/* 6 GPIO bits */
+#define	AR_GPIOD_MASK	0x2f		/* 6-bit mask */
+
+void
+ar5211GetMacAddress(struct ath_hal *ah, uint8_t *mac)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
+}
+
+HAL_BOOL
+ar5211SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
+	return AH_TRUE;
+}
+
+void
+ar5211GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
+{
+	static const uint8_t ones[IEEE80211_ADDR_LEN] =
+		{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+	OS_MEMCPY(mask, ones, IEEE80211_ADDR_LEN);
+}
+
+HAL_BOOL
+ar5211SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
+{
+	return AH_FALSE;
+}
+
+/*
+ * Read 16 bits of data from the specified EEPROM offset.
+ */
+HAL_BOOL
+ar5211EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
+{
+	OS_REG_WRITE(ah, AR_EEPROM_ADDR, off);
+	OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ);
+
+	if (!ath_hal_wait(ah, AR_EEPROM_STS,
+	    AR_EEPROM_STS_READ_COMPLETE | AR_EEPROM_STS_READ_ERROR,
+	    AR_EEPROM_STS_READ_COMPLETE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: read failed for entry 0x%x\n", __func__, off);
+		return AH_FALSE;
+	}
+	*data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
+	return AH_TRUE;
+}
+
+#ifdef AH_SUPPORT_WRITE_EEPROM
+/*
+ * Write 16 bits of data to the specified EEPROM offset.
+ */
+HAL_BOOL
+ar5211EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)
+{
+	return AH_FALSE;
+}
+#endif /* AH_SUPPORT_WRITE_EEPROM */
+
+/*
+ * Attempt to change the cards operating regulatory domain to the given value
+ */
+HAL_BOOL
+ar5211SetRegulatoryDomain(struct ath_hal *ah,
+	uint16_t regDomain, HAL_STATUS *status)
+{
+	HAL_STATUS ecode;
+
+	if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
+		ecode = HAL_EINVAL;
+		goto bad;
+	}
+	/*
+	 * Check if EEPROM is configured to allow this; must
+	 * be a proper version and the protection bits must
+	 * permit re-writing that segment of the EEPROM.
+	 */
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
+		ecode = HAL_EEWRITE;
+		goto bad;
+	}
+#ifdef AH_SUPPORT_WRITE_REGDOMAIN
+	if (ar5211EepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: set regulatory domain to %u (0x%x)\n",
+		    __func__, regDomain, regDomain);
+		AH_PRIVATE(ah)->ah_currentRD = regDomain;
+		return AH_TRUE;
+	}
+#endif
+	ecode = HAL_EIO;
+bad:
+	if (status)
+		*status = ecode;
+	return AH_FALSE;
+}
+
+/*
+ * Return the wireless modes (a,b,g,t) supported by hardware.
+ *
+ * This value is what is actually supported by the hardware
+ * and is unaffected by regulatory/country code settings.
+ *
+ */
+u_int
+ar5211GetWirelessModes(struct ath_hal *ah)
+{
+	u_int mode = 0;
+
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
+		mode = HAL_MODE_11A;
+		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
+			mode |= HAL_MODE_TURBO | HAL_MODE_108A;
+	}
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
+		mode |= HAL_MODE_11B;
+	return mode;
+}
+
+#if 0
+HAL_BOOL
+ar5211GetTurboDisable(struct ath_hal *ah)
+{
+	return (AH5211(ah)->ah_turboDisable != 0);
+}
+#endif
+
+/*
+ * Called if RfKill is supported (according to EEPROM).  Set the interrupt and
+ * GPIO values so the ISR and can disable RF on a switch signal
+ */
+void
+ar5211EnableRfKill(struct ath_hal *ah)
+{
+	uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
+	int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
+	int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
+
+	/*
+	 * Configure the desired GPIO port for input
+	 * and enable baseband rf silence.
+	 */
+	ar5211GpioCfgInput(ah, select);
+	OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000);
+	/*
+	 * If radio disable switch connection to GPIO bit x is enabled
+	 * program GPIO interrupt.
+	 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
+	 * verified that it is a later version of eeprom, it has a place for
+	 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
+	 * connection is present.
+	 */
+	ar5211GpioSetIntr(ah, select, (ar5211GpioGet(ah, select) != polarity));
+}
+
+/*
+ * Configure GPIO Output lines
+ */
+HAL_BOOL
+ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+{
+	uint32_t reg;
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	reg =  OS_REG_READ(ah, AR_GPIOCR);
+	reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
+	reg |= AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT);
+
+	OS_REG_WRITE(ah, AR_GPIOCR, reg);
+	return AH_TRUE;
+}
+
+/*
+ * Configure GPIO Input lines
+ */
+HAL_BOOL
+ar5211GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
+{
+	uint32_t reg;
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	reg =  OS_REG_READ(ah, AR_GPIOCR);
+	reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
+	reg |= AR_GPIOCR_0_CR_N << (gpio * AR_GPIOCR_CR_SHIFT);
+
+	OS_REG_WRITE(ah, AR_GPIOCR, reg);
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - set output lines
+ */
+HAL_BOOL
+ar5211GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
+{
+	uint32_t reg;
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	reg =  OS_REG_READ(ah, AR_GPIODO);
+	reg &= ~(1 << gpio);
+	reg |= (val&1) << gpio;
+
+	OS_REG_WRITE(ah, AR_GPIODO, reg);
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - get input lines
+ */
+uint32_t
+ar5211GpioGet(struct ath_hal *ah, uint32_t gpio)
+{
+	if (gpio < AR_NUM_GPIO) {
+		uint32_t val = OS_REG_READ(ah, AR_GPIODI);
+		val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
+		return val;
+	} else  {
+		return 0xffffffff;
+	}
+}
+
+/*
+ * Set the GPIO 0 Interrupt (gpio is ignored)
+ */
+void
+ar5211GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
+{
+	uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
+
+	/* Clear the bits that we will modify. */
+	val &= ~(AR_GPIOCR_INT_SEL0 | AR_GPIOCR_INT_SELH | AR_GPIOCR_INT_ENA |
+			AR_GPIOCR_0_CR_A);
+
+	val |= AR_GPIOCR_INT_SEL0 | AR_GPIOCR_INT_ENA;
+	if (ilevel)
+		val |= AR_GPIOCR_INT_SELH;
+
+	/* Don't need to change anything for low level interrupt. */
+	OS_REG_WRITE(ah, AR_GPIOCR, val);
+
+	/* Change the interrupt mask. */
+	ar5211SetInterrupts(ah, AH5211(ah)->ah_maskReg | HAL_INT_GPIO);
+}
+
+/*
+ * Change the LED blinking pattern to correspond to the connectivity
+ */
+void
+ar5211SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
+{
+	static const uint32_t ledbits[8] = {
+		AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_INIT */
+		AR_PCICFG_LEDCTL_PEND|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_SCAN */
+		AR_PCICFG_LEDCTL_PEND|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_AUTH */
+		AR_PCICFG_LEDCTL_ASSOC|AR_PCICFG_LEDMODE_PROP,/* HAL_LED_ASSOC*/
+		AR_PCICFG_LEDCTL_ASSOC|AR_PCICFG_LEDMODE_PROP,/* HAL_LED_RUN */
+		AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
+		AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
+		AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
+	};
+	OS_REG_WRITE(ah, AR_PCICFG,
+		(OS_REG_READ(ah, AR_PCICFG) &~
+			(AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE))
+		| ledbits[state & 0x7]
+	);
+}
+
+/*
+ * Change association related fields programmed into the hardware.
+ * Writing a valid BSSID to the hardware effectively enables the hardware
+ * to synchronize its TSF to the correct beacons and receive frames coming
+ * from that BSSID. It is called by the SME JOIN operation.
+ */
+void
+ar5211WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	/* XXX save bssid for possible re-use on reset */
+	OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
+	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
+	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
+				     ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
+}
+
+/*
+ * Get the current hardware tsf for stamlme.
+ */
+uint64_t
+ar5211GetTsf64(struct ath_hal *ah)
+{
+	uint32_t low1, low2, u32;
+
+	/* sync multi-word read */
+	low1 = OS_REG_READ(ah, AR_TSF_L32);
+	u32 = OS_REG_READ(ah, AR_TSF_U32);
+	low2 = OS_REG_READ(ah, AR_TSF_L32);
+	if (low2 < low1) {	/* roll over */
+		/*
+		 * If we are not preempted this will work.  If we are
+		 * then we re-reading AR_TSF_U32 does no good as the
+		 * low bits will be meaningless.  Likewise reading
+		 * L32, U32, U32, then comparing the last two reads
+		 * to check for rollover doesn't help if preempted--so
+		 * we take this approach as it costs one less PCI
+		 * read which can be noticeable when doing things
+		 * like timestamping packets in monitor mode.
+		 */
+		u32++;
+	}
+	return (((uint64_t) u32) << 32) | ((uint64_t) low2);
+}
+
+/*
+ * Get the current hardware tsf for stamlme.
+ */
+uint32_t
+ar5211GetTsf32(struct ath_hal *ah)
+{
+	return OS_REG_READ(ah, AR_TSF_L32);
+}
+
+/*
+ * Reset the current hardware tsf for stamlme
+ */
+void
+ar5211ResetTsf(struct ath_hal *ah)
+{
+	uint32_t val = OS_REG_READ(ah, AR_BEACON);
+
+	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
+}
+
+/*
+ * Grab a semi-random value from hardware registers - may not
+ * change often
+ */
+uint32_t
+ar5211GetRandomSeed(struct ath_hal *ah)
+{
+	uint32_t nf;
+
+	nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
+	if (nf & 0x100)
+		nf = 0 - ((nf ^ 0x1ff) + 1);
+	return (OS_REG_READ(ah, AR_TSF_U32) ^
+		OS_REG_READ(ah, AR_TSF_L32) ^ nf);
+}
+
+/*
+ * Detect if our card is present
+ */
+HAL_BOOL
+ar5211DetectCardPresent(struct ath_hal *ah)
+{
+	uint16_t macVersion, macRev;
+	uint32_t v;
+
+	/*
+	 * Read the Silicon Revision register and compare that
+	 * to what we read at attach time.  If the same, we say
+	 * a card/device is present.
+	 */
+	v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M;
+	macVersion = v >> AR_SREV_ID_S;
+	macRev = v & AR_SREV_REVISION_M;
+	return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
+		AH_PRIVATE(ah)->ah_macRev == macRev);
+}
+
+/*
+ * Update MIB Counters
+ */
+void
+ar5211UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)
+{
+	stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
+	stats->rts_bad	  += OS_REG_READ(ah, AR_RTS_FAIL);
+	stats->fcs_bad	  += OS_REG_READ(ah, AR_FCS_FAIL);
+	stats->rts_good	  += OS_REG_READ(ah, AR_RTS_OK);
+	stats->beacons	  += OS_REG_READ(ah, AR_BEACON_CNT);
+}
+
+HAL_BOOL
+ar5211SetSifsTime(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	if (us > ath_hal_mac_usec(ah, 0xffff)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
+		    __func__, us);
+		ahp->ah_sifstime = (u_int) -1;	/* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us));
+		ahp->ah_slottime = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5211GetSifsTime(struct ath_hal *ah)
+{
+	u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+HAL_BOOL
+ar5211SetSlotTime(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
+		    __func__, us);
+		ahp->ah_slottime = us;	/* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
+		ahp->ah_slottime = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5211GetSlotTime(struct ath_hal *ah)
+{
+	u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+HAL_BOOL
+ar5211SetAckTimeout(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
+		    __func__, us);
+		ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
+			AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
+		ahp->ah_acktimeout = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5211GetAckTimeout(struct ath_hal *ah)
+{
+	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+u_int
+ar5211GetAckCTSRate(struct ath_hal *ah)
+{
+	return ((AH5211(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
+}
+
+HAL_BOOL
+ar5211SetAckCTSRate(struct ath_hal *ah, u_int high)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	if (high) {
+		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
+		ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
+	} else {
+		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
+		ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
+	}
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5211SetCTSTimeout(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
+		    __func__, us);
+		ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
+			AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
+		ahp->ah_ctstimeout = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5211GetCTSTimeout(struct ath_hal *ah)
+{
+	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+HAL_BOOL
+ar5211SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
+{
+	/* nothing to do */
+        return AH_TRUE;
+}
+
+void
+ar5211SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
+{
+}
+
+/*
+ * Control Adaptive Noise Immunity Parameters
+ */
+HAL_BOOL
+ar5211AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
+{
+	return AH_FALSE;
+}
+
+void
+ar5211AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats, HAL_CHANNEL *chan)
+{
+}
+
+void
+ar5211MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
+{
+}
+
+/*
+ * Get the rssi of frame curently being received.
+ */
+uint32_t
+ar5211GetCurRssi(struct ath_hal *ah)
+{
+	return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
+}
+
+u_int
+ar5211GetDefAntenna(struct ath_hal *ah)
+{   
+	return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
+}   
+
+void
+ar5211SetDefAntenna(struct ath_hal *ah, u_int antenna)
+{
+	OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
+}
+
+HAL_ANT_SETTING
+ar5211GetAntennaSwitch(struct ath_hal *ah)
+{
+	return AH5211(ah)->ah_diversityControl;
+}
+
+HAL_BOOL
+ar5211SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
+{
+	const HAL_CHANNEL *chan =
+		(const HAL_CHANNEL *) AH_PRIVATE(ah)->ah_curchan;
+
+	if (chan == AH_NULL) {
+		AH5211(ah)->ah_diversityControl = settings;
+		return AH_TRUE;
+	}
+	return ar5211SetAntennaSwitchInternal(ah, settings, chan);
+}
+
+HAL_STATUS
+ar5211GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+	uint32_t capability, uint32_t *result)
+{
+
+	switch (type) {
+	case HAL_CAP_CIPHER:		/* cipher handled in hardware */
+		switch (capability) {
+		case HAL_CIPHER_AES_OCB:
+		case HAL_CIPHER_WEP:
+		case HAL_CIPHER_CLR:
+			return HAL_OK;
+		default:
+			return HAL_ENOTSUPP;
+		}
+	default:
+		return ath_hal_getcapability(ah, type, capability, result);
+	}
+}
+
+HAL_BOOL
+ar5211SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+	uint32_t capability, uint32_t setting, HAL_STATUS *status)
+{
+	switch (type) {
+	case HAL_CAP_DIAG:		/* hardware diagnostic support */
+		/*
+		 * NB: could split this up into virtual capabilities,
+		 *     (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
+		 *     seems worth the additional complexity.
+		 */
+#ifdef AH_DEBUG
+		AH_PRIVATE(ah)->ah_diagreg = setting;
+#else
+		AH_PRIVATE(ah)->ah_diagreg = setting & 0x6;	/* ACK+CTS */
+#endif
+		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
+		return AH_TRUE;
+	default:
+		return ath_hal_setcapability(ah, type, capability,
+			setting, status);
+	}
+}
+
+HAL_BOOL
+ar5211GetDiagState(struct ath_hal *ah, int request,
+	const void *args, uint32_t argsize,
+	void **result, uint32_t *resultsize)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	(void) ahp;
+	if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
+		return AH_TRUE;
+	switch (request) {
+	case HAL_DIAG_EEPROM:
+		return ath_hal_eepromDiag(ah, request,
+		    args, argsize, result, resultsize);
+	case HAL_DIAG_RFGAIN:
+		*result = &ahp->ah_gainValues;
+		*resultsize = sizeof(GAIN_VALUES);
+		return AH_TRUE;
+	case HAL_DIAG_RFGAIN_CURSTEP:
+		*result = __DECONST(void *, ahp->ah_gainValues.currStep);
+		*resultsize = (*result == AH_NULL) ?
+			0 : sizeof(GAIN_OPTIMIZATION_STEP);
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_phy.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_phy.c
new file mode 100644
index 0000000..62a46b5
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_phy.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_phy.c,v 1.3 2008/11/10 01:19:37 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5211/ar5211.h"
+
+/* shorthands to compact tables for readability */
+#define	OFDM	IEEE80211_T_OFDM
+#define	CCK	IEEE80211_T_CCK
+#define	TURBO	IEEE80211_T_TURBO
+
+HAL_RATE_TABLE ar5211_11a_table = {
+	8,  /* number of rates */
+	{ 0 },
+	{
+/*                                                  short            ctrl  */
+/*                valid                 rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, OFDM,    6000,     0x0b,    0x00, (0x80|12),   0 },
+/*   9 Mb */ {  AH_TRUE, OFDM,    9000,     0x0f,    0x00,        18,   0 },
+/*  12 Mb */ {  AH_TRUE, OFDM,   12000,     0x0a,    0x00, (0x80|24),   2 },
+/*  18 Mb */ {  AH_TRUE, OFDM,   18000,     0x0e,    0x00,        36,   2 },
+/*  24 Mb */ {  AH_TRUE, OFDM,   24000,     0x09,    0x00, (0x80|48),   4 },
+/*  36 Mb */ {  AH_TRUE, OFDM,   36000,     0x0d,    0x00,        72,   4 },
+/*  48 Mb */ {  AH_TRUE, OFDM,   48000,     0x08,    0x00,        96,   4 },
+/*  54 Mb */ {  AH_TRUE, OFDM,   54000,     0x0c,    0x00,       108,   4 }
+	},
+};
+
+HAL_RATE_TABLE ar5211_turbo_table = {
+	8,  /* number of rates */
+	{ 0 },
+	{
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, TURBO,   6000,    0x0b,    0x00, (0x80|12),   0 },
+/*   9 Mb */ {  AH_TRUE, TURBO,   9000,    0x0f,    0x00,        18,   0 },
+/*  12 Mb */ {  AH_TRUE, TURBO,  12000,    0x0a,    0x00, (0x80|24),   2 },
+/*  18 Mb */ {  AH_TRUE, TURBO,  18000,    0x0e,    0x00,        36,   2 },
+/*  24 Mb */ {  AH_TRUE, TURBO,  24000,    0x09,    0x00, (0x80|48),   4 },
+/*  36 Mb */ {  AH_TRUE, TURBO,  36000,    0x0d,    0x00,        72,   4 },
+/*  48 Mb */ {  AH_TRUE, TURBO,  48000,    0x08,    0x00,        96,   4 },
+/*  54 Mb */ {  AH_TRUE, TURBO,  54000,    0x0c,    0x00,       108,   4 }
+	},
+};
+
+HAL_RATE_TABLE ar5211_11b_table = {
+	4,  /* number of rates */
+	{ 0 },
+	{
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   1 Mb */ {  AH_TRUE,  CCK,    1000,    0x0b,    0x00, (0x80| 2),   0 },
+/*   2 Mb */ {  AH_TRUE,  CCK,    2000,    0x0a,    0x04, (0x80| 4),   1 },
+/* 5.5 Mb */ {  AH_TRUE,  CCK,    5500,    0x09,    0x04, (0x80|11),   1 },
+/*  11 Mb */ {  AH_TRUE,  CCK,   11000,    0x08,    0x04, (0x80|22),   1 }
+	},
+};
+
+#undef	OFDM
+#undef	CCK
+#undef	TURBO
+
+
+const HAL_RATE_TABLE *
+ar5211GetRateTable(struct ath_hal *ah, u_int mode)
+{
+	HAL_RATE_TABLE *rt;
+	switch (mode) {
+	case HAL_MODE_11A:
+		rt = &ar5211_11a_table;
+		break;
+	case HAL_MODE_11B:
+		rt = &ar5211_11b_table;
+		break;
+	case HAL_MODE_TURBO:
+		rt =  &ar5211_turbo_table;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",
+		    __func__, mode);
+		return AH_NULL;
+	}
+	ath_hal_setupratetable(ah, rt);
+	return rt;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_power.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_power.c
new file mode 100644
index 0000000..bcfcf7c
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_power.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_power.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+#include "ar5211/ar5211desc.h"
+
+/*
+ * Notify Power Mgt is enabled in self-generated frames.
+ * If requested, force chip awake.
+ *
+ * Returns A_OK if chip is awake or successfully forced awake.
+ *
+ * WARNING WARNING WARNING
+ * There is a problem with the chip where sometimes it will not wake up.
+ */
+static HAL_BOOL
+ar5211SetPowerModeAwake(struct ath_hal *ah, int setChip)
+{
+#define	POWER_UP_TIME	2000
+	uint32_t val;
+	int i;
+
+	if (setChip) {
+		OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE);
+		OS_DELAY(10);	/* Give chip the chance to awake */
+
+		for (i = POWER_UP_TIME / 200; i != 0; i--) {
+			val = OS_REG_READ(ah, AR_PCICFG);
+			if ((val & AR_PCICFG_SPWR_DN) == 0)
+				break;
+			OS_DELAY(200);
+			OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE,
+				AR_SCR_SLE_WAKE);
+		}
+		if (i == 0) {
+#ifdef AH_DEBUG
+			ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",
+				__func__, POWER_UP_TIME/20);
+#endif
+			return AH_FALSE;
+		}
+	} 
+
+	OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	return AH_TRUE;
+#undef POWER_UP_TIME
+}
+
+/*
+ * Notify Power Mgt is disabled in self-generated frames.
+ * If requested, force chip to sleep.
+ */
+static void
+ar5211SetPowerModeSleep(struct ath_hal *ah, int setChip)
+{
+	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	if (setChip)
+		OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
+}
+
+/*
+ * Notify Power Management is enabled in self-generating
+ * fames.  If request, set power mode of chip to
+ * auto/normal.  Duration in units of 128us (1/8 TU).
+ */
+static void
+ar5211SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)
+{
+	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	if (setChip)
+		OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);
+}
+
+HAL_BOOL
+ar5211SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+#ifdef AH_DEBUG
+	static const char* modes[] = {
+		"AWAKE",
+		"FULL-SLEEP",
+		"NETWORK SLEEP",
+		"UNDEFINED"
+	};
+#endif
+	int status = AH_TRUE;
+
+	HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
+		modes[ahp->ah_powerMode], modes[mode],
+		setChip ? "set chip " : "");
+	switch (mode) {
+	case HAL_PM_AWAKE:
+		status = ar5211SetPowerModeAwake(ah, setChip);
+		break;
+	case HAL_PM_FULL_SLEEP:
+		ar5211SetPowerModeSleep(ah, setChip);
+		break;
+	case HAL_PM_NETWORK_SLEEP:
+		ar5211SetPowerModeNetworkSleep(ah, setChip);
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",
+		    __func__, mode);
+		return AH_FALSE;
+	}
+	ahp->ah_powerMode = mode;
+	return status; 
+}
+
+HAL_POWER_MODE
+ar5211GetPowerMode(struct ath_hal *ah)
+{
+	/* Just so happens the h/w maps directly to the abstracted value */
+	return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_recv.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_recv.c
new file mode 100644
index 0000000..c5b0e18
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_recv.c
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_recv.c,v 1.4 2008/11/10 04:08:02 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_desc.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+#include "ar5211/ar5211desc.h"
+
+/*
+ * Get the RXDP.
+ */
+uint32_t
+ar5211GetRxDP(struct ath_hal *ah)
+{
+	return OS_REG_READ(ah, AR_RXDP);
+}
+
+/*
+ * Set the RxDP.
+ */
+void
+ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp)
+{
+	OS_REG_WRITE(ah, AR_RXDP, rxdp);
+	HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
+}
+
+
+/*
+ * Set Receive Enable bits.
+ */
+void
+ar5211EnableReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
+}
+
+/*
+ * Stop Receive at the DMA engine
+ */
+HAL_BOOL
+ar5211StopDmaReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);	/* Set receive disable bit */
+	if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s failed to stop in 10ms\n"
+				   "AR_CR=0x%08X\nAR_DIAG_SW=0x%08X\n"
+				   , __func__
+				   , OS_REG_READ(ah, AR_CR)
+				   , OS_REG_READ(ah, AR_DIAG_SW)
+		);
+#endif
+		return AH_FALSE;
+	} else {
+		return AH_TRUE;
+	}
+}
+
+/*
+ * Start Transmit at the PCU engine (unpause receive)
+ */
+void
+ar5211StartPcuReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_DIAG_SW,
+		OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
+}
+
+/*
+ * Stop Transmit at the PCU engine (pause receive)
+ */
+void
+ar5211StopPcuReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_DIAG_SW,
+		OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
+}
+
+/*
+ * Set multicast filter 0 (lower 32-bits)
+ *			   filter 1 (upper 32-bits)
+ */
+void
+ar5211SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
+{
+	OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
+	OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
+}
+
+/*
+ * Clear multicast filter by index
+ */
+HAL_BOOL
+ar5211ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
+{
+	uint32_t val;
+
+	if (ix >= 64)
+		return AH_FALSE;
+	if (ix >= 32) {
+		val = OS_REG_READ(ah, AR_MCAST_FIL1);
+		OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
+	} else {
+		val = OS_REG_READ(ah, AR_MCAST_FIL0);
+		OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Set multicast filter by index
+ */
+HAL_BOOL
+ar5211SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
+{
+	uint32_t val;
+
+	if (ix >= 64)
+		return AH_FALSE;
+	if (ix >= 32) {
+		val = OS_REG_READ(ah, AR_MCAST_FIL1);
+		OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
+	} else {
+		val = OS_REG_READ(ah, AR_MCAST_FIL0);
+		OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Get receive filter.
+ */
+uint32_t
+ar5211GetRxFilter(struct ath_hal *ah)
+{
+	return OS_REG_READ(ah, AR_RX_FILTER);
+}
+
+/*
+ * Set receive filter.
+ */
+void
+ar5211SetRxFilter(struct ath_hal *ah, uint32_t bits)
+{
+	OS_REG_WRITE(ah, AR_RX_FILTER, bits);
+}
+
+/*
+ * Initialize RX descriptor, by clearing the status and clearing
+ * the size.  This is not strictly HW dependent, but we want the
+ * control and status words to be opaque above the hal.
+ */
+HAL_BOOL
+ar5211SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	uint32_t size, u_int flags)
+{
+	struct ar5211_desc *ads = AR5211DESC(ds);
+
+	ads->ds_ctl0 = 0;
+	ads->ds_ctl1 = size & AR_BufLen;
+	if (ads->ds_ctl1 != size) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
+		    __func__, size);
+		return AH_FALSE;
+	}
+	if (flags & HAL_RXDESC_INTREQ)
+		ads->ds_ctl1 |= AR_RxInterReq;
+	ads->ds_status0 = ads->ds_status1 = 0;
+
+	return AH_TRUE;
+}
+
+/*
+ * Process an RX descriptor, and return the status to the caller.
+ * Copy some hardware specific items into the software portion
+ * of the descriptor.
+ *
+ * NB: the caller is responsible for validating the memory contents
+ *     of the descriptor (e.g. flushing any cached copy).
+ */
+HAL_STATUS
+ar5211ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	uint32_t pa, struct ath_desc *nds, uint64_t tsf,
+	struct ath_rx_status *rs)
+{
+	struct ar5211_desc *ads = AR5211DESC(ds);
+	struct ar5211_desc *ands = AR5211DESC(nds);
+
+	if ((ads->ds_status1 & AR_Done) == 0)
+		return HAL_EINPROGRESS;
+	/*
+	 * Given the use of a self-linked tail be very sure that the hw is
+	 * done with this descriptor; the hw may have done this descriptor
+	 * once and picked it up again...make sure the hw has moved on.
+	 */
+	if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
+		return HAL_EINPROGRESS;
+
+	rs->rs_datalen = ads->ds_status0 & AR_DataLen;
+	rs->rs_tstamp = MS(ads->ds_status1, AR_RcvTimestamp);
+	rs->rs_status = 0;
+	if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
+		if (ads->ds_status1 & AR_CRCErr)
+			rs->rs_status |= HAL_RXERR_CRC;
+		else if (ads->ds_status1 & AR_DecryptCRCErr)
+			rs->rs_status |= HAL_RXERR_DECRYPT;
+		else {
+			rs->rs_status |= HAL_RXERR_PHY;
+			rs->rs_phyerr = MS(ads->ds_status1, AR_PHYErr);
+		}
+	}
+	/* XXX what about KeyCacheMiss? */
+	rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
+	if (ads->ds_status1 & AR_KeyIdxValid)
+		rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
+	else
+		rs->rs_keyix = HAL_RXKEYIX_INVALID;
+	/* NB: caller expected to do rate table mapping */
+	rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
+	rs->rs_antenna  = MS(ads->ds_status0, AR_RcvAntenna);
+	rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;
+
+	return HAL_OK;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_reset.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_reset.c
new file mode 100644
index 0000000..6646a4d
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_reset.c
@@ -0,0 +1,2138 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_reset.c,v 1.9 2008/11/27 22:29:52 sam Exp $
+ */
+#include "opt_ah.h"
+
+/*
+ * Chips specific device attachment and device info collection
+ * Connects Init Reg Vectors, EEPROM Data, and device Functions.
+ */
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+#include "ar5211/ar5211phy.h"
+
+#include "ah_eeprom_v3.h"
+
+/* Add static register initialization vectors */
+#include "ar5211/boss.ini"
+
+/*
+ * Structure to hold 11b tuning information for Beanie/Sombrero
+ * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12
+ */
+typedef struct {
+	uint32_t	refClkSel;	/* reference clock, 1 for 16 MHz */
+	uint32_t	channelSelect;	/* P[7:4]S[3:0] bits */
+	uint16_t	channel5111;	/* 11a channel for 5111 */
+} CHAN_INFO_2GHZ;
+
+#define CI_2GHZ_INDEX_CORRECTION 19
+const static CHAN_INFO_2GHZ chan2GHzData[] = {
+	{ 1, 0x46, 96  },	/* 2312 -19 */
+	{ 1, 0x46, 97  },	/* 2317 -18 */
+	{ 1, 0x46, 98  },	/* 2322 -17 */
+	{ 1, 0x46, 99  },	/* 2327 -16 */
+	{ 1, 0x46, 100 },	/* 2332 -15 */
+	{ 1, 0x46, 101 },	/* 2337 -14 */
+	{ 1, 0x46, 102 },	/* 2342 -13 */
+	{ 1, 0x46, 103 },	/* 2347 -12 */
+	{ 1, 0x46, 104 },	/* 2352 -11 */
+	{ 1, 0x46, 105 },	/* 2357 -10 */
+	{ 1, 0x46, 106 },	/* 2362  -9 */
+	{ 1, 0x46, 107 },	/* 2367  -8 */
+	{ 1, 0x46, 108 },	/* 2372  -7 */
+	/* index -6 to 0 are pad to make this a nolookup table */
+	{ 1, 0x46, 116 },	/*       -6 */
+	{ 1, 0x46, 116 },	/*       -5 */
+	{ 1, 0x46, 116 },	/*       -4 */
+	{ 1, 0x46, 116 },	/*       -3 */
+	{ 1, 0x46, 116 },	/*       -2 */
+	{ 1, 0x46, 116 },	/*       -1 */
+	{ 1, 0x46, 116 },	/*        0 */
+	{ 1, 0x46, 116 },	/* 2412   1 */
+	{ 1, 0x46, 117 },	/* 2417   2 */
+	{ 1, 0x46, 118 },	/* 2422   3 */
+	{ 1, 0x46, 119 },	/* 2427   4 */
+	{ 1, 0x46, 120 },	/* 2432   5 */
+	{ 1, 0x46, 121 },	/* 2437   6 */
+	{ 1, 0x46, 122 },	/* 2442   7 */
+	{ 1, 0x46, 123 },	/* 2447   8 */
+	{ 1, 0x46, 124 },	/* 2452   9 */
+	{ 1, 0x46, 125 },	/* 2457  10 */
+	{ 1, 0x46, 126 },	/* 2462  11 */
+	{ 1, 0x46, 127 },	/* 2467  12 */
+	{ 1, 0x46, 128 },	/* 2472  13 */
+	{ 1, 0x44, 124 },	/* 2484  14 */
+	{ 1, 0x46, 136 },	/* 2512  15 */
+	{ 1, 0x46, 140 },	/* 2532  16 */
+	{ 1, 0x46, 144 },	/* 2552  17 */
+	{ 1, 0x46, 148 },	/* 2572  18 */
+	{ 1, 0x46, 152 },	/* 2592  19 */
+	{ 1, 0x46, 156 },	/* 2612  20 */
+	{ 1, 0x46, 160 },	/* 2632  21 */
+	{ 1, 0x46, 164 },	/* 2652  22 */
+	{ 1, 0x46, 168 },	/* 2672  23 */
+	{ 1, 0x46, 172 },	/* 2692  24 */
+	{ 1, 0x46, 176 },	/* 2712  25 */
+	{ 1, 0x46, 180 } 	/* 2732  26 */
+};
+
+/* Power timeouts in usec to wait for chip to wake-up. */
+#define POWER_UP_TIME	2000
+
+#define	DELAY_PLL_SETTLE	300		/* 300 us */
+#define	DELAY_BASE_ACTIVATE	100		/* 100 us */
+
+#define NUM_RATES	8
+
+static HAL_BOOL ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask);
+static HAL_BOOL ar5211SetChannel(struct ath_hal *,  HAL_CHANNEL_INTERNAL *);
+static int16_t ar5211RunNoiseFloor(struct ath_hal *,
+		uint8_t runTime, int16_t startingNF);
+static HAL_BOOL ar5211IsNfGood(struct ath_hal *, HAL_CHANNEL_INTERNAL *chan);
+static HAL_BOOL ar5211SetRf6and7(struct ath_hal *, HAL_CHANNEL *chan);
+static HAL_BOOL ar5211SetBoardValues(struct ath_hal *, HAL_CHANNEL *chan);
+static void ar5211SetPowerTable(struct ath_hal *,
+		PCDACS_EEPROM *pSrcStruct, uint16_t channel);
+static void ar5211SetRateTable(struct ath_hal *,
+		RD_EDGES_POWER *pRdEdgesPower, TRGT_POWER_INFO *pPowerInfo,
+		uint16_t numChannels, HAL_CHANNEL *chan);
+static uint16_t ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue,
+		const PCDACS_EEPROM *pSrcStruct);
+static HAL_BOOL ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue,
+		const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue);
+static uint16_t ar5211GetInterpolatedValue(uint16_t target,
+		uint16_t srcLeft, uint16_t srcRight,
+		uint16_t targetLeft, uint16_t targetRight, HAL_BOOL scaleUp);
+static void ar5211GetLowerUpperValues(uint16_t value,
+		const uint16_t *pList, uint16_t listSize,
+		uint16_t *pLowerValue, uint16_t *pUpperValue);
+static void ar5211GetLowerUpperPcdacs(uint16_t pcdac,
+		uint16_t channel, const PCDACS_EEPROM *pSrcStruct,
+		uint16_t *pLowerPcdac, uint16_t *pUpperPcdac);
+
+static void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *);;
+static void ar5211RequestRfgain(struct ath_hal *);
+static HAL_BOOL ar5211InvalidGainReadback(struct ath_hal *, GAIN_VALUES *);
+static HAL_BOOL ar5211IsGainAdjustNeeded(struct ath_hal *, const GAIN_VALUES *);
+static int32_t ar5211AdjustGain(struct ath_hal *, GAIN_VALUES *);
+static void ar5211SetOperatingMode(struct ath_hal *, int opmode);
+
+/*
+ * Places the device in and out of reset and then places sane
+ * values in the registers based on EEPROM config, initialization
+ * vectors (as determined by the mode), and station configuration
+ *
+ * bChannelChange is used to preserve DMA/PCU registers across
+ * a HW Reset during channel change.
+ */
+HAL_BOOL
+ar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode,
+	HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+{
+uint32_t softLedCfg, softLedState;
+#define	N(a)	(sizeof (a) /sizeof (a[0]))
+#define	FAIL(_code)	do { ecode = _code; goto bad; } while (0)
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	HAL_CHANNEL_INTERNAL *ichan;
+	uint32_t i, ledstate;
+	HAL_STATUS ecode;
+	int q;
+
+	uint32_t		data, synthDelay;
+	uint32_t		macStaId1;    
+	uint16_t		modesIndex = 0, freqIndex = 0;
+	uint32_t		saveFrameSeqCount[AR_NUM_DCU];
+	uint32_t		saveTsfLow = 0, saveTsfHigh = 0;
+	uint32_t		saveDefAntenna;
+
+	HALDEBUG(ah, HAL_DEBUG_RESET,
+	     "%s: opmode %u channel %u/0x%x %s channel\n",
+	     __func__, opmode, chan->channel, chan->channelFlags,
+	     bChannelChange ? "change" : "same");
+
+	OS_MARK(ah, AH_MARK_RESET, bChannelChange);
+#define	IS(_c,_f)	(((_c)->channelFlags & _f) || 0)
+	if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan,CHANNEL_5GHZ)) == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+	if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+#undef IS
+	/*
+	 * Map public channel to private.
+	 */
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+	switch (opmode) {
+	case HAL_M_STA:
+	case HAL_M_IBSS:
+	case HAL_M_HOSTAP:
+	case HAL_M_MONITOR:
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid operating mode %u\n", __func__, opmode);
+		FAIL(HAL_EINVAL);
+		break;
+	}
+	HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3);
+
+	/* Preserve certain DMA hardware registers on a channel change */
+	if (bChannelChange) {
+		/*
+		 * Need to save/restore the TSF because of an issue
+		 * that accelerates the TSF during a chip reset.
+		 *
+		 * We could use system timer routines to more
+		 * accurately restore the TSF, but
+		 * 1. Timer routines on certain platforms are
+		 *	not accurate enough (e.g. 1 ms resolution).
+		 * 2. It would still not be accurate.
+		 *
+		 * The most important aspect of this workaround,
+		 * is that, after reset, the TSF is behind
+		 * other STAs TSFs.  This will allow the STA to
+		 * properly resynchronize its TSF in adhoc mode.
+		 */
+		saveTsfLow  = OS_REG_READ(ah, AR_TSF_L32);
+		saveTsfHigh = OS_REG_READ(ah, AR_TSF_U32);
+
+		/* Read frame sequence count */
+		if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
+			saveFrameSeqCount[0] = OS_REG_READ(ah, AR_D0_SEQNUM);
+		} else {
+			for (i = 0; i < AR_NUM_DCU; i++)
+				saveFrameSeqCount[i] = OS_REG_READ(ah, AR_DSEQNUM(i));
+		}
+		if (!(ichan->privFlags & CHANNEL_DFS)) 
+			ichan->privFlags &= ~CHANNEL_INTERFERENCE;
+		chan->channelFlags = ichan->channelFlags;
+		chan->privFlags = ichan->privFlags;
+	}
+
+	/*
+	 * Preserve the antenna on a channel change
+	 */
+	saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
+	if (saveDefAntenna == 0)
+		saveDefAntenna = 1;
+
+	/* Save hardware flag before chip reset clears the register */
+	macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
+
+	/* Save led state from pci config register */
+	ledstate = OS_REG_READ(ah, AR_PCICFG) &
+		(AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK |
+		 AR_PCICFG_LEDSLOW);
+	softLedCfg = OS_REG_READ(ah, AR_GPIOCR);
+	softLedState = OS_REG_READ(ah, AR_GPIODO);
+
+	if (!ar5211ChipReset(ah, chan->channelFlags)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Setup the indices for the next set of register array writes */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+		modesIndex = 1;
+		freqIndex  = 1;
+		break;
+	case CHANNEL_T:
+		modesIndex = 2;
+		freqIndex  = 1;
+		break;
+	case CHANNEL_B:
+		modesIndex = 3;
+		freqIndex  = 2;
+		break;
+	case CHANNEL_PUREG:
+		modesIndex = 4;
+		freqIndex  = 2;
+		break;
+	default:
+		/* Ah, a new wireless mode */
+		HALASSERT(0);
+		break;
+	}
+
+	/* Set correct Baseband to analog shift setting to access analog chips. */
+	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
+		OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);
+	} else {
+		OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);
+	}
+
+	/* Write parameters specific to AR5211 */
+	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
+		if (IS_CHAN_2GHZ(chan) &&
+		    AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) {
+			HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+			uint32_t ob2GHz, db2GHz;
+
+			if (IS_CHAN_CCK(chan)) {
+				ob2GHz = ee->ee_ob2GHz[0];
+				db2GHz = ee->ee_db2GHz[0];
+			} else {
+				ob2GHz = ee->ee_ob2GHz[1];
+				db2GHz = ee->ee_db2GHz[1];
+			}
+			ob2GHz = ath_hal_reverseBits(ob2GHz, 3);
+			db2GHz = ath_hal_reverseBits(db2GHz, 3);
+			ar5211Mode2_4[25][freqIndex] =
+				(ar5211Mode2_4[25][freqIndex] & ~0xC0) |
+					((ob2GHz << 6) & 0xC0);
+			ar5211Mode2_4[26][freqIndex] =
+				(ar5211Mode2_4[26][freqIndex] & ~0x0F) |
+					(((ob2GHz >> 2) & 0x1) |
+					 ((db2GHz << 1) & 0x0E));
+		}
+		for (i = 0; i < N(ar5211Mode2_4); i++)
+			OS_REG_WRITE(ah, ar5211Mode2_4[i][0],
+				ar5211Mode2_4[i][freqIndex]);
+	}
+
+	/* Write the analog registers 6 and 7 before other config */
+	ar5211SetRf6and7(ah, chan);
+
+	/* Write registers that vary across all modes */
+	for (i = 0; i < N(ar5211Modes); i++)
+		OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]);
+
+	/* Write RFGain Parameters that differ between 2.4 and 5 GHz */
+	for (i = 0; i < N(ar5211BB_RfGain); i++)
+		OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]);
+
+	/* Write Common Array Parameters */
+	for (i = 0; i < N(ar5211Common); i++) {
+		uint32_t reg = ar5211Common[i][0];
+		/* On channel change, don't reset the PCU registers */
+		if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))
+			OS_REG_WRITE(ah, reg, ar5211Common[i][1]);
+	}
+
+	/* Fix pre-AR5211 register values, this includes AR5311s. */
+	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
+		/*
+		 * The TX and RX latency values have changed locations
+		 * within the USEC register in AR5211.  Since they're
+		 * set via the .ini, for both AR5211 and AR5311, they
+		 * are written properly here for AR5311.
+		 */
+		data = OS_REG_READ(ah, AR_USEC);
+		/* Must be 0 for proper write in AR5311 */
+		HALASSERT((data & 0x00700000) == 0);
+		OS_REG_WRITE(ah, AR_USEC,
+			(data & (AR_USEC_M | AR_USEC_32_M | AR5311_USEC_TX_LAT_M)) |
+			((29 << AR5311_USEC_RX_LAT_S) & AR5311_USEC_RX_LAT_M));
+		/* The following registers exist only on AR5311. */
+		OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0);
+
+		/* Set proper ADC & DAC delays for AR5311. */
+		OS_REG_WRITE(ah, 0x00009878, 0x00000008);
+
+		/* Enable the PCU FIFO corruption ECO on AR5311. */
+		OS_REG_WRITE(ah, AR_DIAG_SW,
+			OS_REG_READ(ah, AR_DIAG_SW) | AR5311_DIAG_SW_USE_ECO);
+	}
+
+	/* Restore certain DMA hardware registers on a channel change */
+	if (bChannelChange) {
+		/* Restore TSF */
+		OS_REG_WRITE(ah, AR_TSF_L32, saveTsfLow);
+		OS_REG_WRITE(ah, AR_TSF_U32, saveTsfHigh);
+
+		if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) {
+			OS_REG_WRITE(ah, AR_D0_SEQNUM, saveFrameSeqCount[0]);
+		} else {
+			for (i = 0; i < AR_NUM_DCU; i++)
+				OS_REG_WRITE(ah, AR_DSEQNUM(i), saveFrameSeqCount[i]);
+		}
+	}
+
+	OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
+	OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
+		| macStaId1
+	);
+	ar5211SetOperatingMode(ah, opmode);
+
+	/* Restore previous led state */
+	OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
+	OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg);
+	OS_REG_WRITE(ah, AR_GPIODO, softLedState);
+
+	/* Restore previous antenna */
+	OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
+
+	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
+	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
+
+	/* Restore bmiss rssi & count thresholds */
+	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
+
+	OS_REG_WRITE(ah, AR_ISR, ~0);		/* cleared on write */
+
+	/*
+	 * for pre-Production Oahu only.
+	 * Disable clock gating in all DMA blocks. Helps when using
+	 * 11B and AES but results in higher power consumption.
+	 */
+	if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_OAHU &&
+	    AH_PRIVATE(ah)->ah_macRev < AR_SREV_OAHU_PROD) {
+		OS_REG_WRITE(ah, AR_CFG,
+			OS_REG_READ(ah, AR_CFG) | AR_CFG_CLK_GATE_DIS);
+	}
+
+	/* Setup the transmit power values. */
+	if (!ar5211SetTransmitPower(ah, chan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error init'ing transmit power\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/*
+	 * Configurable OFDM spoofing for 11n compatibility; used
+	 * only when operating in station mode.
+	 */
+	if (opmode != HAL_M_HOSTAP &&
+	    (AH_PRIVATE(ah)->ah_11nCompat & HAL_DIAG_11N_SERVICES) != 0) {
+		/* NB: override the .ini setting */
+		OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
+			AR_PHY_FRAME_CTL_ERR_SERV,
+			MS(AH_PRIVATE(ah)->ah_11nCompat, HAL_DIAG_11N_SERVICES)&1);
+	}
+
+	/* Setup board specific options for EEPROM version 3 */
+	ar5211SetBoardValues(ah, chan);
+
+	if (!ar5211SetChannel(ah, ichan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
+		    __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Activate the PHY */
+	if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B && IS_CHAN_2GHZ(chan))
+		OS_REG_WRITE(ah, 0xd808, 0x502); /* required for FPGA */
+	OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+
+	/*
+	 * Wait for the frequency synth to settle (synth goes on
+	 * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
+	 * Value is in 100ns increments.
+	 */
+	data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_M;
+	if (IS_CHAN_CCK(chan)) {
+		synthDelay = (4 * data) / 22;
+	} else {
+		synthDelay = data / 10;
+	}
+	/*
+	 * There is an issue if the AP starts the calibration before
+	 * the baseband timeout completes.  This could result in the
+	 * rxclear false triggering.  Add an extra delay to ensure this
+	 * this does not happen.
+	 */
+	OS_DELAY(synthDelay + DELAY_BASE_ACTIVATE);
+
+	/* Calibrate the AGC and wait for completion. */
+	OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
+		 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
+	(void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0);
+
+	/* Perform noise floor and set status */
+	if (!ar5211CalNoiseFloor(ah, ichan)) {
+		if (!IS_CHAN_CCK(chan))
+			chan->channelFlags |= CHANNEL_CW_INT;
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: noise floor calibration failed\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
+	if (ahp->ah_calibrationTime != 0) {
+		OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,
+			AR_PHY_TIMING_CTRL4_DO_IQCAL | (INIT_IQCAL_LOG_COUNT_MAX << AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S));
+		ahp->ah_bIQCalibration = AH_TRUE;
+	}
+
+	/* set 1:1 QCU to DCU mapping for all queues */
+	for (q = 0; q < AR_NUM_DCU; q++)
+		OS_REG_WRITE(ah, AR_DQCUMASK(q), 1<<q);
+
+	for (q = 0; q < HAL_NUM_TX_QUEUES; q++)
+		ar5211ResetTxQueue(ah, q);
+
+	/* Setup QCU0 transmit interrupt masks (TX_ERR, TX_OK, TX_DESC, TX_URN) */
+	OS_REG_WRITE(ah, AR_IMR_S0,
+		 (AR_IMR_S0_QCU_TXOK & AR_QCU_0) |
+		 (AR_IMR_S0_QCU_TXDESC & (AR_QCU_0<<AR_IMR_S0_QCU_TXDESC_S)));
+	OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0));
+	OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0));
+
+	/*
+	 * GBL_EIFS must always be written after writing
+	 *		to any QCUMASK register.
+	 */
+	OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, OS_REG_READ(ah, AR_D_GBL_IFS_EIFS));
+
+	/* Now set up the Interrupt Mask Register and save it for future use */
+	OS_REG_WRITE(ah, AR_IMR, INIT_INTERRUPT_MASK);
+	ahp->ah_maskReg = INIT_INTERRUPT_MASK;
+
+	/* Enable bus error interrupts */
+	OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) |
+		 AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR);
+
+	/* Enable interrupts specific to AP */
+	if (opmode == HAL_M_HOSTAP) {
+		OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_MIB);
+		ahp->ah_maskReg |= AR_IMR_MIB;
+	}
+
+	if (AH_PRIVATE(ah)->ah_rfkillEnabled)
+		ar5211EnableRfKill(ah);
+
+	/*
+	 * Writing to AR_BEACON will start timers. Hence it should
+	 * be the last register to be written. Do not reset tsf, do
+	 * not enable beacons at this point, but preserve other values
+	 * like beaconInterval.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON,
+		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
+
+	/* Restore user-specified slot time and timeouts */
+	if (ahp->ah_sifstime != (u_int) -1)
+		ar5211SetSifsTime(ah, ahp->ah_sifstime);
+	if (ahp->ah_slottime != (u_int) -1)
+		ar5211SetSlotTime(ah, ahp->ah_slottime);
+	if (ahp->ah_acktimeout != (u_int) -1)
+		ar5211SetAckTimeout(ah, ahp->ah_acktimeout);
+	if (ahp->ah_ctstimeout != (u_int) -1)
+		ar5211SetCTSTimeout(ah, ahp->ah_ctstimeout);
+	if (AH_PRIVATE(ah)->ah_diagreg != 0)
+		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
+
+	AH_PRIVATE(ah)->ah_opmode = opmode;	/* record operating mode */
+
+	HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
+
+	return AH_TRUE;
+bad:
+	if (*status)
+		*status = ecode;
+	return AH_FALSE;
+#undef FAIL
+#undef N
+}
+
+/*
+ * Places the PHY and Radio chips into reset.  A full reset
+ * must be called to leave this state.  The PCI/MAC/PCU are
+ * not placed into reset as we must receive interrupt to
+ * re-enable the hardware.
+ */
+HAL_BOOL
+ar5211PhyDisable(struct ath_hal *ah)
+{
+	return ar5211SetResetReg(ah, AR_RC_BB);
+}
+
+/*
+ * Places all of hardware into reset
+ */
+HAL_BOOL
+ar5211Disable(struct ath_hal *ah)
+{
+	if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+	/*
+	 * Reset the HW - PCI must be reset after the rest of the
+	 * device has been reset.
+	 */
+	if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
+		return AH_FALSE;
+	OS_DELAY(2100);	   /* 8245 @ 96Mhz hangs with 2000us. */
+
+	return AH_TRUE;
+}
+
+/*
+ * Places the hardware into reset and then pulls it out of reset
+ *
+ * Only write the PLL if we're changing to or from CCK mode
+ *
+ * Attach calls with channelFlags = 0, as the coldreset should have
+ * us in the correct mode and we cannot check the hwchannel flags.
+ */
+HAL_BOOL
+ar5211ChipReset(struct ath_hal *ah, uint16_t channelFlags)
+{
+	if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+
+	/* Set CCK and Turbo modes correctly */
+	switch (channelFlags & CHANNEL_ALL) {
+	case CHANNEL_2GHZ|CHANNEL_CCK:
+	case CHANNEL_2GHZ|CHANNEL_CCK|CHANNEL_TURBO:
+		OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
+		OS_REG_WRITE(ah, AR5211_PHY_MODE,
+			AR5211_PHY_MODE_CCK | AR5211_PHY_MODE_RF2GHZ);
+		OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
+		/* Wait for the PLL to settle */
+		OS_DELAY(DELAY_PLL_SETTLE);
+		break;
+	case CHANNEL_2GHZ|CHANNEL_OFDM:
+	case CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO:
+		OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
+		if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
+			OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
+			OS_DELAY(DELAY_PLL_SETTLE);
+			OS_REG_WRITE(ah, AR5211_PHY_MODE,
+				AR5211_PHY_MODE_OFDM | AR5211_PHY_MODE_RF2GHZ);
+		}
+		break;
+	case CHANNEL_A:
+	case CHANNEL_T:
+		if (channelFlags & CHANNEL_TURBO) {
+			OS_REG_WRITE(ah, AR_PHY_TURBO,
+				AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT);
+		} else {				/* 5 GHZ OFDM Mode */
+			OS_REG_WRITE(ah, AR_PHY_TURBO, 0);
+		}
+		if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) {
+			OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40);
+			OS_DELAY(DELAY_PLL_SETTLE);
+			OS_REG_WRITE(ah, AR5211_PHY_MODE,
+				AR5211_PHY_MODE_OFDM | AR5211_PHY_MODE_RF5GHZ);
+		}
+		break;
+	}
+	/* NB: else no flags set - must be attach calling - do nothing */
+
+	/*
+	 * Reset the HW - PCI must be reset after the rest of the
+	 * device has been reset
+	 */
+	if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
+		return AH_FALSE;
+	OS_DELAY(2100);	   /* 8245 @ 96Mhz hangs with 2000us. */
+
+	/* Bring out of sleep mode (AGAIN) */
+	if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+
+	/* Clear warm reset register */
+	return ar5211SetResetReg(ah, 0);
+}
+
+/*
+ * Recalibrate the lower PHY chips to account for temperature/environment
+ * changes.
+ */
+HAL_BOOL
+ar5211PerCalibrationN(struct ath_hal *ah,  HAL_CHANNEL *chan, u_int chainMask,
+	HAL_BOOL longCal, HAL_BOOL *isCalDone)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	HAL_CHANNEL_INTERNAL *ichan;
+	int32_t qCoff, qCoffDenom;
+	uint32_t data;
+	int32_t iqCorrMeas;
+	int32_t iCoff, iCoffDenom;
+	uint32_t powerMeasQ, powerMeasI;
+
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		return AH_FALSE;
+	}
+	/* IQ calibration in progress. Check to see if it has finished. */
+	if (ahp->ah_bIQCalibration &&
+	    !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
+		/* IQ Calibration has finished. */
+		ahp->ah_bIQCalibration = AH_FALSE;
+
+		/* Read calibration results. */
+		powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I);
+		powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q);
+		iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS);
+
+		/*
+		 * Prescale these values to remove 64-bit operation requirement at the loss
+		 * of a little precision.
+		 */
+		iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
+		qCoffDenom = powerMeasQ / 64;
+
+		/* Protect against divide-by-0. */
+		if (iCoffDenom != 0 && qCoffDenom != 0) {
+			iCoff = (-iqCorrMeas) / iCoffDenom;
+			/* IQCORR_Q_I_COFF is a signed 6 bit number */
+			iCoff = iCoff & 0x3f;
+
+			qCoff = ((int32_t)powerMeasI / qCoffDenom) - 64;
+			/* IQCORR_Q_Q_COFF is a signed 5 bit number */
+			qCoff = qCoff & 0x1f;
+
+			HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasI = 0x%08x\n",
+			    powerMeasI);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasQ = 0x%08x\n",
+			    powerMeasQ);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL, "iqCorrMeas = 0x%08x\n",
+			    iqCorrMeas);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL, "iCoff	  = %d\n",
+			    iCoff);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL, "qCoff	  = %d\n",
+			    qCoff);
+
+			/* Write IQ */
+			data  = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) |
+				AR_PHY_TIMING_CTRL4_IQCORR_ENABLE |
+				(((uint32_t)iCoff) << AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S) |
+				((uint32_t)qCoff);
+			OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data);
+		}
+	}
+	*isCalDone = !ahp->ah_bIQCalibration;
+
+	if (longCal) {
+		/* Perform noise floor and set status */
+		if (!ar5211IsNfGood(ah, ichan)) {
+			/* report up and clear internal state */
+			chan->channelFlags |= CHANNEL_CW_INT;
+			ichan->channelFlags &= ~CHANNEL_CW_INT;
+			return AH_FALSE;
+		}
+		if (!ar5211CalNoiseFloor(ah, ichan)) {
+			/*
+			 * Delay 5ms before retrying the noise floor
+			 * just to make sure, as we are in an error
+			 * condition here.
+			 */
+			OS_DELAY(5000);
+			if (!ar5211CalNoiseFloor(ah, ichan)) {
+				if (!IS_CHAN_CCK(chan))
+					chan->channelFlags |= CHANNEL_CW_INT;
+				return AH_FALSE;
+			}
+		}
+		ar5211RequestRfgain(ah);
+	}
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5211PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
+{
+	return ar5211PerCalibrationN(ah,  chan, 0x1, AH_TRUE, isIQdone);
+}
+
+HAL_BOOL
+ar5211ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	/* XXX */
+	return AH_TRUE;
+}
+
+/*
+ * Writes the given reset bit mask into the reset register
+ */
+static HAL_BOOL
+ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask)
+{
+	uint32_t mask = resetMask ? resetMask : ~0;
+	HAL_BOOL rt;
+
+	(void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */
+	OS_REG_WRITE(ah, AR_RC, resetMask);
+
+	/* need to wait at least 128 clocks when reseting PCI before read */
+	OS_DELAY(15);
+
+	resetMask &= AR_RC_MAC | AR_RC_BB;
+	mask &= AR_RC_MAC | AR_RC_BB;
+	rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
+        if ((resetMask & AR_RC_MAC) == 0) {
+		if (isBigEndian()) {
+			/*
+			 * Set CFG, little-endian for register
+			 * and descriptor accesses.
+			 */
+			mask = INIT_CONFIG_STATUS |
+				AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG;
+			OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
+		} else
+			OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
+	}
+	return rt;
+}
+
+/*
+ * Takes the MHz channel value and sets the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus before AGC is active
+ *   or by disabling the AGC.
+ */
+static HAL_BOOL
+ar5211SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t refClk, reg32, data2111;
+	int16_t chan5111, chanIEEE;
+
+	chanIEEE = ath_hal_mhz2ieee(ah, chan->channel, chan->channelFlags);
+	if (IS_CHAN_2GHZ(chan)) {
+		const CHAN_INFO_2GHZ* ci =
+			&chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION];
+
+		data2111 = ((ath_hal_reverseBits(ci->channelSelect, 8) & 0xff)
+				<< 5)
+			 | (ci->refClkSel << 4);
+		chan5111 = ci->channel5111;
+	} else {
+		data2111 = 0;
+		chan5111 = chanIEEE;
+	}
+
+	/* Rest of the code is common for 5 GHz and 2.4 GHz. */
+	if (chan5111 >= 145 || (chan5111 & 0x1)) {
+		reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xFF;
+		refClk = 1;
+	} else {
+		reg32 = ath_hal_reverseBits(((chan5111 - 24) / 2), 8) & 0xFF;
+		refClk = 0;
+	}
+
+	reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1;
+	OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));
+	reg32 >>= 8;
+	OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+}
+
+static int16_t
+ar5211GetNoiseFloor(struct ath_hal *ah)
+{
+	int16_t nf;
+
+	nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
+	if (nf & 0x100)
+		nf = 0 - ((nf ^ 0x1ff) + 1);
+	return nf;
+}
+
+/*
+ * Peform the noisefloor calibration for the length of time set
+ * in runTime (valid values 1 to 7)
+ *
+ * Returns: The NF value at the end of the given time (or 0 for failure)
+ */
+int16_t
+ar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF)
+{
+	int i, searchTime;
+
+	HALASSERT(runTime <= 7);
+
+	/* Setup  noise floor run time and starting value */
+	OS_REG_WRITE(ah, AR_PHY(25),
+		(OS_REG_READ(ah, AR_PHY(25)) & ~0xFFF) |
+			 ((runTime << 9) & 0xE00) | (startingNF & 0x1FF));
+	/* Calibrate the noise floor */
+	OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
+		OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
+
+	/* Compute the required amount of searchTime needed to finish NF */
+	if (runTime == 0) {
+		/* 8 search windows * 6.4us each */
+		searchTime = 8  * 7;
+	} else {
+		/* 512 * runtime search windows * 6.4us each */
+		searchTime = (runTime * 512)  * 7;
+	}
+
+	/*
+	 * Do not read noise floor until it has been updated
+	 *
+	 * As a guesstimate - we may only get 1/60th the time on
+	 * the air to see search windows  in a heavily congested
+	 * network (40 us every 2400 us of time)
+	 */
+	for (i = 0; i < 60; i++) {
+		if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0)
+			break;
+		OS_DELAY(searchTime);
+	}
+	if (i >= 60) {
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "NF with runTime %d failed to end on channel %d\n",
+		    runTime, AH_PRIVATE(ah)->ah_curchan->channel);
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "  PHY NF Reg state:	 0x%x\n",
+		    OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "  PHY Active Reg state: 0x%x\n",
+		    OS_REG_READ(ah, AR_PHY_ACTIVE));
+		return 0;
+	}
+
+	return ar5211GetNoiseFloor(ah);
+}
+
+static HAL_BOOL
+getNoiseFloorThresh(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, int16_t *nft)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
+	case CHANNEL_A:
+		*nft = ee->ee_noiseFloorThresh[0];
+		break;
+	case CHANNEL_CCK|CHANNEL_2GHZ:
+		*nft = ee->ee_noiseFloorThresh[1];
+		break;
+	case CHANNEL_OFDM|CHANNEL_2GHZ:
+		*nft = ee->ee_noiseFloorThresh[2];
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Read the NF and check it against the noise floor threshhold
+ *
+ * Returns: TRUE if the NF is good
+ */
+static HAL_BOOL
+ar5211IsNfGood(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+	int16_t nf, nfThresh;
+
+	if (!getNoiseFloorThresh(ah, chan, &nfThresh))
+		return AH_FALSE;
+	if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: NF did not complete in calibration window\n", __func__);
+	nf = ar5211GetNoiseFloor(ah);
+	if (nf > nfThresh) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: noise floor failed; detected %u, threshold %u\n",
+		    __func__, nf, nfThresh);
+		/*
+		 * NB: Don't discriminate 2.4 vs 5Ghz, if this
+		 *     happens it indicates a problem regardless
+		 *     of the band.
+		 */
+		chan->channelFlags |= CHANNEL_CW_INT;
+	}
+	chan->rawNoiseFloor = nf;
+	return (nf <= nfThresh);
+}
+
+/*
+ * Peform the noisefloor calibration and check for any constant channel
+ * interference.
+ *
+ * NOTE: preAR5211 have a lengthy carrier wave detection process - hence
+ * it is if'ed for MKK regulatory domain only.
+ *
+ * Returns: TRUE for a successful noise floor calibration; else FALSE
+ */
+HAL_BOOL
+ar5211CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+#define	N(a)	(sizeof (a) / sizeof (a[0]))
+	/* Check for Carrier Wave interference in MKK regulatory zone */
+	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU &&
+	    ath_hal_getnfcheckrequired(ah, (HAL_CHANNEL *) chan)) {
+		static const uint8_t runtime[3] = { 0, 2, 7 };
+		int16_t nf, nfThresh;
+		int i;
+
+		if (!getNoiseFloorThresh(ah, chan, &nfThresh))
+			return AH_FALSE;
+		/*
+		 * Run a quick noise floor that will hopefully
+		 * complete (decrease delay time).
+		 */
+		for (i = 0; i < N(runtime); i++) {
+			nf = ar5211RunNoiseFloor(ah, runtime[i], 0);
+			if (nf > nfThresh) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+				    "%s: run failed with %u > threshold %u "
+				    "(runtime %u)\n", __func__,
+				    nf, nfThresh, runtime[i]);
+				chan->rawNoiseFloor = 0;
+			} else
+				chan->rawNoiseFloor = nf;
+		}
+		return (i <= N(runtime));
+	} else {
+		/* Calibrate the noise floor */
+		OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
+			OS_REG_READ(ah, AR_PHY_AGC_CONTROL) |
+				 AR_PHY_AGC_CONTROL_NF);
+	}
+	return AH_TRUE;
+#undef N
+}
+
+/*
+ * Adjust NF based on statistical values for 5GHz frequencies.
+ */
+int16_t
+ar5211GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
+{
+	static const struct {
+		uint16_t freqLow;
+		int16_t	  adjust;
+	} adjust5111[] = {
+		{ 5790,	11 },	/* NB: ordered high -> low */
+		{ 5730, 10 },
+		{ 5690,  9 },
+		{ 5660,  8 },
+		{ 5610,  7 },
+		{ 5530,  5 },
+		{ 5450,  4 },
+		{ 5379,  2 },
+		{ 5209,  0 },	/* XXX? bogus but doesn't matter */
+		{    0,  1 },
+	};
+	int i;
+
+	for (i = 0; c->channel <= adjust5111[i].freqLow; i++)
+		;
+	/* NB: placeholder for 5111's less severe requirement */
+	return adjust5111[i].adjust / 3;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * analog registers 6 and 7
+ *
+ * REQUIRES: Access to the analog device
+ */
+static HAL_BOOL
+ar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+#define	N(a)	(sizeof (a) / sizeof (a[0]))
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	uint16_t rfXpdGain, rfPloSel, rfPwdXpd;
+	uint16_t tempOB, tempDB;
+	uint16_t freqIndex;
+	int i;
+
+	freqIndex = (chan->channelFlags & CHANNEL_2GHZ) ? 2 : 1;
+
+	/*
+	 * TODO: This array mode correspondes with the index used
+	 *	 during the read.
+	 * For readability, this should be changed to an enum or #define
+	 */
+	switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
+	case CHANNEL_A:
+		if (chan->channel > 4000 && chan->channel < 5260) {
+			tempOB = ee->ee_ob1;
+			tempDB = ee->ee_db1;
+		} else if (chan->channel >= 5260 && chan->channel < 5500) {
+			tempOB = ee->ee_ob2;
+			tempDB = ee->ee_db2;
+		} else if (chan->channel >= 5500 && chan->channel < 5725) {
+			tempOB = ee->ee_ob3;
+			tempDB = ee->ee_db3;
+		} else if (chan->channel >= 5725) {
+			tempOB = ee->ee_ob4;
+			tempDB = ee->ee_db4;
+		} else {
+			/* XXX panic?? */
+			tempOB = tempDB = 0;
+		}
+
+		rfXpdGain = ee->ee_xgain[0];
+		rfPloSel  = ee->ee_xpd[0];
+		rfPwdXpd  = !ee->ee_xpd[0];
+
+		ar5211Rf6n7[5][freqIndex]  =
+			(ar5211Rf6n7[5][freqIndex] & ~0x10000000) |
+				(ee->ee_cornerCal.pd84<< 28);
+		ar5211Rf6n7[6][freqIndex]  =
+			(ar5211Rf6n7[6][freqIndex] & ~0x04000000) |
+				(ee->ee_cornerCal.pd90 << 26);
+		ar5211Rf6n7[21][freqIndex] =
+			(ar5211Rf6n7[21][freqIndex] & ~0x08) |
+				(ee->ee_cornerCal.gSel << 3);
+		break;
+	case CHANNEL_CCK|CHANNEL_2GHZ:
+		tempOB = ee->ee_obFor24;
+		tempDB = ee->ee_dbFor24;
+		rfXpdGain = ee->ee_xgain[1];
+		rfPloSel  = ee->ee_xpd[1];
+		rfPwdXpd  = !ee->ee_xpd[1];
+		break;
+	case CHANNEL_OFDM|CHANNEL_2GHZ:
+		tempOB = ee->ee_obFor24g;
+		tempDB = ee->ee_dbFor24g;
+		rfXpdGain = ee->ee_xgain[2];
+		rfPloSel  = ee->ee_xpd[2];
+		rfPwdXpd  = !ee->ee_xpd[2];
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	HALASSERT(1 <= tempOB && tempOB <= 5);
+	HALASSERT(1 <= tempDB && tempDB <= 5);
+
+	/* Set rfXpdGain and rfPwdXpd */
+	ar5211Rf6n7[11][freqIndex] =  (ar5211Rf6n7[11][freqIndex] & ~0xC0) |
+		(((ath_hal_reverseBits(rfXpdGain, 4) << 7) | (rfPwdXpd << 6)) & 0xC0);
+	ar5211Rf6n7[12][freqIndex] =  (ar5211Rf6n7[12][freqIndex] & ~0x07) |
+		((ath_hal_reverseBits(rfXpdGain, 4) >> 1) & 0x07);
+
+	/* Set OB */
+	ar5211Rf6n7[12][freqIndex] =  (ar5211Rf6n7[12][freqIndex] & ~0x80) |
+		((ath_hal_reverseBits(tempOB, 3) << 7) & 0x80);
+	ar5211Rf6n7[13][freqIndex] =  (ar5211Rf6n7[13][freqIndex] & ~0x03) |
+		((ath_hal_reverseBits(tempOB, 3) >> 1) & 0x03);
+
+	/* Set DB */
+	ar5211Rf6n7[13][freqIndex] =  (ar5211Rf6n7[13][freqIndex] & ~0x1C) |
+		((ath_hal_reverseBits(tempDB, 3) << 2) & 0x1C);
+
+	/* Set rfPloSel */
+	ar5211Rf6n7[17][freqIndex] =  (ar5211Rf6n7[17][freqIndex] & ~0x08) |
+		((rfPloSel << 3) & 0x08);
+
+	/* Write the Rf registers 6 & 7 */
+	for (i = 0; i < N(ar5211Rf6n7); i++)
+		OS_REG_WRITE(ah, ar5211Rf6n7[i][0], ar5211Rf6n7[i][freqIndex]);
+
+	/* Now that we have reprogrammed rfgain value, clear the flag. */
+	ahp->ah_rfgainState = RFGAIN_INACTIVE;
+
+	return AH_TRUE;
+#undef N
+}
+
+HAL_BOOL
+ar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
+                       const HAL_CHANNEL *chan)
+{
+#define	ANT_SWITCH_TABLE1	0x9960
+#define	ANT_SWITCH_TABLE2	0x9964
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	uint32_t antSwitchA, antSwitchB;
+	int ix;
+
+	switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
+	case CHANNEL_A:		ix = 0; break;
+	case CHANNEL_B:		ix = 1; break;
+	case CHANNEL_PUREG:	ix = 2; break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	antSwitchA =  ee->ee_antennaControl[1][ix]
+		   | (ee->ee_antennaControl[2][ix] << 6)
+		   | (ee->ee_antennaControl[3][ix] << 12) 
+		   | (ee->ee_antennaControl[4][ix] << 18)
+		   | (ee->ee_antennaControl[5][ix] << 24)
+		   ;
+	antSwitchB =  ee->ee_antennaControl[6][ix]
+		   | (ee->ee_antennaControl[7][ix] << 6)
+		   | (ee->ee_antennaControl[8][ix] << 12)
+		   | (ee->ee_antennaControl[9][ix] << 18)
+		   | (ee->ee_antennaControl[10][ix] << 24)
+		   ;
+	/*
+	 * For fixed antenna, give the same setting for both switch banks
+	 */
+	switch (settings) {
+	case HAL_ANT_FIXED_A:
+		antSwitchB = antSwitchA;
+		break;
+	case HAL_ANT_FIXED_B:
+		antSwitchA = antSwitchB;
+		break;
+	case HAL_ANT_VARIABLE:
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n",
+		    __func__, settings);
+		return AH_FALSE;
+	}
+	ahp->ah_diversityControl = settings;
+
+	OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA);
+	OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB);
+
+	return AH_TRUE;
+#undef ANT_SWITCH_TABLE1
+#undef ANT_SWITCH_TABLE2
+}
+
+/*
+ * Reads EEPROM header info and programs the device for correct operation
+ * given the channel value
+ */
+static HAL_BOOL
+ar5211SetBoardValues(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	int arrayMode, falseDectectBackoff;
+
+	switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
+	case CHANNEL_A:
+		arrayMode = 0;
+		OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
+			AR_PHY_FRAME_CTL_TX_CLIP, ee->ee_cornerCal.clip);
+		break;
+	case CHANNEL_CCK|CHANNEL_2GHZ:
+		arrayMode = 1;
+		break;
+	case CHANNEL_OFDM|CHANNEL_2GHZ:
+		arrayMode = 2;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/* Set the antenna register(s) correctly for the chip revision */
+	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
+		OS_REG_WRITE(ah, AR_PHY(68),
+			(OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 0x3);
+	} else {
+		OS_REG_WRITE(ah, AR_PHY(68),
+			(OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFC06) |
+			(ee->ee_antennaControl[0][arrayMode] << 4) | 0x1);
+
+		ar5211SetAntennaSwitchInternal(ah,
+			ahp->ah_diversityControl, chan);
+
+		/* Set the Noise Floor Thresh on ar5211 devices */
+		OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2),
+			(ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) | (1<<9));
+	}
+	OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2),
+		(OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) |
+		((ee->ee_switchSettling[arrayMode] << 7) & 0x3F80));
+	OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2),
+		(OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) |
+		((ee->ee_txrxAtten[arrayMode] << 12) & 0x3F000));
+	OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2),
+		(OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) |
+		((ee->ee_pgaDesiredSize[arrayMode] << 8) & 0xFF00) |
+		(ee->ee_adcDesiredSize[arrayMode] & 0x00FF));
+	OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2),
+		(ee->ee_txEndToXPAOff[arrayMode] << 24) |
+		(ee->ee_txEndToXPAOff[arrayMode] << 16) |
+		(ee->ee_txFrameToXPAOn[arrayMode] << 8) |
+		ee->ee_txFrameToXPAOn[arrayMode]);
+	OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2),
+		(OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) |
+		(ee->ee_txEndToXLNAOn[arrayMode] << 8));
+	OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2),
+		(OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) |
+		((ee->ee_thresh62[arrayMode] << 12) & 0x7F000));
+
+#define NO_FALSE_DETECT_BACKOFF   2
+#define CB22_FALSE_DETECT_BACKOFF 6
+	/*
+	 * False detect backoff - suspected 32 MHz spur causes
+	 * false detects in OFDM, causing Tx Hangs.  Decrease
+	 * weak signal sensitivity for this card.
+	 */
+	falseDectectBackoff = NO_FALSE_DETECT_BACKOFF;
+	if (AH_PRIVATE(ah)->ah_eeversion < AR_EEPROM_VER3_3) {
+		if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&
+		    IS_CHAN_OFDM(chan))
+			falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF;
+	} else {
+		uint32_t remainder = chan->channel % 32;
+
+		if (remainder && (remainder < 10 || remainder > 22))
+			falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode];
+	}
+	OS_REG_WRITE(ah, 0x9924,
+		(OS_REG_READ(ah, 0x9924) & 0xFFFFFF01)
+		| ((falseDectectBackoff << 1) & 0xF7));
+
+	return AH_TRUE;
+#undef NO_FALSE_DETECT_BACKOFF
+#undef CB22_FALSE_DETECT_BACKOFF
+}
+
+/*
+ * Set the limit on the overall output power.  Used for dynamic
+ * transmit power control and the like.
+ *
+ * NOTE: The power is passed in is in units of 0.5 dBm.
+ */
+HAL_BOOL
+ar5211SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
+{
+
+	AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
+	OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, limit);
+	return AH_TRUE;
+}
+
+/*
+ * Sets the transmit power in the baseband for the given
+ * operating channel and mode.
+ */
+HAL_BOOL
+ar5211SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	TRGT_POWER_INFO *pi;
+	RD_EDGES_POWER *rep;
+	PCDACS_EEPROM eepromPcdacs;
+	u_int nchan, cfgCtl;
+	int i;
+
+	/* setup the pcdac struct to point to the correct info, based on mode */
+	switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
+	case CHANNEL_A:
+		eepromPcdacs.numChannels = ee->ee_numChannels11a;
+		eepromPcdacs.pChannelList= ee->ee_channels11a;
+		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;
+		nchan = ee->ee_numTargetPwr_11a;
+		pi = ee->ee_trgtPwr_11a;
+		break;
+	case CHANNEL_OFDM|CHANNEL_2GHZ:
+		eepromPcdacs.numChannels = ee->ee_numChannels2_4;
+		eepromPcdacs.pChannelList= ee->ee_channels11g;
+		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;
+		nchan = ee->ee_numTargetPwr_11g;
+		pi = ee->ee_trgtPwr_11g;
+		break;
+	case CHANNEL_CCK|CHANNEL_2GHZ:
+		eepromPcdacs.numChannels = ee->ee_numChannels2_4;
+		eepromPcdacs.pChannelList= ee->ee_channels11b;
+		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;
+		nchan = ee->ee_numTargetPwr_11b;
+		pi = ee->ee_trgtPwr_11b;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	ar5211SetPowerTable(ah, &eepromPcdacs, chan->channel);
+
+	rep = AH_NULL;
+	/* Match CTL to EEPROM value */
+	cfgCtl = ath_hal_getctl(ah, chan);
+	for (i = 0; i < ee->ee_numCtls; i++)
+		if (ee->ee_ctl[i] != 0 && ee->ee_ctl[i] == cfgCtl) {
+			rep = &ee->ee_rdEdgesPower[i * NUM_EDGES];
+			break;
+		}
+	ar5211SetRateTable(ah, rep, pi, nchan, chan);
+
+	return AH_TRUE;
+}
+
+/*
+ * Read the transmit power levels from the structures taken
+ * from EEPROM. Interpolate read transmit power values for
+ * this channel. Organize the transmit power values into a
+ * table for writing into the hardware.
+ */
+void
+ar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct, uint16_t channel)
+{
+	static FULL_PCDAC_STRUCT pcdacStruct;
+	static uint16_t pcdacTable[PWR_TABLE_SIZE];
+
+	uint16_t	 i, j;
+	uint16_t	 *pPcdacValues;
+	int16_t	  *pScaledUpDbm;
+	int16_t	  minScaledPwr;
+	int16_t	  maxScaledPwr;
+	int16_t	  pwr;
+	uint16_t	 pcdacMin = 0;
+	uint16_t	 pcdacMax = 63;
+	uint16_t	 pcdacTableIndex;
+	uint16_t	 scaledPcdac;
+	uint32_t	 addr;
+	uint32_t	 temp32;
+
+	OS_MEMZERO(&pcdacStruct, sizeof(FULL_PCDAC_STRUCT));
+	OS_MEMZERO(pcdacTable, sizeof(uint16_t) * PWR_TABLE_SIZE);
+	pPcdacValues = pcdacStruct.PcdacValues;
+	pScaledUpDbm = pcdacStruct.PwrValues;
+
+	/* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */
+	for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++)
+		pPcdacValues[j] = i;
+
+	pcdacStruct.numPcdacValues = j;
+	pcdacStruct.pcdacMin = PCDAC_START;
+	pcdacStruct.pcdacMax = PCDAC_STOP;
+
+	/* Fill out the power values for this channel */
+	for (j = 0; j < pcdacStruct.numPcdacValues; j++ )
+		pScaledUpDbm[j] = ar5211GetScaledPower(channel, pPcdacValues[j], pSrcStruct);
+
+	/* Now scale the pcdac values to fit in the 64 entry power table */
+	minScaledPwr = pScaledUpDbm[0];
+	maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1];
+
+	/* find minimum and make monotonic */
+	for (j = 0; j < pcdacStruct.numPcdacValues; j++) {
+		if (minScaledPwr >= pScaledUpDbm[j]) {
+			minScaledPwr = pScaledUpDbm[j];
+			pcdacMin = j;
+		}
+		/*
+		 * Make the full_hsh monotonically increasing otherwise
+		 * interpolation algorithm will get fooled gotta start
+		 * working from the top, hence i = 63 - j.
+		 */
+		i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j);
+		if (i == 0)
+			break;
+		if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) {
+			/*
+			 * It could be a glitch, so make the power for
+			 * this pcdac the same as the power from the
+			 * next highest pcdac.
+			 */
+			pScaledUpDbm[i - 1] = pScaledUpDbm[i];
+		}
+	}
+
+	for (j = 0; j < pcdacStruct.numPcdacValues; j++)
+		if (maxScaledPwr < pScaledUpDbm[j]) {
+			maxScaledPwr = pScaledUpDbm[j];
+			pcdacMax = j;
+		}
+
+	/* Find the first power level with a pcdac */
+	pwr = (uint16_t)(PWR_STEP * ((minScaledPwr - PWR_MIN + PWR_STEP / 2) / PWR_STEP)  + PWR_MIN);
+
+	/* Write all the first pcdac entries based off the pcdacMin */
+	pcdacTableIndex = 0;
+	for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++)
+		pcdacTable[pcdacTableIndex++] = pcdacMin;
+
+	i = 0;
+	while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1]) {
+		pwr += PWR_STEP;
+		/* stop if dbM > max_power_possible */
+		while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
+		       (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0)
+			i++;
+		/* scale by 2 and add 1 to enable round up or down as needed */
+		scaledPcdac = (uint16_t)(ar5211GetInterpolatedValue(pwr,
+				pScaledUpDbm[i], pScaledUpDbm[i+1],
+				(uint16_t)(pPcdacValues[i] * 2),
+				(uint16_t)(pPcdacValues[i+1] * 2), 0) + 1);
+
+		pcdacTable[pcdacTableIndex] = scaledPcdac / 2;
+		if (pcdacTable[pcdacTableIndex] > pcdacMax)
+			pcdacTable[pcdacTableIndex] = pcdacMax;
+		pcdacTableIndex++;
+	}
+
+	/* Write all the last pcdac entries based off the last valid pcdac */
+	while (pcdacTableIndex < PWR_TABLE_SIZE) {
+		pcdacTable[pcdacTableIndex] = pcdacTable[pcdacTableIndex - 1];
+		pcdacTableIndex++;
+	}
+
+	/* Finally, write the power values into the baseband power table */
+	addr = AR_PHY_BASE + (608 << 2);
+	for (i = 0; i < 32; i++) {
+		temp32 = 0xffff & ((pcdacTable[2 * i + 1] << 8) | 0xff);
+		temp32 = (temp32 << 16) | (0xffff & ((pcdacTable[2 * i] << 8) | 0xff));
+		OS_REG_WRITE(ah, addr, temp32);
+		addr += 4;
+	}
+
+}
+
+/*
+ * Set the transmit power in the baseband for the given
+ * operating channel and mode.
+ */
+void
+ar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower,
+	TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels,
+	HAL_CHANNEL *chan)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	static uint16_t ratesArray[NUM_RATES];
+	static const uint16_t tpcScaleReductionTable[5] =
+		{ 0, 3, 6, 9, MAX_RATE_POWER };
+
+	uint16_t	*pRatesPower;
+	uint16_t	lowerChannel, lowerIndex=0, lowerPower=0;
+	uint16_t	upperChannel, upperIndex=0, upperPower=0;
+	uint16_t	twiceMaxEdgePower=63;
+	uint16_t	twicePower = 0;
+	uint16_t	i, numEdges;
+	uint16_t	tempChannelList[NUM_EDGES]; /* temp array for holding edge channels */
+	uint16_t	twiceMaxRDPower;
+	int16_t	 scaledPower = 0;		/* for gcc -O2 */
+	uint16_t	mask = 0x3f;
+	HAL_BOOL	  paPreDEnable = 0;
+	int8_t	  twiceAntennaGain, twiceAntennaReduction = 0;
+
+	pRatesPower = ratesArray;
+	twiceMaxRDPower = chan->maxRegTxPower * 2;
+
+	if (IS_CHAN_5GHZ(chan)) {
+		twiceAntennaGain = ee->ee_antennaGainMax[0];
+	} else {
+		twiceAntennaGain = ee->ee_antennaGainMax[1];
+	}
+
+	twiceAntennaReduction = ath_hal_getantennareduction(ah, chan, twiceAntennaGain);
+
+	if (pRdEdgesPower) {
+		/* Get the edge power */
+		for (i = 0; i < NUM_EDGES; i++) {
+			if (pRdEdgesPower[i].rdEdge == 0)
+				break;
+			tempChannelList[i] = pRdEdgesPower[i].rdEdge;
+		}
+		numEdges = i;
+
+		ar5211GetLowerUpperValues(chan->channel, tempChannelList,
+			numEdges, &lowerChannel, &upperChannel);
+		/* Get the index for this channel */
+		for (i = 0; i < numEdges; i++)
+			if (lowerChannel == tempChannelList[i])
+				break;
+		HALASSERT(i != numEdges);
+
+		if ((lowerChannel == upperChannel &&
+		     lowerChannel == chan->channel) ||
+		    pRdEdgesPower[i].flag) {
+			twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower;
+			HALASSERT(twiceMaxEdgePower > 0);
+		}
+	}
+
+	/* extrapolate the power values for the test Groups */
+	for (i = 0; i < numChannels; i++)
+		tempChannelList[i] = pPowerInfo[i].testChannel;
+
+	ar5211GetLowerUpperValues(chan->channel, tempChannelList,
+		numChannels, &lowerChannel, &upperChannel);
+
+	/* get the index for the channel */
+	for (i = 0; i < numChannels; i++) {
+		if (lowerChannel == tempChannelList[i])
+			lowerIndex = i;
+		if (upperChannel == tempChannelList[i]) {
+			upperIndex = i;
+			break;
+		}
+	}
+
+	for (i = 0; i < NUM_RATES; i++) {
+		if (IS_CHAN_OFDM(chan)) {
+			/* power for rates 6,9,12,18,24 is all the same */
+			if (i < 5) {
+				lowerPower = pPowerInfo[lowerIndex].twicePwr6_24;
+				upperPower = pPowerInfo[upperIndex].twicePwr6_24;
+			} else if (i == 5) {
+				lowerPower = pPowerInfo[lowerIndex].twicePwr36;
+				upperPower = pPowerInfo[upperIndex].twicePwr36;
+			} else if (i == 6) {
+				lowerPower = pPowerInfo[lowerIndex].twicePwr48;
+				upperPower = pPowerInfo[upperIndex].twicePwr48;
+			} else if (i == 7) {
+				lowerPower = pPowerInfo[lowerIndex].twicePwr54;
+				upperPower = pPowerInfo[upperIndex].twicePwr54;
+			}
+		} else {
+			switch (i) {
+			case 0:
+			case 1:
+				lowerPower = pPowerInfo[lowerIndex].twicePwr6_24;
+				upperPower = pPowerInfo[upperIndex].twicePwr6_24;
+				break;
+			case 2:
+			case 3:
+				lowerPower = pPowerInfo[lowerIndex].twicePwr36;
+				upperPower = pPowerInfo[upperIndex].twicePwr36;
+				break;
+			case 4:
+			case 5:
+				lowerPower = pPowerInfo[lowerIndex].twicePwr48;
+				upperPower = pPowerInfo[upperIndex].twicePwr48;
+				break;
+			case 6:
+			case 7:
+				lowerPower = pPowerInfo[lowerIndex].twicePwr54;
+				upperPower = pPowerInfo[upperIndex].twicePwr54;
+				break;
+			}
+		}
+
+		twicePower = ar5211GetInterpolatedValue(chan->channel,
+			lowerChannel, upperChannel, lowerPower, upperPower, 0);
+
+		/* Reduce power by band edge restrictions */
+		twicePower = AH_MIN(twicePower, twiceMaxEdgePower);
+
+		/*
+		 * If turbo is set, reduce power to keep power
+		 * consumption under 2 Watts.  Note that we always do
+		 * this unless specially configured.  Then we limit
+		 * power only for non-AP operation.
+		 */
+		if (IS_CHAN_TURBO(chan) &&
+		    AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1
+#ifdef AH_ENABLE_AP_SUPPORT
+		    && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP
+#endif
+		) {
+			twicePower = AH_MIN(twicePower, ee->ee_turbo2WMaxPower5);
+		}
+
+		/* Reduce power by max regulatory domain allowed restrictions */
+		pRatesPower[i] = AH_MIN(twicePower, twiceMaxRDPower - twiceAntennaReduction);
+
+		/* Use 6 Mb power level for transmit power scaling reduction */
+		/* We don't want to reduce higher rates if its not needed */
+		if (i == 0) {
+			scaledPower = pRatesPower[0] -
+				(tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2);
+			if (scaledPower < 1)
+				scaledPower = 1;
+		}
+
+		pRatesPower[i] = AH_MIN(pRatesPower[i], scaledPower);
+	}
+
+	/* Record txPower at Rate 6 for info gathering */
+	ahp->ah_tx6PowerInHalfDbm = pRatesPower[0];
+
+#ifdef AH_DEBUG
+	HALDEBUG(ah, HAL_DEBUG_RESET,
+	    "%s: final output power setting %d MHz:\n",
+	    __func__, chan->channel);
+	HALDEBUG(ah, HAL_DEBUG_RESET,
+	    "6 Mb %d dBm, MaxRD: %d dBm, MaxEdge %d dBm\n",
+	    scaledPower / 2, twiceMaxRDPower / 2, twiceMaxEdgePower / 2);
+	HALDEBUG(ah, HAL_DEBUG_RESET, "TPC Scale %d dBm - Ant Red %d dBm\n",
+	    tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2,
+	    twiceAntennaReduction / 2);
+	if (IS_CHAN_TURBO(chan) &&
+	    AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1)
+		HALDEBUG(ah, HAL_DEBUG_RESET, "Max Turbo %d dBm\n",
+		    ee->ee_turbo2WMaxPower5);
+	HALDEBUG(ah, HAL_DEBUG_RESET,
+	    "  %2d | %2d | %2d | %2d | %2d | %2d | %2d | %2d dBm\n",
+	    pRatesPower[0] / 2, pRatesPower[1] / 2, pRatesPower[2] / 2,
+	    pRatesPower[3] / 2, pRatesPower[4] / 2, pRatesPower[5] / 2,
+	    pRatesPower[6] / 2, pRatesPower[7] / 2);
+#endif /* AH_DEBUG */
+
+	/* Write the power table into the hardware */
+	OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
+		 ((paPreDEnable & 1)<< 30) | ((pRatesPower[3] & mask) << 24) |
+		 ((paPreDEnable & 1)<< 22) | ((pRatesPower[2] & mask) << 16) |
+		 ((paPreDEnable & 1)<< 14) | ((pRatesPower[1] & mask) << 8) |
+		 ((paPreDEnable & 1)<< 6 ) |  (pRatesPower[0] & mask));
+	OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
+		 ((paPreDEnable & 1)<< 30) | ((pRatesPower[7] & mask) << 24) |
+		 ((paPreDEnable & 1)<< 22) | ((pRatesPower[6] & mask) << 16) |
+		 ((paPreDEnable & 1)<< 14) | ((pRatesPower[5] & mask) << 8) |
+		 ((paPreDEnable & 1)<< 6 ) |  (pRatesPower[4] & mask));
+
+	/* set max power to the power value at rate 6 */
+	ar5211SetTxPowerLimit(ah, pRatesPower[0]);
+
+	AH_PRIVATE(ah)->ah_maxPowerLevel = pRatesPower[0];
+}
+
+/*
+ * Get or interpolate the pcdac value from the calibrated data
+ */
+uint16_t
+ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue, const PCDACS_EEPROM *pSrcStruct)
+{
+	uint16_t powerValue;
+	uint16_t lFreq, rFreq;		/* left and right frequency values */
+	uint16_t llPcdac, ulPcdac;	/* lower and upper left pcdac values */
+	uint16_t lrPcdac, urPcdac;	/* lower and upper right pcdac values */
+	uint16_t lPwr, uPwr;		/* lower and upper temp pwr values */
+	uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */
+
+	if (ar5211FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue))
+		/* value was copied from srcStruct */
+		return powerValue;
+
+	ar5211GetLowerUpperValues(channel, pSrcStruct->pChannelList,
+		pSrcStruct->numChannels, &lFreq, &rFreq);
+	ar5211GetLowerUpperPcdacs(pcdacValue, lFreq, pSrcStruct,
+		&llPcdac, &ulPcdac);
+	ar5211GetLowerUpperPcdacs(pcdacValue, rFreq, pSrcStruct,
+		&lrPcdac, &urPcdac);
+
+	/* get the power index for the pcdac value */
+	ar5211FindValueInList(lFreq, llPcdac, pSrcStruct, &lPwr);
+	ar5211FindValueInList(lFreq, ulPcdac, pSrcStruct, &uPwr);
+	lScaledPwr = ar5211GetInterpolatedValue(pcdacValue,
+				llPcdac, ulPcdac, lPwr, uPwr, 0);
+
+	ar5211FindValueInList(rFreq, lrPcdac, pSrcStruct, &lPwr);
+	ar5211FindValueInList(rFreq, urPcdac, pSrcStruct, &uPwr);
+	rScaledPwr = ar5211GetInterpolatedValue(pcdacValue,
+				lrPcdac, urPcdac, lPwr, uPwr, 0);
+
+	return ar5211GetInterpolatedValue(channel, lFreq, rFreq,
+		lScaledPwr, rScaledPwr, 0);
+}
+
+/*
+ * Find the value from the calibrated source data struct
+ */
+HAL_BOOL
+ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue,
+	const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue)
+{
+	const DATA_PER_CHANNEL *pChannelData;
+	const uint16_t *pPcdac;
+	uint16_t i, j;
+
+	pChannelData = pSrcStruct->pDataPerChannel;
+	for (i = 0; i < pSrcStruct->numChannels; i++ ) {
+		if (pChannelData->channelValue == channel) {
+			pPcdac = pChannelData->PcdacValues;
+			for (j = 0; j < pChannelData->numPcdacValues; j++ ) {
+				if (*pPcdac == pcdacValue) {
+					*powerValue = pChannelData->PwrValues[j];
+					return AH_TRUE;
+				}
+				pPcdac++;
+			}
+		}
+		pChannelData++;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+uint16_t
+ar5211GetInterpolatedValue(uint16_t target,
+	uint16_t srcLeft, uint16_t srcRight,
+	uint16_t targetLeft, uint16_t targetRight,
+	HAL_BOOL scaleUp)
+{
+	uint16_t rv;
+	int16_t lRatio;
+	uint16_t scaleValue = EEP_SCALE;
+
+	/* to get an accurate ratio, always scale, if want to scale, then don't scale back down */
+	if ((targetLeft * targetRight) == 0)
+		return 0;
+	if (scaleUp)
+		scaleValue = 1;
+
+	if (srcRight != srcLeft) {
+		/*
+		 * Note the ratio always need to be scaled,
+		 * since it will be a fraction.
+		 */
+		lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft);
+		if (lRatio < 0) {
+		    /* Return as Left target if value would be negative */
+		    rv = targetLeft * (scaleUp ? EEP_SCALE : 1);
+		} else if (lRatio > EEP_SCALE) {
+		    /* Return as Right target if Ratio is greater than 100% (SCALE) */
+		    rv = targetRight * (scaleUp ? EEP_SCALE : 1);
+		} else {
+			rv = (lRatio * targetRight + (EEP_SCALE - lRatio) *
+					targetLeft) / scaleValue;
+		}
+	} else {
+		rv = targetLeft;
+		if (scaleUp)
+			rv *= EEP_SCALE;
+	}
+	return rv;
+}
+
+/*
+ *  Look for value being within 0.1 of the search values
+ *  however, NDIS can't do float calculations, so multiply everything
+ *  up by EEP_SCALE so can do integer arithmatic
+ *
+ * INPUT  value	   -value to search for
+ * INPUT  pList	   -ptr to the list to search
+ * INPUT  listSize	-number of entries in list
+ * OUTPUT pLowerValue -return the lower value
+ * OUTPUT pUpperValue -return the upper value
+ */
+void
+ar5211GetLowerUpperValues(uint16_t value,
+	const uint16_t *pList, uint16_t listSize,
+	uint16_t *pLowerValue, uint16_t *pUpperValue)
+{
+	const uint16_t listEndValue = *(pList + listSize - 1);
+	uint32_t target = value * EEP_SCALE;
+	int i;
+
+	/*
+	 * See if value is lower than the first value in the list
+	 * if so return first value
+	 */
+	if (target < (uint32_t)(*pList * EEP_SCALE - EEP_DELTA)) {
+		*pLowerValue = *pList;
+		*pUpperValue = *pList;
+		return;
+	}
+
+	/*
+	 * See if value is greater than last value in list
+	 * if so return last value
+	 */
+	if (target > (uint32_t)(listEndValue * EEP_SCALE + EEP_DELTA)) {
+		*pLowerValue = listEndValue;
+		*pUpperValue = listEndValue;
+		return;
+	}
+
+	/* look for value being near or between 2 values in list */
+	for (i = 0; i < listSize; i++) {
+		/*
+		 * If value is close to the current value of the list
+		 * then target is not between values, it is one of the values
+		 */
+		if (abs(pList[i] * EEP_SCALE - (int32_t) target) < EEP_DELTA) {
+			*pLowerValue = pList[i];
+			*pUpperValue = pList[i];
+			return;
+		}
+
+		/*
+		 * Look for value being between current value and next value
+		 * if so return these 2 values
+		 */
+		if (target < (uint32_t)(pList[i + 1] * EEP_SCALE - EEP_DELTA)) {
+			*pLowerValue = pList[i];
+			*pUpperValue = pList[i + 1];
+			return;
+		}
+	}
+}
+
+/*
+ * Get the upper and lower pcdac given the channel and the pcdac
+ * used in the search
+ */
+void
+ar5211GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
+	const PCDACS_EEPROM *pSrcStruct,
+	uint16_t *pLowerPcdac, uint16_t *pUpperPcdac)
+{
+	const DATA_PER_CHANNEL *pChannelData;
+	int i;
+
+	/* Find the channel information */
+	pChannelData = pSrcStruct->pDataPerChannel;
+	for (i = 0; i < pSrcStruct->numChannels; i++) {
+		if (pChannelData->channelValue == channel)
+			break;
+		pChannelData++;
+	}
+	ar5211GetLowerUpperValues(pcdac, pChannelData->PcdacValues,
+		pChannelData->numPcdacValues, pLowerPcdac, pUpperPcdac);
+}
+
+#define	DYN_ADJ_UP_MARGIN	15
+#define	DYN_ADJ_LO_MARGIN	20
+
+static const GAIN_OPTIMIZATION_LADDER gainLadder = {
+	9,					/* numStepsInLadder */
+	4,					/* defaultStepNum */
+	{ { {4, 1, 1, 1},  6, "FG8"},
+	  { {4, 0, 1, 1},  4, "FG7"},
+	  { {3, 1, 1, 1},  3, "FG6"},
+	  { {4, 0, 0, 1},  1, "FG5"},
+	  { {4, 1, 1, 0},  0, "FG4"},	/* noJack */
+	  { {4, 0, 1, 0}, -2, "FG3"},	/* halfJack */
+	  { {3, 1, 1, 0}, -3, "FG2"},	/* clip3 */
+	  { {4, 0, 0, 0}, -4, "FG1"},	/* noJack */
+	  { {2, 1, 1, 0}, -6, "FG0"} 	/* clip2 */
+	}
+};
+
+/*
+ * Initialize the gain structure to good values
+ */
+void
+ar5211InitializeGainValues(struct ath_hal *ah)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	GAIN_VALUES *gv = &ahp->ah_gainValues;
+
+	/* initialize gain optimization values */
+	gv->currStepNum = gainLadder.defaultStepNum;
+	gv->currStep = &gainLadder.optStep[gainLadder.defaultStepNum];
+	gv->active = AH_TRUE;
+	gv->loTrig = 20;
+	gv->hiTrig = 35;
+}
+
+static HAL_BOOL
+ar5211InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv)
+{
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	uint32_t gStep, g;
+	uint32_t L1, L2, L3, L4;
+
+	if (IS_CHAN_CCK(chan)) {
+		gStep = 0x18;
+		L1 = 0;
+		L2 = gStep + 4;
+		L3 = 0x40;
+		L4 = L3 + 50;
+
+		gv->loTrig = L1;
+		gv->hiTrig = L4+5;
+	} else {
+		gStep = 0x3f;
+		L1 = 0;
+		L2 = 50;
+		L3 = L1;
+		L4 = L3 + 50;
+
+		gv->loTrig = L1 + DYN_ADJ_LO_MARGIN;
+		gv->hiTrig = L4 - DYN_ADJ_UP_MARGIN;
+	}
+	g = gv->currGain;
+
+	return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4));
+}
+
+/*
+ * Enable the probe gain check on the next packet
+ */
+static void
+ar5211RequestRfgain(struct ath_hal *ah)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	/* Enable the gain readback probe */
+	OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE,
+		  SM(ahp->ah_tx6PowerInHalfDbm, AR_PHY_PAPD_PROBE_POWERTX)
+		| AR_PHY_PAPD_PROBE_NEXT_TX);
+
+	ahp->ah_rfgainState = HAL_RFGAIN_READ_REQUESTED;
+}
+
+/*
+ * Exported call to check for a recent gain reading and return
+ * the current state of the thermal calibration gain engine.
+ */
+HAL_RFGAIN
+ar5211GetRfgain(struct ath_hal *ah)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	GAIN_VALUES *gv = &ahp->ah_gainValues;
+	uint32_t rddata;
+
+	if (!gv->active)
+		return HAL_RFGAIN_INACTIVE;
+
+	if (ahp->ah_rfgainState == HAL_RFGAIN_READ_REQUESTED) {
+		/* Caller had asked to setup a new reading. Check it. */
+		rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE);
+
+		if ((rddata & AR_PHY_PAPD_PROBE_NEXT_TX) == 0) {
+			/* bit got cleared, we have a new reading. */
+			gv->currGain = rddata >> AR_PHY_PAPD_PROBE_GAINF_S;
+			/* inactive by default */
+			ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+
+			if (!ar5211InvalidGainReadback(ah, gv) &&
+			    ar5211IsGainAdjustNeeded(ah, gv) &&
+			    ar5211AdjustGain(ah, gv) > 0) {
+				/*
+				 * Change needed. Copy ladder info
+				 * into eeprom info.
+				 */
+				ar5211SetRfgain(ah, gv);
+				ahp->ah_rfgainState = HAL_RFGAIN_NEED_CHANGE;
+			}
+		}
+	}
+	return ahp->ah_rfgainState;
+}
+
+/*
+ * Check to see if our readback gain level sits within the linear
+ * region of our current variable attenuation window
+ */
+static HAL_BOOL
+ar5211IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv)
+{
+	return (gv->currGain <= gv->loTrig || gv->currGain >= gv->hiTrig);
+}
+
+/*
+ * Move the rabbit ears in the correct direction.
+ */
+static int32_t 
+ar5211AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv)
+{
+	/* return > 0 for valid adjustments. */
+	if (!gv->active)
+		return -1;
+
+	gv->currStep = &gainLadder.optStep[gv->currStepNum];
+	if (gv->currGain >= gv->hiTrig) {
+		if (gv->currStepNum == 0) {
+			HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+			    "%s: Max gain limit.\n", __func__);
+			return -1;
+		}
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+		    "%s: Adding gain: currG=%d [%s] --> ",
+		    __func__, gv->currGain, gv->currStep->stepName);
+		gv->targetGain = gv->currGain;
+		while (gv->targetGain >= gv->hiTrig && gv->currStepNum > 0) {
+			gv->targetGain -= 2 * (gainLadder.optStep[--(gv->currStepNum)].stepGain -
+				gv->currStep->stepGain);
+			gv->currStep = &gainLadder.optStep[gv->currStepNum];
+		}
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
+		    gv->targetGain, gv->currStep->stepName);
+		return 1;
+	}
+	if (gv->currGain <= gv->loTrig) {
+		if (gv->currStepNum == gainLadder.numStepsInLadder-1) {
+			HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+			    "%s: Min gain limit.\n", __func__);
+			return -2;
+		}
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+		    "%s: Deducting gain: currG=%d [%s] --> ",
+		    __func__, gv->currGain, gv->currStep->stepName);
+		gv->targetGain = gv->currGain;
+		while (gv->targetGain <= gv->loTrig &&
+		      gv->currStepNum < (gainLadder.numStepsInLadder - 1)) {
+			gv->targetGain -= 2 *
+				(gainLadder.optStep[++(gv->currStepNum)].stepGain - gv->currStep->stepGain);
+			gv->currStep = &gainLadder.optStep[gv->currStepNum];
+		}
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
+		    gv->targetGain, gv->currStep->stepName);
+		return 2;
+	}
+	return 0;		/* caller didn't call needAdjGain first */
+}
+
+/*
+ * Adjust the 5GHz EEPROM information with the desired calibration values.
+ */
+static void
+ar5211SetRfgain(struct ath_hal *ah, const GAIN_VALUES *gv)
+{
+	HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	if (!gv->active)
+		return;
+	ee->ee_cornerCal.clip = gv->currStep->paramVal[0]; /* bb_tx_clip */
+	ee->ee_cornerCal.pd90 = gv->currStep->paramVal[1]; /* rf_pwd_90 */
+	ee->ee_cornerCal.pd84 = gv->currStep->paramVal[2]; /* rf_pwd_84 */
+	ee->ee_cornerCal.gSel = gv->currStep->paramVal[3]; /* rf_rfgainsel */
+}
+
+static void
+ar5211SetOperatingMode(struct ath_hal *ah, int opmode)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	uint32_t val;
+
+	val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;
+	switch (opmode) {
+	case HAL_M_HOSTAP:
+		OS_REG_WRITE(ah, AR_STA_ID1, val
+			| AR_STA_ID1_STA_AP
+			| AR_STA_ID1_RTS_USE_DEF
+			| ahp->ah_staId1Defaults);
+		break;
+	case HAL_M_IBSS:
+		OS_REG_WRITE(ah, AR_STA_ID1, val
+			| AR_STA_ID1_ADHOC
+			| AR_STA_ID1_DESC_ANTENNA
+			| ahp->ah_staId1Defaults);
+		break;
+	case HAL_M_STA:
+	case HAL_M_MONITOR:
+		OS_REG_WRITE(ah, AR_STA_ID1, val
+			| AR_STA_ID1_DEFAULT_ANTENNA
+			| ahp->ah_staId1Defaults);
+		break;
+	}
+}
+
+void
+ar5211SetPCUConfig(struct ath_hal *ah)
+{
+	ar5211SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_xmit.c b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_xmit.c
new file mode 100644
index 0000000..7f75bd0
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211_xmit.c
@@ -0,0 +1,662 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211_xmit.c,v 1.6 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_desc.h"
+
+#include "ar5211/ar5211.h"
+#include "ar5211/ar5211reg.h"
+#include "ar5211/ar5211desc.h"
+
+/*
+ * Update Tx FIFO trigger level.
+ *
+ * Set bIncTrigLevel to TRUE to increase the trigger level.
+ * Set bIncTrigLevel to FALSE to decrease the trigger level.
+ *
+ * Returns TRUE if the trigger level was updated
+ */
+HAL_BOOL
+ar5211UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
+{
+	uint32_t curTrigLevel, txcfg;
+	HAL_INT ints = ar5211GetInterrupts(ah);
+
+	/*
+	 * Disable chip interrupts. This is because halUpdateTxTrigLevel
+	 * is called from both ISR and non-ISR contexts.
+	 */
+	ar5211SetInterrupts(ah, ints &~ HAL_INT_GLOBAL);
+	txcfg = OS_REG_READ(ah, AR_TXCFG);
+	curTrigLevel = (txcfg & AR_TXCFG_FTRIG_M) >> AR_TXCFG_FTRIG_S;
+	if (bIncTrigLevel){
+		/* increase the trigger level */
+		curTrigLevel = curTrigLevel +
+			((MAX_TX_FIFO_THRESHOLD - curTrigLevel) / 2);
+	} else {
+		/* decrease the trigger level if not already at the minimum */
+		if (curTrigLevel > MIN_TX_FIFO_THRESHOLD) {
+			/* decrease the trigger level */
+			curTrigLevel--;
+		} else {
+			/* no update to the trigger level */
+			/* re-enable chip interrupts */
+			ar5211SetInterrupts(ah, ints);
+			return AH_FALSE;
+		}
+	}
+	/* Update the trigger level */
+	OS_REG_WRITE(ah, AR_TXCFG, (txcfg &~ AR_TXCFG_FTRIG_M) |
+		((curTrigLevel << AR_TXCFG_FTRIG_S) & AR_TXCFG_FTRIG_M));
+	/* re-enable chip interrupts */
+	ar5211SetInterrupts(ah, ints);
+	return AH_TRUE;
+}
+
+/*
+ * Set the properties of the tx queue with the parameters
+ * from qInfo.  The queue must previously have been setup
+ * with a call to ar5211SetupTxQueue.
+ */
+HAL_BOOL
+ar5211SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	if (q >= HAL_NUM_TX_QUEUES) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);
+}
+
+/*
+ * Return the properties for the specified tx queue.
+ */
+HAL_BOOL
+ar5211GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	if (q >= HAL_NUM_TX_QUEUES) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);
+}
+
+/*
+ * Allocate and initialize a tx DCU/QCU combination.
+ */
+int
+ar5211SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
+	const HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	HAL_TX_QUEUE_INFO *qi;
+	int q;
+
+	switch (type) {
+	case HAL_TX_QUEUE_BEACON:
+		q = 9;
+		break;
+	case HAL_TX_QUEUE_CAB:
+		q = 8;
+		break;
+	case HAL_TX_QUEUE_DATA:
+		q = 0;
+		if (ahp->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE)
+			return q;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad tx queue type %u\n",
+		    __func__, type);
+		return -1;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
+
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
+		    __func__, q);
+		return -1;
+	}
+	OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
+	qi->tqi_type = type;
+	if (qInfo == AH_NULL) {
+		/* by default enable OK+ERR+DESC+URN interrupts */
+		qi->tqi_qflags =
+			  HAL_TXQ_TXOKINT_ENABLE
+			| HAL_TXQ_TXERRINT_ENABLE
+			| HAL_TXQ_TXDESCINT_ENABLE
+			| HAL_TXQ_TXURNINT_ENABLE
+			;
+		qi->tqi_aifs = INIT_AIFS;
+		qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;	/* NB: do at reset */
+		qi->tqi_cwmax = INIT_CWMAX;
+		qi->tqi_shretry = INIT_SH_RETRY;
+		qi->tqi_lgretry = INIT_LG_RETRY;
+	} else
+		(void) ar5211SetTxQueueProps(ah, q, qInfo);
+	return q;
+}
+
+/*
+ * Update the h/w interrupt registers to reflect a tx q's configuration.
+ */
+static void
+setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
+	    "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__
+		, ahp->ah_txOkInterruptMask
+		, ahp->ah_txErrInterruptMask
+		, ahp->ah_txDescInterruptMask
+		, ahp->ah_txEolInterruptMask
+		, ahp->ah_txUrnInterruptMask
+	);
+
+	OS_REG_WRITE(ah, AR_IMR_S0,
+		  SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
+		| SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
+	);
+	OS_REG_WRITE(ah, AR_IMR_S1,
+		  SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
+		| SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
+	);
+	OS_REG_RMW_FIELD(ah, AR_IMR_S2,
+		AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
+}
+
+
+/*
+ * Free a tx DCU/QCU combination.
+ */
+HAL_BOOL
+ar5211ReleaseTxQueue(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	HAL_TX_QUEUE_INFO *qi;
+
+	if (q >= HAL_NUM_TX_QUEUES) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);
+
+	qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
+	ahp->ah_txOkInterruptMask &= ~(1 << q);
+	ahp->ah_txErrInterruptMask &= ~(1 << q);
+	ahp->ah_txDescInterruptMask &= ~(1 << q);
+	ahp->ah_txEolInterruptMask &= ~(1 << q);
+	ahp->ah_txUrnInterruptMask &= ~(1 << q);
+	setTxQInterrupts(ah, qi);
+
+	return AH_TRUE;
+}
+
+/*
+ * Set the retry, aifs, cwmin/max, readyTime regs for specified queue
+ */
+HAL_BOOL
+ar5211ResetTxQueue(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5211 *ahp = AH5211(ah);
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	HAL_TX_QUEUE_INFO *qi;
+	uint32_t cwMin, chanCwMin, value;
+
+	if (q >= HAL_NUM_TX_QUEUES) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
+		    __func__, q);
+		return AH_TRUE;		/* XXX??? */
+	}
+
+	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
+		/*
+		 * Select cwmin according to channel type.
+		 * NB: chan can be NULL during attach
+		 */
+		if (chan && IS_CHAN_B(chan))
+			chanCwMin = INIT_CWMIN_11B;
+		else
+			chanCwMin = INIT_CWMIN;
+		/* make sure that the CWmin is of the form (2^n - 1) */
+		for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
+			;
+	} else
+		cwMin = qi->tqi_cwmin;
+
+	/* set cwMin/Max and AIFS values */
+	OS_REG_WRITE(ah, AR_DLCL_IFS(q),
+		  SM(cwMin, AR_D_LCL_IFS_CWMIN)
+		| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
+		| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
+
+	/* Set retry limit values */
+	OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), 
+		   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
+		 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
+		 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
+		 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
+	);
+
+	/* enable early termination on the QCU */
+	OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
+
+	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
+		/* Configure DCU to use the global sequence count */
+		OS_REG_WRITE(ah, AR_DMISC(q), AR5311_D_MISC_SEQ_NUM_CONTROL);
+	}
+	/* multiqueue support */
+	if (qi->tqi_cbrPeriod) {
+		OS_REG_WRITE(ah, AR_QCBRCFG(q), 
+			  SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
+			| SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
+		OS_REG_WRITE(ah, AR_QMISC(q),
+			OS_REG_READ(ah, AR_QMISC(q)) |
+			AR_Q_MISC_FSP_CBR |
+			(qi->tqi_cbrOverflowLimit ?
+				AR_Q_MISC_CBR_EXP_CNTR_LIMIT : 0));
+	}
+	if (qi->tqi_readyTime) {
+		OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
+			SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) | 
+			AR_Q_RDYTIMECFG_EN);
+	}
+	if (qi->tqi_burstTime) {
+		OS_REG_WRITE(ah, AR_DCHNTIME(q),
+			SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
+			AR_D_CHNTIME_EN);
+		if (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE) {
+			OS_REG_WRITE(ah, AR_QMISC(q),
+			     OS_REG_READ(ah, AR_QMISC(q)) |
+			     AR_Q_MISC_RDYTIME_EXP_POLICY);
+		}
+	}
+
+	if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
+		OS_REG_WRITE(ah, AR_DMISC(q),
+			OS_REG_READ(ah, AR_DMISC(q)) |
+			AR_D_MISC_POST_FR_BKOFF_DIS);
+	}
+	if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
+		OS_REG_WRITE(ah, AR_DMISC(q),
+			OS_REG_READ(ah, AR_DMISC(q)) |
+			AR_D_MISC_FRAG_BKOFF_EN);
+	}
+	switch (qi->tqi_type) {
+	case HAL_TX_QUEUE_BEACON:
+		/* Configure QCU for beacons */
+		OS_REG_WRITE(ah, AR_QMISC(q),
+			OS_REG_READ(ah, AR_QMISC(q))
+			| AR_Q_MISC_FSP_DBA_GATED
+			| AR_Q_MISC_BEACON_USE
+			| AR_Q_MISC_CBR_INCR_DIS1);
+		/* Configure DCU for beacons */
+		value = (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
+			| AR_D_MISC_BEACON_USE | AR_D_MISC_POST_FR_BKOFF_DIS;
+		if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU)
+			value |= AR5311_D_MISC_SEQ_NUM_CONTROL;
+		OS_REG_WRITE(ah, AR_DMISC(q), value);
+		break;
+	case HAL_TX_QUEUE_CAB:
+		/* Configure QCU for CAB (Crap After Beacon) frames */
+		OS_REG_WRITE(ah, AR_QMISC(q),
+			OS_REG_READ(ah, AR_QMISC(q))
+			| AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1
+			| AR_Q_MISC_CBR_INCR_DIS0 | AR_Q_MISC_RDYTIME_EXP_POLICY);
+
+		value = (ahp->ah_beaconInterval
+			- (ath_hal_sw_beacon_response_time - ath_hal_dma_beacon_response_time)
+			- ath_hal_additional_swba_backoff) * 1024;
+		OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);
+
+		/* Configure DCU for CAB */
+		value = (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S);
+		if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU)
+			value |= AR5311_D_MISC_SEQ_NUM_CONTROL;
+		OS_REG_WRITE(ah, AR_QMISC(q), value);
+		break;
+	default:
+		/* NB: silence compiler */
+		break;
+	}
+
+	/*
+	 * Always update the secondary interrupt mask registers - this
+	 * could be a new queue getting enabled in a running system or
+	 * hw getting re-initialized during a reset!
+	 *
+	 * Since we don't differentiate between tx interrupts corresponding
+	 * to individual queues - secondary tx mask regs are always unmasked;
+	 * tx interrupts are enabled/disabled for all queues collectively
+	 * using the primary mask reg
+	 */
+	if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
+		ahp->ah_txOkInterruptMask |= 1 << q;
+	else
+		ahp->ah_txOkInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
+		ahp->ah_txErrInterruptMask |= 1 << q;
+	else
+		ahp->ah_txErrInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
+		ahp->ah_txDescInterruptMask |= 1 << q;
+	else
+		ahp->ah_txDescInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
+		ahp->ah_txEolInterruptMask |= 1 << q;
+	else
+		ahp->ah_txEolInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
+		ahp->ah_txUrnInterruptMask |= 1 << q;
+	else
+		ahp->ah_txUrnInterruptMask &= ~(1 << q);
+	setTxQInterrupts(ah, qi);
+
+	return AH_TRUE;
+}
+
+/*
+ * Get the TXDP for the specified data queue.
+ */
+uint32_t
+ar5211GetTxDP(struct ath_hal *ah, u_int q)
+{
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+	return OS_REG_READ(ah, AR_QTXDP(q));
+}
+
+/*
+ * Set the TxDP for the specified tx queue.
+ */
+HAL_BOOL
+ar5211SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
+{
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+	HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	/*
+	 * Make sure that TXE is deasserted before setting the TXDP.  If TXE
+	 * is still asserted, setting TXDP will have no effect.
+	 */
+	HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
+
+	OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
+
+	return AH_TRUE;
+}
+
+/*
+ * Set Transmit Enable bits for the specified queues.
+ */
+HAL_BOOL
+ar5211StartTxDma(struct ath_hal *ah, u_int q)
+{
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+	HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	/* Check that queue is not already active */
+	HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1<<q)) == 0);
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
+
+	/* Check to be sure we're not enabling a q that has its TXD bit set. */
+	HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
+
+	OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
+	return AH_TRUE;
+}
+
+/*
+ * Return the number of frames pending on the specified queue.
+ */
+uint32_t
+ar5211NumTxPending(struct ath_hal *ah, u_int q)
+{
+	uint32_t n;
+
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+	HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	n = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT_M;
+	/*
+	 * Pending frame count (PFC) can momentarily go to zero
+	 * while TXE remains asserted.  In other words a PFC of
+	 * zero is not sufficient to say that the queue has stopped.
+	 */
+	if (n == 0 && (OS_REG_READ(ah, AR_Q_TXE) & (1<<q)))
+		n = 1;			/* arbitrarily pick 1 */
+	return n;
+}
+
+/*
+ * Stop transmit on the specified queue
+ */
+HAL_BOOL
+ar5211StopTxDma(struct ath_hal *ah, u_int q)
+{
+	int i;
+
+	HALASSERT(q < HAL_NUM_TX_QUEUES);
+	HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	OS_REG_WRITE(ah, AR_Q_TXD, 1<<q);
+	for (i = 0; i < 10000; i++) {
+		if (ar5211NumTxPending(ah, q) == 0)
+			break;
+		OS_DELAY(10);
+	}
+	OS_REG_WRITE(ah, AR_Q_TXD, 0);
+
+	return (i < 10000);
+}
+
+/*
+ * Descriptor Access Functions
+ */
+
+#define	VALID_PKT_TYPES \
+	((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
+	 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
+	 (1<<HAL_PKT_TYPE_BEACON))
+#define	isValidPktType(_t)	((1<<(_t)) & VALID_PKT_TYPES)
+#define	VALID_TX_RATES \
+	((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
+	 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
+	 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
+#define	isValidTxRate(_r)	((1<<(_r)) & VALID_TX_RATES)
+
+HAL_BOOL
+ar5211SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int pktLen,
+	u_int hdrLen,
+	HAL_PKT_TYPE type,
+	u_int txPower,
+	u_int txRate0, u_int txTries0,
+	u_int keyIx,
+	u_int antMode,
+	u_int flags,
+	u_int rtsctsRate,
+	u_int rtsctsDuration,
+	u_int compicvLen, 
+	u_int compivLen,
+	u_int comp)
+{
+	struct ar5211_desc *ads = AR5211DESC(ds);
+
+	(void) hdrLen;
+	(void) txPower;
+	(void) rtsctsRate; (void) rtsctsDuration;
+
+	HALASSERT(txTries0 != 0);
+	HALASSERT(isValidPktType(type));
+	HALASSERT(isValidTxRate(txRate0));
+	/* XXX validate antMode */
+
+	ads->ds_ctl0 = (pktLen & AR_FrameLen)
+		     | (txRate0 << AR_XmitRate_S)
+		     | (antMode << AR_AntModeXmit_S)
+		     | (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
+		     | (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
+		     | (flags & HAL_TXDESC_RTSENA ? AR_RTSCTSEnable : 0)
+		     | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
+		     ;
+	ads->ds_ctl1 = (type << 26)
+		     | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
+		     ;
+
+	if (keyIx != HAL_TXKEYIX_INVALID) {
+		ads->ds_ctl1 |=
+			(keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
+		ads->ds_ctl0 |= AR_EncryptKeyValid;
+	}
+	return AH_TRUE;
+#undef RATE
+}
+
+HAL_BOOL
+ar5211SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int txRate1, u_int txTries1,
+	u_int txRate2, u_int txTries2,
+	u_int txRate3, u_int txTries3)
+{
+	(void) ah; (void) ds;
+	(void) txRate1; (void) txTries1;
+	(void) txRate2; (void) txTries2;
+	(void) txRate3; (void) txTries3;
+	return AH_FALSE;
+}
+
+void
+ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
+{
+	struct ar5211_desc *ads = AR5211DESC(ds);
+
+	ads->ds_ctl0 |= AR_TxInterReq;
+}
+
+HAL_BOOL
+ar5211FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
+	const struct ath_desc *ds0)
+{
+	struct ar5211_desc *ads = AR5211DESC(ds);
+
+	HALASSERT((segLen &~ AR_BufLen) == 0);
+
+	if (firstSeg) {
+		/*
+		 * First descriptor, don't clobber xmit control data
+		 * setup by ar5211SetupTxDesc.
+		 */
+		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
+	} else if (lastSeg) {		/* !firstSeg && lastSeg */
+		/*
+		 * Last descriptor in a multi-descriptor frame,
+		 * copy the transmit parameters from the first
+		 * frame for processing on completion. 
+		 */
+		ads->ds_ctl0 = AR5211DESC_CONST(ds0)->ds_ctl0;
+		ads->ds_ctl1 = segLen;
+	} else {			/* !firstSeg && !lastSeg */
+		/*
+		 * Intermediate descriptor in a multi-descriptor frame.
+		 */
+		ads->ds_ctl0 = 0;
+		ads->ds_ctl1 = segLen | AR_More;
+	}
+	ads->ds_status0 = ads->ds_status1 = 0;
+	return AH_TRUE;
+}
+
+/*
+ * Processing of HW TX descriptor.
+ */
+HAL_STATUS
+ar5211ProcTxDesc(struct ath_hal *ah,
+	struct ath_desc *ds, struct ath_tx_status *ts)
+{
+	struct ar5211_desc *ads = AR5211DESC(ds);
+
+	if ((ads->ds_status1 & AR_Done) == 0)
+		return HAL_EINPROGRESS;
+
+	/* Update software copies of the HW status */
+	ts->ts_seqnum = MS(ads->ds_status1, AR_SeqNum);
+	ts->ts_tstamp = MS(ads->ds_status0, AR_SendTimestamp);
+	ts->ts_status = 0;
+	if ((ads->ds_status0 & AR_FrmXmitOK) == 0) {
+		if (ads->ds_status0 & AR_ExcessiveRetries)
+			ts->ts_status |= HAL_TXERR_XRETRY;
+		if (ads->ds_status0 & AR_Filtered)
+			ts->ts_status |= HAL_TXERR_FILT;
+		if (ads->ds_status0 & AR_FIFOUnderrun)
+			ts->ts_status |= HAL_TXERR_FIFO;
+	}
+	ts->ts_rate = MS(ads->ds_ctl0, AR_XmitRate);
+	ts->ts_rssi = MS(ads->ds_status1, AR_AckSigStrength);
+	ts->ts_shortretry = MS(ads->ds_status0, AR_ShortRetryCnt);
+	ts->ts_longretry = MS(ads->ds_status0, AR_LongRetryCnt);
+	ts->ts_virtcol = MS(ads->ds_status0, AR_VirtCollCnt);
+	ts->ts_antenna = 0;		/* NB: don't know */
+	ts->ts_finaltsi = 0;
+	/*
+	 * NB: the number of retries is one less than it should be.
+	 * Also, 0 retries and 1 retry are both reported as 0 retries.
+	 */
+	if (ts->ts_shortretry > 0)
+		ts->ts_shortretry++;
+	if (ts->ts_longretry > 0)
+		ts->ts_longretry++;
+
+	return HAL_OK;
+}
+
+/*
+ * Determine which tx queues need interrupt servicing.
+ * STUB.
+ */
+void
+ar5211GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
+{
+	return;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211desc.h b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211desc.h
new file mode 100644
index 0000000..9fa6e29
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211desc.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211desc.h,v 1.5 2008/11/10 04:08:03 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5211DESC_H
+#define _DEV_ATH_AR5211DESC_H
+
+#include "ah_desc.h"
+
+/*
+ * Defintions for the DMA descriptors used by the Atheros
+ * AR5211 and AR5110 Wireless Lan controller parts.
+ */
+
+/* DMA descriptors */
+struct ar5211_desc {
+	uint32_t	ds_link;	/* link pointer */
+	uint32_t	ds_data;	/* data buffer pointer */
+	uint32_t	ds_ctl0;	/* DMA control 0 */
+	uint32_t	ds_ctl1;	/* DMA control 1 */
+	uint32_t	ds_status0;	/* DMA status 0 */
+	uint32_t	ds_status1;	/* DMA status 1 */
+} __packed;
+#define	AR5211DESC(_ds)	((struct ar5211_desc *)(_ds))
+#define	AR5211DESC_CONST(_ds)	((const struct ar5211_desc *)(_ds))
+
+/* TX ds_ctl0 */
+#define	AR_FrameLen		0x00000fff	/* frame length */
+/* bits 12-17 are reserved */
+#define	AR_XmitRate		0x003c0000	/* txrate */
+#define	AR_XmitRate_S		18
+#define	AR_RTSCTSEnable		0x00400000	/* RTS/CTS enable */
+#define	AR_VEOL			0x00800000	/* virtual end-of-list */
+#define	AR_ClearDestMask	0x01000000	/* Clear destination mask bit */
+#define	AR_AntModeXmit		0x1e000000	/* TX antenna seslection */
+#define	AR_AntModeXmit_S	25
+#define	AR_TxInterReq		0x20000000	/* TX interrupt request */
+#define	AR_EncryptKeyValid	0x40000000	/* EncryptKeyIdx is valid */
+/* bit 31 is reserved */
+
+/* TX ds_ctl1 */
+#define	AR_BufLen		0x00000fff	/* data buffer length */
+#define	AR_More			0x00001000	/* more desc in this frame */
+#define	AR_EncryptKeyIdx	0x000fe000	/* ecnrypt key table index */
+#define	AR_EncryptKeyIdx_S	13
+#define	AR_FrmType		0x00700000	/* frame type indication */
+#define	AR_FrmType_S		20
+#define	AR_Frm_Normal		0x00000000	/* normal frame */
+#define	AR_Frm_ATIM		0x00100000	/* ATIM frame */
+#define	AR_Frm_PSPOLL		0x00200000	/* PS poll frame */
+#define	AR_Frm_Beacon		0x00300000	/* Beacon frame */
+#define	AR_Frm_ProbeResp	0x00400000	/* no delay data */
+#define	AR_NoAck		0x00800000	/* No ACK flag */
+/* bits 24-31 are reserved */
+
+/* RX ds_ctl1 */
+/*	AR_BufLen		0x00000fff	   data buffer length */
+/* bit 12 is reserved */
+#define	AR_RxInterReq		0x00002000	/* RX interrupt request */
+/* bits 14-31 are reserved */
+
+/* TX ds_status0 */
+#define	AR_FrmXmitOK		0x00000001	/* TX success */
+#define	AR_ExcessiveRetries	0x00000002	/* excessive retries */
+#define	AR_FIFOUnderrun		0x00000004	/* TX FIFO underrun */
+#define	AR_Filtered		0x00000008	/* TX filter indication */
+/* NB: the spec has the Short+Long retry counts reversed */
+#define	AR_LongRetryCnt		0x000000f0	/* long retry count */
+#define	AR_LongRetryCnt_S	4
+#define	AR_ShortRetryCnt	0x00000f00	/* short retry count */
+#define	AR_ShortRetryCnt_S	8
+#define	AR_VirtCollCnt		0x0000f000	/* virtual collision count */
+#define	AR_VirtCollCnt_S	12
+#define	AR_SendTimestamp	0xffff0000	/* TX timestamp */
+#define	AR_SendTimestamp_S	16
+
+/* RX ds_status0 */
+#define	AR_DataLen		0x00000fff	/* RX data length */
+/*	AR_More			0x00001000	   more desc in this frame */
+/* bits 13-14 are reserved */
+#define	AR_RcvRate		0x00078000	/* reception rate */
+#define	AR_RcvRate_S		15
+#define	AR_RcvSigStrength	0x07f80000	/* receive signal strength */
+#define	AR_RcvSigStrength_S	19
+#define	AR_RcvAntenna		0x38000000	/* receive antenaa */
+#define	AR_RcvAntenna_S		27
+/* bits 30-31 are reserved */
+
+/* TX ds_status1 */
+#define	AR_Done			0x00000001	/* descripter complete */
+#define	AR_SeqNum		0x00001ffe	/* TX sequence number */
+#define	AR_SeqNum_S		1
+#define	AR_AckSigStrength	0x001fe000	/* strength of ACK */
+#define	AR_AckSigStrength_S	13
+/* bits 21-31 are reserved */
+
+/* RX ds_status1 */
+/*	AR_Done			0x00000001	   descripter complete */
+#define	AR_FrmRcvOK		0x00000002	/* frame reception success */
+#define	AR_CRCErr		0x00000004	/* CRC error */
+/* bit 3 reserved */
+#define	AR_DecryptCRCErr	0x00000010	/* Decryption CRC fiailure */
+#define	AR_PHYErr		0x000000e0	/* PHY error */
+#define	AR_PHYErr_S		5
+#define	AR_PHYErr_Underrun	0x00000000	/* Transmit underrun */
+#define	AR_PHYErr_Tim		0x00000020	/* Timing error */
+#define	AR_PHYErr_Par		0x00000040	/* Parity error */
+#define	AR_PHYErr_Rate		0x00000060	/* Illegal rate */
+#define	AR_PHYErr_Len		0x00000080	/* Illegal length */
+#define	AR_PHYErr_Radar		0x000000a0	/* Radar detect */
+#define	AR_PHYErr_Srv		0x000000c0	/* Illegal service */
+#define	AR_PHYErr_TOR		0x000000e0	/* Transmit override receive */
+#define	AR_KeyIdxValid		0x00000100	/* decryption key index valid */
+#define	AR_KeyIdx		0x00007e00	/* Decryption key index */
+#define	AR_KeyIdx_S		9
+#define	AR_RcvTimestamp		0x0fff8000	/* timestamp */
+#define	AR_RcvTimestamp_S	15
+#define	AR_KeyCacheMiss		0x10000000	/* key cache miss indication */
+
+#endif /* _DEV_ATH_AR5211DESC_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211phy.h b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211phy.h
new file mode 100644
index 0000000..8bd7051
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211phy.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211phy.h,v 1.4 2008/11/10 01:19:38 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5211PHY_H
+#define _DEV_ATH_AR5211PHY_H
+
+/*
+ * Definitions for the PHY on the Atheros AR5211/5311 chipset.
+ */
+
+/* PHY registers */
+#define	AR_PHY_BASE	0x9800	/* PHY registers base address */
+#define	AR_PHY(_n)	(AR_PHY_BASE + ((_n)<<2))
+
+#define	AR_PHY_TURBO	0x9804	/* PHY frame control register */
+#define	AR_PHY_FC_TURBO_MODE	0x00000001	/* Set turbo mode bits */
+#define	AR_PHY_FC_TURBO_SHORT	0x00000002	/* Set short symbols to turbo mode setting */
+
+#define	AR_PHY_CHIP_ID	0x9818	/* PHY chip revision ID */
+
+#define	AR_PHY_ACTIVE	0x981C	/* PHY activation register */
+#define	AR_PHY_ACTIVE_EN	0x00000001	/* Activate PHY chips */
+#define	AR_PHY_ACTIVE_DIS	0x00000000	/* Deactivate PHY chips */
+
+#define	AR_PHY_AGC_CONTROL	0x9860	/* PHY chip calibration and noise floor setting */
+#define	AR_PHY_AGC_CONTROL_CAL	0x00000001	/* Perform PHY chip internal calibration */
+#define	AR_PHY_AGC_CONTROL_NF	0x00000002	/* Perform PHY chip noise-floor calculation */
+
+#define	AR_PHY_PLL_CTL	0x987c	/* PLL control register */
+#define	AR_PHY_PLL_CTL_44	0x19	/* 44 MHz for 11b channels and FPGA */
+#define	AR_PHY_PLL_CTL_40	0x18	/* 40 MHz */
+#define	AR_PHY_PLL_CTL_20	0x13	/* 20 MHz half rate 11a for emulation */
+
+
+#define	AR_PHY_RX_DELAY	0x9914	/* PHY analog_power_on_time, in 100ns increments */
+#define	AR_PHY_RX_DELAY_M	0x00003FFF	/* Mask for delay from active assertion (wake up) */
+				/* to enable_receiver */
+
+#define	AR_PHY_TIMING_CTRL4	0x9920	/* PHY */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M	0x0000001F	/* Mask for kcos_theta-1 for q correction */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M	0x000007E0	/* Mask for sin_theta for i correction */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S	5         	/* Shift for sin_theta for i correction */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_ENABLE	0x00000800	/* enable IQ correction */
+#define	AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M	0x0000F000	/* Mask for max number of samples (logarithmic) */
+#define	AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S	12        	/* Shift for max number of samples */
+#define	AR_PHY_TIMING_CTRL4_DO_IQCAL	0x00010000	/* perform IQ calibration */
+
+#define	AR_PHY_PAPD_PROBE	0x9930
+#define	AR_PHY_PAPD_PROBE_POWERTX	0x00007E00
+#define	AR_PHY_PAPD_PROBE_POWERTX_S	9
+#define	AR_PHY_PAPD_PROBE_NEXT_TX	0x00008000	/* command to take next reading */
+#define	AR_PHY_PAPD_PROBE_GAINF	0xFE000000
+#define	AR_PHY_PAPD_PROBE_GAINF_S	25
+
+#define	AR_PHY_POWER_TX_RATE1		0x9934
+#define	AR_PHY_POWER_TX_RATE2		0x9938
+#define	AR_PHY_POWER_TX_RATE_MAX	0x993c
+
+#define	AR_PHY_FRAME_CTL	0x9944
+#define	AR_PHY_FRAME_CTL_TX_CLIP	0x00000038
+#define	AR_PHY_FRAME_CTL_TX_CLIP_S	3
+#define AR_PHY_FRAME_CTL_ERR_SERV	0x20000000
+#define AR_PHY_FRAME_CTL_ERR_SERV_S	29
+
+#define	AR_PHY_RADAR_0	0x9954	/* PHY radar detection settings */
+#define	AR_PHY_RADAR_0_ENA	0x00000001	/* Enable radar detection */
+
+#define	AR_PHY_IQCAL_RES_PWR_MEAS_I	0x9c10	/*PHY IQ calibration results - power measurement for I */
+#define	AR_PHY_IQCAL_RES_PWR_MEAS_Q	0x9c14	/*PHY IQ calibration results - power measurement for Q */
+#define	AR_PHY_IQCAL_RES_IQ_CORR_MEAS	0x9c18	/*PHY IQ calibration results - IQ correlation measurement */
+#define	AR_PHY_CURRENT_RSSI	0x9c1c	/* rssi of current frame being received */
+
+#define	AR5211_PHY_MODE	0xA200	/* Mode register */
+#define	AR5211_PHY_MODE_OFDM	0x0	/* bit 0 = 0 for OFDM */
+#define	AR5211_PHY_MODE_CCK	0x1	/* bit 0 = 1 for CCK */
+#define	AR5211_PHY_MODE_RF5GHZ	0x0	/* bit 1 = 0 for 5 GHz */
+#define	AR5211_PHY_MODE_RF2GHZ	0x2	/* bit 1 = 1 for 2.4 GHz */
+
+#endif /* _DEV_ATH_AR5211PHY_H */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211reg.h b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211reg.h
new file mode 100644
index 0000000..babd565
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/ar5211reg.h
@@ -0,0 +1,853 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5211reg.h,v 1.4 2008/11/10 01:19:38 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5211REG_H
+#define _DEV_ATH_AR5211REG_H
+
+/*
+ * Definitions for the Atheros AR5211/5311 chipset.
+ */
+
+/*
+ * Maui2/Spirit specific registers/fields are indicated by AR5311.
+ * Oahu specific registers/fields are indicated by AR5211.
+ */
+
+/* DMA Control and Interrupt Registers */
+#define	AR_CR		0x0008		/* control register */
+#define	AR_RXDP		0x000C		/* receive queue descriptor pointer */
+#define	AR_CFG		0x0014		/* configuration and status register */
+#define	AR_IER		0x0024		/* Interrupt enable register */
+#define	AR_RTSD0	0x0028		/* RTS Duration Parameters 0 */
+#define	AR_RTSD1	0x002c		/* RTS Duration Parameters 1 */
+#define	AR_TXCFG	0x0030		/* tx DMA size config register */
+#define	AR_RXCFG	0x0034		/* rx DMA size config register */
+#define	AR5211_JUMBO_LAST	0x0038	/* Jumbo descriptor last address */
+#define	AR_MIBC		0x0040		/* MIB control register */
+#define	AR_TOPS		0x0044		/* timeout prescale count */
+#define	AR_RXNPTO	0x0048		/* no frame received timeout */
+#define	AR_TXNPTO	0x004C		/* no frame trasmitted timeout */
+#define	AR_RFGTO	0x0050		/* receive frame gap timeout */
+#define	AR_RFCNT	0x0054		/* receive frame count limit */
+#define	AR_MACMISC	0x0058		/* miscellaneous control/status */
+#define	AR5311_QDCLKGATE	0x005c	/* QCU/DCU clock gating control */
+#define	AR_ISR		0x0080		/* Primary interrupt status register */
+#define	AR_ISR_S0	0x0084		/* Secondary interrupt status reg 0 */
+#define	AR_ISR_S1	0x0088		/* Secondary interrupt status reg 1 */
+#define	AR_ISR_S2	0x008c		/* Secondary interrupt status reg 2 */
+#define	AR_ISR_S3	0x0090		/* Secondary interrupt status reg 3 */
+#define	AR_ISR_S4	0x0094		/* Secondary interrupt status reg 4 */
+#define	AR_IMR		0x00a0		/* Primary interrupt mask register */
+#define	AR_IMR_S0	0x00a4		/* Secondary interrupt mask reg 0 */
+#define	AR_IMR_S1	0x00a8		/* Secondary interrupt mask reg 1 */
+#define	AR_IMR_S2	0x00ac		/* Secondary interrupt mask reg 2 */
+#define	AR_IMR_S3	0x00b0		/* Secondary interrupt mask reg 3 */
+#define	AR_IMR_S4	0x00b4		/* Secondary interrupt mask reg 4 */
+#define	AR_ISR_RAC	0x00c0		/* Primary interrupt status reg, */
+/* Shadow copies with read-and-clear access */
+#define	AR_ISR_S0_S	0x00c4		/* Secondary interrupt status reg 0 */
+#define	AR_ISR_S1_S	0x00c8		/* Secondary interrupt status reg 1 */
+#define	AR_ISR_S2_S	0x00cc		/* Secondary interrupt status reg 2 */
+#define	AR_ISR_S3_S	0x00d0		/* Secondary interrupt status reg 3 */
+#define	AR_ISR_S4_S	0x00d4		/* Secondary interrupt status reg 4 */
+
+#define	AR_Q0_TXDP	0x0800		/* Transmit Queue descriptor pointer */
+#define	AR_Q1_TXDP	0x0804		/* Transmit Queue descriptor pointer */
+#define	AR_Q2_TXDP	0x0808		/* Transmit Queue descriptor pointer */
+#define	AR_Q3_TXDP	0x080c		/* Transmit Queue descriptor pointer */
+#define	AR_Q4_TXDP	0x0810		/* Transmit Queue descriptor pointer */
+#define	AR_Q5_TXDP	0x0814		/* Transmit Queue descriptor pointer */
+#define	AR_Q6_TXDP	0x0818		/* Transmit Queue descriptor pointer */
+#define	AR_Q7_TXDP	0x081c		/* Transmit Queue descriptor pointer */
+#define	AR_Q8_TXDP	0x0820		/* Transmit Queue descriptor pointer */
+#define	AR_Q9_TXDP	0x0824		/* Transmit Queue descriptor pointer */
+#define	AR_QTXDP(i)	(AR_Q0_TXDP + ((i)<<2))
+
+#define	AR_Q_TXE	0x0840		/* Transmit Queue enable */
+#define	AR_Q_TXD	0x0880		/* Transmit Queue disable */
+
+#define	AR_Q0_CBRCFG	0x08c0		/* CBR configuration */
+#define	AR_Q1_CBRCFG	0x08c4		/* CBR configuration */
+#define	AR_Q2_CBRCFG	0x08c8		/* CBR configuration */
+#define	AR_Q3_CBRCFG	0x08cc		/* CBR configuration */
+#define	AR_Q4_CBRCFG	0x08d0		/* CBR configuration */
+#define	AR_Q5_CBRCFG	0x08d4		/* CBR configuration */
+#define	AR_Q6_CBRCFG	0x08d8		/* CBR configuration */
+#define	AR_Q7_CBRCFG	0x08dc		/* CBR configuration */
+#define	AR_Q8_CBRCFG	0x08e0		/* CBR configuration */
+#define	AR_Q9_CBRCFG	0x08e4		/* CBR configuration */
+#define	AR_QCBRCFG(i)	(AR_Q0_CBRCFG + ((i)<<2))
+
+#define	AR_Q0_RDYTIMECFG	0x0900	/* ReadyTime configuration */
+#define	AR_Q1_RDYTIMECFG	0x0904	/* ReadyTime configuration */
+#define	AR_Q2_RDYTIMECFG	0x0908	/* ReadyTime configuration */
+#define	AR_Q3_RDYTIMECFG	0x090c	/* ReadyTime configuration */
+#define	AR_Q4_RDYTIMECFG	0x0910	/* ReadyTime configuration */
+#define	AR_Q5_RDYTIMECFG	0x0914	/* ReadyTime configuration */
+#define	AR_Q6_RDYTIMECFG	0x0918	/* ReadyTime configuration */
+#define	AR_Q7_RDYTIMECFG	0x091c	/* ReadyTime configuration */
+#define	AR_Q8_RDYTIMECFG	0x0920	/* ReadyTime configuration */
+#define	AR_Q9_RDYTIMECFG	0x0924	/* ReadyTime configuration */
+#define	AR_QRDYTIMECFG(i)	(AR_Q0_RDYTIMECFG + ((i)<<2))
+
+#define	AR_Q_ONESHOTARM_SC	0x0940	/* OneShotArm set control */
+#define	AR_Q_ONESHOTARM_CC	0x0980	/* OneShotArm clear control */
+
+#define	AR_Q0_MISC	0x09c0		/* Miscellaneous QCU settings */
+#define	AR_Q1_MISC	0x09c4		/* Miscellaneous QCU settings */
+#define	AR_Q2_MISC	0x09c8		/* Miscellaneous QCU settings */
+#define	AR_Q3_MISC	0x09cc		/* Miscellaneous QCU settings */
+#define	AR_Q4_MISC	0x09d0		/* Miscellaneous QCU settings */
+#define	AR_Q5_MISC	0x09d4		/* Miscellaneous QCU settings */
+#define	AR_Q6_MISC	0x09d8		/* Miscellaneous QCU settings */
+#define	AR_Q7_MISC	0x09dc		/* Miscellaneous QCU settings */
+#define	AR_Q8_MISC	0x09e0		/* Miscellaneous QCU settings */
+#define	AR_Q9_MISC	0x09e4		/* Miscellaneous QCU settings */
+#define	AR_QMISC(i)	(AR_Q0_MISC + ((i)<<2))
+
+#define	AR_Q0_STS	0x0a00		/* Miscellaneous QCU status */
+#define	AR_Q1_STS	0x0a04		/* Miscellaneous QCU status */
+#define	AR_Q2_STS	0x0a08		/* Miscellaneous QCU status */
+#define	AR_Q3_STS	0x0a0c		/* Miscellaneous QCU status */
+#define	AR_Q4_STS	0x0a10		/* Miscellaneous QCU status */
+#define	AR_Q5_STS	0x0a14		/* Miscellaneous QCU status */
+#define	AR_Q6_STS	0x0a18		/* Miscellaneous QCU status */
+#define	AR_Q7_STS	0x0a1c		/* Miscellaneous QCU status */
+#define	AR_Q8_STS	0x0a20		/* Miscellaneous QCU status */
+#define	AR_Q9_STS	0x0a24		/* Miscellaneous QCU status */
+#define	AR_QSTS(i)	(AR_Q0_STS + ((i)<<2))
+
+#define	AR_Q_RDYTIMESHDN	0x0a40	/* ReadyTimeShutdown status */
+#define	AR_D0_QCUMASK	0x1000		/* QCU Mask */
+#define	AR_D1_QCUMASK	0x1004		/* QCU Mask */
+#define	AR_D2_QCUMASK	0x1008		/* QCU Mask */
+#define	AR_D3_QCUMASK	0x100c		/* QCU Mask */
+#define	AR_D4_QCUMASK	0x1010		/* QCU Mask */
+#define	AR_D5_QCUMASK	0x1014		/* QCU Mask */
+#define	AR_D6_QCUMASK	0x1018		/* QCU Mask */
+#define	AR_D7_QCUMASK	0x101c		/* QCU Mask */
+#define	AR_D8_QCUMASK	0x1020		/* QCU Mask */
+#define	AR_D9_QCUMASK	0x1024		/* QCU Mask */
+#define	AR_DQCUMASK(i)	(AR_D0_QCUMASK + ((i)<<2))
+
+#define	AR_D0_LCL_IFS	0x1040		/* DCU-specific IFS settings */
+#define	AR_D1_LCL_IFS	0x1044		/* DCU-specific IFS settings */
+#define	AR_D2_LCL_IFS	0x1048		/* DCU-specific IFS settings */
+#define	AR_D3_LCL_IFS	0x104c		/* DCU-specific IFS settings */
+#define	AR_D4_LCL_IFS	0x1050		/* DCU-specific IFS settings */
+#define	AR_D5_LCL_IFS	0x1054		/* DCU-specific IFS settings */
+#define	AR_D6_LCL_IFS	0x1058		/* DCU-specific IFS settings */
+#define	AR_D7_LCL_IFS	0x105c		/* DCU-specific IFS settings */
+#define	AR_D8_LCL_IFS	0x1060		/* DCU-specific IFS settings */
+#define	AR_D9_LCL_IFS	0x1064		/* DCU-specific IFS settings */
+#define	AR_DLCL_IFS(i)	(AR_D0_LCL_IFS + ((i)<<2))
+
+#define	AR_D0_RETRY_LIMIT	0x1080	/* Retry limits */
+#define	AR_D1_RETRY_LIMIT	0x1084	/* Retry limits */
+#define	AR_D2_RETRY_LIMIT	0x1088	/* Retry limits */
+#define	AR_D3_RETRY_LIMIT	0x108c	/* Retry limits */
+#define	AR_D4_RETRY_LIMIT	0x1090	/* Retry limits */
+#define	AR_D5_RETRY_LIMIT	0x1094	/* Retry limits */
+#define	AR_D6_RETRY_LIMIT	0x1098	/* Retry limits */
+#define	AR_D7_RETRY_LIMIT	0x109c	/* Retry limits */
+#define	AR_D8_RETRY_LIMIT	0x10a0	/* Retry limits */
+#define	AR_D9_RETRY_LIMIT	0x10a4	/* Retry limits */
+#define	AR_DRETRY_LIMIT(i)	(AR_D0_RETRY_LIMIT + ((i)<<2))
+
+#define	AR_D0_CHNTIME	0x10c0		/* ChannelTime settings */
+#define	AR_D1_CHNTIME	0x10c4		/* ChannelTime settings */
+#define	AR_D2_CHNTIME	0x10c8		/* ChannelTime settings */
+#define	AR_D3_CHNTIME	0x10cc		/* ChannelTime settings */
+#define	AR_D4_CHNTIME	0x10d0		/* ChannelTime settings */
+#define	AR_D5_CHNTIME	0x10d4		/* ChannelTime settings */
+#define	AR_D6_CHNTIME	0x10d8		/* ChannelTime settings */
+#define	AR_D7_CHNTIME	0x10dc		/* ChannelTime settings */
+#define	AR_D8_CHNTIME	0x10e0		/* ChannelTime settings */
+#define	AR_D9_CHNTIME	0x10e4		/* ChannelTime settings */
+#define	AR_DCHNTIME(i)	(AR_D0_CHNTIME + ((i)<<2))
+
+#define	AR_D0_MISC	0x1100		/* Misc DCU-specific settings */
+#define	AR_D1_MISC	0x1104		/* Misc DCU-specific settings */
+#define	AR_D2_MISC	0x1108		/* Misc DCU-specific settings */
+#define	AR_D3_MISC	0x110c		/* Misc DCU-specific settings */
+#define	AR_D4_MISC	0x1110		/* Misc DCU-specific settings */
+#define	AR_D5_MISC	0x1114		/* Misc DCU-specific settings */
+#define	AR_D6_MISC	0x1118		/* Misc DCU-specific settings */
+#define	AR_D7_MISC	0x111c		/* Misc DCU-specific settings */
+#define	AR_D8_MISC	0x1120		/* Misc DCU-specific settings */
+#define	AR_D9_MISC	0x1124		/* Misc DCU-specific settings */
+#define	AR_DMISC(i)	(AR_D0_MISC + ((i)<<2))
+
+#define	AR_D0_SEQNUM	0x1140		/* Frame seqnum control/status */
+#define	AR_D1_SEQNUM	0x1144		/* Frame seqnum control/status */
+#define	AR_D2_SEQNUM	0x1148		/* Frame seqnum control/status */
+#define	AR_D3_SEQNUM	0x114c		/* Frame seqnum control/status */
+#define	AR_D4_SEQNUM	0x1150		/* Frame seqnum control/status */
+#define	AR_D5_SEQNUM	0x1154		/* Frame seqnum control/status */
+#define	AR_D6_SEQNUM	0x1158		/* Frame seqnum control/status */
+#define	AR_D7_SEQNUM	0x115c		/* Frame seqnum control/status */
+#define	AR_D8_SEQNUM	0x1160		/* Frame seqnum control/status */
+#define	AR_D9_SEQNUM	0x1164		/* Frame seqnum control/status */
+#define	AR_DSEQNUM(i)	(AR_D0_SEQNUM + ((i<<2)))
+
+/* MAC DCU-global IFS settings */
+#define	AR_D_GBL_IFS_SIFS	0x1030	/* DCU global SIFS settings */
+#define	AR_D_GBL_IFS_SLOT	0x1070	/* DC global slot interval */
+#define	AR_D_GBL_IFS_EIFS	0x10b0	/* DCU global EIFS setting */
+#define	AR_D_GBL_IFS_MISC	0x10f0	/* DCU global misc. IFS settings */
+#define	AR_D_FPCTL	0x1230		/* DCU frame prefetch settings */
+#define	AR_D_TXPSE	0x1270		/* DCU transmit pause control/status */
+#define	AR_D_TXBLK_CMD	0x1038		/* DCU transmit filter cmd (w/only) */
+#define	AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i))	/* DCU transmit filter data */
+#define	AR_D_TXBLK_CLR	0x143c		/* DCU clear tx filter (w/only) */
+#define	AR_D_TXBLK_SET	0x147c		/* DCU set tx filter (w/only) */
+
+#define	AR_D_TXPSE	0x1270		/* DCU transmit pause control/status */
+
+#define	AR_RC		0x4000		/* Warm reset control register */
+#define	AR_SCR		0x4004		/* Sleep control register */
+#define	AR_INTPEND	0x4008		/* Interrupt Pending register */
+#define	AR_SFR		0x400C		/* Sleep force register */
+#define	AR_PCICFG	0x4010		/* PCI configuration register */
+#define	AR_GPIOCR	0x4014		/* GPIO control register */
+#define	AR_GPIODO	0x4018		/* GPIO data output access register */
+#define	AR_GPIODI	0x401C		/* GPIO data input access register */
+#define	AR_SREV		0x4020		/* Silicon Revision register */
+
+#define	AR_EEPROM_ADDR	0x6000		/* EEPROM address register (10 bit) */
+#define	AR_EEPROM_DATA	0x6004		/* EEPROM data register (16 bit) */
+#define	AR_EEPROM_CMD	0x6008		/* EEPROM command register */
+#define	AR_EEPROM_STS	0x600c		/* EEPROM status register */
+#define	AR_EEPROM_CFG	0x6010		/* EEPROM configuration register */
+
+#define	AR_STA_ID0	0x8000		/* station ID0 - low 32 bits */
+#define	AR_STA_ID1	0x8004		/* station ID1 - upper 16 bits */
+#define	AR_BSS_ID0	0x8008		/* BSSID low 32 bits */
+#define	AR_BSS_ID1	0x800C		/* BSSID upper 16 bits / AID */
+#define	AR_SLOT_TIME	0x8010		/* Time-out after a collision */
+#define	AR_TIME_OUT	0x8014		/* ACK & CTS time-out */
+#define	AR_RSSI_THR	0x8018		/* RSSI warning & missed beacon threshold */
+#define	AR_USEC		0x801c		/* transmit latency register */
+#define	AR_BEACON	0x8020		/* beacon control value/mode bits */
+#define	AR_CFP_PERIOD	0x8024		/* CFP Interval (TU/msec) */
+#define	AR_TIMER0	0x8028		/* Next beacon time (TU/msec) */
+#define	AR_TIMER1	0x802c		/* DMA beacon alert time (1/8 TU) */
+#define	AR_TIMER2	0x8030		/* Software beacon alert (1/8 TU) */
+#define	AR_TIMER3	0x8034		/* ATIM window time */
+#define	AR_CFP_DUR	0x8038		/* maximum CFP duration in TU */
+#define	AR_RX_FILTER	0x803C		/* receive filter register */
+#define	AR_MCAST_FIL0	0x8040		/* multicast filter lower 32 bits */
+#define	AR_MCAST_FIL1	0x8044		/* multicast filter upper 32 bits */
+#define	AR_DIAG_SW	0x8048		/* PCU control register */
+#define	AR_TSF_L32	0x804c		/* local clock lower 32 bits */
+#define	AR_TSF_U32	0x8050		/* local clock upper 32 bits */
+#define	AR_TST_ADDAC	0x8054		/* ADDAC test register */
+#define	AR_DEF_ANTENNA	0x8058		/* default antenna register */
+
+#define	AR_LAST_TSTP	0x8080		/* Time stamp of the last beacon rcvd */
+#define	AR_NAV		0x8084		/* current NAV value */
+#define	AR_RTS_OK	0x8088		/* RTS exchange success counter */
+#define	AR_RTS_FAIL	0x808c		/* RTS exchange failure counter */
+#define	AR_ACK_FAIL	0x8090		/* ACK failure counter */
+#define	AR_FCS_FAIL	0x8094		/* FCS check failure counter */
+#define	AR_BEACON_CNT	0x8098		/* Valid beacon counter */
+
+#define	AR_KEYTABLE_0	0x8800		/* Encryption key table */
+#define	AR_KEYTABLE(n)	(AR_KEYTABLE_0 + ((n)*32))
+
+#define	AR_CR_RXE	0x00000004	/* Receive enable */
+#define	AR_CR_RXD	0x00000020	/* Receive disable */
+#define	AR_CR_SWI	0x00000040	/* One-shot software interrupt */
+#define	AR_CR_BITS	"\20\3RXE\6RXD\7SWI"
+
+#define	AR_CFG_SWTD	0x00000001	/* byteswap tx descriptor words */
+#define	AR_CFG_SWTB	0x00000002	/* byteswap tx data buffer words */
+#define	AR_CFG_SWRD	0x00000004	/* byteswap rx descriptor words */
+#define	AR_CFG_SWRB	0x00000008	/* byteswap rx data buffer words */
+#define	AR_CFG_SWRG	0x00000010	/* byteswap register access data words */
+#define	AR_CFG_AP_ADHOC_INDICATION	0x00000020	/* AP/adhoc indication (0-AP, 1-Adhoc) */
+#define	AR_CFG_PHOK	0x00000100	/* PHY OK status */
+#define	AR_CFG_EEBS	0x00000200	/* EEPROM busy */
+#define	AR_CFG_CLK_GATE_DIS	0x00000400	/* Clock gating disable (Oahu only) */
+#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH_M	0x00060000	/* Mask of PCI core master request queue full threshold */
+#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH_S	17        	/* Shift for PCI core master request queue full threshold */
+#define	AR_CFG_BITS \
+	"\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\10PHYOK11EEBS"
+
+#define	AR_IER_ENABLE	0x00000001	/* Global interrupt enable */
+#define	AR_IER_DISABLE	0x00000000	/* Global interrupt disable */
+#define	AR_IER_BITS	"\20\1ENABLE"
+
+#define	AR_RTSD0_RTS_DURATION_6_M	0x000000FF
+#define	AR_RTSD0_RTS_DURATION_6_S	0
+#define	AR_RTSD0_RTS_DURATION_9_M	0x0000FF00
+#define	AR_RTSD0_RTS_DURATION_9_S	8
+#define	AR_RTSD0_RTS_DURATION_12_M	0x00FF0000
+#define	AR_RTSD0_RTS_DURATION_12_S	16
+#define	AR_RTSD0_RTS_DURATION_18_M	0xFF000000
+#define	AR_RTSD0_RTS_DURATION_18_S	24
+
+#define	AR_RTSD0_RTS_DURATION_24_M	0x000000FF
+#define	AR_RTSD0_RTS_DURATION_24_S	0
+#define	AR_RTSD0_RTS_DURATION_36_M	0x0000FF00
+#define	AR_RTSD0_RTS_DURATION_36_S	8
+#define	AR_RTSD0_RTS_DURATION_48_M	0x00FF0000
+#define	AR_RTSD0_RTS_DURATION_48_S	16
+#define	AR_RTSD0_RTS_DURATION_54_M	0xFF000000
+#define	AR_RTSD0_RTS_DURATION_54_S	24
+
+#define	AR_DMASIZE_4B	0x00000000	/* DMA size 4 bytes (TXCFG + RXCFG) */
+#define	AR_DMASIZE_8B	0x00000001	/* DMA size 8 bytes */
+#define	AR_DMASIZE_16B	0x00000002	/* DMA size 16 bytes */
+#define	AR_DMASIZE_32B	0x00000003	/* DMA size 32 bytes */
+#define	AR_DMASIZE_64B	0x00000004	/* DMA size 64 bytes */
+#define	AR_DMASIZE_128B	0x00000005	/* DMA size 128 bytes */
+#define	AR_DMASIZE_256B	0x00000006	/* DMA size 256 bytes */
+#define	AR_DMASIZE_512B	0x00000007	/* DMA size 512 bytes */
+
+#define	AR_TXCFG_FTRIG_M	0x000003F0	/* Mask for Frame trigger level */
+#define	AR_TXCFG_FTRIG_S	4         	/* Shift for Frame trigger level */
+#define	AR_TXCFG_FTRIG_IMMED	0x00000000	/* bytes in PCU TX FIFO before air */
+#define	AR_TXCFG_FTRIG_64B	0x00000010	/* default */
+#define	AR_TXCFG_FTRIG_128B	0x00000020
+#define	AR_TXCFG_FTRIG_192B	0x00000030
+#define	AR_TXCFG_FTRIG_256B	0x00000040	/* 5 bits total */
+#define	AR_TXCFG_BITS	"\20"
+
+#define	AR5311_RXCFG_DEF_RX_ANTENNA	0x00000008	/* Default Receive Antenna */
+						/* Maui2/Spirit only - reserved on Oahu */
+#define	AR_RXCFG_ZLFDMA	0x00000010	/* Enable DMA of zero-length frame */
+#define	AR_RXCFG_EN_JUM	0x00000020	/* Enable jumbo rx descriptors */
+#define	AR_RXCFG_WR_JUM	0x00000040	/* Wrap jumbo rx descriptors */
+
+#define	AR_MIBC_COW	0x00000001	/* counter overflow warning */
+#define	AR_MIBC_FMC	0x00000002	/* freeze MIB counters */
+#define	AR_MIBC_CMC	0x00000004	/* clear MIB counters */
+#define	AR_MIBC_MCS	0x00000008	/* MIB counter strobe, increment all */
+
+#define	AR_TOPS_MASK	0x0000FFFF	/* Mask for timeout prescale */
+
+#define	AR_RXNPTO_MASK	0x000003FF	/* Mask for no frame received timeout */
+
+#define	AR_TXNPTO_MASK	0x000003FF	/* Mask for no frame transmitted timeout */
+#define	AR_TXNPTO_QCU_MASK	0x03FFFC00	/* Mask indicating the set of QCUs */
+					/* for which frame completions will cause */
+					/* a reset of the no frame transmitted timeout */
+
+#define	AR_RPGTO_MASK	0x000003FF	/* Mask for receive frame gap timeout */
+
+#define	AR_RPCNT_MASK	0x0000001F	/* Mask for receive frame count limit */
+
+#define	AR_MACMISC_DMA_OBS_M	0x000001E0	/* Mask for DMA observation bus mux select */
+#define	AR_MACMISC_DMA_OBS_S	5         	/* Shift for DMA observation bus mux select */
+#define	AR_MACMISC_MISC_OBS_M	0x00000E00	/* Mask for MISC observation bus mux select */
+#define	AR_MACMISC_MISC_OBS_S	9         	/* Shift for MISC observation bus mux select */
+#define	AR_MACMISC_MAC_OBS_BUS_LSB_M	0x00007000	/* Mask for MAC observation bus mux select (lsb) */
+#define	AR_MACMISC_MAC_OBS_BUS_LSB_S	12        	/* Shift for MAC observation bus mux select (lsb) */
+#define	AR_MACMISC_MAC_OBS_BUS_MSB_M	0x00038000	/* Mask for MAC observation bus mux select (msb) */
+#define	AR_MACMISC_MAC_OBS_BUS_MSB_S	15        	/* Shift for MAC observation bus mux select (msb) */
+
+				/* Maui2/Spirit only. */
+#define	AR5311_QDCLKGATE_QCU_M	0x0000FFFF	/* Mask for QCU clock disable */
+#define	AR5311_QDCLKGATE_DCU_M	0x07FF0000	/* Mask for DCU clock disable */
+
+	/* Interrupt Status Registers */
+#define	AR_ISR_RXOK	0x00000001	/* At least one frame received sans errors */
+#define	AR_ISR_RXDESC	0x00000002	/* Receive interrupt request */
+#define	AR_ISR_RXERR	0x00000004	/* Receive error interrupt */
+#define	AR_ISR_RXNOPKT	0x00000008	/* No frame received within timeout clock */
+#define	AR_ISR_RXEOL	0x00000010	/* Received descriptor empty interrupt */
+#define	AR_ISR_RXORN	0x00000020	/* Receive FIFO overrun interrupt */
+#define	AR_ISR_TXOK	0x00000040	/* Transmit okay interrupt */
+#define	AR_ISR_TXDESC	0x00000080	/* Transmit interrupt request */
+#define	AR_ISR_TXERR	0x00000100	/* Transmit error interrupt */
+#define	AR_ISR_TXNOPKT	0x00000200	/* No frame transmitted interrupt */
+#define	AR_ISR_TXEOL	0x00000400	/* Transmit descriptor empty interrupt */
+#define	AR_ISR_TXURN	0x00000800	/* Transmit FIFO underrun interrupt */
+#define	AR_ISR_MIB	0x00001000	/* MIB interrupt - see MIBC */
+#define	AR_ISR_SWI	0x00002000	/* Software interrupt */
+#define	AR_ISR_RXPHY	0x00004000	/* PHY receive error interrupt */
+#define	AR_ISR_RXKCM	0x00008000	/* Key-cache miss interrupt */
+#define	AR_ISR_SWBA	0x00010000	/* Software beacon alert interrupt */
+#define	AR_ISR_BRSSI	0x00020000	/* Beacon threshold interrupt */
+#define	AR_ISR_BMISS	0x00040000	/* Beacon missed interrupt */
+#define	AR_ISR_HIUERR	0x00080000	/* An unexpected bus error has occurred */
+#define	AR_ISR_BNR	0x00100000	/* Beacon not ready interrupt */
+#define	AR_ISR_TIM	0x00800000	/* TIM interrupt */
+#define	AR_ISR_GPIO	0x01000000	/* GPIO Interrupt */
+#define	AR_ISR_QCBROVF	0x02000000	/* QCU CBR overflow interrupt */
+#define	AR_ISR_QCBRURN	0x04000000	/* QCU CBR underrun interrupt */
+#define	AR_ISR_QTRIG	0x08000000	/* QCU scheduling trigger interrupt */
+#define	AR_ISR_RESV0	0xF0000000	/* Reserved */
+
+#define	AR_ISR_S0_QCU_TXOK_M	0x000003FF	/* Mask for TXOK (QCU 0-9) */
+#define	AR_ISR_S0_QCU_TXDESC_M	0x03FF0000	/* Mask for TXDESC (QCU 0-9) */
+
+#define	AR_ISR_S1_QCU_TXERR_M	0x000003FF	/* Mask for TXERR (QCU 0-9) */
+#define	AR_ISR_S1_QCU_TXEOL_M	0x03FF0000	/* Mask for TXEOL (QCU 0-9) */
+
+#define	AR_ISR_S2_QCU_TXURN_M	0x000003FF	/* Mask for TXURN (QCU 0-9) */
+#define	AR_ISR_S2_MCABT	0x00010000	/* Master cycle abort interrupt */
+#define	AR_ISR_S2_SSERR	0x00020000	/* SERR interrupt */
+#define	AR_ISR_S2_DPERR	0x00040000	/* PCI bus parity error */
+#define	AR_ISR_S2_RESV0	0xFFF80000	/* Reserved */
+
+#define	AR_ISR_S3_QCU_QCBROVF_M	0x000003FF	/* Mask for QCBROVF (QCU 0-9) */
+#define	AR_ISR_S3_QCU_QCBRURN_M	0x03FF0000	/* Mask for QCBRURN (QCU 0-9) */
+
+#define	AR_ISR_S4_QCU_QTRIG_M	0x000003FF	/* Mask for QTRIG (QCU 0-9) */
+#define	AR_ISR_S4_RESV0	0xFFFFFC00	/* Reserved */
+
+	/* Interrupt Mask Registers */
+#define	AR_IMR_RXOK	0x00000001	/* At least one frame received sans errors */
+#define	AR_IMR_RXDESC	0x00000002	/* Receive interrupt request */
+#define	AR_IMR_RXERR	0x00000004	/* Receive error interrupt */
+#define	AR_IMR_RXNOPKT	0x00000008	/* No frame received within timeout clock */
+#define	AR_IMR_RXEOL	0x00000010	/* Received descriptor empty interrupt */
+#define	AR_IMR_RXORN	0x00000020	/* Receive FIFO overrun interrupt */
+#define	AR_IMR_TXOK	0x00000040	/* Transmit okay interrupt */
+#define	AR_IMR_TXDESC	0x00000080	/* Transmit interrupt request */
+#define	AR_IMR_TXERR	0x00000100	/* Transmit error interrupt */
+#define	AR_IMR_TXNOPKT	0x00000200	/* No frame transmitted interrupt */
+#define	AR_IMR_TXEOL	0x00000400	/* Transmit descriptor empty interrupt */
+#define	AR_IMR_TXURN	0x00000800	/* Transmit FIFO underrun interrupt */
+#define	AR_IMR_MIB	0x00001000	/* MIB interrupt - see MIBC */
+#define	AR_IMR_SWI	0x00002000	/* Software interrupt */
+#define	AR_IMR_RXPHY	0x00004000	/* PHY receive error interrupt */
+#define	AR_IMR_RXKCM	0x00008000	/* Key-cache miss interrupt */
+#define	AR_IMR_SWBA	0x00010000	/* Software beacon alert interrupt */
+#define	AR_IMR_BRSSI	0x00020000	/* Beacon threshold interrupt */
+#define	AR_IMR_BMISS	0x00040000	/* Beacon missed interrupt */
+#define	AR_IMR_HIUERR	0x00080000	/* An unexpected bus error has occurred */
+#define	AR_IMR_BNR	0x00100000	/* BNR interrupt */
+#define	AR_IMR_TIM	0x00800000	/* TIM interrupt */
+#define	AR_IMR_GPIO	0x01000000	/* GPIO Interrupt */
+#define	AR_IMR_QCBROVF	0x02000000	/* QCU CBR overflow interrupt */
+#define	AR_IMR_QCBRURN	0x04000000	/* QCU CBR underrun interrupt */
+#define	AR_IMR_QTRIG	0x08000000	/* QCU scheduling trigger interrupt */
+#define	AR_IMR_RESV0	0xF0000000	/* Reserved */
+
+#define	AR_IMR_S0_QCU_TXOK	0x000003FF	/* Mask for TXOK (QCU 0-9) */
+#define	AR_IMR_S0_QCU_TXOK_S	0
+#define	AR_IMR_S0_QCU_TXDESC	0x03FF0000	/* Mask for TXDESC (QCU 0-9) */
+#define	AR_IMR_S0_QCU_TXDESC_S	16        	/* Shift for TXDESC (QCU 0-9) */
+
+#define	AR_IMR_S1_QCU_TXERR	0x000003FF	/* Mask for TXERR (QCU 0-9) */
+#define	AR_IMR_S1_QCU_TXERR_S	0
+#define	AR_IMR_S1_QCU_TXEOL	0x03FF0000	/* Mask for TXEOL (QCU 0-9) */
+#define	AR_IMR_S1_QCU_TXEOL_S	16        	/* Shift for TXEOL (QCU 0-9) */
+
+#define	AR_IMR_S2_QCU_TXURN	0x000003FF	/* Mask for TXURN (QCU 0-9) */
+#define	AR_IMR_S2_QCU_TXURN_S	0
+#define	AR_IMR_S2_MCABT	0x00010000	/* Master cycle abort interrupt */
+#define	AR_IMR_S2_SSERR	0x00020000	/* SERR interrupt */
+#define	AR_IMR_S2_DPERR	0x00040000	/* PCI bus parity error */
+#define	AR_IMR_S2_RESV0	0xFFF80000	/* Reserved */
+
+#define	AR_IMR_S3_QCU_QCBROVF_M	0x000003FF	/* Mask for QCBROVF (QCU 0-9) */
+#define	AR_IMR_S3_QCU_QCBRURN_M	0x03FF0000	/* Mask for QCBRURN (QCU 0-9) */
+#define	AR_IMR_S3_QCU_QCBRURN_S	16        	/* Shift for QCBRURN (QCU 0-9) */
+
+#define	AR_IMR_S4_QCU_QTRIG_M	0x000003FF	/* Mask for QTRIG (QCU 0-9) */
+#define	AR_IMR_S4_RESV0	0xFFFFFC00	/* Reserved */
+
+	/* Interrupt status registers (read-and-clear access, secondary shadow copies) */
+
+	/* QCU registers */
+#define	AR_NUM_QCU	10    	/* Only use QCU 0-9 for forward QCU compatibility */
+#define	AR_QCU_0	0x0001
+#define	AR_QCU_1	0x0002
+#define	AR_QCU_2	0x0004
+#define	AR_QCU_3	0x0008
+#define	AR_QCU_4	0x0010
+#define	AR_QCU_5	0x0020
+#define	AR_QCU_6	0x0040
+#define	AR_QCU_7	0x0080
+#define	AR_QCU_8	0x0100
+#define	AR_QCU_9	0x0200
+
+#define	AR_Q_TXE_M	0x000003FF	/* Mask for TXE (QCU 0-9) */
+
+#define	AR_Q_TXD_M	0x000003FF	/* Mask for TXD (QCU 0-9) */
+
+#define	AR_Q_CBRCFG_CBR_INTERVAL	0x00FFFFFF	/* Mask for CBR interval (us) */
+#define	AR_Q_CBRCFG_CBR_INTERVAL_S		0	/* Shift for CBR interval */
+#define	AR_Q_CBRCFG_CBR_OVF_THRESH	0xFF000000	/* Mask for CBR overflow threshold */
+#define	AR_Q_CBRCFG_CBR_OVF_THRESH_S		24	/* Shift for " " " */
+
+#define	AR_Q_RDYTIMECFG_INT	0x00FFFFFF 	/* CBR interval (us) */
+#define	AR_Q_RDYTIMECFG_INT_S	0		/* Shift for ReadyTime Interval (us) */
+#define	AR_Q_RDYTIMECFG_DURATION_M	0x00FFFFFF	/* Mask for CBR interval (us) */
+#define	AR_Q_RDYTIMECFG_EN	0x01000000	/* ReadyTime enable */
+#define	AR_Q_RDYTIMECFG_RESV0	0xFE000000	/* Reserved */
+
+#define	AR_Q_ONESHOTARM_SC_M	0x0000FFFF	/* Mask for MAC_Q_ONESHOTARM_SC (QCU 0-15) */
+#define	AR_Q_ONESHOTARM_SC_RESV0 0xFFFF0000	/* Reserved */
+
+#define	AR_Q_ONESHOTARM_CC_M	0x0000FFFF	/* Mask for MAC_Q_ONESHOTARM_CC (QCU 0-15) */
+#define	AR_Q_ONESHOTARM_CC_RESV0 0xFFFF0000	/* Reserved */
+
+#define	AR_Q_MISC_FSP_M		0x0000000F	/* Mask for Frame Scheduling Policy */
+#define	AR_Q_MISC_FSP_ASAP		0	/* ASAP */
+#define	AR_Q_MISC_FSP_CBR		1	/* CBR */
+#define	AR_Q_MISC_FSP_DBA_GATED		2	/* DMA Beacon Alert gated */
+#define	AR_Q_MISC_FSP_TIM_GATED		3	/* TIM gated */
+#define	AR_Q_MISC_FSP_BEACON_SENT_GATED	4	/* Beacon-sent-gated */
+#define	AR_Q_MISC_ONE_SHOT_EN	0x00000010	/* OneShot enable */
+#define	AR_Q_MISC_CBR_INCR_DIS1	0x00000020	/* Disable CBR expired counter
+						   incr (empty q) */
+#define	AR_Q_MISC_CBR_INCR_DIS0	0x00000040	/* Disable CBR expired counter
+						   incr (empty beacon q) */
+#define	AR_Q_MISC_BEACON_USE	0x00000080	/* Beacon use indication */
+#define	AR_Q_MISC_CBR_EXP_CNTR_LIMIT	0x00000100	/* CBR expired counter limit enable */
+#define	AR_Q_MISC_RDYTIME_EXP_POLICY	0x00000200	/* Enable TXE cleared on ReadyTime expired or VEOL */
+#define	AR_Q_MISC_RESET_CBR_EXP_CTR	0x00000400	/* Reset CBR expired counter */
+#define	AR_Q_MISC_DCU_EARLY_TERM_REQ	0x00000800	/* DCU frame early termination request control */
+#define	AR_Q_MISC_RESV0	0xFFFFF000	/* Reserved */
+
+#define	AR_Q_STS_PEND_FR_CNT_M	0x00000003	/* Mask for Pending Frame Count */
+#define	AR_Q_STS_RESV0	0x000000FC	/* Reserved */
+#define	AR_Q_STS_CBR_EXP_CNT_M	0x0000FF00	/* Mask for CBR expired counter */
+#define	AR_Q_STS_RESV1	0xFFFF0000	/* Reserved */
+
+#define	AR_Q_RDYTIMESHDN_M	0x000003FF	/* Mask for ReadyTimeShutdown status (QCU 0-9) */
+
+	/* DCU registers */
+#define	AR_NUM_DCU	10    	/* Only use 10 DCU's for forward QCU/DCU compatibility */
+#define	AR_DCU_0	0x0001
+#define	AR_DCU_1	0x0002
+#define	AR_DCU_2	0x0004
+#define	AR_DCU_3	0x0008
+#define	AR_DCU_4	0x0010
+#define	AR_DCU_5	0x0020
+#define	AR_DCU_6	0x0040
+#define	AR_DCU_7	0x0080
+#define	AR_DCU_8	0x0100
+#define	AR_DCU_9	0x0200
+
+#define	AR_D_QCUMASK_M	0x000003FF	/* Mask for QCU Mask (QCU 0-9) */
+#define	AR_D_QCUMASK_RESV0	0xFFFFFC00	/* Reserved */
+
+#define	AR_D_LCL_IFS_CWMIN	0x000003FF	/* Mask for CW_MIN */
+#define	AR_D_LCL_IFS_CWMIN_S	0		/* Shift for CW_MIN */
+#define	AR_D_LCL_IFS_CWMAX	0x000FFC00	/* Mask for CW_MAX */
+#define	AR_D_LCL_IFS_CWMAX_S	10        	/* Shift for CW_MAX */
+#define	AR_D_LCL_IFS_AIFS	0x0FF00000	/* Mask for AIFS */
+#define	AR_D_LCL_IFS_AIFS_S	20        	/* Shift for AIFS */
+#define	AR_D_LCL_IFS_RESV0	0xF0000000	/* Reserved */
+
+#define	AR_D_RETRY_LIMIT_FR_SH	0x0000000F	/* Mask for frame short retry limit */
+#define	AR_D_RETRY_LIMIT_FR_SH_S	0	/* Shift for frame short retry limit */
+#define	AR_D_RETRY_LIMIT_FR_LG	0x000000F0	/* Mask for frame long retry limit */
+#define	AR_D_RETRY_LIMIT_FR_LG_S	4	/* Shift for frame long retry limit */
+#define	AR_D_RETRY_LIMIT_STA_SH	0x00003F00	/* Mask for station short retry limit */
+#define	AR_D_RETRY_LIMIT_STA_SH_S	8	/* Shift for station short retry limit */
+#define	AR_D_RETRY_LIMIT_STA_LG	0x000FC000	/* Mask for station short retry limit */
+#define	AR_D_RETRY_LIMIT_STA_LG_S	14	/* Shift for station short retry limit */
+#define	AR_D_RETRY_LIMIT_RESV0	0xFFF00000	/* Reserved */
+
+#define	AR_D_CHNTIME_EN	0x00100000	/* ChannelTime enable */
+#define	AR_D_CHNTIME_RESV0	0xFFE00000	/* Reserved */
+#define	AR_D_CHNTIME_DUR	0x000FFFFF	/* Mask for ChannelTime duration (us) */
+#define AR_D_CHNTIME_DUR_S              0 /* Shift for ChannelTime duration */
+
+#define	AR_D_MISC_BKOFF_THRESH_M	0x000007FF	/* Mask for Backoff threshold setting */
+#define AR_D_MISC_FRAG_BKOFF_EN         0x00000200 /* Backoff during a frag burst */
+#define	AR_D_MISC_HCF_POLL_EN	0x00000800	/* HFC poll enable */
+#define	AR_D_MISC_BKOFF_PERSISTENCE	0x00001000	/* Backoff persistence factor setting */
+#define	AR_D_MISC_FR_PREFETCH_EN	0x00002000	/* Frame prefetch enable */
+#define	AR_D_MISC_VIR_COL_HANDLING_M	0x0000C000	/* Mask for Virtual collision handling policy */
+#define	AR_D_MISC_VIR_COL_HANDLING_NORMAL	0     	/* Normal */
+#define	AR_D_MISC_VIR_COL_HANDLING_MODIFIED	1   	/* Modified */
+#define	AR_D_MISC_VIR_COL_HANDLING_IGNORE	2     	/* Ignore */
+#define	AR_D_MISC_BEACON_USE	0x00010000	/* Beacon use indication */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL	0x00060000	/* Mask for DCU arbiter lockout control */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_S	17        	/* Shift for DCU arbiter lockout control */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE	0      	/* No lockout */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR	1  	/* Intra-frame */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL	2    	/* Global */
+#define	AR_D_MISC_ARB_LOCKOUT_IGNORE	0x00080000	/* DCU arbiter lockout ignore control */
+#define	AR_D_MISC_SEQ_NUM_INCR_DIS	0x00100000	/* Sequence number increment disable */
+#define	AR_D_MISC_POST_FR_BKOFF_DIS	0x00200000	/* Post-frame backoff disable */
+#define	AR_D_MISC_VIRT_COLL_POLICY	0x00400000	/* Virtual coll. handling policy */
+#define	AR_D_MISC_BLOWN_IFS_POLICY	0x00800000	/* Blown IFS handling policy */
+#define	AR5311_D_MISC_SEQ_NUM_CONTROL	0x01000000	/* Sequence Number local or global */
+						/* Maui2/Spirit only, reserved on Oahu */
+#define	AR_D_MISC_RESV0	0xFE000000	/* Reserved */
+
+#define	AR_D_SEQNUM_M	0x00000FFF	/* Mask for value of sequence number */
+#define	AR_D_SEQNUM_RESV0	0xFFFFF000	/* Reserved */
+
+#define	AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL	0x00000007	/* Mask forLFSR slice select */
+#define	AR_D_GBL_IFS_MISC_TURBO_MODE	0x00000008	/* Turbo mode indication */
+#define	AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC	0x000003F0	/* Mask for SIFS duration (us) */
+#define	AR_D_GBL_IFS_MISC_USEC_DURATION	0x000FFC00	/* Mask for microsecond duration */
+#define	AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY	0x00300000	/* Mask for DCU arbiter delay */
+#define	AR_D_GBL_IFS_MISC_RESV0	0xFFC00000	/* Reserved */
+
+/* Oahu only */
+#define	AR_D_TXPSE_CTRL_M	0x000003FF	/* Mask of DCUs to pause (DCUs 0-9) */
+#define	AR_D_TXPSE_RESV0	0x0000FC00	/* Reserved */
+#define	AR_D_TXPSE_STATUS	0x00010000	/* Transmit pause status */
+#define	AR_D_TXPSE_RESV1	0xFFFE0000	/* Reserved */
+
+	/* DMA & PCI Registers in PCI space (usable during sleep) */
+#define	AR_RC_MAC	0x00000001	/* MAC reset */
+#define	AR_RC_BB	0x00000002	/* Baseband reset */
+#define	AR_RC_RESV0	0x00000004	/* Reserved */
+#define	AR_RC_RESV1	0x00000008	/* Reserved */
+#define	AR_RC_PCI	0x00000010	/* PCI-core reset */
+#define	AR_RC_BITS	"\20\1MAC\2BB\3RESV0\4RESV1\5RPCI"
+
+#define	AR_SCR_SLDUR	0x0000ffff	/* sleep duration mask, units of 128us */
+#define	AR_SCR_SLDUR_S	0
+#define	AR_SCR_SLE	0x00030000	/* sleep enable mask */
+#define	AR_SCR_SLE_S	16		/* sleep enable bits shift */
+#define	AR_SCR_SLE_WAKE	0x00000000	/* force wake */
+#define	AR_SCR_SLE_SLP	0x00010000	/* force sleep */
+#define	AR_SCR_SLE_NORM	0x00020000	/* sleep logic normal operation */
+#define	AR_SCR_SLE_UNITS	0x00000008	/* SCR units/TU */
+#define	AR_SCR_BITS	"\20\20SLE_SLP\21SLE"
+
+#define	AR_INTPEND_TRUE	0x00000001	/* interrupt pending */
+#define	AR_INTPEND_BITS	"\20\1IP"
+
+#define	AR_SFR_SLEEP	0x00000001	/* force sleep */
+
+#define	AR_PCICFG_CLKRUNEN	0x00000004	/* enable PCI CLKRUN function */
+#define	AR_PCICFG_EEPROM_SIZE_M	0x00000018	/* Mask for EEPROM size */
+#define	AR_PCICFG_EEPROM_SIZE_S	  3	/* Mask for EEPROM size */
+#define	AR_PCICFG_EEPROM_SIZE_4K	 0	/* EEPROM size 4 Kbit */
+#define	AR_PCICFG_EEPROM_SIZE_8K	 1	/* EEPROM size 8 Kbit */
+#define	AR_PCICFG_EEPROM_SIZE_16K	2	/* EEPROM size 16 Kbit */
+#define	AR_PCICFG_EEPROM_SIZE_FAILED	3	/* Failure */
+#define	AR_PCICFG_LEDCTL	0x00000060 /* LED control Status */
+#define	AR_PCICFG_LEDCTL_NONE	0x00000000 /* STA is not associated or trying */
+#define	AR_PCICFG_LEDCTL_PEND	0x00000020 /* STA is trying to associate */
+#define	AR_PCICFG_LEDCTL_ASSOC	0x00000040 /* STA is associated */
+#define	AR_PCICFG_PCI_BUS_SEL_M	0x00000380	/* Mask for PCI observation bus mux select */
+#define	AR_PCICFG_DIS_CBE_FIX	0x00000400	/* Disable fix for bad PCI CBE# generation */
+#define	AR_PCICFG_SL_INTEN	0x00000800	/* enable interrupt line assertion when asleep */
+#define	AR_PCICFG_RESV0		0x00001000	/* Reserved */
+#define	AR_PCICFG_SL_INPEN	0x00002000	/* Force asleep when an interrupt is pending */
+#define	AR_PCICFG_RESV1		0x0000C000	/* Reserved */
+#define	AR_PCICFG_SPWR_DN	0x00010000	/* mask for sleep/awake indication */
+#define	AR_PCICFG_LEDMODE	0x000E0000 /* LED mode */
+#define	AR_PCICFG_LEDMODE_PROP	0x00000000 /* Blink prop to filtered tx/rx */
+#define	AR_PCICFG_LEDMODE_RPROP	0x00020000 /* Blink prop to unfiltered tx/rx */
+#define	AR_PCICFG_LEDMODE_SPLIT	0x00040000 /* Blink power for tx/net for rx */
+#define	AR_PCICFG_LEDMODE_RAND	0x00060000 /* Blink randomly */
+#define	AR_PCICFG_LEDBLINK	0x00700000 /* LED blink threshold select */
+#define	AR_PCICFG_LEDBLINK_S	20
+#define	AR_PCICFG_LEDSLOW	0x00800000 /* LED slowest blink rate mode */
+#define	AR_PCICFG_RESV2		0xFF000000	/* Reserved */
+#define	AR_PCICFG_BITS	"\20\3CLKRUNEN\13SL_INTEN"
+
+#define	AR_GPIOCR_CR_SHIFT	2         	/* Each CR is 2 bits */
+#define	AR_GPIOCR_0_CR_N	0x00000000	/* Input only mode for GPIODO[0] */
+#define	AR_GPIOCR_0_CR_0	0x00000001	/* Output only if GPIODO[0] = 0 */
+#define	AR_GPIOCR_0_CR_1	0x00000002	/* Output only if GPIODO[0] = 1 */
+#define	AR_GPIOCR_0_CR_A	0x00000003	/* Always output */
+#define	AR_GPIOCR_1_CR_N	0x00000000	/* Input only mode for GPIODO[1] */
+#define	AR_GPIOCR_1_CR_0	0x00000004	/* Output only if GPIODO[1] = 0 */
+#define	AR_GPIOCR_1_CR_1	0x00000008	/* Output only if GPIODO[1] = 1 */
+#define	AR_GPIOCR_1_CR_A	0x0000000C	/* Always output */
+#define	AR_GPIOCR_2_CR_N	0x00000000	/* Input only mode for GPIODO[2] */
+#define	AR_GPIOCR_2_CR_0	0x00000010	/* Output only if GPIODO[2] = 0 */
+#define	AR_GPIOCR_2_CR_1	0x00000020	/* Output only if GPIODO[2] = 1 */
+#define	AR_GPIOCR_2_CR_A	0x00000030	/* Always output */
+#define	AR_GPIOCR_3_CR_N	0x00000000	/* Input only mode for GPIODO[3] */
+#define	AR_GPIOCR_3_CR_0	0x00000040	/* Output only if GPIODO[3] = 0 */
+#define	AR_GPIOCR_3_CR_1	0x00000080	/* Output only if GPIODO[3] = 1 */
+#define	AR_GPIOCR_3_CR_A	0x000000C0	/* Always output */
+#define	AR_GPIOCR_4_CR_N	0x00000000	/* Input only mode for GPIODO[4] */
+#define	AR_GPIOCR_4_CR_0	0x00000100	/* Output only if GPIODO[4] = 0 */
+#define	AR_GPIOCR_4_CR_1	0x00000200	/* Output only if GPIODO[4] = 1 */
+#define	AR_GPIOCR_4_CR_A	0x00000300	/* Always output */
+#define	AR_GPIOCR_5_CR_N	0x00000000	/* Input only mode for GPIODO[5] */
+#define	AR_GPIOCR_5_CR_0	0x00000400	/* Output only if GPIODO[5] = 0 */
+#define	AR_GPIOCR_5_CR_1	0x00000800	/* Output only if GPIODO[5] = 1 */
+#define	AR_GPIOCR_5_CR_A	0x00000C00	/* Always output */
+#define	AR_GPIOCR_INT_SHIFT	12        	/* Interrupt select field shifter */
+#define	AR_GPIOCR_INT_MASK	0x00007000	/* Interrupt select field mask */
+#define	AR_GPIOCR_INT_SEL0	0x00000000	/* Select Interrupt Pin GPIO_0 */
+#define	AR_GPIOCR_INT_SEL1	0x00001000	/* Select Interrupt Pin GPIO_1 */
+#define	AR_GPIOCR_INT_SEL2	0x00002000	/* Select Interrupt Pin GPIO_2 */
+#define	AR_GPIOCR_INT_SEL3	0x00003000	/* Select Interrupt Pin GPIO_3 */
+#define	AR_GPIOCR_INT_SEL4	0x00004000	/* Select Interrupt Pin GPIO_4 */
+#define	AR_GPIOCR_INT_SEL5	0x00005000	/* Select Interrupt Pin GPIO_5 */
+#define	AR_GPIOCR_INT_ENA	0x00008000	/* Enable GPIO Interrupt */
+#define	AR_GPIOCR_INT_SELL	0x00000000	/* Generate Interrupt if selected pin is low */
+#define	AR_GPIOCR_INT_SELH	0x00010000	/* Generate Interrupt if selected pin is high */
+
+#define	AR_SREV_ID_M	0x000000FF	/* Mask to read SREV info */
+#define	AR_PCICFG_EEPROM_SIZE_16K	2	/* EEPROM size 16 Kbit */
+#define	AR_SREV_ID_S		4		/* Major Rev Info */
+#define	AR_SREV_REVISION_M	0x0000000F	/* Chip revision level */
+#define	AR_SREV_FPGA		1
+#define	AR_SREV_D2PLUS		2
+#define	AR_SREV_D2PLUS_MS	3		/* metal spin */
+#define	AR_SREV_CRETE		4
+#define	AR_SREV_CRETE_MS	5		/* FCS metal spin */
+#define	AR_SREV_CRETE_MS23	7		/* 2.3 metal spin (6 skipped) */
+#define	AR_SREV_CRETE_23	8		/* 2.3 full tape out */
+#define	AR_SREV_VERSION_M	0x000000F0	/* Chip version indication */
+#define	AR_SREV_VERSION_CRETE	0
+#define	AR_SREV_VERSION_MAUI_1	1
+#define	AR_SREV_VERSION_MAUI_2	2
+#define	AR_SREV_VERSION_SPIRIT	3
+#define	AR_SREV_VERSION_OAHU	4
+#define	AR_SREV_OAHU_ES		0	/* Engineering Sample */
+#define	AR_SREV_OAHU_PROD	2	/* Production */
+
+#define	RAD5_SREV_MAJOR	0x10	/* All current supported ar5211 5 GHz radios are rev 0x10 */
+#define	RAD5_SREV_PROD	0x15	/* Current production level radios */
+#define	RAD2_SREV_MAJOR	0x20	/* All current supported ar5211 2 GHz radios are rev 0x10 */
+
+	/* EEPROM Registers in the MAC */
+#define	AR_EEPROM_CMD_READ	0x00000001
+#define	AR_EEPROM_CMD_WRITE	0x00000002
+#define	AR_EEPROM_CMD_RESET	0x00000004
+
+#define	AR_EEPROM_STS_READ_ERROR	0x00000001
+#define	AR_EEPROM_STS_READ_COMPLETE	0x00000002
+#define	AR_EEPROM_STS_WRITE_ERROR	0x00000004
+#define	AR_EEPROM_STS_WRITE_COMPLETE	0x00000008
+
+#define	AR_EEPROM_CFG_SIZE_M	0x00000003	/* Mask for EEPROM size determination override */
+#define	AR_EEPROM_CFG_SIZE_AUTO	0
+#define	AR_EEPROM_CFG_SIZE_4KBIT	1
+#define	AR_EEPROM_CFG_SIZE_8KBIT	2
+#define	AR_EEPROM_CFG_SIZE_16KBIT	3
+#define	AR_EEPROM_CFG_DIS_WAIT_WRITE_COMPL	0x00000004	/* Disable wait for write completion */
+#define	AR_EEPROM_CFG_CLOCK_M	0x00000018	/* Mask for EEPROM clock rate control */
+#define	AR_EEPROM_CFG_CLOCK_S	3        	/* Shift for EEPROM clock rate control */
+#define	AR_EEPROM_CFG_CLOCK_156KHZ	0
+#define	AR_EEPROM_CFG_CLOCK_312KHZ	1
+#define	AR_EEPROM_CFG_CLOCK_625KHZ	2
+#define	AR_EEPROM_CFG_RESV0	0x000000E0	/* Reserved */
+#define	AR_EEPROM_CFG_PROT_KEY_M	0x00FFFF00	/* Mask for EEPROM protection key */
+#define	AR_EEPROM_CFG_PROT_KEY_S	8          	/* Shift for EEPROM protection key */
+#define	AR_EEPROM_CFG_EN_L	0x01000000	/* EPRM_EN_L setting */
+
+	/* MAC PCU Registers */
+#define	AR_STA_ID1_SADH_MASK	0x0000FFFF	/* Mask for upper 16 bits of MAC addr */
+#define	AR_STA_ID1_STA_AP	0x00010000	/* Device is AP */
+#define	AR_STA_ID1_ADHOC	0x00020000	/* Device is ad-hoc */
+#define	AR_STA_ID1_PWR_SAV	0x00040000	/* Power save reporting in self-generated frames */
+#define	AR_STA_ID1_KSRCHDIS	0x00080000	/* Key search disable */
+#define	AR_STA_ID1_PCF	0x00100000	/* Observe PCF */
+#define	AR_STA_ID1_DEFAULT_ANTENNA	0x00200000	/* Use default antenna */
+#define	AR_STA_ID1_DESC_ANTENNA	0x00400000	/* Update default antenna w/ TX antenna */
+#define	AR_STA_ID1_RTS_USE_DEF	0x00800000	/* Use default antenna to send RTS */
+#define	AR_STA_ID1_ACKCTS_6MB	0x01000000	/* Use 6Mb/s rate for ACK & CTS */
+#define	AR_STA_ID1_BASE_RATE_11B	0x02000000	/* Use 11b base rate for ACK & CTS */
+#define	AR_STA_ID1_BITS \
+	"\20\20AP\21ADHOC\22PWR_SAV\23KSRCHDIS\25PCF"
+
+#define	AR_BSS_ID1_U16_M	0x0000FFFF	/* Mask for upper 16 bits of BSSID */
+#define	AR_BSS_ID1_AID_M	0xFFFF0000	/* Mask for association ID */
+#define	AR_BSS_ID1_AID_S	16       	/* Shift for association ID */
+
+#define	AR_SLOT_TIME_MASK	0x000007FF	/* Slot time mask */
+
+#define	AR_TIME_OUT_ACK		0x00001FFF	/* Mask for ACK time-out */
+#define	AR_TIME_OUT_ACK_S	0		/* Shift for ACK time-out */
+#define	AR_TIME_OUT_CTS		0x1FFF0000	/* Mask for CTS time-out */
+#define	AR_TIME_OUT_CTS_S	16       	/* Shift for CTS time-out */
+
+#define	AR_RSSI_THR_MASK	0x000000FF	/* Mask for Beacon RSSI warning threshold */
+#define	AR_RSSI_THR_BM_THR	0x0000FF00	/* Mask for Missed beacon threshold */
+#define	AR_RSSI_THR_BM_THR_S	8        	/* Shift for Missed beacon threshold */
+
+#define	AR_USEC_M	0x0000007F		/* Mask for clock cycles in 1 usec */
+#define	AR_USEC_32_M	0x00003F80		/* Mask for number of 32MHz clock cycles in 1 usec */
+#define	AR_USEC_32_S	7			/* Shift for number of 32MHz clock cycles in 1 usec */
+/*
+ * Tx/Rx latencies are to signal start and are in usecs.
+ *
+ * NOTE: AR5211/AR5311 difference: on Oahu, the TX latency field
+ *       has increased from 6 bits to 9 bits.  The RX latency field
+ *	 is unchanged, but is shifted over 3 bits.
+ */
+#define	AR5311_USEC_TX_LAT_M	0x000FC000	/* Tx latency */
+#define	AR5311_USEC_TX_LAT_S	14
+#define	AR5311_USEC_RX_LAT_M	0x03F00000	/* Rx latency */
+#define	AR5311_USEC_RX_LAT_S	20
+
+#define	AR5211_USEC_TX_LAT_M	0x007FC000	/* Tx latency */
+#define	AR5211_USEC_TX_LAT_S	14
+#define	AR5211_USEC_RX_LAT_M	0x1F800000	/* Rx latency */
+#define	AR5211_USEC_RX_LAT_S	23
+
+
+#define	AR_BEACON_PERIOD	0x0000FFFF	/* Beacon period in TU/msec */
+#define	AR_BEACON_PERIOD_S	0		/* Byte offset of PERIOD start*/
+#define	AR_BEACON_TIM		0x007F0000	/* Byte offset of TIM start */
+#define	AR_BEACON_TIM_S		16        	/* Byte offset of TIM start */
+#define	AR_BEACON_EN		0x00800000	/* beacon enable */
+#define	AR_BEACON_RESET_TSF	0x01000000	/* Clears TSF to 0 */
+#define	AR_BEACON_BITS	"\20\27ENABLE\30RESET_TSF"
+
+#define	AR_RX_FILTER_ALL	0x00000000	/* Disallow all frames */
+#define	AR_RX_UCAST		0x00000001	/* Allow unicast frames */
+#define	AR_RX_MCAST		0x00000002	/* Allow multicast frames */
+#define	AR_RX_BCAST		0x00000004	/* Allow broadcast frames */
+#define	AR_RX_CONTROL		0x00000008	/* Allow control frames */
+#define	AR_RX_BEACON		0x00000010	/* Allow beacon frames */
+#define	AR_RX_PROM		0x00000020	/* Promiscuous mode */
+#define	AR_RX_PHY_ERR		0x00000040	/* Allow all phy errors */
+#define	AR_RX_PHY_RADAR		0x00000080	/* Allow radar phy errors */
+#define	AR_RX_FILTER_BITS \
+	"\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC\7PHY_ERR\10PHY_RADAR"
+
+#define	AR_DIAG_SW_CACHE_ACK	0x00000001	/* disable ACK if no valid key*/
+#define	AR_DIAG_SW_DIS_ACK	0x00000002	/* disable ACK generation */
+#define	AR_DIAG_SW_DIS_CTS	0x00000004	/* disable CTS generation */
+#define	AR_DIAG_SW_DIS_ENCRYPT	0x00000008	/* disable encryption */
+#define	AR_DIAG_SW_DIS_DECRYPT	0x00000010	/* disable decryption */
+#define	AR_DIAG_SW_DIS_RX	0x00000020	/* disable receive */
+#define	AR_DIAG_SW_CORR_FCS	0x00000080	/* corrupt FCS */
+#define	AR_DIAG_SW_CHAN_INFO	0x00000100	/* dump channel info */
+#define	AR_DIAG_SW_EN_SCRAMSD	0x00000200	/* enable fixed scrambler seed*/
+#define	AR5311_DIAG_SW_USE_ECO	0x00000400	/* "super secret" use ECO enable bit */
+#define	AR_DIAG_SW_SCRAM_SEED_M	0x0001FC00	/* Fixed scrambler seed mask */
+#define	AR_DIAG_SW_SCRAM_SEED_S	10       	/* Fixed scrambler seed shfit */
+#define	AR_DIAG_SW_FRAME_NV0	0x00020000	/* accept frames of non-zero protocol version */
+#define	AR_DIAG_SW_OBS_PT_SEL_M	0x000C0000	/* Observation point select */
+#define	AR_DIAG_SW_OBS_PT_SEL_S	18       	/* Observation point select */
+#define	AR_DIAG_SW_BITS \
+	"\20\1DIS_CACHE_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_RX"\
+	"\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED\14USE_ECO\24FRAME_NV0"
+
+#define	AR_KEYTABLE_KEY0(n)	(AR_KEYTABLE(n) + 0)	/* key bit 0-31 */
+#define	AR_KEYTABLE_KEY1(n)	(AR_KEYTABLE(n) + 4)	/* key bit 32-47 */
+#define	AR_KEYTABLE_KEY2(n)	(AR_KEYTABLE(n) + 8)	/* key bit 48-79 */
+#define	AR_KEYTABLE_KEY3(n)	(AR_KEYTABLE(n) + 12)	/* key bit 80-95 */
+#define	AR_KEYTABLE_KEY4(n)	(AR_KEYTABLE(n) + 16)	/* key bit 96-127 */
+#define	AR_KEYTABLE_TYPE(n)	(AR_KEYTABLE(n) + 20)	/* key type */
+#define	AR_KEYTABLE_TYPE_40	0x00000000	/* WEP 40 bit key */
+#define	AR_KEYTABLE_TYPE_104	0x00000001	/* WEP 104 bit key */
+#define	AR_KEYTABLE_TYPE_128	0x00000003	/* WEP 128 bit key */
+#define	AR_KEYTABLE_TYPE_AES	0x00000005	/* AES 128 bit key */
+#define	AR_KEYTABLE_TYPE_CLR	0x00000007	/* no encryption */
+#define	AR_KEYTABLE_MAC0(n)	(AR_KEYTABLE(n) + 24)	/* MAC address 1-32 */
+#define	AR_KEYTABLE_MAC1(n)	(AR_KEYTABLE(n) + 28)	/* MAC address 33-47 */
+#define	AR_KEYTABLE_VALID	0x00008000	/* key and MAC address valid */
+
+#endif /* _DEV_ATH_AR5211REG_H */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5211/boss.ini b/sys/dev/netif/ath/hal/ath_hal/ar5211/boss.ini
new file mode 100644
index 0000000..a041c44
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5211/boss.ini
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2006 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: boss.ini,v 1.3 2008/11/10 04:08:03 sam Exp $
+ */
+/* Auto Generated PCI Register Writes.  Created: 09/12/02 */
+
+static const uint32_t ar5211Modes[][5] = {
+	{ 0x00000030, 0x00000015, 0x00000015, 0x0000001d, 0x00000015 },
+	{ 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x00001064, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f },
+	{ 0x00001070, 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 },
+	{ 0x00001030, 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 },
+	{ 0x000010b0, 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 },
+	{ 0x000010f0, 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 },
+	{ 0x00008014, 0x04000400, 0x08000800, 0x20003000, 0x04000400 },
+	{ 0x0000801c, 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 },
+	{ 0x00009804, 0x00000000, 0x00000003, 0x00000000, 0x00000000 },
+	{ 0x00009820, 0x02020200, 0x02020200, 0x02010200, 0x02020200 },
+	{ 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e },
+	{ 0x00009828, 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 },
+	{ 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+	{ 0x00009838, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b },
+	{ 0x00009844, 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c },
+	{ 0x00009848, 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 },
+	{ 0x00009850, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 },
+	{ 0x00009858, 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e },
+	{ 0x0000985c, 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e },
+	{ 0x00009860, 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 },
+	{ 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+	{ 0x00009914, 0x00002710, 0x00002710, 0x0000157c, 0x00002710 },
+	{ 0x00009918, 0x00000190, 0x00000190, 0x00000084, 0x00000190 },
+	{ 0x00009944, 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 },
+	{ 0x0000a180, 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff },
+	{ 0x000098d4, 0x00000010, 0x00000014, 0x00000010, 0x00000010 },
+};
+
+static const uint32_t ar5211Common[][2] = {
+	{ 0x0000000c, 0x00000000 },
+	{ 0x00000028, 0x84849c9c },
+	{ 0x0000002c, 0x7c7c7c7c },
+	{ 0x00000034, 0x00000005 },
+	{ 0x00000040, 0x00000000 },
+	{ 0x00000044, 0x00000008 },
+	{ 0x00000048, 0x00000008 },
+	{ 0x0000004c, 0x00000010 },
+	{ 0x00000050, 0x00000000 },
+	{ 0x00000054, 0x0000001f },
+	{ 0x00000800, 0x00000000 },
+	{ 0x00000804, 0x00000000 },
+	{ 0x00000808, 0x00000000 },
+	{ 0x0000080c, 0x00000000 },
+	{ 0x00000810, 0x00000000 },
+	{ 0x00000814, 0x00000000 },
+	{ 0x00000818, 0x00000000 },
+	{ 0x0000081c, 0x00000000 },
+	{ 0x00000820, 0x00000000 },
+	{ 0x00000824, 0x00000000 },
+	{ 0x00001230, 0x00000000 },
+	{ 0x00008004, 0x00000000 },
+	{ 0x00008008, 0x00000000 },
+	{ 0x0000800c, 0x00000000 },
+	{ 0x00008018, 0x00000000 },
+	{ 0x00008024, 0x00000000 },
+	{ 0x00008028, 0x00000030 },
+	{ 0x0000802c, 0x0007ffff },
+	{ 0x00008030, 0x01ffffff },
+	{ 0x00008034, 0x00000031 },
+	{ 0x00008038, 0x00000000 },
+	{ 0x0000803c, 0x00000000 },
+	{ 0x00008040, 0x00000000 },
+	{ 0x00008044, 0x00000002 },
+	{ 0x00008048, 0x00000000 },
+	{ 0x00008054, 0x00000000 },
+	{ 0x00008058, 0x00000000 },
+	{ 0x00009808, 0x00000000 },
+	{ 0x0000980c, 0x2d849093 },
+	{ 0x00009810, 0x7d32e000 },
+	{ 0x00009814, 0x00000f6b },
+	{ 0x0000981c, 0x00000000 },
+	{ 0x0000982c, 0x00026ffe },
+	{ 0x00009830, 0x00000000 },
+	{ 0x0000983c, 0x00020100 },
+	{ 0x00009840, 0x206a017a },
+	{ 0x0000984c, 0x1284613c },
+	{ 0x00009854, 0x00000859 },
+	{ 0x00009868, 0x409a4190 },
+	{ 0x0000986c, 0x050cb081 },
+	{ 0x00009870, 0x0000000f },
+	{ 0x00009874, 0x00000080 },
+	{ 0x00009878, 0x0000000c },
+	{ 0x00009900, 0x00000000 },
+	{ 0x00009904, 0x00000000 },
+	{ 0x00009908, 0x00000000 },
+	{ 0x0000990c, 0x00800000 },
+	{ 0x00009910, 0x00000001 },
+	{ 0x0000991c, 0x0000092a },
+	{ 0x00009920, 0x00000000 },
+	{ 0x00009924, 0x00058a05 },
+	{ 0x00009928, 0x00000001 },
+	{ 0x0000992c, 0x00000000 },
+	{ 0x00009930, 0x00000000 },
+	{ 0x00009934, 0x00000000 },
+	{ 0x00009938, 0x00000000 },
+	{ 0x0000993c, 0x0000003f },
+	{ 0x00009940, 0x00000004 },
+	{ 0x00009948, 0x00000000 },
+	{ 0x0000994c, 0x00000000 },
+	{ 0x00009950, 0x00000000 },
+	{ 0x00009954, 0x5d50f14c },
+	{ 0x00009958, 0x00000018 },
+	{ 0x0000995c, 0x004b6a8e },
+	{ 0x0000a184, 0x06ff05ff },
+	{ 0x0000a188, 0x07ff07ff },
+	{ 0x0000a18c, 0x08ff08ff },
+	{ 0x0000a190, 0x09ff09ff },
+	{ 0x0000a194, 0x0aff0aff },
+	{ 0x0000a198, 0x0bff0bff },
+	{ 0x0000a19c, 0x0cff0cff },
+	{ 0x0000a1a0, 0x0dff0dff },
+	{ 0x0000a1a4, 0x0fff0eff },
+	{ 0x0000a1a8, 0x12ff12ff },
+	{ 0x0000a1ac, 0x14ff13ff },
+	{ 0x0000a1b0, 0x16ff15ff },
+	{ 0x0000a1b4, 0x19ff17ff },
+	{ 0x0000a1b8, 0x1bff1aff },
+	{ 0x0000a1bc, 0x1eff1dff },
+	{ 0x0000a1c0, 0x23ff20ff },
+	{ 0x0000a1c4, 0x27ff25ff },
+	{ 0x0000a1c8, 0x2cff29ff },
+	{ 0x0000a1cc, 0x31ff2fff },
+	{ 0x0000a1d0, 0x37ff34ff },
+	{ 0x0000a1d4, 0x3aff3aff },
+	{ 0x0000a1d8, 0x3aff3aff },
+	{ 0x0000a1dc, 0x3aff3aff },
+	{ 0x0000a1e0, 0x3aff3aff },
+	{ 0x0000a1e4, 0x3aff3aff },
+	{ 0x0000a1e8, 0x3aff3aff },
+	{ 0x0000a1ec, 0x3aff3aff },
+	{ 0x0000a1f0, 0x3aff3aff },
+	{ 0x0000a1f4, 0x3aff3aff },
+	{ 0x0000a1f8, 0x3aff3aff },
+	{ 0x0000a1fc, 0x3aff3aff },
+	{ 0x00009b00, 0x00000000 },
+	{ 0x00009b04, 0x00000020 },
+	{ 0x00009b08, 0x00000010 },
+	{ 0x00009b0c, 0x00000030 },
+	{ 0x00009b10, 0x00000008 },
+	{ 0x00009b14, 0x00000028 },
+	{ 0x00009b18, 0x00000004 },
+	{ 0x00009b1c, 0x00000024 },
+	{ 0x00009b20, 0x00000014 },
+	{ 0x00009b24, 0x00000034 },
+	{ 0x00009b28, 0x0000000c },
+	{ 0x00009b2c, 0x0000002c },
+	{ 0x00009b30, 0x00000002 },
+	{ 0x00009b34, 0x00000022 },
+	{ 0x00009b38, 0x00000012 },
+	{ 0x00009b3c, 0x00000032 },
+	{ 0x00009b40, 0x0000000a },
+	{ 0x00009b44, 0x0000002a },
+	{ 0x00009b48, 0x00000006 },
+	{ 0x00009b4c, 0x00000026 },
+	{ 0x00009b50, 0x00000016 },
+	{ 0x00009b54, 0x00000036 },
+	{ 0x00009b58, 0x0000000e },
+	{ 0x00009b5c, 0x0000002e },
+	{ 0x00009b60, 0x00000001 },
+	{ 0x00009b64, 0x00000021 },
+	{ 0x00009b68, 0x00000011 },
+	{ 0x00009b6c, 0x00000031 },
+	{ 0x00009b70, 0x00000009 },
+	{ 0x00009b74, 0x00000029 },
+	{ 0x00009b78, 0x00000005 },
+	{ 0x00009b7c, 0x00000025 },
+	{ 0x00009b80, 0x00000015 },
+	{ 0x00009b84, 0x00000035 },
+	{ 0x00009b88, 0x0000000d },
+	{ 0x00009b8c, 0x0000002d },
+	{ 0x00009b90, 0x00000003 },
+	{ 0x00009b94, 0x00000023 },
+	{ 0x00009b98, 0x00000013 },
+	{ 0x00009b9c, 0x00000033 },
+	{ 0x00009ba0, 0x0000000b },
+	{ 0x00009ba4, 0x0000002b },
+	{ 0x00009ba8, 0x0000002b },
+	{ 0x00009bac, 0x0000002b },
+	{ 0x00009bb0, 0x0000002b },
+	{ 0x00009bb4, 0x0000002b },
+	{ 0x00009bb8, 0x0000002b },
+	{ 0x00009bbc, 0x0000002b },
+	{ 0x00009bc0, 0x0000002b },
+	{ 0x00009bc4, 0x0000002b },
+	{ 0x00009bc8, 0x0000002b },
+	{ 0x00009bcc, 0x0000002b },
+	{ 0x00009bd0, 0x0000002b },
+	{ 0x00009bd4, 0x0000002b },
+	{ 0x00009bd8, 0x0000002b },
+	{ 0x00009bdc, 0x0000002b },
+	{ 0x00009be0, 0x0000002b },
+	{ 0x00009be4, 0x0000002b },
+	{ 0x00009be8, 0x0000002b },
+	{ 0x00009bec, 0x0000002b },
+	{ 0x00009bf0, 0x0000002b },
+	{ 0x00009bf4, 0x0000002b },
+	{ 0x00009bf8, 0x00000002 },
+	{ 0x00009bfc, 0x00000016 },
+	{ 0x000098d4, 0x00000020 },
+	{ 0x000098d8, 0x00601068 },
+};
+
+static uint32_t ar5211Mode2_4[][3] = {
+	{ 0x0000a204, 0x00000000, 0x00000000 },
+	{ 0x0000a208, 0x503e4646, 0x503e4646 },
+	{ 0x0000a20c, 0x6480416c, 0x6480416c },
+	{ 0x0000a210, 0x0199a003, 0x0199a003 },
+	{ 0x0000a214, 0x044cd610, 0x044cd610 },
+	{ 0x0000a218, 0x13800040, 0x13800040 },
+	{ 0x0000a21c, 0x1be00060, 0x1be00060 },
+	{ 0x0000a220, 0x0c53800a, 0x0c53800a },
+	{ 0x0000a224, 0x0014df3b, 0x0014df3b },
+	{ 0x0000a228, 0x000001b5, 0x000001b5 },
+	{ 0x0000a22c, 0x00000020, 0x00000020 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00380000, 0x00380000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x000400f9, 0x000400f9 },
+	{ 0x000098d4, 0x00000000, 0x00000004 },
+};
+
+static const uint32_t ar5211BB_RfGain[][3] = {
+	{ 0x00009a00, 0x000001a9, 0x00000000 },
+	{ 0x00009a04, 0x000001e9, 0x00000040 },
+	{ 0x00009a08, 0x00000029, 0x00000080 },
+	{ 0x00009a0c, 0x00000069, 0x00000150 },
+	{ 0x00009a10, 0x00000199, 0x00000190 },
+	{ 0x00009a14, 0x000001d9, 0x000001d0 },
+	{ 0x00009a18, 0x00000019, 0x00000010 },
+	{ 0x00009a1c, 0x00000059, 0x00000044 },
+	{ 0x00009a20, 0x00000099, 0x00000084 },
+	{ 0x00009a24, 0x000001a5, 0x00000148 },
+	{ 0x00009a28, 0x000001e5, 0x00000188 },
+	{ 0x00009a2c, 0x00000025, 0x000001c8 },
+	{ 0x00009a30, 0x000001c8, 0x00000014 },
+	{ 0x00009a34, 0x00000008, 0x00000042 },
+	{ 0x00009a38, 0x00000048, 0x00000082 },
+	{ 0x00009a3c, 0x00000088, 0x00000178 },
+	{ 0x00009a40, 0x00000198, 0x000001b8 },
+	{ 0x00009a44, 0x000001d8, 0x000001f8 },
+	{ 0x00009a48, 0x00000018, 0x00000012 },
+	{ 0x00009a4c, 0x00000058, 0x00000052 },
+	{ 0x00009a50, 0x00000098, 0x00000092 },
+	{ 0x00009a54, 0x000001a4, 0x0000017c },
+	{ 0x00009a58, 0x000001e4, 0x000001bc },
+	{ 0x00009a5c, 0x00000024, 0x000001fc },
+	{ 0x00009a60, 0x00000064, 0x0000000a },
+	{ 0x00009a64, 0x000000a4, 0x0000004a },
+	{ 0x00009a68, 0x000000e4, 0x0000008a },
+	{ 0x00009a6c, 0x0000010a, 0x0000015a },
+	{ 0x00009a70, 0x0000014a, 0x0000019a },
+	{ 0x00009a74, 0x0000018a, 0x000001da },
+	{ 0x00009a78, 0x000001ca, 0x0000000e },
+	{ 0x00009a7c, 0x0000000a, 0x0000004e },
+	{ 0x00009a80, 0x0000004a, 0x0000008e },
+	{ 0x00009a84, 0x0000008a, 0x0000015e },
+	{ 0x00009a88, 0x000001ba, 0x0000019e },
+	{ 0x00009a8c, 0x000001fa, 0x000001de },
+	{ 0x00009a90, 0x0000003a, 0x00000009 },
+	{ 0x00009a94, 0x0000007a, 0x00000049 },
+	{ 0x00009a98, 0x00000186, 0x00000089 },
+	{ 0x00009a9c, 0x000001c6, 0x00000179 },
+	{ 0x00009aa0, 0x00000006, 0x000001b9 },
+	{ 0x00009aa4, 0x00000046, 0x000001f9 },
+	{ 0x00009aa8, 0x00000086, 0x00000039 },
+	{ 0x00009aac, 0x000000c6, 0x00000079 },
+	{ 0x00009ab0, 0x000000c6, 0x000000b9 },
+	{ 0x00009ab4, 0x000000c6, 0x000001bd },
+	{ 0x00009ab8, 0x000000c6, 0x000001fd },
+	{ 0x00009abc, 0x000000c6, 0x0000003d },
+	{ 0x00009ac0, 0x000000c6, 0x0000007d },
+	{ 0x00009ac4, 0x000000c6, 0x000000bd },
+	{ 0x00009ac8, 0x000000c6, 0x000000fd },
+	{ 0x00009acc, 0x000000c6, 0x000000fd },
+	{ 0x00009ad0, 0x000000c6, 0x000000fd },
+	{ 0x00009ad4, 0x000000c6, 0x000000fd },
+	{ 0x00009ad8, 0x000000c6, 0x000000fd },
+	{ 0x00009adc, 0x000000c6, 0x000000fd },
+	{ 0x00009ae0, 0x000000c6, 0x000000fd },
+	{ 0x00009ae4, 0x000000c6, 0x000000fd },
+	{ 0x00009ae8, 0x000000c6, 0x000000fd },
+	{ 0x00009aec, 0x000000c6, 0x000000fd },
+	{ 0x00009af0, 0x000000c6, 0x000000fd },
+	{ 0x00009af4, 0x000000c6, 0x000000fd },
+	{ 0x00009af8, 0x000000c6, 0x000000fd },
+	{ 0x00009afc, 0x000000c6, 0x000000fd },
+};
+
+static uint32_t ar5211Rf6n7[][3] = {
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x10000000, 0x10000000 },
+	{ 0x0000989c, 0x04000000, 0x04000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x00000000 },
+	{ 0x0000989c, 0x00000000, 0x0a000000 },
+	{ 0x0000989c, 0x00380080, 0x02380080 },
+	{ 0x0000989c, 0x00020006, 0x00000006 },
+	{ 0x0000989c, 0x00000092, 0x00000092 },
+	{ 0x0000989c, 0x000000a0, 0x000000a0 },
+	{ 0x0000989c, 0x00040007, 0x00040007 },
+	{ 0x000098d4, 0x0000001a, 0x0000001a },
+	{ 0x0000989c, 0x00000048, 0x00000048 },
+	{ 0x0000989c, 0x00000010, 0x00000010 },
+	{ 0x0000989c, 0x00000008, 0x00000008 },
+	{ 0x0000989c, 0x0000000f, 0x0000000f },
+	{ 0x0000989c, 0x000000f2, 0x00000062 },
+	{ 0x0000989c, 0x0000904f, 0x0000904c },
+	{ 0x0000989c, 0x0000125a, 0x0000129a },
+	{ 0x000098cc, 0x0000000e, 0x0000000f },
+};
+
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2316.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2316.c
new file mode 100644
index 0000000..c724a95
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2316.c
@@ -0,0 +1,767 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar2316.c,v 1.9 2008/11/15 22:15:46 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#include "ah_eeprom_v3.h"
+
+#define AH_5212_2316
+#include "ar5212/ar5212.ini"
+
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+
+typedef	RAW_DATA_STRUCT_2413 RAW_DATA_STRUCT_2316;
+typedef RAW_DATA_PER_CHANNEL_2413 RAW_DATA_PER_CHANNEL_2316;
+#define PWR_TABLE_SIZE_2316 PWR_TABLE_SIZE_2413
+
+struct ar2316State {
+	RF_HAL_FUNCS	base;		/* public state, must be first */
+	uint16_t	pcdacTable[PWR_TABLE_SIZE_2316];
+
+	uint32_t	Bank1Data[N(ar5212Bank1_2316)];
+	uint32_t	Bank2Data[N(ar5212Bank2_2316)];
+	uint32_t	Bank3Data[N(ar5212Bank3_2316)];
+	uint32_t	Bank6Data[N(ar5212Bank6_2316)];
+	uint32_t	Bank7Data[N(ar5212Bank7_2316)];
+
+	/*
+	 * Private state for reduced stack usage.
+	 */
+	/* filled out Vpd table for all pdGains (chanL) */
+	uint16_t vpdTable_L[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (chanR) */
+	uint16_t vpdTable_R[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (interpolated) */
+	uint16_t vpdTable_I[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+};
+#define	AR2316(ah)	((struct ar2316State *) AH5212(ah)->ah_rfHal)
+
+extern	void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+		uint32_t numBits, uint32_t firstBit, uint32_t column);
+
+static void
+ar2316WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+	int regWrites)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2316, modesIndex, regWrites);
+	HAL_INI_WRITE_ARRAY(ah, ar5212Common_2316, 1, regWrites);
+	HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2316, freqIndex, regWrites);
+
+	/* For AP51 */
+        if (!ahp->ah_cwCalRequire) {
+		OS_REG_WRITE(ah, 0xa358, (OS_REG_READ(ah, 0xa358) & ~0x2));
+        } else {
+		ahp->ah_cwCalRequire = AH_FALSE;
+        }
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ */
+static HAL_BOOL
+ar2316SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t channelSel  = 0;
+	uint32_t bModeSynth  = 0;
+	uint32_t aModeRefSel = 0;
+	uint32_t reg32       = 0;
+
+	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+
+	if (chan->channel < 4800) {
+		uint32_t txctl;
+
+		if (((chan->channel - 2192) % 5) == 0) {
+			channelSel = ((chan->channel - 672) * 2 - 3040)/10;
+			bModeSynth = 0;
+		} else if (((chan->channel - 2224) % 5) == 0) {
+			channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
+			bModeSynth = 1;
+		} else {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: invalid channel %u MHz\n",
+			    __func__, chan->channel);
+			return AH_FALSE;
+		}
+
+		channelSel = (channelSel << 2) & 0xff;
+		channelSel = ath_hal_reverseBits(channelSel, 8);
+
+		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+		if (chan->channel == 2484) {
+			/* Enable channel spreading for channel 14 */
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+		}
+	} else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 20 << 2), 8);
+		aModeRefSel = ath_hal_reverseBits(3, 2);
+	} else if ((chan->channel % 10) == 0) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 10 << 1), 8);
+		aModeRefSel = ath_hal_reverseBits(2, 2);
+	} else if ((chan->channel % 5) == 0) {
+		channelSel = ath_hal_reverseBits(
+			(chan->channel - 4800) / 5, 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
+		    __func__, chan->channel);
+		return AH_FALSE;
+	}
+
+	reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
+			(1 << 12) | 0x1;
+	OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
+
+	reg32 >>= 8;
+	OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ *
+ * REQUIRES: Access to the analog rf device
+ */
+static HAL_BOOL
+ar2316SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    \
+	int i;								    \
+	for (i = 0; i < N(ar5212Bank##_ix##_2316); i++)			    \
+		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2316[i][_col];\
+} while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t ob2GHz = 0, db2GHz = 0;
+	struct ar2316State *priv = AR2316(ah);
+	int regWrites = 0;
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+	    "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
+	    __func__, chan->channel, chan->channelFlags, modesIndex);
+
+	HALASSERT(priv != AH_NULL);
+
+	/* Setup rf parameters */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_B:
+		ob2GHz = ee->ee_obFor24;
+		db2GHz = ee->ee_dbFor24;
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		ob2GHz = ee->ee_obFor24g;
+		db2GHz = ee->ee_dbFor24g;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/* Bank 1 Write */
+	RF_BANK_SETUP(priv, 1, 1);
+
+	/* Bank 2 Write */
+	RF_BANK_SETUP(priv, 2, modesIndex);
+
+	/* Bank 3 Write */
+	RF_BANK_SETUP(priv, 3, modesIndex);
+
+	/* Bank 6 Write */
+	RF_BANK_SETUP(priv, 6, modesIndex);
+
+	ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz,   3, 178, 0);
+	ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz,   3, 175, 0);
+
+	/* Bank 7 Setup */
+	RF_BANK_SETUP(priv, 7, modesIndex);
+
+	/* Write Analog registers */
+	HAL_INI_WRITE_BANK(ah, ar5212Bank1_2316, priv->Bank1Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank2_2316, priv->Bank2Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank3_2316, priv->Bank3Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank6_2316, priv->Bank6Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank7_2316, priv->Bank7Data, regWrites);
+
+	/* Now that we have reprogrammed rfgain value, clear the flag. */
+	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+
+	return AH_TRUE;
+#undef	RF_BANK_SETUP
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar2316GetRfBank(struct ath_hal *ah, int bank)
+{
+	struct ar2316State *priv = AR2316(ah);
+
+	HALASSERT(priv != AH_NULL);
+	switch (bank) {
+	case 1: return priv->Bank1Data;
+	case 2: return priv->Bank2Data;
+	case 3: return priv->Bank3Data;
+	case 6: return priv->Bank6Data;
+	case 7: return priv->Bank7Data;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+	    __func__, bank);
+	return AH_NULL;
+}
+
+/*
+ * Return indices surrounding the value in sorted integer lists.
+ *
+ * NB: the input list is assumed to be sorted in ascending order
+ */
+static void
+GetLowerUpperIndex(int16_t v, const uint16_t *lp, uint16_t listSize,
+                          uint32_t *vlo, uint32_t *vhi)
+{
+	int16_t target = v;
+	const int16_t *ep = lp+listSize;
+	const int16_t *tp;
+
+	/*
+	 * Check first and last elements for out-of-bounds conditions.
+	 */
+	if (target < lp[0]) {
+		*vlo = *vhi = 0;
+		return;
+	}
+	if (target >= ep[-1]) {
+		*vlo = *vhi = listSize - 1;
+		return;
+	}
+
+	/* look for value being near or between 2 values in list */
+	for (tp = lp; tp < ep; tp++) {
+		/*
+		 * If value is close to the current value of the list
+		 * then target is not between values, it is one of the values
+		 */
+		if (*tp == target) {
+			*vlo = *vhi = tp - (const int16_t *) lp;
+			return;
+		}
+		/*
+		 * Look for value being between current value and next value
+		 * if so return these 2 values
+		 */
+		if (target < tp[1]) {
+			*vlo = tp - (const int16_t *) lp;
+			*vhi = *vlo + 1;
+			return;
+		}
+	}
+}
+
+/*
+ * Fill the Vpdlist for indices Pmax-Pmin
+ */
+static HAL_BOOL
+ar2316FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t  Pmax,
+		   const int16_t *pwrList, const int16_t *VpdList,
+		   uint16_t numIntercepts, uint16_t retVpdList[][64])
+{
+	uint16_t ii, jj, kk;
+	int16_t currPwr = (int16_t)(2*Pmin);
+	/* since Pmin is pwr*2 and pwrList is 4*pwr */
+	uint32_t  idxL, idxR;
+
+	ii = 0;
+	jj = 0;
+
+	if (numIntercepts < 2)
+		return AH_FALSE;
+
+	while (ii <= (uint16_t)(Pmax - Pmin)) {
+		GetLowerUpperIndex(currPwr, pwrList, numIntercepts, 
+					 &(idxL), &(idxR));
+		if (idxR < 1)
+			idxR = 1;			/* extrapolate below */
+		if (idxL == (uint32_t)(numIntercepts - 1))
+			idxL = numIntercepts - 2;	/* extrapolate above */
+		if (pwrList[idxL] == pwrList[idxR])
+			kk = VpdList[idxL];
+		else
+			kk = (uint16_t)
+				(((currPwr - pwrList[idxL])*VpdList[idxR]+ 
+				  (pwrList[idxR] - currPwr)*VpdList[idxL])/
+				 (pwrList[idxR] - pwrList[idxL]));
+		retVpdList[pdGainIdx][ii] = kk;
+		ii++;
+		currPwr += 2;				/* half dB steps */
+	}
+
+	return AH_TRUE;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+static int16_t
+interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+	int16_t targetLeft, int16_t targetRight)
+{
+	int16_t rv;
+
+	if (srcRight != srcLeft) {
+		rv = ((target - srcLeft)*targetRight +
+		      (srcRight - target)*targetLeft) / (srcRight - srcLeft);
+	} else {
+		rv = targetLeft;
+	}
+	return rv;
+}
+
+/*
+ * Uses the data points read from EEPROM to reconstruct the pdadc power table
+ * Called by ar2316SetPowerTable()
+ */
+static int 
+ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
+		const RAW_DATA_STRUCT_2316 *pRawDataset,
+		uint16_t pdGainOverlap_t2, 
+		int16_t  *pMinCalPower, uint16_t pPdGainBoundaries[], 
+		uint16_t pPdGainValues[], uint16_t pPDADCValues[]) 
+{
+	struct ar2316State *priv = AR2316(ah);
+#define	VpdTable_L	priv->vpdTable_L
+#define	VpdTable_R	priv->vpdTable_R
+#define	VpdTable_I	priv->vpdTable_I
+	uint32_t ii, jj, kk;
+	int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
+	uint32_t idxL, idxR;
+	uint32_t numPdGainsUsed = 0;
+	/* 
+	 * If desired to support -ve power levels in future, just
+	 * change pwr_I_0 to signed 5-bits.
+	 */
+	int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on. */
+	int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on */
+	uint16_t numVpd = 0;
+	uint16_t Vpd_step;
+	int16_t tmpVal ; 
+	uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;
+
+	/* Get upper lower index */
+	GetLowerUpperIndex(channel, pRawDataset->pChannels,
+				 pRawDataset->numChannels, &(idxL), &(idxR));
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;
+			Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];
+			if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {
+				Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];
+			}
+			Pmin_t2[numPdGainsUsed] = (int16_t)
+				(Pmin_t2[numPdGainsUsed] / 2);
+			Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])
+				Pmax_t2[numPdGainsUsed] = 
+					pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);
+			ar2316FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]), 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L
+					   );
+			ar2316FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R
+					   );
+			for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {
+				VpdTable_I[numPdGainsUsed][kk] = 
+					interpolate_signed(
+							   channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],
+							   (int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);
+			}
+			/* fill VpdTable_I for this pdGain */
+			numPdGainsUsed++;
+		}
+		/* if this pdGain is used */
+	}
+
+	*pMinCalPower = Pmin_t2[0];
+	kk = 0; /* index for the final table */
+	for (ii = 0; ii < numPdGainsUsed; ii++) {
+		if (ii == (numPdGainsUsed - 1))
+			pPdGainBoundaries[ii] = Pmax_t2[ii] +
+				PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;
+		else 
+			pPdGainBoundaries[ii] = (uint16_t)
+				((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );
+		if (pPdGainBoundaries[ii] > 63) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: clamp pPdGainBoundaries[%d] %d\n",
+			    __func__, ii, pPdGainBoundaries[ii]);/*XXX*/
+			pPdGainBoundaries[ii] = 63;
+		}
+
+		/* Find starting index for this pdGain */
+		if (ii == 0) 
+			ss = 0; /* for the first pdGain, start from index 0 */
+		else 
+			ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) - 
+				pdGainOverlap_t2;
+		Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
+		/*
+		 *-ve ss indicates need to extrapolate data below for this pdGain
+		 */
+		while (ss < 0) {
+			tmpVal = (int16_t)(VpdTable_I[ii][0] + ss*Vpd_step);
+			pPDADCValues[kk++] = (uint16_t)((tmpVal < 0) ? 0 : tmpVal);
+			ss++;
+		}
+
+		sizeCurrVpdTable = Pmax_t2[ii] - Pmin_t2[ii];
+		tgtIndex = pPdGainBoundaries[ii] + pdGainOverlap_t2 - Pmin_t2[ii];
+		maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
+
+		while (ss < (int16_t)maxIndex)
+			pPDADCValues[kk++] = VpdTable_I[ii][ss++];
+
+		Vpd_step = (uint16_t)(VpdTable_I[ii][sizeCurrVpdTable-1] -
+				       VpdTable_I[ii][sizeCurrVpdTable-2]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);           
+		/*
+		 * for last gain, pdGainBoundary == Pmax_t2, so will 
+		 * have to extrapolate
+		 */
+		if (tgtIndex > maxIndex) {	/* need to extrapolate above */
+			while(ss < (int16_t)tgtIndex) {
+				tmpVal = (uint16_t)
+					(VpdTable_I[ii][sizeCurrVpdTable-1] + 
+					 (ss-maxIndex)*Vpd_step);
+				pPDADCValues[kk++] = (tmpVal > 127) ? 
+					127 : tmpVal;
+				ss++;
+			}
+		}				/* extrapolated above */
+	}					/* for all pdGainUsed */
+
+	while (ii < MAX_NUM_PDGAINS_PER_CHANNEL) {
+		pPdGainBoundaries[ii] = pPdGainBoundaries[ii-1];
+		ii++;
+	}
+	while (kk < 128) {
+		pPDADCValues[kk] = pPDADCValues[kk-1];
+		kk++;
+	}
+
+	return numPdGainsUsed;
+#undef VpdTable_L
+#undef VpdTable_R
+#undef VpdTable_I
+}
+
+static HAL_BOOL
+ar2316SetPowerTable(struct ath_hal *ah,
+	int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan, 
+	uint16_t *rfXpdGain)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL;
+	uint16_t pdGainOverlap_t2;
+	int16_t minCalPower2316_t2;
+	uint16_t *pdadcValues = ahp->ah_pcdacTable;
+	uint16_t gainBoundaries[4];
+	uint32_t reg32, regoffset;
+	int i, numPdGainsUsed;
+#ifndef AH_USE_INIPDGAIN
+	uint32_t tpcrg1;
+#endif
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
+	    __func__, chan->channel,chan->channelFlags);
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
+		return AH_FALSE;
+	}
+
+	pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
+					  AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
+    
+	numPdGainsUsed = ar2316getGainBoundariesAndPdadcsForPowers(ah,
+		chan->channel, pRawDataset, pdGainOverlap_t2,
+		&minCalPower2316_t2,gainBoundaries, rfXpdGain, pdadcValues);
+	HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
+
+#ifdef AH_USE_INIPDGAIN
+	/*
+	 * Use pd_gains curve from eeprom; Atheros always uses
+	 * the default curve from the ini file but some vendors
+	 * (e.g. Zcomax) want to override this curve and not
+	 * honoring their settings results in tx power 5dBm low.
+	 */
+	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 
+			 (pRawDataset->pDataPerChannel[0].numPdGains - 1));
+#else
+	tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);
+	tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)
+		  | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
+	switch (numPdGainsUsed) {
+	case 3:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;
+		tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
+		/* fall thru... */
+	case 2:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;
+		tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
+		/* fall thru... */
+	case 1:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;
+		tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
+		break;
+	}
+#ifdef AH_DEBUG
+	if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "
+		    "pd_gains (default 0x%x, calculated 0x%x)\n",
+		    __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);
+#endif
+	OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);
+#endif
+
+	/*
+	 * Note the pdadc table may not start at 0 dBm power, could be
+	 * negative or greater than 0.  Need to offset the power
+	 * values by the amount of minPower for griffin
+	 */
+	if (minCalPower2316_t2 != 0)
+		ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2316_t2);
+	else
+		ahp->ah_txPowerIndexOffset = 0;
+
+	/* Finally, write the power values into the baseband power table */
+	regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
+	for (i = 0; i < 32; i++) {
+		reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0)  | 
+			((pdadcValues[4*i + 1] & 0xFF) << 8)  |
+			((pdadcValues[4*i + 2] & 0xFF) << 16) |
+			((pdadcValues[4*i + 3] & 0xFF) << 24) ;        
+		OS_REG_WRITE(ah, regoffset, reg32);
+		regoffset += 4;
+	}
+
+	OS_REG_WRITE(ah, AR_PHY_TPCRG5, 
+		     SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 
+		     SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
+		     SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
+		     SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
+		     SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
+
+	return AH_TRUE;
+}
+
+static int16_t
+ar2316GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2316 *data)
+{
+	uint32_t ii,jj;
+	uint16_t Pmin=0,numVpd;
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = data->pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			Pmin = data->pDataPerPDGain[jj].pwr_t4[0];
+			return(Pmin);
+		}
+	}
+	return(Pmin);
+}
+
+static int16_t
+ar2316GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2316 *data)
+{
+	uint32_t ii;
+	uint16_t Pmax=0,numVpd;
+	
+	for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		/* work forwards cuase lowest pdGain for highest power */
+		numVpd = data->pDataPerPDGain[ii].numVpd;
+		if (numVpd > 0) {
+			Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
+			return(Pmax);
+		}
+	}
+	return(Pmax);
+}
+
+static HAL_BOOL
+ar2316GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+	int16_t *maxPow, int16_t *minPow)
+{
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2316 *pRawDataset = AH_NULL;
+	const RAW_DATA_PER_CHANNEL_2316 *data=AH_NULL;
+	uint16_t numChannels;
+	int totalD,totalF, totalMin,last, i;
+
+	*maxPow = 0;
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else
+		return(AH_FALSE);
+
+	numChannels = pRawDataset->numChannels;
+	data = pRawDataset->pDataPerChannel;
+	
+	/* Make sure the channel is in the range of the TP values 
+	 *  (freq piers)
+	 */
+	if (numChannels < 1)
+		return(AH_FALSE);
+
+	if ((chan->channel < data[0].channelValue) ||
+	    (chan->channel > data[numChannels-1].channelValue)) {
+		if (chan->channel < data[0].channelValue) {
+			*maxPow = ar2316GetMaxPower(ah, &data[0]);
+			*minPow = ar2316GetMinPower(ah, &data[0]);
+			return(AH_TRUE);
+		} else {
+			*maxPow = ar2316GetMaxPower(ah, &data[numChannels - 1]);
+			*minPow = ar2316GetMinPower(ah, &data[numChannels - 1]);
+			return(AH_TRUE);
+		}
+	}
+
+	/* Linearly interpolate the power value now */
+	for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+	     last = i++);
+	totalD = data[i].channelValue - data[last].channelValue;
+	if (totalD > 0) {
+		totalF = ar2316GetMaxPower(ah, &data[i]) - ar2316GetMaxPower(ah, &data[last]);
+		*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + 
+				     ar2316GetMaxPower(ah, &data[last])*totalD)/totalD);
+		totalMin = ar2316GetMinPower(ah, &data[i]) - ar2316GetMinPower(ah, &data[last]);
+		*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+				     ar2316GetMinPower(ah, &data[last])*totalD)/totalD);
+		return(AH_TRUE);
+	} else {
+		if (chan->channel == data[i].channelValue) {
+			*maxPow = ar2316GetMaxPower(ah, &data[i]);
+			*minPow = ar2316GetMinPower(ah, &data[i]);
+			return(AH_TRUE);
+		} else
+			return(AH_FALSE);
+	}
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar2316RfDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(ahp->ah_rfHal != AH_NULL);
+	ath_hal_free(ahp->ah_rfHal);
+	ahp->ah_rfHal = AH_NULL;
+}
+
+/*
+ * Allocate memory for private state.
+ * Scratch Buffer will be reinitialized every reset so no need to zero now
+ */
+static HAL_BOOL
+ar2316RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar2316State *priv;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	HALASSERT(ahp->ah_rfHal == AH_NULL);
+	priv = ath_hal_malloc(sizeof(struct ar2316State));
+	if (priv == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot allocate private state\n", __func__);
+		*status = HAL_ENOMEM;		/* XXX */
+		return AH_FALSE;
+	}
+	priv->base.rfDetach		= ar2316RfDetach;
+	priv->base.writeRegs		= ar2316WriteRegs;
+	priv->base.getRfBank		= ar2316GetRfBank;
+	priv->base.setChannel		= ar2316SetChannel;
+	priv->base.setRfRegs		= ar2316SetRfRegs;
+	priv->base.setPowerTable	= ar2316SetPowerTable;
+	priv->base.getChannelMaxMinPower = ar2316GetChannelMaxMinPower;
+	priv->base.getNfAdjust		= ar5212GetNfAdjust;
+
+	ahp->ah_pcdacTable = priv->pcdacTable;
+	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+	ahp->ah_rfHal = &priv->base;
+
+	ahp->ah_cwCalRequire = AH_TRUE;		/* force initial cal */
+
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+ar2316Probe(struct ath_hal *ah)
+{
+	return IS_2316(ah);
+}
+AH_RF(RF2316, ar2316Probe, ar2316RfAttach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2317.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2317.c
new file mode 100644
index 0000000..c83cff0
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2317.c
@@ -0,0 +1,744 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar2317.c,v 1.8 2008/11/15 22:15:46 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#include "ah_eeprom_v3.h"
+
+#define AH_5212_2317
+#include "ar5212/ar5212.ini"
+
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+
+typedef	RAW_DATA_STRUCT_2413 RAW_DATA_STRUCT_2317;
+typedef RAW_DATA_PER_CHANNEL_2413 RAW_DATA_PER_CHANNEL_2317;
+#define PWR_TABLE_SIZE_2317 PWR_TABLE_SIZE_2413
+
+struct ar2317State {
+	RF_HAL_FUNCS	base;		/* public state, must be first */
+	uint16_t	pcdacTable[PWR_TABLE_SIZE_2317];
+
+	uint32_t	Bank1Data[N(ar5212Bank1_2317)];
+	uint32_t	Bank2Data[N(ar5212Bank2_2317)];
+	uint32_t	Bank3Data[N(ar5212Bank3_2317)];
+	uint32_t	Bank6Data[N(ar5212Bank6_2317)];
+	uint32_t	Bank7Data[N(ar5212Bank7_2317)];
+
+	/*
+	 * Private state for reduced stack usage.
+	 */
+	/* filled out Vpd table for all pdGains (chanL) */
+	uint16_t vpdTable_L[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (chanR) */
+	uint16_t vpdTable_R[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (interpolated) */
+	uint16_t vpdTable_I[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+};
+#define	AR2317(ah)	((struct ar2317State *) AH5212(ah)->ah_rfHal)
+
+extern	void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+		uint32_t numBits, uint32_t firstBit, uint32_t column);
+
+static void
+ar2317WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+	int writes)
+{
+	HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2317, modesIndex, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212Common_2317, 1, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2317, freqIndex, writes);
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ */
+static HAL_BOOL
+ar2317SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t channelSel  = 0;
+	uint32_t bModeSynth  = 0;
+	uint32_t aModeRefSel = 0;
+	uint32_t reg32       = 0;
+
+	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+
+	if (chan->channel < 4800) {
+		uint32_t txctl;
+		channelSel = chan->channel - 2272 ;
+		channelSel = ath_hal_reverseBits(channelSel, 8);
+
+		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+		if (chan->channel == 2484) {
+			/* Enable channel spreading for channel 14 */
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+		}
+	} else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 20 << 2), 8);
+		aModeRefSel = ath_hal_reverseBits(3, 2);
+	} else if ((chan->channel % 10) == 0) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 10 << 1), 8);
+		aModeRefSel = ath_hal_reverseBits(2, 2);
+	} else if ((chan->channel % 5) == 0) {
+		channelSel = ath_hal_reverseBits(
+			(chan->channel - 4800) / 5, 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
+		    __func__, chan->channel);
+		return AH_FALSE;
+	}
+
+	reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
+			(1 << 12) | 0x1;
+	OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
+
+	reg32 >>= 8;
+	OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ *
+ * REQUIRES: Access to the analog rf device
+ */
+static HAL_BOOL
+ar2317SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    \
+	int i;								    \
+	for (i = 0; i < N(ar5212Bank##_ix##_2317); i++)			    \
+		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2317[i][_col];\
+} while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t ob2GHz = 0, db2GHz = 0;
+	struct ar2317State *priv = AR2317(ah);
+	int regWrites = 0;
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+	    "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
+	    __func__, chan->channel, chan->channelFlags, modesIndex);
+
+	HALASSERT(priv);
+
+	/* Setup rf parameters */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_B:
+		ob2GHz = ee->ee_obFor24;
+		db2GHz = ee->ee_dbFor24;
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		ob2GHz = ee->ee_obFor24g;
+		db2GHz = ee->ee_dbFor24g;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/* Bank 1 Write */
+	RF_BANK_SETUP(priv, 1, 1);
+
+	/* Bank 2 Write */
+	RF_BANK_SETUP(priv, 2, modesIndex);
+
+	/* Bank 3 Write */
+	RF_BANK_SETUP(priv, 3, modesIndex);
+
+	/* Bank 6 Write */
+	RF_BANK_SETUP(priv, 6, modesIndex);
+
+	ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz,   3, 193, 0);
+	ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz,   3, 190, 0);
+
+	/* Bank 7 Setup */
+	RF_BANK_SETUP(priv, 7, modesIndex);
+
+	/* Write Analog registers */
+	HAL_INI_WRITE_BANK(ah, ar5212Bank1_2317, priv->Bank1Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank2_2317, priv->Bank2Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank3_2317, priv->Bank3Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank6_2317, priv->Bank6Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank7_2317, priv->Bank7Data, regWrites);	
+	/* Now that we have reprogrammed rfgain value, clear the flag. */
+	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+
+	return AH_TRUE;
+#undef	RF_BANK_SETUP
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar2317GetRfBank(struct ath_hal *ah, int bank)
+{
+	struct ar2317State *priv = AR2317(ah);
+
+	HALASSERT(priv != AH_NULL);
+	switch (bank) {
+	case 1: return priv->Bank1Data;
+	case 2: return priv->Bank2Data;
+	case 3: return priv->Bank3Data;
+	case 6: return priv->Bank6Data;
+	case 7: return priv->Bank7Data;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+	    __func__, bank);
+	return AH_NULL;
+}
+
+/*
+ * Return indices surrounding the value in sorted integer lists.
+ *
+ * NB: the input list is assumed to be sorted in ascending order
+ */
+static void
+GetLowerUpperIndex(int16_t v, const uint16_t *lp, uint16_t listSize,
+                          uint32_t *vlo, uint32_t *vhi)
+{
+	int16_t target = v;
+	const int16_t *ep = lp+listSize;
+	const int16_t *tp;
+
+	/*
+	 * Check first and last elements for out-of-bounds conditions.
+	 */
+	if (target < lp[0]) {
+		*vlo = *vhi = 0;
+		return;
+	}
+	if (target >= ep[-1]) {
+		*vlo = *vhi = listSize - 1;
+		return;
+	}
+
+	/* look for value being near or between 2 values in list */
+	for (tp = lp; tp < ep; tp++) {
+		/*
+		 * If value is close to the current value of the list
+		 * then target is not between values, it is one of the values
+		 */
+		if (*tp == target) {
+			*vlo = *vhi = tp - (const int16_t *) lp;
+			return;
+		}
+		/*
+		 * Look for value being between current value and next value
+		 * if so return these 2 values
+		 */
+		if (target < tp[1]) {
+			*vlo = tp - (const int16_t *) lp;
+			*vhi = *vlo + 1;
+			return;
+		}
+	}
+}
+
+/*
+ * Fill the Vpdlist for indices Pmax-Pmin
+ */
+static HAL_BOOL
+ar2317FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t  Pmax,
+		   const int16_t *pwrList, const int16_t *VpdList,
+		   uint16_t numIntercepts, uint16_t retVpdList[][64])
+{
+	uint16_t ii, jj, kk;
+	int16_t currPwr = (int16_t)(2*Pmin);
+	/* since Pmin is pwr*2 and pwrList is 4*pwr */
+	uint32_t  idxL, idxR;
+
+	ii = 0;
+	jj = 0;
+
+	if (numIntercepts < 2)
+		return AH_FALSE;
+
+	while (ii <= (uint16_t)(Pmax - Pmin)) {
+		GetLowerUpperIndex(currPwr, pwrList, numIntercepts, 
+					 &(idxL), &(idxR));
+		if (idxR < 1)
+			idxR = 1;			/* extrapolate below */
+		if (idxL == (uint32_t)(numIntercepts - 1))
+			idxL = numIntercepts - 2;	/* extrapolate above */
+		if (pwrList[idxL] == pwrList[idxR])
+			kk = VpdList[idxL];
+		else
+			kk = (uint16_t)
+				(((currPwr - pwrList[idxL])*VpdList[idxR]+ 
+				  (pwrList[idxR] - currPwr)*VpdList[idxL])/
+				 (pwrList[idxR] - pwrList[idxL]));
+		retVpdList[pdGainIdx][ii] = kk;
+		ii++;
+		currPwr += 2;				/* half dB steps */
+	}
+
+	return AH_TRUE;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+static int16_t
+interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+	int16_t targetLeft, int16_t targetRight)
+{
+	int16_t rv;
+
+	if (srcRight != srcLeft) {
+		rv = ((target - srcLeft)*targetRight +
+		      (srcRight - target)*targetLeft) / (srcRight - srcLeft);
+	} else {
+		rv = targetLeft;
+	}
+	return rv;
+}
+
+/*
+ * Uses the data points read from EEPROM to reconstruct the pdadc power table
+ * Called by ar2317SetPowerTable()
+ */
+static int 
+ar2317getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
+		const RAW_DATA_STRUCT_2317 *pRawDataset,
+		uint16_t pdGainOverlap_t2, 
+		int16_t  *pMinCalPower, uint16_t pPdGainBoundaries[], 
+		uint16_t pPdGainValues[], uint16_t pPDADCValues[]) 
+{
+	struct ar2317State *priv = AR2317(ah);
+#define	VpdTable_L	priv->vpdTable_L
+#define	VpdTable_R	priv->vpdTable_R
+#define	VpdTable_I	priv->vpdTable_I
+	/* XXX excessive stack usage? */
+	uint32_t ii, jj, kk;
+	int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
+	uint32_t idxL, idxR;
+	uint32_t numPdGainsUsed = 0;
+	/* 
+	 * If desired to support -ve power levels in future, just
+	 * change pwr_I_0 to signed 5-bits.
+	 */
+	int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on. */
+	int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on */
+	uint16_t numVpd = 0;
+	uint16_t Vpd_step;
+	int16_t tmpVal ; 
+	uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;
+
+	/* Get upper lower index */
+	GetLowerUpperIndex(channel, pRawDataset->pChannels,
+				 pRawDataset->numChannels, &(idxL), &(idxR));
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;
+			Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];
+			if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {
+				Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];
+			}
+			Pmin_t2[numPdGainsUsed] = (int16_t)
+				(Pmin_t2[numPdGainsUsed] / 2);
+			Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])
+				Pmax_t2[numPdGainsUsed] = 
+					pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);
+			ar2317FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]), 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L
+					   );
+			ar2317FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R
+					   );
+			for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {
+				VpdTable_I[numPdGainsUsed][kk] = 
+					interpolate_signed(
+							   channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],
+							   (int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);
+			}
+			/* fill VpdTable_I for this pdGain */
+			numPdGainsUsed++;
+		}
+		/* if this pdGain is used */
+	}
+
+	*pMinCalPower = Pmin_t2[0];
+	kk = 0; /* index for the final table */
+	for (ii = 0; ii < numPdGainsUsed; ii++) {
+		if (ii == (numPdGainsUsed - 1))
+			pPdGainBoundaries[ii] = Pmax_t2[ii] +
+				PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;
+		else 
+			pPdGainBoundaries[ii] = (uint16_t)
+				((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );
+		if (pPdGainBoundaries[ii] > 63) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: clamp pPdGainBoundaries[%d] %d\n",
+			   __func__, ii, pPdGainBoundaries[ii]);/*XXX*/
+			pPdGainBoundaries[ii] = 63;
+		}
+
+		/* Find starting index for this pdGain */
+		if (ii == 0) 
+			ss = 0; /* for the first pdGain, start from index 0 */
+		else 
+			ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) - 
+				pdGainOverlap_t2;
+		Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
+		/*
+		 *-ve ss indicates need to extrapolate data below for this pdGain
+		 */
+		while (ss < 0) {
+			tmpVal = (int16_t)(VpdTable_I[ii][0] + ss*Vpd_step);
+			pPDADCValues[kk++] = (uint16_t)((tmpVal < 0) ? 0 : tmpVal);
+			ss++;
+		}
+
+		sizeCurrVpdTable = Pmax_t2[ii] - Pmin_t2[ii];
+		tgtIndex = pPdGainBoundaries[ii] + pdGainOverlap_t2 - Pmin_t2[ii];
+		maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
+
+		while (ss < (int16_t)maxIndex)
+			pPDADCValues[kk++] = VpdTable_I[ii][ss++];
+
+		Vpd_step = (uint16_t)(VpdTable_I[ii][sizeCurrVpdTable-1] -
+				       VpdTable_I[ii][sizeCurrVpdTable-2]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);           
+		/*
+		 * for last gain, pdGainBoundary == Pmax_t2, so will 
+		 * have to extrapolate
+		 */
+		if (tgtIndex > maxIndex) {	/* need to extrapolate above */
+			while(ss < (int16_t)tgtIndex) {
+				tmpVal = (uint16_t)
+					(VpdTable_I[ii][sizeCurrVpdTable-1] + 
+					 (ss-maxIndex)*Vpd_step);
+				pPDADCValues[kk++] = (tmpVal > 127) ? 
+					127 : tmpVal;
+				ss++;
+			}
+		}				/* extrapolated above */
+	}					/* for all pdGainUsed */
+
+	while (ii < MAX_NUM_PDGAINS_PER_CHANNEL) {
+		pPdGainBoundaries[ii] = pPdGainBoundaries[ii-1];
+		ii++;
+	}
+	while (kk < 128) {
+		pPDADCValues[kk] = pPDADCValues[kk-1];
+		kk++;
+	}
+
+	return numPdGainsUsed;
+#undef VpdTable_L
+#undef VpdTable_R
+#undef VpdTable_I
+}
+
+static HAL_BOOL
+ar2317SetPowerTable(struct ath_hal *ah,
+	int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan, 
+	uint16_t *rfXpdGain)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2317 *pRawDataset = AH_NULL;
+	uint16_t pdGainOverlap_t2;
+	int16_t minCalPower2317_t2;
+	uint16_t *pdadcValues = ahp->ah_pcdacTable;
+	uint16_t gainBoundaries[4];
+	uint32_t reg32, regoffset;
+	int i, numPdGainsUsed;
+#ifndef AH_USE_INIPDGAIN
+	uint32_t tpcrg1;
+#endif
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
+	    __func__, chan->channel,chan->channelFlags);
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
+		return AH_FALSE;
+	}
+
+	pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
+					  AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
+    
+	numPdGainsUsed = ar2317getGainBoundariesAndPdadcsForPowers(ah,
+		chan->channel, pRawDataset, pdGainOverlap_t2,
+		&minCalPower2317_t2,gainBoundaries, rfXpdGain, pdadcValues);
+	HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
+
+#ifdef AH_USE_INIPDGAIN
+	/*
+	 * Use pd_gains curve from eeprom; Atheros always uses
+	 * the default curve from the ini file but some vendors
+	 * (e.g. Zcomax) want to override this curve and not
+	 * honoring their settings results in tx power 5dBm low.
+	 */
+	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 
+			 (pRawDataset->pDataPerChannel[0].numPdGains - 1));
+#else
+	tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);
+	tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)
+		  | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
+	switch (numPdGainsUsed) {
+	case 3:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;
+		tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
+		/* fall thru... */
+	case 2:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;
+		tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
+		/* fall thru... */
+	case 1:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;
+		tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
+		break;
+	}
+#ifdef AH_DEBUG
+	if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "
+		    "pd_gains (default 0x%x, calculated 0x%x)\n",
+		    __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);
+#endif
+	OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);
+#endif
+
+	/*
+	 * Note the pdadc table may not start at 0 dBm power, could be
+	 * negative or greater than 0.  Need to offset the power
+	 * values by the amount of minPower for griffin
+	 */
+	if (minCalPower2317_t2 != 0)
+		ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2317_t2);
+	else
+		ahp->ah_txPowerIndexOffset = 0;
+
+	/* Finally, write the power values into the baseband power table */
+	regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
+	for (i = 0; i < 32; i++) {
+		reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0)  | 
+			((pdadcValues[4*i + 1] & 0xFF) << 8)  |
+			((pdadcValues[4*i + 2] & 0xFF) << 16) |
+			((pdadcValues[4*i + 3] & 0xFF) << 24) ;        
+		OS_REG_WRITE(ah, regoffset, reg32);
+		regoffset += 4;
+	}
+
+	OS_REG_WRITE(ah, AR_PHY_TPCRG5, 
+		     SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 
+		     SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
+		     SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
+		     SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
+		     SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
+
+	return AH_TRUE;
+}
+
+static int16_t
+ar2317GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2317 *data)
+{
+	uint32_t ii,jj;
+	uint16_t Pmin=0,numVpd;
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = data->pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			Pmin = data->pDataPerPDGain[jj].pwr_t4[0];
+			return(Pmin);
+		}
+	}
+	return(Pmin);
+}
+
+static int16_t
+ar2317GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2317 *data)
+{
+	uint32_t ii;
+	uint16_t Pmax=0,numVpd;
+	uint16_t vpdmax;
+	
+	for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		/* work forwards cuase lowest pdGain for highest power */
+		numVpd = data->pDataPerPDGain[ii].numVpd;
+		if (numVpd > 0) {
+			Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
+			vpdmax = data->pDataPerPDGain[ii].Vpd[numVpd-1];
+			return(Pmax);
+		}
+	}
+	return(Pmax);
+}
+
+static HAL_BOOL
+ar2317GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+	int16_t *maxPow, int16_t *minPow)
+{
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2317 *pRawDataset = AH_NULL;
+	const RAW_DATA_PER_CHANNEL_2317 *data=AH_NULL;
+	uint16_t numChannels;
+	int totalD,totalF, totalMin,last, i;
+
+	*maxPow = 0;
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else
+		return(AH_FALSE);
+
+	numChannels = pRawDataset->numChannels;
+	data = pRawDataset->pDataPerChannel;
+	
+	/* Make sure the channel is in the range of the TP values 
+	 *  (freq piers)
+	 */
+	if (numChannels < 1)
+		return(AH_FALSE);
+
+	if ((chan->channel < data[0].channelValue) ||
+	    (chan->channel > data[numChannels-1].channelValue)) {
+		if (chan->channel < data[0].channelValue) {
+			*maxPow = ar2317GetMaxPower(ah, &data[0]);
+			*minPow = ar2317GetMinPower(ah, &data[0]);
+			return(AH_TRUE);
+		} else {
+			*maxPow = ar2317GetMaxPower(ah, &data[numChannels - 1]);
+			*minPow = ar2317GetMinPower(ah, &data[numChannels - 1]);
+			return(AH_TRUE);
+		}
+	}
+
+	/* Linearly interpolate the power value now */
+	for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+	     last = i++);
+	totalD = data[i].channelValue - data[last].channelValue;
+	if (totalD > 0) {
+		totalF = ar2317GetMaxPower(ah, &data[i]) - ar2317GetMaxPower(ah, &data[last]);
+		*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + 
+				     ar2317GetMaxPower(ah, &data[last])*totalD)/totalD);
+		totalMin = ar2317GetMinPower(ah, &data[i]) - ar2317GetMinPower(ah, &data[last]);
+		*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+				     ar2317GetMinPower(ah, &data[last])*totalD)/totalD);
+		return(AH_TRUE);
+	} else {
+		if (chan->channel == data[i].channelValue) {
+			*maxPow = ar2317GetMaxPower(ah, &data[i]);
+			*minPow = ar2317GetMinPower(ah, &data[i]);
+			return(AH_TRUE);
+		} else
+			return(AH_FALSE);
+	}
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar2317RfDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(ahp->ah_rfHal != AH_NULL);
+	ath_hal_free(ahp->ah_rfHal);
+	ahp->ah_rfHal = AH_NULL;
+}
+
+/*
+ * Allocate memory for analog bank scratch buffers
+ * Scratch Buffer will be reinitialized every reset so no need to zero now
+ */
+static HAL_BOOL
+ar2317RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar2317State *priv;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	HALASSERT(ahp->ah_rfHal == AH_NULL);
+	priv = ath_hal_malloc(sizeof(struct ar2317State));
+	if (priv == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot allocate private state\n", __func__);
+		*status = HAL_ENOMEM;		/* XXX */
+		return AH_FALSE;
+	}
+	priv->base.rfDetach		= ar2317RfDetach;
+	priv->base.writeRegs		= ar2317WriteRegs;
+	priv->base.getRfBank		= ar2317GetRfBank;
+	priv->base.setChannel		= ar2317SetChannel;
+	priv->base.setRfRegs		= ar2317SetRfRegs;
+	priv->base.setPowerTable	= ar2317SetPowerTable;
+	priv->base.getChannelMaxMinPower = ar2317GetChannelMaxMinPower;
+	priv->base.getNfAdjust		= ar5212GetNfAdjust;
+
+	ahp->ah_pcdacTable = priv->pcdacTable;
+	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+	ahp->ah_rfHal = &priv->base;
+
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+ar2317Probe(struct ath_hal *ah)
+{
+	return IS_2317(ah);
+}
+AH_RF(RF2317, ar2317Probe, ar2317RfAttach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2413.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2413.c
new file mode 100644
index 0000000..a9e4686
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2413.c
@@ -0,0 +1,759 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar2413.c,v 1.8 2008/11/15 22:15:46 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#include "ah_eeprom_v3.h"
+
+#define AH_5212_2413
+#include "ar5212/ar5212.ini"
+
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+
+struct ar2413State {
+	RF_HAL_FUNCS	base;		/* public state, must be first */
+	uint16_t	pcdacTable[PWR_TABLE_SIZE_2413];
+
+	uint32_t	Bank1Data[N(ar5212Bank1_2413)];
+	uint32_t	Bank2Data[N(ar5212Bank2_2413)];
+	uint32_t	Bank3Data[N(ar5212Bank3_2413)];
+	uint32_t	Bank6Data[N(ar5212Bank6_2413)];
+	uint32_t	Bank7Data[N(ar5212Bank7_2413)];
+
+	/*
+	 * Private state for reduced stack usage.
+	 */
+	/* filled out Vpd table for all pdGains (chanL) */
+	uint16_t vpdTable_L[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (chanR) */
+	uint16_t vpdTable_R[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (interpolated) */
+	uint16_t vpdTable_I[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+};
+#define	AR2413(ah)	((struct ar2413State *) AH5212(ah)->ah_rfHal)
+
+extern	void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+		uint32_t numBits, uint32_t firstBit, uint32_t column);
+
+static void
+ar2413WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+	int writes)
+{
+	HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2413, modesIndex, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212Common_2413, 1, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2413, freqIndex, writes);
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ */
+static HAL_BOOL
+ar2413SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t channelSel  = 0;
+	uint32_t bModeSynth  = 0;
+	uint32_t aModeRefSel = 0;
+	uint32_t reg32       = 0;
+	uint16_t freq;
+
+	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+
+	if (chan->channel < 4800) {
+		uint32_t txctl;
+
+		if (((chan->channel - 2192) % 5) == 0) {
+			channelSel = ((chan->channel - 672) * 2 - 3040)/10;
+			bModeSynth = 0;
+		} else if (((chan->channel - 2224) % 5) == 0) {
+			channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
+			bModeSynth = 1;
+		} else {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: invalid channel %u MHz\n",
+			    __func__, chan->channel);
+			return AH_FALSE;
+		}
+
+		channelSel = (channelSel << 2) & 0xff;
+		channelSel = ath_hal_reverseBits(channelSel, 8);
+
+		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+		if (chan->channel == 2484) {
+			/* Enable channel spreading for channel 14 */
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+		}
+	} else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
+		freq = chan->channel - 2; /* Align to even 5MHz raster */
+		channelSel = ath_hal_reverseBits(
+			(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
+            	aModeRefSel = ath_hal_reverseBits(0, 2);
+	} else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 20 << 2), 8);
+		aModeRefSel = ath_hal_reverseBits(3, 2);
+	} else if ((chan->channel % 10) == 0) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 10 << 1), 8);
+		aModeRefSel = ath_hal_reverseBits(2, 2);
+	} else if ((chan->channel % 5) == 0) {
+		channelSel = ath_hal_reverseBits(
+			(chan->channel - 4800) / 5, 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
+		    __func__, chan->channel);
+		return AH_FALSE;
+	}
+
+	reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
+			(1 << 12) | 0x1;
+	OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
+
+	reg32 >>= 8;
+	OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+
+	return AH_TRUE;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ *
+ * REQUIRES: Access to the analog rf device
+ */
+static HAL_BOOL
+ar2413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    \
+	int i;								    \
+	for (i = 0; i < N(ar5212Bank##_ix##_2413); i++)			    \
+		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2413[i][_col];\
+} while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t ob2GHz = 0, db2GHz = 0;
+	struct ar2413State *priv = AR2413(ah);
+	int regWrites = 0;
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+	    "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
+	    __func__, chan->channel, chan->channelFlags, modesIndex);
+
+	HALASSERT(priv);
+
+	/* Setup rf parameters */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_B:
+		ob2GHz = ee->ee_obFor24;
+		db2GHz = ee->ee_dbFor24;
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		ob2GHz = ee->ee_obFor24g;
+		db2GHz = ee->ee_dbFor24g;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/* Bank 1 Write */
+	RF_BANK_SETUP(priv, 1, 1);
+
+	/* Bank 2 Write */
+	RF_BANK_SETUP(priv, 2, modesIndex);
+
+	/* Bank 3 Write */
+	RF_BANK_SETUP(priv, 3, modesIndex);
+
+	/* Bank 6 Write */
+	RF_BANK_SETUP(priv, 6, modesIndex);
+
+	ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz,   3, 168, 0);
+	ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz,   3, 165, 0);
+
+	/* Bank 7 Setup */
+	RF_BANK_SETUP(priv, 7, modesIndex);
+
+	/* Write Analog registers */
+	HAL_INI_WRITE_BANK(ah, ar5212Bank1_2413, priv->Bank1Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank2_2413, priv->Bank2Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank3_2413, priv->Bank3Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank6_2413, priv->Bank6Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank7_2413, priv->Bank7Data, regWrites);
+
+	/* Now that we have reprogrammed rfgain value, clear the flag. */
+	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+
+	return AH_TRUE;
+#undef	RF_BANK_SETUP
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar2413GetRfBank(struct ath_hal *ah, int bank)
+{
+	struct ar2413State *priv = AR2413(ah);
+
+	HALASSERT(priv != AH_NULL);
+	switch (bank) {
+	case 1: return priv->Bank1Data;
+	case 2: return priv->Bank2Data;
+	case 3: return priv->Bank3Data;
+	case 6: return priv->Bank6Data;
+	case 7: return priv->Bank7Data;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+	    __func__, bank);
+	return AH_NULL;
+}
+
+/*
+ * Return indices surrounding the value in sorted integer lists.
+ *
+ * NB: the input list is assumed to be sorted in ascending order
+ */
+static void
+GetLowerUpperIndex(int16_t v, const uint16_t *lp, uint16_t listSize,
+                          uint32_t *vlo, uint32_t *vhi)
+{
+	int16_t target = v;
+	const uint16_t *ep = lp+listSize;
+	const uint16_t *tp;
+
+	/*
+	 * Check first and last elements for out-of-bounds conditions.
+	 */
+	if (target < lp[0]) {
+		*vlo = *vhi = 0;
+		return;
+	}
+	if (target >= ep[-1]) {
+		*vlo = *vhi = listSize - 1;
+		return;
+	}
+
+	/* look for value being near or between 2 values in list */
+	for (tp = lp; tp < ep; tp++) {
+		/*
+		 * If value is close to the current value of the list
+		 * then target is not between values, it is one of the values
+		 */
+		if (*tp == target) {
+			*vlo = *vhi = tp - (const uint16_t *) lp;
+			return;
+		}
+		/*
+		 * Look for value being between current value and next value
+		 * if so return these 2 values
+		 */
+		if (target < tp[1]) {
+			*vlo = tp - (const uint16_t *) lp;
+			*vhi = *vlo + 1;
+			return;
+		}
+	}
+}
+
+/*
+ * Fill the Vpdlist for indices Pmax-Pmin
+ */
+static HAL_BOOL
+ar2413FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t  Pmax,
+		   const int16_t *pwrList, const uint16_t *VpdList,
+		   uint16_t numIntercepts, uint16_t retVpdList[][64])
+{
+	uint16_t ii, jj, kk;
+	int16_t currPwr = (int16_t)(2*Pmin);
+	/* since Pmin is pwr*2 and pwrList is 4*pwr */
+	uint32_t  idxL, idxR;
+
+	ii = 0;
+	jj = 0;
+
+	if (numIntercepts < 2)
+		return AH_FALSE;
+
+	while (ii <= (uint16_t)(Pmax - Pmin)) {
+		GetLowerUpperIndex(currPwr, (const uint16_t *) pwrList,
+				   numIntercepts, &(idxL), &(idxR));
+		if (idxR < 1)
+			idxR = 1;			/* extrapolate below */
+		if (idxL == (uint32_t)(numIntercepts - 1))
+			idxL = numIntercepts - 2;	/* extrapolate above */
+		if (pwrList[idxL] == pwrList[idxR])
+			kk = VpdList[idxL];
+		else
+			kk = (uint16_t)
+				(((currPwr - pwrList[idxL])*VpdList[idxR]+ 
+				  (pwrList[idxR] - currPwr)*VpdList[idxL])/
+				 (pwrList[idxR] - pwrList[idxL]));
+		retVpdList[pdGainIdx][ii] = kk;
+		ii++;
+		currPwr += 2;				/* half dB steps */
+	}
+
+	return AH_TRUE;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+static int16_t
+interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+	int16_t targetLeft, int16_t targetRight)
+{
+	int16_t rv;
+
+	if (srcRight != srcLeft) {
+		rv = ((target - srcLeft)*targetRight +
+		      (srcRight - target)*targetLeft) / (srcRight - srcLeft);
+	} else {
+		rv = targetLeft;
+	}
+	return rv;
+}
+
+/*
+ * Uses the data points read from EEPROM to reconstruct the pdadc power table
+ * Called by ar2413SetPowerTable()
+ */
+static int 
+ar2413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
+		const RAW_DATA_STRUCT_2413 *pRawDataset,
+		uint16_t pdGainOverlap_t2, 
+		int16_t  *pMinCalPower, uint16_t pPdGainBoundaries[], 
+		uint16_t pPdGainValues[], uint16_t pPDADCValues[]) 
+{
+	struct ar2413State *priv = AR2413(ah);
+#define	VpdTable_L	priv->vpdTable_L
+#define	VpdTable_R	priv->vpdTable_R
+#define	VpdTable_I	priv->vpdTable_I
+	uint32_t ii, jj, kk;
+	int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
+	uint32_t idxL, idxR;
+	uint32_t numPdGainsUsed = 0;
+	/* 
+	 * If desired to support -ve power levels in future, just
+	 * change pwr_I_0 to signed 5-bits.
+	 */
+	int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on. */
+	int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on */
+	uint16_t numVpd = 0;
+	uint16_t Vpd_step;
+	int16_t tmpVal ; 
+	uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;
+
+	/* Get upper lower index */
+	GetLowerUpperIndex(channel, pRawDataset->pChannels,
+				 pRawDataset->numChannels, &(idxL), &(idxR));
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;
+			Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];
+			if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {
+				Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];
+			}
+			Pmin_t2[numPdGainsUsed] = (int16_t)
+				(Pmin_t2[numPdGainsUsed] / 2);
+			Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])
+				Pmax_t2[numPdGainsUsed] = 
+					pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);
+			ar2413FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]), 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L
+					   );
+			ar2413FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R
+					   );
+			for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {
+				VpdTable_I[numPdGainsUsed][kk] = 
+					interpolate_signed(
+							   channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],
+							   (int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);
+			}
+			/* fill VpdTable_I for this pdGain */
+			numPdGainsUsed++;
+		}
+		/* if this pdGain is used */
+	}
+
+	*pMinCalPower = Pmin_t2[0];
+	kk = 0; /* index for the final table */
+	for (ii = 0; ii < numPdGainsUsed; ii++) {
+		if (ii == (numPdGainsUsed - 1))
+			pPdGainBoundaries[ii] = Pmax_t2[ii] +
+				PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;
+		else 
+			pPdGainBoundaries[ii] = (uint16_t)
+				((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );
+		if (pPdGainBoundaries[ii] > 63) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: clamp pPdGainBoundaries[%d] %d\n",
+			    __func__, ii, pPdGainBoundaries[ii]);/*XXX*/
+			pPdGainBoundaries[ii] = 63;
+		}
+
+		/* Find starting index for this pdGain */
+		if (ii == 0) 
+			ss = 0; /* for the first pdGain, start from index 0 */
+		else 
+			ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) - 
+				pdGainOverlap_t2;
+		Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
+		/*
+		 *-ve ss indicates need to extrapolate data below for this pdGain
+		 */
+		while (ss < 0) {
+			tmpVal = (int16_t)(VpdTable_I[ii][0] + ss*Vpd_step);
+			pPDADCValues[kk++] = (uint16_t)((tmpVal < 0) ? 0 : tmpVal);
+			ss++;
+		}
+
+		sizeCurrVpdTable = Pmax_t2[ii] - Pmin_t2[ii];
+		tgtIndex = pPdGainBoundaries[ii] + pdGainOverlap_t2 - Pmin_t2[ii];
+		maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
+
+		while (ss < (int16_t)maxIndex)
+			pPDADCValues[kk++] = VpdTable_I[ii][ss++];
+
+		Vpd_step = (uint16_t)(VpdTable_I[ii][sizeCurrVpdTable-1] -
+				       VpdTable_I[ii][sizeCurrVpdTable-2]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);           
+		/*
+		 * for last gain, pdGainBoundary == Pmax_t2, so will 
+		 * have to extrapolate
+		 */
+		if (tgtIndex > maxIndex) {	/* need to extrapolate above */
+			while(ss < (int16_t)tgtIndex) {
+				tmpVal = (uint16_t)
+					(VpdTable_I[ii][sizeCurrVpdTable-1] + 
+					 (ss-maxIndex)*Vpd_step);
+				pPDADCValues[kk++] = (tmpVal > 127) ? 
+					127 : tmpVal;
+				ss++;
+			}
+		}				/* extrapolated above */
+	}					/* for all pdGainUsed */
+
+	while (ii < MAX_NUM_PDGAINS_PER_CHANNEL) {
+		pPdGainBoundaries[ii] = pPdGainBoundaries[ii-1];
+		ii++;
+	}
+	while (kk < 128) {
+		pPDADCValues[kk] = pPDADCValues[kk-1];
+		kk++;
+	}
+
+	return numPdGainsUsed;
+#undef VpdTable_L
+#undef VpdTable_R
+#undef VpdTable_I
+}
+
+static HAL_BOOL
+ar2413SetPowerTable(struct ath_hal *ah,
+	int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan, 
+	uint16_t *rfXpdGain)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
+	uint16_t pdGainOverlap_t2;
+	int16_t minCalPower2413_t2;
+	uint16_t *pdadcValues = ahp->ah_pcdacTable;
+	uint16_t gainBoundaries[4];
+	uint32_t reg32, regoffset;
+	int i, numPdGainsUsed;
+#ifndef AH_USE_INIPDGAIN
+	uint32_t tpcrg1;
+#endif
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
+	    __func__, chan->channel,chan->channelFlags);
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: illegal mode\n", __func__);
+		return AH_FALSE;
+	}
+
+	pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
+					  AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
+    
+	numPdGainsUsed = ar2413getGainBoundariesAndPdadcsForPowers(ah,
+		chan->channel, pRawDataset, pdGainOverlap_t2,
+		&minCalPower2413_t2,gainBoundaries, rfXpdGain, pdadcValues);
+	HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
+
+#ifdef AH_USE_INIPDGAIN
+	/*
+	 * Use pd_gains curve from eeprom; Atheros always uses
+	 * the default curve from the ini file but some vendors
+	 * (e.g. Zcomax) want to override this curve and not
+	 * honoring their settings results in tx power 5dBm low.
+	 */
+	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 
+			 (pRawDataset->pDataPerChannel[0].numPdGains - 1));
+#else
+	tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);
+	tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)
+		  | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
+	switch (numPdGainsUsed) {
+	case 3:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;
+		tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
+		/* fall thru... */
+	case 2:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;
+		tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
+		/* fall thru... */
+	case 1:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;
+		tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
+		break;
+	}
+#ifdef AH_DEBUG
+	if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "
+		    "pd_gains (default 0x%x, calculated 0x%x)\n",
+		    __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);
+#endif
+	OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);
+#endif
+
+	/*
+	 * Note the pdadc table may not start at 0 dBm power, could be
+	 * negative or greater than 0.  Need to offset the power
+	 * values by the amount of minPower for griffin
+	 */
+	if (minCalPower2413_t2 != 0)
+		ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2413_t2);
+	else
+		ahp->ah_txPowerIndexOffset = 0;
+
+	/* Finally, write the power values into the baseband power table */
+	regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
+	for (i = 0; i < 32; i++) {
+		reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0)  | 
+			((pdadcValues[4*i + 1] & 0xFF) << 8)  |
+			((pdadcValues[4*i + 2] & 0xFF) << 16) |
+			((pdadcValues[4*i + 3] & 0xFF) << 24) ;        
+		OS_REG_WRITE(ah, regoffset, reg32);
+		regoffset += 4;
+	}
+
+	OS_REG_WRITE(ah, AR_PHY_TPCRG5, 
+		     SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 
+		     SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
+		     SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
+		     SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
+		     SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
+
+	return AH_TRUE;
+}
+
+static int16_t
+ar2413GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)
+{
+	uint32_t ii,jj;
+	uint16_t Pmin=0,numVpd;
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = data->pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			Pmin = data->pDataPerPDGain[jj].pwr_t4[0];
+			return(Pmin);
+		}
+	}
+	return(Pmin);
+}
+
+static int16_t
+ar2413GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)
+{
+	uint32_t ii;
+	uint16_t Pmax=0,numVpd;
+	
+	for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		/* work forwards cuase lowest pdGain for highest power */
+		numVpd = data->pDataPerPDGain[ii].numVpd;
+		if (numVpd > 0) {
+			Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
+			return(Pmax);
+		}
+	}
+	return(Pmax);
+}
+
+static HAL_BOOL
+ar2413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+	int16_t *maxPow, int16_t *minPow)
+{
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
+	const RAW_DATA_PER_CHANNEL_2413 *data = AH_NULL;
+	uint16_t numChannels;
+	int totalD,totalF, totalMin,last, i;
+
+	*maxPow = 0;
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else
+		return(AH_FALSE);
+
+	numChannels = pRawDataset->numChannels;
+	data = pRawDataset->pDataPerChannel;
+	
+	/* Make sure the channel is in the range of the TP values 
+	 *  (freq piers)
+	 */
+	if (numChannels < 1)
+		return(AH_FALSE);
+
+	if ((chan->channel < data[0].channelValue) ||
+	    (chan->channel > data[numChannels-1].channelValue)) {
+		if (chan->channel < data[0].channelValue) {
+			*maxPow = ar2413GetMaxPower(ah, &data[0]);
+			*minPow = ar2413GetMinPower(ah, &data[0]);
+			return(AH_TRUE);
+		} else {
+			*maxPow = ar2413GetMaxPower(ah, &data[numChannels - 1]);
+			*minPow = ar2413GetMinPower(ah, &data[numChannels - 1]);
+			return(AH_TRUE);
+		}
+	}
+
+	/* Linearly interpolate the power value now */
+	for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+	     last = i++);
+	totalD = data[i].channelValue - data[last].channelValue;
+	if (totalD > 0) {
+		totalF = ar2413GetMaxPower(ah, &data[i]) - ar2413GetMaxPower(ah, &data[last]);
+		*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + 
+				     ar2413GetMaxPower(ah, &data[last])*totalD)/totalD);
+		totalMin = ar2413GetMinPower(ah, &data[i]) - ar2413GetMinPower(ah, &data[last]);
+		*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+				     ar2413GetMinPower(ah, &data[last])*totalD)/totalD);
+		return(AH_TRUE);
+	} else {
+		if (chan->channel == data[i].channelValue) {
+			*maxPow = ar2413GetMaxPower(ah, &data[i]);
+			*minPow = ar2413GetMinPower(ah, &data[i]);
+			return(AH_TRUE);
+		} else
+			return(AH_FALSE);
+	}
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar2413RfDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(ahp->ah_rfHal != AH_NULL);
+	ath_hal_free(ahp->ah_rfHal);
+	ahp->ah_rfHal = AH_NULL;
+}
+
+/*
+ * Allocate memory for analog bank scratch buffers
+ * Scratch Buffer will be reinitialized every reset so no need to zero now
+ */
+static HAL_BOOL
+ar2413RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar2413State *priv;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	HALASSERT(ahp->ah_rfHal == AH_NULL);
+	priv = ath_hal_malloc(sizeof(struct ar2413State));
+	if (priv == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot allocate private state\n", __func__);
+		*status = HAL_ENOMEM;		/* XXX */
+		return AH_FALSE;
+	}
+	priv->base.rfDetach		= ar2413RfDetach;
+	priv->base.writeRegs		= ar2413WriteRegs;
+	priv->base.getRfBank		= ar2413GetRfBank;
+	priv->base.setChannel		= ar2413SetChannel;
+	priv->base.setRfRegs		= ar2413SetRfRegs;
+	priv->base.setPowerTable	= ar2413SetPowerTable;
+	priv->base.getChannelMaxMinPower = ar2413GetChannelMaxMinPower;
+	priv->base.getNfAdjust		= ar5212GetNfAdjust;
+
+	ahp->ah_pcdacTable = priv->pcdacTable;
+	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+	ahp->ah_rfHal = &priv->base;
+
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+ar2413Probe(struct ath_hal *ah)
+{
+	return IS_2413(ah);
+}
+AH_RF(RF2413, ar2413Probe, ar2413RfAttach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2425.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2425.c
new file mode 100644
index 0000000..adb41b5
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar2425.c
@@ -0,0 +1,722 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar2425.c,v 1.8 2008/11/16 21:33:05 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#include "ah_eeprom_v3.h"
+
+#define AH_5212_2425
+#define AH_5212_2417
+#include "ar5212/ar5212.ini"
+
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+
+struct ar2425State {
+	RF_HAL_FUNCS	base;		/* public state, must be first */
+	uint16_t	pcdacTable[PWR_TABLE_SIZE_2413];
+
+	uint32_t	Bank1Data[N(ar5212Bank1_2425)];
+	uint32_t	Bank2Data[N(ar5212Bank2_2425)];
+	uint32_t	Bank3Data[N(ar5212Bank3_2425)];
+	uint32_t	Bank6Data[N(ar5212Bank6_2425)];	/* 2417 is same size */
+	uint32_t	Bank7Data[N(ar5212Bank7_2425)];
+};
+#define	AR2425(ah)	((struct ar2425State *) AH5212(ah)->ah_rfHal)
+
+extern	void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+		uint32_t numBits, uint32_t firstBit, uint32_t column);
+
+static void
+ar2425WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+	int writes)
+{
+	HAL_INI_WRITE_ARRAY(ah, ar5212Modes_2425, modesIndex, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212Common_2425, 1, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_2425, freqIndex, writes);
+#if 0
+	/*
+	 * for SWAN similar to Condor
+	 * Bit 0 enables link to go to L1 when MAC goes to sleep.
+	 * Bit 3 enables the loop back the link down to reset.
+	 */
+	if (IS_PCIE(ah) && ath_hal_pcieL1SKPEnable) {
+		OS_REG_WRITE(ah, AR_PCIE_PMC,
+		    AR_PCIE_PMC_ENA_L1 | AR_PCIE_PMC_ENA_RESET);
+	}
+	/*
+	 * for Standby issue in Swan/Condor.
+	 * Bit 9 (MAC_WOW_PWR_STATE_MASK_D2)to be set to avoid skips
+	 *	before last Training Sequence 2 (TS2)
+	 * Bit 8 (MAC_WOW_PWR_STATE_MASK_D1)to be unset to assert
+	 *	Power Reset along with PCI Reset
+	 */
+	OS_REG_SET_BIT(ah, AR_PCIE_PMC, MAC_WOW_PWR_STATE_MASK_D2);
+#endif
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ */
+static HAL_BOOL
+ar2425SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t channelSel  = 0;
+	uint32_t bModeSynth  = 0;
+	uint32_t aModeRefSel = 0;
+	uint32_t reg32       = 0;
+	uint16_t freq;
+
+	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+
+	if (chan->channel < 4800) {
+		uint32_t txctl;
+
+        channelSel = chan->channel - 2272;
+        channelSel = ath_hal_reverseBits(channelSel, 8);
+
+		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+        if (chan->channel == 2484) {
+			// Enable channel spreading for channel 14
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+		}
+
+	} else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
+		freq = chan->channel - 2; /* Align to even 5MHz raster */
+		channelSel = ath_hal_reverseBits(
+			(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
+            	aModeRefSel = ath_hal_reverseBits(0, 2);
+	} else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 20 << 2), 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else if ((chan->channel % 10) == 0) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 10 << 1), 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else if ((chan->channel % 5) == 0) {
+		channelSel = ath_hal_reverseBits(
+			(chan->channel - 4800) / 5, 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
+		    __func__, chan->channel);
+		return AH_FALSE;
+	}
+
+	reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
+			(1 << 12) | 0x1;
+	OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
+
+	reg32 >>= 8;
+	OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ *
+ * REQUIRES: Access to the analog rf device
+ */
+static HAL_BOOL
+ar2425SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    \
+	int i;								    \
+	for (i = 0; i < N(ar5212Bank##_ix##_2425); i++)			    \
+		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2425[i][_col];\
+} while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	struct ar2425State *priv = AR2425(ah);
+	uint16_t ob2GHz = 0, db2GHz = 0;
+	int regWrites = 0;
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+	    "==>%s:chan 0x%x flag 0x%x modesIndex 0x%x\n",
+	    __func__, chan->channel, chan->channelFlags, modesIndex);
+
+	HALASSERT(priv);
+
+	/* Setup rf parameters */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_B:
+		ob2GHz = ee->ee_obFor24;
+		db2GHz = ee->ee_dbFor24;
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		ob2GHz = ee->ee_obFor24g;
+		db2GHz = ee->ee_dbFor24g;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+			__func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/* Bank 1 Write */
+	RF_BANK_SETUP(priv, 1, 1);
+
+	/* Bank 2 Write */
+	RF_BANK_SETUP(priv, 2, modesIndex);
+
+	/* Bank 3 Write */
+	RF_BANK_SETUP(priv, 3, modesIndex);
+
+	/* Bank 6 Write */
+	RF_BANK_SETUP(priv, 6, modesIndex);
+
+        ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 193, 0);
+        ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 190, 0);
+
+	/* Bank 7 Setup */
+	RF_BANK_SETUP(priv, 7, modesIndex);
+
+	/* Write Analog registers */
+	HAL_INI_WRITE_BANK(ah, ar5212Bank1_2425, priv->Bank1Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank2_2425, priv->Bank2Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank3_2425, priv->Bank3Data, regWrites);
+	if (IS_2417(ah)) {
+		HALASSERT(N(ar5212Bank6_2425) == N(ar5212Bank6_2417));
+		HAL_INI_WRITE_BANK(ah, ar5212Bank6_2417, priv->Bank6Data,
+		    regWrites);
+	} else
+		HAL_INI_WRITE_BANK(ah, ar5212Bank6_2425, priv->Bank6Data,
+		    regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank7_2425, priv->Bank7Data, regWrites);
+
+	/* Now that we have reprogrammed rfgain value, clear the flag. */
+	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "<==%s\n", __func__);
+	return AH_TRUE;
+#undef	RF_BANK_SETUP
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar2425GetRfBank(struct ath_hal *ah, int bank)
+{
+	struct ar2425State *priv = AR2425(ah);
+
+	HALASSERT(priv != AH_NULL);
+	switch (bank) {
+	case 1: return priv->Bank1Data;
+	case 2: return priv->Bank2Data;
+	case 3: return priv->Bank3Data;
+	case 6: return priv->Bank6Data;
+	case 7: return priv->Bank7Data;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+	    __func__, bank);
+	return AH_NULL;
+}
+
+/*
+ * Return indices surrounding the value in sorted integer lists.
+ *
+ * NB: the input list is assumed to be sorted in ascending order
+ */
+static void
+GetLowerUpperIndex(int16_t v, const uint16_t *lp, uint16_t listSize,
+                          uint32_t *vlo, uint32_t *vhi)
+{
+	int16_t target = v;
+	const uint16_t *ep = lp+listSize;
+	const uint16_t *tp;
+
+	/*
+	 * Check first and last elements for out-of-bounds conditions.
+	 */
+	if (target < lp[0]) {
+		*vlo = *vhi = 0;
+		return;
+	}
+	if (target >= ep[-1]) {
+		*vlo = *vhi = listSize - 1;
+		return;
+	}
+
+	/* look for value being near or between 2 values in list */
+	for (tp = lp; tp < ep; tp++) {
+		/*
+		 * If value is close to the current value of the list
+		 * then target is not between values, it is one of the values
+		 */
+		if (*tp == target) {
+			*vlo = *vhi = tp - (const uint16_t *) lp;
+			return;
+		}
+		/*
+		 * Look for value being between current value and next value
+		 * if so return these 2 values
+		 */
+		if (target < tp[1]) {
+			*vlo = tp - (const uint16_t *) lp;
+			*vhi = *vlo + 1;
+			return;
+		}
+	}
+}
+
+/*
+ * Fill the Vpdlist for indices Pmax-Pmin
+ */
+static HAL_BOOL
+ar2425FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t  Pmax,
+		   const int16_t *pwrList, const uint16_t *VpdList,
+		   uint16_t numIntercepts,
+		   uint16_t retVpdList[][64])
+{
+	uint16_t ii, jj, kk;
+	int16_t currPwr = (int16_t)(2*Pmin);
+	/* since Pmin is pwr*2 and pwrList is 4*pwr */
+	uint32_t  idxL, idxR;
+
+	ii = 0;
+	jj = 0;
+
+	if (numIntercepts < 2)
+		return AH_FALSE;
+
+	while (ii <= (uint16_t)(Pmax - Pmin)) {
+		GetLowerUpperIndex(currPwr, (const uint16_t *) pwrList,
+				   numIntercepts, &(idxL), &(idxR));
+		if (idxR < 1)
+			idxR = 1;			/* extrapolate below */
+		if (idxL == (uint32_t)(numIntercepts - 1))
+			idxL = numIntercepts - 2;	/* extrapolate above */
+		if (pwrList[idxL] == pwrList[idxR])
+			kk = VpdList[idxL];
+		else
+			kk = (uint16_t)
+				(((currPwr - pwrList[idxL])*VpdList[idxR]+ 
+				  (pwrList[idxR] - currPwr)*VpdList[idxL])/
+				 (pwrList[idxR] - pwrList[idxL]));
+		retVpdList[pdGainIdx][ii] = kk;
+		ii++;
+		currPwr += 2;				/* half dB steps */
+	}
+
+	return AH_TRUE;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+static int16_t
+interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+	int16_t targetLeft, int16_t targetRight)
+{
+	int16_t rv;
+
+	if (srcRight != srcLeft) {
+		rv = ((target - srcLeft)*targetRight +
+		      (srcRight - target)*targetLeft) / (srcRight - srcLeft);
+	} else {
+		rv = targetLeft;
+	}
+	return rv;
+}
+
+/*
+ * Uses the data points read from EEPROM to reconstruct the pdadc power table
+ * Called by ar2425SetPowerTable()
+ */
+static void 
+ar2425getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
+		const RAW_DATA_STRUCT_2413 *pRawDataset,
+		uint16_t pdGainOverlap_t2, 
+		int16_t  *pMinCalPower, uint16_t pPdGainBoundaries[], 
+		uint16_t pPdGainValues[], uint16_t pPDADCValues[]) 
+{
+    /* Note the items statically allocated below are to reduce stack usage */
+	uint32_t ii, jj, kk;
+	int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
+	uint32_t idxL, idxR;
+	uint32_t numPdGainsUsed = 0;
+        static uint16_t VpdTable_L[MAX_NUM_PDGAINS_PER_CHANNEL][MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (chanL) */
+        static uint16_t VpdTable_R[MAX_NUM_PDGAINS_PER_CHANNEL][MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (chanR) */
+        static uint16_t VpdTable_I[MAX_NUM_PDGAINS_PER_CHANNEL][MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (interpolated) */
+	/* 
+	 * If desired to support -ve power levels in future, just
+	 * change pwr_I_0 to signed 5-bits.
+	 */
+        static int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on. */
+        static int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on */
+	uint16_t numVpd = 0;
+	uint16_t Vpd_step;
+	int16_t tmpVal ; 
+	uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "==>%s:\n", __func__);
+    
+	/* Get upper lower index */
+	GetLowerUpperIndex(channel, pRawDataset->pChannels,
+				 pRawDataset->numChannels, &(idxL), &(idxR));
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;
+			Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];
+			if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {
+				Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];
+			}
+			Pmin_t2[numPdGainsUsed] = (int16_t)
+				(Pmin_t2[numPdGainsUsed] / 2);
+			Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])
+				Pmax_t2[numPdGainsUsed] = 
+					pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);
+			ar2425FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]), 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L
+					   );
+			ar2425FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R
+					   );
+			for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {
+				VpdTable_I[numPdGainsUsed][kk] = 
+					interpolate_signed(
+							   channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],
+							   (int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);
+			}
+			/* fill VpdTable_I for this pdGain */
+			numPdGainsUsed++;
+		}
+		/* if this pdGain is used */
+	}
+
+	*pMinCalPower = Pmin_t2[0];
+	kk = 0; /* index for the final table */
+	for (ii = 0; ii < numPdGainsUsed; ii++) {
+		if (ii == (numPdGainsUsed - 1))
+			pPdGainBoundaries[ii] = Pmax_t2[ii] +
+				PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;
+		else 
+			pPdGainBoundaries[ii] = (uint16_t)
+				((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );
+
+		/* Find starting index for this pdGain */
+		if (ii == 0) 
+			ss = 0; /* for the first pdGain, start from index 0 */
+		else 
+			ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) - 
+				pdGainOverlap_t2;
+		Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
+		/*
+		 *-ve ss indicates need to extrapolate data below for this pdGain
+		 */
+		while (ss < 0) {
+			tmpVal = (int16_t)(VpdTable_I[ii][0] + ss*Vpd_step);
+			pPDADCValues[kk++] = (uint16_t)((tmpVal < 0) ? 0 : tmpVal);
+			ss++;
+		}
+
+		sizeCurrVpdTable = Pmax_t2[ii] - Pmin_t2[ii];
+		tgtIndex = pPdGainBoundaries[ii] + pdGainOverlap_t2 - Pmin_t2[ii];
+		maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
+
+		while (ss < (int16_t)maxIndex)
+			pPDADCValues[kk++] = VpdTable_I[ii][ss++];
+
+		Vpd_step = (uint16_t)(VpdTable_I[ii][sizeCurrVpdTable-1] -
+				       VpdTable_I[ii][sizeCurrVpdTable-2]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);           
+		/*
+		 * for last gain, pdGainBoundary == Pmax_t2, so will 
+		 * have to extrapolate
+		 */
+		if (tgtIndex > maxIndex) {	/* need to extrapolate above */
+			while(ss < (int16_t)tgtIndex) {
+				tmpVal = (uint16_t)
+					(VpdTable_I[ii][sizeCurrVpdTable-1] + 
+					 (ss-maxIndex)*Vpd_step);
+				pPDADCValues[kk++] = (tmpVal > 127) ? 
+					127 : tmpVal;
+				ss++;
+			}
+		}				/* extrapolated above */
+	}					/* for all pdGainUsed */
+
+	while (ii < MAX_NUM_PDGAINS_PER_CHANNEL) {
+		pPdGainBoundaries[ii] = pPdGainBoundaries[ii-1];
+		ii++;
+	}
+	while (kk < 128) {
+		pPDADCValues[kk] = pPDADCValues[kk-1];
+		kk++;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "<==%s\n", __func__);
+}
+
+
+/* Same as 2413 set power table */
+static HAL_BOOL
+ar2425SetPowerTable(struct ath_hal *ah,
+	int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan, 
+	uint16_t *rfXpdGain)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
+	uint16_t pdGainOverlap_t2;
+	int16_t minCalPower2413_t2;
+	uint16_t *pdadcValues = ahp->ah_pcdacTable;
+	uint16_t gainBoundaries[4];
+	uint32_t i, reg32, regoffset;
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s:chan 0x%x flag 0x%x\n",
+	    __func__, chan->channel,chan->channelFlags);
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s:illegal mode\n", __func__);
+		return AH_FALSE;
+	}
+
+	pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
+					  AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
+    
+	ar2425getGainBoundariesAndPdadcsForPowers(ah, chan->channel,
+		pRawDataset, pdGainOverlap_t2,&minCalPower2413_t2,gainBoundaries,
+		rfXpdGain, pdadcValues);
+
+	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 
+			 (pRawDataset->pDataPerChannel[0].numPdGains - 1));
+
+	/*
+	 * Note the pdadc table may not start at 0 dBm power, could be
+	 * negative or greater than 0.  Need to offset the power
+	 * values by the amount of minPower for griffin
+	 */
+	if (minCalPower2413_t2 != 0)
+		ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower2413_t2);
+	else
+		ahp->ah_txPowerIndexOffset = 0;
+
+	/* Finally, write the power values into the baseband power table */
+	regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
+	for (i = 0; i < 32; i++) {
+		reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0)  | 
+			((pdadcValues[4*i + 1] & 0xFF) << 8)  |
+			((pdadcValues[4*i + 2] & 0xFF) << 16) |
+			((pdadcValues[4*i + 3] & 0xFF) << 24) ;        
+		OS_REG_WRITE(ah, regoffset, reg32);
+		regoffset += 4;
+	}
+
+	OS_REG_WRITE(ah, AR_PHY_TPCRG5, 
+		     SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 
+		     SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
+		     SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
+		     SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
+		     SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
+
+	return AH_TRUE;
+}
+
+static int16_t
+ar2425GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)
+{
+	uint32_t ii,jj;
+	uint16_t Pmin=0,numVpd;
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = data->pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			Pmin = data->pDataPerPDGain[jj].pwr_t4[0];
+			return(Pmin);
+		}
+	}
+	return(Pmin);
+}
+
+static int16_t
+ar2425GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)
+{
+	uint32_t ii;
+	uint16_t Pmax=0,numVpd;
+	
+	for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		/* work forwards cuase lowest pdGain for highest power */
+		numVpd = data->pDataPerPDGain[ii].numVpd;
+		if (numVpd > 0) {
+			Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
+			return(Pmax);
+		}
+	}
+	return(Pmax);
+}
+
+static
+HAL_BOOL
+ar2425GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+				     int16_t *maxPow, int16_t *minPow)
+{
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
+	const RAW_DATA_PER_CHANNEL_2413 *data = AH_NULL;
+	uint16_t numChannels;
+	int totalD,totalF, totalMin,last, i;
+
+	*maxPow = 0;
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else
+		return(AH_FALSE);
+
+	numChannels = pRawDataset->numChannels;
+	data = pRawDataset->pDataPerChannel;
+	
+	/* Make sure the channel is in the range of the TP values 
+	 *  (freq piers)
+	 */
+	if (numChannels < 1)
+		return(AH_FALSE);
+
+	if ((chan->channel < data[0].channelValue) ||
+	    (chan->channel > data[numChannels-1].channelValue)) {
+		if (chan->channel < data[0].channelValue) {
+			*maxPow = ar2425GetMaxPower(ah, &data[0]);
+			*minPow = ar2425GetMinPower(ah, &data[0]);
+			return(AH_TRUE);
+		} else {
+			*maxPow = ar2425GetMaxPower(ah, &data[numChannels - 1]);
+			*minPow = ar2425GetMinPower(ah, &data[numChannels - 1]);
+			return(AH_TRUE);
+		}
+	}
+
+	/* Linearly interpolate the power value now */
+	for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+	     last = i++);
+	totalD = data[i].channelValue - data[last].channelValue;
+	if (totalD > 0) {
+		totalF = ar2425GetMaxPower(ah, &data[i]) - ar2425GetMaxPower(ah, &data[last]);
+		*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + 
+				     ar2425GetMaxPower(ah, &data[last])*totalD)/totalD);
+		totalMin = ar2425GetMinPower(ah, &data[i]) - ar2425GetMinPower(ah, &data[last]);
+		*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+				     ar2425GetMinPower(ah, &data[last])*totalD)/totalD);
+		return(AH_TRUE);
+	} else {
+		if (chan->channel == data[i].channelValue) {
+			*maxPow = ar2425GetMaxPower(ah, &data[i]);
+			*minPow = ar2425GetMinPower(ah, &data[i]);
+			return(AH_TRUE);
+		} else
+			return(AH_FALSE);
+	}
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar2425RfDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(ahp->ah_rfHal != AH_NULL);
+	ath_hal_free(ahp->ah_rfHal);
+	ahp->ah_rfHal = AH_NULL;
+}
+
+/*
+ * Allocate memory for analog bank scratch buffers
+ * Scratch Buffer will be reinitialized every reset so no need to zero now
+ */
+static HAL_BOOL
+ar2425RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar2425State *priv;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	HALASSERT(ahp->ah_rfHal == AH_NULL);
+	priv = ath_hal_malloc(sizeof(struct ar2425State));
+	if (priv == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot allocate private state\n", __func__);
+		*status = HAL_ENOMEM;		/* XXX */
+		return AH_FALSE;
+	}
+	priv->base.rfDetach		= ar2425RfDetach;
+	priv->base.writeRegs		= ar2425WriteRegs;
+	priv->base.getRfBank		= ar2425GetRfBank;
+	priv->base.setChannel		= ar2425SetChannel;
+	priv->base.setRfRegs		= ar2425SetRfRegs;
+	priv->base.setPowerTable	= ar2425SetPowerTable;
+	priv->base.getChannelMaxMinPower = ar2425GetChannelMaxMinPower;
+	priv->base.getNfAdjust		= ar5212GetNfAdjust;
+
+	ahp->ah_pcdacTable = priv->pcdacTable;
+	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+	ahp->ah_rfHal = &priv->base;
+
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+ar2425Probe(struct ath_hal *ah)
+{
+	return IS_2425(ah) || IS_2417(ah);
+}
+AH_RF(RF2425, ar2425Probe, ar2425RfAttach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5111.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5111.c
new file mode 100644
index 0000000..79d1101
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5111.c
@@ -0,0 +1,711 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5111.c,v 1.2.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ah_eeprom_v3.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#define AH_5212_5111
+#include "ar5212/ar5212.ini"
+
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+
+struct ar5111State {
+	RF_HAL_FUNCS	base;		/* public state, must be first */
+	uint16_t	pcdacTable[PWR_TABLE_SIZE];
+
+	uint32_t	Bank0Data[N(ar5212Bank0_5111)];
+	uint32_t	Bank1Data[N(ar5212Bank1_5111)];
+	uint32_t	Bank2Data[N(ar5212Bank2_5111)];
+	uint32_t	Bank3Data[N(ar5212Bank3_5111)];
+	uint32_t	Bank6Data[N(ar5212Bank6_5111)];
+	uint32_t	Bank7Data[N(ar5212Bank7_5111)];
+};
+#define	AR5111(ah)	((struct ar5111State *) AH5212(ah)->ah_rfHal)
+
+static uint16_t ar5212GetScaledPower(uint16_t channel, uint16_t pcdacValue,
+		const PCDACS_EEPROM *pSrcStruct);
+static HAL_BOOL ar5212FindValueInList(uint16_t channel, uint16_t pcdacValue,
+		const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue);
+static void ar5212GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
+		const PCDACS_EEPROM *pSrcStruct,
+		uint16_t *pLowerPcdac, uint16_t *pUpperPcdac);
+
+extern void ar5212GetLowerUpperValues(uint16_t value,
+		const uint16_t *pList, uint16_t listSize,
+		uint16_t *pLowerValue, uint16_t *pUpperValue);
+extern	void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+		uint32_t numBits, uint32_t firstBit, uint32_t column);
+
+static void
+ar5111WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+	int writes)
+{
+	HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5111, modesIndex, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212Common_5111, 1, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5111, freqIndex, writes);
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ */
+static HAL_BOOL
+ar5111SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+#define CI_2GHZ_INDEX_CORRECTION 19
+	uint32_t refClk, reg32, data2111;
+	int16_t chan5111, chanIEEE;
+
+	/*
+	 * Structure to hold 11b tuning information for 5111/2111
+	 * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12
+	 */
+	typedef struct {
+		uint32_t	refClkSel;	/* reference clock, 1 for 16 MHz */
+		uint32_t	channelSelect;	/* P[7:4]S[3:0] bits */
+		uint16_t	channel5111;	/* 11a channel for 5111 */
+	} CHAN_INFO_2GHZ;
+
+	static const CHAN_INFO_2GHZ chan2GHzData[] = {
+		{ 1, 0x46, 96  },	/* 2312 -19 */
+		{ 1, 0x46, 97  },	/* 2317 -18 */
+		{ 1, 0x46, 98  },	/* 2322 -17 */
+		{ 1, 0x46, 99  },	/* 2327 -16 */
+		{ 1, 0x46, 100 },	/* 2332 -15 */
+		{ 1, 0x46, 101 },	/* 2337 -14 */
+		{ 1, 0x46, 102 },	/* 2342 -13 */
+		{ 1, 0x46, 103 },	/* 2347 -12 */
+		{ 1, 0x46, 104 },	/* 2352 -11 */
+		{ 1, 0x46, 105 },	/* 2357 -10 */
+		{ 1, 0x46, 106 },	/* 2362  -9 */
+		{ 1, 0x46, 107 },	/* 2367  -8 */
+		{ 1, 0x46, 108 },	/* 2372  -7 */
+		/* index -6 to 0 are pad to make this a nolookup table */
+		{ 1, 0x46, 116 },	/*       -6 */
+		{ 1, 0x46, 116 },	/*       -5 */
+		{ 1, 0x46, 116 },	/*       -4 */
+		{ 1, 0x46, 116 },	/*       -3 */
+		{ 1, 0x46, 116 },	/*       -2 */
+		{ 1, 0x46, 116 },	/*       -1 */
+		{ 1, 0x46, 116 },	/*        0 */
+		{ 1, 0x46, 116 },	/* 2412   1 */
+		{ 1, 0x46, 117 },	/* 2417   2 */
+		{ 1, 0x46, 118 },	/* 2422   3 */
+		{ 1, 0x46, 119 },	/* 2427   4 */
+		{ 1, 0x46, 120 },	/* 2432   5 */
+		{ 1, 0x46, 121 },	/* 2437   6 */
+		{ 1, 0x46, 122 },	/* 2442   7 */
+		{ 1, 0x46, 123 },	/* 2447   8 */
+		{ 1, 0x46, 124 },	/* 2452   9 */
+		{ 1, 0x46, 125 },	/* 2457  10 */
+		{ 1, 0x46, 126 },	/* 2462  11 */
+		{ 1, 0x46, 127 },	/* 2467  12 */
+		{ 1, 0x46, 128 },	/* 2472  13 */
+		{ 1, 0x44, 124 },	/* 2484  14 */
+		{ 1, 0x46, 136 },	/* 2512  15 */
+		{ 1, 0x46, 140 },	/* 2532  16 */
+		{ 1, 0x46, 144 },	/* 2552  17 */
+		{ 1, 0x46, 148 },	/* 2572  18 */
+		{ 1, 0x46, 152 },	/* 2592  19 */
+		{ 1, 0x46, 156 },	/* 2612  20 */
+		{ 1, 0x46, 160 },	/* 2632  21 */
+		{ 1, 0x46, 164 },	/* 2652  22 */
+		{ 1, 0x46, 168 },	/* 2672  23 */
+		{ 1, 0x46, 172 },	/* 2692  24 */
+		{ 1, 0x46, 176 },	/* 2712  25 */
+		{ 1, 0x46, 180 } 	/* 2732  26 */
+	};
+
+	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+
+	chanIEEE = ath_hal_mhz2ieee(ah, chan->channel, chan->channelFlags);
+	if (IS_CHAN_2GHZ(chan)) {
+		const CHAN_INFO_2GHZ* ci =
+			&chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION];
+		uint32_t txctl;
+
+		data2111 = ((ath_hal_reverseBits(ci->channelSelect, 8) & 0xff)
+				<< 5)
+			 | (ci->refClkSel << 4);
+		chan5111 = ci->channel5111;
+		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+		if (chan->channel == 2484) {
+			/* Enable channel spreading for channel 14 */
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+		}
+	} else {
+		chan5111 = chanIEEE;	/* no conversion needed */
+		data2111 = 0;
+	}
+
+	/* Rest of the code is common for 5 GHz and 2.4 GHz. */
+	if (chan5111 >= 145 || (chan5111 & 0x1)) {
+		reg32  = ath_hal_reverseBits(chan5111 - 24, 8) & 0xff;
+		refClk = 1;
+	} else {
+		reg32  = ath_hal_reverseBits(((chan5111 - 24)/2), 8) & 0xff;
+		refClk = 0;
+	}
+
+	reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1;
+	OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));
+	reg32 >>= 8;
+	OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+#undef CI_2GHZ_INDEX_CORRECTION
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar5111GetRfBank(struct ath_hal *ah, int bank)
+{
+	struct ar5111State *priv = AR5111(ah);
+
+	HALASSERT(priv != AH_NULL);
+	switch (bank) {
+	case 0: return priv->Bank0Data;
+	case 1: return priv->Bank1Data;
+	case 2: return priv->Bank2Data;
+	case 3: return priv->Bank3Data;
+	case 6: return priv->Bank6Data;
+	case 7: return priv->Bank7Data;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+	    __func__, bank);
+	return AH_NULL;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ *
+ * REQUIRES: Access to the analog rf device
+ */
+static HAL_BOOL
+ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+	uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t rfXpdGainFixed, rfPloSel, rfPwdXpd, gainI;
+	uint16_t tempOB, tempDB;
+	uint32_t ob2GHz, db2GHz, rfReg[N(ar5212Bank6_5111)];
+	int i, regWrites = 0;
+
+	/* Setup rf parameters */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+	case CHANNEL_T:
+		if (4000 < chan->channel && chan->channel < 5260) {
+			tempOB = ee->ee_ob1;
+			tempDB = ee->ee_db1;
+		} else if (5260 <= chan->channel && chan->channel < 5500) {
+			tempOB = ee->ee_ob2;
+			tempDB = ee->ee_db2;
+		} else if (5500 <= chan->channel && chan->channel < 5725) {
+			tempOB = ee->ee_ob3;
+			tempDB = ee->ee_db3;
+		} else if (chan->channel >= 5725) {
+			tempOB = ee->ee_ob4;
+			tempDB = ee->ee_db4;
+		} else {
+			/* XXX when does this happen??? */
+			tempOB = tempDB = 0;
+		}
+		ob2GHz = db2GHz = 0;
+
+		rfXpdGainFixed = ee->ee_xgain[headerInfo11A];
+		rfPloSel = ee->ee_xpd[headerInfo11A];
+		rfPwdXpd = !ee->ee_xpd[headerInfo11A];
+		gainI = ee->ee_gainI[headerInfo11A];
+		break;
+	case CHANNEL_B:
+		tempOB = ee->ee_obFor24;
+		tempDB = ee->ee_dbFor24;
+		ob2GHz = ee->ee_ob2GHz[0];
+		db2GHz = ee->ee_db2GHz[0];
+
+		rfXpdGainFixed = ee->ee_xgain[headerInfo11B];
+		rfPloSel = ee->ee_xpd[headerInfo11B];
+		rfPwdXpd = !ee->ee_xpd[headerInfo11B];
+		gainI = ee->ee_gainI[headerInfo11B];
+		break;
+	case CHANNEL_G:
+		tempOB = ee->ee_obFor24g;
+		tempDB = ee->ee_dbFor24g;
+		ob2GHz = ee->ee_ob2GHz[1];
+		db2GHz = ee->ee_db2GHz[1];
+
+		rfXpdGainFixed = ee->ee_xgain[headerInfo11G];
+		rfPloSel = ee->ee_xpd[headerInfo11G];
+		rfPwdXpd = !ee->ee_xpd[headerInfo11G];
+		gainI = ee->ee_gainI[headerInfo11G];
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	HALASSERT(1 <= tempOB && tempOB <= 5);
+	HALASSERT(1 <= tempDB && tempDB <= 5);
+
+	/* Bank 0 Write */
+	for (i = 0; i < N(ar5212Bank0_5111); i++)
+		rfReg[i] = ar5212Bank0_5111[i][modesIndex];
+	if (IS_CHAN_2GHZ(chan)) {
+		ar5212ModifyRfBuffer(rfReg, ob2GHz, 3, 119, 0);
+		ar5212ModifyRfBuffer(rfReg, db2GHz, 3, 122, 0);
+	}
+	HAL_INI_WRITE_BANK(ah, ar5212Bank0_5111, rfReg, regWrites);
+
+	/* Bank 1 Write */
+	HAL_INI_WRITE_ARRAY(ah, ar5212Bank1_5111, 1, regWrites);
+
+	/* Bank 2 Write */
+	HAL_INI_WRITE_ARRAY(ah, ar5212Bank2_5111, modesIndex, regWrites);
+
+	/* Bank 3 Write */
+	HAL_INI_WRITE_ARRAY(ah, ar5212Bank3_5111, modesIndex, regWrites);
+
+	/* Bank 6 Write */
+	for (i = 0; i < N(ar5212Bank6_5111); i++)
+		rfReg[i] = ar5212Bank6_5111[i][modesIndex];
+	if (IS_CHAN_A(chan)) {		/* NB: CHANNEL_A | CHANNEL_T */
+		ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd84, 1, 51, 3);
+		ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd90, 1, 45, 3);
+	}
+	ar5212ModifyRfBuffer(rfReg, rfPwdXpd, 1, 95, 0);
+	ar5212ModifyRfBuffer(rfReg, rfXpdGainFixed, 4, 96, 0);
+	/* Set 5212 OB & DB */
+	ar5212ModifyRfBuffer(rfReg, tempOB, 3, 104, 0);
+	ar5212ModifyRfBuffer(rfReg, tempDB, 3, 107, 0);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank6_5111, rfReg, regWrites);
+
+	/* Bank 7 Write */
+	for (i = 0; i < N(ar5212Bank7_5111); i++)
+		rfReg[i] = ar5212Bank7_5111[i][modesIndex];
+	ar5212ModifyRfBuffer(rfReg, gainI, 6, 29, 0);   
+	ar5212ModifyRfBuffer(rfReg, rfPloSel, 1, 4, 0);   
+
+	if (IS_CHAN_QUARTER_RATE(chan) || IS_CHAN_HALF_RATE(chan)) {
+        	uint32_t	rfWaitI, rfWaitS, rfMaxTime;
+
+        	rfWaitS = 0x1f;
+        	rfWaitI = (IS_CHAN_HALF_RATE(chan)) ?  0x10 : 0x1f;
+        	rfMaxTime = 3;
+        	ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0);
+        	ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0);
+        	ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0);
+
+	}
+
+	HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites);
+
+	/* Now that we have reprogrammed rfgain value, clear the flag. */
+	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+
+	return AH_TRUE;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+static uint16_t
+interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+	uint16_t targetLeft, uint16_t targetRight)
+{
+	uint16_t rv;
+	int16_t lRatio;
+
+	/* to get an accurate ratio, always scale, if want to scale, then don't scale back down */
+	if ((targetLeft * targetRight) == 0)
+		return 0;
+
+	if (srcRight != srcLeft) {
+		/*
+		 * Note the ratio always need to be scaled,
+		 * since it will be a fraction.
+		 */
+		lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft);
+		if (lRatio < 0) {
+		    /* Return as Left target if value would be negative */
+		    rv = targetLeft;
+		} else if (lRatio > EEP_SCALE) {
+		    /* Return as Right target if Ratio is greater than 100% (SCALE) */
+		    rv = targetRight;
+		} else {
+			rv = (lRatio * targetRight + (EEP_SCALE - lRatio) *
+					targetLeft) / EEP_SCALE;
+		}
+	} else {
+		rv = targetLeft;
+	}
+	return rv;
+}
+
+/*
+ * Read the transmit power levels from the structures taken from EEPROM
+ * Interpolate read transmit power values for this channel
+ * Organize the transmit power values into a table for writing into the hardware
+ */
+static HAL_BOOL
+ar5111SetPowerTable(struct ath_hal *ah,
+	int16_t *pMinPower, int16_t *pMaxPower, HAL_CHANNEL_INTERNAL *chan,
+	uint16_t *rfXpdGain)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	FULL_PCDAC_STRUCT pcdacStruct;
+	int i, j;
+
+	uint16_t     *pPcdacValues;
+	int16_t      *pScaledUpDbm;
+	int16_t      minScaledPwr;
+	int16_t      maxScaledPwr;
+	int16_t      pwr;
+	uint16_t     pcdacMin = 0;
+	uint16_t     pcdacMax = PCDAC_STOP;
+	uint16_t     pcdacTableIndex;
+	uint16_t     scaledPcdac;
+	PCDACS_EEPROM *pSrcStruct;
+	PCDACS_EEPROM eepromPcdacs;
+
+	/* setup the pcdac struct to point to the correct info, based on mode */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+	case CHANNEL_T:
+		eepromPcdacs.numChannels     = ee->ee_numChannels11a;
+		eepromPcdacs.pChannelList    = ee->ee_channels11a;
+		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;
+		break;
+	case CHANNEL_B:
+		eepromPcdacs.numChannels     = ee->ee_numChannels2_4;
+		eepromPcdacs.pChannelList    = ee->ee_channels11b;
+		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		eepromPcdacs.numChannels     = ee->ee_numChannels2_4;
+		eepromPcdacs.pChannelList    = ee->ee_channels11g;
+		eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	pSrcStruct = &eepromPcdacs;
+
+	OS_MEMZERO(&pcdacStruct, sizeof(pcdacStruct));
+	pPcdacValues = pcdacStruct.PcdacValues;
+	pScaledUpDbm = pcdacStruct.PwrValues;
+
+	/* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */
+	for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++)
+		pPcdacValues[j] = i;
+
+	pcdacStruct.numPcdacValues = j;
+	pcdacStruct.pcdacMin = PCDAC_START;
+	pcdacStruct.pcdacMax = PCDAC_STOP;
+
+	/* Fill out the power values for this channel */
+	for (j = 0; j < pcdacStruct.numPcdacValues; j++ )
+		pScaledUpDbm[j] = ar5212GetScaledPower(chan->channel,
+			pPcdacValues[j], pSrcStruct);
+
+	/* Now scale the pcdac values to fit in the 64 entry power table */
+	minScaledPwr = pScaledUpDbm[0];
+	maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1];
+
+	/* find minimum and make monotonic */
+	for (j = 0; j < pcdacStruct.numPcdacValues; j++) {
+		if (minScaledPwr >= pScaledUpDbm[j]) {
+			minScaledPwr = pScaledUpDbm[j];
+			pcdacMin = j;
+		}
+		/*
+		 * Make the full_hsh monotonically increasing otherwise
+		 * interpolation algorithm will get fooled gotta start
+		 * working from the top, hence i = 63 - j.
+		 */
+		i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j);
+		if (i == 0)
+			break;
+		if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) {
+			/*
+			 * It could be a glitch, so make the power for
+			 * this pcdac the same as the power from the
+			 * next highest pcdac.
+			 */
+			pScaledUpDbm[i - 1] = pScaledUpDbm[i];
+		}
+	}
+
+	for (j = 0; j < pcdacStruct.numPcdacValues; j++)
+		if (maxScaledPwr < pScaledUpDbm[j]) {
+			maxScaledPwr = pScaledUpDbm[j];
+			pcdacMax = j;
+		}
+
+	/* Find the first power level with a pcdac */
+	pwr = (uint16_t)(PWR_STEP *
+		((minScaledPwr - PWR_MIN + PWR_STEP / 2) / PWR_STEP) + PWR_MIN);
+
+	/* Write all the first pcdac entries based off the pcdacMin */
+	pcdacTableIndex = 0;
+	for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++) {
+		HALASSERT(pcdacTableIndex < PWR_TABLE_SIZE);
+		ahp->ah_pcdacTable[pcdacTableIndex++] = pcdacMin;
+	}
+
+	i = 0;
+	while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
+	    pcdacTableIndex < PWR_TABLE_SIZE) {
+		pwr += PWR_STEP;
+		/* stop if dbM > max_power_possible */
+		while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
+		       (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0)
+			i++;
+		/* scale by 2 and add 1 to enable round up or down as needed */
+		scaledPcdac = (uint16_t)(interpolate(pwr,
+			pScaledUpDbm[i], pScaledUpDbm[i + 1],
+			(uint16_t)(pPcdacValues[i] * 2),
+			(uint16_t)(pPcdacValues[i + 1] * 2)) + 1);
+
+		HALASSERT(pcdacTableIndex < PWR_TABLE_SIZE);
+		ahp->ah_pcdacTable[pcdacTableIndex] = scaledPcdac / 2;
+		if (ahp->ah_pcdacTable[pcdacTableIndex] > pcdacMax)
+			ahp->ah_pcdacTable[pcdacTableIndex] = pcdacMax;
+		pcdacTableIndex++;
+	}
+
+	/* Write all the last pcdac entries based off the last valid pcdac */
+	while (pcdacTableIndex < PWR_TABLE_SIZE) {
+		ahp->ah_pcdacTable[pcdacTableIndex] =
+			ahp->ah_pcdacTable[pcdacTableIndex - 1];
+		pcdacTableIndex++;
+	}
+
+	/* No power table adjustment for 5111 */
+	ahp->ah_txPowerIndexOffset = 0;
+
+	return AH_TRUE;
+}
+
+/*
+ * Get or interpolate the pcdac value from the calibrated data.
+ */
+static uint16_t
+ar5212GetScaledPower(uint16_t channel, uint16_t pcdacValue,
+	const PCDACS_EEPROM *pSrcStruct)
+{
+	uint16_t powerValue;
+	uint16_t lFreq, rFreq;		/* left and right frequency values */
+	uint16_t llPcdac, ulPcdac;	/* lower and upper left pcdac values */
+	uint16_t lrPcdac, urPcdac;	/* lower and upper right pcdac values */
+	uint16_t lPwr, uPwr;		/* lower and upper temp pwr values */
+	uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */
+
+	if (ar5212FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue)) {
+		/* value was copied from srcStruct */
+		return powerValue;
+	}
+
+	ar5212GetLowerUpperValues(channel,
+		pSrcStruct->pChannelList, pSrcStruct->numChannels,
+		&lFreq, &rFreq);
+	ar5212GetLowerUpperPcdacs(pcdacValue,
+		lFreq, pSrcStruct, &llPcdac, &ulPcdac);
+	ar5212GetLowerUpperPcdacs(pcdacValue,
+		rFreq, pSrcStruct, &lrPcdac, &urPcdac);
+
+	/* get the power index for the pcdac value */
+	ar5212FindValueInList(lFreq, llPcdac, pSrcStruct, &lPwr);
+	ar5212FindValueInList(lFreq, ulPcdac, pSrcStruct, &uPwr);
+	lScaledPwr = interpolate(pcdacValue, llPcdac, ulPcdac, lPwr, uPwr);
+
+	ar5212FindValueInList(rFreq, lrPcdac, pSrcStruct, &lPwr);
+	ar5212FindValueInList(rFreq, urPcdac, pSrcStruct, &uPwr);
+	rScaledPwr = interpolate(pcdacValue, lrPcdac, urPcdac, lPwr, uPwr);
+
+	return interpolate(channel, lFreq, rFreq, lScaledPwr, rScaledPwr);
+}
+
+/*
+ * Find the value from the calibrated source data struct
+ */
+static HAL_BOOL
+ar5212FindValueInList(uint16_t channel, uint16_t pcdacValue,
+	const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue)
+{
+	const DATA_PER_CHANNEL *pChannelData = pSrcStruct->pDataPerChannel;
+	int i;
+
+	for (i = 0; i < pSrcStruct->numChannels; i++ ) {
+		if (pChannelData->channelValue == channel) {
+			const uint16_t* pPcdac = pChannelData->PcdacValues;
+			int j;
+
+			for (j = 0; j < pChannelData->numPcdacValues; j++ ) {
+				if (*pPcdac == pcdacValue) {
+					*powerValue = pChannelData->PwrValues[j];
+					return AH_TRUE;
+				}
+				pPcdac++;
+			}
+		}
+		pChannelData++;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Get the upper and lower pcdac given the channel and the pcdac
+ * used in the search
+ */
+static void
+ar5212GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
+	const PCDACS_EEPROM *pSrcStruct,
+	uint16_t *pLowerPcdac, uint16_t *pUpperPcdac)
+{
+	const DATA_PER_CHANNEL *pChannelData = pSrcStruct->pDataPerChannel;
+	int i;
+
+	/* Find the channel information */
+	for (i = 0; i < pSrcStruct->numChannels; i++) {
+		if (pChannelData->channelValue == channel)
+			break;
+		pChannelData++;
+	}
+	ar5212GetLowerUpperValues(pcdac, pChannelData->PcdacValues,
+		      pChannelData->numPcdacValues,
+		      pLowerPcdac, pUpperPcdac);
+}
+
+static HAL_BOOL
+ar5111GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+	int16_t *maxPow, int16_t *minPow)
+{
+	/* XXX - Get 5111 power limits! */
+	/* NB: caller will cope */
+	return AH_FALSE;
+}
+
+/*
+ * Adjust NF based on statistical values for 5GHz frequencies.
+ */
+static int16_t
+ar5111GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
+{
+	static const struct {
+		uint16_t freqLow;
+		int16_t	  adjust;
+	} adjust5111[] = {
+		{ 5790,	6 },	/* NB: ordered high -> low */
+		{ 5730, 4 },
+		{ 5690, 3 },
+		{ 5660, 2 },
+		{ 5610, 1 },
+		{ 5530, 0 },
+		{ 5450, 0 },
+		{ 5379, 1 },
+		{ 5209, 3 },
+		{ 3000, 5 },
+		{    0, 0 },
+	};
+	int i;
+
+	for (i = 0; c->channel <= adjust5111[i].freqLow; i++)
+		;
+	return adjust5111[i].adjust;
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar5111RfDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(ahp->ah_rfHal != AH_NULL);
+	ath_hal_free(ahp->ah_rfHal);
+	ahp->ah_rfHal = AH_NULL;
+}
+
+/*
+ * Allocate memory for analog bank scratch buffers
+ * Scratch Buffer will be reinitialized every reset so no need to zero now
+ */
+static HAL_BOOL
+ar5111RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5111State *priv;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	HALASSERT(ahp->ah_rfHal == AH_NULL);
+	priv = ath_hal_malloc(sizeof(struct ar5111State));
+	if (priv == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot allocate private state\n", __func__);
+		*status = HAL_ENOMEM;		/* XXX */
+		return AH_FALSE;
+	}
+	priv->base.rfDetach		= ar5111RfDetach;
+	priv->base.writeRegs		= ar5111WriteRegs;
+	priv->base.getRfBank		= ar5111GetRfBank;
+	priv->base.setChannel		= ar5111SetChannel;
+	priv->base.setRfRegs		= ar5111SetRfRegs;
+	priv->base.setPowerTable	= ar5111SetPowerTable;
+	priv->base.getChannelMaxMinPower = ar5111GetChannelMaxMinPower;
+	priv->base.getNfAdjust		= ar5111GetNfAdjust;
+
+	ahp->ah_pcdacTable = priv->pcdacTable;
+	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+	ahp->ah_rfHal = &priv->base;
+
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+ar5111Probe(struct ath_hal *ah)
+{
+	return IS_RAD5111(ah);
+}
+AH_RF(RF5111, ar5111Probe, ar5111RfAttach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5112.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5112.c
new file mode 100644
index 0000000..b124b1a
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5112.c
@@ -0,0 +1,881 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5112.c,v 1.7 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ah_eeprom_v3.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#define AH_5212_5112
+#include "ar5212/ar5212.ini"
+
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+
+struct ar5112State {
+	RF_HAL_FUNCS	base;		/* public state, must be first */
+	uint16_t	pcdacTable[PWR_TABLE_SIZE];
+
+	uint32_t	Bank1Data[N(ar5212Bank1_5112)];
+	uint32_t	Bank2Data[N(ar5212Bank2_5112)];
+	uint32_t	Bank3Data[N(ar5212Bank3_5112)];
+	uint32_t	Bank6Data[N(ar5212Bank6_5112)];
+	uint32_t	Bank7Data[N(ar5212Bank7_5112)];
+};
+#define	AR5112(ah)	((struct ar5112State *) AH5212(ah)->ah_rfHal)
+
+static	void ar5212GetLowerUpperIndex(uint16_t v,
+		uint16_t *lp, uint16_t listSize,
+		uint32_t *vlo, uint32_t *vhi);
+static HAL_BOOL getFullPwrTable(uint16_t numPcdacs, uint16_t *pcdacs,
+		int16_t *power, int16_t maxPower, int16_t *retVals);
+static int16_t getPminAndPcdacTableFromPowerTable(int16_t *pwrTableT4,
+		uint16_t retVals[]);
+static int16_t getPminAndPcdacTableFromTwoPowerTables(int16_t *pwrTableLXpdT4,
+		int16_t *pwrTableHXpdT4, uint16_t retVals[], int16_t *pMid);
+static int16_t interpolate_signed(uint16_t target,
+		uint16_t srcLeft, uint16_t srcRight,
+		int16_t targetLeft, int16_t targetRight);
+
+extern	void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+		uint32_t numBits, uint32_t firstBit, uint32_t column);
+
+static void
+ar5112WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+	int writes)
+{
+	HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5112, modesIndex, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212Common_5112, 1, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5112, freqIndex, writes);
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ */
+static HAL_BOOL
+ar5112SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t channelSel  = 0;
+	uint32_t bModeSynth  = 0;
+	uint32_t aModeRefSel = 0;
+	uint32_t reg32       = 0;
+	uint16_t freq;
+
+	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+
+	if (chan->channel < 4800) {
+		uint32_t txctl;
+
+		if (((chan->channel - 2192) % 5) == 0) {
+			channelSel = ((chan->channel - 672) * 2 - 3040)/10;
+			bModeSynth = 0;
+		} else if (((chan->channel - 2224) % 5) == 0) {
+			channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
+			bModeSynth = 1;
+		} else {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: invalid channel %u MHz\n",
+			    __func__, chan->channel);
+			return AH_FALSE;
+		}
+
+		channelSel = (channelSel << 2) & 0xff;
+		channelSel = ath_hal_reverseBits(channelSel, 8);
+
+		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+		if (chan->channel == 2484) {
+			/* Enable channel spreading for channel 14 */
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+		}
+	} else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
+		freq = chan->channel - 2; /* Align to even 5MHz raster */
+		channelSel = ath_hal_reverseBits(
+			(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
+            	aModeRefSel = ath_hal_reverseBits(0, 2);
+	} else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 20 << 2), 8);
+		aModeRefSel = ath_hal_reverseBits(3, 2);
+	} else if ((chan->channel % 10) == 0) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 10 << 1), 8);
+		aModeRefSel = ath_hal_reverseBits(2, 2);
+	} else if ((chan->channel % 5) == 0) {
+		channelSel = ath_hal_reverseBits(
+			(chan->channel - 4800) / 5, 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
+		    __func__, chan->channel);
+		return AH_FALSE;
+	}
+
+	reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
+			(1 << 12) | 0x1;
+	OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
+
+	reg32 >>= 8;
+	OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar5112GetRfBank(struct ath_hal *ah, int bank)
+{
+	struct ar5112State *priv = AR5112(ah);
+
+	HALASSERT(priv != AH_NULL);
+	switch (bank) {
+	case 1: return priv->Bank1Data;
+	case 2: return priv->Bank2Data;
+	case 3: return priv->Bank3Data;
+	case 6: return priv->Bank6Data;
+	case 7: return priv->Bank7Data;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+	    __func__, bank);
+	return AH_NULL;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ *
+ * REQUIRES: Access to the analog rf device
+ */
+static HAL_BOOL
+ar5112SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+	uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    \
+	int i;								    \
+	for (i = 0; i < N(ar5212Bank##_ix##_5112); i++)			    \
+		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_5112[i][_col];\
+} while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t rfXpdSel, gainI;
+	uint16_t ob5GHz = 0, db5GHz = 0;
+	uint16_t ob2GHz = 0, db2GHz = 0;
+	struct ar5112State *priv = AR5112(ah);
+	GAIN_VALUES *gv = &ahp->ah_gainValues;
+	int regWrites = 0;
+
+	HALASSERT(priv);
+
+	/* Setup rf parameters */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+	case CHANNEL_T:
+		if (chan->channel > 4000 && chan->channel < 5260) {
+			ob5GHz = ee->ee_ob1;
+			db5GHz = ee->ee_db1;
+		} else if (chan->channel >= 5260 && chan->channel < 5500) {
+			ob5GHz = ee->ee_ob2;
+			db5GHz = ee->ee_db2;
+		} else if (chan->channel >= 5500 && chan->channel < 5725) {
+			ob5GHz = ee->ee_ob3;
+			db5GHz = ee->ee_db3;
+		} else if (chan->channel >= 5725) {
+			ob5GHz = ee->ee_ob4;
+			db5GHz = ee->ee_db4;
+		} else {
+			/* XXX else */
+		}
+		rfXpdSel = ee->ee_xpd[headerInfo11A];
+		gainI = ee->ee_gainI[headerInfo11A];
+		break;
+	case CHANNEL_B:
+		ob2GHz = ee->ee_ob2GHz[0];
+		db2GHz = ee->ee_db2GHz[0];
+		rfXpdSel = ee->ee_xpd[headerInfo11B];
+		gainI = ee->ee_gainI[headerInfo11B];
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		ob2GHz = ee->ee_ob2GHz[1];
+		db2GHz = ee->ee_ob2GHz[1];
+		rfXpdSel = ee->ee_xpd[headerInfo11G];
+		gainI = ee->ee_gainI[headerInfo11G];
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/* Setup Bank 1 Write */
+	RF_BANK_SETUP(priv, 1, 1);
+
+	/* Setup Bank 2 Write */
+	RF_BANK_SETUP(priv, 2, modesIndex);
+
+	/* Setup Bank 3 Write */
+	RF_BANK_SETUP(priv, 3, modesIndex);
+
+	/* Setup Bank 6 Write */
+	RF_BANK_SETUP(priv, 6, modesIndex);
+
+	ar5212ModifyRfBuffer(priv->Bank6Data, rfXpdSel,     1, 302, 0);
+
+	ar5212ModifyRfBuffer(priv->Bank6Data, rfXpdGain[0], 2, 270, 0);
+	ar5212ModifyRfBuffer(priv->Bank6Data, rfXpdGain[1], 2, 257, 0);
+
+	if (IS_CHAN_OFDM(chan)) {
+		ar5212ModifyRfBuffer(priv->Bank6Data,
+			gv->currStep->paramVal[GP_PWD_138], 1, 168, 3);
+		ar5212ModifyRfBuffer(priv->Bank6Data,
+			gv->currStep->paramVal[GP_PWD_137], 1, 169, 3);
+		ar5212ModifyRfBuffer(priv->Bank6Data,
+			gv->currStep->paramVal[GP_PWD_136], 1, 170, 3);
+		ar5212ModifyRfBuffer(priv->Bank6Data,
+			gv->currStep->paramVal[GP_PWD_132], 1, 174, 3);
+		ar5212ModifyRfBuffer(priv->Bank6Data,
+			gv->currStep->paramVal[GP_PWD_131], 1, 175, 3);
+		ar5212ModifyRfBuffer(priv->Bank6Data,
+			gv->currStep->paramVal[GP_PWD_130], 1, 176, 3);
+	}
+
+	/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
+	if (IS_CHAN_2GHZ(chan)) {
+		ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 287, 0);
+		ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 290, 0);
+	} else {
+		ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 279, 0);
+		ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 282, 0);
+	}
+	
+	/* Lower synth voltage for X112 Rev 2.0 only */
+	if (IS_RADX112_REV2(ah)) {
+		/* Non-Reversed analyg registers - so values are pre-reversed */
+		ar5212ModifyRfBuffer(priv->Bank6Data, 2, 2, 90, 2);
+		ar5212ModifyRfBuffer(priv->Bank6Data, 2, 2, 92, 2);
+		ar5212ModifyRfBuffer(priv->Bank6Data, 2, 2, 94, 2);
+		ar5212ModifyRfBuffer(priv->Bank6Data, 2, 1, 254, 2);
+	}
+
+    /* Decrease Power Consumption for 5312/5213 and up */
+    if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
+        ar5212ModifyRfBuffer(priv->Bank6Data, 1, 1, 281, 1);
+        ar5212ModifyRfBuffer(priv->Bank6Data, 1, 2, 1, 3);
+        ar5212ModifyRfBuffer(priv->Bank6Data, 1, 2, 3, 3);
+        ar5212ModifyRfBuffer(priv->Bank6Data, 1, 1, 139, 3);
+        ar5212ModifyRfBuffer(priv->Bank6Data, 1, 1, 140, 3);
+    }
+
+	/* Setup Bank 7 Setup */
+	RF_BANK_SETUP(priv, 7, modesIndex);
+	if (IS_CHAN_OFDM(chan))
+		ar5212ModifyRfBuffer(priv->Bank7Data,
+			gv->currStep->paramVal[GP_MIXGAIN_OVR], 2, 37, 0);
+
+	ar5212ModifyRfBuffer(priv->Bank7Data, gainI, 6, 14, 0);
+
+	/* Adjust params for Derby TX power control */
+	if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) {
+        	uint32_t	rfDelay, rfPeriod;
+
+        	rfDelay = 0xf;
+        	rfPeriod = (IS_CHAN_HALF_RATE(chan)) ?  0x8 : 0xf;
+        	ar5212ModifyRfBuffer(priv->Bank7Data, rfDelay, 4, 58, 0);
+        	ar5212ModifyRfBuffer(priv->Bank7Data, rfPeriod, 4, 70, 0);
+	}
+
+#ifdef notyet
+	/* Analog registers are setup - EAR can modify */
+	if (ar5212IsEarEngaged(pDev, chan))
+		uint32_t modifier;
+		ar5212EarModify(pDev, EAR_LC_RF_WRITE, chan, &modifier);
+#endif
+	/* Write Analog registers */
+	HAL_INI_WRITE_BANK(ah, ar5212Bank1_5112, priv->Bank1Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank2_5112, priv->Bank2Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank3_5112, priv->Bank3Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank6_5112, priv->Bank6Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank7_5112, priv->Bank7Data, regWrites);
+
+	/* Now that we have reprogrammed rfgain value, clear the flag. */
+	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+	return AH_TRUE;
+#undef	RF_BANK_SETUP
+}
+
+/*
+ * Read the transmit power levels from the structures taken from EEPROM
+ * Interpolate read transmit power values for this channel
+ * Organize the transmit power values into a table for writing into the hardware
+ */
+static HAL_BOOL
+ar5112SetPowerTable(struct ath_hal *ah,
+	int16_t *pPowerMin, int16_t *pPowerMax, HAL_CHANNEL_INTERNAL *chan,
+	uint16_t *rfXpdGain)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint32_t numXpdGain = IS_RADX112_REV2(ah) ? 2 : 1;
+	uint32_t    xpdGainMask = 0;
+	int16_t     powerMid, *pPowerMid = &powerMid;
+
+	const EXPN_DATA_PER_CHANNEL_5112 *pRawCh;
+	const EEPROM_POWER_EXPN_5112     *pPowerExpn = AH_NULL;
+
+	uint32_t    ii, jj, kk;
+	int16_t     minPwr_t4, maxPwr_t4, Pmin, Pmid;
+
+	uint32_t    chan_idx_L = 0, chan_idx_R = 0;
+	uint16_t    chan_L, chan_R;
+
+	int16_t     pwr_table0[64];
+	int16_t     pwr_table1[64];
+	uint16_t    pcdacs[10];
+	int16_t     powers[10];
+	uint16_t    numPcd;
+	int16_t     powTableLXPD[2][64];
+	int16_t     powTableHXPD[2][64];
+	int16_t     tmpPowerTable[64];
+	uint16_t    xgainList[2];
+	uint16_t    xpdMask;
+
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+	case CHANNEL_T:
+		pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11A];
+		xpdGainMask = ee->ee_xgain[headerInfo11A];
+		break;
+	case CHANNEL_B:
+		pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11B];
+		xpdGainMask = ee->ee_xgain[headerInfo11B];
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		pPowerExpn = &ee->ee_modePowerArray5112[headerInfo11G];
+		xpdGainMask = ee->ee_xgain[headerInfo11G];
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown channel flags 0x%x\n",
+		    __func__, chan->channelFlags & CHANNEL_ALL);
+		return AH_FALSE;
+	}
+
+	if ((xpdGainMask & pPowerExpn->xpdMask) < 1) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: desired xpdGainMask 0x%x not supported by "
+		    "calibrated xpdMask 0x%x\n", __func__,
+		    xpdGainMask, pPowerExpn->xpdMask);
+		return AH_FALSE;
+	}
+
+	maxPwr_t4 = (int16_t)(2*(*pPowerMax));	/* pwr_t2 -> pwr_t4 */
+	minPwr_t4 = (int16_t)(2*(*pPowerMin));	/* pwr_t2 -> pwr_t4 */
+
+	xgainList[0] = 0xDEAD;
+	xgainList[1] = 0xDEAD;
+
+	kk = 0;
+	xpdMask = pPowerExpn->xpdMask;
+	for (jj = 0; jj < NUM_XPD_PER_CHANNEL; jj++) {
+		if (((xpdMask >> jj) & 1) > 0) {
+			if (kk > 1) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+				    "A maximum of 2 xpdGains supported"
+				    "in pExpnPower data\n");
+				return AH_FALSE;
+			}
+			xgainList[kk++] = (uint16_t)jj;
+		}
+	}
+
+	ar5212GetLowerUpperIndex(chan->channel, &pPowerExpn->pChannels[0],
+		pPowerExpn->numChannels, &chan_idx_L, &chan_idx_R);
+
+	kk = 0;
+	for (ii = chan_idx_L; ii <= chan_idx_R; ii++) {
+		pRawCh = &(pPowerExpn->pDataPerChannel[ii]);
+		if (xgainList[1] == 0xDEAD) {
+			jj = xgainList[0];
+			numPcd = pRawCh->pDataPerXPD[jj].numPcdacs;
+			OS_MEMCPY(&pcdacs[0], &pRawCh->pDataPerXPD[jj].pcdac[0],
+				numPcd * sizeof(uint16_t));
+			OS_MEMCPY(&powers[0], &pRawCh->pDataPerXPD[jj].pwr_t4[0],
+				numPcd * sizeof(int16_t));
+			if (!getFullPwrTable(numPcd, &pcdacs[0], &powers[0],
+				pRawCh->maxPower_t4, &tmpPowerTable[0])) {
+				return AH_FALSE;
+			}
+			OS_MEMCPY(&powTableLXPD[kk][0], &tmpPowerTable[0],
+				64*sizeof(int16_t));
+		} else {
+			jj = xgainList[0];
+			numPcd = pRawCh->pDataPerXPD[jj].numPcdacs;
+			OS_MEMCPY(&pcdacs[0], &pRawCh->pDataPerXPD[jj].pcdac[0],
+				numPcd*sizeof(uint16_t));
+			OS_MEMCPY(&powers[0],
+				&pRawCh->pDataPerXPD[jj].pwr_t4[0],
+				numPcd*sizeof(int16_t));
+			if (!getFullPwrTable(numPcd, &pcdacs[0], &powers[0],
+				pRawCh->maxPower_t4, &tmpPowerTable[0])) {
+				return AH_FALSE;
+			}
+			OS_MEMCPY(&powTableLXPD[kk][0], &tmpPowerTable[0],
+				64 * sizeof(int16_t));
+
+			jj = xgainList[1];
+			numPcd = pRawCh->pDataPerXPD[jj].numPcdacs;
+			OS_MEMCPY(&pcdacs[0], &pRawCh->pDataPerXPD[jj].pcdac[0],
+				numPcd * sizeof(uint16_t));
+			OS_MEMCPY(&powers[0],
+				&pRawCh->pDataPerXPD[jj].pwr_t4[0],
+				numPcd * sizeof(int16_t));
+			if (!getFullPwrTable(numPcd, &pcdacs[0], &powers[0],
+				pRawCh->maxPower_t4, &tmpPowerTable[0])) {
+				return AH_FALSE;
+			}
+			OS_MEMCPY(&powTableHXPD[kk][0], &tmpPowerTable[0],
+				64 * sizeof(int16_t));
+		}
+		kk++;
+	}
+
+	chan_L = pPowerExpn->pChannels[chan_idx_L];
+	chan_R = pPowerExpn->pChannels[chan_idx_R];
+	kk = chan_idx_R - chan_idx_L;
+
+	if (xgainList[1] == 0xDEAD) {
+		for (jj = 0; jj < 64; jj++) {
+			pwr_table0[jj] = interpolate_signed(
+				chan->channel, chan_L, chan_R,
+				powTableLXPD[0][jj], powTableLXPD[kk][jj]);
+		}
+		Pmin = getPminAndPcdacTableFromPowerTable(&pwr_table0[0],
+				ahp->ah_pcdacTable);
+		*pPowerMin = (int16_t) (Pmin / 2);
+		*pPowerMid = (int16_t) (pwr_table0[63] / 2);
+		*pPowerMax = (int16_t) (pwr_table0[63] / 2);
+		rfXpdGain[0] = xgainList[0];
+		rfXpdGain[1] = rfXpdGain[0];
+	} else {
+		for (jj = 0; jj < 64; jj++) {
+			pwr_table0[jj] = interpolate_signed(
+				chan->channel, chan_L, chan_R,
+				powTableLXPD[0][jj], powTableLXPD[kk][jj]);
+			pwr_table1[jj] = interpolate_signed(
+				chan->channel, chan_L, chan_R,
+				powTableHXPD[0][jj], powTableHXPD[kk][jj]);
+		}
+		if (numXpdGain == 2) {
+			Pmin = getPminAndPcdacTableFromTwoPowerTables(
+				&pwr_table0[0], &pwr_table1[0],
+				ahp->ah_pcdacTable, &Pmid);
+			*pPowerMin = (int16_t) (Pmin / 2);
+			*pPowerMid = (int16_t) (Pmid / 2);
+			*pPowerMax = (int16_t) (pwr_table0[63] / 2);
+			rfXpdGain[0] = xgainList[0];
+			rfXpdGain[1] = xgainList[1];
+		} else if (minPwr_t4 <= pwr_table1[63] &&
+			   maxPwr_t4 <= pwr_table1[63]) {
+			Pmin = getPminAndPcdacTableFromPowerTable(
+				&pwr_table1[0], ahp->ah_pcdacTable);
+			rfXpdGain[0] = xgainList[1];
+			rfXpdGain[1] = rfXpdGain[0];
+			*pPowerMin = (int16_t) (Pmin / 2);
+			*pPowerMid = (int16_t) (pwr_table1[63] / 2);
+			*pPowerMax = (int16_t) (pwr_table1[63] / 2);
+		} else {
+			Pmin = getPminAndPcdacTableFromPowerTable(
+				&pwr_table0[0], ahp->ah_pcdacTable);
+			rfXpdGain[0] = xgainList[0];
+			rfXpdGain[1] = rfXpdGain[0];
+			*pPowerMin = (int16_t) (Pmin/2);
+			*pPowerMid = (int16_t) (pwr_table0[63] / 2);
+			*pPowerMax = (int16_t) (pwr_table0[63] / 2);
+		}
+	}
+
+	/*
+	 * Move 5112 rates to match power tables where the max
+	 * power table entry corresponds with maxPower.
+	 */
+	HALASSERT(*pPowerMax <= PCDAC_STOP);
+	ahp->ah_txPowerIndexOffset = PCDAC_STOP - *pPowerMax;
+
+	return AH_TRUE;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+static int16_t
+interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+	int16_t targetLeft, int16_t targetRight)
+{
+	int16_t rv;
+
+	if (srcRight != srcLeft) {
+		rv = ((target - srcLeft)*targetRight +
+		      (srcRight - target)*targetLeft) / (srcRight - srcLeft);
+	} else {
+		rv = targetLeft;
+	}
+	return rv;
+}
+
+/*
+ * Return indices surrounding the value in sorted integer lists.
+ *
+ * NB: the input list is assumed to be sorted in ascending order
+ */
+static void
+ar5212GetLowerUpperIndex(uint16_t v, uint16_t *lp, uint16_t listSize,
+                          uint32_t *vlo, uint32_t *vhi)
+{
+	uint32_t target = v;
+	uint16_t *ep = lp+listSize;
+	uint16_t *tp;
+
+	/*
+	 * Check first and last elements for out-of-bounds conditions.
+	 */
+	if (target < lp[0]) {
+		*vlo = *vhi = 0;
+		return;
+	}
+	if (target >= ep[-1]) {
+		*vlo = *vhi = listSize - 1;
+		return;
+	}
+
+	/* look for value being near or between 2 values in list */
+	for (tp = lp; tp < ep; tp++) {
+		/*
+		 * If value is close to the current value of the list
+		 * then target is not between values, it is one of the values
+		 */
+		if (*tp == target) {
+			*vlo = *vhi = tp - lp;
+			return;
+		}
+		/*
+		 * Look for value being between current value and next value
+		 * if so return these 2 values
+		 */
+		if (target < tp[1]) {
+			*vlo = tp - lp;
+			*vhi = *vlo + 1;
+			return;
+		}
+	}
+}
+
+static HAL_BOOL
+getFullPwrTable(uint16_t numPcdacs, uint16_t *pcdacs, int16_t *power, int16_t maxPower, int16_t *retVals)
+{
+	uint16_t    ii;
+	uint16_t    idxL = 0;
+	uint16_t    idxR = 1;
+
+	if (numPcdacs < 2) {
+		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+		     "%s: at least 2 pcdac values needed [%d]\n",
+		     __func__, numPcdacs);
+		return AH_FALSE;
+	}
+	for (ii = 0; ii < 64; ii++) {
+		if (ii>pcdacs[idxR] && idxR < numPcdacs-1) {
+			idxL++;
+			idxR++;
+		}
+		retVals[ii] = interpolate_signed(ii,
+			pcdacs[idxL], pcdacs[idxR], power[idxL], power[idxR]);
+		if (retVals[ii] >= maxPower) {
+			while (ii < 64)
+				retVals[ii++] = maxPower;
+		}
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Takes a single calibration curve and creates a power table.
+ * Adjusts the new power table so the max power is relative
+ * to the maximum index in the power table.
+ *
+ * WARNING: rates must be adjusted for this relative power table
+ */
+static int16_t
+getPminAndPcdacTableFromPowerTable(int16_t *pwrTableT4, uint16_t retVals[])
+{
+    int16_t ii, jj, jjMax;
+    int16_t pMin, currPower, pMax;
+
+    /* If the spread is > 31.5dB, keep the upper 31.5dB range */
+    if ((pwrTableT4[63] - pwrTableT4[0]) > 126) {
+        pMin = pwrTableT4[63] - 126;
+    } else {
+        pMin = pwrTableT4[0];
+    }
+
+    pMax = pwrTableT4[63];
+    jjMax = 63;
+
+    /* Search for highest pcdac 0.25dB below maxPower */
+    while ((pwrTableT4[jjMax] > (pMax - 1) ) && (jjMax >= 0)) {
+        jjMax--;
+    }
+
+    jj = jjMax;
+    currPower = pMax;
+    for (ii = 63; ii >= 0; ii--) {
+        while ((jj < 64) && (jj > 0) && (pwrTableT4[jj] >= currPower)) {
+            jj--;
+        }
+        if (jj == 0) {
+            while (ii >= 0) {
+                retVals[ii] = retVals[ii + 1];
+                ii--;
+            }
+            break;
+        }
+        retVals[ii] = jj;
+        currPower -= 2;  // corresponds to a 0.5dB step
+    }
+    return pMin;
+}
+
+/*
+ * Combines the XPD curves from two calibration sets into a single
+ * power table and adjusts the power table so the max power is relative
+ * to the maximum index in the power table
+ *
+ * WARNING: rates must be adjusted for this relative power table
+ */
+static int16_t
+getPminAndPcdacTableFromTwoPowerTables(int16_t *pwrTableLXpdT4,
+	int16_t *pwrTableHXpdT4, uint16_t retVals[], int16_t *pMid)
+{
+    int16_t     ii, jj, jjMax;
+    int16_t     pMin, pMax, currPower;
+    int16_t     *pwrTableT4;
+    uint16_t    msbFlag = 0x40;  // turns on the 7th bit of the pcdac
+
+    /* If the spread is > 31.5dB, keep the upper 31.5dB range */
+    if ((pwrTableLXpdT4[63] - pwrTableHXpdT4[0]) > 126) {
+        pMin = pwrTableLXpdT4[63] - 126;
+    } else {
+        pMin = pwrTableHXpdT4[0];
+    }
+
+    pMax = pwrTableLXpdT4[63];
+    jjMax = 63;
+    /* Search for highest pcdac 0.25dB below maxPower */
+    while ((pwrTableLXpdT4[jjMax] > (pMax - 1) ) && (jjMax >= 0)){
+        jjMax--;
+    }
+
+    *pMid = pwrTableHXpdT4[63];
+    jj = jjMax;
+    ii = 63;
+    currPower = pMax;
+    pwrTableT4 = &(pwrTableLXpdT4[0]);
+    while (ii >= 0) {
+        if ((currPower <= *pMid) || ( (jj == 0) && (msbFlag == 0x40))){
+            msbFlag = 0x00;
+            pwrTableT4 = &(pwrTableHXpdT4[0]);
+            jj = 63;
+        }
+        while ((jj > 0) && (pwrTableT4[jj] >= currPower)) {
+            jj--;
+        }
+        if ((jj == 0) && (msbFlag == 0x00)) {
+            while (ii >= 0) {
+                retVals[ii] = retVals[ii+1];
+                ii--;
+            }
+            break;
+        }
+        retVals[ii] = jj | msbFlag;
+        currPower -= 2;  // corresponds to a 0.5dB step
+        ii--;
+    }
+    return pMin;
+}
+
+static int16_t
+ar5112GetMinPower(struct ath_hal *ah, const EXPN_DATA_PER_CHANNEL_5112 *data)
+{
+	int i, minIndex;
+	int16_t minGain,minPwr,minPcdac,retVal;
+
+	/* Assume NUM_POINTS_XPD0 > 0 */
+	minGain = data->pDataPerXPD[0].xpd_gain;
+	for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
+		if (data->pDataPerXPD[i].xpd_gain < minGain) {
+			minIndex = i;
+			minGain = data->pDataPerXPD[i].xpd_gain;
+		}
+	}
+	minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
+	minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
+	for (i=1; i<NUM_POINTS_XPD0; i++) {
+		if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
+			minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
+			minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
+		}
+	}
+	retVal = minPwr - (minPcdac*2);
+	return(retVal);
+}
+	
+static HAL_BOOL
+ar5112GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+	int16_t *maxPow, int16_t *minPow)
+{
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	int numChannels=0,i,last;
+	int totalD, totalF,totalMin;
+	const EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
+	const EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
+
+	*maxPow = 0;
+	if (IS_CHAN_A(chan)) {
+		powerArray = ee->ee_modePowerArray5112;
+		data = powerArray[headerInfo11A].pDataPerChannel;
+		numChannels = powerArray[headerInfo11A].numChannels;
+	} else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
+		/* XXX - is this correct? Should we also use the same power for turbo G? */
+		powerArray = ee->ee_modePowerArray5112;
+		data = powerArray[headerInfo11G].pDataPerChannel;
+		numChannels = powerArray[headerInfo11G].numChannels;
+	} else if (IS_CHAN_B(chan)) {
+		powerArray = ee->ee_modePowerArray5112;
+		data = powerArray[headerInfo11B].pDataPerChannel;
+		numChannels = powerArray[headerInfo11B].numChannels;
+	} else {
+		return (AH_TRUE);
+	}
+	/* Make sure the channel is in the range of the TP values 
+	 *  (freq piers)
+	 */
+	if (numChannels < 1)
+		return(AH_FALSE);
+
+	if ((chan->channel < data[0].channelValue) ||
+	    (chan->channel > data[numChannels-1].channelValue)) {
+		if (chan->channel < data[0].channelValue) {
+			*maxPow = data[0].maxPower_t4;
+			*minPow = ar5112GetMinPower(ah, &data[0]);
+			return(AH_TRUE);
+		} else {
+			*maxPow = data[numChannels - 1].maxPower_t4;
+			*minPow = ar5112GetMinPower(ah, &data[numChannels - 1]);
+			return(AH_TRUE);
+		}
+	}
+
+	/* Linearly interpolate the power value now */
+	for (last=0,i=0;
+	     (i<numChannels) && (chan->channel > data[i].channelValue);
+	     last=i++);
+	totalD = data[i].channelValue - data[last].channelValue;
+	if (totalD > 0) {
+		totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
+		*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
+
+		totalMin = ar5112GetMinPower(ah,&data[i]) - ar5112GetMinPower(ah, &data[last]);
+		*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar5112GetMinPower(ah, &data[last])*totalD)/totalD);
+		return (AH_TRUE);
+	} else {
+		if (chan->channel == data[i].channelValue) {
+			*maxPow = data[i].maxPower_t4;
+			*minPow = ar5112GetMinPower(ah, &data[i]);
+			return(AH_TRUE);
+		} else
+			return(AH_FALSE);
+	}
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar5112RfDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(ahp->ah_rfHal != AH_NULL);
+	ath_hal_free(ahp->ah_rfHal);
+	ahp->ah_rfHal = AH_NULL;
+}
+
+/*
+ * Allocate memory for analog bank scratch buffers
+ * Scratch Buffer will be reinitialized every reset so no need to zero now
+ */
+static HAL_BOOL
+ar5112RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5112State *priv;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	HALASSERT(ahp->ah_rfHal == AH_NULL);
+	priv = ath_hal_malloc(sizeof(struct ar5112State));
+	if (priv == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot allocate private state\n", __func__);
+		*status = HAL_ENOMEM;		/* XXX */
+		return AH_FALSE;
+	}
+	priv->base.rfDetach		= ar5112RfDetach;
+	priv->base.writeRegs		= ar5112WriteRegs;
+	priv->base.getRfBank		= ar5112GetRfBank;
+	priv->base.setChannel		= ar5112SetChannel;
+	priv->base.setRfRegs		= ar5112SetRfRegs;
+	priv->base.setPowerTable	= ar5112SetPowerTable;
+	priv->base.getChannelMaxMinPower = ar5112GetChannelMaxMinPower;
+	priv->base.getNfAdjust		= ar5212GetNfAdjust;
+
+	ahp->ah_pcdacTable = priv->pcdacTable;
+	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+	ahp->ah_rfHal = &priv->base;
+
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+ar5112Probe(struct ath_hal *ah)
+{
+	return IS_RAD5112(ah);
+}
+AH_RF(RF5112, ar5112Probe, ar5112RfAttach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212.h b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212.h
new file mode 100644
index 0000000..6645b76
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212.h
@@ -0,0 +1,603 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212.h,v 1.16 2008/11/22 07:42:00 sam Exp $
+ */
+#ifndef _ATH_AR5212_H_
+#define _ATH_AR5212_H_
+
+#include "ah_eeprom.h"
+
+#define	AR5212_MAGIC	0x19541014
+
+/* DCU Transmit Filter macros */
+#define CALC_MMR(dcu, idx) \
+	( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
+#define TXBLK_FROM_MMR(mmr) \
+	(AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
+#define CALC_TXBLK_ADDR(dcu, idx)	(TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
+#define CALC_TXBLK_VALUE(idx)		(1 << (idx & 0x1f))
+
+/* MAC register values */
+
+#define INIT_INTERRUPT_MASK \
+	( AR_IMR_TXERR  | AR_IMR_TXOK | AR_IMR_RXORN | \
+	  AR_IMR_RXERR  | AR_IMR_RXOK | AR_IMR_TXURN | \
+	  AR_IMR_HIUERR )
+#define INIT_BEACON_CONTROL \
+	((INIT_RESET_TSF << 24)  | (INIT_BEACON_EN << 23) | \
+	  (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD)
+
+#define INIT_CONFIG_STATUS	0x00000000
+#define INIT_RSSI_THR		0x00000781	/* Missed beacon counter initialized to 0x7 (max is 0xff) */
+#define INIT_IQCAL_LOG_COUNT_MAX	0xF
+#define INIT_BCON_CNTRL_REG	0x00000000
+
+#define INIT_USEC		40
+#define HALF_RATE_USEC		19 /* ((40 / 2) - 1 ) */
+#define QUARTER_RATE_USEC	9  /* ((40 / 4) - 1 ) */
+
+#define RX_NON_FULL_RATE_LATENCY	63
+#define TX_HALF_RATE_LATENCY		108
+#define TX_QUARTER_RATE_LATENCY		216
+
+#define IFS_SLOT_FULL_RATE	0x168 /* 9 us half, 40 MHz core clock (9*40) */
+#define IFS_SLOT_HALF_RATE	0x104 /* 13 us half, 20 MHz core clock (13*20) */
+#define IFS_SLOT_QUARTER_RATE	0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
+#define IFS_EIFS_FULL_RATE	0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
+#define IFS_EIFS_HALF_RATE	0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
+#define IFS_EIFS_QUARTER_RATE	0xD48 /* (298 + (2 * 21)) * 10MHz core clock */
+
+#define ACK_CTS_TIMEOUT_11A	0x3E8 /* ACK timeout in 11a core clocks */
+
+/* Tx frame start to tx data start delay */
+#define TX_FRAME_D_START_HALF_RATE 	0xc
+#define TX_FRAME_D_START_QUARTER_RATE 	0xd
+
+/*
+ * Various fifo fill before Tx start, in 64-byte units
+ * i.e. put the frame in the air while still DMAing
+ */
+#define MIN_TX_FIFO_THRESHOLD	0x1
+#define MAX_TX_FIFO_THRESHOLD	((IEEE80211_MAX_LEN / 64) + 1)
+#define INIT_TX_FIFO_THRESHOLD	MIN_TX_FIFO_THRESHOLD
+
+#define	HAL_DECOMP_MASK_SIZE	128	/* 1 byte per key */
+
+/*
+ * Gain support.
+ */
+#define	NUM_CORNER_FIX_BITS		4
+#define	NUM_CORNER_FIX_BITS_5112	7
+#define	DYN_ADJ_UP_MARGIN		15
+#define	DYN_ADJ_LO_MARGIN		20
+#define	PHY_PROBE_CCK_CORRECTION	5
+#define	CCK_OFDM_GAIN_DELTA		15
+
+enum GAIN_PARAMS {
+	GP_TXCLIP,
+	GP_PD90,
+	GP_PD84,
+	GP_GSEL,
+};
+
+enum GAIN_PARAMS_5112 {
+	GP_MIXGAIN_OVR,
+	GP_PWD_138,
+	GP_PWD_137,
+	GP_PWD_136,
+	GP_PWD_132,
+	GP_PWD_131,
+	GP_PWD_130,
+};
+
+typedef struct _gainOptStep {
+	int16_t	paramVal[NUM_CORNER_FIX_BITS_5112];
+	int32_t	stepGain;
+	int8_t	stepName[16];
+} GAIN_OPTIMIZATION_STEP;
+
+typedef struct {
+	uint32_t	numStepsInLadder;
+	uint32_t	defaultStepNum;
+	GAIN_OPTIMIZATION_STEP optStep[10];
+} GAIN_OPTIMIZATION_LADDER;
+
+typedef struct {
+	uint32_t	currStepNum;
+	uint32_t	currGain;
+	uint32_t	targetGain;
+	uint32_t	loTrig;
+	uint32_t	hiTrig;
+	uint32_t	gainFCorrection;
+	uint32_t	active;
+	const GAIN_OPTIMIZATION_STEP *currStep;
+} GAIN_VALUES;
+
+/* RF HAL structures */
+typedef struct RfHalFuncs {
+	void	  *priv;		/* private state */
+
+	void	  (*rfDetach)(struct ath_hal *ah);
+	void	  (*writeRegs)(struct ath_hal *,
+			u_int modeIndex, u_int freqIndex, int regWrites);
+	uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
+	HAL_BOOL  (*setChannel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+	HAL_BOOL  (*setRfRegs)(struct ath_hal *,
+		      HAL_CHANNEL_INTERNAL *, uint16_t modesIndex,
+		      uint16_t *rfXpdGain);
+	HAL_BOOL  (*setPowerTable)(struct ath_hal *ah,
+		      int16_t *minPower, int16_t *maxPower,
+		      HAL_CHANNEL_INTERNAL *, uint16_t *rfXpdGain);
+	HAL_BOOL  (*getChannelMaxMinPower)(struct ath_hal *ah, HAL_CHANNEL *,
+		      int16_t *maxPow, int16_t *minPow);
+	int16_t	  (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
+} RF_HAL_FUNCS;
+
+struct ar5212AniParams {
+	int		maxNoiseImmunityLevel;	/* [0..4] */
+	int		totalSizeDesired[5];
+	int		coarseHigh[5];
+	int		coarseLow[5];
+	int		firpwr[5];
+
+	int		maxSpurImmunityLevel;	/* [0..7] */
+	int		cycPwrThr1[8];
+
+	int		maxFirstepLevel;	/* [0..2] */
+	int		firstep[3];
+
+	uint32_t	ofdmTrigHigh;
+	uint32_t	ofdmTrigLow;
+	uint32_t	cckTrigHigh;
+	uint32_t	cckTrigLow;
+	int32_t		rssiThrLow;
+	uint32_t	rssiThrHigh;
+
+	int		period;			/* update listen period */
+
+	/* NB: intentionally ordered so data exported to user space is first */
+	uint32_t	ofdmPhyErrBase;	/* Base value for ofdm err counter */
+	uint32_t	cckPhyErrBase;	/* Base value for cck err counters */
+};
+
+/*
+ * Per-channel ANI state private to the driver.
+ */
+struct ar5212AniState {
+	uint8_t		noiseImmunityLevel;
+	uint8_t		spurImmunityLevel;
+	uint8_t		firstepLevel;
+	uint8_t		ofdmWeakSigDetectOff;
+	uint8_t		cckWeakSigThreshold;
+	uint32_t	listenTime;
+
+	/* NB: intentionally ordered so data exported to user space is first */
+	HAL_CHANNEL	c;
+	HAL_BOOL	isSetup;	/* has state to do a restore */
+	uint32_t	txFrameCount;	/* Last txFrameCount */
+	uint32_t	rxFrameCount;	/* Last rx Frame count */
+	uint32_t	cycleCount;	/* Last cycleCount
+					   (to detect wrap-around) */
+	uint32_t	ofdmPhyErrCount;/* OFDM err count since last reset */
+	uint32_t	cckPhyErrCount;	/* CCK err count since last reset */
+
+	const struct ar5212AniParams *params;
+};
+
+#define	HAL_ANI_ENA		0x00000001	/* ANI operation enabled */
+#define	HAL_RSSI_ANI_ENA	0x00000002	/* rssi-based processing ena'd*/
+
+struct ar5212Stats {
+	uint32_t	ast_ani_niup;	/* ANI increased noise immunity */
+	uint32_t	ast_ani_nidown;	/* ANI decreased noise immunity */
+	uint32_t	ast_ani_spurup;	/* ANI increased spur immunity */
+	uint32_t	ast_ani_spurdown;/* ANI descreased spur immunity */
+	uint32_t	ast_ani_ofdmon;	/* ANI OFDM weak signal detect on */
+	uint32_t	ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
+	uint32_t	ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
+	uint32_t	ast_ani_ccklow;	/* ANI CCK weak signal threshold low */
+	uint32_t	ast_ani_stepup;	/* ANI increased first step level */
+	uint32_t	ast_ani_stepdown;/* ANI decreased first step level */
+	uint32_t	ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
+	uint32_t	ast_ani_cckerrs;/* ANI cumulative cck phy err count */
+	uint32_t	ast_ani_reset;	/* ANI parameters zero'd for non-STA */
+	uint32_t	ast_ani_lzero;	/* ANI listen time forced to zero */
+	uint32_t	ast_ani_lneg;	/* ANI listen time calculated < 0 */
+	HAL_MIB_STATS	ast_mibstats;	/* MIB counter stats */
+	HAL_NODE_STATS	ast_nodestats;	/* Latest rssi stats from driver */
+};
+
+/*
+ * NF Cal history buffer
+ */
+#define	AR5212_CCA_MAX_GOOD_VALUE	-95
+#define	AR5212_CCA_MAX_HIGH_VALUE	-62
+#define	AR5212_CCA_MIN_BAD_VALUE	-125
+
+#define	AR512_NF_CAL_HIST_MAX		5
+
+struct ar5212NfCalHist {
+	int16_t		nfCalBuffer[AR512_NF_CAL_HIST_MAX];
+	int16_t		privNF;
+	uint8_t		currIndex;
+	uint8_t		first_run;
+	uint8_t		invalidNFcount;
+};
+
+struct ath_hal_5212 {
+	struct ath_hal_private	ah_priv;	/* base class */
+
+	/*
+	 * Per-chip common Initialization data.
+	 * NB: RF backends have their own ini data.
+	 */
+	HAL_INI_ARRAY	ah_ini_modes;
+	HAL_INI_ARRAY	ah_ini_common;
+
+	GAIN_VALUES	ah_gainValues;
+
+	uint8_t		ah_macaddr[IEEE80211_ADDR_LEN];
+	uint8_t		ah_bssid[IEEE80211_ADDR_LEN];
+	uint8_t		ah_bssidmask[IEEE80211_ADDR_LEN];
+
+	/*
+	 * Runtime state.
+	 */
+	uint32_t	ah_maskReg;		/* copy of AR_IMR */
+	struct ar5212Stats ah_stats;		/* various statistics */
+	RF_HAL_FUNCS	*ah_rfHal;
+	uint32_t	ah_txDescMask;		/* mask for TXDESC */
+	uint32_t	ah_txOkInterruptMask;
+	uint32_t	ah_txErrInterruptMask;
+	uint32_t	ah_txDescInterruptMask;
+	uint32_t	ah_txEolInterruptMask;
+	uint32_t	ah_txUrnInterruptMask;
+	HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
+	uint32_t	ah_intrTxqs;		/* tx q interrupt state */
+						/* decomp mask array */
+	uint8_t		ah_decompMask[HAL_DECOMP_MASK_SIZE];
+	HAL_POWER_MODE	ah_powerMode;
+	HAL_ANT_SETTING ah_antControl;		/* antenna setting */
+	HAL_BOOL	ah_diversity;		/* fast diversity setting */
+	enum {
+		IQ_CAL_INACTIVE,
+		IQ_CAL_RUNNING,
+		IQ_CAL_DONE
+	} ah_bIQCalibration;			/* IQ calibrate state */
+	HAL_RFGAIN	ah_rfgainState;		/* RF gain calibrartion state */
+	uint32_t	ah_tx6PowerInHalfDbm;	/* power output for 6Mb tx */
+	uint32_t	ah_staId1Defaults;	/* STA_ID1 default settings */
+	uint32_t	ah_miscMode;		/* MISC_MODE settings */
+	uint32_t	ah_rssiThr;		/* RSSI_THR settings */
+	HAL_BOOL	ah_cwCalRequire;	/* for ap51 */
+	HAL_BOOL	ah_tpcEnabled;		/* per-packet tpc enabled */
+	HAL_BOOL	ah_phyPowerOn;		/* PHY power state */
+	HAL_BOOL	ah_isHb63;		/* cached HB63 check */
+	uint32_t	ah_macTPC;		/* tpc register */
+	uint32_t	ah_beaconInterval;	/* XXX */
+	enum {
+		AUTO_32KHZ,		/* use it if 32kHz crystal present */
+		USE_32KHZ,		/* do it regardless */
+		DONT_USE_32KHZ,		/* don't use it regardless */
+	} ah_enable32kHzClock;			/* whether to sleep at 32kHz */
+	uint32_t	ah_ofdmTxPower;
+	int16_t		ah_txPowerIndexOffset;
+	/*
+	 * Noise floor cal histogram support.
+	 */
+	struct ar5212NfCalHist ah_nfCalHist;
+
+	u_int		ah_slottime;		/* user-specified slot time */
+	u_int		ah_acktimeout;		/* user-specified ack timeout */
+	u_int		ah_ctstimeout;		/* user-specified cts timeout */
+	u_int		ah_sifstime;		/* user-specified sifs time */
+	/*
+	 * RF Silent handling; setup according to the EEPROM.
+	 */
+	uint32_t	ah_gpioSelect;		/* GPIO pin to use */
+	uint32_t	ah_polarity;		/* polarity to disable RF */
+	uint32_t	ah_gpioBit;		/* after init, prev value */
+	/*
+	 * ANI support.
+	 */
+	uint32_t	ah_procPhyErr;		/* Process Phy errs */
+	HAL_BOOL	ah_hasHwPhyCounters;	/* Hardware has phy counters */
+	struct ar5212AniParams ah_aniParams24;	/* 2.4GHz parameters */
+	struct ar5212AniParams ah_aniParams5;	/* 5GHz parameters */
+	struct ar5212AniState	*ah_curani;	/* cached last reference */
+	struct ar5212AniState	ah_ani[64];	/* per-channel state */
+
+	/*
+	 * Transmit power state.  Note these are maintained
+	 * here so they can be retrieved by diagnostic tools.
+	 */
+	uint16_t	*ah_pcdacTable;
+	u_int		ah_pcdacTableSize;
+	uint16_t	ah_ratesArray[16];
+};
+#define	AH5212(_ah)	((struct ath_hal_5212 *)(_ah))
+
+/*
+ * IS_XXXX macros test the MAC version
+ * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G)
+ *
+ * Some single chip radios have equivalent radio/RF (e.g. 5112)
+ * for those use IS_RADXXX_ANY macros.
+ */
+#define IS_2317(ah) \
+	((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \
+	 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2))
+#define	IS_2316(ah) \
+	(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415)
+#define	IS_2413(ah) \
+	(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))
+#define IS_5424(ah) \
+	(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \
+	(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \
+	  AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))
+#define IS_5413(ah) \
+	(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))
+#define IS_2425(ah) \
+	(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425)
+#define IS_2417(ah) \
+	((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)
+#define IS_HB63(ah)		(AH5212(ah)->ah_isHb63 == AH_TRUE)
+
+#define IS_PCIE(ah) (IS_5424(ah) || IS_2425(ah))
+
+#define	AH_RADIO_MAJOR(ah) \
+	(AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)
+#define	AH_RADIO_MINOR(ah) \
+	(AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR)
+#define	IS_RAD5111(ah) \
+	(AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \
+	 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR)
+#define	IS_RAD5112(ah) \
+	(AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \
+	 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR)
+/* NB: does not include 5413 as Atheros' IS_5112 macro does */
+#define	IS_RAD5112_ANY(ah) \
+	(AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \
+	 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR)
+#define	IS_RAD5112_REV1(ah) \
+	(IS_RAD5112(ah) && \
+	 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR))
+#define IS_RADX112_REV2(ah) \
+	(AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \
+	 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \
+	 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \
+	 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1)
+
+#define	ar5212RfDetach(ah) do {				\
+	if (AH5212(ah)->ah_rfHal != AH_NULL)		\
+		AH5212(ah)->ah_rfHal->rfDetach(ah);	\
+} while (0)
+#define	ar5212GetRfBank(ah, b) \
+	AH5212(ah)->ah_rfHal->getRfBank(ah, b)
+
+/*
+ * Hack macros for Nala/San: 11b is handled
+ * using 11g; flip the channel flags to accomplish this.
+ */
+#define SAVE_CCK(_ah, _chan, _flag) do {			\
+	if ((IS_2425(_ah) || IS_2417(_ah)) &&			\
+	    (((_chan)->channelFlags) & CHANNEL_CCK)) {		\
+		(_chan)->channelFlags &= ~CHANNEL_CCK;		\
+		(_chan)->channelFlags |= CHANNEL_OFDM;		\
+		(_flag) = AH_TRUE;				\
+	}							\
+} while (0)
+#define RESTORE_CCK(_ah, _chan, _flag) do {                     \
+	if ((IS_2425(_ah) || IS_2417(_ah)) && (_flag) == AH_TRUE) {\
+		(_chan)->channelFlags &= ~CHANNEL_OFDM;		\
+		(_chan)->channelFlags |= CHANNEL_CCK;		\
+	}							\
+} while (0)
+
+struct ath_hal;
+
+extern	uint32_t ar5212GetRadioRev(struct ath_hal *ah);
+extern	void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC,
+		HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
+extern	void ar5212Detach(struct ath_hal *ah);
+extern  HAL_BOOL ar5212ChipTest(struct ath_hal *ah);
+extern  HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah,
+                uint16_t flags, uint16_t *low, uint16_t *high);
+extern	HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah);
+
+extern	void ar5212SetBeaconTimers(struct ath_hal *ah,
+		const HAL_BEACON_TIMERS *);
+extern	void ar5212BeaconInit(struct ath_hal *ah,
+		uint32_t next_beacon, uint32_t beacon_period);
+extern	void ar5212ResetStaBeaconTimers(struct ath_hal *ah);
+extern	void ar5212SetStaBeaconTimers(struct ath_hal *ah,
+		const HAL_BEACON_STATE *);
+
+extern	HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah);
+extern	HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
+extern	HAL_INT ar5212GetInterrupts(struct ath_hal *ah);
+extern	HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints);
+
+extern	uint32_t ar5212GetKeyCacheSize(struct ath_hal *);
+extern	HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry);
+extern	HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
+extern	HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *,
+			uint16_t entry, const uint8_t *mac);
+extern	HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
+                       const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
+
+extern	void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac);
+extern	HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *);
+extern	void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac);
+extern	HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *);
+extern	HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data);
+extern	HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data);
+extern	HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
+		uint16_t regDomain, HAL_STATUS *stats);
+extern	u_int ar5212GetWirelessModes(struct ath_hal *ah);
+extern	void ar5212EnableRfKill(struct ath_hal *);
+extern	HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
+extern	uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
+extern	void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
+extern	void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
+extern	void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,
+		uint16_t assocId);
+extern	uint32_t ar5212GetTsf32(struct ath_hal *ah);
+extern	uint64_t ar5212GetTsf64(struct ath_hal *ah);
+extern	void ar5212ResetTsf(struct ath_hal *ah);
+extern	void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);
+extern	uint32_t ar5212GetRandomSeed(struct ath_hal *ah);
+extern	HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah);
+extern	void ar5212EnableMibCounters(struct ath_hal *);
+extern	void ar5212DisableMibCounters(struct ath_hal *);
+extern	void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);
+extern	HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah);
+extern	uint32_t ar5212GetCurRssi(struct ath_hal *ah);
+extern	u_int ar5212GetDefAntenna(struct ath_hal *ah);
+extern	void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna);
+extern	HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *);
+extern	HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
+extern	HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah);
+extern	HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int);
+extern	u_int ar5212GetSifsTime(struct ath_hal *);
+extern	HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int);
+extern	u_int ar5212GetSlotTime(struct ath_hal *);
+extern	HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int);
+extern	u_int ar5212GetAckTimeout(struct ath_hal *);
+extern	HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int);
+extern	u_int ar5212GetAckCTSRate(struct ath_hal *);
+extern	HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int);
+extern	u_int ar5212GetCTSTimeout(struct ath_hal *);
+extern  HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int);
+void 	ar5212SetCoverageClass(struct ath_hal *, uint8_t, int);
+extern	void ar5212SetPCUConfig(struct ath_hal *);
+extern	HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);
+extern	void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
+extern	void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
+extern	int16_t ar5212GetNfAdjust(struct ath_hal *,
+		const HAL_CHANNEL_INTERNAL *);
+extern	void ar5212SetCompRegs(struct ath_hal *ah);
+extern	HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
+		uint32_t, uint32_t *);
+extern	HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
+		uint32_t, uint32_t, HAL_STATUS *);
+extern	HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,
+		const void *args, uint32_t argsize,
+		void **result, uint32_t *resultsize);
+
+extern	HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
+		int setChip);
+extern	HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);
+extern	HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);
+
+extern	uint32_t ar5212GetRxDP(struct ath_hal *ath);
+extern	void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp);
+extern	void ar5212EnableReceive(struct ath_hal *ah);
+extern	HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);
+extern	void ar5212StartPcuReceive(struct ath_hal *ah);
+extern	void ar5212StopPcuReceive(struct ath_hal *ah);
+extern	void ar5212SetMulticastFilter(struct ath_hal *ah,
+		uint32_t filter0, uint32_t filter1);
+extern	HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix);
+extern	HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix);
+extern	uint32_t ar5212GetRxFilter(struct ath_hal *ah);
+extern	void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits);
+extern	HAL_BOOL ar5212SetupRxDesc(struct ath_hal *,
+		struct ath_desc *, uint32_t size, u_int flags);
+extern	HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
+		uint32_t, struct ath_desc *, uint64_t,
+		struct ath_rx_status *);
+
+extern	HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
+		HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status);
+extern	HAL_BOOL ar5212SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+extern	void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
+extern	HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);
+extern	HAL_BOOL ar5212Disable(struct ath_hal *ah);
+extern	HAL_BOOL ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *);
+extern	HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan,
+		HAL_BOOL *isIQdone);
+extern	HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
+		u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
+extern	HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
+extern	int16_t ar5212GetNoiseFloor(struct ath_hal *ah);
+extern	void ar5212InitNfCalHistBuffer(struct ath_hal *);
+extern	int16_t ar5212GetNfHistMid(const int16_t calData[]);
+extern	void ar5212SetSpurMitigation(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+extern	HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,
+		HAL_ANT_SETTING settings, const HAL_CHANNEL_INTERNAL *ichan);
+extern	HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
+extern	HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,
+					  HAL_CHANNEL *chans, uint32_t nchans);
+extern	void ar5212InitializeGainValues(struct ath_hal *);
+extern	HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);
+extern	void ar5212RequestRfgain(struct ath_hal *);
+
+extern	HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *,
+		HAL_BOOL IncTrigLevel);
+extern  HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q,
+		const HAL_TXQ_INFO *qInfo);
+extern	HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q,
+		HAL_TXQ_INFO *qInfo);
+extern	int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
+		const HAL_TXQ_INFO *qInfo);
+extern	HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q);
+extern	HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q);
+extern	uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q);
+extern	HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);
+extern	HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q);
+extern	uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q);
+extern	HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q);
+extern	HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+		u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
+		u_int txRate0, u_int txTries0,
+		u_int keyIx, u_int antMode, u_int flags,
+		u_int rtsctsRate, u_int rtsctsDuration,
+		u_int compicvLen, u_int compivLen, u_int comp);
+extern	HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *,
+		u_int txRate1, u_int txRetries1,
+		u_int txRate2, u_int txRetries2,
+		u_int txRate3, u_int txRetries3);
+extern	HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+		u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
+		const struct ath_desc *ds0);
+extern	HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,
+		struct ath_desc *, struct ath_tx_status *);
+extern  void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
+extern  void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
+
+extern	const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode);
+
+extern	void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *,
+		const struct ar5212AniParams *, HAL_BOOL ena);
+extern	void ar5212AniDetach(struct ath_hal *);
+extern	struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *);
+extern	struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *);
+extern	HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param);
+extern	HAL_BOOL ar5212AniSetParams(struct ath_hal *,
+		const struct ar5212AniParams *, const struct ar5212AniParams *);
+struct ath_rx_status;
+extern	void ar5212AniPhyErrReport(struct ath_hal *ah,
+		const struct ath_rx_status *rs);
+extern	void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
+extern	void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
+			     HAL_CHANNEL *);
+extern	void ar5212AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *,
+		HAL_OPMODE, int);
+#endif	/* _ATH_AR5212_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212.ini b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212.ini
new file mode 100644
index 0000000..d53dbe2
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212.ini
@@ -0,0 +1,2171 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212.ini,v 1.3 2008/11/10 04:08:03 sam Exp $
+ */
+/* Auto Generated PCI Register Writes.  Created: 09/01/04 */
+
+#ifdef AH_5212_COMMON
+static const uint32_t ar5212Modes[][6] = {
+    { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x00001064, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
+    { 0x00001030, 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 },
+    { 0x00001070, 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 },
+    { 0x000010b0, 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 },
+    { 0x000010f0, 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 },
+    { 0x00008014, 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 },
+    { 0x00009804, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 },
+    { 0x00009820, 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 },
+    { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e },
+    { 0x00009844, 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 },
+    { 0x00009860, 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 },
+    { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+    { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
+    { 0x00009918, 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 },
+    { 0x00009924, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 },
+    { 0x0000a230, 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 },
+};
+#endif /* AH_5212_COMMON */
+
+#ifdef AH_5212_5111
+static const uint32_t ar5212Modes_5111[][6] = {
+    { 0x00000030, 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 },
+    { 0x0000801c, 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009838, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b },
+    { 0x00009848, 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 },
+    { 0x00009850, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 },
+    { 0x00009858, 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e },
+    { 0x0000985c, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 },
+    { 0x00009914, 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 },
+    { 0x00009944, 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 },
+    { 0x0000a20c, 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a },
+};
+#endif /* AH_5212_5111 */
+
+#ifdef AH_5212_5112
+static const uint32_t ar5212Modes_5112[][6] = {
+    { 0x00000030, 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 },
+    { 0x0000801c, 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009838, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b },
+    { 0x00009848, 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 },
+    { 0x00009850, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 },
+    { 0x00009858, 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e },
+    { 0x0000985c, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 },
+    { 0x00009944, 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 },
+    { 0x0000a204, 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 },
+    { 0x0000a208, 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 },
+    { 0x0000a20c, 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a },
+};
+#endif /* AH_5212_5112 */
+
+#ifdef AH_5212_2413
+static const uint32_t ar5212Modes_2413[][6] = {
+    { 0x00000030, 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 },
+    { 0x0000801c, 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 },
+    { 0x00009838, 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a },
+    { 0x00009848, 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 },
+    { 0x00009850, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da },
+    { 0x00009858, 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e },
+    { 0x0000985c, 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 },
+    { 0x00009944, 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 },
+    { 0x0000a204, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a208, 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 },
+    { 0x0000a20c, 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a },
+};
+#endif /* AH_5212_2413 */
+
+#ifdef AH_5212_2316
+static const uint32_t ar5212Modes_2316[][6] = {
+    { 0x00000030, 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 },
+    { 0x0000801c, 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 },
+    { 0x00009838, 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a },
+    { 0x00009848, 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 },
+    { 0x00009850, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da },
+    { 0x00009858, 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e },
+    { 0x0000985c, 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 },
+    { 0x00009944, 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 },
+    { 0x0000a204, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a208, 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 },
+    { 0x0000a20c, 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a },
+};
+#endif
+
+#ifdef AH_5212_5413
+static const uint32_t ar5212Modes_5413[][6] = {
+    { 0x00000030, 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 },
+    { 0x0000801c, 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009838, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b },
+    { 0x00009848, 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 },
+    { 0x00009850, 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da },
+    { 0x00009858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e },
+    { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 },
+    { 0x00009944, 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 },
+    { 0x0000a204, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a208, 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 },
+    { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a },
+    { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
+    { 0x0000a304, 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 },
+    { 0x0000a308, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 },
+    { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a },
+    { 0x0000a310, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f },
+    { 0x0000a314, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b },
+    { 0x0000a318, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a },
+    { 0x0000a31c, 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b },
+    { 0x0000a320, 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f },
+    { 0x0000a324, 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f },
+    { 0x0000a328, 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f },
+    { 0x0000a32c, 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f },
+    { 0x0000a330, 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f },
+    { 0x0000a334, 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf },
+};
+#endif /* AH_5212_5413 */
+
+#ifdef AH_5212_2425
+static const uint32_t ar5212Modes_2425[][6] = {
+    { 0x00000030, 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 },
+    { 0x0000801c, 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf },
+    { 0x00009804, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009838, 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b },
+    { 0x00009844, 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 },
+    { 0x00009848, 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 },
+    { 0x00009850, 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da },
+    { 0x00009858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e },
+    { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 },
+    { 0x00009944, 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 },
+    { 0x0000a204, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a208, 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 },
+    { 0x0000a20c, 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a },
+    { 0x0000a324, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf },
+    { 0x0000a328, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf },
+    { 0x0000a32c, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf },
+    { 0x0000a330, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf },
+    { 0x0000a334, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf },
+};
+#endif /* AH_5212_2425 */
+
+#ifdef AH_5212_COMMON
+static const uint32_t ar5212Common[][2] = {
+    { 0x0000000c, 0x00000000 },
+    { 0x00000034, 0x00000005 },
+    { 0x00000040, 0x00000000 },
+    { 0x00000044, 0x00000008 },
+    { 0x00000048, 0x00000008 },
+    { 0x0000004c, 0x00000010 },
+    { 0x00000050, 0x00000000 },
+    { 0x00000054, 0x0000001f },
+    { 0x00000800, 0x00000000 },
+    { 0x00000804, 0x00000000 },
+    { 0x00000808, 0x00000000 },
+    { 0x0000080c, 0x00000000 },
+    { 0x00000810, 0x00000000 },
+    { 0x00000814, 0x00000000 },
+    { 0x00000818, 0x00000000 },
+    { 0x0000081c, 0x00000000 },
+    { 0x00000820, 0x00000000 },
+    { 0x00000824, 0x00000000 },
+    { 0x00001270, 0x00000000 },
+    { 0x00001038, 0x00000000 },
+    { 0x00001078, 0x00000000 },
+    { 0x000010b8, 0x00000000 },
+    { 0x000010f8, 0x00000000 },
+    { 0x00001138, 0x00000000 },
+    { 0x00001178, 0x00000000 },
+    { 0x000011b8, 0x00000000 },
+    { 0x000011f8, 0x00000000 },
+    { 0x00001238, 0x00000000 },
+    { 0x00001278, 0x00000000 },
+    { 0x000012b8, 0x00000000 },
+    { 0x000012f8, 0x00000000 },
+    { 0x00001338, 0x00000000 },
+    { 0x00001378, 0x00000000 },
+    { 0x000013b8, 0x00000000 },
+    { 0x000013f8, 0x00000000 },
+    { 0x00001438, 0x00000000 },
+    { 0x00001478, 0x00000000 },
+    { 0x000014b8, 0x00000000 },
+    { 0x000014f8, 0x00000000 },
+    { 0x00001538, 0x00000000 },
+    { 0x00001578, 0x00000000 },
+    { 0x000015b8, 0x00000000 },
+    { 0x000015f8, 0x00000000 },
+    { 0x00001638, 0x00000000 },
+    { 0x00001678, 0x00000000 },
+    { 0x000016b8, 0x00000000 },
+    { 0x000016f8, 0x00000000 },
+    { 0x00001738, 0x00000000 },
+    { 0x00001778, 0x00000000 },
+    { 0x000017b8, 0x00000000 },
+    { 0x000017f8, 0x00000000 },
+    { 0x0000103c, 0x00000000 },
+    { 0x0000107c, 0x00000000 },
+    { 0x000010bc, 0x00000000 },
+    { 0x000010fc, 0x00000000 },
+    { 0x0000113c, 0x00000000 },
+    { 0x0000117c, 0x00000000 },
+    { 0x000011bc, 0x00000000 },
+    { 0x000011fc, 0x00000000 },
+    { 0x0000123c, 0x00000000 },
+    { 0x0000127c, 0x00000000 },
+    { 0x000012bc, 0x00000000 },
+    { 0x000012fc, 0x00000000 },
+    { 0x0000133c, 0x00000000 },
+    { 0x0000137c, 0x00000000 },
+    { 0x000013bc, 0x00000000 },
+    { 0x000013fc, 0x00000000 },
+    { 0x0000143c, 0x00000000 },
+    { 0x0000147c, 0x00000000 },
+    { 0x00008004, 0x00000000 },
+    { 0x00008008, 0x00000000 },
+    { 0x0000800c, 0x00000000 },
+    { 0x00008020, 0x00000000 },
+    { 0x00008024, 0x00000000 },
+    { 0x00008028, 0x00000030 },
+    { 0x0000802c, 0x0007ffff },
+    { 0x00008030, 0x01ffffff },
+    { 0x00008034, 0x00000031 },
+    { 0x00008038, 0x00000000 },
+    { 0x0000803c, 0x00000000 },
+    { 0x00008048, 0x00000000 },
+    { 0x00008054, 0x00000000 },
+    { 0x00008058, 0x00000000 },
+    { 0x0000805c, 0x000fc78f },
+    { 0x000080c0, 0x2a82301a },
+    { 0x000080c4, 0x05dc01e0 },
+    { 0x000080c8, 0x1f402710 },
+    { 0x000080cc, 0x01f40000 },
+    { 0x000080d0, 0x00001e1c },
+    { 0x000080d4, 0x0002aaaa },
+    { 0x000080d8, 0x02005555 },
+    { 0x000080dc, 0x00000000 },
+    { 0x000080e0, 0xffffffff },
+    { 0x000080e4, 0x0000ffff },
+    { 0x000080e8, 0x00000000 },
+    { 0x000080ec, 0x00000000 },
+    { 0x000080f0, 0x00000000 },
+    { 0x000080f4, 0x00000000 },
+    { 0x000080f8, 0x00000000 },
+    { 0x000080fc, 0x00000088 },
+    { 0x00008700, 0x00000000 },
+    { 0x00008704, 0x0000008c },
+    { 0x00008708, 0x000000e4 },
+    { 0x0000870c, 0x000002d5 },
+    { 0x00008710, 0x00000000 },
+    { 0x00008714, 0x00000000 },
+    { 0x00008718, 0x000000a0 },
+    { 0x0000871c, 0x000001c9 },
+    { 0x00008720, 0x0000002c },
+    { 0x00008724, 0x0000002c },
+    { 0x00008728, 0x00000030 },
+    { 0x0000872c, 0x0000003c },
+    { 0x00008730, 0x0000002c },
+    { 0x00008734, 0x0000002c },
+    { 0x00008738, 0x00000030 },
+    { 0x0000873c, 0x0000003c },
+    { 0x00008740, 0x00000000 },
+    { 0x00008744, 0x00000000 },
+    { 0x00008748, 0x00000000 },
+    { 0x0000874c, 0x00000000 },
+    { 0x00008750, 0x00000000 },
+    { 0x00008754, 0x00000000 },
+    { 0x00008758, 0x00000000 },
+    { 0x0000875c, 0x00000000 },
+    { 0x00008760, 0x000000d5 },
+    { 0x00008764, 0x000000df },
+    { 0x00008768, 0x00000102 },
+    { 0x0000876c, 0x0000013a },
+    { 0x00008770, 0x00000075 },
+    { 0x00008774, 0x0000007f },
+    { 0x00008778, 0x000000a2 },
+    { 0x0000877c, 0x00000000 },
+    { 0x00008100, 0x00010002 },
+    { 0x00008104, 0x00000001 },
+    { 0x00008108, 0x000000c0 },
+    { 0x0000810c, 0x00000000 },
+    { 0x00008110, 0x00000168 },
+    { 0x00008114, 0x00000000 },
+    { 0x000087c0, 0x03020100 },
+    { 0x000087c4, 0x07060504 },
+    { 0x000087c8, 0x0b0a0908 },
+    { 0x000087cc, 0x0f0e0d0c },
+    { 0x000087d0, 0x13121110 },
+    { 0x000087d4, 0x17161514 },
+    { 0x000087d8, 0x1b1a1918 },
+    { 0x000087dc, 0x1f1e1d1c },
+    { 0x000087e0, 0x03020100 },
+    { 0x000087e4, 0x07060504 },
+    { 0x000087e8, 0x0b0a0908 },
+    { 0x000087ec, 0x0f0e0d0c },
+    { 0x000087f0, 0x13121110 },
+    { 0x000087f4, 0x17161514 },
+    { 0x000087f8, 0x1b1a1918 },
+    { 0x000087fc, 0x1f1e1d1c },
+    { 0x0000980c, 0xad848e19 },
+    { 0x00009810, 0x7d28e000 },
+    { 0x00009814, 0x9c0a9f6b },
+    { 0x0000981c, 0x00000000 },
+    { 0x00009840, 0x206a017a },
+    { 0x00009854, 0x00000859 },
+    { 0x00009900, 0x00000000 },
+    { 0x00009904, 0x00000000 },
+    { 0x00009908, 0x00000000 },
+    { 0x0000990c, 0x00800000 },
+    { 0x00009910, 0x00000001 },
+    { 0x0000991c, 0x00000c80 },
+    { 0x00009920, 0x05100000 },
+    { 0x00009928, 0x00000001 },
+    { 0x0000992c, 0x00000004 },
+    { 0x00009934, 0x1e1f2022 },
+    { 0x00009938, 0x0a0b0c0d },
+    { 0x0000993c, 0x0000003f },
+    { 0x00009948, 0x9280b212 },
+    { 0x00009954, 0x5d50e188 },
+    { 0x0000995c, 0x004b6a8e },
+    { 0x00009968, 0x000003ce },
+    { 0x00009970, 0x192fb515 },
+    { 0x00009978, 0x00000001 },
+    { 0x0000997c, 0x00000000 },
+    { 0x0000a210, 0x00806333 },
+    { 0x0000a214, 0x00106c10 },
+    { 0x0000a218, 0x009c4060 },
+    { 0x0000a220, 0x018830c6 },
+    { 0x0000a224, 0x00000400 },
+    { 0x0000a22c, 0x00000000 },
+    { 0x0000a234, 0x20202020 },
+    { 0x0000a238, 0x20202020 },
+    { 0x0000a240, 0x38490a20 },
+    { 0x0000a244, 0x00007bb6 },
+    { 0x0000a248, 0x0fff3ffc },
+    { 0x00009b00, 0x00000000 },
+    { 0x00009b28, 0x0000000c },
+    { 0x00009b38, 0x00000012 },
+    { 0x00009b64, 0x00000021 },
+    { 0x00009b8c, 0x0000002d },
+    { 0x00009b9c, 0x00000033 },
+};
+#endif /* AH_5212_COMMON */
+
+#ifdef AH_5212_5111
+static const uint32_t ar5212Common_5111[][2] = {
+    { 0x00001230, 0x00000000 },
+    { 0x00009808, 0x00000000 },
+    { 0x0000982c, 0x00022ffe },
+    { 0x0000983c, 0x00020100 },
+    { 0x0000984c, 0x1284613c },
+    { 0x00009930, 0x00004883 },
+    { 0x00009940, 0x00000004 },
+    { 0x00009958, 0x000000ff },
+    { 0x00009974, 0x00000000 },
+    { 0x000099f8, 0x00000018 },
+    { 0x0000a204, 0x00000000 },
+    { 0x0000a208, 0xd03e6788 },
+    { 0x0000a228, 0x000001b5 },
+    { 0x0000a23c, 0x13c889af },
+    { 0x00009b04, 0x00000020 },
+    { 0x00009b08, 0x00000010 },
+    { 0x00009b0c, 0x00000030 },
+    { 0x00009b10, 0x00000008 },
+    { 0x00009b14, 0x00000028 },
+    { 0x00009b18, 0x00000004 },
+    { 0x00009b1c, 0x00000024 },
+    { 0x00009b20, 0x00000014 },
+    { 0x00009b24, 0x00000034 },
+    { 0x00009b2c, 0x0000002c },
+    { 0x00009b30, 0x00000002 },
+    { 0x00009b34, 0x00000022 },
+    { 0x00009b3c, 0x00000032 },
+    { 0x00009b40, 0x0000000a },
+    { 0x00009b44, 0x0000002a },
+    { 0x00009b48, 0x00000006 },
+    { 0x00009b4c, 0x00000026 },
+    { 0x00009b50, 0x00000016 },
+    { 0x00009b54, 0x00000036 },
+    { 0x00009b58, 0x0000000e },
+    { 0x00009b5c, 0x0000002e },
+    { 0x00009b60, 0x00000001 },
+    { 0x00009b68, 0x00000011 },
+    { 0x00009b6c, 0x00000031 },
+    { 0x00009b70, 0x00000009 },
+    { 0x00009b74, 0x00000029 },
+    { 0x00009b78, 0x00000005 },
+    { 0x00009b7c, 0x00000025 },
+    { 0x00009b80, 0x00000015 },
+    { 0x00009b84, 0x00000035 },
+    { 0x00009b88, 0x0000000d },
+    { 0x00009b90, 0x00000003 },
+    { 0x00009b94, 0x00000023 },
+    { 0x00009b98, 0x00000013 },
+    { 0x00009ba0, 0x0000000b },
+    { 0x00009ba4, 0x0000002b },
+    { 0x00009ba8, 0x0000002b },
+    { 0x00009bac, 0x0000002b },
+    { 0x00009bb0, 0x0000002b },
+    { 0x00009bb4, 0x0000002b },
+    { 0x00009bb8, 0x0000002b },
+    { 0x00009bbc, 0x0000002b },
+    { 0x00009bc0, 0x0000002b },
+    { 0x00009bc4, 0x0000002b },
+    { 0x00009bc8, 0x0000002b },
+    { 0x00009bcc, 0x0000002b },
+    { 0x00009bd0, 0x0000002b },
+    { 0x00009bd4, 0x0000002b },
+    { 0x00009bd8, 0x0000002b },
+    { 0x00009bdc, 0x0000002b },
+    { 0x00009be0, 0x0000002b },
+    { 0x00009be4, 0x0000002b },
+    { 0x00009be8, 0x0000002b },
+    { 0x00009bec, 0x0000002b },
+    { 0x00009bf0, 0x0000002b },
+    { 0x00009bf4, 0x0000002b },
+    { 0x00009bf8, 0x00000002 },
+    { 0x00009bfc, 0x00000016 },
+};
+#endif /* AH_5212_5111 */
+
+#ifdef AH_5212_5112
+static const uint32_t ar5212Common_5112[][2] = {
+    { 0x00001230, 0x00000000 },
+    { 0x00009808, 0x00000000 },
+    { 0x0000982c, 0x00022ffe },
+    { 0x0000983c, 0x00020100 },
+    { 0x0000984c, 0x1284613c },
+    { 0x00009930, 0x00004882 },
+    { 0x00009940, 0x00000004 },
+    { 0x00009958, 0x000000ff },
+    { 0x00009974, 0x00000000 },
+    { 0x0000a228, 0x000001b5 },
+    { 0x0000a23c, 0x13c889af },
+    { 0x00009b04, 0x00000001 },
+    { 0x00009b08, 0x00000002 },
+    { 0x00009b0c, 0x00000003 },
+    { 0x00009b10, 0x00000004 },
+    { 0x00009b14, 0x00000005 },
+    { 0x00009b18, 0x00000008 },
+    { 0x00009b1c, 0x00000009 },
+    { 0x00009b20, 0x0000000a },
+    { 0x00009b24, 0x0000000b },
+    { 0x00009b2c, 0x0000000d },
+    { 0x00009b30, 0x00000010 },
+    { 0x00009b34, 0x00000011 },
+    { 0x00009b3c, 0x00000013 },
+    { 0x00009b40, 0x00000014 },
+    { 0x00009b44, 0x00000015 },
+    { 0x00009b48, 0x00000018 },
+    { 0x00009b4c, 0x00000019 },
+    { 0x00009b50, 0x0000001a },
+    { 0x00009b54, 0x0000001b },
+    { 0x00009b58, 0x0000001c },
+    { 0x00009b5c, 0x0000001d },
+    { 0x00009b60, 0x00000020 },
+    { 0x00009b68, 0x00000022 },
+    { 0x00009b6c, 0x00000023 },
+    { 0x00009b70, 0x00000024 },
+    { 0x00009b74, 0x00000025 },
+    { 0x00009b78, 0x00000028 },
+    { 0x00009b7c, 0x00000029 },
+    { 0x00009b80, 0x0000002a },
+    { 0x00009b84, 0x0000002b },
+    { 0x00009b88, 0x0000002c },
+    { 0x00009b90, 0x00000030 },
+    { 0x00009b94, 0x00000031 },
+    { 0x00009b98, 0x00000032 },
+    { 0x00009ba0, 0x00000034 },
+    { 0x00009ba4, 0x00000035 },
+    { 0x00009ba8, 0x00000035 },
+    { 0x00009bac, 0x00000035 },
+    { 0x00009bb0, 0x00000035 },
+    { 0x00009bb4, 0x00000035 },
+    { 0x00009bb8, 0x00000035 },
+    { 0x00009bbc, 0x00000035 },
+    { 0x00009bc0, 0x00000035 },
+    { 0x00009bc4, 0x00000035 },
+    { 0x00009bc8, 0x00000035 },
+    { 0x00009bcc, 0x00000035 },
+    { 0x00009bd0, 0x00000035 },
+    { 0x00009bd4, 0x00000035 },
+    { 0x00009bd8, 0x00000035 },
+    { 0x00009bdc, 0x00000035 },
+    { 0x00009be0, 0x00000035 },
+    { 0x00009be4, 0x00000035 },
+    { 0x00009be8, 0x00000035 },
+    { 0x00009bec, 0x00000035 },
+    { 0x00009bf0, 0x00000035 },
+    { 0x00009bf4, 0x00000035 },
+    { 0x00009bf8, 0x00000010 },
+    { 0x00009bfc, 0x0000001a },
+};
+#endif /* AH_5212_5112 */
+
+#ifdef AH_5212_2413
+static const uint32_t ar5212Common_2413[][2] = {
+    { 0x00001230, 0x000003e0 },
+    { 0x00008060, 0x0000000f },
+    { 0x00008118, 0x00000000 },
+    { 0x0000811c, 0x00000000 },
+    { 0x00008120, 0x00000000 },
+    { 0x00008124, 0x00000000 },
+    { 0x00008128, 0x00000000 },
+    { 0x0000812c, 0x00000000 },
+    { 0x00008130, 0x00000000 },
+    { 0x00008134, 0x00000000 },
+    { 0x00008138, 0x00000000 },
+    { 0x0000813c, 0x00000000 },
+    { 0x00008140, 0x800000a8 },
+    { 0x00008144, 0x00000000 },
+    { 0x00009808, 0x00000000 },
+    { 0x0000982c, 0x0000a000 },
+    { 0x0000983c, 0x00200400 },
+    { 0x0000984c, 0x1284233c },
+    { 0x00009870, 0x0000001f },
+    { 0x00009874, 0x00000080 },
+    { 0x00009878, 0x0000000e },
+    { 0x00009958, 0x000000ff },
+    { 0x00009980, 0x00000000 },
+    { 0x00009984, 0x02800000 },
+    { 0x000099a0, 0x00000000 },
+    { 0x000099e0, 0x00000000 },
+    { 0x000099e4, 0xaaaaaaaa },
+    { 0x000099e8, 0x3c466478 },
+    { 0x000099ec, 0x000000aa },
+    { 0x000099f0, 0x0000000c },
+    { 0x000099f4, 0x000000ff },
+    { 0x000099f8, 0x00000014 },
+    { 0x0000a228, 0x000009b5 },
+    { 0x0000a23c, 0x93c889af },
+    { 0x0000a24c, 0x00000001 },
+    { 0x0000a250, 0x0000a000 },
+    { 0x0000a254, 0x00000000 },
+    { 0x0000a258, 0x0cc75380 },
+    { 0x0000a25c, 0x0f0f0f01 },
+    { 0x0000a260, 0x5f690f01 },
+    { 0x0000a264, 0x00418a11 },
+    { 0x0000a268, 0x00000000 },
+    { 0x0000a26c, 0x0c30c16a },
+    { 0x0000a270, 0x00820820 },
+    { 0x0000a274, 0x001b7caa },
+    { 0x0000a278, 0x1ce739ce },
+    { 0x0000a27c, 0x051701ce },
+    { 0x0000a300, 0x18010000 },
+    { 0x0000a304, 0x30032602 },
+    { 0x0000a308, 0x48073e06 },
+    { 0x0000a30c, 0x560b4c0a },
+    { 0x0000a310, 0x641a600f },
+    { 0x0000a314, 0x784f6e1b },
+    { 0x0000a318, 0x868f7c5a },
+    { 0x0000a31c, 0x8ecf865b },
+    { 0x0000a320, 0x9d4f970f },
+    { 0x0000a324, 0xa5cfa18f },
+    { 0x0000a328, 0xb55faf1f },
+    { 0x0000a32c, 0xbddfb99f },
+    { 0x0000a330, 0xcd7fc73f },
+    { 0x0000a334, 0xd5ffd1bf },
+    { 0x0000a338, 0x00000000 },
+    { 0x0000a33c, 0x00000000 },
+    { 0x0000a340, 0x00000000 },
+    { 0x0000a344, 0x00000000 },
+    { 0x0000a348, 0x3fffffff },
+    { 0x0000a34c, 0x3fffffff },
+    { 0x0000a350, 0x3fffffff },
+    { 0x0000a354, 0x0003ffff },
+    { 0x0000a358, 0x79a8aa1f },
+    { 0x0000a35c, 0x066c420f },
+    { 0x0000a360, 0x0f282207 },
+    { 0x0000a364, 0x17601685 },
+    { 0x0000a368, 0x1f801104 },
+    { 0x0000a36c, 0x37a00c03 },
+    { 0x0000a370, 0x3fc40883 },
+    { 0x0000a374, 0x57c00803 },
+    { 0x0000a378, 0x5fd80682 },
+    { 0x0000a37c, 0x7fe00482 },
+    { 0x0000a380, 0x7f3c7bba },
+    { 0x0000a384, 0xf3307ff0 },
+    { 0x00009b04, 0x00000001 },
+    { 0x00009b08, 0x00000002 },
+    { 0x00009b0c, 0x00000003 },
+    { 0x00009b10, 0x00000004 },
+    { 0x00009b14, 0x00000005 },
+    { 0x00009b18, 0x00000008 },
+    { 0x00009b1c, 0x00000009 },
+    { 0x00009b20, 0x0000000a },
+    { 0x00009b24, 0x0000000b },
+    { 0x00009b2c, 0x0000000d },
+    { 0x00009b30, 0x00000010 },
+    { 0x00009b34, 0x00000011 },
+    { 0x00009b3c, 0x00000013 },
+    { 0x00009b40, 0x00000014 },
+    { 0x00009b44, 0x00000015 },
+    { 0x00009b48, 0x00000018 },
+    { 0x00009b4c, 0x00000019 },
+    { 0x00009b50, 0x0000001a },
+    { 0x00009b54, 0x0000001b },
+    { 0x00009b58, 0x0000001c },
+    { 0x00009b5c, 0x0000001d },
+    { 0x00009b60, 0x00000020 },
+    { 0x00009b68, 0x00000022 },
+    { 0x00009b6c, 0x00000023 },
+    { 0x00009b70, 0x00000024 },
+    { 0x00009b74, 0x00000025 },
+    { 0x00009b78, 0x00000028 },
+    { 0x00009b7c, 0x00000029 },
+    { 0x00009b80, 0x0000002a },
+    { 0x00009b84, 0x0000002b },
+    { 0x00009b88, 0x0000002c },
+    { 0x00009b90, 0x00000030 },
+    { 0x00009b94, 0x00000031 },
+    { 0x00009b98, 0x00000032 },
+    { 0x00009ba0, 0x00000034 },
+    { 0x00009ba4, 0x00000035 },
+    { 0x00009ba8, 0x00000035 },
+    { 0x00009bac, 0x00000035 },
+    { 0x00009bb0, 0x00000035 },
+    { 0x00009bb4, 0x00000035 },
+    { 0x00009bb8, 0x00000035 },
+    { 0x00009bbc, 0x00000035 },
+    { 0x00009bc0, 0x00000035 },
+    { 0x00009bc4, 0x00000035 },
+    { 0x00009bc8, 0x00000035 },
+    { 0x00009bcc, 0x00000035 },
+    { 0x00009bd0, 0x00000035 },
+    { 0x00009bd4, 0x00000035 },
+    { 0x00009bd8, 0x00000035 },
+    { 0x00009bdc, 0x00000035 },
+    { 0x00009be0, 0x00000035 },
+    { 0x00009be4, 0x00000035 },
+    { 0x00009be8, 0x00000035 },
+    { 0x00009bec, 0x00000035 },
+    { 0x00009bf0, 0x00000035 },
+    { 0x00009bf4, 0x00000035 },
+    { 0x00009bf8, 0x00000010 },
+    { 0x00009bfc, 0x0000001a },
+};
+#endif /* AH_5212_2413 */
+
+#ifdef AH_5212_2316
+static const uint32_t ar5212Common_2316[][2] = {
+    { 0x00001230, 0x000003e0 },
+    { 0x00008060, 0x0000000f },
+    { 0x00008118, 0x00000000 },
+    { 0x0000811c, 0x00000000 },
+    { 0x00008120, 0x00000000 },
+    { 0x00008124, 0x00000000 },
+    { 0x00008128, 0x00000000 },
+    { 0x0000812c, 0x00000000 },
+    { 0x00008130, 0x00000000 },
+    { 0x00008134, 0x00000000 },
+    { 0x00008138, 0x00000000 },
+    { 0x0000813c, 0x00000000 },
+    { 0x00008140, 0x800000a8 },
+    { 0x00008144, 0x00000000 },
+    { 0x00009808, 0x00004000 },
+    { 0x0000982c, 0x0000a000 },
+    { 0x0000983c, 0x00200400 },
+    { 0x0000984c, 0x1284233c },
+    { 0x00009870, 0x0000001f },
+    { 0x00009874, 0x00000080 },
+    { 0x00009878, 0x0000000e },
+    { 0x00009958, 0x000000ff },
+    { 0x00009980, 0x00000000 },
+    { 0x00009984, 0x02800000 },
+    { 0x000099a0, 0x00000000 },
+    { 0x000099e0, 0x00000000 },
+    { 0x000099e4, 0xaaaaaaaa },
+    { 0x000099e8, 0x3c466478 },
+    { 0x000099ec, 0x000000aa },
+    { 0x000099f0, 0x0000000c },
+    { 0x000099f4, 0x000000ff },
+    { 0x000099f8, 0x00000014 },
+    { 0x0000a228, 0x000009b5 },
+    { 0x0000a23c, 0x93c889af },
+    { 0x0000a24c, 0x00000001 },
+    { 0x0000a250, 0x0000a000 },
+    { 0x0000a254, 0x00000000 },
+    { 0x0000a258, 0x0cc75380 },
+    { 0x0000a25c, 0x0f0f0f01 },
+    { 0x0000a260, 0x5f690f01 },
+    { 0x0000a264, 0x00418a11 },
+    { 0x0000a268, 0x00000000 },
+    { 0x0000a26c, 0x0c30c16a },
+    { 0x0000a270, 0x00820820 },
+    { 0x0000a274, 0x081b7caa },
+    { 0x0000a278, 0x1ce739ce },
+    { 0x0000a27c, 0x051701ce },
+    { 0x0000a300, 0x18010000 },
+    { 0x0000a304, 0x30032602 },
+    { 0x0000a308, 0x48073e06 },
+    { 0x0000a30c, 0x560b4c0a },
+    { 0x0000a310, 0x641a600f },
+    { 0x0000a314, 0x784f6e1b },
+    { 0x0000a318, 0x868f7c5a },
+    { 0x0000a31c, 0x8ecf865b },
+    { 0x0000a320, 0x9d4f970f },
+    { 0x0000a324, 0xa5cfa18f },
+    { 0x0000a328, 0xb55faf1f },
+    { 0x0000a32c, 0xbddfb99f },
+    { 0x0000a330, 0xcd7fc73f },
+    { 0x0000a334, 0xd5ffd1bf },
+    { 0x0000a338, 0x00000000 },
+    { 0x0000a33c, 0x00000000 },
+    { 0x0000a340, 0x00000000 },
+    { 0x0000a344, 0x00000000 },
+    { 0x0000a348, 0x3fffffff },
+    { 0x0000a34c, 0x3fffffff },
+    { 0x0000a350, 0x3fffffff },
+    { 0x0000a354, 0x0003ffff },
+    { 0x0000a358, 0x79a8aa1f },
+    { 0x0000a35c, 0x066c420f },
+    { 0x0000a360, 0x0f282207 },
+    { 0x0000a364, 0x17601685 },
+    { 0x0000a368, 0x1f801104 },
+    { 0x0000a36c, 0x37a00c03 },
+    { 0x0000a370, 0x3fc40883 },
+    { 0x0000a374, 0x57c00803 },
+    { 0x0000a378, 0x5fd80682 },
+    { 0x0000a37c, 0x7fe00482 },
+    { 0x0000a380, 0x7f3c7bba },
+    { 0x0000a384, 0xf3307ff0 },
+    { 0x00009b04, 0x00000001 },
+    { 0x00009b08, 0x00000002 },
+    { 0x00009b0c, 0x00000003 },
+    { 0x00009b10, 0x00000004 },
+    { 0x00009b14, 0x00000005 },
+    { 0x00009b18, 0x00000008 },
+    { 0x00009b1c, 0x00000009 },
+    { 0x00009b20, 0x0000000a },
+    { 0x00009b24, 0x0000000b },
+    { 0x00009b2c, 0x0000000d },
+    { 0x00009b30, 0x00000010 },
+    { 0x00009b34, 0x00000011 },
+    { 0x00009b3c, 0x00000013 },
+    { 0x00009b40, 0x00000014 },
+    { 0x00009b44, 0x00000015 },
+    { 0x00009b48, 0x00000018 },
+    { 0x00009b4c, 0x00000019 },
+    { 0x00009b50, 0x0000001a },
+    { 0x00009b54, 0x0000001b },
+    { 0x00009b58, 0x0000001c },
+    { 0x00009b5c, 0x0000001d },
+    { 0x00009b60, 0x00000020 },
+    { 0x00009b68, 0x00000022 },
+    { 0x00009b6c, 0x00000023 },
+    { 0x00009b70, 0x00000024 },
+    { 0x00009b74, 0x00000025 },
+    { 0x00009b78, 0x00000028 },
+    { 0x00009b7c, 0x00000029 },
+    { 0x00009b80, 0x0000002a },
+    { 0x00009b84, 0x0000002b },
+    { 0x00009b88, 0x0000002c },
+    { 0x00009b90, 0x00000030 },
+    { 0x00009b94, 0x00000031 },
+    { 0x00009b98, 0x00000032 },
+    { 0x00009ba0, 0x00000034 },
+    { 0x00009ba4, 0x00000035 },
+    { 0x00009ba8, 0x00000035 },
+    { 0x00009bac, 0x00000035 },
+    { 0x00009bb0, 0x00000035 },
+    { 0x00009bb4, 0x00000035 },
+    { 0x00009bb8, 0x00000035 },
+    { 0x00009bbc, 0x00000035 },
+    { 0x00009bc0, 0x00000035 },
+    { 0x00009bc4, 0x00000035 },
+    { 0x00009bc8, 0x00000035 },
+    { 0x00009bcc, 0x00000035 },
+    { 0x00009bd0, 0x00000035 },
+    { 0x00009bd4, 0x00000035 },
+    { 0x00009bd8, 0x00000035 },
+    { 0x00009bdc, 0x00000035 },
+    { 0x00009be0, 0x00000035 },
+    { 0x00009be4, 0x00000035 },
+    { 0x00009be8, 0x00000035 },
+    { 0x00009bec, 0x00000035 },
+    { 0x00009bf0, 0x00000035 },
+    { 0x00009bf4, 0x00000035 },
+    { 0x00009bf8, 0x00000010 },
+    { 0x00009bfc, 0x0000001a },
+};
+#endif
+
+#ifdef AH_5212_5413
+static const uint32_t ar5212Common_5413[][2] = {
+    { 0x00001230, 0x000003e0 },
+    { 0x00004068, 0x00000010 },
+    { 0x00008060, 0x0000000f },
+    { 0x0000809c, 0x00000000 },
+    { 0x000080a0, 0x00000000 },
+    { 0x00008118, 0x00000000 },
+    { 0x0000811c, 0x00000000 },
+    { 0x00008120, 0x00000000 },
+    { 0x00008124, 0x00000000 },
+    { 0x00008128, 0x00000000 },
+    { 0x0000812c, 0x00000000 },
+    { 0x00008130, 0x00000000 },
+    { 0x00008134, 0x00000000 },
+    { 0x00008138, 0x00000000 },
+    { 0x0000813c, 0x00000000 },
+    { 0x00008140, 0x800003f9 },
+    { 0x00008144, 0x00000000 },
+    { 0x00009808, 0x00000000 },
+    { 0x0000982c, 0x0000a000 },
+    { 0x0000983c, 0x00200400 },
+    { 0x0000984c, 0x1284233c },
+    { 0x00009870, 0x0000001f },
+    { 0x00009874, 0x00000080 },
+    { 0x00009878, 0x0000000e },
+    { 0x00009958, 0x00081fff },
+    { 0x00009980, 0x00000000 },
+    { 0x00009984, 0x02800000 },
+    { 0x000099a0, 0x00000000 },
+    { 0x000099e0, 0x00000000 },
+    { 0x000099e4, 0xaaaaaaaa },
+    { 0x000099e8, 0x3c466478 },
+    { 0x000099ec, 0x000000aa },
+    { 0x000099f0, 0x0000000c },
+    { 0x000099f4, 0x000000ff },
+    { 0x000099f8, 0x00000014 },
+    { 0x0000a228, 0x000009b5 },
+    { 0x0000a23c, 0x93c889af },
+    { 0x0000a24c, 0x00000001 },
+    { 0x0000a250, 0x0000a000 },
+    { 0x0000a254, 0x00000000 },
+    { 0x0000a258, 0x0cc75380 },
+    { 0x0000a25c, 0x0f0f0f01 },
+    { 0x0000a260, 0x5f690f01 },
+    { 0x0000a264, 0x00418a11 },
+    { 0x0000a268, 0x00000000 },
+    { 0x0000a26c, 0x0c30c16a },
+    { 0x0000a270, 0x00820820 },
+    { 0x0000a274, 0x081b7caa },
+    { 0x0000a278, 0x1ce739ce },
+    { 0x0000a27c, 0x051701ce },
+    { 0x0000a338, 0x00000000 },
+    { 0x0000a33c, 0x00000000 },
+    { 0x0000a340, 0x00000000 },
+    { 0x0000a344, 0x00000000 },
+    { 0x0000a348, 0x3fffffff },
+    { 0x0000a34c, 0x3fffffff },
+    { 0x0000a350, 0x3fffffff },
+    { 0x0000a354, 0x0003ffff },
+    { 0x0000a358, 0x79a8aa1f },
+    { 0x0000a35c, 0x066c420f },
+    { 0x0000a360, 0x0f282207 },
+    { 0x0000a364, 0x17601685 },
+    { 0x0000a368, 0x1f801104 },
+    { 0x0000a36c, 0x37a00c03 },
+    { 0x0000a370, 0x3fc40883 },
+    { 0x0000a374, 0x57c00803 },
+    { 0x0000a378, 0x5fd80682 },
+    { 0x0000a37c, 0x7fe00482 },
+    { 0x0000a380, 0x7f3c7bba },
+    { 0x0000a384, 0xf3307ff0 },
+    { 0x00009b04, 0x00000001 },
+    { 0x00009b08, 0x00000002 },
+    { 0x00009b0c, 0x00000003 },
+    { 0x00009b10, 0x00000004 },
+    { 0x00009b14, 0x00000005 },
+    { 0x00009b18, 0x00000008 },
+    { 0x00009b1c, 0x00000009 },
+    { 0x00009b20, 0x0000000a },
+    { 0x00009b24, 0x0000000b },
+    { 0x00009b2c, 0x0000000d },
+    { 0x00009b30, 0x00000010 },
+    { 0x00009b34, 0x00000011 },
+    { 0x00009b3c, 0x00000013 },
+    { 0x00009b40, 0x00000014 },
+    { 0x00009b44, 0x00000015 },
+    { 0x00009b48, 0x00000018 },
+    { 0x00009b4c, 0x00000019 },
+    { 0x00009b50, 0x0000001a },
+    { 0x00009b54, 0x0000001b },
+    { 0x00009b58, 0x0000001c },
+    { 0x00009b5c, 0x0000001d },
+    { 0x00009b60, 0x00000020 },
+    { 0x00009b68, 0x00000022 },
+    { 0x00009b6c, 0x00000023 },
+    { 0x00009b70, 0x00000024 },
+    { 0x00009b74, 0x00000025 },
+    { 0x00009b78, 0x00000028 },
+    { 0x00009b7c, 0x00000029 },
+    { 0x00009b80, 0x0000002a },
+    { 0x00009b84, 0x0000002b },
+    { 0x00009b88, 0x0000002c },
+    { 0x00009b90, 0x00000030 },
+    { 0x00009b94, 0x00000031 },
+    { 0x00009b98, 0x00000032 },
+    { 0x00009ba0, 0x00000034 },
+    { 0x00009ba4, 0x00000035 },
+    { 0x00009ba8, 0x00000035 },
+    { 0x00009bac, 0x00000035 },
+    { 0x00009bb0, 0x00000035 },
+    { 0x00009bb4, 0x00000035 },
+    { 0x00009bb8, 0x00000035 },
+    { 0x00009bbc, 0x00000035 },
+    { 0x00009bc0, 0x00000035 },
+    { 0x00009bc4, 0x00000035 },
+    { 0x00009bc8, 0x00000035 },
+    { 0x00009bcc, 0x00000035 },
+    { 0x00009bd0, 0x00000035 },
+    { 0x00009bd4, 0x00000035 },
+    { 0x00009bd8, 0x00000035 },
+    { 0x00009bdc, 0x00000035 },
+    { 0x00009be0, 0x00000035 },
+    { 0x00009be4, 0x00000035 },
+    { 0x00009be8, 0x00000035 },
+    { 0x00009bec, 0x00000035 },
+    { 0x00009bf0, 0x00000035 },
+    { 0x00009bf4, 0x00000035 },
+    { 0x00009bf8, 0x00000010 },
+    { 0x00009bfc, 0x0000001a },
+};
+#endif /* AH_5212_5413 */
+
+#ifdef AH_5212_2425
+static const uint32_t ar5212Common_2425[][2] = {
+    { 0x00001230, 0x000003e0 },
+    { 0x00008060, 0x0000000f },
+    { 0x0000809c, 0x00000000 },
+    { 0x000080a0, 0x00000000 },
+    { 0x00008118, 0x00000000 },
+    { 0x0000811c, 0x00000000 },
+    { 0x00008120, 0x00000000 },
+    { 0x00008124, 0x00000000 },
+    { 0x00008128, 0x00000000 },
+    { 0x0000812c, 0x00000000 },
+    { 0x00008130, 0x00000000 },
+    { 0x00008134, 0x00000000 },
+    { 0x00008138, 0x00000000 },
+    { 0x0000813c, 0x00000000 },
+    { 0x00008140, 0x800003f9 },
+    { 0x00008144, 0x00000000 },
+    { 0x00009808, 0x00000000 },
+    { 0x0000982c, 0x0000a000 },
+    { 0x0000983c, 0x00200400 },
+    { 0x0000984c, 0x1284233c },
+    { 0x00009870, 0x0000001f },
+    { 0x00009874, 0x00000080 },
+    { 0x00009878, 0x0000000e },
+    { 0x00009958, 0x00081fff },
+    { 0x00009980, 0x00000000 },
+    { 0x00009984, 0x02800000 },
+    { 0x000099a0, 0x00000000 },
+    { 0x000099dc, 0xfebadbe8 },
+    { 0x000099e0, 0x00000000 },
+    { 0x000099e4, 0xaaaaaaaa },
+    { 0x000099e8, 0x3c466478 },
+    { 0x000099ec, 0x000000aa },
+    { 0x000099f0, 0x0000000c },
+    { 0x000099f4, 0x000000ff },
+    { 0x000099f8, 0x00000014 },
+    { 0x0000a228, 0x000009b5 },
+    { 0x0000a234, 0x20202020 },
+    { 0x0000a238, 0x20202020 },
+    { 0x0000a23c, 0x93c889af },
+    { 0x0000a24c, 0x00000001 },
+    { 0x0000a250, 0x0000a000 },
+    { 0x0000a254, 0x00000000 },
+    { 0x0000a258, 0x0cc75380 },
+    { 0x0000a25c, 0x0f0f0f01 },
+    { 0x0000a260, 0x5f690f01 },
+    { 0x0000a264, 0x00418a11 },
+    { 0x0000a268, 0x00000000 },
+    { 0x0000a26c, 0x0c30c166 },
+    { 0x0000a270, 0x00820820 },
+    { 0x0000a274, 0x081a3caa },
+    { 0x0000a278, 0x1ce739ce },
+    { 0x0000a27c, 0x051701ce },
+    { 0x0000a300, 0x16010000 },
+    { 0x0000a304, 0x2c032402 },
+    { 0x0000a308, 0x48433e42 },
+    { 0x0000a30c, 0x5a0f500b },
+    { 0x0000a310, 0x6c4b624a },
+    { 0x0000a314, 0x7e8b748a },
+    { 0x0000a318, 0x96cf8ccb },
+    { 0x0000a31c, 0xa34f9d0f },
+    { 0x0000a320, 0xa7cfa58f },
+    { 0x0000a348, 0x3fffffff },
+    { 0x0000a34c, 0x3fffffff },
+    { 0x0000a350, 0x3fffffff },
+    { 0x0000a354, 0x0003ffff },
+    { 0x0000a358, 0x79a8aa1f },
+    { 0x0000a35c, 0x066c420f },
+    { 0x0000a360, 0x0f282207 },
+    { 0x0000a364, 0x17601685 },
+    { 0x0000a368, 0x1f801104 },
+    { 0x0000a36c, 0x37a00c03 },
+    { 0x0000a370, 0x3fc40883 },
+    { 0x0000a374, 0x57c00803 },
+    { 0x0000a378, 0x5fd80682 },
+    { 0x0000a37c, 0x7fe00482 },
+    { 0x0000a380, 0x7f3c7bba },
+    { 0x0000a384, 0xf3307ff0 },
+};
+#endif /* AH_5212_2425 */
+
+#ifdef AH_5212_5111
+static const uint32_t ar5212Bank0_5111[][6] = {
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 },
+    { 0x0000989c, 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd },
+    { 0x000098d4, 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 },
+};
+
+static const uint32_t ar5212BB_RfGain_5111[][3] = {
+    { 0x00009a00, 0x000001a9, 0x00000000 },
+    { 0x00009a04, 0x000001e9, 0x00000040 },
+    { 0x00009a08, 0x00000029, 0x00000080 },
+    { 0x00009a0c, 0x00000069, 0x00000150 },
+    { 0x00009a10, 0x00000199, 0x00000190 },
+    { 0x00009a14, 0x000001d9, 0x000001d0 },
+    { 0x00009a18, 0x00000019, 0x00000010 },
+    { 0x00009a1c, 0x00000059, 0x00000044 },
+    { 0x00009a20, 0x00000099, 0x00000084 },
+    { 0x00009a24, 0x000001a5, 0x00000148 },
+    { 0x00009a28, 0x000001e5, 0x00000188 },
+    { 0x00009a2c, 0x00000025, 0x000001c8 },
+    { 0x00009a30, 0x000001c8, 0x00000014 },
+    { 0x00009a34, 0x00000008, 0x00000042 },
+    { 0x00009a38, 0x00000048, 0x00000082 },
+    { 0x00009a3c, 0x00000088, 0x00000178 },
+    { 0x00009a40, 0x00000198, 0x000001b8 },
+    { 0x00009a44, 0x000001d8, 0x000001f8 },
+    { 0x00009a48, 0x00000018, 0x00000012 },
+    { 0x00009a4c, 0x00000058, 0x00000052 },
+    { 0x00009a50, 0x00000098, 0x00000092 },
+    { 0x00009a54, 0x000001a4, 0x0000017c },
+    { 0x00009a58, 0x000001e4, 0x000001bc },
+    { 0x00009a5c, 0x00000024, 0x000001fc },
+    { 0x00009a60, 0x00000064, 0x0000000a },
+    { 0x00009a64, 0x000000a4, 0x0000004a },
+    { 0x00009a68, 0x000000e4, 0x0000008a },
+    { 0x00009a6c, 0x0000010a, 0x0000015a },
+    { 0x00009a70, 0x0000014a, 0x0000019a },
+    { 0x00009a74, 0x0000018a, 0x000001da },
+    { 0x00009a78, 0x000001ca, 0x0000000e },
+    { 0x00009a7c, 0x0000000a, 0x0000004e },
+    { 0x00009a80, 0x0000004a, 0x0000008e },
+    { 0x00009a84, 0x0000008a, 0x0000015e },
+    { 0x00009a88, 0x000001ba, 0x0000019e },
+    { 0x00009a8c, 0x000001fa, 0x000001de },
+    { 0x00009a90, 0x0000003a, 0x00000009 },
+    { 0x00009a94, 0x0000007a, 0x00000049 },
+    { 0x00009a98, 0x00000186, 0x00000089 },
+    { 0x00009a9c, 0x000001c6, 0x00000179 },
+    { 0x00009aa0, 0x00000006, 0x000001b9 },
+    { 0x00009aa4, 0x00000046, 0x000001f9 },
+    { 0x00009aa8, 0x00000086, 0x00000039 },
+    { 0x00009aac, 0x000000c6, 0x00000079 },
+    { 0x00009ab0, 0x000000c6, 0x000000b9 },
+    { 0x00009ab4, 0x000000c6, 0x000001bd },
+    { 0x00009ab8, 0x000000c6, 0x000001fd },
+    { 0x00009abc, 0x000000c6, 0x0000003d },
+    { 0x00009ac0, 0x000000c6, 0x0000007d },
+    { 0x00009ac4, 0x000000c6, 0x000000bd },
+    { 0x00009ac8, 0x000000c6, 0x000000fd },
+    { 0x00009acc, 0x000000c6, 0x000000fd },
+    { 0x00009ad0, 0x000000c6, 0x000000fd },
+    { 0x00009ad4, 0x000000c6, 0x000000fd },
+    { 0x00009ad8, 0x000000c6, 0x000000fd },
+    { 0x00009adc, 0x000000c6, 0x000000fd },
+    { 0x00009ae0, 0x000000c6, 0x000000fd },
+    { 0x00009ae4, 0x000000c6, 0x000000fd },
+    { 0x00009ae8, 0x000000c6, 0x000000fd },
+    { 0x00009aec, 0x000000c6, 0x000000fd },
+    { 0x00009af0, 0x000000c6, 0x000000fd },
+    { 0x00009af4, 0x000000c6, 0x000000fd },
+    { 0x00009af8, 0x000000c6, 0x000000fd },
+    { 0x00009afc, 0x000000c6, 0x000000fd },
+};
+#endif /* AH_5212_5111 */
+
+#ifdef AH_5212_5112
+static const uint32_t ar5212BB_RfGain_5112[][3] = {
+    { 0x00009a00, 0x00000007, 0x00000007 },
+    { 0x00009a04, 0x00000047, 0x00000047 },
+    { 0x00009a08, 0x00000087, 0x00000087 },
+    { 0x00009a0c, 0x000001a0, 0x000001a0 },
+    { 0x00009a10, 0x000001e0, 0x000001e0 },
+    { 0x00009a14, 0x00000020, 0x00000020 },
+    { 0x00009a18, 0x00000060, 0x00000060 },
+    { 0x00009a1c, 0x000001a1, 0x000001a1 },
+    { 0x00009a20, 0x000001e1, 0x000001e1 },
+    { 0x00009a24, 0x00000021, 0x00000021 },
+    { 0x00009a28, 0x00000061, 0x00000061 },
+    { 0x00009a2c, 0x00000162, 0x00000162 },
+    { 0x00009a30, 0x000001a2, 0x000001a2 },
+    { 0x00009a34, 0x000001e2, 0x000001e2 },
+    { 0x00009a38, 0x00000022, 0x00000022 },
+    { 0x00009a3c, 0x00000062, 0x00000062 },
+    { 0x00009a40, 0x00000163, 0x00000163 },
+    { 0x00009a44, 0x000001a3, 0x000001a3 },
+    { 0x00009a48, 0x000001e3, 0x000001e3 },
+    { 0x00009a4c, 0x00000023, 0x00000023 },
+    { 0x00009a50, 0x00000063, 0x00000063 },
+    { 0x00009a54, 0x00000184, 0x00000184 },
+    { 0x00009a58, 0x000001c4, 0x000001c4 },
+    { 0x00009a5c, 0x00000004, 0x00000004 },
+    { 0x00009a60, 0x000001ea, 0x0000000b },
+    { 0x00009a64, 0x0000002a, 0x0000004b },
+    { 0x00009a68, 0x0000006a, 0x0000008b },
+    { 0x00009a6c, 0x000000aa, 0x000001ac },
+    { 0x00009a70, 0x000001ab, 0x000001ec },
+    { 0x00009a74, 0x000001eb, 0x0000002c },
+    { 0x00009a78, 0x0000002b, 0x00000012 },
+    { 0x00009a7c, 0x0000006b, 0x00000052 },
+    { 0x00009a80, 0x000000ab, 0x00000092 },
+    { 0x00009a84, 0x000001ac, 0x00000193 },
+    { 0x00009a88, 0x000001ec, 0x000001d3 },
+    { 0x00009a8c, 0x0000002c, 0x00000013 },
+    { 0x00009a90, 0x0000003a, 0x00000053 },
+    { 0x00009a94, 0x0000007a, 0x00000093 },
+    { 0x00009a98, 0x000000ba, 0x00000194 },
+    { 0x00009a9c, 0x000001bb, 0x000001d4 },
+    { 0x00009aa0, 0x000001fb, 0x00000014 },
+    { 0x00009aa4, 0x0000003b, 0x0000003a },
+    { 0x00009aa8, 0x0000007b, 0x0000007a },
+    { 0x00009aac, 0x000000bb, 0x000000ba },
+    { 0x00009ab0, 0x000001bc, 0x000001bb },
+    { 0x00009ab4, 0x000001fc, 0x000001fb },
+    { 0x00009ab8, 0x0000003c, 0x0000003b },
+    { 0x00009abc, 0x0000007c, 0x0000007b },
+    { 0x00009ac0, 0x000000bc, 0x000000bb },
+    { 0x00009ac4, 0x000000fc, 0x000001bc },
+    { 0x00009ac8, 0x000000fc, 0x000001fc },
+    { 0x00009acc, 0x000000fc, 0x0000003c },
+    { 0x00009ad0, 0x000000fc, 0x0000007c },
+    { 0x00009ad4, 0x000000fc, 0x000000bc },
+    { 0x00009ad8, 0x000000fc, 0x000000fc },
+    { 0x00009adc, 0x000000fc, 0x000000fc },
+    { 0x00009ae0, 0x000000fc, 0x000000fc },
+    { 0x00009ae4, 0x000000fc, 0x000000fc },
+    { 0x00009ae8, 0x000000fc, 0x000000fc },
+    { 0x00009aec, 0x000000fc, 0x000000fc },
+    { 0x00009af0, 0x000000fc, 0x000000fc },
+    { 0x00009af4, 0x000000fc, 0x000000fc },
+    { 0x00009af8, 0x000000fc, 0x000000fc },
+    { 0x00009afc, 0x000000fc, 0x000000fc },
+};
+#endif /* AH_5212_5112 */
+
+#ifdef AH_5212_2413
+static const uint32_t ar5212BB_RfGain_2413[][3] = {
+    { 0x00009a00, 0x00000000, 0x00000000 },
+    { 0x00009a04, 0x00000000, 0x00000040 },
+    { 0x00009a08, 0x00000000, 0x00000080 },
+    { 0x00009a0c, 0x00000000, 0x00000181 },
+    { 0x00009a10, 0x00000000, 0x000001c1 },
+    { 0x00009a14, 0x00000000, 0x00000001 },
+    { 0x00009a18, 0x00000000, 0x00000041 },
+    { 0x00009a1c, 0x00000000, 0x00000081 },
+    { 0x00009a20, 0x00000000, 0x00000168 },
+    { 0x00009a24, 0x00000000, 0x000001a8 },
+    { 0x00009a28, 0x00000000, 0x000001e8 },
+    { 0x00009a2c, 0x00000000, 0x00000028 },
+    { 0x00009a30, 0x00000000, 0x00000068 },
+    { 0x00009a34, 0x00000000, 0x00000189 },
+    { 0x00009a38, 0x00000000, 0x000001c9 },
+    { 0x00009a3c, 0x00000000, 0x00000009 },
+    { 0x00009a40, 0x00000000, 0x00000049 },
+    { 0x00009a44, 0x00000000, 0x00000089 },
+    { 0x00009a48, 0x00000000, 0x00000190 },
+    { 0x00009a4c, 0x00000000, 0x000001d0 },
+    { 0x00009a50, 0x00000000, 0x00000010 },
+    { 0x00009a54, 0x00000000, 0x00000050 },
+    { 0x00009a58, 0x00000000, 0x00000090 },
+    { 0x00009a5c, 0x00000000, 0x00000191 },
+    { 0x00009a60, 0x00000000, 0x000001d1 },
+    { 0x00009a64, 0x00000000, 0x00000011 },
+    { 0x00009a68, 0x00000000, 0x00000051 },
+    { 0x00009a6c, 0x00000000, 0x00000091 },
+    { 0x00009a70, 0x00000000, 0x00000178 },
+    { 0x00009a74, 0x00000000, 0x000001b8 },
+    { 0x00009a78, 0x00000000, 0x000001f8 },
+    { 0x00009a7c, 0x00000000, 0x00000038 },
+    { 0x00009a80, 0x00000000, 0x00000078 },
+    { 0x00009a84, 0x00000000, 0x00000199 },
+    { 0x00009a88, 0x00000000, 0x000001d9 },
+    { 0x00009a8c, 0x00000000, 0x00000019 },
+    { 0x00009a90, 0x00000000, 0x00000059 },
+    { 0x00009a94, 0x00000000, 0x00000099 },
+    { 0x00009a98, 0x00000000, 0x000000d9 },
+    { 0x00009a9c, 0x00000000, 0x000000f9 },
+    { 0x00009aa0, 0x00000000, 0x000000f9 },
+    { 0x00009aa4, 0x00000000, 0x000000f9 },
+    { 0x00009aa8, 0x00000000, 0x000000f9 },
+    { 0x00009aac, 0x00000000, 0x000000f9 },
+    { 0x00009ab0, 0x00000000, 0x000000f9 },
+    { 0x00009ab4, 0x00000000, 0x000000f9 },
+    { 0x00009ab8, 0x00000000, 0x000000f9 },
+    { 0x00009abc, 0x00000000, 0x000000f9 },
+    { 0x00009ac0, 0x00000000, 0x000000f9 },
+    { 0x00009ac4, 0x00000000, 0x000000f9 },
+    { 0x00009ac8, 0x00000000, 0x000000f9 },
+    { 0x00009acc, 0x00000000, 0x000000f9 },
+    { 0x00009ad0, 0x00000000, 0x000000f9 },
+    { 0x00009ad4, 0x00000000, 0x000000f9 },
+    { 0x00009ad8, 0x00000000, 0x000000f9 },
+    { 0x00009adc, 0x00000000, 0x000000f9 },
+    { 0x00009ae0, 0x00000000, 0x000000f9 },
+    { 0x00009ae4, 0x00000000, 0x000000f9 },
+    { 0x00009ae8, 0x00000000, 0x000000f9 },
+    { 0x00009aec, 0x00000000, 0x000000f9 },
+    { 0x00009af0, 0x00000000, 0x000000f9 },
+    { 0x00009af4, 0x00000000, 0x000000f9 },
+    { 0x00009af8, 0x00000000, 0x000000f9 },
+    { 0x00009afc, 0x00000000, 0x000000f9 },
+};
+#endif /* AH_5212_2413 */
+
+#ifdef AH_5212_2316
+static const uint32_t ar5212BB_RfGain_2316[][3] = {
+    { 0x00009a00, 0x00000000, 0x00000000 },
+    { 0x00009a04, 0x00000000, 0x00000040 },
+    { 0x00009a08, 0x00000000, 0x00000080 },
+    { 0x00009a0c, 0x00000000, 0x00000161 },
+    { 0x00009a10, 0x00000000, 0x000001a1 },
+    { 0x00009a14, 0x00000000, 0x000001e1 },
+    { 0x00009a18, 0x00000000, 0x00000021 },
+    { 0x00009a1c, 0x00000000, 0x00000061 },
+    { 0x00009a20, 0x00000000, 0x000000a1 },
+    { 0x00009a24, 0x00000000, 0x00000168 },
+    { 0x00009a28, 0x00000000, 0x000001a8 },
+    { 0x00009a2c, 0x00000000, 0x000001e8 },
+    { 0x00009a30, 0x00000000, 0x00000028 },
+    { 0x00009a34, 0x00000000, 0x00000068 },
+    { 0x00009a38, 0x00000000, 0x000000a8 },
+    { 0x00009a3c, 0x00000000, 0x00000189 },
+    { 0x00009a40, 0x00000000, 0x000001c9 },
+    { 0x00009a44, 0x00000000, 0x00000009 },
+    { 0x00009a48, 0x00000000, 0x00000049 },
+    { 0x00009a4c, 0x00000000, 0x00000089 },
+    { 0x00009a50, 0x00000000, 0x000001b0 },
+    { 0x00009a54, 0x00000000, 0x000001f0 },
+    { 0x00009a58, 0x00000000, 0x00000030 },
+    { 0x00009a5c, 0x00000000, 0x00000070 },
+    { 0x00009a60, 0x00000000, 0x000000b0 },
+    { 0x00009a64, 0x00000000, 0x000001b1 },
+    { 0x00009a68, 0x00000000, 0x000001f1 },
+    { 0x00009a6c, 0x00000000, 0x00000031 },
+    { 0x00009a70, 0x00000000, 0x00000071 },
+    { 0x00009a74, 0x00000000, 0x00000198 },
+    { 0x00009a78, 0x00000000, 0x000001d8 },
+    { 0x00009a7c, 0x00000000, 0x00000018 },
+    { 0x00009a80, 0x00000000, 0x00000058 },
+    { 0x00009a84, 0x00000000, 0x00000098 },
+    { 0x00009a88, 0x00000000, 0x00000199 },
+    { 0x00009a8c, 0x00000000, 0x000001d9 },
+    { 0x00009a90, 0x00000000, 0x00000019 },
+    { 0x00009a94, 0x00000000, 0x00000059 },
+    { 0x00009a98, 0x00000000, 0x00000099 },
+    { 0x00009a9c, 0x00000000, 0x000000d9 },
+    { 0x00009aa0, 0x00000000, 0x000000f9 },
+    { 0x00009aa4, 0x00000000, 0x000000f9 },
+    { 0x00009aa8, 0x00000000, 0x000000f9 },
+    { 0x00009aac, 0x00000000, 0x000000f9 },
+    { 0x00009ab0, 0x00000000, 0x000000f9 },
+    { 0x00009ab4, 0x00000000, 0x000000f9 },
+    { 0x00009ab8, 0x00000000, 0x000000f9 },
+    { 0x00009abc, 0x00000000, 0x000000f9 },
+    { 0x00009ac0, 0x00000000, 0x000000f9 },
+    { 0x00009ac4, 0x00000000, 0x000000f9 },
+    { 0x00009ac8, 0x00000000, 0x000000f9 },
+    { 0x00009acc, 0x00000000, 0x000000f9 },
+    { 0x00009ad0, 0x00000000, 0x000000f9 },
+    { 0x00009ad4, 0x00000000, 0x000000f9 },
+    { 0x00009ad8, 0x00000000, 0x000000f9 },
+    { 0x00009adc, 0x00000000, 0x000000f9 },
+    { 0x00009ae0, 0x00000000, 0x000000f9 },
+    { 0x00009ae4, 0x00000000, 0x000000f9 },
+    { 0x00009ae8, 0x00000000, 0x000000f9 },
+    { 0x00009aec, 0x00000000, 0x000000f9 },
+    { 0x00009af0, 0x00000000, 0x000000f9 },
+    { 0x00009af4, 0x00000000, 0x000000f9 },
+    { 0x00009af8, 0x00000000, 0x000000f9 },
+    { 0x00009afc, 0x00000000, 0x000000f9 },
+};
+#endif
+
+#ifdef AH_5212_5413
+static const uint32_t ar5212BB_RfGain_5413[][3] = {
+    { 0x00009a00, 0x00000000, 0x00000000 },
+    { 0x00009a04, 0x00000040, 0x00000040 },
+    { 0x00009a08, 0x00000080, 0x00000080 },
+    { 0x00009a0c, 0x000001a1, 0x00000161 },
+    { 0x00009a10, 0x000001e1, 0x000001a1 },
+    { 0x00009a14, 0x00000021, 0x000001e1 },
+    { 0x00009a18, 0x00000061, 0x00000021 },
+    { 0x00009a1c, 0x00000188, 0x00000061 },
+    { 0x00009a20, 0x000001c8, 0x00000188 },
+    { 0x00009a24, 0x00000008, 0x000001c8 },
+    { 0x00009a28, 0x00000048, 0x00000008 },
+    { 0x00009a2c, 0x00000088, 0x00000048 },
+    { 0x00009a30, 0x000001a9, 0x00000088 },
+    { 0x00009a34, 0x000001e9, 0x00000169 },
+    { 0x00009a38, 0x00000029, 0x000001a9 },
+    { 0x00009a3c, 0x00000069, 0x000001e9 },
+    { 0x00009a40, 0x000001d0, 0x00000029 },
+    { 0x00009a44, 0x00000010, 0x00000069 },
+    { 0x00009a48, 0x00000050, 0x00000190 },
+    { 0x00009a4c, 0x00000090, 0x000001d0 },
+    { 0x00009a50, 0x000001b1, 0x00000010 },
+    { 0x00009a54, 0x000001f1, 0x00000050 },
+    { 0x00009a58, 0x00000031, 0x00000090 },
+    { 0x00009a5c, 0x00000071, 0x00000171 },
+    { 0x00009a60, 0x000001b8, 0x000001b1 },
+    { 0x00009a64, 0x000001f8, 0x000001f1 },
+    { 0x00009a68, 0x00000038, 0x00000031 },
+    { 0x00009a6c, 0x00000078, 0x00000071 },
+    { 0x00009a70, 0x00000199, 0x00000198 },
+    { 0x00009a74, 0x000001d9, 0x000001d8 },
+    { 0x00009a78, 0x00000019, 0x00000018 },
+    { 0x00009a7c, 0x00000059, 0x00000058 },
+    { 0x00009a80, 0x00000099, 0x00000098 },
+    { 0x00009a84, 0x000000d9, 0x00000179 },
+    { 0x00009a88, 0x000000f9, 0x000001b9 },
+    { 0x00009a8c, 0x000000f9, 0x000001f9 },
+    { 0x00009a90, 0x000000f9, 0x00000039 },
+    { 0x00009a94, 0x000000f9, 0x00000079 },
+    { 0x00009a98, 0x000000f9, 0x000000b9 },
+    { 0x00009a9c, 0x000000f9, 0x000000f9 },
+    { 0x00009aa0, 0x000000f9, 0x000000f9 },
+    { 0x00009aa4, 0x000000f9, 0x000000f9 },
+    { 0x00009aa8, 0x000000f9, 0x000000f9 },
+    { 0x00009aac, 0x000000f9, 0x000000f9 },
+    { 0x00009ab0, 0x000000f9, 0x000000f9 },
+    { 0x00009ab4, 0x000000f9, 0x000000f9 },
+    { 0x00009ab8, 0x000000f9, 0x000000f9 },
+    { 0x00009abc, 0x000000f9, 0x000000f9 },
+    { 0x00009ac0, 0x000000f9, 0x000000f9 },
+    { 0x00009ac4, 0x000000f9, 0x000000f9 },
+    { 0x00009ac8, 0x000000f9, 0x000000f9 },
+    { 0x00009acc, 0x000000f9, 0x000000f9 },
+    { 0x00009ad0, 0x000000f9, 0x000000f9 },
+    { 0x00009ad4, 0x000000f9, 0x000000f9 },
+    { 0x00009ad8, 0x000000f9, 0x000000f9 },
+    { 0x00009adc, 0x000000f9, 0x000000f9 },
+    { 0x00009ae0, 0x000000f9, 0x000000f9 },
+    { 0x00009ae4, 0x000000f9, 0x000000f9 },
+    { 0x00009ae8, 0x000000f9, 0x000000f9 },
+    { 0x00009aec, 0x000000f9, 0x000000f9 },
+    { 0x00009af0, 0x000000f9, 0x000000f9 },
+    { 0x00009af4, 0x000000f9, 0x000000f9 },
+    { 0x00009af8, 0x000000f9, 0x000000f9 },
+    { 0x00009afc, 0x000000f9, 0x000000f9 },
+};
+#endif /* AH_5212_5413 */
+
+#ifdef AH_5212_2425
+static const uint32_t ar5212BB_RfGain_2425[][3] = {
+    { 0x00009a00, 0x00000000, 0x00000000 },
+    { 0x00009a04, 0x00000000, 0x00000040 },
+    { 0x00009a08, 0x00000000, 0x00000080 },
+    { 0x00009a0c, 0x00000000, 0x00000181 },
+    { 0x00009a10, 0x00000000, 0x000001c1 },
+    { 0x00009a14, 0x00000000, 0x00000001 },
+    { 0x00009a18, 0x00000000, 0x00000041 },
+    { 0x00009a1c, 0x00000000, 0x00000081 },
+    { 0x00009a20, 0x00000000, 0x00000188 },
+    { 0x00009a24, 0x00000000, 0x000001c8 },
+    { 0x00009a28, 0x00000000, 0x00000008 },
+    { 0x00009a2c, 0x00000000, 0x00000048 },
+    { 0x00009a30, 0x00000000, 0x00000088 },
+    { 0x00009a34, 0x00000000, 0x00000189 },
+    { 0x00009a38, 0x00000000, 0x000001c9 },
+    { 0x00009a3c, 0x00000000, 0x00000009 },
+    { 0x00009a40, 0x00000000, 0x00000049 },
+    { 0x00009a44, 0x00000000, 0x00000089 },
+    { 0x00009a48, 0x00000000, 0x000001b0 },
+    { 0x00009a4c, 0x00000000, 0x000001f0 },
+    { 0x00009a50, 0x00000000, 0x00000030 },
+    { 0x00009a54, 0x00000000, 0x00000070 },
+    { 0x00009a58, 0x00000000, 0x00000171 },
+    { 0x00009a5c, 0x00000000, 0x000001b1 },
+    { 0x00009a60, 0x00000000, 0x000001f1 },
+    { 0x00009a64, 0x00000000, 0x00000031 },
+    { 0x00009a68, 0x00000000, 0x00000071 },
+    { 0x00009a6c, 0x00000000, 0x000001b8 },
+    { 0x00009a70, 0x00000000, 0x000001f8 },
+    { 0x00009a74, 0x00000000, 0x00000038 },
+    { 0x00009a78, 0x00000000, 0x00000078 },
+    { 0x00009a7c, 0x00000000, 0x000000b8 },
+    { 0x00009a80, 0x00000000, 0x000001b9 },
+    { 0x00009a84, 0x00000000, 0x000001f9 },
+    { 0x00009a88, 0x00000000, 0x00000039 },
+    { 0x00009a8c, 0x00000000, 0x00000079 },
+    { 0x00009a90, 0x00000000, 0x000000b9 },
+    { 0x00009a94, 0x00000000, 0x000000f9 },
+    { 0x00009a98, 0x00000000, 0x000000f9 },
+    { 0x00009a9c, 0x00000000, 0x000000f9 },
+    { 0x00009aa0, 0x00000000, 0x000000f9 },
+    { 0x00009aa4, 0x00000000, 0x000000f9 },
+    { 0x00009aa8, 0x00000000, 0x000000f9 },
+    { 0x00009aac, 0x00000000, 0x000000f9 },
+    { 0x00009ab0, 0x00000000, 0x000000f9 },
+    { 0x00009ab4, 0x00000000, 0x000000f9 },
+    { 0x00009ab8, 0x00000000, 0x000000f9 },
+    { 0x00009abc, 0x00000000, 0x000000f9 },
+    { 0x00009ac0, 0x00000000, 0x000000f9 },
+    { 0x00009ac4, 0x00000000, 0x000000f9 },
+    { 0x00009ac8, 0x00000000, 0x000000f9 },
+    { 0x00009acc, 0x00000000, 0x000000f9 },
+    { 0x00009ad0, 0x00000000, 0x000000f9 },
+    { 0x00009ad4, 0x00000000, 0x000000f9 },
+    { 0x00009ad8, 0x00000000, 0x000000f9 },
+    { 0x00009adc, 0x00000000, 0x000000f9 },
+    { 0x00009ae0, 0x00000000, 0x000000f9 },
+    { 0x00009ae4, 0x00000000, 0x000000f9 },
+    { 0x00009ae8, 0x00000000, 0x000000f9 },
+    { 0x00009aec, 0x00000000, 0x000000f9 },
+    { 0x00009af0, 0x00000000, 0x000000f9 },
+    { 0x00009af4, 0x00000000, 0x000000f9 },
+    { 0x00009af8, 0x00000000, 0x000000f9 },
+    { 0x00009afc, 0x00000000, 0x000000f9 },
+};
+#endif /* AH_5212_2425 */
+
+#ifdef AH_5212_5111
+static const uint32_t ar5212Bank1_5111[][2] = {
+    { 0x000098d4, 0x00000020 },
+};
+#endif /* AH_5212_5111 */
+
+#ifdef AH_5212_5112
+static const uint32_t ar5212Bank1_5112[][2] = {
+    { 0x000098d4, 0x00000020 },
+};
+#endif /* AH_5212_5112 */
+
+#ifdef AH_5212_2413
+static const uint32_t ar5212Bank1_2413[][2] = {
+    { 0x000098d4, 0x00000020 },
+};
+#endif /* AH_5212_2413 */
+
+#ifdef AH_5212_2316
+static const uint32_t ar5212Bank1_2316[][2] = {
+    { 0x000098d4, 0x00000020 },
+};
+#endif
+
+#ifdef AH_5212_5413
+static const uint32_t ar5212Bank1_5413[][2] = {
+    { 0x000098d4, 0x00000020 },
+};
+#endif /* AH_5212_5413 */
+
+#ifdef AH_5212_2425
+static const uint32_t ar5212Bank1_2425[][2] = {
+    { 0x000098d4, 0x00000020 },
+};
+#endif /* AH_5212_2425 */
+
+#ifdef AH_5212_5111
+static const uint32_t ar5212Bank2_5111[][6] = {
+    { 0x000098d4, 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 },
+};
+#endif /* AH_5212_5111 */
+
+#ifdef AH_5212_5112
+static const uint32_t ar5212Bank2_5112[][6] = {
+    { 0x000098d0, 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 },
+};
+#endif /* AH_5212_5112 */
+
+#ifdef AH_5212_2413
+static const uint32_t ar5212Bank2_2413[][6] = {
+    { 0x000098d0, 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 },
+};
+#endif /* AH_5212_2413 */
+
+#ifdef AH_5212_2316
+static const uint32_t ar5212Bank2_2316[][6] = {
+    { 0x000098d0, 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 },
+};
+#endif
+
+#ifdef AH_5212_5413
+static const uint32_t ar5212Bank2_5413[][6] = {
+    { 0x000098d0, 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 },
+};
+#endif /* AH_5212_5413 */
+
+#ifdef AH_5212_2425
+static const uint32_t ar5212Bank2_2425[][6] = {
+    { 0x000098d0, 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 },
+};
+#endif /* AH_5212_2425 */
+
+#ifdef AH_5212_5111
+static const uint32_t ar5212Bank3_5111[][6] = {
+    { 0x000098d8, 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 },
+};
+#endif /* AH_5212_5111 */
+
+#ifdef AH_5212_5112
+static const uint32_t ar5212Bank3_5112[][6] = {
+    { 0x000098dc, 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 },
+};
+#endif /* AH_5212_5112 */
+
+#ifdef AH_5212_2413
+static const uint32_t ar5212Bank3_2413[][6] = {
+    { 0x000098dc, 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 },
+};
+#endif /* AH_5212_2413 */
+
+#ifdef AH_5212_2316
+static const uint32_t ar5212Bank3_2316[][6] = {
+    { 0x000098dc, 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 },
+};
+#endif
+
+#ifdef AH_5212_5413
+static const uint32_t ar5212Bank3_5413[][6] = {
+    { 0x000098dc, 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 },
+};
+#endif /* AH_5212_5413 */
+
+#ifdef AH_5212_2425
+static const uint32_t ar5212Bank3_2425[][6] = {
+    { 0x000098dc, 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 },
+};
+#endif /* AH_5212_2425 */
+
+#ifdef AH_5212_5111
+static const uint32_t ar5212Bank6_5111[][6] = {
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 },
+    { 0x0000989c, 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 },
+    { 0x0000989c, 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 },
+    { 0x0000989c, 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 },
+    { 0x0000989c, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 },
+    { 0x0000989c, 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 },
+    { 0x000098d4, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a },
+};
+#endif /* AH_5212_5111 */
+
+#ifdef AH_5212_5112
+static const uint32_t ar5212Bank6_5112[][6] = {
+    { 0x0000989c, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 },
+    { 0x0000989c, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 },
+    { 0x0000989c, 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 },
+    { 0x0000989c, 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 },
+    { 0x0000989c, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 },
+    { 0x0000989c, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 },
+    { 0x0000989c, 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 },
+    { 0x0000989c, 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000 },
+    { 0x0000989c, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 },
+    { 0x0000989c, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 },
+    { 0x0000989c, 0x02190000, 0x02190000, 0x02190000, 0x02190000, 0x02190000 },
+    { 0x0000989c, 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 },
+    { 0x0000989c, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 },
+    { 0x0000989c, 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 },
+    { 0x0000989c, 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 },
+    { 0x0000989c, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 },
+    { 0x0000989c, 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 },
+    { 0x0000989c, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 },
+    { 0x0000989c, 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 },
+    { 0x0000989c, 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 },
+    { 0x0000989c, 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 },
+    { 0x0000989c, 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 },
+    { 0x0000989c, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080 },
+    { 0x0000989c, 0x00270019, 0x00270019, 0x00270019, 0x00270019, 0x00270019 },
+    { 0x0000989c, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 },
+    { 0x0000989c, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 },
+    { 0x0000989c, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 },
+    { 0x0000989c, 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 },
+    { 0x0000989c, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 },
+    { 0x000098d8, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 },
+};
+#endif /* AH_5212_5112 */
+
+#ifdef AH_5212_2413
+static const uint32_t ar5212Bank6_2413[][6] = {
+    { 0x0000989c, 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x03000000, 0x03000000, 0x03000000, 0x03000000, 0x03000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x40400000, 0x40400000, 0x40400000, 0x40400000, 0x40400000 },
+    { 0x0000989c, 0x65050000, 0x65050000, 0x65050000, 0x65050000, 0x65050000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00420000, 0x00420000, 0x00420000, 0x00420000, 0x00420000 },
+    { 0x0000989c, 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000 },
+    { 0x0000989c, 0x00030000, 0x00030000, 0x00030000, 0x00030000, 0x00030000 },
+    { 0x0000989c, 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000 },
+    { 0x0000989c, 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000 },
+    { 0x0000989c, 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 },
+    { 0x0000989c, 0x04220000, 0x04220000, 0x04220000, 0x04220000, 0x04220000 },
+    { 0x0000989c, 0x00230018, 0x00230018, 0x00230018, 0x00230018, 0x00230018 },
+    { 0x0000989c, 0x00280000, 0x00280000, 0x00280060, 0x00280060, 0x00280060 },
+    { 0x0000989c, 0x005000c0, 0x005000c0, 0x005000c3, 0x005000c3, 0x005000c3 },
+    { 0x0000989c, 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f },
+    { 0x0000989c, 0x00000458, 0x00000458, 0x00000458, 0x00000458, 0x00000458 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000 },
+    { 0x000098d8, 0x00400230, 0x00400230, 0x00400230, 0x00400230, 0x00400230 },
+};
+#endif /* AH_5212_2413 */
+
+#ifdef AH_5212_2316
+static const uint32_t ar5212Bank6_2316[][6] = {
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000 },
+    { 0x0000989c, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 },
+    { 0x0000989c, 0x02000000, 0x02000000, 0x02000000, 0x02000000, 0x02000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x95150000, 0x95150000, 0x95150000, 0x95150000, 0x95150000 },
+    { 0x0000989c, 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00080000, 0x00080000, 0x00080000, 0x00080000, 0x00080000 },
+    { 0x0000989c, 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000 },
+    { 0x0000989c, 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000 },
+    { 0x0000989c, 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000 },
+    { 0x0000989c, 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 },
+    { 0x0000989c, 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000 },
+    { 0x0000989c, 0x10880000, 0x10880000, 0x10880000, 0x10880000, 0x10880000 },
+    { 0x0000989c, 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060 },
+    { 0x0000989c, 0x00a00000, 0x00a00000, 0x00a00080, 0x00a00080, 0x00a00080 },
+    { 0x0000989c, 0x00400000, 0x00400000, 0x0040000d, 0x0040000d, 0x0040000d },
+    { 0x0000989c, 0x00110400, 0x00110400, 0x00110400, 0x00110400, 0x00110400 },
+    { 0x0000989c, 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 },
+    { 0x0000989c, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 },
+    { 0x0000989c, 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00 },
+    { 0x0000989c, 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8 },
+    { 0x000098c0, 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 },
+};
+#endif
+
+#ifdef AH_5212_5413
+static const uint32_t ar5212Bank6_5413[][6] = {
+    { 0x0000989c, 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 },
+    { 0x0000989c, 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 },
+    { 0x0000989c, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 },
+    { 0x0000989c, 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 },
+    { 0x0000989c, 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 },
+    { 0x0000989c, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 },
+    { 0x0000989c, 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 },
+    { 0x0000989c, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 },
+    { 0x0000989c, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 },
+    { 0x0000989c, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 },
+    { 0x0000989c, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 },
+    { 0x0000989c, 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 },
+    { 0x0000989c, 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 },
+    { 0x0000989c, 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 },
+    { 0x0000989c, 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 },
+    { 0x0000989c, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 },
+    { 0x0000989c, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 },
+    { 0x0000989c, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f },
+    { 0x0000989c, 0x00510040, 0x00510040, 0x00510040, 0x00510040, 0x00510040 },
+    { 0x0000989c, 0x005000da, 0x005000da, 0x005000da, 0x005000da, 0x005000da },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 },
+    { 0x0000989c, 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00002c00 },
+    { 0x000098c8, 0x00000403, 0x00000403, 0x00000403, 0x00000403, 0x00000403 },
+};
+#endif /* AH_5212_5413 */
+
+#ifdef AH_5212_2425
+static const uint32_t ar5212Bank6_2425[][6] = {
+    { 0x0000989c, 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 },
+    { 0x0000989c, 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 },
+    { 0x0000989c, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 },
+    { 0x0000989c, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 },
+    { 0x0000989c, 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 },
+    { 0x0000989c, 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 },
+    { 0x0000989c, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a },
+    { 0x0000989c, 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 },
+    { 0x0000989c, 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 },
+    { 0x0000989c, 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 },
+    { 0x0000989c, 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 },
+    { 0x000098c4, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 },
+};
+#endif /* AH_5212_2425 */
+
+#ifdef AH_5212_2417
+static const uint32_t ar5212Bank6_2417[][6] = {
+    { 0x0000989c, 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 },
+    { 0x0000989c, 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 },
+    { 0x0000989c, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 },
+    { 0x0000989c, 0x00e70000, 0x00e70000, 0x80e70000, 0x80e70000, 0x00e70000 },
+    { 0x0000989c, 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 },
+    { 0x0000989c, 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 },
+    { 0x0000989c, 0x0007001a, 0x0007001a, 0x0207001a, 0x0207001a, 0x0007001a },
+    { 0x0000989c, 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 },
+    { 0x0000989c, 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 },
+    { 0x0000989c, 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 },
+    { 0x0000989c, 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 },
+    { 0x000098c4, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 },
+};
+#endif /* AH_5212_2417 */
+
+#ifdef AH_5212_5111
+static const uint32_t ar5212Bank7_5111[][6] = {
+    { 0x0000989c, 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 },
+    { 0x0000989c, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
+    { 0x0000989c, 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 },
+    { 0x0000989c, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f },
+    { 0x0000989c, 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 },
+    { 0x0000989c, 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f },
+    { 0x0000989c, 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a },
+    { 0x000098cc, 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e },
+};
+#endif /* AH_5212_5111 */
+
+#ifdef AH_5212_5112
+static const uint32_t ar5212Bank7_5112[][6] = {
+    { 0x0000989c, 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 },
+    { 0x0000989c, 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 },
+    { 0x0000989c, 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 },
+    { 0x0000989c, 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 },
+    { 0x0000989c, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 },
+    { 0x0000989c, 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 },
+    { 0x0000989c, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 },
+    { 0x0000989c, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 },
+    { 0x0000989c, 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 },
+    { 0x0000989c, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 },
+    { 0x0000989c, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc },
+    { 0x0000989c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c },
+    { 0x000098c4, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 },
+};
+#endif /* AH_5212_5112 */
+
+#ifdef AH_5212_2413
+static const uint32_t ar5212Bank7_2413[][6] = {
+    { 0x0000989c, 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 },
+    { 0x0000989c, 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 },
+    { 0x000098cc, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e },
+};
+#endif /* AH_5212_2413 */
+
+#ifdef AH_5212_2316
+static const uint32_t ar5212Bank7_2316[][6] = {
+    { 0x0000989c, 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 },
+    { 0x0000989c, 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 },
+    { 0x000098cc, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e },
+};
+#endif
+
+#ifdef AH_5212_5413
+static const uint32_t ar5212Bank7_5413[][6] = {
+    { 0x0000989c, 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 },
+    { 0x0000989c, 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 },
+    { 0x000098cc, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e },
+};
+#endif /* AH_5212_5413 */
+
+#ifdef AH_5212_2317
+static const uint32_t ar5212Modes_2317[][6] = {
+    { 0x00000030, 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 },
+    { 0x0000801c, 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 },
+    { 0x00009838, 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a },
+    { 0x00009848, 0x0018da6d, 0x0018da6d, 0x001a6a67, 0x001a6a67, 0x001a6a67 },
+    { 0x00009850, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da },
+    { 0x00009858, 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e },
+    { 0x0000985c, 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 },
+    { 0x00009944, 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 },
+    { 0x0000a204, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a208, 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 },
+    { 0x0000a20c, 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a },
+};
+
+static const uint32_t ar5212Common_2317[][2] = {
+    { 0x00001230, 0x000003e0 },
+    { 0x00008060, 0x0000000f },
+    { 0x00008118, 0x00000000 },
+    { 0x0000811c, 0x00000000 },
+    { 0x00008120, 0x00000000 },
+    { 0x00008124, 0x00000000 },
+    { 0x00008128, 0x00000000 },
+    { 0x0000812c, 0x00000000 },
+    { 0x00008130, 0x00000000 },
+    { 0x00008134, 0x00000000 },
+    { 0x00008138, 0x00000000 },
+    { 0x0000813c, 0x00000000 },
+    { 0x00008140, 0x800000a8 },
+    { 0x00008144, 0x00000000 },
+    { 0x00009808, 0x00004000 },
+    { 0x0000982c, 0x0000a000 },
+    { 0x0000983c, 0x00200400 },
+    { 0x0000984c, 0x1284233c },
+    { 0x00009870, 0x0000001f },
+    { 0x00009874, 0x00000080 },
+    { 0x00009878, 0x0000000e },
+    { 0x00009958, 0x000000ff },
+    { 0x00009980, 0x00000000 },
+    { 0x00009984, 0x02800000 },
+    { 0x000099a0, 0x00000000 },
+    { 0x000099e0, 0x00000001 },
+    { 0x000099e4, 0xaaaaaaaa },
+    { 0x000099e8, 0x3c466478 },
+    { 0x000099ec, 0x000000aa },
+    { 0x000099f0, 0x0000000c },
+    { 0x000099f4, 0x000000ff },
+    { 0x000099f8, 0x00000014 },
+    { 0x0000a228, 0x000009b5 },
+    { 0x0000a23c, 0x93c889af },
+    { 0x0000a24c, 0x00000001 },
+    { 0x0000a250, 0x0000a000 },
+    { 0x0000a254, 0x00000000 },
+    { 0x0000a258, 0x0cc75380 },
+    { 0x0000a25c, 0x0f0f0f01 },
+    { 0x0000a260, 0x5f690f01 },
+    { 0x0000a264, 0x00418a11 },
+    { 0x0000a268, 0x00000000 },
+    { 0x0000a26c, 0x0c30c16a },
+    { 0x0000a270, 0x00820820 },
+    { 0x0000a274, 0x081a3caa },
+    { 0x0000a278, 0x1ce739ce },
+    { 0x0000a27c, 0x051701ce },
+    { 0x0000a300, 0x16010000 },
+    { 0x0000a304, 0x2c032402 },
+    { 0x0000a308, 0x48433e42 },
+    { 0x0000a30c, 0x5a0f500b },
+    { 0x0000a310, 0x6c4b624a },
+    { 0x0000a314, 0x7e8b748a },
+    { 0x0000a318, 0x96cf8ccb },
+    { 0x0000a31c, 0xa34f9d0f },
+    { 0x0000a320, 0xa7cfa58f },
+    { 0x0000a348, 0x3fffffff },
+    { 0x0000a34c, 0x3fffffff },
+    { 0x0000a350, 0x3fffffff },
+    { 0x0000a354, 0x0003ffff },
+    { 0x0000a358, 0x79a8aa1f },
+    { 0x0000a35c, 0x066c420f },
+    { 0x0000a360, 0x0f282207 },
+    { 0x0000a364, 0x17601685 },
+    { 0x0000a368, 0x1f801104 },
+    { 0x0000a36c, 0x37a00c03 },
+    { 0x0000a370, 0x3fc40883 },
+    { 0x0000a374, 0x57c00803 },
+    { 0x0000a378, 0x5fd80682 },
+    { 0x0000a37c, 0x7fe00482 },
+    { 0x0000a380, 0x7f3c7bba },
+    { 0x0000a384, 0xf3307ff0 },
+    { 0x00009b04, 0x00000001 },
+    { 0x00009b08, 0x00000002 },
+    { 0x00009b0c, 0x00000003 },
+    { 0x00009b10, 0x00000004 },
+    { 0x00009b14, 0x00000005 },
+    { 0x00009b18, 0x00000008 },
+    { 0x00009b1c, 0x00000009 },
+    { 0x00009b20, 0x0000000a },
+    { 0x00009b24, 0x0000000b },
+    { 0x00009b2c, 0x0000000d },
+    { 0x00009b30, 0x00000010 },
+    { 0x00009b34, 0x00000011 },
+    { 0x00009b3c, 0x00000013 },
+    { 0x00009b40, 0x00000014 },
+    { 0x00009b44, 0x00000015 },
+    { 0x00009b48, 0x00000018 },
+    { 0x00009b4c, 0x00000019 },
+    { 0x00009b50, 0x0000001a },
+    { 0x00009b54, 0x0000001b },
+    { 0x00009b58, 0x0000001c },
+    { 0x00009b5c, 0x0000001d },
+    { 0x00009b60, 0x00000020 },
+    { 0x00009b68, 0x00000022 },
+    { 0x00009b6c, 0x00000023 },
+    { 0x00009b70, 0x00000024 },
+    { 0x00009b74, 0x00000025 },
+    { 0x00009b78, 0x00000028 },
+    { 0x00009b7c, 0x00000029 },
+    { 0x00009b80, 0x0000002a },
+    { 0x00009b84, 0x0000002b },
+    { 0x00009b88, 0x0000002c },
+    { 0x00009b90, 0x00000030 },
+    { 0x00009b94, 0x00000031 },
+    { 0x00009b98, 0x00000032 },
+    { 0x00009ba0, 0x00000034 },
+    { 0x00009ba4, 0x00000035 },
+    { 0x00009ba8, 0x00000035 },
+    { 0x00009bac, 0x00000035 },
+    { 0x00009bb0, 0x00000035 },
+    { 0x00009bb4, 0x00000035 },
+    { 0x00009bb8, 0x00000035 },
+    { 0x00009bbc, 0x00000035 },
+    { 0x00009bc0, 0x00000035 },
+    { 0x00009bc4, 0x00000035 },
+    { 0x00009bc8, 0x00000035 },
+    { 0x00009bcc, 0x00000035 },
+    { 0x00009bd0, 0x00000035 },
+    { 0x00009bd4, 0x00000035 },
+    { 0x00009bd8, 0x00000035 },
+    { 0x00009bdc, 0x00000035 },
+    { 0x00009be0, 0x00000035 },
+    { 0x00009be4, 0x00000035 },
+    { 0x00009be8, 0x00000035 },
+    { 0x00009bec, 0x00000035 },
+    { 0x00009bf0, 0x00000035 },
+    { 0x00009bf4, 0x00000035 },
+    { 0x00009bf8, 0x00000010 },
+    { 0x00009bfc, 0x0000001a },
+};
+
+static const uint32_t ar5212BB_RfGain_2317[][3] = {
+    { 0x00009a00, 0x00000000, 0x00000000 },
+    { 0x00009a04, 0x00000000, 0x00000040 },
+    { 0x00009a08, 0x00000000, 0x00000080 },
+    { 0x00009a0c, 0x00000000, 0x00000181 },
+    { 0x00009a10, 0x00000000, 0x000001c1 },
+    { 0x00009a14, 0x00000000, 0x00000001 },
+    { 0x00009a18, 0x00000000, 0x00000041 },
+    { 0x00009a1c, 0x00000000, 0x00000081 },
+    { 0x00009a20, 0x00000000, 0x00000188 },
+    { 0x00009a24, 0x00000000, 0x000001c8 },
+    { 0x00009a28, 0x00000000, 0x00000008 },
+    { 0x00009a2c, 0x00000000, 0x00000048 },
+    { 0x00009a30, 0x00000000, 0x00000088 },
+    { 0x00009a34, 0x00000000, 0x00000189 },
+    { 0x00009a38, 0x00000000, 0x000001c9 },
+    { 0x00009a3c, 0x00000000, 0x00000009 },
+    { 0x00009a40, 0x00000000, 0x00000049 },
+    { 0x00009a44, 0x00000000, 0x00000089 },
+    { 0x00009a48, 0x00000000, 0x00000190 },
+    { 0x00009a4c, 0x00000000, 0x000001d0 },
+    { 0x00009a50, 0x00000000, 0x00000010 },
+    { 0x00009a54, 0x00000000, 0x00000050 },
+    { 0x00009a58, 0x00000000, 0x00000090 },
+    { 0x00009a5c, 0x00000000, 0x00000191 },
+    { 0x00009a60, 0x00000000, 0x000001d1 },
+    { 0x00009a64, 0x00000000, 0x00000011 },
+    { 0x00009a68, 0x00000000, 0x00000051 },
+    { 0x00009a6c, 0x00000000, 0x00000091 },
+    { 0x00009a70, 0x00000000, 0x00000178 },
+    { 0x00009a74, 0x00000000, 0x000001b8 },
+    { 0x00009a78, 0x00000000, 0x000001f8 },
+    { 0x00009a7c, 0x00000000, 0x00000038 },
+    { 0x00009a80, 0x00000000, 0x00000078 },
+    { 0x00009a84, 0x00000000, 0x00000179 },
+    { 0x00009a88, 0x00000000, 0x000001b9 },
+    { 0x00009a8c, 0x00000000, 0x000001f9 },
+    { 0x00009a90, 0x00000000, 0x00000039 },
+    { 0x00009a94, 0x00000000, 0x00000079 },
+    { 0x00009a98, 0x00000000, 0x000000b9 },
+    { 0x00009a9c, 0x00000000, 0x000000f9 },
+    { 0x00009aa0, 0x00000000, 0x000000f9 },
+    { 0x00009aa4, 0x00000000, 0x000000f9 },
+    { 0x00009aa8, 0x00000000, 0x000000f9 },
+    { 0x00009aac, 0x00000000, 0x000000f9 },
+    { 0x00009ab0, 0x00000000, 0x000000f9 },
+    { 0x00009ab4, 0x00000000, 0x000000f9 },
+    { 0x00009ab8, 0x00000000, 0x000000f9 },
+    { 0x00009abc, 0x00000000, 0x000000f9 },
+    { 0x00009ac0, 0x00000000, 0x000000f9 },
+    { 0x00009ac4, 0x00000000, 0x000000f9 },
+    { 0x00009ac8, 0x00000000, 0x000000f9 },
+    { 0x00009acc, 0x00000000, 0x000000f9 },
+    { 0x00009ad0, 0x00000000, 0x000000f9 },
+    { 0x00009ad4, 0x00000000, 0x000000f9 },
+    { 0x00009ad8, 0x00000000, 0x000000f9 },
+    { 0x00009adc, 0x00000000, 0x000000f9 },
+    { 0x00009ae0, 0x00000000, 0x000000f9 },
+    { 0x00009ae4, 0x00000000, 0x000000f9 },
+    { 0x00009ae8, 0x00000000, 0x000000f9 },
+    { 0x00009aec, 0x00000000, 0x000000f9 },
+    { 0x00009af0, 0x00000000, 0x000000f9 },
+    { 0x00009af4, 0x00000000, 0x000000f9 },
+    { 0x00009af8, 0x00000000, 0x000000f9 },
+    { 0x00009afc, 0x00000000, 0x000000f9 },
+};
+
+static const uint32_t ar5212Bank1_2317[][2] = {
+    { 0x000098d4, 0x00000020 },
+};
+
+static const uint32_t ar5212Bank2_2317[][6] = {
+    { 0x000098d0, 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 },
+};
+
+static const uint32_t ar5212Bank3_2317[][6] = {
+    { 0x000098dc, 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 },
+};
+
+static const uint32_t ar5212Bank6_2317[][6] = {
+    { 0x0000989c, 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 },
+    { 0x0000989c, 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 },
+    { 0x0000989c, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 },
+    { 0x0000989c, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 },
+    { 0x0000989c, 0x00140100, 0x00140100, 0x00140100, 0x00140100, 0x00140100 },
+    { 0x0000989c, 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 },
+    { 0x0000989c, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a },
+    { 0x0000989c, 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 },
+    { 0x0000989c, 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 },
+    { 0x0000989c, 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 },
+    { 0x0000989c, 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 },
+    { 0x000098c4, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 },
+};
+
+static const uint32_t ar5212Bank7_2317[][6] = {
+    { 0x0000989c, 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 },
+    { 0x0000989c, 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 },
+    { 0x000098cc, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e },
+};
+#endif /* AH_5212_2317 */
+
+#ifdef AH_5212_2425
+static const uint32_t ar5212Bank7_2425[][6] = {
+    { 0x0000989c, 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 },
+    { 0x0000989c, 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 },
+    { 0x000098cc, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e },
+};
+#endif /* AH_5212_2425 */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_ani.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_ani.c
new file mode 100644
index 0000000..df4d737
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_ani.c
@@ -0,0 +1,1016 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c,v 1.2.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_desc.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+/*
+ * Anti noise immunity support.  We track phy errors and react
+ * to excessive errors by adjusting the noise immunity parameters.
+ */
+
+#define HAL_EP_RND(x, mul) \
+	((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
+#define	BEACON_RSSI(ahp) \
+	HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
+		HAL_RSSI_EP_MULTIPLIER)
+
+/*
+ * ANI processing tunes radio parameters according to PHY errors
+ * and related information.  This is done for for noise and spur
+ * immunity in all operating modes if the device indicates it's
+ * capable at attach time.  In addition, when there is a reference
+ * rssi value (e.g. beacon frames from an ap in station mode)
+ * further tuning is done.
+ *
+ * ANI_ENA indicates whether any ANI processing should be done;
+ * this is specified at attach time.
+ *
+ * ANI_ENA_RSSI indicates whether rssi-based processing should
+ * done, this is enabled based on operating mode and is meaningful
+ * only if ANI_ENA is true.
+ *
+ * ANI parameters are typically controlled only by the hal.  The
+ * AniControl interface however permits manual tuning through the
+ * diagnostic api.
+ */
+#define ANI_ENA(ah) \
+	(AH5212(ah)->ah_procPhyErr & HAL_ANI_ENA)
+#define ANI_ENA_RSSI(ah) \
+	(AH5212(ah)->ah_procPhyErr & HAL_RSSI_ANI_ENA)
+
+#define	ah_mibStats	ah_stats.ast_mibstats
+
+static void
+enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "
+	    "OfdmPhyErrBase 0x%x cckPhyErrBase 0x%x\n",
+	    __func__, params->ofdmPhyErrBase, params->cckPhyErrBase);
+
+	OS_REG_WRITE(ah, AR_FILTOFDM, 0);
+	OS_REG_WRITE(ah, AR_FILTCCK, 0);
+
+	OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
+	OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
+	OS_REG_WRITE(ah, AR_PHYCNTMASK1, AR_PHY_ERR_OFDM_TIMING);
+	OS_REG_WRITE(ah, AR_PHYCNTMASK2, AR_PHY_ERR_CCK_TIMING);
+
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);	/* save+clear counters*/
+	ar5212EnableMibCounters(ah);			/* enable everything */
+}
+
+static void 
+disableAniMIBCounters(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_ANI, "Disable MIB counters\n");
+
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);	/* save stats */
+	ar5212DisableMibCounters(ah);			/* disable everything */
+
+	OS_REG_WRITE(ah, AR_PHYCNTMASK1, 0);
+	OS_REG_WRITE(ah, AR_PHYCNTMASK2, 0);
+}
+
+/*
+ * This routine returns the index into the aniState array that
+ * corresponds to the channel in *chan.  If no match is found and the
+ * array is still not fully utilized, a new entry is created for the
+ * channel.  We assume the attach function has already initialized the
+ * ah_ani values and only the channel field needs to be set.
+ */
+static int
+ar5212GetAniChannelIndex(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+#define N(a)     (sizeof(a) / sizeof(a[0]))
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	int i;
+
+	for (i = 0; i < N(ahp->ah_ani); i++) {
+		struct ar5212AniState *asp = &ahp->ah_ani[i];
+		if (asp->c.channel == chan->channel)
+			return i;
+		if (asp->c.channel == 0) {
+			asp->c.channel = chan->channel;
+			asp->c.channelFlags = chan->channelFlags;
+			asp->c.privFlags = chan->privFlags;
+			asp->isSetup = AH_FALSE;
+			if (IS_CHAN_2GHZ(chan))
+				asp->params = &ahp->ah_aniParams24;
+			else
+				asp->params = &ahp->ah_aniParams5;
+			return i;
+		}
+	}
+	/* XXX statistic */
+	HALDEBUG(ah, HAL_DEBUG_ANY,
+	    "No more channel states left. Using channel 0\n");
+	return 0;		/* XXX gotta return something valid */
+#undef N
+}
+
+/*
+ * Return the current ANI state of the channel we're on
+ */
+struct ar5212AniState *
+ar5212AniGetCurrentState(struct ath_hal *ah)
+{
+	return AH5212(ah)->ah_curani;
+}
+
+/*
+ * Return the current statistics.
+ */
+struct ar5212Stats *
+ar5212AniGetCurrentStats(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	/* update mib stats so we return current data */
+	/* XXX? side-effects to doing this here? */
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
+	return &ahp->ah_stats;
+}
+
+static void
+setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)
+{
+	if (params->ofdmTrigHigh >= AR_PHY_COUNTMAX) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "OFDM Trigger %d is too high for hw counters, using max\n",
+		    params->ofdmTrigHigh);
+		params->ofdmPhyErrBase = 0;
+	} else
+		params->ofdmPhyErrBase = AR_PHY_COUNTMAX - params->ofdmTrigHigh;
+	if (params->cckTrigHigh >= AR_PHY_COUNTMAX) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "CCK Trigger %d is too high for hw counters, using max\n",
+		    params->cckTrigHigh);
+		params->cckPhyErrBase = 0;
+	} else
+		params->cckPhyErrBase = AR_PHY_COUNTMAX - params->cckTrigHigh;
+}
+
+/*
+ * Setup ANI handling.  Sets all thresholds and reset the
+ * channel statistics.  Note that ar5212AniReset should be
+ * called by ar5212Reset before anything else happens and
+ * that's where we force initial settings.
+ */
+void
+ar5212AniAttach(struct ath_hal *ah, const struct ar5212AniParams *params24,
+	const struct ar5212AniParams *params5, HAL_BOOL enable)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	ahp->ah_hasHwPhyCounters =
+		AH_PRIVATE(ah)->ah_caps.halHwPhyCounterSupport;
+
+	if (params24 != AH_NULL) {
+		OS_MEMCPY(&ahp->ah_aniParams24, params24, sizeof(*params24));
+		setPhyErrBase(ah, &ahp->ah_aniParams24);
+	}
+	if (params5 != AH_NULL) {
+		OS_MEMCPY(&ahp->ah_aniParams5, params5, sizeof(*params5));
+		setPhyErrBase(ah, &ahp->ah_aniParams5);
+	}
+
+	OS_MEMZERO(ahp->ah_ani, sizeof(ahp->ah_ani));
+	if (ahp->ah_hasHwPhyCounters) {
+		/* Enable MIB Counters */
+		enableAniMIBCounters(ah, &ahp->ah_aniParams24 /*XXX*/);
+	}
+	if (enable) {		/* Enable ani now */
+		HALASSERT(params24 != AH_NULL && params5 != AH_NULL);
+		ahp->ah_procPhyErr |= HAL_ANI_ENA;
+	} else {
+		ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
+	}
+}
+
+HAL_BOOL
+ar5212AniSetParams(struct ath_hal *ah, const struct ar5212AniParams *params24,
+	const struct ar5212AniParams *params5)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_BOOL ena = (ahp->ah_procPhyErr & HAL_ANI_ENA) != 0;
+
+	ar5212AniControl(ah, HAL_ANI_MODE, AH_FALSE);
+
+	OS_MEMCPY(&ahp->ah_aniParams24, params24, sizeof(*params24));
+	setPhyErrBase(ah, &ahp->ah_aniParams24);
+	OS_MEMCPY(&ahp->ah_aniParams5, params5, sizeof(*params5));
+	setPhyErrBase(ah, &ahp->ah_aniParams5);
+
+	OS_MEMZERO(ahp->ah_ani, sizeof(ahp->ah_ani));
+	ar5212AniReset(ah, AH_PRIVATE(ah)->ah_curchan,
+	    AH_PRIVATE(ah)->ah_opmode, AH_FALSE);
+
+	ar5212AniControl(ah, HAL_ANI_MODE, ena);
+
+	return AH_TRUE;
+}
+
+/*
+ * Cleanup any ANI state setup.
+ */
+void
+ar5212AniDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");
+	if (ahp->ah_hasHwPhyCounters)
+		disableAniMIBCounters(ah);
+}
+
+/*
+ * Control Adaptive Noise Immunity Parameters
+ */
+HAL_BOOL
+ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
+{
+	typedef int TABLE[];
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState = ahp->ah_curani;
+	const struct ar5212AniParams *params = aniState->params;
+
+	OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);
+
+	switch (cmd) {
+	case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
+		u_int level = param;
+
+		if (level > params->maxNoiseImmunityLevel) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: level out of range (%u > %u)\n",
+			    __func__, level, params->maxNoiseImmunityLevel);
+			return AH_FALSE;
+		}
+
+		OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+		    AR_PHY_DESIRED_SZ_TOT_DES, params->totalSizeDesired[level]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
+		    AR_PHY_AGC_CTL1_COARSE_LOW, params->coarseLow[level]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
+		    AR_PHY_AGC_CTL1_COARSE_HIGH, params->coarseHigh[level]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+		    AR_PHY_FIND_SIG_FIRPWR, params->firpwr[level]);
+
+		if (level > aniState->noiseImmunityLevel)
+			ahp->ah_stats.ast_ani_niup++;
+		else if (level < aniState->noiseImmunityLevel)
+			ahp->ah_stats.ast_ani_nidown++;
+		aniState->noiseImmunityLevel = level;
+		break;
+	}
+	case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: {
+		static const TABLE m1ThreshLow   = { 127,   50 };
+		static const TABLE m2ThreshLow   = { 127,   40 };
+		static const TABLE m1Thresh      = { 127, 0x4d };
+		static const TABLE m2Thresh      = { 127, 0x40 };
+		static const TABLE m2CountThr    = {  31,   16 };
+		static const TABLE m2CountThrLow = {  63,   48 };
+		u_int on = param ? 1 : 0;
+
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
+
+		if (on) {
+			OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
+				AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+		} else {
+			OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
+				AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+		}
+		if (on)
+			ahp->ah_stats.ast_ani_ofdmon++;
+		else
+			ahp->ah_stats.ast_ani_ofdmoff++;
+		aniState->ofdmWeakSigDetectOff = !on;
+		break;
+	}
+	case HAL_ANI_CCK_WEAK_SIGNAL_THR: {
+		static const TABLE weakSigThrCck = { 8, 6 };
+		u_int high = param ? 1 : 0;
+
+		OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
+		    AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]);
+		if (high)
+			ahp->ah_stats.ast_ani_cckhigh++;
+		else
+			ahp->ah_stats.ast_ani_ccklow++;
+		aniState->cckWeakSigThreshold = high;
+		break;
+	}
+	case HAL_ANI_FIRSTEP_LEVEL: {
+		u_int level = param;
+
+		if (level > params->maxFirstepLevel) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: level out of range (%u > %u)\n",
+			    __func__, level, params->maxFirstepLevel);
+			return AH_FALSE;
+		}
+		OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+		    AR_PHY_FIND_SIG_FIRSTEP, params->firstep[level]);
+		if (level > aniState->firstepLevel)
+			ahp->ah_stats.ast_ani_stepup++;
+		else if (level < aniState->firstepLevel)
+			ahp->ah_stats.ast_ani_stepdown++;
+		aniState->firstepLevel = level;
+		break;
+	}
+	case HAL_ANI_SPUR_IMMUNITY_LEVEL: {
+		u_int level = param;
+
+		if (level > params->maxSpurImmunityLevel) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: level out of range (%u > %u)\n",
+			    __func__, level, params->maxSpurImmunityLevel);
+			return AH_FALSE;
+		}
+		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
+		    AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]);
+		if (level > aniState->spurImmunityLevel)
+			ahp->ah_stats.ast_ani_spurup++;
+		else if (level < aniState->spurImmunityLevel)
+			ahp->ah_stats.ast_ani_spurdown++;
+		aniState->spurImmunityLevel = level;
+		break;
+	}
+	case HAL_ANI_PRESENT:
+		break;
+	case HAL_ANI_MODE:
+		if (param == 0) {
+			ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
+			/* Turn off HW counters if we have them */
+			ar5212AniDetach(ah);
+			ar5212SetRxFilter(ah,
+				ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
+		} else {			/* normal/auto mode */
+			/* don't mess with state if already enabled */
+			if (ahp->ah_procPhyErr & HAL_ANI_ENA)
+				break;
+			if (ahp->ah_hasHwPhyCounters) {
+				ar5212SetRxFilter(ah,
+					ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
+				/* Enable MIB Counters */
+				enableAniMIBCounters(ah,
+				    ahp->ah_curani != AH_NULL ?
+					ahp->ah_curani->params:
+					&ahp->ah_aniParams24 /*XXX*/);
+			} else {
+				ar5212SetRxFilter(ah,
+					ar5212GetRxFilter(ah) | HAL_RX_FILTER_PHYERR);
+			}
+			ahp->ah_procPhyErr |= HAL_ANI_ENA;
+		}
+		break;
+#ifdef AH_PRIVATE_DIAG
+	case HAL_ANI_PHYERR_RESET:
+		ahp->ah_stats.ast_ani_ofdmerrs = 0;
+		ahp->ah_stats.ast_ani_cckerrs = 0;
+		break;
+#endif /* AH_PRIVATE_DIAG */
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid cmd %u\n",
+		    __func__, cmd);
+		return AH_FALSE;
+	}
+	return AH_TRUE;
+}
+
+static void
+ar5212AniOfdmErrTrigger(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	struct ar5212AniState *aniState;
+	const struct ar5212AniParams *params;
+
+	HALASSERT(chan != AH_NULL);
+
+	if (!ANI_ENA(ah))
+		return;
+
+	aniState = ahp->ah_curani;
+	params = aniState->params;
+	/* First, raise noise immunity level, up to max */
+	if (aniState->noiseImmunityLevel+1 <= params->maxNoiseImmunityLevel) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
+		    aniState->noiseImmunityLevel + 1);
+		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 
+				 aniState->noiseImmunityLevel + 1);
+		return;
+	}
+	/* then, raise spur immunity level, up to max */
+	if (aniState->spurImmunityLevel+1 <= params->maxSpurImmunityLevel) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise SI to %u\n", __func__,
+		    aniState->spurImmunityLevel + 1);
+		ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+				 aniState->spurImmunityLevel + 1);
+		return;
+	}
+
+	if (ANI_ENA_RSSI(ah)) {
+		int32_t rssi = BEACON_RSSI(ahp);
+		if (rssi > params->rssiThrHigh) {
+			/*
+			 * Beacon rssi is high, can turn off ofdm
+			 * weak sig detect.
+			 */
+			if (!aniState->ofdmWeakSigDetectOff) {
+				HALDEBUG(ah, HAL_DEBUG_ANI,
+				    "%s: rssi %d OWSD off\n", __func__, rssi);
+				ar5212AniControl(ah,
+				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				    AH_FALSE);
+				ar5212AniControl(ah,
+				    HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
+				return;
+			}
+			/* 
+			 * If weak sig detect is already off, as last resort,
+			 * raise firstep level 
+			 */
+			if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
+				HALDEBUG(ah, HAL_DEBUG_ANI,
+				    "%s: rssi %d raise ST %u\n", __func__, rssi,
+				    aniState->firstepLevel+1);
+				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+						 aniState->firstepLevel + 1);
+				return;
+			}
+		} else if (rssi > params->rssiThrLow) {
+			/* 
+			 * Beacon rssi in mid range, need ofdm weak signal
+			 * detect, but we can raise firststepLevel.
+			 */
+			if (aniState->ofdmWeakSigDetectOff) {
+				HALDEBUG(ah, HAL_DEBUG_ANI,
+				    "%s: rssi %d OWSD on\n", __func__, rssi);
+				ar5212AniControl(ah,
+				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				    AH_TRUE);
+			}
+			if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
+				HALDEBUG(ah, HAL_DEBUG_ANI,
+				    "%s: rssi %d raise ST %u\n", __func__, rssi,
+				    aniState->firstepLevel+1);
+				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+				     aniState->firstepLevel + 1);
+			}
+			return;
+		} else {
+			/* 
+			 * Beacon rssi is low, if in 11b/g mode, turn off ofdm
+			 * weak signal detection and zero firstepLevel to
+			 * maximize CCK sensitivity 
+			 */
+			/* XXX can optimize */
+			if (IS_CHAN_B(chan) || IS_CHAN_G(chan)) {
+				if (!aniState->ofdmWeakSigDetectOff) {
+					HALDEBUG(ah, HAL_DEBUG_ANI,
+					    "%s: rssi %d OWSD off\n",
+					    __func__, rssi);
+					ar5212AniControl(ah,
+					    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+					    AH_FALSE);
+				}
+				if (aniState->firstepLevel > 0) {
+					HALDEBUG(ah, HAL_DEBUG_ANI,
+					    "%s: rssi %d zero ST (was %u)\n",
+					    __func__, rssi,
+					    aniState->firstepLevel);
+					ar5212AniControl(ah,
+					     HAL_ANI_FIRSTEP_LEVEL, 0);
+				}
+				return;
+			}
+		}
+	}
+}
+
+static void
+ar5212AniCckErrTrigger(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	struct ar5212AniState *aniState;
+	const struct ar5212AniParams *params;
+
+	HALASSERT(chan != AH_NULL);
+
+	if (!ANI_ENA(ah))
+		return;
+
+	/* first, raise noise immunity level, up to max */
+	aniState = ahp->ah_curani;
+	params = aniState->params;
+	if (aniState->noiseImmunityLevel+1 <= params->maxNoiseImmunityLevel) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: raise NI to %u\n", __func__,
+		    aniState->noiseImmunityLevel + 1);
+		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+				 aniState->noiseImmunityLevel + 1);
+		return;
+	}
+
+	if (ANI_ENA_RSSI(ah)) {
+		int32_t rssi = BEACON_RSSI(ahp);
+		if (rssi >  params->rssiThrLow) {
+			/*
+			 * Beacon signal in mid and high range,
+			 * raise firstep level.
+			 */
+			if (aniState->firstepLevel+1 <= params->maxFirstepLevel) {
+				HALDEBUG(ah, HAL_DEBUG_ANI,
+				    "%s: rssi %d raise ST %u\n", __func__, rssi,
+				    aniState->firstepLevel+1);
+				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+						 aniState->firstepLevel + 1);
+			}
+		} else {
+			/*
+			 * Beacon rssi is low, zero firstep level to maximize
+			 * CCK sensitivity in 11b/g mode.
+			 */
+			/* XXX can optimize */
+			if (IS_CHAN_B(chan) || IS_CHAN_G(chan)) {
+				if (aniState->firstepLevel > 0) {
+					HALDEBUG(ah, HAL_DEBUG_ANI,
+					    "%s: rssi %d zero ST (was %u)\n",
+					    __func__, rssi,
+					    aniState->firstepLevel);
+					ar5212AniControl(ah,
+					    HAL_ANI_FIRSTEP_LEVEL, 0);
+				}
+			}
+		}
+	}
+}
+
+static void
+ar5212AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	aniState->listenTime = 0;
+	if (ahp->ah_hasHwPhyCounters) {
+		const struct ar5212AniParams *params = aniState->params;
+		/*
+		 * NB: these are written on reset based on the
+		 *     ini so we must re-write them!
+		 */
+		OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
+		OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
+		OS_REG_WRITE(ah, AR_PHYCNTMASK1, AR_PHY_ERR_OFDM_TIMING);
+		OS_REG_WRITE(ah, AR_PHYCNTMASK2, AR_PHY_ERR_CCK_TIMING);
+
+		/* Clear the mib counters and save them in the stats */
+		ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
+	}
+	aniState->ofdmPhyErrCount = 0;
+	aniState->cckPhyErrCount = 0;
+}
+
+/*
+ * Restore/reset the ANI parameters and reset the statistics.
+ * This routine must be called for every channel change.
+ *
+ * NOTE: This is where ah_curani is set; other ani code assumes
+ *       it is setup to reflect the current channel.
+ */
+void
+ar5212AniReset(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+	HAL_OPMODE opmode, int restore)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState;
+	uint32_t rxfilter;
+	int index;
+
+	index = ar5212GetAniChannelIndex(ah, chan);
+	aniState = &ahp->ah_ani[index];
+	ahp->ah_curani = aniState;
+#if 0
+	ath_hal_printf(ah,"%s: chan %u/0x%x restore %d setup %d opmode %u\n",
+	    __func__, chan->channel, chan->channelFlags, restore,
+	    aniState->isSetup, opmode);
+#else
+	HALDEBUG(ah, HAL_DEBUG_ANI,
+	    "%s: chan %u/0x%x restore %d setup %d opmode %u\n",
+	    __func__, chan->channel, chan->channelFlags, restore,
+	    aniState->isSetup, opmode);
+#endif
+	OS_MARK(ah, AH_MARK_ANI_RESET, opmode);
+
+	/*
+	 * Turn off PHY error frame delivery while we futz with settings.
+	 */
+	rxfilter = ar5212GetRxFilter(ah);
+	ar5212SetRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);
+	/*
+	 * Automatic processing is done only in station mode right now.
+	 */
+	if (opmode == HAL_M_STA)
+		ahp->ah_procPhyErr |= HAL_RSSI_ANI_ENA;
+	else
+		ahp->ah_procPhyErr &= ~HAL_RSSI_ANI_ENA;
+	/*
+	 * Set all ani parameters.  We either set them to initial
+	 * values or restore the previous ones for the channel.
+	 * XXX if ANI follows hardware, we don't care what mode we're
+	 * XXX in, we should keep the ani parameters
+	 */
+	if (restore && aniState->isSetup) {
+		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+				 aniState->noiseImmunityLevel);
+		ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+				 aniState->spurImmunityLevel);
+		ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				 !aniState->ofdmWeakSigDetectOff);
+		ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
+				 aniState->cckWeakSigThreshold);
+		ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+				 aniState->firstepLevel);
+	} else {
+		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
+		ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
+		ar5212AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+			AH_TRUE);
+		ar5212AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
+		ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
+		aniState->isSetup = AH_TRUE;
+	}
+	ar5212AniRestart(ah, aniState);
+
+	/* restore RX filter mask */
+	ar5212SetRxFilter(ah, rxfilter);
+}
+
+/*
+ * Process a MIB interrupt.  We may potentially be invoked because
+ * any of the MIB counters overflow/trigger so don't assume we're
+ * here because a PHY error counter triggered.
+ */
+void
+ar5212ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	uint32_t phyCnt1, phyCnt2;
+
+	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "
+	    "filtofdm 0x%x filtcck 0x%x\n",
+	    __func__, OS_REG_READ(ah, AR_MIBC),
+	    OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
+	    OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
+
+	/*
+	 * First order of business is to clear whatever caused
+	 * the interrupt so we don't keep getting interrupted.
+	 * We have the usual mib counters that are reset-on-read
+	 * and the additional counters that appeared starting in
+	 * Hainan.  We collect the mib counters and explicitly
+	 * zero additional counters we are not using.  Anything
+	 * else is reset only if it caused the interrupt.
+	 */
+	/* NB: these are not reset-on-read */
+	phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);
+	phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);
+	/* not used, always reset them in case they are the cause */
+	OS_REG_WRITE(ah, AR_FILTOFDM, 0);
+	OS_REG_WRITE(ah, AR_FILTCCK, 0);
+
+	/* Clear the mib counters and save them in the stats */
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
+	ahp->ah_stats.ast_nodestats = *stats;
+
+	/*
+	 * Check for an ani stat hitting the trigger threshold.
+	 * When this happens we get a MIB interrupt and the top
+	 * 2 bits of the counter register will be 0b11, hence
+	 * the mask check of phyCnt?.
+	 */
+	if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 
+	    ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
+		struct ar5212AniState *aniState = ahp->ah_curani;
+		const struct ar5212AniParams *params = aniState->params;
+		uint32_t ofdmPhyErrCnt, cckPhyErrCnt;
+
+		ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
+		ahp->ah_stats.ast_ani_ofdmerrs +=
+			ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
+		aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
+
+		cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
+		ahp->ah_stats.ast_ani_cckerrs +=
+			cckPhyErrCnt - aniState->cckPhyErrCount;
+		aniState->cckPhyErrCount = cckPhyErrCnt;
+
+		/*
+		 * NB: figure out which counter triggered.  If both
+		 * trigger we'll only deal with one as the processing
+		 * clobbers the error counter so the trigger threshold
+		 * check will never be true.
+		 */
+		if (aniState->ofdmPhyErrCount > params->ofdmTrigHigh)
+			ar5212AniOfdmErrTrigger(ah);
+		if (aniState->cckPhyErrCount > params->cckTrigHigh)
+			ar5212AniCckErrTrigger(ah);
+		/* NB: always restart to insure the h/w counters are reset */
+		ar5212AniRestart(ah, aniState);
+	}
+}
+
+void 
+ar5212AniPhyErrReport(struct ath_hal *ah, const struct ath_rx_status *rs)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState;
+	const struct ar5212AniParams *params;
+
+	HALASSERT(!ahp->ah_hasHwPhyCounters && rs != AH_NULL);
+
+	aniState = ahp->ah_curani;
+	params = aniState->params;
+	if (rs->rs_phyerr == HAL_PHYERR_OFDM_TIMING) {
+		aniState->ofdmPhyErrCount++;
+		ahp->ah_stats.ast_ani_ofdmerrs++;
+		if (aniState->ofdmPhyErrCount > params->ofdmTrigHigh) {
+			ar5212AniOfdmErrTrigger(ah);
+			ar5212AniRestart(ah, aniState);
+		}
+	} else if (rs->rs_phyerr == HAL_PHYERR_CCK_TIMING) {
+		aniState->cckPhyErrCount++;
+		ahp->ah_stats.ast_ani_cckerrs++;
+		if (aniState->cckPhyErrCount > params->cckTrigHigh) {
+			ar5212AniCckErrTrigger(ah);
+			ar5212AniRestart(ah, aniState);
+		}
+	}
+}
+
+static void
+ar5212AniLowerImmunity(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState;
+	const struct ar5212AniParams *params;
+	
+	HALASSERT(ANI_ENA(ah));
+
+	aniState = ahp->ah_curani;
+	params = aniState->params;
+	if (ANI_ENA_RSSI(ah)) {
+		int32_t rssi = BEACON_RSSI(ahp);
+		if (rssi > params->rssiThrHigh) {
+			/* 
+			 * Beacon signal is high, leave ofdm weak signal
+			 * detection off or it may oscillate.  Let it fall
+			 * through.
+			 */
+		} else if (rssi > params->rssiThrLow) {
+			/*
+			 * Beacon rssi in mid range, turn on ofdm weak signal
+			 * detection or lower firstep level.
+			 */
+			if (aniState->ofdmWeakSigDetectOff) {
+				HALDEBUG(ah, HAL_DEBUG_ANI,
+				    "%s: rssi %d OWSD on\n", __func__, rssi);
+				ar5212AniControl(ah,
+				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				    AH_TRUE);
+				return;
+			}
+			if (aniState->firstepLevel > 0) {
+				HALDEBUG(ah, HAL_DEBUG_ANI,
+				    "%s: rssi %d lower ST %u\n", __func__, rssi,
+				    aniState->firstepLevel-1);
+				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+						 aniState->firstepLevel - 1);
+				return;
+			}
+		} else {
+			/*
+			 * Beacon rssi is low, reduce firstep level.
+			 */
+			if (aniState->firstepLevel > 0) {
+				HALDEBUG(ah, HAL_DEBUG_ANI,
+				    "%s: rssi %d lower ST %u\n", __func__, rssi,
+				    aniState->firstepLevel-1);
+				ar5212AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+						 aniState->firstepLevel - 1);
+				return;
+			}
+		}
+	}
+	/* then lower spur immunity level, down to zero */
+	if (aniState->spurImmunityLevel > 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower SI %u\n",
+		    __func__, aniState->spurImmunityLevel-1);
+		ar5212AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+				 aniState->spurImmunityLevel - 1);
+		return;
+	}
+	/* 
+	 * if all else fails, lower noise immunity level down to a min value
+	 * zero for now
+	 */
+	if (aniState->noiseImmunityLevel > 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "%s: lower NI %u\n",
+		    __func__, aniState->noiseImmunityLevel-1);
+		ar5212AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+				 aniState->noiseImmunityLevel - 1);
+		return;
+	}
+}
+
+#define CLOCK_RATE 44000	/* XXX use mac_usec or similar */
+/* convert HW counter values to ms using 11g clock rate, goo9d enough
+   for 11a and Turbo */
+
+/* 
+ * Return an approximation of the time spent ``listening'' by
+ * deducting the cycles spent tx'ing and rx'ing from the total
+ * cycle count since our last call.  A return value <0 indicates
+ * an invalid/inconsistent time.
+ */
+static int32_t
+ar5212AniGetListenTime(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState;
+	uint32_t txFrameCount, rxFrameCount, cycleCount;
+	int32_t listenTime;
+
+	txFrameCount = OS_REG_READ(ah, AR_TFCNT);
+	rxFrameCount = OS_REG_READ(ah, AR_RFCNT);
+	cycleCount = OS_REG_READ(ah, AR_CCCNT);
+
+	aniState = ahp->ah_curani;
+	if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
+		/*
+		 * Cycle counter wrap (or initial call); it's not possible
+		 * to accurately calculate a value because the registers
+		 * right shift rather than wrap--so punt and return 0.
+		 */
+		listenTime = 0;
+		ahp->ah_stats.ast_ani_lzero++;
+	} else {
+		int32_t ccdelta = cycleCount - aniState->cycleCount;
+		int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
+		int32_t tfdelta = txFrameCount - aniState->txFrameCount;
+		listenTime = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE;
+	}
+	aniState->cycleCount = cycleCount;
+	aniState->txFrameCount = txFrameCount;
+	aniState->rxFrameCount = rxFrameCount;
+	return listenTime;
+}
+
+/*
+ * Update ani stats in preparation for listen time processing.
+ */
+static void
+updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const struct ar5212AniParams *params = aniState->params;
+	uint32_t phyCnt1, phyCnt2;
+	int32_t ofdmPhyErrCnt, cckPhyErrCnt;
+
+	HALASSERT(ahp->ah_hasHwPhyCounters);
+
+	/* Clear the mib counters and save them in the stats */
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
+
+	/* NB: these are not reset-on-read */
+	phyCnt1 = OS_REG_READ(ah, AR_PHYCNT1);
+	phyCnt2 = OS_REG_READ(ah, AR_PHYCNT2);
+
+	/* NB: these are spec'd to never roll-over */
+	ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
+	if (ofdmPhyErrCnt < 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "OFDM phyErrCnt %d phyCnt1 0x%x\n",
+		    ofdmPhyErrCnt, phyCnt1);
+		ofdmPhyErrCnt = AR_PHY_COUNTMAX;
+	}
+	ahp->ah_stats.ast_ani_ofdmerrs +=
+	     ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
+	aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
+
+	cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
+	if (cckPhyErrCnt < 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "CCK phyErrCnt %d phyCnt2 0x%x\n",
+		    cckPhyErrCnt, phyCnt2);
+		cckPhyErrCnt = AR_PHY_COUNTMAX;
+	}
+	ahp->ah_stats.ast_ani_cckerrs +=
+		cckPhyErrCnt - aniState->cckPhyErrCount;
+	aniState->cckPhyErrCount = cckPhyErrCnt;
+}
+
+/*
+ * Do periodic processing.  This routine is called from the
+ * driver's rx interrupt handler after processing frames.
+ */
+void
+ar5212AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
+		HAL_CHANNEL *chan)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState = ahp->ah_curani;
+	const struct ar5212AniParams *params;
+	int32_t listenTime;
+
+	ahp->ah_stats.ast_nodestats.ns_avgbrssi = stats->ns_avgbrssi;
+
+	/* XXX can aniState be null? */
+	if (aniState == AH_NULL)
+		return;
+	if (!ANI_ENA(ah))
+		return;
+
+	listenTime = ar5212AniGetListenTime(ah);
+	if (listenTime < 0) {
+		ahp->ah_stats.ast_ani_lneg++;
+		/* restart ANI period if listenTime is invalid */
+		ar5212AniRestart(ah, aniState);
+	}
+	/* XXX beware of overflow? */
+	aniState->listenTime += listenTime;
+
+	OS_MARK(ah, AH_MARK_ANI_POLL, aniState->listenTime);
+
+	params = aniState->params;
+	if (aniState->listenTime > 5*params->period) {
+		/* 
+		 * Check to see if need to lower immunity if
+		 * 5 aniPeriods have passed
+		 */
+		if (ahp->ah_hasHwPhyCounters)
+			updateMIBStats(ah, aniState);
+		if (aniState->ofdmPhyErrCount <= aniState->listenTime *
+		    params->ofdmTrigLow/1000 &&
+		    aniState->cckPhyErrCount <= aniState->listenTime *
+		    params->cckTrigLow/1000)
+			ar5212AniLowerImmunity(ah);
+		ar5212AniRestart(ah, aniState);
+	} else if (aniState->listenTime > params->period) {
+		if (ahp->ah_hasHwPhyCounters)
+			updateMIBStats(ah, aniState);
+		/* check to see if need to raise immunity */
+		if (aniState->ofdmPhyErrCount > aniState->listenTime *
+		    params->ofdmTrigHigh / 1000) {
+			HALDEBUG(ah, HAL_DEBUG_ANI,
+			    "%s: OFDM err %u listenTime %u\n", __func__,
+			    aniState->ofdmPhyErrCount, aniState->listenTime);
+			ar5212AniOfdmErrTrigger(ah);
+			ar5212AniRestart(ah, aniState);
+		} else if (aniState->cckPhyErrCount > aniState->listenTime *
+			   params->cckTrigHigh / 1000) {
+			HALDEBUG(ah, HAL_DEBUG_ANI,
+			    "%s: CCK err %u listenTime %u\n", __func__,
+			    aniState->cckPhyErrCount, aniState->listenTime);
+			ar5212AniCckErrTrigger(ah);
+			ar5212AniRestart(ah, aniState);
+		}
+	}
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_attach.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_attach.c
new file mode 100644
index 0000000..5c51af8
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_attach.c
@@ -0,0 +1,870 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_attach.c,v 1.18 2008/11/19 22:10:42 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#define AH_5212_COMMON
+#include "ar5212/ar5212.ini"
+
+static const struct ath_hal_private ar5212hal = {{
+	.ah_magic			= AR5212_MAGIC,
+	.ah_abi				= HAL_ABI_VERSION,
+	.ah_countryCode			= CTRY_DEFAULT,
+
+	.ah_getRateTable		= ar5212GetRateTable,
+	.ah_detach			= ar5212Detach,
+
+	/* Reset Functions */
+	.ah_reset			= ar5212Reset,
+	.ah_phyDisable			= ar5212PhyDisable,
+	.ah_disable			= ar5212Disable,
+	.ah_setPCUConfig		= ar5212SetPCUConfig,
+	.ah_perCalibration		= ar5212PerCalibration,
+	.ah_perCalibrationN		= ar5212PerCalibrationN,
+	.ah_resetCalValid		= ar5212ResetCalValid,
+	.ah_setTxPowerLimit		= ar5212SetTxPowerLimit,
+	.ah_getChanNoise		= ath_hal_getChanNoise,
+
+	/* Transmit functions */
+	.ah_updateTxTrigLevel		= ar5212UpdateTxTrigLevel,
+	.ah_setupTxQueue		= ar5212SetupTxQueue,
+	.ah_setTxQueueProps             = ar5212SetTxQueueProps,
+	.ah_getTxQueueProps             = ar5212GetTxQueueProps,
+	.ah_releaseTxQueue		= ar5212ReleaseTxQueue,
+	.ah_resetTxQueue		= ar5212ResetTxQueue,
+	.ah_getTxDP			= ar5212GetTxDP,
+	.ah_setTxDP			= ar5212SetTxDP,
+	.ah_numTxPending		= ar5212NumTxPending,
+	.ah_startTxDma			= ar5212StartTxDma,
+	.ah_stopTxDma			= ar5212StopTxDma,
+	.ah_setupTxDesc			= ar5212SetupTxDesc,
+	.ah_setupXTxDesc		= ar5212SetupXTxDesc,
+	.ah_fillTxDesc			= ar5212FillTxDesc,
+	.ah_procTxDesc			= ar5212ProcTxDesc,
+	.ah_getTxIntrQueue		= ar5212GetTxIntrQueue,
+	.ah_reqTxIntrDesc 		= ar5212IntrReqTxDesc,
+
+	/* RX Functions */
+	.ah_getRxDP			= ar5212GetRxDP,
+	.ah_setRxDP			= ar5212SetRxDP,
+	.ah_enableReceive		= ar5212EnableReceive,
+	.ah_stopDmaReceive		= ar5212StopDmaReceive,
+	.ah_startPcuReceive		= ar5212StartPcuReceive,
+	.ah_stopPcuReceive		= ar5212StopPcuReceive,
+	.ah_setMulticastFilter		= ar5212SetMulticastFilter,
+	.ah_setMulticastFilterIndex	= ar5212SetMulticastFilterIndex,
+	.ah_clrMulticastFilterIndex	= ar5212ClrMulticastFilterIndex,
+	.ah_getRxFilter			= ar5212GetRxFilter,
+	.ah_setRxFilter			= ar5212SetRxFilter,
+	.ah_setupRxDesc			= ar5212SetupRxDesc,
+	.ah_procRxDesc			= ar5212ProcRxDesc,
+	.ah_rxMonitor			= ar5212AniPoll,
+	.ah_procMibEvent		= ar5212ProcessMibIntr,
+
+	/* Misc Functions */
+	.ah_getCapability		= ar5212GetCapability,
+	.ah_setCapability		= ar5212SetCapability,
+	.ah_getDiagState		= ar5212GetDiagState,
+	.ah_getMacAddress		= ar5212GetMacAddress,
+	.ah_setMacAddress		= ar5212SetMacAddress,
+	.ah_getBssIdMask		= ar5212GetBssIdMask,
+	.ah_setBssIdMask		= ar5212SetBssIdMask,
+	.ah_setRegulatoryDomain		= ar5212SetRegulatoryDomain,
+	.ah_setLedState			= ar5212SetLedState,
+	.ah_writeAssocid		= ar5212WriteAssocid,
+	.ah_gpioCfgInput		= ar5212GpioCfgInput,
+	.ah_gpioCfgOutput		= ar5212GpioCfgOutput,
+	.ah_gpioGet			= ar5212GpioGet,
+	.ah_gpioSet			= ar5212GpioSet,
+	.ah_gpioSetIntr			= ar5212GpioSetIntr,
+	.ah_getTsf32			= ar5212GetTsf32,
+	.ah_getTsf64			= ar5212GetTsf64,
+	.ah_resetTsf			= ar5212ResetTsf,
+	.ah_detectCardPresent		= ar5212DetectCardPresent,
+	.ah_updateMibCounters		= ar5212UpdateMibCounters,
+	.ah_getRfGain			= ar5212GetRfgain,
+	.ah_getDefAntenna		= ar5212GetDefAntenna,
+	.ah_setDefAntenna		= ar5212SetDefAntenna,
+	.ah_getAntennaSwitch		= ar5212GetAntennaSwitch,
+	.ah_setAntennaSwitch		= ar5212SetAntennaSwitch,
+	.ah_setSifsTime			= ar5212SetSifsTime,
+	.ah_getSifsTime			= ar5212GetSifsTime,
+	.ah_setSlotTime			= ar5212SetSlotTime,
+	.ah_getSlotTime			= ar5212GetSlotTime,
+	.ah_setAckTimeout		= ar5212SetAckTimeout,
+	.ah_getAckTimeout		= ar5212GetAckTimeout,
+	.ah_setAckCTSRate		= ar5212SetAckCTSRate,
+	.ah_getAckCTSRate		= ar5212GetAckCTSRate,
+	.ah_setCTSTimeout		= ar5212SetCTSTimeout,
+	.ah_getCTSTimeout		= ar5212GetCTSTimeout,
+	.ah_setDecompMask               = ar5212SetDecompMask,
+	.ah_setCoverageClass            = ar5212SetCoverageClass,
+
+	/* Key Cache Functions */
+	.ah_getKeyCacheSize		= ar5212GetKeyCacheSize,
+	.ah_resetKeyCacheEntry		= ar5212ResetKeyCacheEntry,
+	.ah_isKeyCacheEntryValid	= ar5212IsKeyCacheEntryValid,
+	.ah_setKeyCacheEntry		= ar5212SetKeyCacheEntry,
+	.ah_setKeyCacheEntryMac		= ar5212SetKeyCacheEntryMac,
+
+	/* Power Management Functions */
+	.ah_setPowerMode		= ar5212SetPowerMode,
+	.ah_getPowerMode		= ar5212GetPowerMode,
+
+	/* Beacon Functions */
+	.ah_setBeaconTimers		= ar5212SetBeaconTimers,
+	.ah_beaconInit			= ar5212BeaconInit,
+	.ah_setStationBeaconTimers	= ar5212SetStaBeaconTimers,
+	.ah_resetStationBeaconTimers	= ar5212ResetStaBeaconTimers,
+
+	/* Interrupt Functions */
+	.ah_isInterruptPending		= ar5212IsInterruptPending,
+	.ah_getPendingInterrupts	= ar5212GetPendingInterrupts,
+	.ah_getInterrupts		= ar5212GetInterrupts,
+	.ah_setInterrupts		= ar5212SetInterrupts },
+
+	.ah_getChannelEdges		= ar5212GetChannelEdges,
+	.ah_getWirelessModes		= ar5212GetWirelessModes,
+	.ah_eepromRead			= ar5212EepromRead,
+#ifdef AH_SUPPORT_WRITE_EEPROM
+	.ah_eepromWrite			= ar5212EepromWrite,
+#endif
+	.ah_gpioCfgOutput		= ar5212GpioCfgOutput,
+	.ah_gpioCfgInput		= ar5212GpioCfgInput,
+	.ah_gpioGet			= ar5212GpioGet,
+	.ah_gpioSet			= ar5212GpioSet,
+	.ah_gpioSetIntr			= ar5212GpioSetIntr,
+	.ah_getChipPowerLimits		= ar5212GetChipPowerLimits,
+};
+
+/*
+ * Disable PLL when in L0s as well as receiver clock when in L1.
+ * This power saving option must be enabled through the Serdes.
+ *
+ * Programming the Serdes must go through the same 288 bit serial shift
+ * register as the other analog registers.  Hence the 9 writes.
+ *
+ * XXX Clean up the magic numbers.
+ */
+static void
+configurePciePowerSave(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
+
+	/* RX shut off when elecidle is asserted */
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
+                                                                                           
+	/* Shut off PLL and CLKREQ active in L1 */
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
+	OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
+                                                                                           
+	/* Load the new settings */
+	OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
+}
+
+uint32_t
+ar5212GetRadioRev(struct ath_hal *ah)
+{
+	uint32_t val;
+	int i;
+
+	/* Read Radio Chip Rev Extract */
+	OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16);
+	for (i = 0; i < 8; i++)
+		OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
+	val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
+	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
+	return ath_hal_reverseBits(val, 8);
+}
+
+static void
+ar5212AniSetup(struct ath_hal *ah)
+{
+	static const struct ar5212AniParams aniparams = {
+		.maxNoiseImmunityLevel	= 4,	/* levels 0..4 */
+		.totalSizeDesired	= { -55, -55, -55, -55, -62 },
+		.coarseHigh		= { -14, -14, -14, -14, -12 },
+		.coarseLow		= { -64, -64, -64, -64, -70 },
+		.firpwr			= { -78, -78, -78, -78, -80 },
+		.maxSpurImmunityLevel	= 2,	/* NB: depends on chip rev */
+		.cycPwrThr1		= { 2, 4, 6, 8, 10, 12, 14, 16 },
+		.maxFirstepLevel	= 2,	/* levels 0..2 */
+		.firstep		= { 0, 4, 8 },
+		.ofdmTrigHigh		= 500,
+		.ofdmTrigLow		= 200,
+		.cckTrigHigh		= 200,
+		.cckTrigLow		= 100,
+		.rssiThrHigh		= 40,
+		.rssiThrLow		= 7,
+		.period			= 100,
+	};
+	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) {
+		struct ar5212AniParams tmp;
+		OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams));
+		tmp.maxSpurImmunityLevel = 7;	/* Venice and earlier */
+		ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE);
+	} else
+		ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
+}
+
+/*
+ * Attach for an AR5212 part.
+ */
+void
+ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+	static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] =
+		{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+	struct ath_hal *ah;
+
+	ah = &ahp->ah_priv.h;
+	/* set initial values */
+	OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private));
+	ah->ah_sc = sc;
+	ah->ah_st = st;
+	ah->ah_sh = sh;
+
+	ah->ah_devid = devid;			/* NB: for alq */
+	AH_PRIVATE(ah)->ah_devid = devid;
+	AH_PRIVATE(ah)->ah_subvendorid = 0;	/* XXX */
+
+	AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
+	AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX;	/* no scaling */
+
+	ahp->ah_antControl = HAL_ANT_VARIABLE;
+	ahp->ah_diversity = AH_TRUE;
+	ahp->ah_bIQCalibration = AH_FALSE;
+	/*
+	 * Enable MIC handling.
+	 */
+	ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
+	ahp->ah_rssiThr = INIT_RSSI_THR;
+	ahp->ah_tpcEnabled = AH_FALSE;		/* disabled by default */
+	ahp->ah_phyPowerOn = AH_FALSE;
+	ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK)
+		       | SM(MAX_RATE_POWER, AR_TPC_CTS)
+		       | SM(MAX_RATE_POWER, AR_TPC_CHIRP);
+	ahp->ah_beaconInterval = 100;		/* XXX [20..1000] */
+	ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */
+	ahp->ah_slottime = (u_int) -1;
+	ahp->ah_acktimeout = (u_int) -1;
+	ahp->ah_ctstimeout = (u_int) -1;
+	ahp->ah_sifstime = (u_int) -1;
+	OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
+#undef N
+}
+
+/*
+ * Validate MAC version and revision. 
+ */
+static HAL_BOOL
+ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
+{
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+	static const struct {
+		uint8_t	version;
+		uint8_t	revMin, revMax;
+	} macs[] = {
+	    { AR_SREV_VERSION_VENICE,
+	      AR_SREV_D2PLUS,		AR_SREV_REVISION_MAX },
+	    { AR_SREV_VERSION_GRIFFIN,
+	      AR_SREV_D2PLUS,		AR_SREV_REVISION_MAX },
+	    { AR_SREV_5413,
+	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
+	    { AR_SREV_5424,
+	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
+	    { AR_SREV_2425,
+	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
+	    { AR_SREV_2417,
+	      AR_SREV_REVISION_MIN,	AR_SREV_REVISION_MAX },
+	};
+	int i;
+
+	for (i = 0; i < N(macs); i++)
+		if (macs[i].version == macVersion &&
+		    macs[i].revMin <= macRev && macRev <= macs[i].revMax)
+			return AH_TRUE;
+	return AH_FALSE;
+#undef N
+}
+       
+/*
+ * Attach for an AR5212 part.
+ */
+static struct ath_hal *
+ar5212Attach(uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+#define	AH_EEPROM_PROTECT(ah) \
+	(IS_PCIE(ah) ? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
+	struct ath_hal_5212 *ahp;
+	struct ath_hal *ah;
+	struct ath_hal_rf *rf;
+	uint32_t val;
+	uint16_t eeval;
+	HAL_STATUS ecode;
+
+	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
+	    __func__, sc, (void*) st, (void*) sh);
+
+	/* NB: memory is returned zero'd */
+	ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
+	if (ahp == AH_NULL) {
+		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+		    "%s: cannot allocate memory for state block\n", __func__);
+		*status = HAL_ENOMEM;
+		return AH_NULL;
+	}
+	ar5212InitState(ahp, devid, sc, st, sh, status);
+	ah = &ahp->ah_priv.h;
+
+	if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
+		    __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+	/* Read Revisions from Chips before taking out of reset */
+	val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
+	AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
+	AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
+
+	if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: Mac Chip Rev 0x%02x.%x not supported\n" ,
+		    __func__, AH_PRIVATE(ah)->ah_macVersion,
+		    AH_PRIVATE(ah)->ah_macRev);
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+	}
+
+	/* setup common ini data; rf backends handle remainder */
+	HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
+	HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
+
+	if (!ar5212ChipReset(ah, AH_NULL)) {	/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
+
+	if (IS_PCIE(ah)) {
+		/* XXX: build flag to disable this? */
+		configurePciePowerSave(ah);
+	}
+
+	if (!ar5212ChipTest(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
+		    __func__);
+		ecode = HAL_ESELFTEST;
+		goto bad;
+	}
+
+	/* Enable PCI core retry fix in software for Hainan and up */
+	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE)
+		OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN);
+
+	/*
+	 * Set correct Baseband to analog shift
+	 * setting to access analog chips.
+	 */
+	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+	/* Read Radio Chip Rev Extract */
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
+
+	rf = ath_hal_rfprobe(ah, &ecode);
+	if (rf == AH_NULL)
+		goto bad;
+
+	/* NB: silently accept anything in release code per Atheros */
+	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
+	case AR_RAD5111_SREV_MAJOR:
+	case AR_RAD5112_SREV_MAJOR:
+	case AR_RAD2112_SREV_MAJOR:
+	case AR_RAD2111_SREV_MAJOR:
+	case AR_RAD2413_SREV_MAJOR:
+	case AR_RAD5413_SREV_MAJOR:
+	case AR_RAD5424_SREV_MAJOR:
+		break;
+	default:
+		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
+			/*
+			 * When RF_Silent is used, the
+			 * analog chip is reset.  So when the system boots
+			 * up with the radio switch off we cannot determine
+			 * the RF chip rev.  To workaround this check the
+			 * mac+phy revs and if Hainan, set the radio rev
+			 * to Derby.
+			 */
+			if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
+			    AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN &&
+			    AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) {
+				AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN;
+				break;
+			}
+			if (IS_2413(ah)) {		/* Griffin */
+				AH_PRIVATE(ah)->ah_analog5GhzRev =
+				    AR_RAD2413_SREV_MAJOR | 0x1;
+				break;
+			}
+			if (IS_5413(ah)) {		/* Eagle */	
+				AH_PRIVATE(ah)->ah_analog5GhzRev =
+				    AR_RAD5413_SREV_MAJOR | 0x2;
+				break;
+			}
+			if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */	
+				AH_PRIVATE(ah)->ah_analog5GhzRev =
+				    AR_RAD5424_SREV_MAJOR | 0x2;
+				break;
+			}
+		}
+#ifdef AH_DEBUG
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
+		    "this driver\n",
+		    __func__, AH_PRIVATE(ah)->ah_analog5GhzRev);
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+#endif
+	}
+	if (IS_RAD5112_REV1(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: 5112 Rev 1 is not supported by this "
+		    "driver (analog5GhzRev 0x%x)\n", __func__,
+		    AH_PRIVATE(ah)->ah_analog5GhzRev);
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+	}
+
+	val = OS_REG_READ(ah, AR_PCICFG);
+	val = MS(val, AR_PCICFG_EEPROM_SIZE);
+	if (val == 0) {
+		if (!IS_PCIE(ah)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: unsupported EEPROM size %u (0x%x) found\n",
+			    __func__, val, val);
+			ecode = HAL_EESIZE;
+			goto bad;
+		}
+		/* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */
+	} else if (val != AR_PCICFG_EEPROM_SIZE_16K) {
+		if (AR_PCICFG_EEPROM_SIZE_FAILED == val) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: unsupported EEPROM size %u (0x%x) found\n",
+			    __func__, val, val);
+			ecode = HAL_EESIZE;
+			goto bad;
+		}
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: EEPROM size = %d. Must be %d (16k).\n",
+		    __func__, val, AR_PCICFG_EEPROM_SIZE_16K);
+		ecode = HAL_EESIZE;
+		goto bad;
+	}
+	ecode = ath_hal_legacyEepromAttach(ah);
+	if (ecode != HAL_OK) {
+		goto bad;
+	}
+	ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON);
+
+	/*
+	 * If Bmode and AR5212, verify 2.4 analog exists
+	 */
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
+	    (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
+		/*
+		 * Set correct Baseband to analog shift
+		 * setting to access analog chips.
+		 */
+		OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
+		OS_DELAY(2000);
+		AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
+
+		/* Set baseband for 5GHz chip */
+		OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+		OS_DELAY(2000);
+		if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: 2G Radio Chip Rev 0x%02X is not "
+			    "supported by this driver\n", __func__,
+			    AH_PRIVATE(ah)->ah_analog2GhzRev);
+			ecode = HAL_ENOTSUPP;
+			goto bad;
+		}
+	}
+
+	ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot read regulatory domain from EEPROM\n",
+		    __func__);
+		goto bad;
+        }
+	AH_PRIVATE(ah)->ah_currentRD = eeval;
+	/* XXX record serial number */
+
+	/*
+	 * Got everything we need now to setup the capabilities.
+	 */
+	if (!ar5212FillCapabilityInfo(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: failed ar5212FillCapabilityInfo\n", __func__);
+		ecode = HAL_EEREAD;
+		goto bad;
+	}
+
+	if (!rf->attach(ah, &ecode)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
+		    __func__, ecode);
+		goto bad;
+	}
+	/*
+	 * Set noise floor adjust method; we arrange a
+	 * direct call instead of thunking.
+	 */
+	AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
+
+	/* Initialize gain ladder thermal calibration structure */
+	ar5212InitializeGainValues(ah);
+
+	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error getting mac address from EEPROM\n", __func__);
+		goto bad;
+        }
+
+	ar5212AniSetup(ah);
+	/* Setup of Radar/AR structures happens in ath_hal_initchannels*/
+	ar5212InitNfCalHistBuffer(ah);
+
+	/* XXX EAR stuff goes here */
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
+
+	return ah;
+
+bad:
+	if (ahp)
+		ar5212Detach((struct ath_hal *) ahp);
+	if (status)
+		*status = ecode;
+	return AH_NULL;
+#undef AH_EEPROM_PROTECT
+}
+
+void
+ar5212Detach(struct ath_hal *ah)
+{
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
+
+	HALASSERT(ah != AH_NULL);
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	ar5212AniDetach(ah);
+	ar5212RfDetach(ah);
+	ar5212Disable(ah);
+	ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
+
+	ath_hal_eepromDetach(ah);
+	ath_hal_free(ah);
+}
+
+HAL_BOOL
+ar5212ChipTest(struct ath_hal *ah)
+{
+	uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };
+	uint32_t regHold[2];
+	uint32_t patternData[4] =
+	    { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
+	int i, j;
+
+	/* Test PHY & MAC registers */
+	for (i = 0; i < 2; i++) {
+		uint32_t addr = regAddr[i];
+		uint32_t wrData, rdData;
+
+		regHold[i] = OS_REG_READ(ah, addr);
+		for (j = 0; j < 0x100; j++) {
+			wrData = (j << 16) | j;
+			OS_REG_WRITE(ah, addr, wrData);
+			rdData = OS_REG_READ(ah, addr);
+			if (rdData != wrData) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+				__func__, addr, wrData, rdData);
+				return AH_FALSE;
+			}
+		}
+		for (j = 0; j < 4; j++) {
+			wrData = patternData[j];
+			OS_REG_WRITE(ah, addr, wrData);
+			rdData = OS_REG_READ(ah, addr);
+			if (wrData != rdData) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+					__func__, addr, wrData, rdData);
+				return AH_FALSE;
+			}
+		}
+		OS_REG_WRITE(ah, regAddr[i], regHold[i]);
+	}
+	OS_DELAY(100);
+	return AH_TRUE;
+}
+
+/*
+ * Store the channel edges for the requested operational mode
+ */
+HAL_BOOL
+ar5212GetChannelEdges(struct ath_hal *ah,
+	uint16_t flags, uint16_t *low, uint16_t *high)
+{
+	if (flags & CHANNEL_5GHZ) {
+		*low = 4915;
+		*high = 6100;
+		return AH_TRUE;
+	}
+	if ((flags & CHANNEL_2GHZ) &&
+	    (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) ||
+	     ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) {
+		*low = 2312;
+		*high = 2732;
+		return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Fill all software cached or static hardware state information.
+ * Return failure if capabilities are to come from EEPROM and
+ * cannot be read.
+ */
+HAL_BOOL
+ar5212FillCapabilityInfo(struct ath_hal *ah)
+{
+#define	AR_KEYTABLE_SIZE	128
+#define	IS_GRIFFIN_LITE(ah) \
+    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \
+     AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE)
+#define	IS_COBRA(ah) \
+    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA)
+#define IS_2112(ah) \
+	((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR)
+
+	struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
+	HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
+	uint16_t capField, val;
+
+	/* Read the capability EEPROM location */
+	if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: unable to read caps from eeprom\n", __func__);
+		return AH_FALSE;
+	}
+	if (IS_2112(ah))
+		ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE);
+	if (capField == 0 && IS_GRIFFIN_LITE(ah)) {
+		/*
+		 * For griffin-lite cards with unprogrammed capabilities.
+		 */
+		ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
+		ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
+		ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
+		ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
+		HALDEBUG(ah, HAL_DEBUG_ATTACH,
+		    "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n",
+		    __func__, capField);
+	}
+
+	/* Modify reg domain on newer cards that need to work with older sw */
+	if (ahpriv->ah_opmode != HAL_M_HOSTAP &&
+	    ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
+		if (ahpriv->ah_currentRD == 0x64 ||
+		    ahpriv->ah_currentRD == 0x65)
+			ahpriv->ah_currentRD += 5;
+		else if (ahpriv->ah_currentRD == 0x41)
+			ahpriv->ah_currentRD = 0x43;
+		HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n",
+		    __func__, ahpriv->ah_currentRD);
+	}
+
+	if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 ||
+	    AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) {
+		HALDEBUG(ah, HAL_DEBUG_ATTACH,
+		    "%s: enable Bmode and disable turbo for Swan/Nala\n",
+		    __func__);
+		ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE);
+		ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE);
+		ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE);
+		ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE);
+		ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE);
+	}
+
+	/* Construct wireless mode from EEPROM */
+	pCap->halWirelessModes = 0;
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
+		pCap->halWirelessModes |= HAL_MODE_11A;
+		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
+			pCap->halWirelessModes |= HAL_MODE_TURBO;
+	}
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
+		pCap->halWirelessModes |= HAL_MODE_11B;
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
+	    ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
+		pCap->halWirelessModes |= HAL_MODE_11G;
+		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
+			pCap->halWirelessModes |= HAL_MODE_108G;
+	}
+
+	pCap->halLow2GhzChan = 2312;
+	/* XXX 2417 too? */
+	if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) ||  IS_2417(ah))
+		pCap->halHigh2GhzChan = 2500;
+	else
+		pCap->halHigh2GhzChan = 2732;
+
+	pCap->halLow5GhzChan = 4915;
+	pCap->halHigh5GhzChan = 6100;
+
+	pCap->halCipherCkipSupport = AH_FALSE;
+	pCap->halCipherTkipSupport = AH_TRUE;
+	pCap->halCipherAesCcmSupport =
+		(ath_hal_eepromGetFlag(ah, AR_EEP_AES) &&
+		 ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) ||
+		  ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) &&
+		   (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU))));
+
+	pCap->halMicCkipSupport    = AH_FALSE;
+	pCap->halMicTkipSupport    = AH_TRUE;
+	pCap->halMicAesCcmSupport  = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
+	/*
+	 * Starting with Griffin TX+RX mic keys can be combined
+	 * in one key cache slot.
+	 */
+	if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN)
+		pCap->halTkipMicTxRxKeySupport = AH_TRUE;
+	else
+		pCap->halTkipMicTxRxKeySupport = AH_FALSE;
+	pCap->halChanSpreadSupport = AH_TRUE;
+	pCap->halSleepAfterBeaconBroken = AH_TRUE;
+
+	if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) {
+		pCap->halCompressSupport   =
+			ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) &&
+			(pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
+		pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST);
+		pCap->halFastFramesSupport =
+			ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) &&
+			(pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0;
+		pCap->halChapTuningSupport = AH_TRUE;
+		pCap->halTurboPrimeSupport = AH_TRUE;
+	}
+	pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
+
+	pCap->halPSPollBroken = AH_TRUE;	/* XXX fixed in later revs? */
+	pCap->halVEOLSupport = AH_TRUE;
+	pCap->halBssIdMaskSupport = AH_TRUE;
+	pCap->halMcastKeySrchSupport = AH_TRUE;
+	if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE &&
+	     ahpriv->ah_macRev == 8) ||
+	    ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE)
+		pCap->halTsfAddSupport = AH_TRUE;
+
+	if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
+		pCap->halTotalQueues = val;
+	else
+		pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
+
+	if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
+		pCap->halKeyCacheSize = val;
+	else
+		pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
+
+	pCap->halChanHalfRate = AH_TRUE;
+	pCap->halChanQuarterRate = AH_TRUE;
+
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
+	    ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
+		/* NB: enabled by default */
+		ahpriv->ah_rfkillEnabled = AH_TRUE;
+		pCap->halRfSilentSupport = AH_TRUE;
+	}
+
+	/* NB: this is a guess, noone seems to know the answer */
+	ahpriv->ah_rxornIsFatal =
+	    (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
+
+	/* h/w phy counters first appeared in Hainan */
+	pCap->halHwPhyCounterSupport =
+	    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
+	     AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) ||
+	    AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE;
+
+	pCap->halTstampPrecision = 15;
+
+	return AH_TRUE;
+#undef IS_COBRA
+#undef IS_GRIFFIN_LITE
+#undef AR_KEYTABLE_SIZE
+}
+
+static const char*
+ar5212Probe(uint16_t vendorid, uint16_t devid)
+{
+	if (vendorid == ATHEROS_VENDOR_ID ||
+	    vendorid == ATHEROS_3COM_VENDOR_ID ||
+	    vendorid == ATHEROS_3COM2_VENDOR_ID) {
+		switch (devid) {
+		case AR5212_FPGA:
+			return "Atheros 5212 (FPGA)";
+		case AR5212_DEVID:
+		case AR5212_DEVID_IBM:
+		case AR5212_DEFAULT:
+			return "Atheros 5212";
+		case AR5212_AR2413:
+			return "Atheros 2413";
+		case AR5212_AR2417:
+			return "Atheros 2417";
+		case AR5212_AR5413:
+			return "Atheros 5413";
+		case AR5212_AR5424:
+			return "Atheros 5424/2424";
+		}
+	}
+	return AH_NULL;
+}
+AH_CHIP(AR5212, ar5212Probe, ar5212Attach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_beacon.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_beacon.c
new file mode 100644
index 0000000..2dbc0cb
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_beacon.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_beacon.c,v 1.6 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212desc.h"
+
+/*
+ * Initialize all of the hardware registers used to
+ * send beacons.  Note that for station operation the
+ * driver calls ar5212SetStaBeaconTimers instead.
+ */
+void
+ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
+{
+
+	OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
+	OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
+	OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
+	OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
+	/*
+	 * Set the Beacon register after setting all timers.
+	 */
+	if (bt->bt_intval & AR_BEACON_RESET_TSF) {
+		/*
+		 * When resetting the TSF,
+		 * write twice to the corresponding register; each
+		 * write to the RESET_TSF bit toggles the internal
+		 * signal to cause a reset of the TSF - but if the signal
+		 * is left high, it will reset the TSF on the next
+		 * chip reset also! writing the bit an even number
+		 * of times fixes this issue
+		 */
+		OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
+	}
+	OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
+}
+
+/*
+ * Old api for setting up beacon timer registers when
+ * operating in !station mode.  Note the fixed constants
+ * adjusting the DBA and SWBA timers and the fixed ATIM
+ * window.
+ */
+void
+ar5212BeaconInit(struct ath_hal *ah,
+	uint32_t next_beacon, uint32_t beacon_period)
+{
+	HAL_BEACON_TIMERS bt;
+
+	bt.bt_nexttbtt = next_beacon;
+	/* 
+	 * TIMER1: in AP/adhoc mode this controls the DMA beacon
+	 * alert timer; otherwise it controls the next wakeup time.
+	 * TIMER2: in AP mode, it controls the SBA beacon alert
+	 * interrupt; otherwise it sets the start of the next CFP.
+	 */
+	switch (AH_PRIVATE(ah)->ah_opmode) {
+	case HAL_M_STA:
+	case HAL_M_MONITOR:
+		bt.bt_nextdba = 0xffff;
+		bt.bt_nextswba = 0x7ffff;
+		break;
+	case HAL_M_HOSTAP:
+	case HAL_M_IBSS:
+		bt.bt_nextdba = (next_beacon -
+			ath_hal_dma_beacon_response_time) << 3;	/* 1/8 TU */
+		bt.bt_nextswba = (next_beacon -
+			ath_hal_sw_beacon_response_time) << 3;	/* 1/8 TU */
+		break;
+	}
+	/*
+	 * Set the ATIM window 
+	 * Our hardware does not support an ATIM window of 0
+	 * (beacons will not work).  If the ATIM windows is 0,
+	 * force it to 1.
+	 */
+	bt.bt_nextatim = next_beacon + 1;
+	bt.bt_intval = beacon_period &
+		(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
+	ar5212SetBeaconTimers(ah, &bt);
+}
+
+void
+ar5212ResetStaBeaconTimers(struct ath_hal *ah)
+{
+	uint32_t val;
+
+	OS_REG_WRITE(ah, AR_TIMER0, 0);		/* no beacons */
+	val = OS_REG_READ(ah, AR_STA_ID1);
+	val |= AR_STA_ID1_PWR_SAV;		/* XXX */
+	/* tell the h/w that the associated AP is not PCF capable */
+	OS_REG_WRITE(ah, AR_STA_ID1,
+		val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
+	OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
+}
+
+/*
+ * Set all the beacon related bits on the h/w for stations
+ * i.e. initializes the corresponding h/w timers;
+ * also tells the h/w whether to anticipate PCF beacons
+ */
+void
+ar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
+
+	HALASSERT(bs->bs_intval != 0);
+	/* if the AP will do PCF */
+	if (bs->bs_cfpmaxduration != 0) {
+		/* tell the h/w that the associated AP is PCF capable */
+		OS_REG_WRITE(ah, AR_STA_ID1,
+			OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
+
+		/* set CFP_PERIOD(1.024ms) register */
+		OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
+
+		/* set CFP_DUR(1.024ms) register to max cfp duration */
+		OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
+
+		/* set TIMER2(128us) to anticipated time of next CFP */
+		OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
+	} else {
+		/* tell the h/w that the associated AP is not PCF capable */
+		OS_REG_WRITE(ah, AR_STA_ID1,
+			OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
+	}
+
+	/*
+	 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
+	 */
+	OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
+
+	/*
+	 * Start the beacon timers by setting the BEACON register
+	 * to the beacon interval; also write the tim offset which
+	 * we should know by now.  The code, in ar5211WriteAssocid,
+	 * also sets the tim offset once the AID is known which can
+	 * be left as such for now.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON, 
+		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
+		| SM(bs->bs_intval, AR_BEACON_PERIOD)
+		| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
+	);
+
+	/*
+	 * Configure the BMISS interrupt.  Note that we
+	 * assume the caller blocks interrupts while enabling
+	 * the threshold.
+	 */
+	HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
+	ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
+			| SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
+	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
+
+	/*
+	 * Program the sleep registers to correlate with the beacon setup.
+	 */
+
+	/*
+	 * Oahu beacons timers on the station were used for power
+	 * save operation (waking up in anticipation of a beacon)
+	 * and any CFP function; Venice does sleep/power-save timers
+	 * differently - so this is the right place to set them up;
+	 * don't think the beacon timers are used by venice sta hw
+	 * for any useful purpose anymore
+	 * Setup venice's sleep related timers
+	 * Current implementation assumes sw processing of beacons -
+	 *   assuming an interrupt is generated every beacon which
+	 *   causes the hardware to become awake until the sw tells
+	 *   it to go to sleep again; beacon timeout is to allow for
+	 *   beacon jitter; cab timeout is max time to wait for cab
+	 *   after seeing the last DTIM or MORE CAB bit
+	 */
+#define CAB_TIMEOUT_VAL     10 /* in TU */
+#define BEACON_TIMEOUT_VAL  10 /* in TU */
+#define SLEEP_SLOP          3  /* in TU */
+
+	/*
+	 * For max powersave mode we may want to sleep for longer than a
+	 * beacon period and not want to receive all beacons; modify the
+	 * timers accordingly; make sure to align the next TIM to the
+	 * next DTIM if we decide to wake for DTIMs only
+	 */
+	beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
+	HALASSERT(beaconintval != 0);
+	if (bs->bs_sleepduration > beaconintval) {
+		HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
+				bs->bs_sleepduration);
+		beaconintval = bs->bs_sleepduration;
+	}
+	dtimperiod = bs->bs_dtimperiod;
+	if (bs->bs_sleepduration > dtimperiod) {
+		HALASSERT(dtimperiod == 0 ||
+			roundup(bs->bs_sleepduration, dtimperiod) ==
+				bs->bs_sleepduration);
+		dtimperiod = bs->bs_sleepduration;
+	}
+	HALASSERT(beaconintval <= dtimperiod);
+	if (beaconintval == dtimperiod)
+		nextTbtt = bs->bs_nextdtim;
+	else
+		nextTbtt = bs->bs_nexttbtt;
+	nextdtim = bs->bs_nextdtim;
+
+	OS_REG_WRITE(ah, AR_SLEEP1,
+		  SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM)
+		| SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT)
+		| AR_SLEEP1_ASSUME_DTIM
+		| AR_SLEEP1_ENH_SLEEP_ENA
+	);
+	OS_REG_WRITE(ah, AR_SLEEP2,
+		  SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM)
+		| SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT)
+	);
+	OS_REG_WRITE(ah, AR_SLEEP3,
+		  SM(beaconintval, AR_SLEEP3_TIM_PERIOD)
+		| SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD)
+	);
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
+	    __func__, bs->bs_nextdtim);
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
+	    __func__, nextTbtt);
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
+	    __func__, beaconintval);
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
+	    __func__, dtimperiod);
+#undef CAB_TIMEOUT_VAL
+#undef BEACON_TIMEOUT_VAL
+#undef SLEEP_SLOP
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_eeprom.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_eeprom.c
new file mode 100644
index 0000000..d2999fd
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_eeprom.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_eeprom.c,v 1.6 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+#ifdef AH_DEBUG
+#include "ah_desc.h"			/* NB: for HAL_PHYERR* */
+#endif
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+/*
+ * Read 16 bits of data from offset into *data
+ */
+HAL_BOOL
+ar5212EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
+{
+	OS_REG_WRITE(ah, AR_EEPROM_ADDR, off);
+	OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ);
+
+	if (!ath_hal_wait(ah, AR_EEPROM_STS,
+	    AR_EEPROM_STS_READ_COMPLETE | AR_EEPROM_STS_READ_ERROR,
+	    AR_EEPROM_STS_READ_COMPLETE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n",
+		    __func__, off);
+		return AH_FALSE;
+	}
+	*data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
+	return AH_TRUE;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_gpio.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_gpio.c
new file mode 100644
index 0000000..eb0022f
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_gpio.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_gpio.c,v 1.3 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+#ifdef AH_DEBUG
+#include "ah_desc.h"			/* NB: for HAL_PHYERR* */
+#endif
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#define	AR_NUM_GPIO	6		/* 6 GPIO pins */
+#define	AR_GPIOD_MASK	0x0000002F	/* GPIO data reg r/w mask */
+
+/*
+ * Configure GPIO Output lines
+ */
+HAL_BOOL
+ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+{
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	/*
+	 * NB: AR_GPIOCR_CR_A(pin) is all 1's so there's no need
+	 *     to clear the field before or'ing in the new value.
+	 */
+	OS_REG_WRITE(ah, AR_GPIOCR, 
+		  OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio));
+
+	return AH_TRUE;
+}
+
+/*
+ * Configure GPIO Input lines
+ */
+HAL_BOOL
+ar5212GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
+{
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	OS_REG_WRITE(ah, AR_GPIOCR, 
+		  (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
+		| AR_GPIOCR_CR_N(gpio));
+
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - set output lines
+ */
+HAL_BOOL
+ar5212GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
+{
+	uint32_t reg;
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	reg =  OS_REG_READ(ah, AR_GPIODO);
+	reg &= ~(1 << gpio);
+	reg |= (val&1) << gpio;
+
+	OS_REG_WRITE(ah, AR_GPIODO, reg);
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - get input lines
+ */
+uint32_t
+ar5212GpioGet(struct ath_hal *ah, uint32_t gpio)
+{
+	if (gpio < AR_NUM_GPIO) {
+		uint32_t val = OS_REG_READ(ah, AR_GPIODI);
+		val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
+		return val;
+	} else  {
+		return 0xffffffff;
+	}
+}
+
+/*
+ * Set the GPIO Interrupt
+ */
+void
+ar5212GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
+{
+	uint32_t val;
+
+	/* XXX bounds check gpio */
+	val = OS_REG_READ(ah, AR_GPIOCR);
+	val &= ~(AR_GPIOCR_CR_A(gpio) |
+		 AR_GPIOCR_INT_MASK | AR_GPIOCR_INT_ENA | AR_GPIOCR_INT_SEL);
+	val |= AR_GPIOCR_CR_N(gpio) | AR_GPIOCR_INT(gpio) | AR_GPIOCR_INT_ENA;
+	if (ilevel)
+		val |= AR_GPIOCR_INT_SELH;	/* interrupt on pin high */
+	else
+		val |= AR_GPIOCR_INT_SELL;	/* interrupt on pin low */
+
+	/* Don't need to change anything for low level interrupt. */
+	OS_REG_WRITE(ah, AR_GPIOCR, val);
+
+	/* Change the interrupt mask. */
+	(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_interrupts.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_interrupts.c
new file mode 100644
index 0000000..5d0b39c
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_interrupts.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_interrupts.c,v 1.6 2008/11/27 22:30:00 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+
+/*
+ * Checks to see if an interrupt is pending on our NIC
+ *
+ * Returns: TRUE    if an interrupt is pending
+ *          FALSE   if not
+ */
+HAL_BOOL
+ar5212IsInterruptPending(struct ath_hal *ah)
+{
+	/* 
+	 * Some platforms trigger our ISR before applying power to
+	 * the card, so make sure the INTPEND is really 1, not 0xffffffff.
+	 */
+	return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE);
+}
+
+/*
+ * Reads the Interrupt Status Register value from the NIC, thus deasserting
+ * the interrupt line, and returns both the masked and unmasked mapped ISR
+ * values.  The value returned is mapped to abstract the hw-specific bit
+ * locations in the Interrupt Status Register.
+ *
+ * Returns: A hardware-abstracted bitmap of all non-masked-out
+ *          interrupts pending, as well as an unmasked value
+ */
+HAL_BOOL
+ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
+{
+	uint32_t isr, isr0, isr1;
+	uint32_t mask2=0;
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	isr = OS_REG_READ(ah, AR_ISR);
+	if (isr & AR_ISR_BCNMISC) {
+		uint32_t isr2;
+		isr2 = OS_REG_READ(ah, AR_ISR_S2);
+		if (isr2 & AR_ISR_S2_TIM)
+			mask2 |= HAL_INT_TIM;
+		if (isr2 & AR_ISR_S2_DTIM)
+			mask2 |= HAL_INT_DTIM;
+		if (isr2 & AR_ISR_S2_DTIMSYNC)
+			mask2 |= HAL_INT_DTIMSYNC;
+		if (isr2 & (AR_ISR_S2_CABEND ))
+			mask2 |= HAL_INT_CABEND;
+	}
+	isr = OS_REG_READ(ah, AR_ISR_RAC);
+	if (isr == 0xffffffff) {
+		*masked = 0;
+		return AH_FALSE;;
+	}
+
+	*masked = isr & HAL_INT_COMMON;
+
+	if (isr & AR_ISR_HIUERR)
+		*masked |= HAL_INT_FATAL;
+	if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
+		*masked |= HAL_INT_RX;
+	if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
+		*masked |= HAL_INT_TX;
+		isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
+		ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK);
+		ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC);
+		isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
+		ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
+		ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
+	}
+
+	/*
+	 * Receive overrun is usually non-fatal on Oahu/Spirit.
+	 * BUT on some parts rx could fail and the chip must be reset.
+	 * So we force a hardware reset in all cases.
+	 */
+	if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: receive FIFO overrun interrupt\n", __func__);
+		*masked |= HAL_INT_FATAL;
+	}
+	*masked |= mask2;
+
+	/*
+	 * On fatal errors collect ISR state for debugging.
+	 */
+	if (*masked & HAL_INT_FATAL) {
+		AH_PRIVATE(ah)->ah_fatalState[0] = isr;
+		AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
+		AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
+		AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
+		AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);
+		AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n",
+		    __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]);
+	}
+	return AH_TRUE;
+}
+
+HAL_INT
+ar5212GetInterrupts(struct ath_hal *ah)
+{
+	return AH5212(ah)->ah_maskReg;
+}
+
+/*
+ * Atomically enables NIC interrupts.  Interrupts are passed in
+ * via the enumerated bitmask in ints.
+ */
+HAL_INT
+ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	uint32_t omask = ahp->ah_maskReg;
+	uint32_t mask,mask2;
+
+	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
+	    __func__, omask, ints);
+
+	if (omask & HAL_INT_GLOBAL) {
+		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
+		OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+		(void) OS_REG_READ(ah, AR_IER);   /* flush write to HW */
+	}
+
+	mask = ints & HAL_INT_COMMON;
+	mask2 = 0;
+	if (ints & HAL_INT_TX) {
+		if (ahp->ah_txOkInterruptMask)
+			mask |= AR_IMR_TXOK;
+		if (ahp->ah_txErrInterruptMask)
+			mask |= AR_IMR_TXERR;
+		if (ahp->ah_txDescInterruptMask)
+			mask |= AR_IMR_TXDESC;
+		if (ahp->ah_txEolInterruptMask)
+			mask |= AR_IMR_TXEOL;
+	}
+	if (ints & HAL_INT_RX)
+		mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
+	if (ints & (HAL_INT_BMISC)) {
+		mask |= AR_IMR_BCNMISC;
+		if (ints & HAL_INT_TIM)
+			mask2 |= AR_IMR_S2_TIM;
+		if (ints & HAL_INT_DTIM)
+			mask2 |= AR_IMR_S2_DTIM;
+		if (ints & HAL_INT_DTIMSYNC)
+			mask2 |= AR_IMR_S2_DTIMSYNC;
+		if (ints & HAL_INT_CABEND)
+			mask2 |= (AR_IMR_S2_CABEND );
+	}
+	if (ints & HAL_INT_FATAL) {
+		/*
+		 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
+		 *     so enabling HIUERR enables delivery.
+		 */
+		mask |= AR_IMR_HIUERR;
+	}
+
+	/* Write the new IMR and store off our SW copy. */
+	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
+	OS_REG_WRITE(ah, AR_IMR, mask);
+	OS_REG_WRITE(ah, AR_IMR_S2, 
+				 (OS_REG_READ(ah, AR_IMR_S2) & 
+				  ~(AR_IMR_S2_TIM |
+					AR_IMR_S2_DTIM |
+					AR_IMR_S2_DTIMSYNC |
+					AR_IMR_S2_CABEND |
+					AR_IMR_S2_CABTO  |
+					AR_IMR_S2_TSFOOR ) ) 
+				 | mask2);
+	ahp->ah_maskReg = ints;
+
+	/* Re-enable interrupts if they were enabled before. */
+	if (ints & HAL_INT_GLOBAL) {
+		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
+		OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+	}
+
+
+	return omask;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_keycache.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_keycache.c
new file mode 100644
index 0000000..a1f2dbb
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_keycache.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_keycache.c,v 1.4 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212desc.h"
+
+/*
+ * Note: The key cache hardware requires that each double-word
+ * pair be written in even/odd order (since the destination is
+ * a 64-bit register).  Don't reorder the writes in this code
+ * w/o considering this!
+ */
+#define	KEY_XOR			0xaa
+
+#define	IS_MIC_ENABLED(ah) \
+	(AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
+
+/*
+ * Return the size of the hardware key cache.
+ */
+uint32_t
+ar5212GetKeyCacheSize(struct ath_hal *ah)
+{
+	return AH_PRIVATE(ah)->ah_caps.halKeyCacheSize;
+}
+
+/*
+ * Return true if the specific key cache entry is valid.
+ */
+HAL_BOOL
+ar5212IsKeyCacheEntryValid(struct ath_hal *ah, uint16_t entry)
+{
+	if (entry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
+		uint32_t val = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
+		if (val & AR_KEYTABLE_VALID)
+			return AH_TRUE;
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Clear the specified key cache entry and any associated MIC entry.
+ */
+HAL_BOOL
+ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)
+{
+	uint32_t keyType;
+
+	if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
+		    __func__, entry);
+		return AH_FALSE;
+	}
+	keyType = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
+
+	/* XXX why not clear key type/valid bit first? */
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
+	OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
+	OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
+	OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
+	OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
+	if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
+		uint16_t micentry = entry+64;	/* MIC goes at slot+64 */
+
+		HALASSERT(micentry < AH_PRIVATE(ah)->ah_caps.halKeyCacheSize);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
+		/* NB: key type and MAC are known to be ok */
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Sets the mac part of the specified key cache entry (and any
+ * associated MIC entry) and mark them valid.
+ */
+HAL_BOOL
+ar5212SetKeyCacheEntryMac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
+{
+	uint32_t macHi, macLo;
+
+	if (entry >= AH_PRIVATE(ah)->ah_caps.halKeyCacheSize) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
+		    __func__, entry);
+		return AH_FALSE;
+	}
+	/*
+	 * Set MAC address -- shifted right by 1.  MacLo is
+	 * the 4 MSBs, and MacHi is the 2 LSBs.
+	 */
+	if (mac != AH_NULL) {
+		macHi = (mac[5] << 8) | mac[4];
+		macLo = (mac[3] << 24)| (mac[2] << 16)
+		      | (mac[1] << 8) | mac[0];
+		macLo >>= 1;
+		macLo |= (macHi & 1) << 31;	/* carry */
+		macHi >>= 1;
+	} else {
+		macLo = macHi = 0;
+	}
+	OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
+	OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
+	return AH_TRUE;
+}
+
+/*
+ * Sets the contents of the specified key cache entry
+ * and any associated MIC entry.
+ */
+HAL_BOOL
+ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
+                       const HAL_KEYVAL *k, const uint8_t *mac,
+                       int xorKey)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+	uint32_t key0, key1, key2, key3, key4;
+	uint32_t keyType;
+	uint32_t xorMask = xorKey ?
+		(KEY_XOR << 24 | KEY_XOR << 16 | KEY_XOR << 8 | KEY_XOR) : 0;
+
+	if (entry >= pCap->halKeyCacheSize) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: entry %u out of range\n",
+		    __func__, entry);
+		return AH_FALSE;
+	}
+	switch (k->kv_type) {
+	case HAL_CIPHER_AES_OCB:
+		keyType = AR_KEYTABLE_TYPE_AES;
+		break;
+	case HAL_CIPHER_AES_CCM:
+		if (!pCap->halCipherAesCcmSupport) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: AES-CCM not supported by mac rev 0x%x\n",
+			    __func__, AH_PRIVATE(ah)->ah_macRev);
+			return AH_FALSE;
+		}
+		keyType = AR_KEYTABLE_TYPE_CCM;
+		break;
+	case HAL_CIPHER_TKIP:
+		keyType = AR_KEYTABLE_TYPE_TKIP;
+		if (IS_MIC_ENABLED(ah) && entry+64 >= pCap->halKeyCacheSize) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: entry %u inappropriate for TKIP\n",
+			    __func__, entry);
+			return AH_FALSE;
+		}
+		break;
+	case HAL_CIPHER_WEP:
+		if (k->kv_len < 40 / NBBY) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: WEP key length %u too small\n",
+			    __func__, k->kv_len);
+			return AH_FALSE;
+		}
+		if (k->kv_len <= 40 / NBBY)
+			keyType = AR_KEYTABLE_TYPE_40;
+		else if (k->kv_len <= 104 / NBBY)
+			keyType = AR_KEYTABLE_TYPE_104;
+		else
+			keyType = AR_KEYTABLE_TYPE_128;
+		break;
+	case HAL_CIPHER_CLR:
+		keyType = AR_KEYTABLE_TYPE_CLR;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cipher %u not supported\n",
+		    __func__, k->kv_type);
+		return AH_FALSE;
+	}
+
+	key0 = LE_READ_4(k->kv_val+0) ^ xorMask;
+	key1 = (LE_READ_2(k->kv_val+4) ^ xorMask) & 0xffff;
+	key2 = LE_READ_4(k->kv_val+6) ^ xorMask;
+	key3 = (LE_READ_2(k->kv_val+10) ^ xorMask) & 0xffff;
+	key4 = LE_READ_4(k->kv_val+12) ^ xorMask;
+	if (k->kv_len <= 104 / NBBY)
+		key4 &= 0xff;
+
+	/*
+	 * Note: key cache hardware requires that each double-word
+	 * pair be written in even/odd order (since the destination is
+	 * a 64-bit register).  Don't reorder these writes w/o
+	 * considering this!
+	 */
+	if (keyType == AR_KEYTABLE_TYPE_TKIP && IS_MIC_ENABLED(ah)) {
+		uint16_t micentry = entry+64;	/* MIC goes at slot+64 */
+		uint32_t mic0, mic1, mic2, mic3, mic4;
+
+		/*
+		 * Invalidate the encrypt/decrypt key until the MIC
+		 * key is installed so pending rx frames will fail
+		 * with decrypt errors rather than a MIC error.
+		 */
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
+		OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
+		(void) ar5212SetKeyCacheEntryMac(ah, entry, mac);
+
+
+		/*
+		 * Write MIC entry according to new or old key layout.
+		 * The MISC_MODE register is assumed already set so
+		 * these writes will be handled properly (happens on
+		 * attach and at every reset).
+		 */
+		/* RX mic */
+		mic0 = LE_READ_4(k->kv_mic+0);
+		mic2 = LE_READ_4(k->kv_mic+4);
+		if (ahp->ah_miscMode & AR_MISC_MODE_MIC_NEW_LOC_ENABLE) {
+			/*
+			 * Both RX and TX mic values can be combined into
+			 * one cache slot entry:
+			 *  8*N + 800         31:0    RX Michael key 0
+			 *  8*N + 804         15:0    TX Michael key 0 [31:16]
+			 *  8*N + 808         31:0    RX Michael key 1
+			 *  8*N + 80C         15:0    TX Michael key 0 [15:0]
+			 *  8*N + 810         31:0    TX Michael key 1
+			 *  8*N + 814         15:0    reserved
+			 *  8*N + 818         31:0    reserved
+			 *  8*N + 81C         14:0    reserved
+			 *                    15      key valid == 0
+			 */
+			/* TX mic */
+			mic1 = LE_READ_2(k->kv_txmic+2) & 0xffff;
+			mic3 = LE_READ_2(k->kv_txmic+0) & 0xffff;
+			mic4 = LE_READ_4(k->kv_txmic+4);
+		} else {
+			mic1 = mic3 = mic4 = 0;
+		}
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
+		OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
+			AR_KEYTABLE_TYPE_CLR);
+		/* NB: MIC key is not marked valid and has no MAC address */
+		OS_REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
+
+		/* correct intentionally corrupted key */
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
+	} else {
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
+		OS_REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
+		OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
+
+		(void) ar5212SetKeyCacheEntryMac(ah, entry, mac);
+	}
+	return AH_TRUE;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_misc.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_misc.c
new file mode 100644
index 0000000..5f23f92
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_misc.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c,v 1.2.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+#ifdef AH_DEBUG
+#include "ah_desc.h"			/* NB: for HAL_PHYERR* */
+#endif
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#include "ah_eeprom_v3.h"
+
+#define	AR_NUM_GPIO	6		/* 6 GPIO pins */
+#define	AR_GPIOD_MASK	0x0000002F	/* GPIO data reg r/w mask */
+
+extern void ar5212SetRateDurationTable(struct ath_hal *, HAL_CHANNEL *);
+
+void
+ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
+}
+
+HAL_BOOL
+ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
+	return AH_TRUE;
+}
+
+void
+ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	OS_MEMCPY(mask, ahp->ah_bssidmask, IEEE80211_ADDR_LEN);
+}
+
+HAL_BOOL
+ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	/* save it since it must be rewritten on reset */
+	OS_MEMCPY(ahp->ah_bssidmask, mask, IEEE80211_ADDR_LEN);
+
+	OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
+	OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
+	return AH_TRUE;
+}
+
+/*
+ * Attempt to change the cards operating regulatory domain to the given value
+ */
+HAL_BOOL
+ar5212SetRegulatoryDomain(struct ath_hal *ah,
+	uint16_t regDomain, HAL_STATUS *status)
+{
+	HAL_STATUS ecode;
+
+	if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
+		ecode = HAL_EINVAL;
+		goto bad;
+	}
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
+		ecode = HAL_EEWRITE;
+		goto bad;
+	}
+#ifdef AH_SUPPORT_WRITE_REGDOMAIN
+	if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: set regulatory domain to %u (0x%x)\n",
+		    __func__, regDomain, regDomain);
+		AH_PRIVATE(ah)->ah_currentRD = regDomain;
+		return AH_TRUE;
+	}
+#endif
+	ecode = HAL_EIO;
+bad:
+	if (status)
+		*status = ecode;
+	return AH_FALSE;
+}
+
+/*
+ * Return the wireless modes (a,b,g,t) supported by hardware.
+ *
+ * This value is what is actually supported by the hardware
+ * and is unaffected by regulatory/country code settings.
+ */
+u_int
+ar5212GetWirelessModes(struct ath_hal *ah)
+{
+	u_int mode = 0;
+
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
+		mode = HAL_MODE_11A;
+		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
+			mode |= HAL_MODE_TURBO | HAL_MODE_108A;
+		if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
+			mode |= HAL_MODE_11A_HALF_RATE;
+		if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
+			mode |= HAL_MODE_11A_QUARTER_RATE;
+	}
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
+		mode |= HAL_MODE_11B;
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
+	    AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
+		mode |= HAL_MODE_11G;
+		if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
+			mode |= HAL_MODE_108G;
+		if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
+			mode |= HAL_MODE_11G_HALF_RATE;
+		if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
+			mode |= HAL_MODE_11G_QUARTER_RATE;
+	}
+	return mode;
+}
+
+/*
+ * Set the interrupt and GPIO values so the ISR can disable RF
+ * on a switch signal.  Assumes GPIO port and interrupt polarity
+ * are set prior to call.
+ */
+void
+ar5212EnableRfKill(struct ath_hal *ah)
+{
+	uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
+	int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
+	int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
+
+	/*
+	 * Configure the desired GPIO port for input
+	 * and enable baseband rf silence.
+	 */
+	ath_hal_gpioCfgInput(ah, select);
+	OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
+	/*
+	 * If radio disable switch connection to GPIO bit x is enabled
+	 * program GPIO interrupt.
+	 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
+	 * verified that it is a later version of eeprom, it has a place for
+	 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
+	 * connection is present.
+	 */
+	ath_hal_gpioSetIntr(ah, select,
+	    (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));
+}
+
+/*
+ * Change the LED blinking pattern to correspond to the connectivity
+ */
+void
+ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
+{
+	static const uint32_t ledbits[8] = {
+		AR_PCICFG_LEDCTL_NONE,	/* HAL_LED_INIT */
+		AR_PCICFG_LEDCTL_PEND,	/* HAL_LED_SCAN */
+		AR_PCICFG_LEDCTL_PEND,	/* HAL_LED_AUTH */
+		AR_PCICFG_LEDCTL_ASSOC,	/* HAL_LED_ASSOC*/
+		AR_PCICFG_LEDCTL_ASSOC,	/* HAL_LED_RUN */
+		AR_PCICFG_LEDCTL_NONE,
+		AR_PCICFG_LEDCTL_NONE,
+		AR_PCICFG_LEDCTL_NONE,
+	};
+	uint32_t bits;
+
+	bits = OS_REG_READ(ah, AR_PCICFG);
+	if (IS_2417(ah)) {
+		/*
+		 * Enable LED for Nala. There is a bit marked reserved
+		 * that must be set and we also turn on the power led.
+		 * Because we mark s/w LED control setting the control
+		 * status bits below is meangless (the driver must flash
+		 * the LED(s) using the GPIO lines).
+		 */
+		bits = (bits &~ AR_PCICFG_LEDMODE)
+		     | SM(AR_PCICFG_LEDMODE_POWON, AR_PCICFG_LEDMODE)
+#if 0
+		     | SM(AR_PCICFG_LEDMODE_NETON, AR_PCICFG_LEDMODE)
+#endif
+		     | 0x08000000;
+	}
+	bits = (bits &~ AR_PCICFG_LEDCTL)
+	     | SM(ledbits[state & 0x7], AR_PCICFG_LEDCTL);
+	OS_REG_WRITE(ah, AR_PCICFG, bits);
+}
+
+/*
+ * Change association related fields programmed into the hardware.
+ * Writing a valid BSSID to the hardware effectively enables the hardware
+ * to synchronize its TSF to the correct beacons and receive frames coming
+ * from that BSSID. It is called by the SME JOIN operation.
+ */
+void
+ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	/* XXX save bssid for possible re-use on reset */
+	OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
+	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
+	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
+				     ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
+}
+
+/*
+ * Get the current hardware tsf for stamlme
+ */
+uint64_t
+ar5212GetTsf64(struct ath_hal *ah)
+{
+	uint32_t low1, low2, u32;
+
+	/* sync multi-word read */
+	low1 = OS_REG_READ(ah, AR_TSF_L32);
+	u32 = OS_REG_READ(ah, AR_TSF_U32);
+	low2 = OS_REG_READ(ah, AR_TSF_L32);
+	if (low2 < low1) {	/* roll over */
+		/*
+		 * If we are not preempted this will work.  If we are
+		 * then we re-reading AR_TSF_U32 does no good as the
+		 * low bits will be meaningless.  Likewise reading
+		 * L32, U32, U32, then comparing the last two reads
+		 * to check for rollover doesn't help if preempted--so
+		 * we take this approach as it costs one less PCI read
+		 * which can be noticeable when doing things like
+		 * timestamping packets in monitor mode.
+		 */
+		u32++;
+	}
+	return (((uint64_t) u32) << 32) | ((uint64_t) low2);
+}
+
+/*
+ * Get the current hardware tsf for stamlme
+ */
+uint32_t
+ar5212GetTsf32(struct ath_hal *ah)
+{
+	return OS_REG_READ(ah, AR_TSF_L32);
+}
+
+/*
+ * Reset the current hardware tsf for stamlme.
+ */
+void
+ar5212ResetTsf(struct ath_hal *ah)
+{
+
+	uint32_t val = OS_REG_READ(ah, AR_BEACON);
+
+	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
+	/*
+	 * When resetting the TSF, write twice to the
+	 * corresponding register; each write to the RESET_TSF bit toggles
+	 * the internal signal to cause a reset of the TSF - but if the signal
+	 * is left high, it will reset the TSF on the next chip reset also!
+	 * writing the bit an even number of times fixes this issue
+	 */
+	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
+}
+
+/*
+ * Set or clear hardware basic rate bit
+ * Set hardware basic rate set if basic rate is found
+ * and basic rate is equal or less than 2Mbps
+ */
+void
+ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
+{
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	uint32_t reg;
+	uint8_t xset;
+	int i;
+
+	if (chan == AH_NULL || !IS_CHAN_CCK(chan))
+		return;
+	xset = 0;
+	for (i = 0; i < rs->rs_count; i++) {
+		uint8_t rset = rs->rs_rates[i];
+		/* Basic rate defined? */
+		if ((rset & 0x80) && (rset &= 0x7f) >= xset)
+			xset = rset;
+	}
+	/*
+	 * Set the h/w bit to reflect whether or not the basic
+	 * rate is found to be equal or less than 2Mbps.
+	 */
+	reg = OS_REG_READ(ah, AR_STA_ID1);
+	if (xset && xset/2 <= 2)
+		OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
+	else
+		OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
+}
+
+/*
+ * Grab a semi-random value from hardware registers - may not
+ * change often
+ */
+uint32_t
+ar5212GetRandomSeed(struct ath_hal *ah)
+{
+	uint32_t nf;
+
+	nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
+	if (nf & 0x100)
+		nf = 0 - ((nf ^ 0x1ff) + 1);
+	return (OS_REG_READ(ah, AR_TSF_U32) ^
+		OS_REG_READ(ah, AR_TSF_L32) ^ nf);
+}
+
+/*
+ * Detect if our card is present
+ */
+HAL_BOOL
+ar5212DetectCardPresent(struct ath_hal *ah)
+{
+	uint16_t macVersion, macRev;
+	uint32_t v;
+
+	/*
+	 * Read the Silicon Revision register and compare that
+	 * to what we read at attach time.  If the same, we say
+	 * a card/device is present.
+	 */
+	v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
+	macVersion = v >> AR_SREV_ID_S;
+	macRev = v & AR_SREV_REVISION;
+	return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
+		AH_PRIVATE(ah)->ah_macRev == macRev);
+}
+
+void
+ar5212EnableMibCounters(struct ath_hal *ah)
+{
+	/* NB: this just resets the mib counter machinery */
+	OS_REG_WRITE(ah, AR_MIBC,
+	    ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) & 0x0f);
+}
+
+void 
+ar5212DisableMibCounters(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_MIBC,  AR_MIBC | AR_MIBC_CMC);
+}
+
+/*
+ * Update MIB Counters
+ */
+void
+ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)
+{
+	stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
+	stats->rts_bad	  += OS_REG_READ(ah, AR_RTS_FAIL);
+	stats->fcs_bad	  += OS_REG_READ(ah, AR_FCS_FAIL);
+	stats->rts_good	  += OS_REG_READ(ah, AR_RTS_OK);
+	stats->beacons	  += OS_REG_READ(ah, AR_BEACON_CNT);
+}
+
+/*
+ * Detect if the HW supports spreading a CCK signal on channel 14
+ */
+HAL_BOOL
+ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)
+{
+	return AH_TRUE;
+}
+
+/*
+ * Get the rssi of frame curently being received.
+ */
+uint32_t
+ar5212GetCurRssi(struct ath_hal *ah)
+{
+	return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
+}
+
+u_int
+ar5212GetDefAntenna(struct ath_hal *ah)
+{   
+	return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
+}   
+
+void
+ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)
+{
+	OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
+}
+
+HAL_ANT_SETTING
+ar5212GetAntennaSwitch(struct ath_hal *ah)
+{
+	return AH5212(ah)->ah_antControl;
+}
+
+HAL_BOOL
+ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_CHANNEL_INTERNAL *ichan = AH_PRIVATE(ah)->ah_curchan;
+
+	if (!ahp->ah_phyPowerOn || ichan == AH_NULL) {
+		/* PHY powered off, just stash settings */
+		ahp->ah_antControl = setting;
+		ahp->ah_diversity = (setting == HAL_ANT_VARIABLE);
+		return AH_TRUE;
+	}
+	return ar5212SetAntennaSwitchInternal(ah, setting, ichan);
+}
+
+HAL_BOOL
+ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)
+{
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5212SetSifsTime(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	if (us > ath_hal_mac_usec(ah, 0xffff)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
+		    __func__, us);
+		ahp->ah_sifstime = (u_int) -1;	/* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us));
+		ahp->ah_slottime = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5212GetSifsTime(struct ath_hal *ah)
+{
+	u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+HAL_BOOL
+ar5212SetSlotTime(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
+		    __func__, us);
+		ahp->ah_slottime = (u_int) -1;	/* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
+		ahp->ah_slottime = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5212GetSlotTime(struct ath_hal *ah)
+{
+	u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+HAL_BOOL
+ar5212SetAckTimeout(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
+		    __func__, us);
+		ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
+			AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
+		ahp->ah_acktimeout = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5212GetAckTimeout(struct ath_hal *ah)
+{
+	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+u_int
+ar5212GetAckCTSRate(struct ath_hal *ah)
+{
+	return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
+}
+
+HAL_BOOL
+ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	if (high) {
+		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
+		ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
+	} else {
+		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
+		ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
+	}
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
+		    __func__, us);
+		ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
+		return AH_FALSE;
+	} else {
+		/* convert to system clocks */
+		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
+			AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
+		ahp->ah_ctstimeout = us;
+		return AH_TRUE;
+	}
+}
+
+u_int
+ar5212GetCTSTimeout(struct ath_hal *ah)
+{
+	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
+	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */
+}
+
+/* Setup decompression for given key index */
+HAL_BOOL
+ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+        if (keyidx >= HAL_DECOMP_MASK_SIZE)
+                return HAL_EINVAL; 
+        OS_REG_WRITE(ah, AR_DCM_A, keyidx);
+        OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
+        ahp->ah_decompMask[keyidx] = en;
+
+        return AH_TRUE;
+}
+
+/* Setup coverage class */
+void
+ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
+{
+	uint32_t slot, timeout, eifs;
+	u_int clkRate;
+
+	AH_PRIVATE(ah)->ah_coverageClass = coverageclass;
+
+	if (now) {
+		if (AH_PRIVATE(ah)->ah_coverageClass == 0)
+			return;
+
+		/* Don't apply coverage class to non A channels */
+		if (!IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
+			return;
+
+		/* Get core clock rate */
+		clkRate = ath_hal_mac_clks(ah, 1);
+
+		/* Compute EIFS */
+		slot = coverageclass * 3 * clkRate;
+		eifs = coverageclass * 6 * clkRate;
+		if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+			slot += IFS_SLOT_HALF_RATE;
+			eifs += IFS_EIFS_HALF_RATE;
+		} else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+			slot += IFS_SLOT_QUARTER_RATE;
+			eifs += IFS_EIFS_QUARTER_RATE;
+		} else { /* full rate */
+			slot += IFS_SLOT_FULL_RATE;
+			eifs += IFS_EIFS_FULL_RATE;
+		}
+
+		/*
+		 * Add additional time for air propagation for ACK and CTS
+		 * timeouts. This value is in core clocks.
+  		 */
+		timeout = ACK_CTS_TIMEOUT_11A + (coverageclass * 3 * clkRate);
+	
+		/*
+		 * Write the values: slot, eifs, ack/cts timeouts.
+		 */
+		OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
+		OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
+		OS_REG_WRITE(ah, AR_TIME_OUT,
+			  SM(timeout, AR_TIME_OUT_CTS)
+			| SM(timeout, AR_TIME_OUT_ACK));
+	}
+}
+
+void
+ar5212SetPCUConfig(struct ath_hal *ah)
+{
+	ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
+}
+
+/*
+ * Return whether an external 32KHz crystal should be used
+ * to reduce power consumption when sleeping.  We do so if
+ * the crystal is present (obtained from EEPROM) and if we
+ * are not running as an AP and are configured to use it.
+ */
+HAL_BOOL
+ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)
+{
+	if (opmode != HAL_M_HOSTAP) {
+		struct ath_hal_5212 *ahp = AH5212(ah);
+		return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&
+		       (ahp->ah_enable32kHzClock == USE_32KHZ ||
+		        ahp->ah_enable32kHzClock == AUTO_32KHZ);
+	} else
+		return AH_FALSE;
+}
+
+/*
+ * If 32KHz clock exists, use it to lower power consumption during sleep
+ *
+ * Note: If clock is set to 32 KHz, delays on accessing certain
+ *       baseband registers (27-31, 124-127) are required.
+ */
+void
+ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
+{
+	if (ar5212Use32KHzclock(ah, opmode)) {
+		/*
+		 * Enable clocks to be turned OFF in BB during sleep
+		 * and also enable turning OFF 32MHz/40MHz Refclk
+		 * from A2.
+		 */
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
+		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
+		    IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
+		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
+		OS_REG_WRITE(ah, AR_TSF_PARM, 61);  /* 32 KHz TSF incr */
+		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
+
+		if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x26);
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0d);
+			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x07);
+			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0x3f);
+			/* # Set sleep clock rate to 32 KHz. */
+			OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x0a);
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0c);
+			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x03);
+			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0x20);
+			OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
+		}
+	} else {
+		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
+		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
+
+		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32MHz TSF inc */
+
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
+
+		if (IS_2417(ah))
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);
+		else if (IS_HB63(ah))
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);
+		else
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
+		OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
+		OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
+		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
+		    IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);
+		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
+		    IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
+	}
+}
+
+/*
+ * If 32KHz clock exists, turn it off and turn back on the 32Mhz
+ */
+void
+ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
+{
+	if (ar5212Use32KHzclock(ah, opmode)) {
+		/* # Set sleep clock rate back to 32 MHz. */
+		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
+		OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
+
+		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32 MHz TSF incr */
+		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
+		    IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
+
+		/*
+		 * Restore BB registers to power-on defaults
+		 */
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0e);
+		OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
+		OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
+		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
+		    IS_RAD5112_ANY(ah) || IS_5413(ah) ?  0x14 : 0x18);
+	}
+}
+
+/*
+ * Adjust NF based on statistical values for 5GHz frequencies.
+ * Default method: this may be overridden by the rf backend.
+ */
+int16_t
+ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
+{
+	static const struct {
+		uint16_t freqLow;
+		int16_t	  adjust;
+	} adjustDef[] = {
+		{ 5790,	11 },	/* NB: ordered high -> low */
+		{ 5730, 10 },
+		{ 5690,  9 },
+		{ 5660,  8 },
+		{ 5610,  7 },
+		{ 5530,  5 },
+		{ 5450,  4 },
+		{ 5379,  2 },
+		{ 5209,  0 },
+		{ 3000,  1 },
+		{    0,  0 },
+	};
+	int i;
+
+	for (i = 0; c->channel <= adjustDef[i].freqLow; i++)
+		;
+	return adjustDef[i].adjust;
+}
+
+HAL_STATUS
+ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+	uint32_t capability, uint32_t *result)
+{
+#define	MACVERSION(ah)	AH_PRIVATE(ah)->ah_macVersion
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+	const struct ar5212AniState *ani;
+
+	switch (type) {
+	case HAL_CAP_CIPHER:		/* cipher handled in hardware */
+		switch (capability) {
+		case HAL_CIPHER_AES_CCM:
+			return pCap->halCipherAesCcmSupport ?
+				HAL_OK : HAL_ENOTSUPP;
+		case HAL_CIPHER_AES_OCB:
+		case HAL_CIPHER_TKIP:
+		case HAL_CIPHER_WEP:
+		case HAL_CIPHER_MIC:
+		case HAL_CIPHER_CLR:
+			return HAL_OK;
+		default:
+			return HAL_ENOTSUPP;
+		}
+	case HAL_CAP_TKIP_MIC:		/* handle TKIP MIC in hardware */
+		switch (capability) {
+		case 0:			/* hardware capability */
+			return HAL_OK;
+		case 1:
+			return (ahp->ah_staId1Defaults &
+			    AR_STA_ID1_CRPT_MIC_ENABLE) ?  HAL_OK : HAL_ENXIO;
+		}
+		return HAL_EINVAL;
+	case HAL_CAP_TKIP_SPLIT:	/* hardware TKIP uses split keys */
+		switch (capability) {
+		case 0:			/* hardware capability */
+			return pCap->halTkipMicTxRxKeySupport ?
+				HAL_ENXIO : HAL_OK;
+		case 1:			/* current setting */
+			return (ahp->ah_miscMode &
+			    AR_MISC_MODE_MIC_NEW_LOC_ENABLE) ? HAL_ENXIO : HAL_OK;
+		}
+		return HAL_EINVAL;
+	case HAL_CAP_WME_TKIPMIC:	/* hardware can do TKIP MIC w/ WMM */
+		/* XXX move to capability bit */
+		return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||
+		    (MACVERSION(ah) == AR_SREV_VERSION_VENICE &&
+		     AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_DIVERSITY:		/* hardware supports fast diversity */
+		switch (capability) {
+		case 0:			/* hardware capability */
+			return HAL_OK;
+		case 1:			/* current setting */
+			return ahp->ah_diversity ? HAL_OK : HAL_ENXIO;
+		}
+		return HAL_EINVAL;
+	case HAL_CAP_DIAG:
+		*result = AH_PRIVATE(ah)->ah_diagreg;
+		return HAL_OK;
+	case HAL_CAP_TPC:
+		switch (capability) {
+		case 0:			/* hardware capability */
+			return HAL_OK;
+		case 1:
+			return ahp->ah_tpcEnabled ? HAL_OK : HAL_ENXIO;
+		}
+		return HAL_OK;
+	case HAL_CAP_PHYDIAG:		/* radar pulse detection capability */
+		switch (capability) {
+		case HAL_CAP_RADAR:
+			return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?
+			    HAL_OK: HAL_ENXIO;
+		case HAL_CAP_AR:
+			return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||
+			    ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?
+			       HAL_OK: HAL_ENXIO;
+		}
+		return HAL_ENXIO;
+	case HAL_CAP_MCAST_KEYSRCH:	/* multicast frame keycache search */
+		switch (capability) {
+		case 0:			/* hardware capability */
+			return HAL_OK;
+		case 1:
+			return (ahp->ah_staId1Defaults &
+			    AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
+		}
+		return HAL_EINVAL;
+	case HAL_CAP_TSF_ADJUST:	/* hardware has beacon tsf adjust */
+		switch (capability) {
+		case 0:			/* hardware capability */
+			return pCap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
+		case 1:
+			return (ahp->ah_miscMode & AR_MISC_MODE_TX_ADD_TSF) ?
+				HAL_OK : HAL_ENXIO;
+		}
+		return HAL_EINVAL;
+	case HAL_CAP_TPC_ACK:
+		*result = MS(ahp->ah_macTPC, AR_TPC_ACK);
+		return HAL_OK;
+	case HAL_CAP_TPC_CTS:
+		*result = MS(ahp->ah_macTPC, AR_TPC_CTS);
+		return HAL_OK;
+	case HAL_CAP_INTMIT:		/* interference mitigation */
+		switch (capability) {
+		case 0:			/* hardware capability */
+			return HAL_OK;
+		case 1:
+			return (ahp->ah_procPhyErr & HAL_ANI_ENA) ?
+				HAL_OK : HAL_ENXIO;
+		case 2:			/* HAL_ANI_NOISE_IMMUNITY_LEVEL */
+		case 3:			/* HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION */
+		case 4:			/* HAL_ANI_CCK_WEAK_SIGNAL_THR */
+		case 5:			/* HAL_ANI_FIRSTEP_LEVEL */
+		case 6:			/* HAL_ANI_SPUR_IMMUNITY_LEVEL */
+			ani = ar5212AniGetCurrentState(ah);
+			if (ani == AH_NULL)
+				return HAL_ENXIO;
+			switch (capability) {
+			case 2:	*result = ani->noiseImmunityLevel; break;
+			case 3: *result = !ani->ofdmWeakSigDetectOff; break;
+			case 4: *result = ani->cckWeakSigThreshold; break;
+			case 5: *result = ani->firstepLevel; break;
+			case 6: *result = ani->spurImmunityLevel; break;
+			}
+			return HAL_OK;
+		}
+		return HAL_EINVAL;
+	default:
+		return ath_hal_getcapability(ah, type, capability, result);
+	}
+#undef MACVERSION
+}
+
+HAL_BOOL
+ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+	uint32_t capability, uint32_t setting, HAL_STATUS *status)
+{
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+	uint32_t v;
+
+	switch (type) {
+	case HAL_CAP_TKIP_MIC:		/* handle TKIP MIC in hardware */
+		if (setting)
+			ahp->ah_staId1Defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
+		else
+			ahp->ah_staId1Defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
+		return AH_TRUE;
+	case HAL_CAP_TKIP_SPLIT:	/* hardware TKIP uses split keys */
+		if (!pCap->halTkipMicTxRxKeySupport)
+			return AH_FALSE;
+		/* NB: true =>'s use split key cache layout */
+		if (setting)
+			ahp->ah_miscMode &= ~AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
+		else
+			ahp->ah_miscMode |= AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
+		/* NB: write here so keys can be setup w/o a reset */
+		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+		return AH_TRUE;
+	case HAL_CAP_DIVERSITY:
+		if (ahp->ah_phyPowerOn) {
+			v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
+			if (setting)
+				v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
+			else
+				v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
+			OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
+		}
+		ahp->ah_diversity = (setting != 0);
+		return AH_TRUE;
+	case HAL_CAP_DIAG:		/* hardware diagnostic support */
+		/*
+		 * NB: could split this up into virtual capabilities,
+		 *     (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
+		 *     seems worth the additional complexity.
+		 */
+		AH_PRIVATE(ah)->ah_diagreg = setting;
+		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
+		return AH_TRUE;
+	case HAL_CAP_TPC:
+		ahp->ah_tpcEnabled = (setting != 0);
+		return AH_TRUE;
+	case HAL_CAP_MCAST_KEYSRCH:	/* multicast frame keycache search */
+		if (setting)
+			ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
+		else
+			ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
+		return AH_TRUE;
+	case HAL_CAP_TPC_ACK:
+	case HAL_CAP_TPC_CTS:
+		setting += ahp->ah_txPowerIndexOffset;
+		if (setting > 63)
+			setting = 63;
+		if (type == HAL_CAP_TPC_ACK) {
+			ahp->ah_macTPC &= AR_TPC_ACK;
+			ahp->ah_macTPC |= MS(setting, AR_TPC_ACK);
+		} else {
+			ahp->ah_macTPC &= AR_TPC_CTS;
+			ahp->ah_macTPC |= MS(setting, AR_TPC_CTS);
+		}
+		OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);
+		return AH_TRUE;
+	case HAL_CAP_INTMIT: {		/* interference mitigation */
+		static const HAL_ANI_CMD cmds[] = {
+			HAL_ANI_PRESENT,
+			HAL_ANI_MODE,
+			HAL_ANI_NOISE_IMMUNITY_LEVEL,
+			HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+			HAL_ANI_CCK_WEAK_SIGNAL_THR,
+			HAL_ANI_FIRSTEP_LEVEL,
+			HAL_ANI_SPUR_IMMUNITY_LEVEL,
+		};
+		return capability < N(cmds) ?
+			ar5212AniControl(ah, cmds[capability], setting) :
+			AH_FALSE;
+	}
+	case HAL_CAP_TSF_ADJUST:	/* hardware has beacon tsf adjust */
+		if (pCap->halTsfAddSupport) {
+			if (setting)
+				ahp->ah_miscMode |= AR_MISC_MODE_TX_ADD_TSF;
+			else
+				ahp->ah_miscMode &= ~AR_MISC_MODE_TX_ADD_TSF;
+			return AH_TRUE;
+		}
+		/* fall thru... */
+	default:
+		return ath_hal_setcapability(ah, type, capability,
+				setting, status);
+	}
+#undef N
+}
+
+HAL_BOOL
+ar5212GetDiagState(struct ath_hal *ah, int request,
+	const void *args, uint32_t argsize,
+	void **result, uint32_t *resultsize)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	(void) ahp;
+	if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
+		return AH_TRUE;
+	switch (request) {
+	case HAL_DIAG_EEPROM:
+	case HAL_DIAG_EEPROM_EXP_11A:
+	case HAL_DIAG_EEPROM_EXP_11B:
+	case HAL_DIAG_EEPROM_EXP_11G:
+	case HAL_DIAG_RFGAIN:
+		return ath_hal_eepromDiag(ah, request,
+		    args, argsize, result, resultsize);
+	case HAL_DIAG_RFGAIN_CURSTEP:
+		*result = __DECONST(void *, ahp->ah_gainValues.currStep);
+		*resultsize = (*result == AH_NULL) ?
+			0 : sizeof(GAIN_OPTIMIZATION_STEP);
+		return AH_TRUE;
+	case HAL_DIAG_PCDAC:
+		*result = ahp->ah_pcdacTable;
+		*resultsize = ahp->ah_pcdacTableSize;
+		return AH_TRUE;
+	case HAL_DIAG_TXRATES:
+		*result = &ahp->ah_ratesArray[0];
+		*resultsize = sizeof(ahp->ah_ratesArray);
+		return AH_TRUE;
+	case HAL_DIAG_ANI_CURRENT:
+		*result = ar5212AniGetCurrentState(ah);
+		*resultsize = (*result == AH_NULL) ?
+			0 : sizeof(struct ar5212AniState);
+		return AH_TRUE;
+	case HAL_DIAG_ANI_STATS:
+		*result = ar5212AniGetCurrentStats(ah);
+		*resultsize = (*result == AH_NULL) ?
+			0 : sizeof(struct ar5212Stats);
+		return AH_TRUE;
+	case HAL_DIAG_ANI_CMD:
+		if (argsize != 2*sizeof(uint32_t))
+			return AH_FALSE;
+		ar5212AniControl(ah, ((const uint32_t *)args)[0],
+			((const uint32_t *)args)[1]);
+		return AH_TRUE;
+	case HAL_DIAG_ANI_PARAMS:
+		/*
+		 * NB: We assume struct ar5212AniParams is identical
+		 * to HAL_ANI_PARAMS; if they diverge then we'll need
+		 * to handle it here
+		 */
+		if (argsize == 0 && args == AH_NULL) {
+			struct ar5212AniState *aniState =
+			    ar5212AniGetCurrentState(ah);
+			if (aniState == AH_NULL)
+				return AH_FALSE;
+			*result = __DECONST(void *, aniState->params);
+			*resultsize = sizeof(struct ar5212AniParams);
+			return AH_TRUE;
+		} else {
+			if (argsize != sizeof(struct ar5212AniParams))
+				return AH_FALSE;
+			return ar5212AniSetParams(ah, args, args);
+		}
+	}
+	return AH_FALSE;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_phy.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_phy.c
new file mode 100644
index 0000000..96e6725
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_phy.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_phy.c,v 1.5 2008/11/15 03:43:53 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+
+/* shorthands to compact tables for readability */
+#define	OFDM	IEEE80211_T_OFDM
+#define	CCK	IEEE80211_T_CCK
+#define	TURBO	IEEE80211_T_TURBO
+
+HAL_RATE_TABLE ar5212_11a_table = {
+	8,  /* number of rates */
+	{ 0 },
+	{
+/*                                                  short            ctrl  */
+/*                valid                 rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, OFDM,    6000,     0x0b,    0x00, (0x80|12),   0 },
+/*   9 Mb */ {  AH_TRUE, OFDM,    9000,     0x0f,    0x00,        18,   0 },
+/*  12 Mb */ {  AH_TRUE, OFDM,   12000,     0x0a,    0x00, (0x80|24),   2 },
+/*  18 Mb */ {  AH_TRUE, OFDM,   18000,     0x0e,    0x00,        36,   2 },
+/*  24 Mb */ {  AH_TRUE, OFDM,   24000,     0x09,    0x00, (0x80|48),   4 },
+/*  36 Mb */ {  AH_TRUE, OFDM,   36000,     0x0d,    0x00,        72,   4 },
+/*  48 Mb */ {  AH_TRUE, OFDM,   48000,     0x08,    0x00,        96,   4 },
+/*  54 Mb */ {  AH_TRUE, OFDM,   54000,     0x0c,    0x00,       108,   4 }
+	},
+};
+
+HAL_RATE_TABLE ar5212_half_table = {
+	8,  /* number of rates */
+	{ 0 },
+	{
+/*                                                  short            ctrl  */
+/*                valid                 rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, OFDM,    3000,     0x0b,    0x00, (0x80|6),   0 },
+/*   9 Mb */ {  AH_TRUE, OFDM,    4500,     0x0f,    0x00,        9,   0 },
+/*  12 Mb */ {  AH_TRUE, OFDM,    6000,     0x0a,    0x00, (0x80|12),   2 },
+/*  18 Mb */ {  AH_TRUE, OFDM,    9000,     0x0e,    0x00,        18,   2 },
+/*  24 Mb */ {  AH_TRUE, OFDM,   12000,     0x09,    0x00, (0x80|24),   4 },
+/*  36 Mb */ {  AH_TRUE, OFDM,   18000,     0x0d,    0x00,        36,   4 },
+/*  48 Mb */ {  AH_TRUE, OFDM,   24000,     0x08,    0x00,        48,   4 },
+/*  54 Mb */ {  AH_TRUE, OFDM,   27000,     0x0c,    0x00,       54,   4 }
+	},
+};
+
+HAL_RATE_TABLE ar5212_quarter_table = {
+	8,  /* number of rates */
+	{ 0 },
+	{
+/*                                                  short            ctrl  */
+/*                valid                 rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, OFDM,    1500,     0x0b,    0x00, (0x80|3),   0 },
+/*   9 Mb */ {  AH_TRUE, OFDM,    2250,     0x0f,    0x00,        4,   0 },
+/*  12 Mb */ {  AH_TRUE, OFDM,    3000,     0x0a,    0x00, (0x80|6),   2 },
+/*  18 Mb */ {  AH_TRUE, OFDM,    4500,     0x0e,    0x00,        9,   2 },
+/*  24 Mb */ {  AH_TRUE, OFDM,    6000,     0x09,    0x00, (0x80|12),   4 },
+/*  36 Mb */ {  AH_TRUE, OFDM,    9000,     0x0d,    0x00,        18,   4 },
+/*  48 Mb */ {  AH_TRUE, OFDM,   12000,     0x08,    0x00,        24,   4 },
+/*  54 Mb */ {  AH_TRUE, OFDM,   13500,     0x0c,    0x00,       27,   4 }
+	},
+};
+
+HAL_RATE_TABLE ar5212_turbog_table = {
+	7,  /* number of rates */
+	{ 0 },
+	{
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, TURBO,   6000,    0x0b,    0x00, (0x80|12),   0 },
+/*  12 Mb */ {  AH_TRUE, TURBO,  12000,    0x0a,    0x00, (0x80|24),   2 },
+/*  18 Mb */ {  AH_TRUE, TURBO,  18000,    0x0e,    0x00,        36,   2 },
+/*  24 Mb */ {  AH_TRUE, TURBO,  24000,    0x09,    0x00, (0x80|48),   3 },
+/*  36 Mb */ {  AH_TRUE, TURBO,  36000,    0x0d,    0x00,        72,   3 },
+/*  48 Mb */ {  AH_TRUE, TURBO,  48000,    0x08,    0x00,        96,   3 },
+/*  54 Mb */ {  AH_TRUE, TURBO,  54000,    0x0c,    0x00,       108,   3 }
+	},
+};
+
+HAL_RATE_TABLE ar5212_turboa_table = {
+	8,  /* number of rates */
+	{ 0 },
+	{
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, TURBO,   6000,    0x0b,    0x00, (0x80|12),   0 },
+/*   9 Mb */ {  AH_TRUE, TURBO,   9000,    0x0f,    0x00,        18,   0 },
+/*  12 Mb */ {  AH_TRUE, TURBO,  12000,    0x0a,    0x00, (0x80|24),   2 },
+/*  18 Mb */ {  AH_TRUE, TURBO,  18000,    0x0e,    0x00,        36,   2 },
+/*  24 Mb */ {  AH_TRUE, TURBO,  24000,    0x09,    0x00, (0x80|48),   4 },
+/*  36 Mb */ {  AH_TRUE, TURBO,  36000,    0x0d,    0x00,        72,   4 },
+/*  48 Mb */ {  AH_TRUE, TURBO,  48000,    0x08,    0x00,        96,   4 },
+/*  54 Mb */ {  AH_TRUE, TURBO,  54000,    0x0c,    0x00,       108,   4 }
+	},
+};
+
+HAL_RATE_TABLE ar5212_11b_table = {
+	4,  /* number of rates */
+	{ 0 },
+	{
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   1 Mb */ {  AH_TRUE,  CCK,    1000,    0x1b,    0x00, (0x80| 2),   0 },
+/*   2 Mb */ {  AH_TRUE,  CCK,    2000,    0x1a,    0x04, (0x80| 4),   1 },
+/* 5.5 Mb */ {  AH_TRUE,  CCK,    5500,    0x19,    0x04, (0x80|11),   1 },
+/*  11 Mb */ {  AH_TRUE,  CCK,   11000,    0x18,    0x04, (0x80|22),   1 }
+	},
+};
+
+
+/* Venice TODO: roundUpRate() is broken when the rate table does not represent rates
+ * in increasing order  e.g.  5.5, 11, 6, 9.    
+ * An average rate of 6 Mbps will currently map to 11 Mbps. 
+ */
+HAL_RATE_TABLE ar5212_11g_table = {
+	12,  /* number of rates */
+	{ 0 },
+	{
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   1 Mb */ {  AH_TRUE, CCK,     1000,    0x1b,    0x00, (0x80| 2),   0 },
+/*   2 Mb */ {  AH_TRUE, CCK,     2000,    0x1a,    0x04, (0x80| 4),   1 },
+/* 5.5 Mb */ {  AH_TRUE, CCK,     5500,    0x19,    0x04, (0x80|11),   2 },
+/*  11 Mb */ {  AH_TRUE, CCK,    11000,    0x18,    0x04, (0x80|22),   3 },
+/* remove rates 6, 9 from rate ctrl */
+/*   6 Mb */ { AH_FALSE, OFDM,    6000,    0x0b,    0x00,        12,   4 },
+/*   9 Mb */ { AH_FALSE, OFDM,    9000,    0x0f,    0x00,        18,   4 },
+/*  12 Mb */ {  AH_TRUE, OFDM,   12000,    0x0a,    0x00,        24,   6 },
+/*  18 Mb */ {  AH_TRUE, OFDM,   18000,    0x0e,    0x00,        36,   6 },
+/*  24 Mb */ {  AH_TRUE, OFDM,   24000,    0x09,    0x00,        48,   8 },
+/*  36 Mb */ {  AH_TRUE, OFDM,   36000,    0x0d,    0x00,        72,   8 },
+/*  48 Mb */ {  AH_TRUE, OFDM,   48000,    0x08,    0x00,        96,   8 },
+/*  54 Mb */ {  AH_TRUE, OFDM,   54000,    0x0c,    0x00,       108,   8 }
+	},
+};
+
+#undef	OFDM
+#undef	CCK
+#undef	TURBO
+#undef	XR
+
+const HAL_RATE_TABLE *
+ar5212GetRateTable(struct ath_hal *ah, u_int mode)
+{
+	HAL_RATE_TABLE *rt;
+	switch (mode) {
+	case HAL_MODE_11A:
+		rt = &ar5212_11a_table;
+		break;
+	case HAL_MODE_11B:
+		rt = &ar5212_11b_table;
+		break;
+	case HAL_MODE_11G:
+#ifdef notdef
+	case HAL_MODE_PUREG:
+#endif
+		rt =  &ar5212_11g_table;
+		break;
+	case HAL_MODE_108A:
+	case HAL_MODE_TURBO:
+		rt =  &ar5212_turboa_table;
+		break;
+	case HAL_MODE_108G:
+		rt =  &ar5212_turbog_table;
+		break;
+	case HAL_MODE_11A_HALF_RATE:
+	case HAL_MODE_11G_HALF_RATE:
+		rt = &ar5212_half_table;
+		break;
+	case HAL_MODE_11A_QUARTER_RATE:
+	case HAL_MODE_11G_QUARTER_RATE:
+		rt = &ar5212_quarter_table;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid mode 0x%x\n",
+		    __func__, mode);
+		return AH_NULL;
+	}
+	ath_hal_setupratetable(ah, rt);
+	return rt;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_power.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_power.c
new file mode 100644
index 0000000..aca52ad
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_power.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_power.c,v 1.4 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212desc.h"
+
+/*
+ * Notify Power Mgt is enabled in self-generated frames.
+ * If requested, force chip awake.
+ *
+ * Returns A_OK if chip is awake or successfully forced awake.
+ *
+ * WARNING WARNING WARNING
+ * There is a problem with the chip where sometimes it will not wake up.
+ */
+static HAL_BOOL
+ar5212SetPowerModeAwake(struct ath_hal *ah, int setChip)
+{
+#define	AR_SCR_MASK \
+    (AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
+     AR_SCR_SLEPOL|AR_SCR_MIBIE)
+#define	POWER_UP_TIME	2000
+	uint32_t scr, val;
+	int i;
+
+	if (setChip) {
+		/*
+		 * Be careful setting the AWAKE mode.  When we are called
+		 * with the chip powered down the read returns 0xffffffff
+		 * which when blindly written back with OS_REG_RMW_FIELD 
+		 * enables the MIB interrupt for the sleep performance
+		 * counters.  This can result in an interrupt storm when
+		 * ANI is in operation as noone knows to turn off the MIB
+		 * interrupt cause.
+		 */
+		scr = OS_REG_READ(ah, AR_SCR);
+		if (scr & ~AR_SCR_MASK) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: bogus SCR 0x%x, PCICFG 0x%x\n",
+			    __func__, scr, OS_REG_READ(ah, AR_PCICFG));
+			scr = 0;
+		}
+		scr = (scr &~ AR_SCR_SLE) | AR_SCR_SLE_WAKE;
+		OS_REG_WRITE(ah, AR_SCR, scr);
+		OS_DELAY(10);	/* Give chip the chance to awake */
+
+		for (i = POWER_UP_TIME / 50; i != 0; i--) {
+			val = OS_REG_READ(ah, AR_PCICFG);
+			if ((val & AR_PCICFG_SPWR_DN) == 0)
+				break;
+			OS_DELAY(50);
+			OS_REG_WRITE(ah, AR_SCR, scr);
+		}
+		if (i == 0) {
+#ifdef AH_DEBUG
+			ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",
+				__func__, POWER_UP_TIME/50);
+#endif
+			return AH_FALSE;
+		}
+	} 
+
+	OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	return AH_TRUE;
+#undef POWER_UP_TIME
+#undef AR_SCR_MASK
+}
+
+/*
+ * Notify Power Mgt is disabled in self-generated frames.
+ * If requested, force chip to sleep.
+ */
+static void
+ar5212SetPowerModeSleep(struct ath_hal *ah, int setChip)
+{
+	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	if (setChip)
+		OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
+}
+
+/*
+ * Notify Power Management is enabled in self-generating
+ * fames.  If request, set power mode of chip to
+ * auto/normal.  Duration in units of 128us (1/8 TU).
+ */
+static void
+ar5212SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)
+{
+	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	if (setChip)
+		OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);
+}
+
+/*
+ * Set power mgt to the requested mode, and conditionally set
+ * the chip as well
+ */
+HAL_BOOL
+ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+#ifdef AH_DEBUG
+	static const char* modes[] = {
+		"AWAKE",
+		"FULL-SLEEP",
+		"NETWORK SLEEP",
+		"UNDEFINED"
+	};
+#endif
+	int status = AH_TRUE;
+
+	HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
+		modes[ahp->ah_powerMode], modes[mode],
+		setChip ? "set chip " : "");
+	switch (mode) {
+	case HAL_PM_AWAKE:
+		status = ar5212SetPowerModeAwake(ah, setChip);
+		break;
+	case HAL_PM_FULL_SLEEP:
+		ar5212SetPowerModeSleep(ah, setChip);
+		break;
+	case HAL_PM_NETWORK_SLEEP:
+		ar5212SetPowerModeNetworkSleep(ah, setChip);
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",
+		    __func__, mode);
+		return AH_FALSE;
+	}
+	ahp->ah_powerMode = mode;
+	return status;
+}
+
+/*
+ * Return the current sleep mode of the chip
+ */
+HAL_POWER_MODE
+ar5212GetPowerMode(struct ath_hal *ah)
+{
+	/* Just so happens the h/w maps directly to the abstracted value */
+	return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);
+}
+
+#if 0
+/*
+ * Return the current sleep state of the chip
+ * TRUE = sleeping
+ */
+HAL_BOOL
+ar5212GetPowerStatus(struct ath_hal *ah)
+{
+	return (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_SPWR_DN) != 0;
+}
+#endif
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_recv.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_recv.c
new file mode 100644
index 0000000..22bc112
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_recv.c
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_recv.c,v 1.4 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212desc.h"
+
+/*
+ * Get the RXDP.
+ */
+uint32_t
+ar5212GetRxDP(struct ath_hal *ath)
+{
+	return OS_REG_READ(ath, AR_RXDP);
+}
+
+/*
+ * Set the RxDP.
+ */
+void
+ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp)
+{
+	OS_REG_WRITE(ah, AR_RXDP, rxdp);
+	HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
+}
+
+/*
+ * Set Receive Enable bits.
+ */
+void
+ar5212EnableReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
+}
+
+/*
+ * Stop Receive at the DMA engine
+ */
+HAL_BOOL
+ar5212StopDmaReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);	/* Set receive disable bit */
+	if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
+			"AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
+			__func__,
+			OS_REG_READ(ah, AR_CR),
+			OS_REG_READ(ah, AR_DIAG_SW));
+#endif
+		return AH_FALSE;
+	} else {
+		return AH_TRUE;
+	}
+}
+
+/*
+ * Start Transmit at the PCU engine (unpause receive)
+ */
+void
+ar5212StartPcuReceive(struct ath_hal *ah)
+{
+	struct ath_hal_private *ahp = AH_PRIVATE(ah);
+
+	OS_REG_WRITE(ah, AR_DIAG_SW,
+		OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
+	ar5212EnableMibCounters(ah);
+	/* NB: restore current settings */
+	ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
+}
+
+/*
+ * Stop Transmit at the PCU engine (pause receive)
+ */
+void
+ar5212StopPcuReceive(struct ath_hal *ah)
+{
+	OS_REG_WRITE(ah, AR_DIAG_SW,
+		OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
+	ar5212DisableMibCounters(ah);
+}
+
+/*
+ * Set multicast filter 0 (lower 32-bits)
+ *               filter 1 (upper 32-bits)
+ */
+void
+ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
+{
+	OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
+	OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
+}
+
+/*
+ * Clear multicast filter by index
+ */
+HAL_BOOL
+ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
+{
+	uint32_t val;
+
+	if (ix >= 64)
+		return AH_FALSE;
+	if (ix >= 32) {
+		val = OS_REG_READ(ah, AR_MCAST_FIL1);
+		OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
+	} else {
+		val = OS_REG_READ(ah, AR_MCAST_FIL0);
+		OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Set multicast filter by index
+ */
+HAL_BOOL
+ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
+{
+	uint32_t val;
+
+	if (ix >= 64)
+		return AH_FALSE;
+	if (ix >= 32) {
+		val = OS_REG_READ(ah, AR_MCAST_FIL1);
+		OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
+	} else {
+		val = OS_REG_READ(ah, AR_MCAST_FIL0);
+		OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Get the receive filter.
+ */
+uint32_t
+ar5212GetRxFilter(struct ath_hal *ah)
+{
+	uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
+	uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
+	if (phybits & AR_PHY_ERR_RADAR)
+		bits |= HAL_RX_FILTER_PHYRADAR;
+	if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING))
+		bits |= HAL_RX_FILTER_PHYERR;
+	return bits;
+}
+
+/*
+ * Set the receive filter.
+ */
+void
+ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
+{
+	uint32_t phybits;
+
+	OS_REG_WRITE(ah, AR_RX_FILTER,
+	    bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR));
+	phybits = 0;
+	if (bits & HAL_RX_FILTER_PHYRADAR)
+		phybits |= AR_PHY_ERR_RADAR;
+	if (bits & HAL_RX_FILTER_PHYERR)
+		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
+	OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
+	if (phybits) {
+		OS_REG_WRITE(ah, AR_RXCFG,
+			OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
+	} else {
+		OS_REG_WRITE(ah, AR_RXCFG,
+			OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
+	}
+}
+
+/*
+ * Initialize RX descriptor, by clearing the status and setting
+ * the size (and any other flags).
+ */
+HAL_BOOL
+ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	uint32_t size, u_int flags)
+{
+	struct ar5212_desc *ads = AR5212DESC(ds);
+
+	HALASSERT((size &~ AR_BufLen) == 0);
+
+	ads->ds_ctl0 = 0;
+	ads->ds_ctl1 = size & AR_BufLen;
+
+	if (flags & HAL_RXDESC_INTREQ)
+		ads->ds_ctl1 |= AR_RxInterReq;
+	ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0;
+
+	return AH_TRUE;
+}
+
+/*
+ * Process an RX descriptor, and return the status to the caller.
+ * Copy some hardware specific items into the software portion
+ * of the descriptor.
+ *
+ * NB: the caller is responsible for validating the memory contents
+ *     of the descriptor (e.g. flushing any cached copy).
+ */
+HAL_STATUS
+ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	uint32_t pa, struct ath_desc *nds, uint64_t tsf,
+	struct ath_rx_status *rs)
+{
+	struct ar5212_desc *ads = AR5212DESC(ds);
+	struct ar5212_desc *ands = AR5212DESC(nds);
+
+	if ((ads->ds_rxstatus1 & AR_Done) == 0)
+		return HAL_EINPROGRESS;
+	/*
+	 * Given the use of a self-linked tail be very sure that the hw is
+	 * done with this descriptor; the hw may have done this descriptor
+	 * once and picked it up again...make sure the hw has moved on.
+	 */
+	if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
+		return HAL_EINPROGRESS;
+
+	rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen;
+	rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp);
+	rs->rs_status = 0;
+	/* XXX what about KeyCacheMiss? */
+	rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength);
+	/* discard invalid h/w rssi data */
+	if (rs->rs_rssi == -128)
+		rs->rs_rssi = 0;
+	if (ads->ds_rxstatus1 & AR_KeyIdxValid)
+		rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx);
+	else
+		rs->rs_keyix = HAL_RXKEYIX_INVALID;
+	/* NB: caller expected to do rate table mapping */
+	rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate);
+	rs->rs_antenna  = MS(ads->ds_rxstatus0, AR_RcvAntenna);
+	rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0;
+
+	if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) {
+		/*
+		 * These four bits should not be set together.  The
+		 * 5212 spec states a Michael error can only occur if
+		 * DecryptCRCErr not set (and TKIP is used).  Experience
+		 * indicates however that you can also get Michael errors
+		 * when a CRC error is detected, but these are specious.
+		 * Consequently we filter them out here so we don't
+		 * confuse and/or complicate drivers.
+		 */
+		if (ads->ds_rxstatus1 & AR_CRCErr)
+			rs->rs_status |= HAL_RXERR_CRC;
+		else if (ads->ds_rxstatus1 & AR_PHYErr) {
+			u_int phyerr;
+
+			rs->rs_status |= HAL_RXERR_PHY;
+			phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode);
+			rs->rs_phyerr = phyerr;
+			if (!AH5212(ah)->ah_hasHwPhyCounters &&
+			    phyerr != HAL_PHYERR_RADAR)
+				ar5212AniPhyErrReport(ah, rs);
+		} else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
+			rs->rs_status |= HAL_RXERR_DECRYPT;
+		else if (ads->ds_rxstatus1 & AR_MichaelErr)
+			rs->rs_status |= HAL_RXERR_MIC;
+	}
+	return HAL_OK;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_reset.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_reset.c
new file mode 100644
index 0000000..fcf5e72
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_reset.c
@@ -0,0 +1,2659 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_reset.c,v 1.20 2008/11/27 22:30:00 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#include "ah_eeprom_v3.h"
+
+/* Additional Time delay to wait after activiting the Base band */
+#define BASE_ACTIVATE_DELAY	100	/* 100 usec */
+#define PLL_SETTLE_DELAY	300	/* 300 usec */
+
+static HAL_BOOL ar5212SetResetReg(struct ath_hal *, uint32_t resetMask);
+/* NB: public for 5312 use */
+HAL_BOOL	ar5212IsSpurChannel(struct ath_hal *, HAL_CHANNEL *);
+HAL_BOOL	ar5212ChannelChange(struct ath_hal *, HAL_CHANNEL *);
+int16_t		ar5212GetNf(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+HAL_BOOL	ar5212SetBoardValues(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+void		ar5212SetDeltaSlope(struct ath_hal *, HAL_CHANNEL *);
+HAL_BOOL	ar5212SetTransmitPower(struct ath_hal *ah,
+		HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain);
+static HAL_BOOL ar5212SetRateTable(struct ath_hal *, 
+		   HAL_CHANNEL *, int16_t tpcScaleReduction, int16_t powerLimit,
+		   HAL_BOOL commit, int16_t *minPower, int16_t *maxPower);
+static void ar5212CorrectGainDelta(struct ath_hal *, int twiceOfdmCckDelta);
+static void ar5212GetTargetPowers(struct ath_hal *, HAL_CHANNEL *,
+		   const TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels,
+		   TRGT_POWER_INFO *pNewPower);
+static uint16_t ar5212GetMaxEdgePower(uint16_t channel,
+		   const RD_EDGES_POWER  *pRdEdgesPower);
+void		ar5212SetRateDurationTable(struct ath_hal *, HAL_CHANNEL *);
+void		ar5212SetIFSTiming(struct ath_hal *, HAL_CHANNEL *);
+
+/* NB: public for RF backend use */
+void		ar5212GetLowerUpperValues(uint16_t value,
+		   uint16_t *pList, uint16_t listSize,
+		   uint16_t *pLowerValue, uint16_t *pUpperValue);
+void		ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+		   uint32_t numBits, uint32_t firstBit, uint32_t column);
+
+static int
+write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+	HAL_BOOL bChannelChange, int writes)
+{
+#define IS_NO_RESET_TIMER_ADDR(x)                      \
+    ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \
+      (((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3)))
+#define	V(r, c)	(ia)->data[((r)*(ia)->cols) + (c)]
+	int r;
+
+	/* Write Common Array Parameters */
+	for (r = 0; r < ia->rows; r++) {
+		uint32_t reg = V(r, 0);
+		/* XXX timer/beacon setup registers? */
+		/* On channel change, don't reset the PCU registers */
+		if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) {
+			OS_REG_WRITE(ah, reg, V(r, 1));
+			DMA_YIELD(writes);
+		}
+	}
+	return writes;
+#undef IS_NO_RESET_TIMER_ADDR
+#undef V
+}
+
+#define IS_DISABLE_FAST_ADC_CHAN(x) (((x) == 2462) || ((x) == 2467))
+
+/*
+ * Places the device in and out of reset and then places sane
+ * values in the registers based on EEPROM config, initialization
+ * vectors (as determined by the mode), and station configuration
+ *
+ * bChannelChange is used to preserve DMA/PCU registers across
+ * a HW Reset during channel change.
+ */
+HAL_BOOL
+ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
+	HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+{
+#define	N(a)	(sizeof (a) / sizeof (a[0]))
+#define	FAIL(_code)	do { ecode = _code; goto bad; } while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *ichan = AH_NULL;
+	const HAL_EEPROM *ee;
+	uint32_t softLedCfg, softLedState;
+	uint32_t saveFrameSeqCount, saveDefAntenna, saveLedState;
+	uint32_t macStaId1, synthDelay, txFrm2TxDStart;
+	uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL];
+	int16_t cckOfdmPwrDelta = 0;
+	u_int modesIndex, freqIndex;
+	HAL_STATUS ecode;
+	int i, regWrites;
+	uint32_t testReg, powerVal;
+	int8_t twiceAntennaGain, twiceAntennaReduction;
+	uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow;
+	HAL_BOOL isBmode = AH_FALSE;
+	HAL_BOOL ichan_isBmode = AH_FALSE;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+	ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	OS_MARK(ah, AH_MARK_RESET, bChannelChange);
+#define	IS(_c,_f)	(((_c)->channelFlags & _f) || 0)
+	if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+	if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+#undef IS
+
+	/* Bring out of sleep mode */
+	if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n",
+		    __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/*
+	 * Map public channel to private.
+	 */
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+	switch (opmode) {
+	case HAL_M_STA:
+	case HAL_M_IBSS:
+	case HAL_M_HOSTAP:
+	case HAL_M_MONITOR:
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
+		    __func__, opmode);
+		FAIL(HAL_EINVAL);
+		break;
+	}
+	HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3);
+
+	SAVE_CCK(ah, ichan, ichan_isBmode);
+	SAVE_CCK(ah, chan, isBmode);
+
+	/* Preserve certain DMA hardware registers on a channel change */
+	if (bChannelChange) {
+		/*
+		 * On Venice, the TSF is almost preserved across a reset;
+		 * it requires doubling writes to the RESET_TSF
+		 * bit in the AR_BEACON register; it also has the quirk
+		 * of the TSF going back in time on the station (station
+		 * latches onto the last beacon's tsf during a reset 50%
+		 * of the times); the latter is not a problem for adhoc
+		 * stations since as long as the TSF is behind, it will
+		 * get resynchronized on receiving the next beacon; the
+		 * TSF going backwards in time could be a problem for the
+		 * sleep operation (supported on infrastructure stations
+		 * only) - the best and most general fix for this situation
+		 * is to resynchronize the various sleep/beacon timers on
+		 * the receipt of the next beacon i.e. when the TSF itself
+		 * gets resynchronized to the AP's TSF - power save is
+		 * needed to be temporarily disabled until that time
+		 *
+		 * Need to save the sequence number to restore it after
+		 * the reset!
+		 */
+		saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);
+	} else
+		saveFrameSeqCount = 0;		/* NB: silence compiler */
+#if 0
+	/*
+	 * XXX disable for now; this appears to sometimes cause OFDM
+	 * XXX timing error floods when ani is enabled and bg scanning
+	 * XXX kicks in
+	 */
+	/* If the channel change is across the same mode - perform a fast channel change */
+	if (IS_2413(ah) || IS_5413(ah)) {
+		/*
+		 * Fast channel change can only be used when:
+		 *  -channel change requested - so it's not the initial reset.
+		 *  -it's not a change to the current channel -
+		 *	often called when switching modes on a channel
+		 *  -the modes of the previous and requested channel are the
+		 *	same
+		 * XXX opmode shouldn't change either?
+		 */
+		if (bChannelChange &&
+		    (AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
+		    (chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) &&
+		    ((chan->channelFlags & CHANNEL_ALL) ==
+		     (AH_PRIVATE(ah)->ah_curchan->channelFlags & CHANNEL_ALL))) {
+			if (ar5212ChannelChange(ah, chan)) {
+				/* If ChannelChange completed - skip the rest of reset */
+				/* XXX ani? */
+				return AH_TRUE;
+			}
+		}
+	}
+#endif
+	/*
+	 * Preserve the antenna on a channel change
+	 */
+	saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
+	if (saveDefAntenna == 0)		/* XXX magic constants */
+		saveDefAntenna = 1;
+
+	/* Save hardware flag before chip reset clears the register */
+	macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 
+		(AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT);
+
+	/* Save led state from pci config register */
+	saveLedState = OS_REG_READ(ah, AR_PCICFG) &
+		(AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK |
+		 AR_PCICFG_LEDSLOW);
+	softLedCfg = OS_REG_READ(ah, AR_GPIOCR);
+	softLedState = OS_REG_READ(ah, AR_GPIODO);
+
+	ar5212RestoreClock(ah, opmode);		/* move to refclk operation */
+
+	/*
+	 * Adjust gain parameters before reset if
+	 * there's an outstanding gain updated.
+	 */
+	(void) ar5212GetRfgain(ah);
+
+	if (!ar5212ChipReset(ah, chan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Setup the indices for the next set of register array writes */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+		modesIndex = 1;
+		freqIndex  = 1;
+		break;
+	case CHANNEL_T:
+		modesIndex = 2;
+		freqIndex  = 1;
+		break;
+	case CHANNEL_B:
+		modesIndex = 3;
+		freqIndex  = 2;
+		break;
+	case CHANNEL_PUREG:
+		modesIndex = 4;
+		freqIndex  = 2;
+		break;
+	case CHANNEL_108G:
+		modesIndex = 5;
+		freqIndex  = 2;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	/* Set correct Baseband to analog shift setting to access analog chips. */
+	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
+	regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
+		regWrites);
+	ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) {
+		ar5212SetIFSTiming(ah, chan);
+		if (IS_5413(ah)) {
+			/*
+			 * Force window_length for 1/2 and 1/4 rate channels,
+			 * the ini file sets this to zero otherwise.
+			 */
+			OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
+				AR_PHY_FRAME_CTL_WINLEN, 3);
+		}
+	}
+
+	/* Overwrite INI values for revised chipsets */
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
+		/* ADC_CTL */
+		OS_REG_WRITE(ah, AR_PHY_ADC_CTL,
+			SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) |
+			SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) |
+			AR_PHY_ADC_CTL_OFF_PWDDAC |
+			AR_PHY_ADC_CTL_OFF_PWDADC);
+
+		/* TX_PWR_ADJ */
+		if (chan->channel == 2484) {
+			cckOfdmPwrDelta = SCALE_OC_DELTA(
+			    ee->ee_cckOfdmPwrDelta -
+			    ee->ee_scaledCh14FilterCckDelta);
+		} else {
+			cckOfdmPwrDelta = SCALE_OC_DELTA(
+			    ee->ee_cckOfdmPwrDelta);
+		}
+
+		if (IS_CHAN_G(chan)) {
+		    OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
+			SM((ee->ee_cckOfdmPwrDelta*-1),
+			    AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) |
+			SM((cckOfdmPwrDelta*-1),
+			    AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX));
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);
+		}
+
+		/* Add barker RSSI thresh enable as disabled */
+		OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK,
+			AR_PHY_DAG_CTRLCCK_EN_RSSI_THR);
+		OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
+			AR_PHY_DAG_CTRLCCK_RSSI_THR, 2);
+
+		/* Set the mute mask to the correct default */
+		OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
+	}
+
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
+		/* Clear reg to alllow RX_CLEAR line debug */
+		OS_REG_WRITE(ah, AR_PHY_BLUETOOTH,  0);
+	}
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
+#ifdef notyet
+		/* Enable burst prefetch for the data queues */
+		OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
+		/* Enable double-buffering */
+		OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
+#endif
+	}
+
+	/* Set ADC/DAC select values */
+	OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
+
+	if (IS_5413(ah) || IS_2417(ah)) {
+		uint32_t newReg=1;
+		if (IS_DISABLE_FAST_ADC_CHAN(chan->channel))
+			newReg = 0;
+		/* As it's a clock changing register, only write when the value needs to be changed */
+		if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg)
+			OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg);
+	}
+
+	/* Setup the transmit power values. */
+	if (!ar5212SetTransmitPower(ah, ichan, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error init'ing transmit power\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Write the analog registers */
+	if (!ahp->ah_rfHal->setRfRegs(ah, ichan, modesIndex, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",
+		    __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
+	if (IS_CHAN_OFDM(chan)) {
+		if ((IS_5413(ah) || (AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)) &&
+		    (!IS_CHAN_B(chan)))
+			ar5212SetSpurMitigation(ah, ichan);
+		ar5212SetDeltaSlope(ah, chan);
+	}
+
+	/* Setup board specific options for EEPROM version 3 */
+	if (!ar5212SetBoardValues(ah, ichan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error setting board options\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Restore certain DMA hardware registers on a channel change */
+	if (bChannelChange)
+		OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount);
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
+	OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
+		| macStaId1
+		| AR_STA_ID1_RTS_USE_DEF
+		| ahp->ah_staId1Defaults
+	);
+	ar5212SetOperatingMode(ah, opmode);
+
+	/* Set Venice BSSID mask according to current state */
+	OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
+	OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
+
+	/* Restore previous led state */
+	OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);
+
+	/* Restore soft Led state to GPIO */
+	OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg);
+	OS_REG_WRITE(ah, AR_GPIODO, softLedState);
+
+	/* Restore previous antenna */
+	OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
+
+	/* then our BSSID */
+	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
+	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
+
+	/* Restore bmiss rssi & count thresholds */
+	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
+
+	OS_REG_WRITE(ah, AR_ISR, ~0);		/* cleared on write */
+
+	if (!ar5212SetChannel(ah, ichan))
+		FAIL(HAL_EIO);
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
+
+	ar5212SetRateDurationTable(ah, chan);
+
+	/* Set Tx frame start to tx data start delay */
+	if (IS_RAD5112_ANY(ah) &&
+	    (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan) ||
+	     IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan))) {
+		txFrm2TxDStart = 
+			(IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) ?
+					TX_FRAME_D_START_HALF_RATE:
+					TX_FRAME_D_START_QUARTER_RATE;
+		OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, 
+			AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart);
+	}
+
+	/*
+	 * Setup fast diversity.
+	 * Fast diversity can be enabled or disabled via regadd.txt.
+	 * Default is enabled.
+	 * For reference,
+	 *    Disable: reg        val
+	 *             0x00009860 0x00009d18 (if 11a / 11g, else no change)
+	 *             0x00009970 0x192bb514
+	 *             0x0000a208 0xd03e4648
+	 *
+	 *    Enable:  0x00009860 0x00009d10 (if 11a / 11g, else no change)
+	 *             0x00009970 0x192fb514
+	 *             0x0000a208 0xd03e6788
+	 */
+
+	/* XXX Setup pre PHY ENABLE EAR additions */
+	/*
+	 * Wait for the frequency synth to settle (synth goes on
+	 * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
+	 * Value is in 100ns increments.
+	 */
+	synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
+	if (IS_CHAN_CCK(chan)) {
+		synthDelay = (4 * synthDelay) / 22;
+	} else {
+		synthDelay /= 10;
+	}
+
+	/* Activate the PHY (includes baseband activate and synthesizer on) */
+	OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+
+	/* 
+	 * There is an issue if the AP starts the calibration before
+	 * the base band timeout completes.  This could result in the
+	 * rx_clear false triggering.  As a workaround we add delay an
+	 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
+	 * does not happen.
+	 */
+	if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+		OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
+	} else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+		OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
+	} else {
+		OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
+	}
+
+	/*
+	 * The udelay method is not reliable with notebooks.
+	 * Need to check to see if the baseband is ready
+	 */
+	testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL);
+	/* Selects the Tx hold */
+	OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD);
+	i = 0;
+	while ((i++ < 20) &&
+	       (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */		OS_DELAY(200);
+	OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg);
+
+	/* Calibrate the AGC and start a NF calculation */
+	OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
+		  OS_REG_READ(ah, AR_PHY_AGC_CONTROL)
+		| AR_PHY_AGC_CONTROL_CAL
+		| AR_PHY_AGC_CONTROL_NF);
+
+	if (!IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) {
+		/* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
+		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 
+			AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
+			INIT_IQCAL_LOG_COUNT_MAX);
+		OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
+			AR_PHY_TIMING_CTRL4_DO_IQCAL);
+		ahp->ah_bIQCalibration = IQ_CAL_RUNNING;
+	} else
+		ahp->ah_bIQCalibration = IQ_CAL_INACTIVE;
+
+	/* Setup compression registers */
+	ar5212SetCompRegs(ah);
+
+	/* Set 1:1 QCU to DCU mapping for all queues */
+	for (i = 0; i < AR_NUM_DCU; i++)
+		OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
+
+	ahp->ah_intrTxqs = 0;
+	for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
+		ar5212ResetTxQueue(ah, i);
+
+	/*
+	 * Setup interrupt handling.  Note that ar5212ResetTxQueue
+	 * manipulates the secondary IMR's as queues are enabled
+	 * and disabled.  This is done with RMW ops to insure the
+	 * settings we make here are preserved.
+	 */
+	ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN
+			| AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN
+			| AR_IMR_HIUERR
+			;
+	if (opmode == HAL_M_HOSTAP)
+		ahp->ah_maskReg |= AR_IMR_MIB;
+	OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
+	/* Enable bus errors that are OR'd to set the HIUERR bit */
+	OS_REG_WRITE(ah, AR_IMR_S2,
+		OS_REG_READ(ah, AR_IMR_S2)
+		| AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR);
+
+	if (AH_PRIVATE(ah)->ah_rfkillEnabled)
+		ar5212EnableRfKill(ah);
+
+	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: offset calibration failed to complete in 1ms;"
+		    " noisy environment?\n", __func__);
+	}
+
+	/*
+	 * Set clocks back to 32kHz if they had been using refClk, then
+	 * use an external 32kHz crystal when sleeping, if one exists.
+	 */
+	ar5212SetupClock(ah, opmode);
+
+	/*
+	 * Writing to AR_BEACON will start timers. Hence it should
+	 * be the last register to be written. Do not reset tsf, do
+	 * not enable beacons at this point, but preserve other values
+	 * like beaconInterval.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON,
+		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
+
+	/* XXX Setup post reset EAR additions */
+
+	/* QoS support */
+	if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE ||
+	    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
+	     AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) {
+		OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa);	/* XXX magic */
+		OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210);	/* XXX magic */
+	}
+
+	/* Turn on NOACK Support for QoS packets */
+	OS_REG_WRITE(ah, AR_NOACK,
+		SM(2, AR_NOACK_2BIT_VALUE) |
+		SM(5, AR_NOACK_BIT_OFFSET) |
+		SM(0, AR_NOACK_BYTE_OFFSET));
+
+	/* Get Antenna Gain reduction */
+	if (IS_CHAN_5GHZ(chan)) {
+		ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain);
+	} else {
+		ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain);
+	}
+	twiceAntennaReduction =
+		ath_hal_getantennareduction(ah, chan, twiceAntennaGain);
+
+	/* TPC for self-generated frames */
+
+	ackTpcPow = MS(ahp->ah_macTPC, AR_TPC_ACK);
+	if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > ichan->maxTxPower)
+		ackTpcPow = ichan->maxTxPower+ahp->ah_txPowerIndexOffset;
+
+	if (ackTpcPow > (2*ichan->maxRegTxPower - twiceAntennaReduction))
+		ackTpcPow = (2*ichan->maxRegTxPower - twiceAntennaReduction)
+			+ ahp->ah_txPowerIndexOffset;
+
+	ctsTpcPow = MS(ahp->ah_macTPC, AR_TPC_CTS);
+	if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > ichan->maxTxPower)
+		ctsTpcPow = ichan->maxTxPower+ahp->ah_txPowerIndexOffset;
+
+	if (ctsTpcPow > (2*ichan->maxRegTxPower - twiceAntennaReduction))
+		ctsTpcPow = (2*ichan->maxRegTxPower - twiceAntennaReduction)
+			+ ahp->ah_txPowerIndexOffset;
+
+	chirpTpcPow = MS(ahp->ah_macTPC, AR_TPC_CHIRP);
+	if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > ichan->maxTxPower)
+		chirpTpcPow = ichan->maxTxPower+ahp->ah_txPowerIndexOffset;
+
+	if (chirpTpcPow > (2*ichan->maxRegTxPower - twiceAntennaReduction))
+		chirpTpcPow = (2*ichan->maxRegTxPower - twiceAntennaReduction)
+			+ ahp->ah_txPowerIndexOffset;
+
+	if (ackTpcPow > 63)
+		ackTpcPow = 63;
+	if (ctsTpcPow > 63)
+		ctsTpcPow = 63;
+	if (chirpTpcPow > 63)
+		chirpTpcPow = 63;
+
+	powerVal = SM(ackTpcPow, AR_TPC_ACK) |
+		SM(ctsTpcPow, AR_TPC_CTS) |
+		SM(chirpTpcPow, AR_TPC_CHIRP);
+
+	OS_REG_WRITE(ah, AR_TPC, powerVal);
+
+	/* Restore user-specified settings */
+	if (ahp->ah_miscMode != 0)
+		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+	if (ahp->ah_sifstime != (u_int) -1)
+		ar5212SetSifsTime(ah, ahp->ah_sifstime);
+	if (ahp->ah_slottime != (u_int) -1)
+		ar5212SetSlotTime(ah, ahp->ah_slottime);
+	if (ahp->ah_acktimeout != (u_int) -1)
+		ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
+	if (ahp->ah_ctstimeout != (u_int) -1)
+		ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
+	if (AH_PRIVATE(ah)->ah_diagreg != 0)
+		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
+
+	AH_PRIVATE(ah)->ah_opmode = opmode;	/* record operating mode */
+
+	if (bChannelChange) {
+		if (!(ichan->privFlags & CHANNEL_DFS)) 
+			ichan->privFlags &= ~CHANNEL_INTERFERENCE;
+		chan->channelFlags = ichan->channelFlags;
+		chan->privFlags = ichan->privFlags;
+		chan->maxRegTxPower = ichan->maxRegTxPower;
+		chan->maxTxPower = ichan->maxTxPower;
+		chan->minTxPower = ichan->minTxPower;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
+
+	RESTORE_CCK(ah, ichan, ichan_isBmode);
+	RESTORE_CCK(ah, chan, isBmode);
+	
+	OS_MARK(ah, AH_MARK_RESET_DONE, 0);
+
+	return AH_TRUE;
+bad:
+	if (ichan != AH_NULL)
+		RESTORE_CCK(ah, ichan, ichan_isBmode);
+	RESTORE_CCK(ah, chan, isBmode);
+
+	OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
+	if (*status)
+		*status = ecode;
+	return AH_FALSE;
+#undef FAIL
+#undef N
+}
+
+/*
+ * Call the rf backend to change the channel.
+ */
+HAL_BOOL
+ar5212SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	/* Change the synth */
+	if (!ahp->ah_rfHal->setChannel(ah, chan))
+		return AH_FALSE;
+	return AH_TRUE;
+}
+
+/*
+ * This channel change evaluates whether the selected hardware can
+ * perform a synthesizer-only channel change (no reset).  If the
+ * TX is not stopped, or the RFBus cannot be granted in the given
+ * time, the function returns false as a reset is necessary
+ */
+HAL_BOOL
+ar5212ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	uint32_t       ulCount;
+	uint32_t   data, synthDelay, qnum;
+	uint16_t   rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL];
+	HAL_BOOL    txStopped = AH_TRUE;
+	HAL_CHANNEL_INTERNAL *ichan;
+
+	/*
+	 * Map public channel to private.
+	 */
+	ichan = ath_hal_checkchannel(ah, chan);
+
+	/* TX must be stopped or RF Bus grant will not work */
+	for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {
+		if (ar5212NumTxPending(ah, qnum)) {
+			txStopped = AH_FALSE;
+			break;
+		}
+	}
+	if (!txStopped)
+		return AH_FALSE;
+
+	/* Kill last Baseband Rx Frame */
+	OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); /* Request analog bus grant */
+	for (ulCount = 0; ulCount < 100; ulCount++) {
+		if (OS_REG_READ(ah, AR_PHY_RFBUS_GNT))
+			break;
+		OS_DELAY(5);
+	}
+	if (ulCount >= 100)
+		return AH_FALSE;
+
+	/* Change the synth */
+	if (!ar5212SetChannel(ah, ichan))
+		return AH_FALSE;
+
+	/*
+	 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
+	 * Read the phy active delay register. Value is in 100ns increments.
+	 */
+	data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
+	if (IS_CHAN_CCK(ichan)) {
+		synthDelay = (4 * data) / 22;
+	} else {
+		synthDelay = data / 10;
+	}
+	OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
+
+	/* Setup the transmit power values. */
+	if (!ar5212SetTransmitPower(ah, ichan, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error init'ing transmit power\n", __func__);
+		return AH_FALSE;
+	}
+
+	/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
+	if (IS_CHAN_OFDM(ichan)) {
+		if ((IS_5413(ah) || (AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)) &&
+		    (!IS_CHAN_B(chan)))
+			ar5212SetSpurMitigation(ah, ichan);
+		ar5212SetDeltaSlope(ah, chan);
+	}
+
+	/* Release the RFBus Grant */
+	OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
+
+	/* Start Noise Floor Cal */
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+
+	if (!(ichan->privFlags & CHANNEL_DFS)) 
+		ichan->privFlags &= ~CHANNEL_INTERFERENCE;
+	chan->channelFlags = ichan->channelFlags;
+	chan->privFlags = ichan->privFlags;
+	chan->maxRegTxPower = ichan->maxRegTxPower;
+	chan->maxTxPower = ichan->maxTxPower;
+	chan->minTxPower = ichan->minTxPower;
+	return AH_TRUE;
+}
+
+void
+ar5212SetOperatingMode(struct ath_hal *ah, int opmode)
+{
+	uint32_t val;
+
+	val = OS_REG_READ(ah, AR_STA_ID1);
+	val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
+	switch (opmode) {
+	case HAL_M_HOSTAP:
+		OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
+					| AR_STA_ID1_KSRCH_MODE);
+		OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+		break;
+	case HAL_M_IBSS:
+		OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
+					| AR_STA_ID1_KSRCH_MODE);
+		OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+		break;
+	case HAL_M_STA:
+	case HAL_M_MONITOR:
+		OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
+		break;
+	}
+}
+
+/*
+ * Places the PHY and Radio chips into reset.  A full reset
+ * must be called to leave this state.  The PCI/MAC/PCU are
+ * not placed into reset as we must receive interrupt to
+ * re-enable the hardware.
+ */
+HAL_BOOL
+ar5212PhyDisable(struct ath_hal *ah)
+{
+	return ar5212SetResetReg(ah, AR_RC_BB);
+}
+
+/*
+ * Places all of hardware into reset
+ */
+HAL_BOOL
+ar5212Disable(struct ath_hal *ah)
+{
+	if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+	/*
+	 * Reset the HW - PCI must be reset after the rest of the
+	 * device has been reset.
+	 */
+	return ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI);
+}
+
+/*
+ * Places the hardware into reset and then pulls it out of reset
+ *
+ * TODO: Only write the PLL if we're changing to or from CCK mode
+ * 
+ * WARNING: The order of the PLL and mode registers must be correct.
+ */
+HAL_BOOL
+ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+
+	OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0);
+
+	/*
+	 * Reset the HW - PCI must be reset after the rest of the
+	 * device has been reset
+	 */
+	if (!ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI))
+		return AH_FALSE;
+
+	/* Bring out of sleep mode (AGAIN) */
+	if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+
+	/* Clear warm reset register */
+	if (!ar5212SetResetReg(ah, 0))
+		return AH_FALSE;
+
+	/*
+	 * Perform warm reset before the mode/PLL/turbo registers
+	 * are changed in order to deactivate the radio.  Mode changes
+	 * with an active radio can result in corrupted shifts to the
+	 * radio device.
+	 */
+
+	/*
+	 * Set CCK and Turbo modes correctly.
+	 */
+	if (chan != AH_NULL) {		/* NB: can be null during attach */
+		uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo;
+
+		if (IS_5413(ah)) {	/* NB: =>'s 5424 also */
+			rfMode = AR_PHY_MODE_AR5112;
+			if (IS_CHAN_HALF_RATE(chan))
+				rfMode |= AR_PHY_MODE_HALF;
+			else if (IS_CHAN_QUARTER_RATE(chan))
+				rfMode |= AR_PHY_MODE_QUARTER;
+
+			if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+				phyPLL = AR_PHY_PLL_CTL_44_5112;
+			else
+				phyPLL = AR_PHY_PLL_CTL_40_5413;
+		} else if (IS_RAD5111(ah)) {
+			rfMode = AR_PHY_MODE_AR5111;
+			if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+				phyPLL = AR_PHY_PLL_CTL_44;
+			else
+				phyPLL = AR_PHY_PLL_CTL_40;
+			if (IS_CHAN_HALF_RATE(chan))
+				phyPLL = AR_PHY_PLL_CTL_HALF;
+			else if (IS_CHAN_QUARTER_RATE(chan))
+				phyPLL = AR_PHY_PLL_CTL_QUARTER;
+		} else {		/* 5112, 2413, 2316, 2317 */
+			rfMode = AR_PHY_MODE_AR5112;
+			if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+				phyPLL = AR_PHY_PLL_CTL_44_5112;
+			else
+				phyPLL = AR_PHY_PLL_CTL_40_5112;
+			if (IS_CHAN_HALF_RATE(chan))
+				phyPLL |= AR_PHY_PLL_CTL_HALF;
+			else if (IS_CHAN_QUARTER_RATE(chan))
+				phyPLL |= AR_PHY_PLL_CTL_QUARTER;
+		}
+		if (IS_CHAN_OFDM(chan) && (IS_CHAN_CCK(chan) || 
+					   IS_CHAN_G(chan)))
+			rfMode |= AR_PHY_MODE_DYNAMIC;
+		else if (IS_CHAN_OFDM(chan))
+			rfMode |= AR_PHY_MODE_OFDM;
+		else
+			rfMode |= AR_PHY_MODE_CCK;
+		if (IS_CHAN_5GHZ(chan))
+			rfMode |= AR_PHY_MODE_RF5GHZ;
+		else
+			rfMode |= AR_PHY_MODE_RF2GHZ;
+		turbo = IS_CHAN_TURBO(chan) ?
+			(AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0;
+		curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);
+		/*
+		 * PLL, Mode, and Turbo values must be written in the correct
+		 * order to ensure:
+		 * - The PLL cannot be set to 44 unless the CCK or DYNAMIC
+		 *   mode bit is set
+		 * - Turbo cannot be set at the same time as CCK or DYNAMIC
+		 */
+		if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan)) {
+			OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
+			OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
+			if (curPhyPLL != phyPLL) {
+				OS_REG_WRITE(ah,  AR_PHY_PLL_CTL,  phyPLL);
+				/* Wait for the PLL to settle */
+				OS_DELAY(PLL_SETTLE_DELAY);
+			}
+		} else {
+			if (curPhyPLL != phyPLL) {
+				OS_REG_WRITE(ah,  AR_PHY_PLL_CTL,  phyPLL);
+				/* Wait for the PLL to settle */
+				OS_DELAY(PLL_SETTLE_DELAY);
+			}
+			OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
+			OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
+		}
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Recalibrate the lower PHY chips to account for temperature/environment
+ * changes.
+ */
+HAL_BOOL
+ar5212PerCalibrationN(struct ath_hal *ah,  HAL_CHANNEL *chan, u_int chainMask,
+	HAL_BOOL longCal, HAL_BOOL *isCalDone)
+{
+#define IQ_CAL_TRIES    10
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *ichan;
+	int32_t qCoff, qCoffDenom;
+	int32_t iqCorrMeas, iCoff, iCoffDenom;
+	uint32_t powerMeasQ, powerMeasI;
+	HAL_BOOL ichan_isBmode = AH_FALSE;
+	HAL_BOOL isBmode = AH_FALSE;
+
+	OS_MARK(ah, AH_MARK_PERCAL, chan->channel);
+	*isCalDone = AH_FALSE;
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		return AH_FALSE;
+	}
+	SAVE_CCK(ah, ichan, ichan_isBmode);
+	SAVE_CCK(ah, chan, isBmode);
+
+	if (ahp->ah_bIQCalibration == IQ_CAL_DONE ||
+	    ahp->ah_bIQCalibration == IQ_CAL_INACTIVE)
+		*isCalDone = AH_TRUE;
+
+	/* IQ calibration in progress. Check to see if it has finished. */
+	if (ahp->ah_bIQCalibration == IQ_CAL_RUNNING &&
+	    !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) {
+		int i;
+
+		/* IQ Calibration has finished. */
+		ahp->ah_bIQCalibration = IQ_CAL_INACTIVE;
+		*isCalDone = AH_TRUE;
+
+		/* workaround for misgated IQ Cal results */
+		i = 0;
+		do {
+			/* Read calibration results. */
+			powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I);
+			powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q);
+			iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS);
+			if (powerMeasI && powerMeasQ)
+				break;
+			/* Do we really need this??? */
+			OS_REG_WRITE (ah,  AR_PHY_TIMING_CTRL4,
+				      OS_REG_READ(ah,  AR_PHY_TIMING_CTRL4) |
+				      AR_PHY_TIMING_CTRL4_DO_IQCAL);
+		} while (++i < IQ_CAL_TRIES);
+
+		/*
+		 * Prescale these values to remove 64-bit operation
+		 * requirement at the loss of a little precision.
+		 */
+		iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
+		qCoffDenom = powerMeasQ / 128;
+
+		/* Protect against divide-by-0 and loss of sign bits. */
+		if (iCoffDenom != 0 && qCoffDenom >= 2) {
+			iCoff = (int8_t)(-iqCorrMeas) / iCoffDenom;
+			/* IQCORR_Q_I_COFF is a signed 6 bit number */
+			if (iCoff < -32) {
+				iCoff = -32;
+			} else if (iCoff > 31) {
+				iCoff = 31;
+			}
+
+			/* IQCORR_Q_Q_COFF is a signed 5 bit number */
+			qCoff = (powerMeasI / qCoffDenom) - 128;
+			if (qCoff < -16) {
+				qCoff = -16;
+			} else if (qCoff > 15) {
+				qCoff = 15;
+			}
+
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "****************** MISGATED IQ CAL! *******************\n");
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "time       = %d, i = %d, \n", OS_GETUPTIME(ah), i);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "powerMeasI = 0x%08x\n", powerMeasI);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "powerMeasQ = 0x%08x\n", powerMeasQ);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "iqCorrMeas = 0x%08x\n", iqCorrMeas);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "iCoff      = %d\n", iCoff);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "qCoff      = %d\n", qCoff);
+
+			/* Write values and enable correction */
+			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
+				AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff);
+			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
+				AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff);
+			OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 
+				AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
+
+			ahp->ah_bIQCalibration = IQ_CAL_DONE;
+			ichan->iqCalValid = AH_TRUE;
+			ichan->iCoff = iCoff;
+			ichan->qCoff = qCoff;
+		}
+	} else if (!IS_CHAN_B(chan) && ahp->ah_bIQCalibration == IQ_CAL_DONE &&
+	    !ichan->iqCalValid) {
+		/*
+		 * Start IQ calibration if configured channel has changed.
+		 * Use a magic number of 15 based on default value.
+		 */
+		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
+			AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
+			INIT_IQCAL_LOG_COUNT_MAX);
+		OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
+			AR_PHY_TIMING_CTRL4_DO_IQCAL);
+		ahp->ah_bIQCalibration = IQ_CAL_RUNNING;
+	}
+	/* XXX EAR */
+
+	if (longCal) {
+		/* Check noise floor results */
+		ar5212GetNf(ah, ichan);
+
+		if ((ichan->channelFlags & CHANNEL_CW_INT) == 0) {
+			/* Perform cal for 5Ghz channels and any OFDM on 5112 */
+			if (IS_CHAN_5GHZ(chan) ||
+			    (IS_RAD5112(ah) && IS_CHAN_OFDM(chan)))
+				ar5212RequestRfgain(ah);
+		} else {
+			/* report up and clear internal state */
+			chan->channelFlags |= CHANNEL_CW_INT;
+			ichan->channelFlags &= ~CHANNEL_CW_INT;
+		}
+	}
+	RESTORE_CCK(ah, ichan, ichan_isBmode);
+	RESTORE_CCK(ah, chan, isBmode);
+
+	return AH_TRUE;
+#undef IQ_CAL_TRIES
+}
+
+HAL_BOOL
+ar5212PerCalibration(struct ath_hal *ah,  HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
+{
+	return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
+}
+
+HAL_BOOL
+ar5212ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	/* XXX */
+	return AH_TRUE;
+}
+
+/*
+ * Write the given reset bit mask into the reset register
+ */
+static HAL_BOOL
+ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask)
+{
+	uint32_t mask = resetMask ? resetMask : ~0;
+	HAL_BOOL rt;
+
+	/* XXX ar5212MacStop & co. */
+
+	if (IS_PCIE(ah)) {
+		resetMask &= ~AR_RC_PCI;
+	}
+
+	(void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */
+	OS_REG_WRITE(ah, AR_RC, resetMask);
+	OS_DELAY(15);			/* need to wait at least 128 clocks
+					   when reseting PCI before read */
+	mask &= (AR_RC_MAC | AR_RC_BB);
+	resetMask &= (AR_RC_MAC | AR_RC_BB);
+	rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
+        if ((resetMask & AR_RC_MAC) == 0) {
+		if (isBigEndian()) {
+			/*
+			 * Set CFG, little-endian for register
+			 * and descriptor accesses.
+			 */
+			mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG;
+#ifndef AH_NEED_DESC_SWAP
+			mask |= AR_CFG_SWTD;
+#endif
+			OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
+		} else
+			OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
+		if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+			(void) OS_REG_READ(ah, AR_ISR_RAC);
+	}
+
+	/* track PHY power state so we don't try to r/w BB registers */
+	AH5212(ah)->ah_phyPowerOn = ((resetMask & AR_RC_BB) == 0);
+	return rt;
+}
+
+int16_t
+ar5212GetNoiseFloor(struct ath_hal *ah)
+{
+	int16_t nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
+	if (nf & 0x100)
+		nf = 0 - ((nf ^ 0x1ff) + 1);
+	return nf;
+}
+
+static HAL_BOOL
+getNoiseFloorThresh(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *chan,
+	int16_t *nft)
+{
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
+	case CHANNEL_A:
+		*nft = ee->ee_noiseFloorThresh[headerInfo11A];
+		break;
+	case CHANNEL_B:
+		*nft = ee->ee_noiseFloorThresh[headerInfo11B];
+		break;
+	case CHANNEL_PUREG:
+		*nft = ee->ee_noiseFloorThresh[headerInfo11G];
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Setup the noise floor cal history buffer.
+ */
+void 
+ar5212InitNfCalHistBuffer(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	int i;
+
+	ahp->ah_nfCalHist.first_run = 1;	
+	ahp->ah_nfCalHist.currIndex = 0;
+	ahp->ah_nfCalHist.privNF = AR5212_CCA_MAX_GOOD_VALUE;
+	ahp->ah_nfCalHist.invalidNFcount = AR512_NF_CAL_HIST_MAX;
+	for (i = 0; i < AR512_NF_CAL_HIST_MAX; i ++)
+		ahp->ah_nfCalHist.nfCalBuffer[i] = AR5212_CCA_MAX_GOOD_VALUE;
+}
+
+/*
+ * Add a noise floor value to the ring buffer.
+ */
+static __inline void
+updateNFHistBuff(struct ar5212NfCalHist *h, int16_t nf)
+{
+ 	h->nfCalBuffer[h->currIndex] = nf;
+     	if (++h->currIndex >= AR512_NF_CAL_HIST_MAX)
+		h->currIndex = 0;
+}	
+
+/*
+ * Return the median noise floor value in the ring buffer.
+ */
+int16_t 
+ar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX])
+{
+	int16_t sort[AR512_NF_CAL_HIST_MAX];
+	int i, j;
+
+	OS_MEMCPY(sort, calData, AR512_NF_CAL_HIST_MAX*sizeof(int16_t));
+	for (i = 0; i < AR512_NF_CAL_HIST_MAX-1; i ++) {
+		for (j = 1; j < AR512_NF_CAL_HIST_MAX-i; j ++) {
+			if (sort[j] > sort[j-1]) {
+				int16_t nf = sort[j];
+				sort[j] = sort[j-1];
+				sort[j-1] = nf;
+			}
+		}
+	}
+	return sort[(AR512_NF_CAL_HIST_MAX-1)>>1];
+}
+
+/*
+ * Read the NF and check it against the noise floor threshhold
+ */
+int16_t
+ar5212GetNf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212NfCalHist *h = &ahp->ah_nfCalHist;
+	int16_t nf, nfThresh;
+ 	int32_t val;
+
+	if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: NF did not complete in calibration window\n", __func__);
+		chan->rawNoiseFloor = h->privNF;	/* most recent value */
+		return chan->rawNoiseFloor;
+	}
+
+	/*
+	 * Finished NF cal, check against threshold.
+	 */
+	nf = ar5212GetNoiseFloor(ah);
+	if (getNoiseFloorThresh(ah, chan, &nfThresh)) {
+		if (nf > nfThresh) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: noise floor failed detected; detected %u, "
+			    "threshold %u\n", __func__, nf, nfThresh);
+			/*
+			 * NB: Don't discriminate 2.4 vs 5Ghz, if this
+			 *     happens it indicates a problem regardless
+			 *     of the band.
+			 */
+			chan->channelFlags |= CHANNEL_CW_INT;
+			nf = 0;
+		}
+	} else
+		nf = 0;
+
+	/*
+	 * Pass through histogram and write median value as
+	 * calculated from the accrued window.  We require a
+	 * full window of in-range values to be seen before we
+	 * start using the history.
+	 */
+	updateNFHistBuff(h, nf);
+	if (h->first_run) {
+		if (nf < AR5212_CCA_MIN_BAD_VALUE ||
+		    nf > AR5212_CCA_MAX_HIGH_VALUE) {
+			nf = AR5212_CCA_MAX_GOOD_VALUE;
+			h->invalidNFcount = AR512_NF_CAL_HIST_MAX;
+		} else if (--(h->invalidNFcount) == 0) {
+			h->first_run = 0;
+			h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer);
+		} else {
+			nf = AR5212_CCA_MAX_GOOD_VALUE;
+		}
+	} else {
+		h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer);
+	}
+
+	val = OS_REG_READ(ah, AR_PHY(25));
+	val &= 0xFFFFFE00;
+	val |= (((uint32_t)nf << 1) & 0x1FF);
+	OS_REG_WRITE(ah, AR_PHY(25), val);
+	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+
+	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n",
+		    __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
+#endif
+	}
+
+	/*
+	 * Now load a high maxCCAPower value again so that we're
+	 * not capped by the median we just loaded
+	 */
+	val &= 0xFFFFFE00;
+	val |= (((uint32_t)(-50) << 1) & 0x1FF);
+	OS_REG_WRITE(ah, AR_PHY(25), val);
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+
+	return (chan->rawNoiseFloor = nf);
+}
+
+/*
+ * Set up compression configuration registers
+ */
+void
+ar5212SetCompRegs(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	int i;
+
+        /* Check if h/w supports compression */
+	if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport)
+		return;
+
+	OS_REG_WRITE(ah, AR_DCCFG, 1);
+
+	OS_REG_WRITE(ah, AR_CCFG,
+		(AR_COMPRESSION_WINDOW_SIZE >> 8) & AR_CCFG_WIN_M);
+
+	OS_REG_WRITE(ah, AR_CCFG,
+		OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN);
+	OS_REG_WRITE(ah, AR_CCUCFG,
+		AR_CCUCFG_RESET_VAL | AR_CCUCFG_CATCHUP_EN);
+
+	OS_REG_WRITE(ah, AR_CPCOVF, 0);
+
+	/* reset decompression mask */
+	for (i = 0; i < HAL_DECOMP_MASK_SIZE; i++) {
+		OS_REG_WRITE(ah, AR_DCM_A, i);
+		OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]);
+	}
+}
+
+HAL_BOOL
+ar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings,
+	const HAL_CHANNEL_INTERNAL *chan)
+{
+#define	ANT_SWITCH_TABLE1	AR_PHY(88)
+#define	ANT_SWITCH_TABLE2	AR_PHY(89)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint32_t antSwitchA, antSwitchB;
+	int ix;
+	HAL_BOOL isBmode = AH_FALSE;
+	/* NB: need local copy for SAVE/RESTORE 'cuz chan is const */
+	HAL_CHANNEL_INTERNAL ichan = *chan;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+	HALASSERT(ahp->ah_phyPowerOn);
+
+	SAVE_CCK(ah, &ichan, isBmode);
+	switch (ichan.channelFlags & CHANNEL_ALL_NOTURBO) {
+	case CHANNEL_A:		ix = 0; break;
+	case CHANNEL_B:		ix = 1; break;
+	case CHANNEL_PUREG:	ix = 2; break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, ichan.channelFlags);
+		RESTORE_CCK(ah, &ichan, isBmode);
+		return AH_FALSE;
+	}
+	RESTORE_CCK(ah, &ichan, isBmode);
+
+	antSwitchA =  ee->ee_antennaControl[1][ix]
+		   | (ee->ee_antennaControl[2][ix] << 6)
+		   | (ee->ee_antennaControl[3][ix] << 12) 
+		   | (ee->ee_antennaControl[4][ix] << 18)
+		   | (ee->ee_antennaControl[5][ix] << 24)
+		   ;
+	antSwitchB =  ee->ee_antennaControl[6][ix]
+		   | (ee->ee_antennaControl[7][ix] << 6)
+		   | (ee->ee_antennaControl[8][ix] << 12)
+		   | (ee->ee_antennaControl[9][ix] << 18)
+		   | (ee->ee_antennaControl[10][ix] << 24)
+		   ;
+	/*
+	 * For fixed antenna, give the same setting for both switch banks
+	 */
+	switch (settings) {
+	case HAL_ANT_FIXED_A:
+		antSwitchB = antSwitchA;
+		break;
+	case HAL_ANT_FIXED_B:
+		antSwitchA = antSwitchB;
+		break;
+	case HAL_ANT_VARIABLE:
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n",
+		    __func__, settings);
+		return AH_FALSE;
+	}
+	if (antSwitchB == antSwitchA) {
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+		    "%s: Setting fast diversity off.\n", __func__);
+		OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT, 
+			       AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+		ahp->ah_diversity = AH_FALSE;
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+		    "%s: Setting fast diversity on.\n", __func__);
+		OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT, 
+			       AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+		ahp->ah_diversity = AH_TRUE;
+	}
+	ahp->ah_antControl = settings;
+
+	OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA);
+	OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB);
+
+	return AH_TRUE;
+#undef ANT_SWITCH_TABLE2
+#undef ANT_SWITCH_TABLE1
+}
+
+HAL_BOOL
+ar5212IsSpurChannel(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+    uint32_t clockFreq =
+	((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32);
+    return ( ((chan->channel % clockFreq) != 0)
+          && (((chan->channel % clockFreq) < 10)
+         || (((chan->channel) % clockFreq) > 22)) );
+}
+
+/*
+ * Read EEPROM header info and program the device for correct operation
+ * given the channel value.
+ */
+HAL_BOOL
+ar5212SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+#define NO_FALSE_DETECT_BACKOFF   2
+#define CB22_FALSE_DETECT_BACKOFF 6
+#define	AR_PHY_BIS(_ah, _reg, _mask, _val) \
+	OS_REG_WRITE(_ah, AR_PHY(_reg), \
+		(OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val));
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	int arrayMode, falseDectectBackoff;
+	int is2GHz = IS_CHAN_2GHZ(chan);
+	int8_t adcDesiredSize, pgaDesiredSize;
+	uint16_t switchSettling, txrxAtten, rxtxMargin;
+	int iCoff, qCoff;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+	case CHANNEL_T:
+		arrayMode = headerInfo11A;
+		if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah))
+			OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
+				AR_PHY_FRAME_CTL_TX_CLIP,
+				ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]);
+		break;
+	case CHANNEL_B:
+		arrayMode = headerInfo11B;
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		arrayMode = headerInfo11G;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/* Set the antenna register(s) correctly for the chip revision */
+	AR_PHY_BIS(ah, 68, 0xFFFFFC06,
+		(ee->ee_antennaControl[0][arrayMode] << 4) | 0x1);
+
+	ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan);
+
+	/* Set the Noise Floor Thresh on ar5211 devices */
+	OS_REG_WRITE(ah, AR_PHY(90),
+		(ee->ee_noiseFloorThresh[arrayMode] & 0x1FF)
+		| (1 << 9));
+
+	if (ee->ee_version >= AR_EEPROM_VER5_0 && IS_CHAN_TURBO(chan)) {
+		switchSettling = ee->ee_switchSettlingTurbo[is2GHz];
+		adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz];
+		pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz];
+		txrxAtten = ee->ee_txrxAttenTurbo[is2GHz];
+		rxtxMargin = ee->ee_rxtxMarginTurbo[is2GHz];
+	} else {
+		switchSettling = ee->ee_switchSettling[arrayMode];
+		adcDesiredSize = ee->ee_adcDesiredSize[arrayMode];
+		pgaDesiredSize = ee->ee_pgaDesiredSize[is2GHz];
+		txrxAtten = ee->ee_txrxAtten[is2GHz];
+		rxtxMargin = ee->ee_rxtxMargin[is2GHz];
+	}
+
+	OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 
+			 AR_PHY_SETTLING_SWITCH, switchSettling);
+	OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+			 AR_PHY_DESIRED_SZ_ADC, adcDesiredSize);
+	OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+			 AR_PHY_DESIRED_SZ_PGA, pgaDesiredSize);
+	OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
+			 AR_PHY_RXGAIN_TXRX_ATTEN, txrxAtten);
+	OS_REG_WRITE(ah, AR_PHY(13),
+		(ee->ee_txEndToXPAOff[arrayMode] << 24)
+		| (ee->ee_txEndToXPAOff[arrayMode] << 16)
+		| (ee->ee_txFrameToXPAOn[arrayMode] << 8)
+		| ee->ee_txFrameToXPAOn[arrayMode]);
+	AR_PHY_BIS(ah, 10, 0xFFFF00FF,
+		ee->ee_txEndToXLNAOn[arrayMode] << 8);
+	AR_PHY_BIS(ah, 25, 0xFFF80FFF,
+		(ee->ee_thresh62[arrayMode] << 12) & 0x7F000);
+
+	/*
+	 * False detect backoff - suspected 32 MHz spur causes false
+	 * detects in OFDM, causing Tx Hangs.  Decrease weak signal
+	 * sensitivity for this card.
+	 */
+	falseDectectBackoff = NO_FALSE_DETECT_BACKOFF;
+	if (ee->ee_version < AR_EEPROM_VER3_3) {
+		/* XXX magic number */
+		if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 &&
+		    IS_CHAN_OFDM(chan))
+			falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF;
+	} else {
+		if (ar5212IsSpurChannel(ah, (HAL_CHANNEL *)chan)) {
+			falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode];
+		}
+	}
+	AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE);
+
+	if (chan->iqCalValid) {
+		iCoff = chan->iCoff;
+		qCoff = chan->qCoff;
+	} else {
+		iCoff = ee->ee_iqCalI[is2GHz];
+		qCoff = ee->ee_iqCalQ[is2GHz];
+	}
+
+	/* write previous IQ results */
+	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
+		AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff);
+	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
+		AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff);
+	OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
+		AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
+
+	if (ee->ee_version >= AR_EEPROM_VER4_1) {
+		if (!IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0)
+			OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
+				AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin);
+	}
+	if (ee->ee_version >= AR_EEPROM_VER5_1) {
+		/* for now always disabled */
+		OS_REG_WRITE(ah,  AR_PHY_HEAVY_CLIP_ENABLE,  0);
+	}
+
+	return AH_TRUE;
+#undef AR_PHY_BIS
+#undef NO_FALSE_DETECT_BACKOFF
+#undef CB22_FALSE_DETECT_BACKOFF
+}
+
+/*
+ * Apply Spur Immunity to Boards that require it.
+ * Applies only to OFDM RX operation.
+ */
+
+void
+ar5212SetSpurMitigation(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
+{
+	uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0};
+	uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan;
+	int32_t spurDeltaPhase = 0, spurFreqSd = 0, spurOffset, binOffsetNumT16, curBinOffset;
+	int16_t numBinOffsets;
+	static const uint16_t magMapFor4[4] = {1, 2, 2, 1};
+	static const uint16_t magMapFor3[3] = {1, 2, 1};
+	const uint16_t *pMagMap;
+	HAL_BOOL is2GHz = IS_CHAN_2GHZ(ichan);
+	uint32_t val;
+
+#define CHAN_TO_SPUR(_f, _freq)   ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 )
+	if (IS_2417(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n",
+		    __func__);
+		return;
+	}
+
+	curChanAsSpur = CHAN_TO_SPUR(is2GHz, ichan->channel);
+
+	if (ichan->mainSpur) {
+		/* Pull out the saved spur value */
+		finalSpur = ichan->mainSpur;
+	} else {
+		/*
+		 * Check if spur immunity should be performed for this channel
+		 * Should only be performed once per channel and then saved
+		 */
+		finalSpur = AR_NO_SPUR;
+		spurDetectWidth = HAL_SPUR_CHAN_WIDTH;
+		if (IS_CHAN_TURBO(ichan))
+			spurDetectWidth *= 2;
+
+		/* Decide if any spur affects the current channel */
+		for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+			spurChan = ath_hal_getSpurChan(ah, i, is2GHz);
+			if (spurChan == AR_NO_SPUR) {
+				break;
+			}
+			if ((curChanAsSpur - spurDetectWidth <= (spurChan & HAL_SPUR_VAL_MASK)) &&
+			    (curChanAsSpur + spurDetectWidth >= (spurChan & HAL_SPUR_VAL_MASK))) {
+				finalSpur = spurChan & HAL_SPUR_VAL_MASK;
+				break;
+			}
+		}
+		/* Save detected spur (or no spur) for this channel */
+		ichan->mainSpur = finalSpur;
+	}
+
+	/* Write spur immunity data */
+	if (finalSpur == AR_NO_SPUR) {
+		/* Disable Spur Immunity Regs if they appear set */
+		if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) {
+			/* Clear Spur Delta Phase, Spur Freq, and enable bits */
+			OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0);
+			val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);
+			val &= ~(AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+				 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
+				 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+			OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val);
+			OS_REG_WRITE(ah, AR_PHY_TIMING11, 0);
+
+			/* Clear pilot masks */
+			OS_REG_WRITE(ah, AR_PHY_TIMING7, 0);
+			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0);
+			OS_REG_WRITE(ah, AR_PHY_TIMING9, 0);
+			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0);
+
+			/* Clear magnitude masks */
+			OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0);
+			OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0);
+			OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0);
+			OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0);
+			OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, 0);
+			OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, 0);
+			OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, 0);
+			OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0);
+		}
+	} else {
+		spurOffset = finalSpur - curChanAsSpur;
+		/*
+		 * Spur calculations:
+		 * spurDeltaPhase is (spurOffsetIn100KHz / chipFrequencyIn100KHz) << 21
+		 * spurFreqSd is (spurOffsetIn100KHz / sampleFrequencyIn100KHz) << 11
+		 */
+		switch (ichan->channelFlags & CHANNEL_ALL) {
+		case CHANNEL_A: /* Chip Frequency & sampleFrequency are 40 MHz */
+			spurDeltaPhase = (spurOffset << 17) / 25;
+			spurFreqSd = spurDeltaPhase >> 10;
+			binWidth = HAL_BIN_WIDTH_BASE_100HZ;
+			break;
+		case CHANNEL_G: /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */
+			spurFreqSd = (spurOffset << 8) / 55;
+			spurDeltaPhase = (spurOffset << 17) / 25;
+			binWidth = HAL_BIN_WIDTH_BASE_100HZ;
+			break;
+		case CHANNEL_T: /* Chip Frequency & sampleFrequency are 80 MHz */
+		case CHANNEL_108G:
+			spurDeltaPhase = (spurOffset << 16) / 25;
+			spurFreqSd = spurDeltaPhase >> 10;
+			binWidth = HAL_BIN_WIDTH_TURBO_100HZ;
+			break;
+		}
+
+		/* Compute Pilot Mask */
+		binOffsetNumT16 = ((spurOffset * 1000) << 4) / binWidth;
+		/* The spur is on a bin if it's remainder at times 16 is 0 */
+		if (binOffsetNumT16 & 0xF) {
+			numBinOffsets = 4;
+			pMagMap = magMapFor4;
+		} else {
+			numBinOffsets = 3;
+			pMagMap = magMapFor3;
+		}
+		for (i = 0; i < numBinOffsets; i++) {
+			if ((binOffsetNumT16 >> 4) > HAL_MAX_BINS_ALLOWED) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+				    "Too man bins in spur mitigation\n");
+				return;
+			}
+
+			/* Get Pilot Mask values */
+			curBinOffset = (binOffsetNumT16 >> 4) + i + 25;
+			if ((curBinOffset >= 0) && (curBinOffset <= 32)) {
+				if (curBinOffset <= 25)
+					pilotMask[0] |= 1 << curBinOffset;
+				else if (curBinOffset >= 27)
+					pilotMask[0] |= 1 << (curBinOffset - 1);
+			} else if ((curBinOffset >= 33) && (curBinOffset <= 52))
+				pilotMask[1] |= 1 << (curBinOffset - 33);
+
+			/* Get viterbi values */
+			if ((curBinOffset >= -1) && (curBinOffset <= 14))
+				binMagMask[0] |= pMagMap[i] << (curBinOffset + 1) * 2;
+			else if ((curBinOffset >= 15) && (curBinOffset <= 30))
+				binMagMask[1] |= pMagMap[i] << (curBinOffset - 15) * 2;
+			else if ((curBinOffset >= 31) && (curBinOffset <= 46))
+				binMagMask[2] |= pMagMap[i] << (curBinOffset -31) * 2;
+			else if((curBinOffset >= 47) && (curBinOffset <= 53))
+				binMagMask[3] |= pMagMap[i] << (curBinOffset -47) * 2;
+		}
+
+		/* Write Spur Delta Phase, Spur Freq, and enable bits */
+		OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF);
+		val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4);
+		val |= (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+			AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 
+			AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+		OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val);
+		OS_REG_WRITE(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_IN_AGC |		
+			     SM(spurFreqSd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
+			     SM(spurDeltaPhase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
+
+		/* Write pilot masks */
+		OS_REG_WRITE(ah, AR_PHY_TIMING7, pilotMask[0]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]);
+		OS_REG_WRITE(ah, AR_PHY_TIMING9, pilotMask[0]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]);
+
+		/* Write magnitude masks */
+		OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, binMagMask[0]);
+		OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, binMagMask[1]);
+		OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, binMagMask[2]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]);
+		OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, binMagMask[0]);
+		OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, binMagMask[1]);
+		OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, binMagMask[2]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]);
+	}
+#undef CHAN_TO_SPUR
+}
+
+
+/*
+ * Delta slope coefficient computation.
+ * Required for OFDM operation.
+ */
+void
+ar5212SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+#define COEF_SCALE_S 24
+#define INIT_CLOCKMHZSCALED	0x64000000
+	unsigned long coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man;
+	unsigned long clockMhzScaled = INIT_CLOCKMHZSCALED;
+
+	if (IS_CHAN_TURBO(chan))
+		clockMhzScaled *= 2;
+	/* half and quarter rate can divide the scaled clock by 2 or 4 respectively */
+	/* scale for selected channel bandwidth */ 
+	if (IS_CHAN_HALF_RATE(chan)) {
+		clockMhzScaled = clockMhzScaled >> 1;
+	} else if (IS_CHAN_QUARTER_RATE(chan)) {
+		clockMhzScaled = clockMhzScaled >> 2;
+	} 
+
+	/*
+	 * ALGO -> coef = 1e8/fcarrier*fclock/40;
+	 * scaled coef to provide precision for this floating calculation 
+	 */
+	coef_scaled = clockMhzScaled / chan->channel;
+
+	/*
+	 * ALGO -> coef_exp = 14-floor(log2(coef)); 
+	 * floor(log2(x)) is the highest set bit position
+	 */
+	for (coef_exp = 31; coef_exp > 0; coef_exp--)
+		if ((coef_scaled >> coef_exp) & 0x1)
+			break;
+	/* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */
+	HALASSERT(coef_exp);
+	coef_exp = 14 - (coef_exp - COEF_SCALE_S);
+
+	/*
+	 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5);
+	 * The coefficient is already shifted up for scaling
+	 */
+	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
+	ds_coef_man = coef_man >> (COEF_SCALE_S - coef_exp);
+	ds_coef_exp = coef_exp - 16;
+
+	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
+		AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
+	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
+		AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
+#undef INIT_CLOCKMHZSCALED
+#undef COEF_SCALE_S
+}
+
+/*
+ * Set a limit on the overall output power.  Used for dynamic
+ * transmit power control and the like.
+ *
+ * NB: limit is in units of 0.5 dbM.
+ */
+HAL_BOOL
+ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
+{
+	uint16_t dummyXpdGains[2];
+	HAL_BOOL ret, isBmode = AH_FALSE;
+
+	SAVE_CCK(ah, AH_PRIVATE(ah)->ah_curchan, isBmode);
+	AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
+	ret = ar5212SetTransmitPower(ah, AH_PRIVATE(ah)->ah_curchan,
+			dummyXpdGains);
+	RESTORE_CCK(ah, AH_PRIVATE(ah)->ah_curchan, isBmode);
+	return ret;
+}
+
+/*
+ * Set the transmit power in the baseband for the given
+ * operating channel and mode.
+ */
+HAL_BOOL
+ar5212SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+	uint16_t *rfXpdGain)
+{
+#define	POW_OFDM(_r, _s)	(((0 & 1)<< ((_s)+6)) | (((_r) & 0x3f) << (_s)))
+#define	POW_CCK(_r, _s)		(((_r) & 0x3f) << (_s))
+#define	N(a)			(sizeof (a) / sizeof (a[0]))
+	static const uint16_t tpcScaleReductionTable[5] =
+		{ 0, 3, 6, 9, MAX_RATE_POWER };
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	int16_t minPower, maxPower, tpcInDb, powerLimit;
+	int i;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	OS_MEMZERO(ahp->ah_pcdacTable, ahp->ah_pcdacTableSize);
+	OS_MEMZERO(ahp->ah_ratesArray, sizeof(ahp->ah_ratesArray));
+
+	powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
+	if (powerLimit >= MAX_RATE_POWER || powerLimit == 0)
+		tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
+	else
+		tpcInDb = 0;
+	if (!ar5212SetRateTable(ah, (HAL_CHANNEL *) chan, tpcInDb, powerLimit,
+				AH_TRUE, &minPower, &maxPower)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n",
+		    __func__);
+		return AH_FALSE;
+	}
+	if (!ahp->ah_rfHal->setPowerTable(ah,
+		&minPower, &maxPower, chan, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
+		    __func__);
+		return AH_FALSE;
+	}
+
+	/* 
+	 * Adjust XR power/rate up by 2 dB to account for greater peak
+	 * to avg ratio - except in newer avg power designs
+	 */
+	if (!IS_2413(ah) && !IS_5413(ah))
+		ahp->ah_ratesArray[15] += 4;
+	/* 
+	 * txPowerIndexOffset is set by the SetPowerTable() call -
+	 *  adjust the rate table 
+	 */
+	for (i = 0; i < N(ahp->ah_ratesArray); i++) {
+		ahp->ah_ratesArray[i] += ahp->ah_txPowerIndexOffset;
+		if (ahp->ah_ratesArray[i] > 63) 
+			ahp->ah_ratesArray[i] = 63;
+	}
+
+	if (ee->ee_eepMap < 2) {
+		/* 
+		 * Correct gain deltas for 5212 G operation -
+		 * Removed with revised chipset
+		 */
+		if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 &&
+		    IS_CHAN_G(chan)) {
+			uint16_t cckOfdmPwrDelta;
+
+			if (chan->channel == 2484) 
+				cckOfdmPwrDelta = SCALE_OC_DELTA(
+					ee->ee_cckOfdmPwrDelta - 
+					ee->ee_scaledCh14FilterCckDelta);
+			else 
+				cckOfdmPwrDelta = SCALE_OC_DELTA(
+					ee->ee_cckOfdmPwrDelta);
+			ar5212CorrectGainDelta(ah, cckOfdmPwrDelta);
+		}
+		/* 
+		 * Finally, write the power values into the
+		 * baseband power table
+		 */
+		for (i = 0; i < (PWR_TABLE_SIZE/2); i++) {
+			OS_REG_WRITE(ah, AR_PHY_PCDAC_TX_POWER(i),
+				 ((((ahp->ah_pcdacTable[2*i + 1] << 8) | 0xff) & 0xffff) << 16)
+				| (((ahp->ah_pcdacTable[2*i]     << 8) | 0xff) & 0xffff)
+			);
+		}
+	}
+
+	/* Write the OFDM power per rate set */
+	OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 
+		POW_OFDM(ahp->ah_ratesArray[3], 24)
+	      | POW_OFDM(ahp->ah_ratesArray[2], 16)
+	      | POW_OFDM(ahp->ah_ratesArray[1],  8)
+	      | POW_OFDM(ahp->ah_ratesArray[0],  0)
+	);
+	OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 
+		POW_OFDM(ahp->ah_ratesArray[7], 24)
+	      | POW_OFDM(ahp->ah_ratesArray[6], 16)
+	      | POW_OFDM(ahp->ah_ratesArray[5],  8)
+	      | POW_OFDM(ahp->ah_ratesArray[4],  0)
+	);
+
+	/* Write the CCK power per rate set */
+	OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
+		POW_CCK(ahp->ah_ratesArray[10], 24)
+	      | POW_CCK(ahp->ah_ratesArray[9],  16)
+	      | POW_CCK(ahp->ah_ratesArray[15],  8)	/* XR target power */
+	      | POW_CCK(ahp->ah_ratesArray[8],   0)
+	);
+	OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
+		POW_CCK(ahp->ah_ratesArray[14], 24)
+	      | POW_CCK(ahp->ah_ratesArray[13], 16)
+	      | POW_CCK(ahp->ah_ratesArray[12],  8)
+	      | POW_CCK(ahp->ah_ratesArray[11],  0)
+	);
+
+	/*
+	 * Set max power to 30 dBm and, optionally,
+	 * enable TPC in tx descriptors.
+	 */
+	OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER |
+		(ahp->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0));
+
+	return AH_TRUE;
+#undef N
+#undef POW_CCK
+#undef POW_OFDM
+}
+
+/*
+ * Sets the transmit power in the baseband for the given
+ * operating channel and mode.
+ */
+static HAL_BOOL
+ar5212SetRateTable(struct ath_hal *ah, HAL_CHANNEL *chan,
+		   int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit,
+                   int16_t *pMinPower, int16_t *pMaxPower)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t *rpow = ahp->ah_ratesArray;
+	uint16_t twiceMaxEdgePower = MAX_RATE_POWER;
+	uint16_t twiceMaxEdgePowerCck = MAX_RATE_POWER;
+	uint16_t twiceMaxRDPower = MAX_RATE_POWER;
+	int i;
+	uint8_t cfgCtl;
+	int8_t twiceAntennaGain, twiceAntennaReduction;
+	const RD_EDGES_POWER *rep;
+	TRGT_POWER_INFO targetPowerOfdm, targetPowerCck;
+	int16_t scaledPower, maxAvailPower = 0;
+	int16_t r13, r9, r7, r0;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	twiceMaxRDPower = chan->maxRegTxPower * 2;
+	*pMaxPower = -MAX_RATE_POWER;
+	*pMinPower = MAX_RATE_POWER;
+
+	/* Get conformance test limit maximum for this channel */
+	cfgCtl = ath_hal_getctl(ah, chan);
+	for (i = 0; i < ee->ee_numCtls; i++) {
+		uint16_t twiceMinEdgePower;
+
+		if (ee->ee_ctl[i] == 0)
+			continue;
+		if (ee->ee_ctl[i] == cfgCtl ||
+		    cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) {
+			rep = &ee->ee_rdEdgesPower[i * NUM_EDGES];
+			twiceMinEdgePower = ar5212GetMaxEdgePower(chan->channel, rep);
+			if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
+				/* Find the minimum of all CTL edge powers that apply to this channel */
+				twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
+			} else {
+				twiceMaxEdgePower = twiceMinEdgePower;
+				break;
+			}
+		}
+	}
+
+	if (IS_CHAN_G(chan)) {
+		/* Check for a CCK CTL for 11G CCK powers */
+		cfgCtl = (cfgCtl & ~CTL_MODE_M) | CTL_11B;
+		for (i = 0; i < ee->ee_numCtls; i++) {
+			uint16_t twiceMinEdgePowerCck;
+
+			if (ee->ee_ctl[i] == 0)
+				continue;
+			if (ee->ee_ctl[i] == cfgCtl ||
+			    cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) {
+				rep = &ee->ee_rdEdgesPower[i * NUM_EDGES];
+				twiceMinEdgePowerCck = ar5212GetMaxEdgePower(chan->channel, rep);
+				if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
+					/* Find the minimum of all CTL edge powers that apply to this channel */
+					twiceMaxEdgePowerCck = AH_MIN(twiceMaxEdgePowerCck, twiceMinEdgePowerCck);
+				} else {
+					twiceMaxEdgePowerCck = twiceMinEdgePowerCck;
+					break;
+				}
+			}
+		}
+	} else {
+		/* Set the 11B cck edge power to the one found before */
+		twiceMaxEdgePowerCck = twiceMaxEdgePower;
+	}
+
+	/* Get Antenna Gain reduction */
+	if (IS_CHAN_5GHZ(chan)) {
+		ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain);
+	} else {
+		ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain);
+	}
+	twiceAntennaReduction =
+		ath_hal_getantennareduction(ah, chan, twiceAntennaGain);
+
+	if (IS_CHAN_OFDM(chan)) {
+		/* Get final OFDM target powers */
+		if (IS_CHAN_2GHZ(chan)) { 
+			ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g,
+				ee->ee_numTargetPwr_11g, &targetPowerOfdm);
+		} else {
+			ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11a,
+				ee->ee_numTargetPwr_11a, &targetPowerOfdm);
+		}
+
+		/* Get Maximum OFDM power */
+		/* Minimum of target and edge powers */
+		scaledPower = AH_MIN(twiceMaxEdgePower,
+				twiceMaxRDPower - twiceAntennaReduction);
+
+		/*
+		 * If turbo is set, reduce power to keep power
+		 * consumption under 2 Watts.  Note that we always do
+		 * this unless specially configured.  Then we limit
+		 * power only for non-AP operation.
+		 */
+		if (IS_CHAN_TURBO(chan)
+#ifdef AH_ENABLE_AP_SUPPORT
+		    && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP
+#endif
+		) {
+			/*
+			 * If turbo is set, reduce power to keep power
+			 * consumption under 2 Watts
+			 */
+			if (ee->ee_version >= AR_EEPROM_VER3_1)
+				scaledPower = AH_MIN(scaledPower,
+					ee->ee_turbo2WMaxPower5);
+			/*
+			 * EEPROM version 4.0 added an additional
+			 * constraint on 2.4GHz channels.
+			 */
+			if (ee->ee_version >= AR_EEPROM_VER4_0 &&
+			    IS_CHAN_2GHZ(chan))
+				scaledPower = AH_MIN(scaledPower,
+					ee->ee_turbo2WMaxPower2);
+		}
+
+		maxAvailPower = AH_MIN(scaledPower,
+					targetPowerOfdm.twicePwr6_24);
+
+		/* Reduce power by max regulatory domain allowed restrictions */
+		scaledPower = maxAvailPower - (tpcScaleReduction * 2);
+		scaledPower = (scaledPower < 0) ? 0 : scaledPower;
+		scaledPower = AH_MIN(scaledPower, powerLimit);
+
+		if (commit) {
+			/* Set OFDM rates 9, 12, 18, 24 */
+			r0 = rpow[0] = rpow[1] = rpow[2] = rpow[3] = rpow[4] = scaledPower;
+
+			/* Set OFDM rates 36, 48, 54, XR */
+			rpow[5] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr36);
+			rpow[6] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr48);
+			r7 = rpow[7] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr54);
+
+			if (ee->ee_version >= AR_EEPROM_VER4_0) {
+				/* Setup XR target power from EEPROM */
+				rpow[15] = AH_MIN(scaledPower, IS_CHAN_2GHZ(chan) ?
+						  ee->ee_xrTargetPower2 : ee->ee_xrTargetPower5);
+			} else {
+				/* XR uses 6mb power */
+				rpow[15] = rpow[0];
+			}
+			ahp->ah_ofdmTxPower = *pMaxPower;
+
+		} else {
+			r0 = scaledPower;
+			r7 = AH_MIN(r0, targetPowerOfdm.twicePwr54);
+		}
+		*pMinPower = r7;
+		*pMaxPower = r0;
+
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+		    "%s: MaxRD: %d TurboMax: %d MaxCTL: %d "
+		    "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n",
+		    __func__, twiceMaxRDPower, ee->ee_turbo2WMaxPower5,
+		    twiceMaxEdgePower, tpcScaleReduction * 2,
+		    chan->channel, chan->channelFlags,
+		    maxAvailPower, targetPowerOfdm.twicePwr6_24, *pMaxPower);
+	}
+
+	if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan)) {
+		/* Get final CCK target powers */
+		ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b,
+			ee->ee_numTargetPwr_11b, &targetPowerCck);
+
+		/* Reduce power by max regulatory domain allowed restrictions */
+		scaledPower = AH_MIN(twiceMaxEdgePowerCck,
+			twiceMaxRDPower - twiceAntennaReduction);
+		if (maxAvailPower < AH_MIN(scaledPower, targetPowerCck.twicePwr6_24))
+			maxAvailPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24);
+
+		/* Reduce power by user selection */
+		scaledPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24) - (tpcScaleReduction * 2);
+		scaledPower = (scaledPower < 0) ? 0 : scaledPower;
+		scaledPower = AH_MIN(scaledPower, powerLimit);
+
+		if (commit) {
+			/* Set CCK rates 2L, 2S, 5.5L, 5.5S, 11L, 11S */
+			rpow[8]  = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24);
+			r9 = rpow[9]  = AH_MIN(scaledPower, targetPowerCck.twicePwr36);
+			rpow[10] = rpow[9];
+			rpow[11] = AH_MIN(scaledPower, targetPowerCck.twicePwr48);
+			rpow[12] = rpow[11];
+			r13 = rpow[13] = AH_MIN(scaledPower, targetPowerCck.twicePwr54);
+			rpow[14] = rpow[13];
+		} else {
+			r9 = AH_MIN(scaledPower, targetPowerCck.twicePwr36);
+			r13 = AH_MIN(scaledPower, targetPowerCck.twicePwr54);
+		}
+
+		/* Set min/max power based off OFDM values or initialization */
+		if (r13 < *pMinPower)
+			*pMinPower = r13;
+		if (r9 > *pMaxPower)
+			*pMaxPower = r9;
+
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+		    "%s: cck: MaxRD: %d MaxCTL: %d "
+		    "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n",
+		    __func__, twiceMaxRDPower, twiceMaxEdgePowerCck,
+		    tpcScaleReduction * 2, chan->channel, chan->channelFlags,
+		    maxAvailPower, targetPowerCck.twicePwr6_24, *pMaxPower);
+	}
+	if (commit) {
+		ahp->ah_tx6PowerInHalfDbm = *pMaxPower;
+		AH_PRIVATE(ah)->ah_maxPowerLevel = ahp->ah_tx6PowerInHalfDbm;
+	}
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5212GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	static const uint16_t tpcScaleReductionTable[5] =
+		{ 0, 3, 6, 9, MAX_RATE_POWER };
+	int16_t minPower, maxPower, tpcInDb, powerLimit;
+	HAL_CHANNEL *chan;
+	int i;
+
+	/*
+	 * Get Pier table max and min powers.
+	 */
+	for (i = 0; i < nchans; i++) {
+		chan = &chans[i];
+		if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {
+			/* NB: rf code returns 1/4 dBm units, convert */
+			chan->maxTxPower = maxPower / 2;
+			chan->minTxPower = minPower / 2;
+		} else {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: no min/max power for %u/0x%x\n",
+			    __func__, chan->channel, chan->channelFlags);
+			chan->maxTxPower = MAX_RATE_POWER;
+			chan->minTxPower = 0;
+		}
+	}
+	/*
+	 * Now adjust to reflect any global scale and/or CTL's.
+	 * (XXX is that correct?)
+	 */
+	powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
+	if (powerLimit >= MAX_RATE_POWER || powerLimit == 0)
+		tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
+	else
+		tpcInDb = 0;
+	for (i=0; i<nchans; i++) {
+		chan = &chans[i];
+		if (!ar5212SetRateTable(ah, (HAL_CHANNEL *) chan, tpcInDb, powerLimit,
+					AH_FALSE, &minPower, &maxPower)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: unable to find max/min power\n",__func__);
+			return AH_FALSE;
+		}
+		if (maxPower < chan->maxTxPower)
+			chan->maxTxPower = maxPower;
+		if (minPower < chan->minTxPower)
+			chan->minTxPower = minPower;
+	}
+#ifdef AH_DEBUG
+	for (i=0; i<nchans; i++) {
+		HALDEBUG(ah, HAL_DEBUG_RESET,
+		    "Chan %d: MaxPow = %d MinPow = %d\n",
+		    chans[i].channel,chans[i].maxTxPower, chans[i].minTxPower);
+	}
+#endif
+	return AH_TRUE;
+}
+
+/*
+ * Correct for the gain-delta between ofdm and cck mode target
+ * powers. Write the results to the rate table and the power table.
+ *
+ *   Conventions :
+ *   1. rpow[ii] is the integer value of 2*(desired power
+ *    for the rate ii in dBm) to provide 0.5dB resolution. rate
+ *    mapping is as following :
+ *     [0..7]  --> ofdm 6, 9, .. 48, 54
+ *     [8..14] --> cck 1L, 2L, 2S, .. 11L, 11S
+ *     [15]    --> XR (all rates get the same power)
+ *   2. powv[ii]  is the pcdac corresponding to ii/2 dBm.
+ */
+static void
+ar5212CorrectGainDelta(struct ath_hal *ah, int twiceOfdmCckDelta)
+{
+#define	N(_a)	(sizeof(_a) / sizeof(_a[0]))
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	int16_t ratesIndex[N(ahp->ah_ratesArray)];
+	uint16_t ii, jj, iter;
+	int32_t cckIndex;
+	int16_t gainDeltaAdjust;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	gainDeltaAdjust = ee->ee_cckOfdmGainDelta;
+
+	/* make a local copy of desired powers as initial indices */
+	OS_MEMCPY(ratesIndex, ahp->ah_ratesArray, sizeof(ratesIndex));
+
+	/* fix only the CCK indices */
+	for (ii = 8; ii < 15; ii++) {
+		/* apply a gain_delta correction of -15 for CCK */
+		ratesIndex[ii] -= gainDeltaAdjust;
+
+		/* Now check for contention with all ofdm target powers */
+		jj = 0;
+		iter = 0;
+		/* indicates not all ofdm rates checked forcontention yet */
+		while (jj < 16) {
+			if (ratesIndex[ii] < 0)
+				ratesIndex[ii] = 0;
+			if (jj == 8) {		/* skip CCK rates */
+				jj = 15;
+				continue;
+			}
+			if (ratesIndex[ii] == ahp->ah_ratesArray[jj]) {
+				if (ahp->ah_ratesArray[jj] == 0)
+					ratesIndex[ii]++;
+				else if (iter > 50) {
+					/*
+					 * To avoid pathological case of of
+					 * dm target powers 0 and 0.5dBm
+					 */
+					ratesIndex[ii]++;
+				} else
+					ratesIndex[ii]--;
+				/* check with all rates again */
+				jj = 0;
+				iter++;
+			} else
+				jj++;
+		}
+		if (ratesIndex[ii] >= PWR_TABLE_SIZE)
+			ratesIndex[ii] = PWR_TABLE_SIZE -1;
+		cckIndex = ahp->ah_ratesArray[ii] - twiceOfdmCckDelta;
+		if (cckIndex < 0)
+			cckIndex = 0;
+
+		/* 
+		 * Validate that the indexes for the powv are not
+		 * out of bounds.
+		 */
+		HALASSERT(cckIndex < PWR_TABLE_SIZE);
+		HALASSERT(ratesIndex[ii] < PWR_TABLE_SIZE);
+		ahp->ah_pcdacTable[ratesIndex[ii]] =
+			ahp->ah_pcdacTable[cckIndex];
+	}
+	/* Override rate per power table with new values */
+	for (ii = 8; ii < 15; ii++)
+		ahp->ah_ratesArray[ii] = ratesIndex[ii];
+#undef N
+}
+
+/*
+ * Find the maximum conformance test limit for the given channel and CTL info
+ */
+static uint16_t
+ar5212GetMaxEdgePower(uint16_t channel, const RD_EDGES_POWER *pRdEdgesPower)
+{
+	/* temp array for holding edge channels */
+	uint16_t tempChannelList[NUM_EDGES];
+	uint16_t clo, chi, twiceMaxEdgePower;
+	int i, numEdges;
+
+	/* Get the edge power */
+	for (i = 0; i < NUM_EDGES; i++) {
+		if (pRdEdgesPower[i].rdEdge == 0)
+			break;
+		tempChannelList[i] = pRdEdgesPower[i].rdEdge;
+	}
+	numEdges = i;
+
+	ar5212GetLowerUpperValues(channel, tempChannelList,
+		numEdges, &clo, &chi);
+	/* Get the index for the lower channel */
+	for (i = 0; i < numEdges && clo != tempChannelList[i]; i++)
+		;
+	/* Is lower channel ever outside the rdEdge? */
+	HALASSERT(i != numEdges);
+
+	if ((clo == chi && clo == channel) || (pRdEdgesPower[i].flag)) {
+		/* 
+		 * If there's an exact channel match or an inband flag set
+		 * on the lower channel use the given rdEdgePower 
+		 */
+		twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower;
+		HALASSERT(twiceMaxEdgePower > 0);
+	} else
+		twiceMaxEdgePower = MAX_RATE_POWER;
+	return twiceMaxEdgePower;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+static uint16_t
+interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+	uint16_t targetLeft, uint16_t targetRight)
+{
+	uint16_t rv;
+	int16_t lRatio;
+
+	/* to get an accurate ratio, always scale, if want to scale, then don't scale back down */
+	if ((targetLeft * targetRight) == 0)
+		return 0;
+
+	if (srcRight != srcLeft) {
+		/*
+		 * Note the ratio always need to be scaled,
+		 * since it will be a fraction.
+		 */
+		lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft);
+		if (lRatio < 0) {
+		    /* Return as Left target if value would be negative */
+		    rv = targetLeft;
+		} else if (lRatio > EEP_SCALE) {
+		    /* Return as Right target if Ratio is greater than 100% (SCALE) */
+		    rv = targetRight;
+		} else {
+			rv = (lRatio * targetRight + (EEP_SCALE - lRatio) *
+					targetLeft) / EEP_SCALE;
+		}
+	} else {
+		rv = targetLeft;
+	}
+	return rv;
+}
+
+/*
+ * Return the four rates of target power for the given target power table 
+ * channel, and number of channels
+ */
+static void
+ar5212GetTargetPowers(struct ath_hal *ah, HAL_CHANNEL *chan,
+	const TRGT_POWER_INFO *powInfo,
+	uint16_t numChannels, TRGT_POWER_INFO *pNewPower)
+{
+	/* temp array for holding target power channels */
+	uint16_t tempChannelList[NUM_TEST_FREQUENCIES];
+	uint16_t clo, chi, ixlo, ixhi;
+	int i;
+
+	/* Copy the target powers into the temp channel list */
+	for (i = 0; i < numChannels; i++)
+		tempChannelList[i] = powInfo[i].testChannel;
+
+	ar5212GetLowerUpperValues(chan->channel, tempChannelList,
+		numChannels, &clo, &chi);
+
+	/* Get the indices for the channel */
+	ixlo = ixhi = 0;
+	for (i = 0; i < numChannels; i++) {
+		if (clo == tempChannelList[i]) {
+			ixlo = i;
+		}
+		if (chi == tempChannelList[i]) {
+			ixhi = i;
+			break;
+		}
+	}
+
+	/*
+	 * Get the lower and upper channels, target powers,
+	 * and interpolate between them.
+	 */
+	pNewPower->twicePwr6_24 = interpolate(chan->channel, clo, chi,
+		powInfo[ixlo].twicePwr6_24, powInfo[ixhi].twicePwr6_24);
+	pNewPower->twicePwr36 = interpolate(chan->channel, clo, chi,
+		powInfo[ixlo].twicePwr36, powInfo[ixhi].twicePwr36);
+	pNewPower->twicePwr48 = interpolate(chan->channel, clo, chi,
+		powInfo[ixlo].twicePwr48, powInfo[ixhi].twicePwr48);
+	pNewPower->twicePwr54 = interpolate(chan->channel, clo, chi,
+		powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54);
+}
+
+/*
+ * Search a list for a specified value v that is within
+ * EEP_DELTA of the search values.  Return the closest
+ * values in the list above and below the desired value.
+ * EEP_DELTA is a factional value; everything is scaled
+ * so only integer arithmetic is used.
+ *
+ * NB: the input list is assumed to be sorted in ascending order
+ */
+void
+ar5212GetLowerUpperValues(uint16_t v, uint16_t *lp, uint16_t listSize,
+                          uint16_t *vlo, uint16_t *vhi)
+{
+	uint32_t target = v * EEP_SCALE;
+	uint16_t *ep = lp+listSize;
+
+	/*
+	 * Check first and last elements for out-of-bounds conditions.
+	 */
+	if (target < (uint32_t)(lp[0] * EEP_SCALE - EEP_DELTA)) {
+		*vlo = *vhi = lp[0];
+		return;
+	}
+	if (target > (uint32_t)(ep[-1] * EEP_SCALE + EEP_DELTA)) {
+		*vlo = *vhi = ep[-1];
+		return;
+	}
+
+	/* look for value being near or between 2 values in list */
+	for (; lp < ep; lp++) {
+		/*
+		 * If value is close to the current value of the list
+		 * then target is not between values, it is one of the values
+		 */
+		if (abs(lp[0] * EEP_SCALE - target) < EEP_DELTA) {
+			*vlo = *vhi = lp[0];
+			return;
+		}
+		/*
+		 * Look for value being between current value and next value
+		 * if so return these 2 values
+		 */
+		if (target < (uint32_t)(lp[1] * EEP_SCALE - EEP_DELTA)) {
+			*vlo = lp[0];
+			*vhi = lp[1];
+			return;
+		}
+	}
+	HALASSERT(AH_FALSE);		/* should not reach here */
+}
+
+/*
+ * Perform analog "swizzling" of parameters into their location
+ *
+ * NB: used by RF backends
+ */
+void
+ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits,
+                     uint32_t firstBit, uint32_t column)
+{
+#define	MAX_ANALOG_START	319		/* XXX */
+	uint32_t tmp32, mask, arrayEntry, lastBit;
+	int32_t bitPosition, bitsLeft;
+
+	HALASSERT(column <= 3);
+	HALASSERT(numBits <= 32);
+	HALASSERT(firstBit + numBits <= MAX_ANALOG_START);
+
+	tmp32 = ath_hal_reverseBits(reg32, numBits);
+	arrayEntry = (firstBit - 1) / 8;
+	bitPosition = (firstBit - 1) % 8;
+	bitsLeft = numBits;
+	while (bitsLeft > 0) {
+		lastBit = (bitPosition + bitsLeft > 8) ?
+			8 : bitPosition + bitsLeft;
+		mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
+			(column * 8);
+		rfBuf[arrayEntry] &= ~mask;
+		rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
+			(column * 8)) & mask;
+		bitsLeft -= 8 - bitPosition;
+		tmp32 = tmp32 >> (8 - bitPosition);
+		bitPosition = 0;
+		arrayEntry++;
+	}
+#undef MAX_ANALOG_START
+}
+
+/*
+ * Sets the rate to duration values in MAC - used for multi-
+ * rate retry.
+ * The rate duration table needs to cover all valid rate codes;
+ * the 11g table covers all ofdm rates, while the 11b table
+ * covers all cck rates => all valid rates get covered between
+ * these two mode's ratetables!
+ * But if we're turbo, the ofdm phy is replaced by the turbo phy
+ * and cck is not valid with turbo => all rates get covered
+ * by the turbo ratetable only
+ */
+void
+ar5212SetRateDurationTable(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	const HAL_RATE_TABLE *rt;
+	int i;
+
+	/* NB: band doesn't matter for 1/2 and 1/4 rate */
+	if (IS_CHAN_HALF_RATE(chan)) {
+		rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE);
+	} else if (IS_CHAN_QUARTER_RATE(chan)) {
+		rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE);
+	} else {
+		rt = ar5212GetRateTable(ah,
+			IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G);
+	}
+
+	for (i = 0; i < rt->rateCount; ++i)
+		OS_REG_WRITE(ah,
+			AR_RATE_DURATION(rt->info[i].rateCode),
+			ath_hal_computetxtime(ah, rt,
+				WLAN_CTRL_FRAME_SIZE,
+				rt->info[i].controlRate, AH_FALSE));
+	if (!IS_CHAN_TURBO(chan)) {
+		/* 11g Table is used to cover the CCK rates. */
+		rt = ar5212GetRateTable(ah, HAL_MODE_11G);
+		for (i = 0; i < rt->rateCount; ++i) {
+			uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode);
+
+			if (rt->info[i].phy != IEEE80211_T_CCK)
+				continue;
+
+			OS_REG_WRITE(ah, reg,
+				ath_hal_computetxtime(ah, rt,
+					WLAN_CTRL_FRAME_SIZE,
+					rt->info[i].controlRate, AH_FALSE));
+			/* cck rates have short preamble option also */
+			if (rt->info[i].shortPreamble) {
+				reg += rt->info[i].shortPreamble << 2;
+				OS_REG_WRITE(ah, reg,
+					ath_hal_computetxtime(ah, rt,
+						WLAN_CTRL_FRAME_SIZE,
+						rt->info[i].controlRate,
+						AH_TRUE));
+			}
+		}
+	}
+}
+
+/* Adjust various register settings based on half/quarter rate clock setting.
+ * This includes: +USEC, TX/RX latency, 
+ *                + IFS params: slot, eifs, misc etc.
+ */
+void 
+ar5212SetIFSTiming(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec;
+
+	HALASSERT(IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan));
+
+	refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32;
+	if (IS_CHAN_HALF_RATE(chan)) {
+		slot = IFS_SLOT_HALF_RATE;
+		rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S;
+		txLat = TX_HALF_RATE_LATENCY << AR5212_USEC_TX_LAT_S;
+		usec = HALF_RATE_USEC;
+		eifs = IFS_EIFS_HALF_RATE;
+		init_usec = INIT_USEC >> 1;
+	} else { /* quarter rate */
+		slot = IFS_SLOT_QUARTER_RATE;
+		rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S;
+		txLat = TX_QUARTER_RATE_LATENCY << AR5212_USEC_TX_LAT_S;
+		usec = QUARTER_RATE_USEC;
+		eifs = IFS_EIFS_QUARTER_RATE;
+		init_usec = INIT_USEC >> 2;
+	}
+
+	OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat));
+	OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
+	OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
+	OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC,
+				AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_rfgain.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_rfgain.c
new file mode 100644
index 0000000..8448ed7
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_rfgain.c
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_rfgain.c,v 1.2 2008/11/19 21:23:01 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#include "ah_eeprom_v3.h"
+
+static const GAIN_OPTIMIZATION_LADDER gainLadder = {
+	9,					/* numStepsInLadder */
+	4,					/* defaultStepNum */
+	{ { {4, 1, 1, 1},  6, "FG8"},
+	  { {4, 0, 1, 1},  4, "FG7"},
+	  { {3, 1, 1, 1},  3, "FG6"},
+	  { {4, 0, 0, 1},  1, "FG5"},
+	  { {4, 1, 1, 0},  0, "FG4"},	/* noJack */
+	  { {4, 0, 1, 0}, -2, "FG3"},	/* halfJack */
+	  { {3, 1, 1, 0}, -3, "FG2"},	/* clip3 */
+	  { {4, 0, 0, 0}, -4, "FG1"},	/* noJack */
+	  { {2, 1, 1, 0}, -6, "FG0"} 	/* clip2 */
+	}
+};
+
+static const GAIN_OPTIMIZATION_LADDER gainLadder5112 = {
+	8,					/* numStepsInLadder */
+	1,					/* defaultStepNum */
+	{ { {3, 0,0,0, 0,0,0},   6, "FG7"},	/* most fixed gain */
+	  { {2, 0,0,0, 0,0,0},   0, "FG6"},
+	  { {1, 0,0,0, 0,0,0},  -3, "FG5"},
+	  { {0, 0,0,0, 0,0,0},  -6, "FG4"},
+	  { {0, 1,1,0, 0,0,0},  -8, "FG3"},
+	  { {0, 1,1,0, 1,1,0}, -10, "FG2"},
+	  { {0, 1,0,1, 1,1,0}, -13, "FG1"},
+	  { {0, 1,0,1, 1,0,1}, -16, "FG0"},	/* least fixed gain */
+	}
+};
+
+/*
+ * Initialize the gain structure to good values
+ */
+void
+ar5212InitializeGainValues(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	GAIN_VALUES *gv = &ahp->ah_gainValues;
+
+	/* initialize gain optimization values */
+	if (IS_RAD5112_ANY(ah)) {
+		gv->currStepNum = gainLadder5112.defaultStepNum;
+		gv->currStep =
+			&gainLadder5112.optStep[gainLadder5112.defaultStepNum];
+		gv->active = AH_TRUE;
+		gv->loTrig = 20;
+		gv->hiTrig = 85;
+	} else {
+		gv->currStepNum = gainLadder.defaultStepNum;
+		gv->currStep = &gainLadder.optStep[gainLadder.defaultStepNum];
+		gv->active = AH_TRUE;
+		gv->loTrig = 20;
+		gv->hiTrig = 35;
+	}
+}
+
+#define	MAX_ANALOG_START	319		/* XXX */
+
+/*
+ * Find analog bits of given parameter data and return a reversed value
+ */
+static uint32_t
+ar5212GetRfField(uint32_t *rfBuf, uint32_t numBits, uint32_t firstBit, uint32_t column)
+{
+	uint32_t reg32 = 0, mask, arrayEntry, lastBit;
+	uint32_t bitPosition, bitsShifted;
+	int32_t bitsLeft;
+
+	HALASSERT(column <= 3);
+	HALASSERT(numBits <= 32);
+	HALASSERT(firstBit + numBits <= MAX_ANALOG_START);
+
+	arrayEntry = (firstBit - 1) / 8;
+	bitPosition = (firstBit - 1) % 8;
+	bitsLeft = numBits;
+	bitsShifted = 0;
+	while (bitsLeft > 0) {
+		lastBit = (bitPosition + bitsLeft > 8) ?
+			(8) : (bitPosition + bitsLeft);
+		mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
+			(column * 8);
+		reg32 |= (((rfBuf[arrayEntry] & mask) >> (column * 8)) >>
+			bitPosition) << bitsShifted;
+		bitsShifted += lastBit - bitPosition;
+		bitsLeft -= (8 - bitPosition);
+		bitPosition = 0;
+		arrayEntry++;
+	}
+	reg32 = ath_hal_reverseBits(reg32, numBits);
+	return reg32;
+}
+
+static HAL_BOOL
+ar5212InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv)
+{
+	uint32_t gStep, g, mixOvr;
+	uint32_t L1, L2, L3, L4;
+
+	if (IS_RAD5112_ANY(ah)) {
+		mixOvr = ar5212GetRfField(ar5212GetRfBank(ah, 7), 1, 36, 0);
+		L1 = 0;
+		L2 = 107;
+		L3 = 0;
+		L4 = 107;
+		if (mixOvr == 1) {
+			L2 = 83;
+			L4 = 83;
+			gv->hiTrig = 55;
+		}
+	} else {
+		gStep = ar5212GetRfField(ar5212GetRfBank(ah, 7), 6, 37, 0);
+
+		L1 = 0;
+		L2 = (gStep == 0x3f) ? 50 : gStep + 4;
+		L3 = (gStep != 0x3f) ? 0x40 : L1;
+		L4 = L3 + 50;
+
+		gv->loTrig = L1 + (gStep == 0x3f ? DYN_ADJ_LO_MARGIN : 0);
+		/* never adjust if != 0x3f */
+		gv->hiTrig = L4 - (gStep == 0x3f ? DYN_ADJ_UP_MARGIN : -5);
+	}
+	g = gv->currGain;
+
+	return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4));
+}
+
+/*
+ * Enable the probe gain check on the next packet
+ */
+void
+ar5212RequestRfgain(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	uint32_t probePowerIndex;
+
+	/* Enable the gain readback probe */
+	probePowerIndex = ahp->ah_ofdmTxPower + ahp->ah_txPowerIndexOffset;
+	OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE,
+		  SM(probePowerIndex, AR_PHY_PAPD_PROBE_POWERTX)
+		| AR_PHY_PAPD_PROBE_NEXT_TX);
+
+	ahp->ah_rfgainState = HAL_RFGAIN_READ_REQUESTED;
+}
+
+/*
+ * Check to see if our readback gain level sits within the linear
+ * region of our current variable attenuation window
+ */
+static HAL_BOOL
+ar5212IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv)
+{
+	return (gv->currGain <= gv->loTrig || gv->currGain >= gv->hiTrig);
+}
+
+/*
+ * Move the rabbit ears in the correct direction.
+ */
+static int32_t 
+ar5212AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv)
+{
+	const GAIN_OPTIMIZATION_LADDER *gl;
+
+	if (IS_RAD5112_ANY(ah))
+		gl = &gainLadder5112;
+	else
+		gl = &gainLadder;
+	gv->currStep = &gl->optStep[gv->currStepNum];
+	if (gv->currGain >= gv->hiTrig) {
+		if (gv->currStepNum == 0) {
+			HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Max gain limit.\n",
+			    __func__);
+			return -1;
+		}
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+		    "%s: Adding gain: currG=%d [%s] --> ",
+		    __func__, gv->currGain, gv->currStep->stepName);
+		gv->targetGain = gv->currGain;
+		while (gv->targetGain >= gv->hiTrig && gv->currStepNum > 0) {
+			gv->targetGain -= 2 * (gl->optStep[--(gv->currStepNum)].stepGain -
+				gv->currStep->stepGain);
+			gv->currStep = &gl->optStep[gv->currStepNum];
+		}
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
+		    gv->targetGain, gv->currStep->stepName);
+		return 1;
+	}
+	if (gv->currGain <= gv->loTrig) {
+		if (gv->currStepNum == gl->numStepsInLadder-1) {
+			HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+			    "%s: Min gain limit.\n", __func__);
+			return -2;
+		}
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+		    "%s: Deducting gain: currG=%d [%s] --> ",
+		    __func__, gv->currGain, gv->currStep->stepName);
+		gv->targetGain = gv->currGain;
+		while (gv->targetGain <= gv->loTrig &&
+		      gv->currStepNum < (gl->numStepsInLadder - 1)) {
+			gv->targetGain -= 2 *
+				(gl->optStep[++(gv->currStepNum)].stepGain - gv->currStep->stepGain);
+			gv->currStep = &gl->optStep[gv->currStepNum];
+		}
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n",
+		    gv->targetGain, gv->currStep->stepName);
+		return 2;
+	}
+	return 0;		/* caller didn't call needAdjGain first */
+}
+
+/*
+ * Read rf register to determine if gainF needs correction
+ */
+static void
+ar5212GetGainFCorrection(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	GAIN_VALUES *gv = &ahp->ah_gainValues;
+
+	HALASSERT(IS_RADX112_REV2(ah));
+
+	gv->gainFCorrection = 0;
+	if (ar5212GetRfField(ar5212GetRfBank(ah, 7), 1, 36, 0) == 1) {
+		uint32_t mixGain = gv->currStep->paramVal[0];
+		uint32_t gainStep =
+			ar5212GetRfField(ar5212GetRfBank(ah, 7), 4, 32, 0);
+		switch (mixGain) {
+		case 0 :
+			gv->gainFCorrection = 0;
+			break;
+		case 1 :
+			gv->gainFCorrection = gainStep;
+			break;
+		case 2 :
+			gv->gainFCorrection = 2 * gainStep - 5;
+			break;
+		case 3 :
+			gv->gainFCorrection = 2 * gainStep;
+			break;
+		}
+	}
+}
+
+/*
+ * Exported call to check for a recent gain reading and return
+ * the current state of the thermal calibration gain engine.
+ */
+HAL_RFGAIN
+ar5212GetRfgain(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	GAIN_VALUES *gv = &ahp->ah_gainValues;
+	uint32_t rddata, probeType;
+
+	if (!gv->active)
+		return HAL_RFGAIN_INACTIVE;
+
+	if (ahp->ah_rfgainState == HAL_RFGAIN_READ_REQUESTED) {
+		/* Caller had asked to setup a new reading. Check it. */
+		rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE);
+
+		if ((rddata & AR_PHY_PAPD_PROBE_NEXT_TX) == 0) {
+			/* bit got cleared, we have a new reading. */
+			gv->currGain = rddata >> AR_PHY_PAPD_PROBE_GAINF_S;
+			probeType = MS(rddata, AR_PHY_PAPD_PROBE_TYPE);
+			if (probeType == AR_PHY_PAPD_PROBE_TYPE_CCK) {
+				const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+
+				HALASSERT(IS_RAD5112_ANY(ah));
+				HALASSERT(ah->ah_magic == AR5212_MAGIC);
+				if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2)
+					gv->currGain += ee->ee_cckOfdmGainDelta;
+				else
+					gv->currGain += PHY_PROBE_CCK_CORRECTION;
+			}
+			if (IS_RADX112_REV2(ah)) {
+				ar5212GetGainFCorrection(ah);
+				if (gv->currGain >= gv->gainFCorrection)
+					gv->currGain -= gv->gainFCorrection;
+				else
+					gv->currGain = 0;
+			}
+			/* inactive by default */
+			ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+
+			if (!ar5212InvalidGainReadback(ah, gv) &&
+			    ar5212IsGainAdjustNeeded(ah, gv) &&
+			    ar5212AdjustGain(ah, gv) > 0) {
+				/*
+				 * Change needed. Copy ladder info
+				 * into eeprom info.
+				 */
+				ahp->ah_rfgainState = HAL_RFGAIN_NEED_CHANGE;
+				/* for ap51 */
+				ahp->ah_cwCalRequire = AH_TRUE;
+				/* Request IQ recalibration for temperature chang */
+				ahp->ah_bIQCalibration = IQ_CAL_INACTIVE;
+			}
+		}
+	}
+	return ahp->ah_rfgainState;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_xmit.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_xmit.c
new file mode 100644
index 0000000..8b4f85c
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212_xmit.c
@@ -0,0 +1,918 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212_xmit.c,v 1.7 2008/11/10 04:08:03 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212desc.h"
+#include "ar5212/ar5212phy.h"
+#ifdef AH_SUPPORT_5311
+#include "ar5212/ar5311reg.h"
+#endif
+
+#ifdef AH_NEED_DESC_SWAP
+static void ar5212SwapTxDesc(struct ath_desc *ds);
+#endif
+
+/*
+ * Update Tx FIFO trigger level.
+ *
+ * Set bIncTrigLevel to TRUE to increase the trigger level.
+ * Set bIncTrigLevel to FALSE to decrease the trigger level.
+ *
+ * Returns TRUE if the trigger level was updated
+ */
+HAL_BOOL
+ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	uint32_t txcfg, curLevel, newLevel;
+	HAL_INT omask;
+
+	/*
+	 * Disable interrupts while futzing with the fifo level.
+	 */
+	omask = ar5212SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
+
+	txcfg = OS_REG_READ(ah, AR_TXCFG);
+	curLevel = MS(txcfg, AR_FTRIG);
+	newLevel = curLevel;
+	if (bIncTrigLevel) {		/* increase the trigger level */
+		if (curLevel < MAX_TX_FIFO_THRESHOLD)
+			newLevel++;
+	} else if (curLevel > MIN_TX_FIFO_THRESHOLD)
+		newLevel--;
+	if (newLevel != curLevel)
+		/* Update the trigger level */
+		OS_REG_WRITE(ah, AR_TXCFG,
+			(txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
+
+	/* re-enable chip interrupts */
+	ar5212SetInterrupts(ah, omask);
+
+	return (newLevel != curLevel);
+}
+
+/*
+ * Set the properties of the tx queue with the parameters
+ * from qInfo.  
+ */
+HAL_BOOL
+ar5212SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+
+	if (q >= pCap->halTotalQueues) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);
+}
+
+/*
+ * Return the properties for the specified tx queue.
+ */
+HAL_BOOL
+ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+
+
+	if (q >= pCap->halTotalQueues) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);
+}
+
+/*
+ * Allocate and initialize a tx DCU/QCU combination.
+ */
+int
+ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
+	const HAL_TXQ_INFO *qInfo)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_TX_QUEUE_INFO *qi;
+	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+	int q, defqflags;
+
+	/* by default enable OK+ERR+DESC+URN interrupts */
+	defqflags = HAL_TXQ_TXOKINT_ENABLE
+		  | HAL_TXQ_TXERRINT_ENABLE
+		  | HAL_TXQ_TXDESCINT_ENABLE
+		  | HAL_TXQ_TXURNINT_ENABLE;
+	/* XXX move queue assignment to driver */
+	switch (type) {
+	case HAL_TX_QUEUE_BEACON:
+		q = pCap->halTotalQueues-1;	/* highest priority */
+		defqflags |= HAL_TXQ_DBA_GATED
+		       | HAL_TXQ_CBR_DIS_QEMPTY
+		       | HAL_TXQ_ARB_LOCKOUT_GLOBAL
+		       | HAL_TXQ_BACKOFF_DISABLE;
+		break;
+	case HAL_TX_QUEUE_CAB:
+		q = pCap->halTotalQueues-2;	/* next highest priority */
+		defqflags |= HAL_TXQ_DBA_GATED
+		       | HAL_TXQ_CBR_DIS_QEMPTY
+		       | HAL_TXQ_CBR_DIS_BEMPTY
+		       | HAL_TXQ_ARB_LOCKOUT_GLOBAL
+		       | HAL_TXQ_BACKOFF_DISABLE;
+		break;
+	case HAL_TX_QUEUE_UAPSD:
+		q = pCap->halTotalQueues-3;	/* nextest highest priority */
+		if (ahp->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: no available UAPSD tx queue\n", __func__);
+			return -1;
+		}
+		break;
+	case HAL_TX_QUEUE_DATA:
+		for (q = 0; q < pCap->halTotalQueues; q++)
+			if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE)
+				break;
+		if (q == pCap->halTotalQueues) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: no available tx queue\n", __func__);
+			return -1;
+		}
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: bad tx queue type %u\n", __func__, type);
+		return -1;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
+
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
+		    __func__, q);
+		return -1;
+	}
+	OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
+	qi->tqi_type = type;
+	if (qInfo == AH_NULL) {
+		qi->tqi_qflags = defqflags;
+		qi->tqi_aifs = INIT_AIFS;
+		qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;	/* NB: do at reset */
+		qi->tqi_cwmax = INIT_CWMAX;
+		qi->tqi_shretry = INIT_SH_RETRY;
+		qi->tqi_lgretry = INIT_LG_RETRY;
+		qi->tqi_physCompBuf = 0;
+	} else {
+		qi->tqi_physCompBuf = qInfo->tqi_compBuf;
+		(void) ar5212SetTxQueueProps(ah, q, qInfo);
+	}
+	/* NB: must be followed by ar5212ResetTxQueue */
+	return q;
+}
+
+/*
+ * Update the h/w interrupt registers to reflect a tx q's configuration.
+ */
+static void
+setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
+	    "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__,
+	    ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask,
+	    ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask,
+	    ahp->ah_txUrnInterruptMask);
+
+	OS_REG_WRITE(ah, AR_IMR_S0,
+		  SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
+		| SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
+	);
+	OS_REG_WRITE(ah, AR_IMR_S1,
+		  SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
+		| SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
+	);
+	OS_REG_RMW_FIELD(ah, AR_IMR_S2,
+		AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
+}
+
+/*
+ * Free a tx DCU/QCU combination.
+ */
+HAL_BOOL
+ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+	HAL_TX_QUEUE_INFO *qi;
+
+	if (q >= pCap->halTotalQueues) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);
+
+	qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
+	ahp->ah_txOkInterruptMask &= ~(1 << q);
+	ahp->ah_txErrInterruptMask &= ~(1 << q);
+	ahp->ah_txDescInterruptMask &= ~(1 << q);
+	ahp->ah_txEolInterruptMask &= ~(1 << q);
+	ahp->ah_txUrnInterruptMask &= ~(1 << q);
+	setTxQInterrupts(ah, qi);
+
+	return AH_TRUE;
+}
+
+/*
+ * Set the retry, aifs, cwmin/max, readyTime regs for specified queue
+ * Assumes:
+ *  phwChannel has been set to point to the current channel
+ */
+HAL_BOOL
+ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	HAL_TX_QUEUE_INFO *qi;
+	uint32_t cwMin, chanCwMin, value, qmisc, dmisc;
+
+	if (q >= pCap->halTotalQueues) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
+		    __func__, q);
+		return AH_FALSE;
+	}
+	qi = &ahp->ah_txq[q];
+	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
+		    __func__, q);
+		return AH_TRUE;		/* XXX??? */
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: reset queue %u\n", __func__, q);
+
+	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
+		/*
+		 * Select cwmin according to channel type.
+		 * NB: chan can be NULL during attach
+		 */
+		if (chan && IS_CHAN_B(chan))
+			chanCwMin = INIT_CWMIN_11B;
+		else
+			chanCwMin = INIT_CWMIN;
+		/* make sure that the CWmin is of the form (2^n - 1) */
+		for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
+			;
+	} else
+		cwMin = qi->tqi_cwmin;
+
+	/* set cwMin/Max and AIFS values */
+	OS_REG_WRITE(ah, AR_DLCL_IFS(q),
+		  SM(cwMin, AR_D_LCL_IFS_CWMIN)
+		| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
+		| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
+
+	/* Set retry limit values */
+	OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), 
+		   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
+		 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
+		 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
+		 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
+	);
+
+	/* NB: always enable early termination on the QCU */
+	qmisc = AR_Q_MISC_DCU_EARLY_TERM_REQ
+	      | SM(AR_Q_MISC_FSP_ASAP, AR_Q_MISC_FSP);
+
+	/* NB: always enable DCU to wait for next fragment from QCU */
+	dmisc = AR_D_MISC_FRAG_WAIT_EN;
+
+#ifdef AH_SUPPORT_5311
+	if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
+		/* Configure DCU to use the global sequence count */
+		dmisc |= AR5311_D_MISC_SEQ_NUM_CONTROL;
+	}
+#endif
+	/* multiqueue support */
+	if (qi->tqi_cbrPeriod) {
+		OS_REG_WRITE(ah, AR_QCBRCFG(q), 
+			  SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
+			| SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
+		qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_CBR;
+		if (qi->tqi_cbrOverflowLimit)
+			qmisc |= AR_Q_MISC_CBR_EXP_CNTR_LIMIT;
+	}
+	if (qi->tqi_readyTime) {
+		OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
+			  SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT)
+			| AR_Q_RDYTIMECFG_ENA);
+	}
+	
+	OS_REG_WRITE(ah, AR_DCHNTIME(q),
+		  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR)
+		| (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
+
+	if (qi->tqi_readyTime &&
+	    (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
+		qmisc |= AR_Q_MISC_RDYTIME_EXP_POLICY;
+	if (qi->tqi_qflags & HAL_TXQ_DBA_GATED)
+		qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_DBA_GATED;
+	if (MS(qmisc, AR_Q_MISC_FSP) != AR_Q_MISC_FSP_ASAP) {
+		/*
+		 * These are meangingful only when not scheduled asap.
+		 */
+		if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY)
+			qmisc |= AR_Q_MISC_CBR_INCR_DIS0;
+		else
+			qmisc &= ~AR_Q_MISC_CBR_INCR_DIS0;
+		if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY)
+			qmisc |= AR_Q_MISC_CBR_INCR_DIS1;
+		else
+			qmisc &= ~AR_Q_MISC_CBR_INCR_DIS1;
+	}
+
+	if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE)
+		dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS;
+	if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE)
+		dmisc |= AR_D_MISC_FRAG_BKOFF_EN;
+	if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL)
+		dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
+			    AR_D_MISC_ARB_LOCKOUT_CNTRL);
+	else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA)
+		dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR,
+			    AR_D_MISC_ARB_LOCKOUT_CNTRL);
+	if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL)
+		dmisc |= SM(AR_D_MISC_VIR_COL_HANDLING_IGNORE,
+			    AR_D_MISC_VIR_COL_HANDLING);
+	if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS)
+		dmisc |= AR_D_MISC_SEQ_NUM_INCR_DIS;
+
+	/*
+	 * Fillin type-dependent bits.  Most of this can be
+	 * removed by specifying the queue parameters in the
+	 * driver; it's here for backwards compatibility.
+	 */
+	switch (qi->tqi_type) {
+	case HAL_TX_QUEUE_BEACON:		/* beacon frames */
+		qmisc |= AR_Q_MISC_FSP_DBA_GATED
+		      |  AR_Q_MISC_BEACON_USE
+		      |  AR_Q_MISC_CBR_INCR_DIS1;
+
+		dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
+			    AR_D_MISC_ARB_LOCKOUT_CNTRL)
+		      |  AR_D_MISC_BEACON_USE
+		      |  AR_D_MISC_POST_FR_BKOFF_DIS;
+		break;
+	case HAL_TX_QUEUE_CAB:			/* CAB  frames */
+		/* 
+		 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY,
+		 * There is an issue with the CAB Queue
+		 * not properly refreshing the Tx descriptor if
+		 * the TXE clear setting is used.
+		 */
+		qmisc |= AR_Q_MISC_FSP_DBA_GATED
+		      |  AR_Q_MISC_CBR_INCR_DIS1
+		      |  AR_Q_MISC_CBR_INCR_DIS0;
+
+		if (!qi->tqi_readyTime) {
+			/*
+			 * NB: don't set default ready time if driver
+			 * has explicitly specified something.  This is
+			 * here solely for backwards compatibility.
+			 */
+			value = (ahp->ah_beaconInterval
+				- (ath_hal_sw_beacon_response_time -
+					ath_hal_dma_beacon_response_time)
+				- ath_hal_additional_swba_backoff) * 1024;
+			OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_ENA);
+		}
+		dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
+			    AR_D_MISC_ARB_LOCKOUT_CNTRL);
+		break;
+	default:			/* NB: silence compiler */
+		break;
+	}
+
+	OS_REG_WRITE(ah, AR_QMISC(q), qmisc);
+	OS_REG_WRITE(ah, AR_DMISC(q), dmisc);
+
+	/* Setup compression scratchpad buffer */
+	/* 
+	 * XXX: calling this asynchronously to queue operation can
+	 *      cause unexpected behavior!!!
+	 */
+	if (qi->tqi_physCompBuf) {
+		HALASSERT(qi->tqi_type == HAL_TX_QUEUE_DATA ||
+			  qi->tqi_type == HAL_TX_QUEUE_UAPSD);
+		OS_REG_WRITE(ah, AR_Q_CBBS, (80 + 2*q));
+		OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);
+		OS_REG_WRITE(ah, AR_Q_CBC,  HAL_COMP_BUF_MAX_SIZE/1024);
+		OS_REG_WRITE(ah, AR_Q0_MISC + 4*q,
+			     OS_REG_READ(ah, AR_Q0_MISC + 4*q)
+			     | AR_Q_MISC_QCU_COMP_EN);
+	}
+	
+	/*
+	 * Always update the secondary interrupt mask registers - this
+	 * could be a new queue getting enabled in a running system or
+	 * hw getting re-initialized during a reset!
+	 *
+	 * Since we don't differentiate between tx interrupts corresponding
+	 * to individual queues - secondary tx mask regs are always unmasked;
+	 * tx interrupts are enabled/disabled for all queues collectively
+	 * using the primary mask reg
+	 */
+	if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
+		ahp->ah_txOkInterruptMask |= 1 << q;
+	else
+		ahp->ah_txOkInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
+		ahp->ah_txErrInterruptMask |= 1 << q;
+	else
+		ahp->ah_txErrInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
+		ahp->ah_txDescInterruptMask |= 1 << q;
+	else
+		ahp->ah_txDescInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
+		ahp->ah_txEolInterruptMask |= 1 << q;
+	else
+		ahp->ah_txEolInterruptMask &= ~(1 << q);
+	if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
+		ahp->ah_txUrnInterruptMask |= 1 << q;
+	else
+		ahp->ah_txUrnInterruptMask &= ~(1 << q);
+	setTxQInterrupts(ah, qi);
+
+	return AH_TRUE;
+}
+
+/*
+ * Get the TXDP for the specified queue
+ */
+uint32_t
+ar5212GetTxDP(struct ath_hal *ah, u_int q)
+{
+	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
+	return OS_REG_READ(ah, AR_QTXDP(q));
+}
+
+/*
+ * Set the TxDP for the specified queue
+ */
+HAL_BOOL
+ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
+{
+	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
+	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	/*
+	 * Make sure that TXE is deasserted before setting the TXDP.  If TXE
+	 * is still asserted, setting TXDP will have no effect.
+	 */
+	HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
+
+	OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
+
+	return AH_TRUE;
+}
+
+/*
+ * Set Transmit Enable bits for the specified queue
+ */
+HAL_BOOL
+ar5212StartTxDma(struct ath_hal *ah, u_int q)
+{
+	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
+
+	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
+
+	/* Check to be sure we're not enabling a q that has its TXD bit set. */
+	HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
+
+	OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
+	return AH_TRUE;
+}
+
+/*
+ * Return the number of pending frames or 0 if the specified
+ * queue is stopped.
+ */
+uint32_t
+ar5212NumTxPending(struct ath_hal *ah, u_int q)
+{
+	uint32_t npend;
+
+	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
+	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
+	if (npend == 0) {
+		/*
+		 * Pending frame count (PFC) can momentarily go to zero
+		 * while TXE remains asserted.  In other words a PFC of
+		 * zero is not sufficient to say that the queue has stopped.
+		 */
+		if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
+			npend = 1;		/* arbitrarily return 1 */
+	}
+	return npend;
+}
+
+/*
+ * Stop transmit on the specified queue
+ */
+HAL_BOOL
+ar5212StopTxDma(struct ath_hal *ah, u_int q)
+{
+	u_int i;
+	u_int wait;
+
+	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
+
+	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
+	for (i = 1000; i != 0; i--) {
+		if (ar5212NumTxPending(ah, q) == 0)
+			break;
+		OS_DELAY(100);        /* XXX get actual value */
+	}
+#ifdef AH_DEBUG
+	if (i == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", __func__,
+		    OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),
+		    OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q)));
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
+		    __func__, OS_REG_READ(ah, AR_QMISC(q)),
+		    OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
+		    OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
+	}
+#endif /* AH_DEBUG */
+
+	/* 2413+ and up can kill packets at the PCU level */
+	if (ar5212NumTxPending(ah, q) &&
+	    (IS_2413(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))) {
+		uint32_t tsfLow, j;
+		
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
+		    "%s: Num of pending TX Frames %d on Q %d\n",
+		    __func__, ar5212NumTxPending(ah, q), q);
+		
+		/* Kill last PCU Tx Frame */
+		/* TODO - save off and restore current values of Q1/Q2? */
+		for (j = 0; j < 2; j++) {
+			tsfLow = OS_REG_READ(ah, AR_TSF_L32);
+			OS_REG_WRITE(ah, AR_QUIET2, SM(100, AR_QUIET2_QUIET_PER) |
+				     SM(10, AR_QUIET2_QUIET_DUR));
+			OS_REG_WRITE(ah, AR_QUIET1, AR_QUIET1_QUIET_ENABLE |
+				     SM(tsfLow >> 10, AR_QUIET1_NEXT_QUIET));
+			if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) {
+				break;
+			}
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: TSF moved while trying to set quiet time "
+			    "TSF: 0x%08x\n", __func__, tsfLow);
+			HALASSERT(j < 1); /* TSF shouldn't count twice or reg access is taking forever */
+		}
+		
+		OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
+		
+		/* Allow the quiet mechanism to do its work */
+		OS_DELAY(200);
+		OS_REG_CLR_BIT(ah, AR_QUIET1, AR_QUIET1_QUIET_ENABLE);
+		
+		/* Give at least 1 millisec more to wait */
+		wait = 100;
+		
+		/* Verify all transmit is dead */
+		while (ar5212NumTxPending(ah, q)) {
+			if ((--wait) == 0) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+				    "%s: Failed to stop Tx DMA in %d msec after killing last frame\n",
+				    __func__, wait);
+				break;
+			}
+			OS_DELAY(10);
+		}
+		
+		OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
+	}
+
+	OS_REG_WRITE(ah, AR_Q_TXD, 0);
+	return (i != 0);
+}
+
+/*
+ * Descriptor Access Functions
+ */
+
+#define	VALID_PKT_TYPES \
+	((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
+	 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
+	 (1<<HAL_PKT_TYPE_BEACON))
+#define	isValidPktType(_t)	((1<<(_t)) & VALID_PKT_TYPES)
+#define	VALID_TX_RATES \
+	((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
+	 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
+	 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
+#define	isValidTxRate(_r)	((1<<(_r)) & VALID_TX_RATES)
+
+HAL_BOOL
+ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int pktLen,
+	u_int hdrLen,
+	HAL_PKT_TYPE type,
+	u_int txPower,
+	u_int txRate0, u_int txTries0,
+	u_int keyIx,
+	u_int antMode,
+	u_int flags,
+	u_int rtsctsRate,
+	u_int rtsctsDuration,
+	u_int compicvLen,
+	u_int compivLen,
+	u_int comp)
+{
+#define	RTSCTS	(HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
+	struct ar5212_desc *ads = AR5212DESC(ds);
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	(void) hdrLen;
+
+	HALASSERT(txTries0 != 0);
+	HALASSERT(isValidPktType(type));
+	HALASSERT(isValidTxRate(txRate0));
+	HALASSERT((flags & RTSCTS) != RTSCTS);
+	/* XXX validate antMode */
+
+        txPower = (txPower + ahp->ah_txPowerIndexOffset );
+        if(txPower > 63)  txPower=63;
+
+	ads->ds_ctl0 = (pktLen & AR_FrameLen)
+		     | (txPower << AR_XmitPower_S)
+		     | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
+		     | (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
+		     | SM(antMode, AR_AntModeXmit)
+		     | (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
+		     ;
+	ads->ds_ctl1 = (type << AR_FrmType_S)
+		     | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
+                     | (comp << AR_CompProc_S)
+                     | (compicvLen << AR_CompICVLen_S)
+                     | (compivLen << AR_CompIVLen_S)
+                     ;
+	ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0)
+		     | (flags & HAL_TXDESC_DURENA ? AR_DurUpdateEna : 0)
+		     ;
+	ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S)
+		     ;
+	if (keyIx != HAL_TXKEYIX_INVALID) {
+		/* XXX validate key index */
+		ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
+		ads->ds_ctl0 |= AR_DestIdxValid;
+	}
+	if (flags & RTSCTS) {
+		if (!isValidTxRate(rtsctsRate)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: invalid rts/cts rate 0x%x\n",
+			    __func__, rtsctsRate);
+			return AH_FALSE;
+		}
+		/* XXX validate rtsctsDuration */
+		ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
+			     | (flags & HAL_TXDESC_RTSENA ? AR_RTSCTSEnable : 0)
+			     ;
+		ads->ds_ctl2 |= SM(rtsctsDuration, AR_RTSCTSDuration);
+		ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
+	}
+	return AH_TRUE;
+#undef RTSCTS
+}
+
+HAL_BOOL
+ar5212SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int txRate1, u_int txTries1,
+	u_int txRate2, u_int txTries2,
+	u_int txRate3, u_int txTries3)
+{
+	struct ar5212_desc *ads = AR5212DESC(ds);
+
+	if (txTries1) {
+		HALASSERT(isValidTxRate(txRate1));
+		ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1)
+			     |  AR_DurUpdateEna
+			     ;
+		ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
+	}
+	if (txTries2) {
+		HALASSERT(isValidTxRate(txRate2));
+		ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2)
+			     |  AR_DurUpdateEna
+			     ;
+		ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
+	}
+	if (txTries3) {
+		HALASSERT(isValidTxRate(txRate3));
+		ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3)
+			     |  AR_DurUpdateEna
+			     ;
+		ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
+	}
+	return AH_TRUE;
+}
+
+void
+ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
+{
+	struct ar5212_desc *ads = AR5212DESC(ds);
+
+#ifdef AH_NEED_DESC_SWAP
+	ads->ds_ctl0 |= __bswap32(AR_TxInterReq);
+#else
+	ads->ds_ctl0 |= AR_TxInterReq;
+#endif
+}
+
+HAL_BOOL
+ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
+	const struct ath_desc *ds0)
+{
+	struct ar5212_desc *ads = AR5212DESC(ds);
+
+	HALASSERT((segLen &~ AR_BufLen) == 0);
+
+	if (firstSeg) {
+		/*
+		 * First descriptor, don't clobber xmit control data
+		 * setup by ar5212SetupTxDesc.
+		 */
+		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
+	} else if (lastSeg) {		/* !firstSeg && lastSeg */
+		/*
+		 * Last descriptor in a multi-descriptor frame,
+		 * copy the multi-rate transmit parameters from
+		 * the first frame for processing on completion. 
+		 */
+		ads->ds_ctl0 = 0;
+		ads->ds_ctl1 = segLen;
+#ifdef AH_NEED_DESC_SWAP
+		ads->ds_ctl2 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl2);
+		ads->ds_ctl3 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl3);
+#else
+		ads->ds_ctl2 = AR5212DESC_CONST(ds0)->ds_ctl2;
+		ads->ds_ctl3 = AR5212DESC_CONST(ds0)->ds_ctl3;
+#endif
+	} else {			/* !firstSeg && !lastSeg */
+		/*
+		 * Intermediate descriptor in a multi-descriptor frame.
+		 */
+		ads->ds_ctl0 = 0;
+		ads->ds_ctl1 = segLen | AR_More;
+		ads->ds_ctl2 = 0;
+		ads->ds_ctl3 = 0;
+	}
+	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
+	return AH_TRUE;
+}
+
+#ifdef AH_NEED_DESC_SWAP
+/* Swap transmit descriptor */
+static __inline void
+ar5212SwapTxDesc(struct ath_desc *ds)
+{
+	ds->ds_data = __bswap32(ds->ds_data);
+        ds->ds_ctl0 = __bswap32(ds->ds_ctl0);
+        ds->ds_ctl1 = __bswap32(ds->ds_ctl1);
+        ds->ds_hw[0] = __bswap32(ds->ds_hw[0]);
+        ds->ds_hw[1] = __bswap32(ds->ds_hw[1]);
+        ds->ds_hw[2] = __bswap32(ds->ds_hw[2]);
+        ds->ds_hw[3] = __bswap32(ds->ds_hw[3]);
+}
+#endif
+
+/*
+ * Processing of HW TX descriptor.
+ */
+HAL_STATUS
+ar5212ProcTxDesc(struct ath_hal *ah,
+	struct ath_desc *ds, struct ath_tx_status *ts)
+{
+	struct ar5212_desc *ads = AR5212DESC(ds);
+
+#ifdef AH_NEED_DESC_SWAP
+	if ((ads->ds_txstatus1 & __bswap32(AR_Done)) == 0)
+                return HAL_EINPROGRESS;
+
+	ar5212SwapTxDesc(ds);
+#else
+	if ((ads->ds_txstatus1 & AR_Done) == 0)
+		return HAL_EINPROGRESS;
+#endif
+
+	/* Update software copies of the HW status */
+	ts->ts_seqnum = MS(ads->ds_txstatus1, AR_SeqNum);
+	ts->ts_tstamp = MS(ads->ds_txstatus0, AR_SendTimestamp);
+	ts->ts_status = 0;
+	if ((ads->ds_txstatus0 & AR_FrmXmitOK) == 0) {
+		if (ads->ds_txstatus0 & AR_ExcessiveRetries)
+			ts->ts_status |= HAL_TXERR_XRETRY;
+		if (ads->ds_txstatus0 & AR_Filtered)
+			ts->ts_status |= HAL_TXERR_FILT;
+		if (ads->ds_txstatus0 & AR_FIFOUnderrun)
+			ts->ts_status |= HAL_TXERR_FIFO;
+	}
+	/*
+	 * Extract the transmit rate used and mark the rate as
+	 * ``alternate'' if it wasn't the series 0 rate.
+	 */
+	ts->ts_finaltsi = MS(ads->ds_txstatus1, AR_FinalTSIndex);
+	switch (ts->ts_finaltsi) {
+	case 0:
+		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
+		break;
+	case 1:
+		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1) |
+			HAL_TXSTAT_ALTRATE;
+		break;
+	case 2:
+		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2) |
+			HAL_TXSTAT_ALTRATE;
+		break;
+	case 3:
+		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3) |
+			HAL_TXSTAT_ALTRATE;
+		break;
+	}
+	ts->ts_rssi = MS(ads->ds_txstatus1, AR_AckSigStrength);
+	ts->ts_shortretry = MS(ads->ds_txstatus0, AR_RTSFailCnt);
+	ts->ts_longretry = MS(ads->ds_txstatus0, AR_DataFailCnt);
+	/*
+	 * The retry count has the number of un-acked tries for the
+	 * final series used.  When doing multi-rate retry we must
+	 * fixup the retry count by adding in the try counts for
+	 * each series that was fully-processed.  Beware that this
+	 * takes values from the try counts in the final descriptor.
+	 * These are not required by the hardware.  We assume they
+	 * are placed there by the driver as otherwise we have no
+	 * access and the driver can't do the calculation because it
+	 * doesn't know the descriptor format.
+	 */
+	switch (ts->ts_finaltsi) {
+	case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2);
+	case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1);
+	case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0);
+	}
+	ts->ts_virtcol = MS(ads->ds_txstatus0, AR_VirtCollCnt);
+	ts->ts_antenna = (ads->ds_txstatus1 & AR_XmitAtenna ? 2 : 1);
+
+	return HAL_OK;
+}
+
+/*
+ * Determine which tx queues need interrupt servicing.
+ */
+void
+ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	*txqs &= ahp->ah_intrTxqs;
+	ahp->ah_intrTxqs &= ~(*txqs);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212desc.h b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212desc.h
new file mode 100644
index 0000000..9885c9f
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212desc.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212desc.h,v 1.4 2008/11/10 04:08:03 sam Exp $
+ */
+#ifndef _ATH_AR5212_DESC_H_
+#define _ATH_AR5212_DESC_H_
+
+/*
+ * Hardware-specific descriptor structures.
+ */
+#include "ah_desc.h"
+
+/*
+ * AR5212-specific tx/rx descriptor definition.
+ */
+struct ar5212_desc {
+	uint32_t	ds_link;	/* link pointer */
+	uint32_t	ds_data;	/* data buffer pointer */
+	uint32_t	ds_ctl0;	/* DMA control 0 */
+	uint32_t	ds_ctl1;	/* DMA control 1 */
+	union {
+		struct {		/* xmit format */
+			uint32_t	ctl2;	/* DMA control 2 */
+			uint32_t	ctl3;	/* DMA control 3 */
+			uint32_t	status0;/* DMA status 0 */
+			uint32_t	status1;/* DMA status 1 */
+		} tx;
+		struct {		/* recv format */
+			uint32_t	status0;/* DMA status 0 */
+			uint32_t	status1;/* DMA status 1 */
+		} rx;
+	} u;
+} __packed;
+#define	AR5212DESC(_ds)	((struct ar5212_desc *)(_ds))
+#define	AR5212DESC_CONST(_ds)	((const struct ar5212_desc *)(_ds))
+
+#define	ds_ctl2		u.tx.ctl2
+#define	ds_ctl3		u.tx.ctl3
+#define	ds_txstatus0	u.tx.status0
+#define	ds_txstatus1	u.tx.status1
+#define	ds_rxstatus0	u.rx.status0
+#define	ds_rxstatus1	u.rx.status1
+
+/* TX ds_ctl0 */
+#define	AR_FrameLen		0x00000fff	/* frame length */
+/* bits 12-15 are reserved */
+#define	AR_XmitPower		0x003f0000	/* transmit power control */
+#define	AR_XmitPower_S		16
+#define	AR_RTSCTSEnable		0x00400000	/* RTS/CTS protocol enable */
+#define	AR_VEOL			0x00800000	/* virtual end-of-list */
+#define	AR_ClearDestMask	0x01000000	/* Clear destination mask bit */
+#define	AR_AntModeXmit		0x1e000000	/* TX antenna seslection */
+#define	AR_AntModeXmit_S	25
+#define	AR_TxInterReq		0x20000000	/* TX interrupt request */
+#define	AR_DestIdxValid		0x40000000	/* destination index valid */
+#define	AR_CTSEnable		0x80000000	/* precede frame with CTS */
+
+/* TX ds_ctl1 */
+#define	AR_BufLen		0x00000fff	/* data buffer length */
+#define	AR_More			0x00001000	/* more desc in this frame */
+#define	AR_DestIdx		0x000fe000	/* destination table index */
+#define	AR_DestIdx_S		13
+#define	AR_FrmType		0x00f00000	/* frame type indication */
+#define	AR_FrmType_S		20
+#define	AR_NoAck		0x01000000	/* No ACK flag */
+#define	AR_CompProc		0x06000000	/* compression processing */
+#define	AR_CompProc_S		25
+#define	AR_CompIVLen		0x18000000	/* length of frame IV */
+#define	AR_CompIVLen_S		27
+#define	AR_CompICVLen		0x60000000	/* length of frame ICV */
+#define	AR_CompICVLen_S		29
+/* bit 31 is reserved */
+
+/* TX ds_ctl2 */
+#define	AR_RTSCTSDuration	0x00007fff	/* RTS/CTS duration */
+#define	AR_RTSCTSDuration_S	0
+#define	AR_DurUpdateEna		0x00008000	/* frame duration update ctl */
+#define	AR_XmitDataTries0	0x000f0000	/* series 0 max attempts */
+#define	AR_XmitDataTries0_S	16
+#define	AR_XmitDataTries1	0x00f00000	/* series 1 max attempts */
+#define	AR_XmitDataTries1_S	20
+#define	AR_XmitDataTries2	0x0f000000	/* series 2 max attempts */
+#define	AR_XmitDataTries2_S	24
+#define	AR_XmitDataTries3	0xf0000000	/* series 3 max attempts */
+#define	AR_XmitDataTries3_S	28
+
+/* TX ds_ctl3 */
+#define	AR_XmitRate0		0x0000001f	/* series 0 tx rate */
+#define	AR_XmitRate0_S		0
+#define	AR_XmitRate1		0x000003e0	/* series 1 tx rate */
+#define	AR_XmitRate1_S		5
+#define	AR_XmitRate2		0x00007c00	/* series 2 tx rate */
+#define	AR_XmitRate2_S		10
+#define	AR_XmitRate3		0x000f8000	/* series 3 tx rate */
+#define	AR_XmitRate3_S		15
+#define	AR_RTSCTSRate		0x01f00000	/* RTS or CTS rate */
+#define	AR_RTSCTSRate_S		20
+/* bits 25-31 are reserved */
+
+/* RX ds_ctl1 */
+/*	AR_BufLen		0x00000fff	   data buffer length */
+/* bit 12 is reserved */
+#define	AR_RxInterReq		0x00002000	/* RX interrupt request */
+/* bits 14-31 are reserved */
+
+/* TX ds_txstatus0 */
+#define	AR_FrmXmitOK		0x00000001	/* TX success */
+#define	AR_ExcessiveRetries	0x00000002	/* excessive retries */
+#define	AR_FIFOUnderrun		0x00000004	/* TX FIFO underrun */
+#define	AR_Filtered		0x00000008	/* TX filter indication */
+#define	AR_RTSFailCnt		0x000000f0	/* RTS failure count */
+#define	AR_RTSFailCnt_S		4
+#define	AR_DataFailCnt		0x00000f00	/* Data failure count */
+#define	AR_DataFailCnt_S	8
+#define	AR_VirtCollCnt		0x0000f000	/* virtual collision count */
+#define	AR_VirtCollCnt_S	12
+#define	AR_SendTimestamp	0xffff0000	/* TX timestamp */
+#define	AR_SendTimestamp_S	16
+
+/* RX ds_rxstatus0 */
+#define	AR_DataLen		0x00000fff	/* RX data length */
+/*	AR_More			0x00001000	   more desc in this frame */
+#define	AR_DecompCRCErr		0x00002000	/* decompression CRC error */
+/* bit 14 is reserved */
+#define	AR_RcvRate		0x000f8000	/* reception rate */
+#define	AR_RcvRate_S		15
+#define	AR_RcvSigStrength	0x0ff00000	/* receive signal strength */
+#define	AR_RcvSigStrength_S	20
+#define	AR_RcvAntenna		0xf0000000	/* receive antenaa */
+#define	AR_RcvAntenna_S		28
+
+/* TX ds_txstatus1 */
+#define	AR_Done			0x00000001	/* descripter complete */
+#define	AR_SeqNum		0x00001ffe	/* TX sequence number */
+#define	AR_SeqNum_S		1
+#define	AR_AckSigStrength	0x001fe000	/* strength of ACK */
+#define	AR_AckSigStrength_S	13
+#define	AR_FinalTSIndex		0x00600000	/* final TX attempt series ix */
+#define	AR_FinalTSIndex_S	21
+#define	AR_CompSuccess		0x00800000	/* compression status */
+#define	AR_XmitAtenna		0x01000000	/* transmit antenna */
+/* bits 25-31 are reserved */
+
+/* RX ds_rxstatus1 */
+/*	AR_Done			0x00000001	   descripter complete */
+#define	AR_FrmRcvOK		0x00000002	/* frame reception success */
+#define	AR_CRCErr		0x00000004	/* CRC error */
+#define	AR_DecryptCRCErr	0x00000008	/* Decryption CRC fiailure */
+#define	AR_PHYErr		0x00000010	/* PHY error */
+#define	AR_MichaelErr		0x00000020	/* Michae MIC decrypt error */
+/* bits 6-7 are reserved */
+#define	AR_KeyIdxValid		0x00000100	/* decryption key index valid */
+#define	AR_KeyIdx		0x0000fe00	/* Decryption key index */
+#define	AR_KeyIdx_S		9
+#define	AR_RcvTimestamp		0x7fff0000	/* timestamp */
+#define	AR_RcvTimestamp_S	16
+#define	AR_KeyCacheMiss		0x80000000	/* key cache miss indication */
+
+/* NB: phy error code overlays key index and valid fields */
+#define	AR_PHYErrCode		0x0000ff00	/* PHY error code */
+#define	AR_PHYErrCode_S		8
+
+#endif /* _ATH_AR5212_DESC_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212phy.h b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212phy.h
new file mode 100644
index 0000000..e040ec7
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212phy.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212phy.h,v 1.7 2008/11/19 21:23:01 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5212PHY_H_
+#define _DEV_ATH_AR5212PHY_H_
+
+/* PHY registers */
+#define	AR_PHY_BASE		0x9800		/* base address of phy regs */
+#define	AR_PHY(_n)		(AR_PHY_BASE + ((_n)<<2))
+
+#define AR_PHY_TEST             0x9800          /* PHY test control */
+#define PHY_AGC_CLR             0x10000000      /* disable AGC to A2 */
+
+#define	AR_PHY_TESTCTRL		0x9808		/* PHY Test Control/Status */
+#define	AR_PHY_TESTCTRL_TXHOLD	0x3800		/* Select Tx hold */
+#define AR_PHY_TESTCTRL_TXSRC_ALT	0x00000080	/* Select input to tsdac along with bit 1 */
+#define AR_PHY_TESTCTRL_TXSRC_ALT_S	7
+#define AR_PHY_TESTCTRL_TXSRC_SRC	0x00000002	/* Used with bit 7 */
+#define AR_PHY_TESTCTRL_TXSRC_SRC_S	1
+
+#define	AR_PHY_TURBO		0x9804		/* frame control register */
+#define	AR_PHY_FC_TURBO_MODE	0x00000001	/* Set turbo mode bits */
+#define	AR_PHY_FC_TURBO_SHORT	0x00000002	/* Set short symbols to turbo mode setting */
+#define AR_PHY_FC_TURBO_MIMO    0x00000004      /* Set turbo for mimo mode */
+
+#define	AR_PHY_TIMING3		0x9814		/* Timing control 3 */
+#define	AR_PHY_TIMING3_DSC_MAN	0xFFFE0000
+#define	AR_PHY_TIMING3_DSC_MAN_S	17
+#define	AR_PHY_TIMING3_DSC_EXP	0x0001E000
+#define	AR_PHY_TIMING3_DSC_EXP_S	13
+
+#define	AR_PHY_CHIP_ID		0x9818		/* PHY chip revision ID */
+#define	AR_PHY_CHIP_ID_REV_2	0x42		/* 5212 Rev 2 BB w. TPC fix */
+#define	AR_PHY_CHIP_ID_REV_3	0x43		/* 5212 Rev 3 5213 */
+#define	AR_PHY_CHIP_ID_REV_4	0x44		/* 5212 Rev 4 2313 and up */
+
+#define	AR_PHY_ACTIVE		0x981C		/* activation register */
+#define	AR_PHY_ACTIVE_EN	0x00000001	/* Activate PHY chips */
+#define	AR_PHY_ACTIVE_DIS	0x00000000	/* Deactivate PHY chips */
+
+#define AR_PHY_TX_CTL		0x9824
+#define AR_PHY_TX_FRAME_TO_TX_DATA_START	0x0000000f
+#define AR_PHY_TX_FRAME_TO_TX_DATA_START_S	0
+
+#define	AR_PHY_ADC_CTL		0x982C
+#define	AR_PHY_ADC_CTL_OFF_INBUFGAIN	0x00000003
+#define	AR_PHY_ADC_CTL_OFF_INBUFGAIN_S	0
+#define	AR_PHY_ADC_CTL_OFF_PWDDAC	0x00002000
+#define	AR_PHY_ADC_CTL_OFF_PWDBANDGAP	0x00004000 /* BB Rev 4.2+ only */
+#define	AR_PHY_ADC_CTL_OFF_PWDADC	0x00008000 /* BB Rev 4.2+ only */
+#define	AR_PHY_ADC_CTL_ON_INBUFGAIN	0x00030000
+#define	AR_PHY_ADC_CTL_ON_INBUFGAIN_S	16
+
+#define	AR_PHY_BB_XP_PA_CTL	0x9838
+#define AR_PHY_BB_XPAA_ACTIVE_HIGH	0x00000001
+#define	AR_PHY_BB_XPAB_ACTIVE_HIGH	0x00000002
+#define	AR_PHY_BB_XPAB_ACTIVE_HIGH_S	1
+
+#define AR_PHY_TSTDAC_CONST	0x983C
+#define AR_PHY_TSTDAC_CONST_Q	0x0003FE00
+#define AR_PHY_TSTDAC_CONST_Q_S	9
+#define AR_PHY_TSTDAC_CONST_I	0x000001FF
+
+
+#define	AR_PHY_SETTLING		0x9844
+#define AR_PHY_SETTLING_AGC 0x0000007F
+#define AR_PHY_SETTLING_AGC_S   0
+#define	AR_PHY_SETTLING_SWITCH	0x00003F80
+#define	AR_PHY_SETTLING_SWITCH_S	7
+
+#define	AR_PHY_RXGAIN		0x9848
+#define	AR_PHY_RXGAIN_TXRX_ATTEN	0x0003F000
+#define	AR_PHY_RXGAIN_TXRX_ATTEN_S	12
+#define	AR_PHY_RXGAIN_TXRX_RF_MAX	0x007C0000
+#define	AR_PHY_RXGAIN_TXRX_RF_MAX_S	18
+
+#define	AR_PHY_DESIRED_SZ	0x9850
+#define	AR_PHY_DESIRED_SZ_ADC		0x000000FF
+#define	AR_PHY_DESIRED_SZ_ADC_S		0
+#define	AR_PHY_DESIRED_SZ_PGA		0x0000FF00
+#define	AR_PHY_DESIRED_SZ_PGA_S		8
+#define	AR_PHY_DESIRED_SZ_TOT_DES	0x0FF00000
+#define	AR_PHY_DESIRED_SZ_TOT_DES_S	20
+
+#define	AR_PHY_FIND_SIG		 0x9858
+#define	AR_PHY_FIND_SIG_FIRSTEP	 0x0003F000
+#define	AR_PHY_FIND_SIG_FIRSTEP_S		 12
+#define	AR_PHY_FIND_SIG_FIRPWR	 0x03FC0000
+#define	AR_PHY_FIND_SIG_FIRPWR_S		 18
+
+#define	AR_PHY_AGC_CTL1		 0x985C
+#define	AR_PHY_AGC_CTL1_COARSE_LOW		 0x00007F80
+#define	AR_PHY_AGC_CTL1_COARSE_LOW_S		 7
+#define	AR_PHY_AGC_CTL1_COARSE_HIGH		 0x003F8000
+#define	AR_PHY_AGC_CTL1_COARSE_HIGH_S		 15
+
+#define	AR_PHY_AGC_CONTROL	0x9860		/* chip calibration and noise floor setting */
+#define	AR_PHY_AGC_CONTROL_CAL	0x00000001	/* do internal calibration */
+#define	AR_PHY_AGC_CONTROL_NF	0x00000002	/* do noise-floor calculation */
+#define AR_PHY_AGC_CONTROL_ENABLE_NF     0x00008000 /* Enable noise floor calibration to happen */
+#define	AR_PHY_AGC_CONTROL_FLTR_CAL	0x00010000  /* Allow Filter calibration */
+#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF  0x00020000 /* Don't update noise floor automatically */
+
+#define	AR_PHY_SFCORR_LOW	 0x986C
+#define	AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW	 0x00000001
+#define	AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW	 0x00003F00
+#define	AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S	 8
+#define	AR_PHY_SFCORR_LOW_M1_THRESH_LOW	 0x001FC000
+#define	AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S	 14
+#define	AR_PHY_SFCORR_LOW_M2_THRESH_LOW	 0x0FE00000
+#define	AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S	 21
+
+#define	AR_PHY_SFCORR	 	0x9868
+#define	AR_PHY_SFCORR_M2COUNT_THR	 0x0000001F
+#define	AR_PHY_SFCORR_M2COUNT_THR_S	 0
+#define	AR_PHY_SFCORR_M1_THRESH	 0x00FE0000
+#define	AR_PHY_SFCORR_M1_THRESH_S	 17
+#define	AR_PHY_SFCORR_M2_THRESH	 0x7F000000
+#define	AR_PHY_SFCORR_M2_THRESH_S	 24
+
+#define	AR_PHY_SLEEP_CTR_CONTROL	0x9870
+#define	AR_PHY_SLEEP_CTR_LIMIT		0x9874
+#define	AR_PHY_SLEEP_SCAL		0x9878
+
+#define	AR_PHY_PLL_CTL		0x987c	/* PLL control register */
+#define	AR_PHY_PLL_CTL_40	0xaa	/* 40 MHz */
+#define	AR_PHY_PLL_CTL_44	0xab	/* 44 MHz for 11b, 11g */
+#define	AR_PHY_PLL_CTL_44_5112	0xeb	/* 44 MHz for 11b, 11g */
+#define	AR_PHY_PLL_CTL_40_5112	0xea	/* 40 MHz for 11a, turbos */
+#define	AR_PHY_PLL_CTL_40_5413  0x04	/* 40 MHz for 11a, turbos with 5413 */
+#define	AR_PHY_PLL_CTL_HALF	0x100	/* Half clock for 1/2 chan width */
+#define	AR_PHY_PLL_CTL_QUARTER	0x200	/* Quarter clock for 1/4 chan width */
+
+#define	AR_PHY_BIN_MASK_1	0x9900
+#define	AR_PHY_BIN_MASK_2	0x9904
+#define	AR_PHY_BIN_MASK_3	0x9908
+
+#define	AR_PHY_MASK_CTL		0x990c		/* What are these for?? */
+#define	AR_PHY_MASK_CTL_MASK_4	0x00003FFF
+#define	AR_PHY_MASK_CTL_MASK_4_S	0
+#define	AR_PHY_MASK_CTL_RATE	0xFF000000
+#define	AR_PHY_MASK_CTL_RATE_S	24
+
+#define	AR_PHY_RX_DELAY		0x9914		/* analog pow-on time (100ns) */
+#define	AR_PHY_RX_DELAY_DELAY	0x00003FFF	/* delay from wakeup to rx ena */
+
+#define	AR_PHY_TIMING_CTRL4		0x9920		/* timing control */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF	0x01F	/* Mask for kcos_theta-1 for q correction */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S	0	/* shift for Q_COFF */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF	0x7E0	/* Mask for sin_theta for i correction */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S	5	/* Shift for sin_theta for i correction */
+#define	AR_PHY_TIMING_CTRL4_IQCORR_ENABLE	0x800	/* enable IQ correction */
+#define	AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX	0xF000	/* Mask for max number of samples (logarithmic) */
+#define	AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S	12	/* Shift for max number of samples */
+#define	AR_PHY_TIMING_CTRL4_DO_IQCAL	0x10000		/* perform IQ calibration */
+#define	AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER	0x40000000	/* Enable spur filter */
+#define	AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK	0x20000000
+#define	AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK	0x10000000
+
+#define	AR_PHY_TIMING5		0x9924
+#define	AR_PHY_TIMING5_CYCPWR_THR1	0x000000FE
+#define	AR_PHY_TIMING5_CYCPWR_THR1_S	1
+
+#define	AR_PHY_PAPD_PROBE	0x9930
+#define	AR_PHY_PAPD_PROBE_POWERTX	0x00007E00
+#define	AR_PHY_PAPD_PROBE_POWERTX_S	9
+#define	AR_PHY_PAPD_PROBE_NEXT_TX	0x00008000	/* command to take next reading */
+#define	AR_PHY_PAPD_PROBE_TYPE	0x01800000
+#define	AR_PHY_PAPD_PROBE_TYPE_S	23
+#define	AR_PHY_PAPD_PROBE_TYPE_OFDM	0
+#define	AR_PHY_PAPD_PROBE_TYPE_CCK	2
+#define	AR_PHY_PAPD_PROBE_GAINF	0xFE000000
+#define	AR_PHY_PAPD_PROBE_GAINF_S	25
+
+#define	AR_PHY_POWER_TX_RATE1	0x9934
+#define	AR_PHY_POWER_TX_RATE2	0x9938
+#define	AR_PHY_POWER_TX_RATE_MAX	0x993c
+#define	AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE	0x00000040
+
+#define	AR_PHY_FRAME_CTL	0x9944
+#define	AR_PHY_FRAME_CTL_TX_CLIP	0x00000038
+#define	AR_PHY_FRAME_CTL_TX_CLIP_S	3
+#define AR_PHY_FRAME_CTL_ERR_SERV	0x20000000
+#define AR_PHY_FRAME_CTL_ERR_SERV_S	29
+#define AR_PHY_FRAME_CTL_EMU_M		0x80000000
+#define AR_PHY_FRAME_CTL_EMU_S		31
+#define AR_PHY_FRAME_CTL_WINLEN		0x00000003
+#define AR_PHY_FRAME_CTL_WINLEN_S	0
+
+#define	AR_PHY_TXPWRADJ		0x994C		/* BB Rev 4.2+ only */
+#define	AR_PHY_TXPWRADJ_CCK_GAIN_DELTA	0x00000FC0
+#define	AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S	6
+#define	AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX	0x00FC0000
+#define	AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S	18
+
+#define	AR_PHY_RADAR_0		0x9954		/* radar detection settings */
+#define	AR_PHY_RADAR_0_ENA	0x00000001	/* Enable radar detection */
+#define AR_PHY_RADAR_0_INBAND	0x0000003e	/* Inband pulse threshold */
+#define AR_PHY_RADAR_0_INBAND_S	1
+#define AR_PHY_RADAR_0_PRSSI	0x00000FC0	/* Pulse rssi threshold */
+#define AR_PHY_RADAR_0_PRSSI_S	6
+#define AR_PHY_RADAR_0_HEIGHT	0x0003F000	/* Pulse height threshold */
+#define AR_PHY_RADAR_0_HEIGHT_S	12
+#define AR_PHY_RADAR_0_RRSSI	0x00FC0000	/* Radar rssi threshold */
+#define AR_PHY_RADAR_0_RRSSI_S	18
+#define AR_PHY_RADAR_0_FIRPWR	0x7F000000	/* Radar firpwr threshold */
+#define AR_PHY_RADAR_0_FIRPWR_S	24
+
+
+#define	AR_PHY_SIGMA_DELTA	0x996C      /* AR5312 only */
+#define	AR_PHY_SIGMA_DELTA_ADC_SEL	0x00000003
+#define	AR_PHY_SIGMA_DELTA_ADC_SEL_S	0
+#define	AR_PHY_SIGMA_DELTA_FILT2	0x000000F8
+#define	AR_PHY_SIGMA_DELTA_FILT2_S	3
+#define	AR_PHY_SIGMA_DELTA_FILT1	0x00001F00
+#define	AR_PHY_SIGMA_DELTA_FILT1_S	8
+#define	AR_PHY_SIGMA_DELTA_ADC_CLIP	0x01FFE000
+#define	AR_PHY_SIGMA_DELTA_ADC_CLIP_S	13
+
+#define	AR_PHY_RESTART		0x9970		/* restart */
+#define	AR_PHY_RESTART_DIV_GC	0x001C0000	/* bb_ant_fast_div_gc_limit */
+#define	AR_PHY_RESTART_DIV_GC_S	18
+
+#define AR_PHY_RFBUS_REQ    0x997C
+#define AR_PHY_RFBUS_REQ_REQUEST    0x00000001
+
+#define	AR_PHY_TIMING7		0x9980		/* Spur mitigation masks */
+#define	AR_PHY_TIMING8		0x9984
+#define	AR_PHY_TIMING8_PILOT_MASK_2	0x000FFFFF
+#define	AR_PHY_TIMING8_PILOT_MASK_2_S	0
+
+#define	AR_PHY_BIN_MASK2_1	0x9988
+#define	AR_PHY_BIN_MASK2_2	0x998c
+#define	AR_PHY_BIN_MASK2_3	0x9990
+#define	AR_PHY_BIN_MASK2_4	0x9994
+#define	AR_PHY_BIN_MASK2_4_MASK_4	0x00003FFF
+#define	AR_PHY_BIN_MASK2_4_MASK_4_S	0
+
+#define	AR_PHY_TIMING9		0x9998
+#define	AR_PHY_TIMING10		0x999c
+#define	AR_PHY_TIMING10_PILOT_MASK_2	0x000FFFFF
+#define	AR_PHY_TIMING10_PILOT_MASK_2_S	0
+
+#define	AR_PHY_TIMING11			0x99a0		/* Spur Mitigation control */
+#define	AR_PHY_TIMING11_SPUR_DELTA_PHASE	0x000FFFFF
+#define	AR_PHY_TIMING11_SPUR_DELTA_PHASE_S	0
+#define	AR_PHY_TIMING11_SPUR_FREQ_SD		0x3FF00000
+#define	AR_PHY_TIMING11_SPUR_FREQ_SD_S		20
+#define AR_PHY_TIMING11_USE_SPUR_IN_AGC		0x40000000
+#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR	0x80000000
+
+#define	AR_PHY_HEAVY_CLIP_ENABLE	0x99E0
+
+#define	AR_PHY_M_SLEEP		0x99f0		/* sleep control registers */
+#define	AR_PHY_REFCLKDLY	0x99f4
+#define	AR_PHY_REFCLKPD		0x99f8
+
+/* PHY IQ calibration results */
+#define	AR_PHY_IQCAL_RES_PWR_MEAS_I	0x9c10	/* power measurement for I */
+#define	AR_PHY_IQCAL_RES_PWR_MEAS_Q	0x9c14	/* power measurement for Q */
+#define	AR_PHY_IQCAL_RES_IQ_CORR_MEAS	0x9c18	/* IQ correlation measurement */
+
+#define	AR_PHY_CURRENT_RSSI	0x9c1c		/* rssi of current frame rx'd */
+
+#define AR_PHY_RFBUS_GNT    0x9c20
+#define AR_PHY_RFBUS_GNT_GRANT  0x1
+                                                                                          
+#define	AR_PHY_PCDAC_TX_POWER_0	0xA180
+#define	AR_PHY_PCDAC_TX_POWER(_n)	(AR_PHY_PCDAC_TX_POWER_0 + ((_n)<<2))
+
+#define	AR_PHY_MODE		0xA200	/* Mode register */
+#define AR_PHY_MODE_QUARTER	0x40	/* Quarter Rate */
+#define AR_PHY_MODE_HALF	0x20	/* Half Rate */
+#define	AR_PHY_MODE_AR5112	0x08	/* AR5112 */
+#define	AR_PHY_MODE_AR5111	0x00	/* AR5111/AR2111 */
+#define	AR_PHY_MODE_DYNAMIC	0x04	/* dynamic CCK/OFDM mode */
+#define	AR_PHY_MODE_RF2GHZ	0x02	/* 2.4 GHz */
+#define	AR_PHY_MODE_RF5GHZ	0x00	/* 5 GHz */
+#define	AR_PHY_MODE_CCK		0x01	/* CCK */
+#define	AR_PHY_MODE_OFDM	0x00	/* OFDM */
+#define	AR_PHY_MODE_DYN_CCK_DISABLE 0x100 /* Disable dynamic CCK detection */
+
+#define	AR_PHY_CCK_TX_CTRL	0xA204
+#define	AR_PHY_CCK_TX_CTRL_JAPAN	0x00000010
+
+#define	AR_PHY_CCK_DETECT	0xA208
+#define	AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK	0x0000003F
+#define	AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S	0
+#define	AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV	0x2000
+
+#define	AR_PHY_GAIN_2GHZ	0xA20C
+#define	AR_PHY_GAIN_2GHZ_RXTX_MARGIN	0x00FC0000
+#define	AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S	18
+
+#define	AR_PHY_CCK_RXCTRL4	0xA21C
+#define	AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT	0x01F80000
+#define	AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S	19
+
+#define	AR_PHY_DAG_CTRLCCK	0xA228
+#define	AR_PHY_DAG_CTRLCCK_EN_RSSI_THR	0x00000200 /* BB Rev 4.2+ only */
+#define	AR_PHY_DAG_CTRLCCK_RSSI_THR	0x0001FC00 /* BB Rev 4.2+ only */
+#define	AR_PHY_DAG_CTRLCCK_RSSI_THR_S	10	   /* BB Rev 4.2+ only */
+
+#define	AR_PHY_POWER_TX_RATE3	0xA234
+#define	AR_PHY_POWER_TX_RATE4	0xA238
+
+#define	AR_PHY_FAST_ADC		0xA24C
+#define	AR_PHY_BLUETOOTH	0xA254
+
+#define	AR_PHY_TPCRG1	0xA258  /* ar2413 power control */
+#define	AR_PHY_TPCRG1_NUM_PD_GAIN	0x0000c000
+#define	AR_PHY_TPCRG1_NUM_PD_GAIN_S	14
+#define	AR_PHY_TPCRG1_PDGAIN_SETTING1	0x00030000
+#define	AR_PHY_TPCRG1_PDGAIN_SETTING1_S	16
+#define	AR_PHY_TPCRG1_PDGAIN_SETTING2	0x000c0000
+#define	AR_PHY_TPCRG1_PDGAIN_SETTING2_S	18
+#define	AR_PHY_TPCRG1_PDGAIN_SETTING3	0x00300000
+#define	AR_PHY_TPCRG1_PDGAIN_SETTING3_S	20
+
+#define	AR_PHY_TPCRG5	0xA26C /* ar2413 power control */
+#define	AR_PHY_TPCRG5_PD_GAIN_OVERLAP	0x0000000F
+#define	AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S		0
+#define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1	0x000003F0
+#define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S	4
+#define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2	0x0000FC00
+#define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S	10
+#define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3	0x003F0000
+#define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S	16
+#define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4	0x0FC00000
+#define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S	22
+
+#endif	/* _DEV_ATH_AR5212PHY_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212reg.h b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212reg.h
new file mode 100644
index 0000000..681c6e3
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5212reg.h
@@ -0,0 +1,995 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5212reg.h,v 1.5 2008/11/16 06:45:43 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5212REG_H_
+#define _DEV_ATH_AR5212REG_H_
+
+/*
+ * Definitions for the Atheros 5212 chipset.
+ */
+
+/* DMA Control and Interrupt Registers */
+#define	AR_CR		0x0008	/* MAC control register */
+#define	AR_RXDP		0x000C	/* MAC receive queue descriptor pointer */
+#define	AR_CFG		0x0014	/* MAC configuration and status register */
+#define	AR_IER		0x0024	/* MAC Interrupt enable register */
+/* 0x28 is RTSD0 on the 5211 */
+/* 0x2c is RTSD1 on the 5211 */
+#define	AR_TXCFG	0x0030	/* MAC tx DMA size config register */
+#define	AR_RXCFG	0x0034	/* MAC rx DMA size config register */
+/* 0x38 is the jumbo descriptor address on the 5211 */
+#define	AR_MIBC		0x0040	/* MAC MIB control register */
+#define	AR_TOPS		0x0044	/* MAC timeout prescale count */
+#define	AR_RXNPTO	0x0048	/* MAC no frame received timeout */
+#define	AR_TXNPTO	0x004C	/* MAC no frame trasmitted timeout */
+#define	AR_RPGTO	0x0050	/* MAC receive frame gap timeout */
+#define	AR_RPCNT	0x0054	/* MAC receive frame count limit */
+#define	AR_MACMISC	0x0058	/* MAC miscellaneous control/status register */
+#define	AR_SPC_0	0x005c	/* MAC sleep performance (awake cycles) */
+#define	AR_SPC_1	0x0060	/* MAC sleep performance (asleep cycles) */
+/* 0x5c is for QCU/DCU clock gating control on 5311 */
+#define	AR_ISR		0x0080	/* MAC Primary interrupt status register */
+#define	AR_ISR_S0	0x0084	/* MAC Secondary interrupt status register 0 */
+#define	AR_ISR_S1	0x0088	/* MAC Secondary interrupt status register 1 */
+#define	AR_ISR_S2	0x008c	/* MAC Secondary interrupt status register 2 */
+#define	AR_ISR_S3	0x0090	/* MAC Secondary interrupt status register 3 */
+#define	AR_ISR_S4	0x0094	/* MAC Secondary interrupt status register 4 */
+#define	AR_IMR		0x00a0	/* MAC Primary interrupt mask register */
+#define	AR_IMR_S0	0x00a4	/* MAC Secondary interrupt mask register 0 */
+#define	AR_IMR_S1	0x00a8	/* MAC Secondary interrupt mask register 1 */
+#define	AR_IMR_S2	0x00ac	/* MAC Secondary interrupt mask register 2 */
+#define	AR_IMR_S3	0x00b0	/* MAC Secondary interrupt mask register 3 */
+#define	AR_IMR_S4	0x00b4	/* MAC Secondary interrupt mask register 4 */
+#define	AR_ISR_RAC	0x00c0	/* ISR read-and-clear access */
+/* Shadow copies with read-and-clear access */
+#define	AR_ISR_S0_S	0x00c4	/* ISR_S0 shadow copy */
+#define	AR_ISR_S1_S	0x00c8	/* ISR_S1 shadow copy */
+#define	AR_ISR_S2_S	0x00cc	/* ISR_S2 shadow copy */
+#define	AR_ISR_S3_S	0x00d0	/* ISR_S3 shadow copy */
+#define	AR_ISR_S4_S	0x00d4	/* ISR_S4 shadow copy */
+#define	AR_DMADBG_0	0x00e0	/* DMA debug 0 */
+#define	AR_DMADBG_1	0x00e4	/* DMA debug 1 */
+#define	AR_DMADBG_2	0x00e8	/* DMA debug 2 */
+#define	AR_DMADBG_3	0x00ec	/* DMA debug 3 */
+#define	AR_DMADBG_4	0x00f0	/* DMA debug 4 */
+#define	AR_DMADBG_5	0x00f4	/* DMA debug 5 */
+#define	AR_DMADBG_6	0x00f8	/* DMA debug 6 */
+#define	AR_DMADBG_7	0x00fc	/* DMA debug 7 */
+#define	AR_DCM_A	0x0400	/* Decompression mask address */
+#define	AR_DCM_D	0x0404	/* Decompression mask data */
+#define	AR_DCCFG	0x0420	/* Decompression configuration */
+#define	AR_CCFG		0x0600	/* Compression configuration */
+#define	AR_CCUCFG	0x0604	/* Compression catchup configuration */
+#define	AR_CPC_0	0x0610	/* Compression performance counter 0 */
+#define	AR_CPC_1	0x0614	/* Compression performance counter 1 */
+#define	AR_CPC_2	0x0618	/* Compression performance counter 2 */
+#define	AR_CPC_3	0x061c	/* Compression performance counter 3 */
+#define	AR_CPCOVF	0x0620	/* Compression performance overflow status */
+
+#define	AR_Q0_TXDP	0x0800	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q1_TXDP	0x0804	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q2_TXDP	0x0808	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q3_TXDP	0x080c	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q4_TXDP	0x0810	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q5_TXDP	0x0814	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q6_TXDP	0x0818	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q7_TXDP	0x081c	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q8_TXDP	0x0820	/* MAC Transmit Queue descriptor pointer */
+#define	AR_Q9_TXDP	0x0824	/* MAC Transmit Queue descriptor pointer */
+#define	AR_QTXDP(_i)	(AR_Q0_TXDP + ((_i)<<2))
+
+#define	AR_Q_TXE	0x0840	/* MAC Transmit Queue enable */
+#define	AR_Q_TXD	0x0880	/* MAC Transmit Queue disable */
+
+#define	AR_Q0_CBRCFG	0x08c0	/* MAC CBR configuration */
+#define	AR_Q1_CBRCFG	0x08c4	/* MAC CBR configuration */
+#define	AR_Q2_CBRCFG	0x08c8	/* MAC CBR configuration */
+#define	AR_Q3_CBRCFG	0x08cc	/* MAC CBR configuration */
+#define	AR_Q4_CBRCFG	0x08d0	/* MAC CBR configuration */
+#define	AR_Q5_CBRCFG	0x08d4	/* MAC CBR configuration */
+#define	AR_Q6_CBRCFG	0x08d8	/* MAC CBR configuration */
+#define	AR_Q7_CBRCFG	0x08dc	/* MAC CBR configuration */
+#define	AR_Q8_CBRCFG	0x08e0	/* MAC CBR configuration */
+#define	AR_Q9_CBRCFG	0x08e4	/* MAC CBR configuration */
+#define	AR_QCBRCFG(_i)	(AR_Q0_CBRCFG + ((_i)<<2))
+
+#define	AR_Q0_RDYTIMECFG	0x0900	/* MAC ReadyTime configuration */
+#define	AR_Q1_RDYTIMECFG	0x0904	/* MAC ReadyTime configuration */
+#define	AR_Q2_RDYTIMECFG	0x0908	/* MAC ReadyTime configuration */
+#define	AR_Q3_RDYTIMECFG	0x090c	/* MAC ReadyTime configuration */
+#define	AR_Q4_RDYTIMECFG	0x0910	/* MAC ReadyTime configuration */
+#define	AR_Q5_RDYTIMECFG	0x0914	/* MAC ReadyTime configuration */
+#define	AR_Q6_RDYTIMECFG	0x0918	/* MAC ReadyTime configuration */
+#define	AR_Q7_RDYTIMECFG	0x091c	/* MAC ReadyTime configuration */
+#define	AR_Q8_RDYTIMECFG	0x0920	/* MAC ReadyTime configuration */
+#define	AR_Q9_RDYTIMECFG	0x0924	/* MAC ReadyTime configuration */
+#define	AR_QRDYTIMECFG(_i)	(AR_Q0_RDYTIMECFG + ((_i)<<2))
+
+#define	AR_Q_ONESHOTARM_SC	0x0940	/* MAC OneShotArm set control */
+#define	AR_Q_ONESHOTARM_CC	0x0980	/* MAC OneShotArm clear control */
+
+#define	AR_Q0_MISC	0x09c0	/* MAC Miscellaneous QCU settings */
+#define	AR_Q1_MISC	0x09c4	/* MAC Miscellaneous QCU settings */
+#define	AR_Q2_MISC	0x09c8	/* MAC Miscellaneous QCU settings */
+#define	AR_Q3_MISC	0x09cc	/* MAC Miscellaneous QCU settings */
+#define	AR_Q4_MISC	0x09d0	/* MAC Miscellaneous QCU settings */
+#define	AR_Q5_MISC	0x09d4	/* MAC Miscellaneous QCU settings */
+#define	AR_Q6_MISC	0x09d8	/* MAC Miscellaneous QCU settings */
+#define	AR_Q7_MISC	0x09dc	/* MAC Miscellaneous QCU settings */
+#define	AR_Q8_MISC	0x09e0	/* MAC Miscellaneous QCU settings */
+#define	AR_Q9_MISC	0x09e4	/* MAC Miscellaneous QCU settings */
+#define	AR_QMISC(_i)	(AR_Q0_MISC + ((_i)<<2))
+
+#define	AR_Q0_STS	0x0a00	/* MAC Miscellaneous QCU status */
+#define	AR_Q1_STS	0x0a04	/* MAC Miscellaneous QCU status */
+#define	AR_Q2_STS	0x0a08	/* MAC Miscellaneous QCU status */
+#define	AR_Q3_STS	0x0a0c	/* MAC Miscellaneous QCU status */
+#define	AR_Q4_STS	0x0a10	/* MAC Miscellaneous QCU status */
+#define	AR_Q5_STS	0x0a14	/* MAC Miscellaneous QCU status */
+#define	AR_Q6_STS	0x0a18	/* MAC Miscellaneous QCU status */
+#define	AR_Q7_STS	0x0a1c	/* MAC Miscellaneous QCU status */
+#define	AR_Q8_STS	0x0a20	/* MAC Miscellaneous QCU status */
+#define	AR_Q9_STS	0x0a24	/* MAC Miscellaneous QCU status */
+#define	AR_QSTS(_i)	(AR_Q0_STS + ((_i)<<2))
+
+#define	AR_Q_RDYTIMESHDN	0x0a40	/* MAC ReadyTimeShutdown status */
+#define	AR_Q_CBBS	0xb00	/* Compression buffer base select */
+#define	AR_Q_CBBA	0xb04	/* Compression buffer base access */
+#define	AR_Q_CBC	0xb08	/* Compression buffer configuration */
+
+#define	AR_D0_QCUMASK	0x1000	/* MAC QCU Mask */
+#define	AR_D1_QCUMASK	0x1004	/* MAC QCU Mask */
+#define	AR_D2_QCUMASK	0x1008	/* MAC QCU Mask */
+#define	AR_D3_QCUMASK	0x100c	/* MAC QCU Mask */
+#define	AR_D4_QCUMASK	0x1010	/* MAC QCU Mask */
+#define	AR_D5_QCUMASK	0x1014	/* MAC QCU Mask */
+#define	AR_D6_QCUMASK	0x1018	/* MAC QCU Mask */
+#define	AR_D7_QCUMASK	0x101c	/* MAC QCU Mask */
+#define	AR_D8_QCUMASK	0x1020	/* MAC QCU Mask */
+#define	AR_D9_QCUMASK	0x1024	/* MAC QCU Mask */
+#define	AR_DQCUMASK(_i)	(AR_D0_QCUMASK + ((_i)<<2))
+
+#define	AR_D0_LCL_IFS	0x1040	/* MAC DCU-specific IFS settings */
+#define	AR_D1_LCL_IFS	0x1044	/* MAC DCU-specific IFS settings */
+#define	AR_D2_LCL_IFS	0x1048	/* MAC DCU-specific IFS settings */
+#define	AR_D3_LCL_IFS	0x104c	/* MAC DCU-specific IFS settings */
+#define	AR_D4_LCL_IFS	0x1050	/* MAC DCU-specific IFS settings */
+#define	AR_D5_LCL_IFS	0x1054	/* MAC DCU-specific IFS settings */
+#define	AR_D6_LCL_IFS	0x1058	/* MAC DCU-specific IFS settings */
+#define	AR_D7_LCL_IFS	0x105c	/* MAC DCU-specific IFS settings */
+#define	AR_D8_LCL_IFS	0x1060	/* MAC DCU-specific IFS settings */
+#define	AR_D9_LCL_IFS	0x1064	/* MAC DCU-specific IFS settings */
+#define	AR_DLCL_IFS(_i)	(AR_D0_LCL_IFS + ((_i)<<2))
+
+#define	AR_D0_RETRY_LIMIT	0x1080	/* MAC Retry limits */
+#define	AR_D1_RETRY_LIMIT	0x1084	/* MAC Retry limits */
+#define	AR_D2_RETRY_LIMIT	0x1088	/* MAC Retry limits */
+#define	AR_D3_RETRY_LIMIT	0x108c	/* MAC Retry limits */
+#define	AR_D4_RETRY_LIMIT	0x1090	/* MAC Retry limits */
+#define	AR_D5_RETRY_LIMIT	0x1094	/* MAC Retry limits */
+#define	AR_D6_RETRY_LIMIT	0x1098	/* MAC Retry limits */
+#define	AR_D7_RETRY_LIMIT	0x109c	/* MAC Retry limits */
+#define	AR_D8_RETRY_LIMIT	0x10a0	/* MAC Retry limits */
+#define	AR_D9_RETRY_LIMIT	0x10a4	/* MAC Retry limits */
+#define	AR_DRETRY_LIMIT(_i)	(AR_D0_RETRY_LIMIT + ((_i)<<2))
+
+#define	AR_D0_CHNTIME	0x10c0	/* MAC ChannelTime settings */
+#define	AR_D1_CHNTIME	0x10c4	/* MAC ChannelTime settings */
+#define	AR_D2_CHNTIME	0x10c8	/* MAC ChannelTime settings */
+#define	AR_D3_CHNTIME	0x10cc	/* MAC ChannelTime settings */
+#define	AR_D4_CHNTIME	0x10d0	/* MAC ChannelTime settings */
+#define	AR_D5_CHNTIME	0x10d4	/* MAC ChannelTime settings */
+#define	AR_D6_CHNTIME	0x10d8	/* MAC ChannelTime settings */
+#define	AR_D7_CHNTIME	0x10dc	/* MAC ChannelTime settings */
+#define	AR_D8_CHNTIME	0x10e0	/* MAC ChannelTime settings */
+#define	AR_D9_CHNTIME	0x10e4	/* MAC ChannelTime settings */
+#define	AR_DCHNTIME(_i)	(AR_D0_CHNTIME + ((_i)<<2))
+
+#define	AR_D0_MISC	0x1100	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D1_MISC	0x1104	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D2_MISC	0x1108	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D3_MISC	0x110c	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D4_MISC	0x1110	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D5_MISC	0x1114	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D6_MISC	0x1118	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D7_MISC	0x111c	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D8_MISC	0x1120	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_D9_MISC	0x1124	/* MAC Miscellaneous DCU-specific settings */
+#define	AR_DMISC(_i)	(AR_D0_MISC + ((_i)<<2))
+
+#define	AR_D_SEQNUM	0x1140	/* MAC Frame sequence number */
+
+/* MAC DCU-global IFS settings */
+#define	AR_D_GBL_IFS_SIFS	0x1030	/* DCU global SIFS settings */
+#define	AR_D_GBL_IFS_SLOT	0x1070	/* DC global slot interval */
+#define	AR_D_GBL_IFS_EIFS	0x10b0	/* DCU global EIFS setting */
+#define	AR_D_GBL_IFS_MISC	0x10f0	/* DCU global misc. IFS settings */
+#define	AR_D_FPCTL	0x1230		/* DCU frame prefetch settings */
+#define	AR_D_TXPSE	0x1270		/* DCU transmit pause control/status */
+#define	AR_D_TXBLK_CMD	0x1038		/* DCU transmit filter cmd (w/only) */
+#define	AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i))	/* DCU transmit filter data */
+#define	AR_D_TXBLK_CLR	0x143c		/* DCU clear tx filter (w/only) */
+#define	AR_D_TXBLK_SET	0x147c		/* DCU set tx filter (w/only) */
+
+#define	AR_RC		0x4000	/* Warm reset control register */
+#define	AR_SCR		0x4004	/* Sleep control register */
+#define	AR_INTPEND	0x4008	/* Interrupt Pending register */
+#define	AR_SFR		0x400C	/* Sleep force register */
+#define	AR_PCICFG	0x4010	/* PCI configuration register */
+#define	AR_GPIOCR	0x4014	/* GPIO control register */
+#define	AR_GPIODO	0x4018	/* GPIO data output access register */
+#define	AR_GPIODI	0x401C	/* GPIO data input access register */
+#define	AR_SREV		0x4020	/* Silicon Revision register */
+#define	AR_TXEPOST	0x4028	/* TXE write posting resgister */
+#define	AR_QSM		0x402C	/* QCU sleep mask */
+
+#define	AR_PCIE_PMC	0x4068	/* PCIe power mgt config and status register */
+#define AR_PCIE_SERDES	0x4080  /* PCIe Serdes register */
+#define AR_PCIE_SERDES2	0x4084  /* PCIe Serdes register */
+
+#define	AR_EEPROM_ADDR	0x6000	/* EEPROM address register (10 bit) */
+#define	AR_EEPROM_DATA	0x6004	/* EEPROM data register (16 bit) */
+#define	AR_EEPROM_CMD	0x6008	/* EEPROM command register */
+#define	AR_EEPROM_STS	0x600c	/* EEPROM status register */
+#define	AR_EEPROM_CFG	0x6010	/* EEPROM configuration register */
+
+#define	AR_STA_ID0	0x8000	/* MAC station ID0 register - low 32 bits */
+#define	AR_STA_ID1	0x8004	/* MAC station ID1 register - upper 16 bits */
+#define	AR_BSS_ID0	0x8008	/* MAC BSSID low 32 bits */
+#define	AR_BSS_ID1	0x800C	/* MAC BSSID upper 16 bits / AID */
+#define	AR_SLOT_TIME	0x8010	/* MAC Time-out after a collision */
+#define	AR_TIME_OUT	0x8014	/* MAC ACK & CTS time-out */
+#define	AR_RSSI_THR	0x8018	/* MAC RSSI warning & missed beacon threshold */
+#define	AR_USEC		0x801c	/* MAC transmit latency register */
+#define	AR_BEACON	0x8020	/* MAC beacon control value/mode bits */
+#define	AR_CFP_PERIOD	0x8024	/* MAC CFP Interval (TU/msec) */
+#define	AR_TIMER0	0x8028	/* MAC Next beacon time (TU/msec) */
+#define	AR_TIMER1	0x802c	/* MAC DMA beacon alert time (1/8 TU) */
+#define	AR_TIMER2	0x8030	/* MAC Software beacon alert (1/8 TU) */
+#define	AR_TIMER3	0x8034	/* MAC ATIM window time */
+#define	AR_CFP_DUR	0x8038	/* MAC maximum CFP duration in TU */
+#define	AR_RX_FILTER	0x803C	/* MAC receive filter register */
+#define	AR_MCAST_FIL0	0x8040	/* MAC multicast filter lower 32 bits */
+#define	AR_MCAST_FIL1	0x8044	/* MAC multicast filter upper 32 bits */
+#define	AR_DIAG_SW	0x8048	/* MAC PCU control register */
+#define	AR_TSF_L32	0x804c	/* MAC local clock lower 32 bits */
+#define	AR_TSF_U32	0x8050	/* MAC local clock upper 32 bits */
+#define	AR_TST_ADDAC	0x8054	/* ADDAC test register */
+#define	AR_DEF_ANTENNA	0x8058	/* default antenna register */
+#define	AR_QOS_MASK	0x805c	/* MAC AES mute mask: QoS field */
+#define	AR_SEQ_MASK	0x8060	/* MAC AES mute mask: seqnum field */
+#define	AR_OBSERV_2	0x8068	/* Observation bus 2 */
+#define	AR_OBSERV_1	0x806c	/* Observation bus 1 */
+
+#define	AR_LAST_TSTP	0x8080	/* MAC Time stamp of the last beacon received */
+#define	AR_NAV		0x8084	/* MAC current NAV value */
+#define	AR_RTS_OK	0x8088	/* MAC RTS exchange success counter */
+#define	AR_RTS_FAIL	0x808c	/* MAC RTS exchange failure counter */
+#define	AR_ACK_FAIL	0x8090	/* MAC ACK failure counter */
+#define	AR_FCS_FAIL	0x8094	/* FCS check failure counter */
+#define	AR_BEACON_CNT	0x8098	/* Valid beacon counter */
+
+#define	AR_SLEEP1	0x80d4	/* Enhanced sleep control 1 */
+#define	AR_SLEEP2	0x80d8	/* Enhanced sleep control 2 */
+#define	AR_SLEEP3	0x80dc	/* Enhanced sleep control 3 */
+#define	AR_BSSMSKL	0x80e0	/* BSSID mask lower 32 bits */
+#define	AR_BSSMSKU	0x80e4	/* BSSID mask upper 16 bits */
+#define	AR_TPC		0x80e8	/* Transmit power control for self gen frames */
+#define	AR_TFCNT	0x80ec	/* Profile count, transmit frames */
+#define	AR_RFCNT	0x80f0	/* Profile count, receive frames */
+#define	AR_RCCNT	0x80f4	/* Profile count, receive clear */
+#define	AR_CCCNT	0x80f8	/* Profile count, cycle counter */
+
+#define AR_QUIET1   0x80fc  /* Quiet time programming for TGh */
+#define AR_QUIET1_NEXT_QUIET_S  0   /* TSF of next quiet period (TU) */
+#define AR_QUIET1_NEXT_QUIET    0xffff
+#define AR_QUIET1_QUIET_ENABLE  0x10000 /* Enable Quiet time operation */
+#define AR_QUIET1_QUIET_ACK_CTS_ENABLE  0x20000 /* Do we ack/cts during quiet period */
+
+#define AR_QUIET2   0x8100  /* More Quiet time programming */
+#define AR_QUIET2_QUIET_PER_S   0   /* Periodicity of quiet period (TU) */
+#define AR_QUIET2_QUIET_PER 0xffff
+#define AR_QUIET2_QUIET_DUR_S   16  /* Duration of quiet period (TU) */
+#define AR_QUIET2_QUIET_DUR 0xffff0000
+
+#define	AR_TSF_PARM	0x8104	/* TSF parameters */
+#define AR_NOACK        0x8108  /* No ack policy in QoS Control Field */ 
+#define	AR_PHY_ERR	0x810c	/* Phy error filter */
+
+#define	AR_QOS_CONTROL	0x8118	/* Control TKIP MIC for QoS */
+#define	AR_QOS_SELECT	0x811c	/* MIC QoS select */
+#define	AR_MISC_MODE	0x8120	/* PCU Misc. mode control */
+
+/* Hainan MIB counter registers */
+#define	AR_FILTOFDM	0x8124	/* Count of filtered OFDM frames */
+#define	AR_FILTCCK	0x8128	/* Count of filtered CCK frames */
+#define	AR_PHYCNT1	0x812c	/* Phy Error 1 counter */
+#define	AR_PHYCNTMASK1	0x8130	/* Phy Error 1 counter mask */
+#define	AR_PHYCNT2	0x8134	/* Phy Error 2 counter */
+#define	AR_PHYCNTMASK2	0x8138	/* Phy Error 2 counter mask */
+#define	AR_PHY_COUNTMAX	(3 << 22)	/* Max value in counter before intr */
+#define	AR_MIBCNT_INTRMASK (3<<22)	/* Mask for top two bits of counters */
+
+#define	AR_RATE_DURATION_0	0x8700		/* base of multi-rate retry */
+#define	AR_RATE_DURATION(_n)	(AR_RATE_DURATION_0 + ((_n)<<2))
+
+#define	AR_KEYTABLE_0	0x8800	/* MAC Key Cache */
+#define	AR_KEYTABLE(_n)	(AR_KEYTABLE_0 + ((_n)*32))
+
+#define	AR_CFP_MASK	0x0000ffff /* Mask for next beacon time */
+
+#define	AR_CR_RXE	0x00000004 /* Receive enable */
+#define	AR_CR_RXD	0x00000020 /* Receive disable */
+#define	AR_CR_SWI	0x00000040 /* One-shot software interrupt */
+
+#define	AR_CFG_SWTD	0x00000001 /* byteswap tx descriptor words */
+#define	AR_CFG_SWTB	0x00000002 /* byteswap tx data buffer words */
+#define	AR_CFG_SWRD	0x00000004 /* byteswap rx descriptor words */
+#define	AR_CFG_SWRB	0x00000008 /* byteswap rx data buffer words */
+#define	AR_CFG_SWRG	0x00000010 /* byteswap register access data words */
+#define	AR_CFG_AP_ADHOC_INDICATION	0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
+#define	AR_CFG_PHOK	0x00000100 /* PHY OK status */
+#define	AR_CFG_EEBS	0x00000200 /* EEPROM busy */
+#define	AR_5211_CFG_CLK_GATE_DIS	0x00000400 /* Clock gating disable (Oahu only) */
+#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH	0x00060000 /* Mask of PCI core master request queue full threshold */
+#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH_S	17         /* Shift for PCI core master request queue full threshold */
+
+#define	AR_IER_ENABLE	0x00000001 /* Global interrupt enable */
+#define	AR_IER_DISABLE	0x00000000 /* Global interrupt disable */
+
+#define	AR_DMASIZE_4B	0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
+#define	AR_DMASIZE_8B	0x00000001 /* DMA size 8 bytes */
+#define	AR_DMASIZE_16B	0x00000002 /* DMA size 16 bytes */
+#define	AR_DMASIZE_32B	0x00000003 /* DMA size 32 bytes */
+#define	AR_DMASIZE_64B	0x00000004 /* DMA size 64 bytes */
+#define	AR_DMASIZE_128B	0x00000005 /* DMA size 128 bytes */
+#define	AR_DMASIZE_256B	0x00000006 /* DMA size 256 bytes */
+#define	AR_DMASIZE_512B	0x00000007 /* DMA size 512 bytes */
+
+#define	AR_FTRIG	0x000003F0 /* Mask for Frame trigger level */
+#define	AR_FTRIG_S	4          /* Shift for Frame trigger level */
+#define	AR_FTRIG_IMMED	0x00000000 /* bytes in PCU TX FIFO before air */
+#define	AR_FTRIG_64B	0x00000010 /* default */
+#define	AR_FTRIG_128B	0x00000020
+#define	AR_FTRIG_192B	0x00000030
+#define	AR_FTRIG_256B	0x00000040 /* 5 bits total */
+
+#define	AR_RXCFG_ZLFDMA	0x00000010 /* Enable DMA of zero-length frame */
+
+#define	AR_MIBC_COW	0x00000001 /* counter overflow warning */
+#define	AR_MIBC_FMC	0x00000002 /* freeze MIB counters */
+#define	AR_MIBC_CMC	0x00000004 /* clear MIB counters */
+#define	AR_MIBC_MCS	0x00000008 /* MIB counter strobe, increment all */
+
+#define	AR_TOPS_MASK	0x0000FFFF /* Mask for timeout prescale */
+
+#define	AR_RXNPTO_MASK	0x000003FF /* Mask for no frame received timeout */
+
+#define	AR_TXNPTO_MASK	0x000003FF /* Mask for no frame transmitted timeout */
+#define	AR_TXNPTO_QCU_MASK	0x000FFC00 /* Mask indicating the set of QCUs */
+				 /* for which frame completions will cause */
+				 /* a reset of the no frame xmit'd timeout */
+
+#define	AR_RPGTO_MASK	0x000003FF /* Mask for receive frame gap timeout */
+
+#define	AR_RPCNT_MASK	0x0000001F /* Mask for receive frame count limit */
+
+#define	AR_MACMISC_DMA_OBS	0x000001E0 /* Mask for DMA observation bus mux select */
+#define	AR_MACMISC_DMA_OBS_S	5          /* Shift for DMA observation bus mux select */
+#define	AR_MACMISC_MISC_OBS	0x00000E00 /* Mask for MISC observation bus mux select */
+#define	AR_MACMISC_MISC_OBS_S	9          /* Shift for MISC observation bus mux select */
+#define	AR_MACMISC_MAC_OBS_BUS_LSB	0x00007000 /* Mask for MAC observation bus mux select (lsb) */
+#define	AR_MACMISC_MAC_OBS_BUS_LSB_S	12         /* Shift for MAC observation bus mux select (lsb) */
+#define	AR_MACMISC_MAC_OBS_BUS_MSB	0x00038000 /* Mask for MAC observation bus mux select (msb) */
+#define	AR_MACMISC_MAC_OBS_BUS_MSB_S	15         /* Shift for MAC observation bus mux select (msb) */
+
+/*
+ * Interrupt Status Registers
+ *
+ * Only the bits in the ISR_P register and the IMR_P registers
+ * control whether the MAC's INTA# output is asserted.  The bits in
+ * the secondary interrupt status/mask registers control what bits
+ * are set in the primary interrupt status register; however the
+ * IMR_S* registers DO NOT determine whether INTA# is asserted.
+ * That is INTA# is asserted only when the logical AND of ISR_P
+ * and IMR_P is non-zero.  The secondary interrupt mask/status
+ * registers affect what bits are set in ISR_P but they do not
+ * directly affect whether INTA# is asserted.
+ */
+#define	AR_ISR_RXOK	0x00000001 /* At least one frame received sans errors */
+#define	AR_ISR_RXDESC	0x00000002 /* Receive interrupt request */
+#define	AR_ISR_RXERR	0x00000004 /* Receive error interrupt */
+#define	AR_ISR_RXNOPKT	0x00000008 /* No frame received within timeout clock */
+#define	AR_ISR_RXEOL	0x00000010 /* Received descriptor empty interrupt */
+#define	AR_ISR_RXORN	0x00000020 /* Receive FIFO overrun interrupt */
+#define	AR_ISR_TXOK	0x00000040 /* Transmit okay interrupt */
+#define	AR_ISR_TXDESC	0x00000080 /* Transmit interrupt request */
+#define	AR_ISR_TXERR	0x00000100 /* Transmit error interrupt */
+#define	AR_ISR_TXNOPKT	0x00000200 /* No frame transmitted interrupt */
+#define	AR_ISR_TXEOL	0x00000400 /* Transmit descriptor empty interrupt */
+#define	AR_ISR_TXURN	0x00000800 /* Transmit FIFO underrun interrupt */
+#define	AR_ISR_MIB	0x00001000 /* MIB interrupt - see MIBC */
+#define	AR_ISR_SWI	0x00002000 /* Software interrupt */
+#define	AR_ISR_RXPHY	0x00004000 /* PHY receive error interrupt */
+#define	AR_ISR_RXKCM	0x00008000 /* Key-cache miss interrupt */
+#define	AR_ISR_SWBA	0x00010000 /* Software beacon alert interrupt */
+#define	AR_ISR_BRSSI	0x00020000 /* Beacon threshold interrupt */
+#define	AR_ISR_BMISS	0x00040000 /* Beacon missed interrupt */
+#define	AR_ISR_HIUERR	0x00080000 /* An unexpected bus error has occurred */
+#define	AR_ISR_BNR	0x00100000 /* Beacon not ready interrupt */
+#define	AR_ISR_RXCHIRP	0x00200000 /* Phy received a 'chirp' */
+#define	AR_ISR_RXDOPPL	0x00400000 /* Phy received a 'doppler chirp' */
+#define	AR_ISR_BCNMISC	0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO,
+				      CABTO, DTIM bits from ISR_S2 */
+#define	AR_ISR_TIM	0x00800000 /* TIM interrupt */
+#define	AR_ISR_GPIO	0x01000000 /* GPIO Interrupt */
+#define	AR_ISR_QCBROVF	0x02000000 /* QCU CBR overflow interrupt */
+#define	AR_ISR_QCBRURN	0x04000000 /* QCU CBR underrun interrupt */
+#define	AR_ISR_QTRIG	0x08000000 /* QCU scheduling trigger interrupt */
+#define	AR_ISR_RESV0	0xF0000000 /* Reserved */
+
+#define	AR_ISR_S0_QCU_TXOK	0x000003FF /* Mask for TXOK (QCU 0-9) */
+#define AR_ISR_S0_QCU_TXOK_S	0
+#define	AR_ISR_S0_QCU_TXDESC	0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
+#define AR_ISR_S0_QCU_TXDESC_S	16
+
+#define	AR_ISR_S1_QCU_TXERR	0x000003FF /* Mask for TXERR (QCU 0-9) */
+#define AR_ISR_S1_QCU_TXERR_S	0
+#define	AR_ISR_S1_QCU_TXEOL	0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
+#define AR_ISR_S1_QCU_TXEOL_S	16
+
+#define	AR_ISR_S2_QCU_TXURN	0x000003FF /* Mask for TXURN (QCU 0-9) */
+#define	AR_ISR_S2_MCABT		0x00010000 /* Master cycle abort interrupt */
+#define	AR_ISR_S2_SSERR		0x00020000 /* SERR interrupt */
+#define	AR_ISR_S2_DPERR		0x00040000 /* PCI bus parity error */
+#define	AR_ISR_S2_TIM		0x01000000 /* TIM */
+#define	AR_ISR_S2_CABEND	0x02000000 /* CABEND */
+#define	AR_ISR_S2_DTIMSYNC	0x04000000 /* DTIMSYNC */
+#define	AR_ISR_S2_BCNTO		0x08000000 /* BCNTO */
+#define	AR_ISR_S2_CABTO		0x10000000 /* CABTO */
+#define	AR_ISR_S2_DTIM		0x20000000 /* DTIM */
+#define	AR_ISR_S2_RESV0		0xE0F8FC00 /* Reserved */
+
+#define	AR_ISR_S3_QCU_QCBROVF	0x000003FF /* Mask for QCBROVF (QCU 0-9) */
+#define	AR_ISR_S3_QCU_QCBRURN	0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
+
+#define	AR_ISR_S4_QCU_QTRIG	0x000003FF /* Mask for QTRIG (QCU 0-9) */
+#define	AR_ISR_S4_RESV0		0xFFFFFC00 /* Reserved */
+
+/*
+ * Interrupt Mask Registers
+ *
+ * Only the bits in the IMR control whether the MAC's INTA#
+ * output will be asserted.  The bits in the secondary interrupt
+ * mask registers control what bits get set in the primary
+ * interrupt status register; however the IMR_S* registers
+ * DO NOT determine whether INTA# is asserted.
+ */
+#define	AR_IMR_RXOK	0x00000001 /* At least one frame received sans errors */
+#define	AR_IMR_RXDESC	0x00000002 /* Receive interrupt request */
+#define	AR_IMR_RXERR	0x00000004 /* Receive error interrupt */
+#define	AR_IMR_RXNOPKT	0x00000008 /* No frame received within timeout clock */
+#define	AR_IMR_RXEOL	0x00000010 /* Received descriptor empty interrupt */
+#define	AR_IMR_RXORN	0x00000020 /* Receive FIFO overrun interrupt */
+#define	AR_IMR_TXOK	0x00000040 /* Transmit okay interrupt */
+#define	AR_IMR_TXDESC	0x00000080 /* Transmit interrupt request */
+#define	AR_IMR_TXERR	0x00000100 /* Transmit error interrupt */
+#define	AR_IMR_TXNOPKT	0x00000200 /* No frame transmitted interrupt */
+#define	AR_IMR_TXEOL	0x00000400 /* Transmit descriptor empty interrupt */
+#define	AR_IMR_TXURN	0x00000800 /* Transmit FIFO underrun interrupt */
+#define	AR_IMR_MIB	0x00001000 /* MIB interrupt - see MIBC */
+#define	AR_IMR_SWI	0x00002000 /* Software interrupt */
+#define	AR_IMR_RXPHY	0x00004000 /* PHY receive error interrupt */
+#define	AR_IMR_RXKCM	0x00008000 /* Key-cache miss interrupt */
+#define	AR_IMR_SWBA	0x00010000 /* Software beacon alert interrupt */
+#define	AR_IMR_BRSSI	0x00020000 /* Beacon threshold interrupt */
+#define	AR_IMR_BMISS	0x00040000 /* Beacon missed interrupt */
+#define	AR_IMR_HIUERR	0x00080000 /* An unexpected bus error has occurred */
+#define	AR_IMR_BNR	0x00100000 /* BNR interrupt */
+#define	AR_IMR_RXCHIRP	0x00200000 /* RXCHIRP interrupt */
+#define	AR_IMR_BCNMISC	0x00800000 /* Venice: BCNMISC */
+#define	AR_IMR_TIM	0x00800000 /* TIM interrupt */
+#define	AR_IMR_GPIO	0x01000000 /* GPIO Interrupt */
+#define	AR_IMR_QCBROVF	0x02000000 /* QCU CBR overflow interrupt */
+#define	AR_IMR_QCBRURN	0x04000000 /* QCU CBR underrun interrupt */
+#define	AR_IMR_QTRIG	0x08000000 /* QCU scheduling trigger interrupt */
+#define	AR_IMR_RESV0	0xF0000000 /* Reserved */
+
+#define	AR_IMR_S0_QCU_TXOK	0x000003FF /* TXOK (QCU 0-9) */
+#define	AR_IMR_S0_QCU_TXOK_S	0
+#define	AR_IMR_S0_QCU_TXDESC	0x03FF0000 /* TXDESC (QCU 0-9) */
+#define	AR_IMR_S0_QCU_TXDESC_S	16
+
+#define	AR_IMR_S1_QCU_TXERR	0x000003FF /* TXERR (QCU 0-9) */
+#define	AR_IMR_S1_QCU_TXERR_S	0
+#define	AR_IMR_S1_QCU_TXEOL	0x03FF0000 /* TXEOL (QCU 0-9) */
+#define	AR_IMR_S1_QCU_TXEOL_S	16
+
+#define	AR_IMR_S2_QCU_TXURN	0x000003FF /* Mask for TXURN (QCU 0-9) */
+#define	AR_IMR_S2_QCU_TXURN_S	0
+#define	AR_IMR_S2_MCABT		0x00010000 /* Master cycle abort interrupt */
+#define	AR_IMR_S2_SSERR		0x00020000 /* SERR interrupt */
+#define	AR_IMR_S2_DPERR		0x00040000 /* PCI bus parity error */
+#define	AR_IMR_S2_TIM		0x01000000 /* TIM */
+#define	AR_IMR_S2_CABEND	0x02000000 /* CABEND */
+#define	AR_IMR_S2_DTIMSYNC	0x04000000 /* DTIMSYNC */
+#define	AR_IMR_S2_BCNTO		0x08000000 /* BCNTO */
+#define	AR_IMR_S2_CABTO		0x10000000 /* CABTO */
+#define	AR_IMR_S2_DTIM		0x20000000 /* DTIM */
+#define	AR_IMR_S2_TSFOOR	0x80000000 /* TSF OOR */
+#define	AR_IMR_S2_RESV0		0xE0F8FC00 /* Reserved */
+
+#define	AR_IMR_S3_QCU_QCBROVF	0x000003FF /* Mask for QCBROVF (QCU 0-9) */
+#define	AR_IMR_S3_QCU_QCBRURN	0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
+#define	AR_IMR_S3_QCU_QCBRURN_S	16         /* Shift for QCBRURN (QCU 0-9) */
+
+#define	AR_IMR_S4_QCU_QTRIG	0x000003FF /* Mask for QTRIG (QCU 0-9) */
+#define	AR_IMR_S4_RESV0		0xFFFFFC00 /* Reserved */
+
+/* QCU registers */
+#define	AR_NUM_QCU	10     /* Only use QCU 0-9 for forward QCU compatibility */
+#define	AR_QCU_0	0x0001
+#define	AR_QCU_1	0x0002
+#define	AR_QCU_2	0x0004
+#define	AR_QCU_3	0x0008
+#define	AR_QCU_4	0x0010
+#define	AR_QCU_5	0x0020
+#define	AR_QCU_6	0x0040
+#define	AR_QCU_7	0x0080
+#define	AR_QCU_8	0x0100
+#define	AR_QCU_9	0x0200
+
+#define	AR_Q_CBRCFG_CBR_INTERVAL	0x00FFFFFF /* Mask for CBR interval (us) */
+#define AR_Q_CBRCFG_CBR_INTERVAL_S      0   /* Shift for CBR interval */
+#define	AR_Q_CBRCFG_CBR_OVF_THRESH	0xFF000000 /* Mask for CBR overflow threshold */
+#define AR_Q_CBRCFG_CBR_OVF_THRESH_S    24  /* Shift for CBR overflow thresh */
+
+#define	AR_Q_RDYTIMECFG_INT	0x00FFFFFF /* CBR interval (us) */
+#define AR_Q_RDYTIMECFG_INT_S   0  // Shift for ReadyTime Interval (us) */
+#define	AR_Q_RDYTIMECFG_ENA	0x01000000 /* CBR enable */
+/* bits 25-31 are reserved */
+
+#define	AR_Q_MISC_FSP		0x0000000F /* Frame Scheduling Policy mask */
+#define	AR_Q_MISC_FSP_ASAP		0	/* ASAP */
+#define	AR_Q_MISC_FSP_CBR		1	/* CBR */
+#define	AR_Q_MISC_FSP_DBA_GATED		2	/* DMA Beacon Alert gated */
+#define	AR_Q_MISC_FSP_TIM_GATED		3	/* TIM gated */
+#define	AR_Q_MISC_FSP_BEACON_SENT_GATED	4	/* Beacon-sent-gated */
+#define	AR_Q_MISC_FSP_S		0
+#define	AR_Q_MISC_ONE_SHOT_EN	0x00000010 /* OneShot enable */
+#define	AR_Q_MISC_CBR_INCR_DIS1	0x00000020 /* Disable CBR expired counter incr
+					      (empty q) */
+#define	AR_Q_MISC_CBR_INCR_DIS0	0x00000040 /* Disable CBR expired counter incr
+					      (empty beacon q) */
+#define	AR_Q_MISC_BEACON_USE	0x00000080 /* Beacon use indication */
+#define	AR_Q_MISC_CBR_EXP_CNTR_LIMIT	0x00000100 /* CBR expired counter limit enable */
+#define	AR_Q_MISC_RDYTIME_EXP_POLICY	0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
+#define	AR_Q_MISC_RESET_CBR_EXP_CTR	0x00000400 /* Reset CBR expired counter */
+#define	AR_Q_MISC_DCU_EARLY_TERM_REQ	0x00000800 /* DCU frame early termination request control */
+#define	AR_Q_MISC_QCU_COMP_EN	0x00001000 /* QCU frame compression enable */
+#define	AR_Q_MISC_RESV0		0xFFFFF000 /* Reserved */
+
+#define	AR_Q_STS_PEND_FR_CNT	0x00000003 /* Mask for Pending Frame Count */
+#define	AR_Q_STS_RESV0		0x000000FC /* Reserved */
+#define	AR_Q_STS_CBR_EXP_CNT	0x0000FF00 /* Mask for CBR expired counter */
+#define	AR_Q_STS_RESV1		0xFFFF0000 /* Reserved */
+
+/* DCU registers */
+#define	AR_NUM_DCU	10     /* Only use 10 DCU's for forward QCU/DCU compatibility */
+#define	AR_DCU_0	0x0001
+#define	AR_DCU_1	0x0002
+#define	AR_DCU_2	0x0004
+#define	AR_DCU_3	0x0008
+#define	AR_DCU_4	0x0010
+#define	AR_DCU_5	0x0020
+#define	AR_DCU_6	0x0040
+#define	AR_DCU_7	0x0080
+#define	AR_DCU_8	0x0100
+#define	AR_DCU_9	0x0200
+
+#define	AR_D_QCUMASK		0x000003FF /* Mask for QCU Mask (QCU 0-9) */
+#define	AR_D_QCUMASK_RESV0	0xFFFFFC00 /* Reserved */
+
+#define	AR_D_LCL_IFS_CWMIN	0x000003FF /* Mask for CW_MIN */
+#define	AR_D_LCL_IFS_CWMIN_S	0
+#define	AR_D_LCL_IFS_CWMAX	0x000FFC00 /* Mask for CW_MAX */
+#define	AR_D_LCL_IFS_CWMAX_S	10
+#define	AR_D_LCL_IFS_AIFS	0x0FF00000 /* Mask for AIFS */
+#define	AR_D_LCL_IFS_AIFS_S	20
+/*
+ *  Note:  even though this field is 8 bits wide the
+ *  maximum supported AIFS value is 0xfc.  Setting the AIFS value
+ *  to 0xfd 0xfe, or 0xff will not work correctly and will cause
+ *  the DCU to hang.
+ */
+#define	AR_D_LCL_IFS_RESV0	0xF0000000 /* Reserved */
+
+#define	AR_D_RETRY_LIMIT_FR_SH	0x0000000F /* frame short retry limit */
+#define	AR_D_RETRY_LIMIT_FR_SH_S	0
+#define	AR_D_RETRY_LIMIT_FR_LG	0x000000F0 /* frame long retry limit */
+#define	AR_D_RETRY_LIMIT_FR_LG_S	4
+#define	AR_D_RETRY_LIMIT_STA_SH	0x00003F00 /* station short retry limit */
+#define	AR_D_RETRY_LIMIT_STA_SH_S	8
+#define	AR_D_RETRY_LIMIT_STA_LG	0x000FC000 /* station short retry limit */
+#define	AR_D_RETRY_LIMIT_STA_LG_S	14
+#define	AR_D_RETRY_LIMIT_RESV0		0xFFF00000 /* Reserved */
+
+#define	AR_D_CHNTIME_DUR		0x000FFFFF /* ChannelTime duration (us) */
+#define AR_D_CHNTIME_DUR_S              0 /* Shift for ChannelTime duration */
+#define	AR_D_CHNTIME_EN			0x00100000 /* ChannelTime enable */
+#define	AR_D_CHNTIME_RESV0		0xFFE00000 /* Reserved */
+
+#define	AR_D_MISC_BKOFF_THRESH	0x0000003F /* Backoff threshold */
+#define	AR_D_MISC_ETS_RTS		0x00000040 /* End of transmission series
+						      station RTS/data failure
+						      count reset policy */
+#define	AR_D_MISC_ETS_CW		0x00000080 /* End of transmission series
+						      CW reset policy */
+#define AR_D_MISC_FRAG_WAIT_EN          0x00000100 /* Wait for next fragment */
+#define AR_D_MISC_FRAG_BKOFF_EN         0x00000200 /* Backoff during a frag burst */
+#define	AR_D_MISC_HCF_POLL_EN		0x00000800 /* HFC poll enable */
+#define	AR_D_MISC_BKOFF_PERSISTENCE	0x00001000 /* Backoff persistence factor
+						      setting */
+#define	AR_D_MISC_FR_PREFETCH_EN	0x00002000 /* Frame prefetch enable */
+#define	AR_D_MISC_VIR_COL_HANDLING	0x0000C000 /* Mask for Virtual collision
+						      handling policy */
+#define	AR_D_MISC_VIR_COL_HANDLING_S	14
+/* FOO redefined for venice CW increment policy */
+#define	AR_D_MISC_VIR_COL_HANDLING_DEFAULT	0	/* Normal */
+#define	AR_D_MISC_VIR_COL_HANDLING_IGNORE	1	/* Ignore */
+#define	AR_D_MISC_BEACON_USE		0x00010000 /* Beacon use indication */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL	0x00060000 /* DCU arbiter lockout ctl */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_S	17         /* DCU arbiter lockout ctl */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE	0	/* No lockout */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR	1	/* Intra-frame */
+#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL	2	/* Global */
+#define	AR_D_MISC_ARB_LOCKOUT_IGNORE	0x00080000 /* DCU arbiter lockout ignore control */
+#define	AR_D_MISC_SEQ_NUM_INCR_DIS	0x00100000 /* Sequence number increment disable */
+#define	AR_D_MISC_POST_FR_BKOFF_DIS	0x00200000 /* Post-frame backoff disable */
+#define	AR_D_MISC_VIRT_COLL_POLICY	0x00400000 /* Virtual coll. handling policy */
+#define	AR_D_MISC_BLOWN_IFS_POLICY	0x00800000 /* Blown IFS handling policy */
+#define	AR_D_MISC_RESV0			0xFE000000 /* Reserved */
+
+#define	AR_D_SEQNUM_RESV0	0xFFFFF000 /* Reserved */
+
+#define	AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL	0x00000007 /* LFSR slice select */
+#define	AR_D_GBL_IFS_MISC_TURBO_MODE	0x00000008 /* Turbo mode indication */
+#define	AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC	0x000003F0 /* SIFS duration (us) */
+#define	AR_D_GBL_IFS_MISC_USEC_DURATION	0x000FFC00 /* microsecond duration */
+#define	AR_D_GBL_IFS_MISC_USEC_DURATION_S 10
+#define	AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY	0x00300000 /* DCU arbiter delay */
+#define	AR_D_GBL_IFS_MISC_RESV0	0xFFC00000 /* Reserved */
+
+/* DMA & PCI Registers in PCI space (usable during sleep) */
+#define	AR_RC_MAC		0x00000001 /* MAC reset */
+#define	AR_RC_BB		0x00000002 /* Baseband reset */
+#define	AR_RC_RESV0		0x00000004 /* Reserved */
+#define	AR_RC_RESV1		0x00000008 /* Reserved */
+#define	AR_RC_PCI		0x00000010 /* PCI-core reset */
+
+#define	AR_SCR_SLDUR		0x0000ffff /* sleep duration, units of 128us */
+#define	AR_SCR_SLDUR_S		0
+#define	AR_SCR_SLE		0x00030000 /* sleep enable */
+#define	AR_SCR_SLE_S		16
+#define	AR_SCR_SLE_WAKE		0 	/* force wake */
+#define	AR_SCR_SLE_SLP		1	/* force sleep */
+#define	AR_SCR_SLE_NORM		2	/* sleep logic normal operation */
+#define	AR_SCR_SLDTP		0x00040000 /* sleep duration timing policy */
+#define	AR_SCR_SLDWP		0x00080000 /* sleep duration write policy */
+#define	AR_SCR_SLEPOL		0x00100000 /* sleep policy mode */
+#define	AR_SCR_MIBIE		0x00200000 /* sleep perf cntrs MIB intr ena */
+
+#define	AR_INTPEND_TRUE		0x00000001 /* interrupt pending */
+
+#define	AR_SFR_SLEEP		0x00000001 /* force sleep */
+
+#define	AR_PCICFG_SCLK_SEL	0x00000002 /* sleep clock select */
+#define	AR_PCICFG_SCLK_SEL_S	1
+#define	AR_PCICFG_CLKRUNEN	0x00000004 /* enable PCI CLKRUN function */
+#define	AR_PCICFG_EEPROM_SIZE	0x00000018 /* Mask for EEPROM size */
+#define	AR_PCICFG_EEPROM_SIZE_4		0	/* EEPROM size 4 Kbit */
+#define	AR_PCICFG_EEPROM_SIZE_8K	1	/* EEPROM size 8 Kbit */
+#define	AR_PCICFG_EEPROM_SIZE_16K	2	/* EEPROM size 16 Kbit */
+#define	AR_PCICFG_EEPROM_SIZE_FAILED	3	/* Failure */
+#define	AR_PCICFG_EEPROM_SIZE_S	3
+#define	AR_PCICFG_LEDCTL	0x00000060 /* LED control Status */
+#define	AR_PCICFG_LEDCTL_NONE	0	   /* STA is not associated or trying */
+#define	AR_PCICFG_LEDCTL_PEND	1	   /* STA is trying to associate */
+#define	AR_PCICFG_LEDCTL_ASSOC	2	   /* STA is associated */
+#define	AR_PCICFG_LEDCTL_S	5
+#define	AR_PCICFG_PCI_BUS_SEL	0x00000380 /* PCI observation bus mux select */
+#define	AR_PCICFG_DIS_CBE_FIX	0x00000400 /* Disable fix for bad PCI CBE# generation */
+#define	AR_PCICFG_SL_INTEN	0x00000800 /* enable interrupt line assertion when asleep */
+#define	AR_PCICFG_RETRYFIXEN	0x00001000 /* Enable PCI core retry fix */
+#define	AR_PCICFG_SL_INPEN	0x00002000 /* Force asleep when an interrupt is pending */
+#define	AR_PCICFG_RESV1		0x0000C000 /* Reserved */
+#define	AR_PCICFG_SPWR_DN	0x00010000 /* mask for sleep/awake indication */
+#define	AR_PCICFG_LEDMODE	0x000E0000 /* LED mode */
+#define	AR_PCICFG_LEDMODE_PROP	0	   /* Blink prop to filtered tx/rx */
+#define	AR_PCICFG_LEDMODE_RPROP	1	   /* Blink prop to unfiltered tx/rx */
+#define	AR_PCICFG_LEDMODE_SPLIT	2	   /* Blink power for tx/net for rx */
+#define	AR_PCICFG_LEDMODE_RAND	3	   /* Blink randomly */
+/* NB: s/w led control present in Hainan 1.1 and above */
+#define	AR_PCICFG_LEDMODE_OFF	4	   /* s/w control + both led's off */
+#define	AR_PCICFG_LEDMODE_POWON	5	   /* s/w control + power led on */
+#define	AR_PCICFG_LEDMODE_NETON	6	   /* s/w control + network led on */
+#define	AR_PCICFG_LEDMODE_S	17
+#define	AR_PCICFG_LEDBLINK	0x00700000 /* LED blink threshold select */
+#define	AR_PCICFG_LEDBLINK_S	20
+#define	AR_PCICFG_LEDSLOW	0x00800000 /* LED slowest blink rate mode */
+#define	AR_PCICFG_LEDSLOW_S	23
+#define	AR_PCICFG_SCLK_RATE_IND 0x03000000 /* Sleep clock rate */
+#define	AR_PCICFG_SCLK_RATE_IND_S 24
+#define	AR_PCICFG_RESV2		0xFC000000 /* Reserved */
+
+#define	AR_GPIOCR_CR_SHIFT	2          /* Each CR is 2 bits */
+#define	AR_GPIOCR_CR_N(_g)	(0 << (AR_GPIOCR_CR_SHIFT * (_g)))
+#define	AR_GPIOCR_CR_0(_g)	(1 << (AR_GPIOCR_CR_SHIFT * (_g)))
+#define	AR_GPIOCR_CR_1(_g)	(2 << (AR_GPIOCR_CR_SHIFT * (_g)))
+#define	AR_GPIOCR_CR_A(_g)	(3 << (AR_GPIOCR_CR_SHIFT * (_g)))
+#define	AR_GPIOCR_INT_SHIFT	12         /* Interrupt select field shifter */
+#define	AR_GPIOCR_INT(_g)	((_g) << AR_GPIOCR_INT_SHIFT)
+#define	AR_GPIOCR_INT_MASK	0x00007000 /* Interrupt select field mask */
+#define	AR_GPIOCR_INT_ENA	0x00008000 /* Enable GPIO Interrupt */
+#define	AR_GPIOCR_INT_SELL	0x00000000 /* Generate int if pin is low */
+#define	AR_GPIOCR_INT_SELH	0x00010000 /* Generate int if pin is high */
+#define	AR_GPIOCR_INT_SEL	AR_GPIOCR_INT_SELH
+
+#define	AR_SREV_ID		0x000000FF /* Mask to read SREV info */
+#define	AR_SREV_ID_S		4	   /* Mask to shift Major Rev Info */
+#define	AR_SREV_REVISION	0x0000000F /* Mask for Chip revision level */
+#define	AR_SREV_REVISION_MIN	0	   /* lowest revision level */
+#define	AR_SREV_REVISION_MAX	0xF	   /* highest revision level */
+#define	AR_SREV_FPGA		1
+#define	AR_SREV_D2PLUS		2
+#define	AR_SREV_D2PLUS_MS	3	/* metal spin */
+#define	AR_SREV_CRETE		4
+#define	AR_SREV_CRETE_MS	5	/* FCS metal spin */
+#define	AR_SREV_CRETE_MS23	7	/* 2.3 metal spin (6 skipped) */
+#define	AR_SREV_CRETE_23	8	/* 2.3 full tape out */
+#define	AR_SREV_GRIFFIN_LITE	8
+#define	AR_SREV_HAINAN		9
+#define	AR_SREV_CONDOR		11
+#define	AR_SREV_VERSION	0x000000F0 /* Mask for Chip version */
+#define	AR_SREV_VERSION_CRETE	0
+#define	AR_SREV_VERSION_MAUI_1	1
+#define	AR_SREV_VERSION_MAUI_2	2
+#define	AR_SREV_VERSION_SPIRIT	3
+#define	AR_SREV_VERSION_OAHU	4
+#define	AR_SREV_VERSION_VENICE	5
+#define	AR_SREV_VERSION_GRIFFIN	7
+#define	AR_SREV_VERSION_CONDOR	9
+#define	AR_SREV_VERSION_EAGLE	10
+#define	AR_SREV_VERSION_COBRA	11	
+#define	AR_SREV_2413		AR_SREV_VERSION_GRIFFIN
+#define	AR_SREV_5413	        AR_SREV_VERSION_EAGLE
+#define	AR_SREV_2415		AR_SREV_VERSION_COBRA
+#define	AR_SREV_5424		AR_SREV_VERSION_CONDOR
+#define	AR_SREV_2425		14	/* SWAN */
+#define	AR_SREV_2417		15	/* Nala */
+#define	AR_SREV_OAHU_ES		0	/* Engineering Sample */
+#define	AR_SREV_OAHU_PROD	2	/* Production */
+
+#define	AR_PHYREV_HAINAN	0x43
+#define	AR_ANALOG5REV_HAINAN	0x46
+
+#define	AR_RADIO_SREV_MAJOR	0xF0
+#define	AR_RADIO_SREV_MINOR	0x0F
+#define	AR_RAD5111_SREV_MAJOR	0x10	/* All current supported ar5211 5 GHz
+					   radios are rev 0x10 */
+#define	AR_RAD5111_SREV_PROD	0x15	/* Current production level radios */
+#define	AR_RAD2111_SREV_MAJOR	0x20	/* All current supported ar5211 2 GHz
+					   radios are rev 0x10 */
+#define	AR_RAD5112_SREV_MAJOR	0x30	/* 5112 Major Rev */
+#define AR_RAD5112_SREV_2_0     0x35    /* AR5112 Revision 2.0 */
+#define AR_RAD5112_SREV_2_1     0x36    /* AR5112 Revision 2.1 */
+#define	AR_RAD2112_SREV_MAJOR	0x40	/* 2112 Major Rev */
+#define AR_RAD2112_SREV_2_0     0x45    /* AR2112 Revision 2.0 */
+#define AR_RAD2112_SREV_2_1     0x46    /* AR2112 Revision 2.1 */
+#define AR_RAD2413_SREV_MAJOR	0x50	/* 2413 Major Rev */
+#define AR_RAD5413_SREV_MAJOR   0x60    /* 5413 Major Rev */
+#define AR_RAD2316_SREV_MAJOR	0x70	/* 2316 Major Rev */
+#define AR_RAD2317_SREV_MAJOR	0x80	/* 2317 Major Rev */
+#define AR_RAD5424_SREV_MAJOR   0xa0    /* Mostly same as 5413 Major Rev */
+
+#define	AR_PCIE_PMC_ENA_L1	0x01	/* enable PCIe core enter L1 when
+					   d2_sleep_en is asserted */
+#define	AR_PCIE_PMC_ENA_RESET	0x08	/* enable reset on link going down */
+
+/* EEPROM Registers in the MAC */
+#define	AR_EEPROM_CMD_READ	0x00000001
+#define	AR_EEPROM_CMD_WRITE	0x00000002
+#define	AR_EEPROM_CMD_RESET	0x00000004
+
+#define	AR_EEPROM_STS_READ_ERROR	0x00000001
+#define	AR_EEPROM_STS_READ_COMPLETE	0x00000002
+#define	AR_EEPROM_STS_WRITE_ERROR	0x00000004
+#define	AR_EEPROM_STS_WRITE_COMPLETE	0x00000008
+
+#define	AR_EEPROM_CFG_SIZE	0x00000003	/* size determination override */
+#define	AR_EEPROM_CFG_SIZE_AUTO		0
+#define	AR_EEPROM_CFG_SIZE_4KBIT	1
+#define	AR_EEPROM_CFG_SIZE_8KBIT	2
+#define	AR_EEPROM_CFG_SIZE_16KBIT	3
+#define	AR_EEPROM_CFG_DIS_WWRCL	0x00000004	/* Disable wait for write completion */
+#define	AR_EEPROM_CFG_CLOCK	0x00000018	/* clock rate control */
+#define	AR_EEPROM_CFG_CLOCK_S		3	/* clock rate control */
+#define	AR_EEPROM_CFG_CLOCK_156KHZ	0
+#define	AR_EEPROM_CFG_CLOCK_312KHZ	1
+#define	AR_EEPROM_CFG_CLOCK_625KHZ	2
+#define	AR_EEPROM_CFG_RESV0	0x000000E0	/* Reserved */
+#define	AR_EEPROM_CFG_PKEY	0x00FFFF00	/* protection key */
+#define	AR_EEPROM_CFG_PKEY_S	8
+#define	AR_EEPROM_CFG_EN_L	0x01000000	/* EPRM_EN_L setting */
+
+/* MAC PCU Registers */
+
+#define	AR_STA_ID1_SADH_MASK	0x0000FFFF /* upper 16 bits of MAC addr */
+#define	AR_STA_ID1_STA_AP	0x00010000 /* Device is AP */
+#define	AR_STA_ID1_ADHOC	0x00020000 /* Device is ad-hoc */
+#define	AR_STA_ID1_PWR_SAV	0x00040000 /* Power save reporting in
+					      self-generated frames */
+#define	AR_STA_ID1_KSRCHDIS	0x00080000 /* Key search disable */
+#define	AR_STA_ID1_PCF		0x00100000 /* Observe PCF */
+#define	AR_STA_ID1_USE_DEFANT	0x00200000 /* Use default antenna */
+#define	AR_STA_ID1_UPD_DEFANT	0x00400000 /* Update default antenna w/
+					      TX antenna */
+#define	AR_STA_ID1_RTS_USE_DEF	0x00800000 /* Use default antenna to send RTS */
+#define	AR_STA_ID1_ACKCTS_6MB	0x01000000 /* Use 6Mb/s rate for ACK & CTS */
+#define	AR_STA_ID1_BASE_RATE_11B 0x02000000/* Use 11b base rate for ACK & CTS */
+#define	AR_STA_ID1_USE_DA_SG	0x04000000 /* Use default antenna for
+					      self-generated frames */
+#define	AR_STA_ID1_CRPT_MIC_ENABLE	0x08000000 /* Enable Michael */
+#define	AR_STA_ID1_KSRCH_MODE	0x10000000 /* Look-up key when keyID != 0 */
+#define	AR_STA_ID1_PRE_SEQNUM	0x20000000 /* Preserve s/w sequence number */
+#define	AR_STA_ID1_CBCIV_ENDIAN	0x40000000
+#define	AR_STA_ID1_MCAST_KSRCH	0x80000000 /* Do keycache search for mcast */
+
+#define	AR_BSS_ID1_U16		0x0000FFFF /* Upper 16 bits of BSSID */
+#define	AR_BSS_ID1_AID		0xFFFF0000 /* Association ID */
+#define	AR_BSS_ID1_AID_S	16
+
+#define	AR_SLOT_TIME_MASK	0x000007FF /* Slot time mask */
+
+#define	AR_TIME_OUT_ACK		0x00003FFF /* ACK time-out */
+#define	AR_TIME_OUT_ACK_S	0
+#define	AR_TIME_OUT_CTS		0x3FFF0000 /* CTS time-out */
+#define	AR_TIME_OUT_CTS_S	16
+
+#define	AR_RSSI_THR_MASK	0x000000FF /* Beacon RSSI warning threshold */
+#define	AR_RSSI_THR_BM_THR	0x0000FF00 /* Missed beacon threshold */
+#define	AR_RSSI_THR_BM_THR_S	8
+
+#define	AR_USEC_USEC		0x0000007F /* clock cycles in 1 usec */
+#define	AR_USEC_USEC_S		0
+#define	AR_USEC_USEC32		0x00003F80 /* 32MHz clock cycles in 1 usec */
+#define	AR_USEC_USEC32_S	7
+
+#define AR5212_USEC_TX_LAT_M    0x007FC000      /* Tx latency */
+#define AR5212_USEC_TX_LAT_S    14
+#define AR5212_USEC_RX_LAT_M    0x1F800000      /* Rx latency */
+#define AR5212_USEC_RX_LAT_S    23
+
+#define	AR_BEACON_PERIOD	0x0000FFFF /* Beacon period mask in TU/msec */
+#define	AR_BEACON_PERIOD_S	0
+#define	AR_BEACON_TIM		0x007F0000 /* byte offset of TIM start */
+#define	AR_BEACON_TIM_S		16
+#define	AR_BEACON_EN		0x00800000 /* Beacon enable */
+#define	AR_BEACON_RESET_TSF	0x01000000 /* Clear TSF to 0 */
+
+#define	AR_RX_NONE		0x00000000 /* Disallow all frames */
+#define	AR_RX_UCAST		0x00000001 /* Allow unicast frames */
+#define	AR_RX_MCAST		0x00000002 /* Allow multicast frames */
+#define	AR_RX_BCAST		0x00000004 /* Allow broadcast frames */
+#define	AR_RX_CONTROL		0x00000008 /* Allow control frames */
+#define	AR_RX_BEACON		0x00000010 /* Allow beacon frames */
+#define	AR_RX_PROM		0x00000020 /* Promiscuous mode, all packets */
+#define	AR_RX_PROBE_REQ		0x00000080 /* Allow probe request frames */
+
+#define	AR_DIAG_CACHE_ACK	0x00000001 /* No ACK if no valid key found */
+#define	AR_DIAG_ACK_DIS		0x00000002 /* Disable ACK generation */
+#define	AR_DIAG_CTS_DIS		0x00000004 /* Disable CTS generation */
+#define	AR_DIAG_ENCRYPT_DIS	0x00000008 /* Disable encryption */
+#define	AR_DIAG_DECRYPT_DIS	0x00000010 /* Disable decryption */
+#define	AR_DIAG_RX_DIS		0x00000020 /* Disable receive */
+#define	AR_DIAG_CORR_FCS	0x00000080 /* Corrupt FCS */
+#define	AR_DIAG_CHAN_INFO	0x00000100 /* Dump channel info */
+#define	AR_DIAG_EN_SCRAMSD	0x00000200 /* Enable fixed scrambler seed */
+#define	AR_DIAG_SCRAM_SEED	0x0001FC00 /* Fixed scrambler seed */
+#define	AR_DIAG_SCRAM_SEED_S	10
+#define	AR_DIAG_FRAME_NV0	0x00020000 /* Accept frames of non-zero
+					      protocol version */
+#define	AR_DIAG_OBS_PT_SEL	0x000C0000 /* Observation point select */
+#define	AR_DIAG_OBS_PT_SEL_S	18
+#define AR_DIAG_RX_CLR_HI	0x00100000 /* Force rx_clear high */
+#define AR_DIAG_IGNORE_CS	0x00200000 /* Force virtual carrier sense */
+#define AR_DIAG_CHAN_IDLE	0x00400000 /* Force channel idle high */
+#define AR_DIAG_PHEAR_ME	0x00800000 /* Uses framed and wait_wep in the pherr_enable_eifs if set to 0 */
+
+#define	AR_SLEEP1_NEXT_DTIM	0x0007ffff /* Abs. time(1/8TU) for next DTIM */
+#define	AR_SLEEP1_NEXT_DTIM_S	0
+#define	AR_SLEEP1_ASSUME_DTIM	0x00080000 /* Assume DTIM present on missent beacon */
+#define	AR_SLEEP1_ENH_SLEEP_ENA	0x00100000 /* Enable enhanced sleep logic */
+#define	AR_SLEEP1_CAB_TIMEOUT	0xff000000 /* CAB timeout(TU) */
+#define	AR_SLEEP1_CAB_TIMEOUT_S	24
+
+#define	AR_SLEEP2_NEXT_TIM	0x0007ffff /* Abs. time(1/8TU) for next DTIM */
+#define	AR_SLEEP2_NEXT_TIM_S	0
+#define	AR_SLEEP2_BEACON_TIMEOUT	0xff000000 /* Beacon timeout(TU) */
+#define	AR_SLEEP2_BEACON_TIMEOUT_S	24
+
+#define	AR_SLEEP3_TIM_PERIOD	0x0000ffff /* Tim/Beacon period (TU) */
+#define	AR_SLEEP3_TIM_PERIOD_S	0
+#define	AR_SLEEP3_DTIM_PERIOD	0xffff0000 /* DTIM period (TU) */
+#define	AR_SLEEP3_DTIM_PERIOD_S	16
+
+#define	AR_TPC_ACK		0x0000003f /* ack frames */
+#define	AR_TPC_ACK_S		0
+#define	AR_TPC_CTS		0x00003f00 /* cts frames */
+#define	AR_TPC_CTS_S		8
+#define	AR_TPC_CHIRP		0x003f0000 /* chirp frames */
+#define	AR_TPC_CHIRP_S		16
+#define AR_TPC_DOPPLER          0x0f000000 /* doppler chirp span */
+#define AR_TPC_DOPPLER_S        24
+
+#define	AR_PHY_ERR_RADAR	0x00000020	/* Radar signal */
+#define	AR_PHY_ERR_OFDM_TIMING	0x00020000	/* False detect for OFDM */
+#define	AR_PHY_ERR_CCK_TIMING	0x02000000	/* False detect for CCK */
+
+#define	AR_TSF_PARM_INCREMENT	0x000000ff
+#define	AR_TSF_PARM_INCREMENT_S	0
+
+#define AR_NOACK_2BIT_VALUE    0x0000000f
+#define AR_NOACK_2BIT_VALUE_S  0
+#define AR_NOACK_BIT_OFFSET     0x00000070
+#define AR_NOACK_BIT_OFFSET_S   4
+#define AR_NOACK_BYTE_OFFSET    0x00000180
+#define AR_NOACK_BYTE_OFFSET_S  7
+
+#define	AR_MISC_MODE_BSSID_MATCH_FORCE  0x1	/* Force BSSID match */
+#define	AR_MISC_MODE_ACKSIFS_MEMORY     0x2	/* ACKSIFS use contents of Rate */
+#define	AR_MISC_MODE_MIC_NEW_LOC_ENABLE 0x4	/* Xmit Michael Key same as Rcv */
+#define	AR_MISC_MODE_TX_ADD_TSF         0x8	/* Beacon/Probe-Rsp timestamp add (not replace) */
+
+#define	AR_KEYTABLE_KEY0(_n)	(AR_KEYTABLE(_n) + 0)	/* key bit 0-31 */
+#define	AR_KEYTABLE_KEY1(_n)	(AR_KEYTABLE(_n) + 4)	/* key bit 32-47 */
+#define	AR_KEYTABLE_KEY2(_n)	(AR_KEYTABLE(_n) + 8)	/* key bit 48-79 */
+#define	AR_KEYTABLE_KEY3(_n)	(AR_KEYTABLE(_n) + 12)	/* key bit 80-95 */
+#define	AR_KEYTABLE_KEY4(_n)	(AR_KEYTABLE(_n) + 16)	/* key bit 96-127 */
+#define	AR_KEYTABLE_TYPE(_n)	(AR_KEYTABLE(_n) + 20)	/* key type */
+#define	AR_KEYTABLE_TYPE_40	0x00000000	/* WEP 40 bit key */
+#define	AR_KEYTABLE_TYPE_104	0x00000001	/* WEP 104 bit key */
+#define	AR_KEYTABLE_TYPE_128	0x00000003	/* WEP 128 bit key */
+#define	AR_KEYTABLE_TYPE_TKIP	0x00000004	/* TKIP and Michael */
+#define	AR_KEYTABLE_TYPE_AES	0x00000005	/* AES/OCB 128 bit key */
+#define	AR_KEYTABLE_TYPE_CCM	0x00000006	/* AES/CCM 128 bit key */
+#define	AR_KEYTABLE_TYPE_CLR	0x00000007	/* no encryption */
+#define	AR_KEYTABLE_ANT		0x00000008	/* previous transmit antenna */
+#define	AR_KEYTABLE_MAC0(_n)	(AR_KEYTABLE(_n) + 24)	/* MAC address 1-32 */
+#define	AR_KEYTABLE_MAC1(_n)	(AR_KEYTABLE(_n) + 28)	/* MAC address 33-47 */
+#define	AR_KEYTABLE_VALID	0x00008000	/* key and MAC address valid */
+
+/* Compress settings */
+#define AR_CCFG_WIN_M           0x00000007 /* mask for AR_CCFG_WIN size */
+#define AR_CCFG_MIB_INT_EN      0x00000008 /* compression performance MIB counter int enable */
+#define AR_CCUCFG_RESET_VAL     0x00100200 /* the should be reset value */
+#define AR_CCUCFG_CATCHUP_EN    0x00000001 /* Compression catchup enable */
+#define AR_DCM_D_EN             0x00000001 /* all direct frames to be decompressed */
+#define AR_COMPRESSION_WINDOW_SIZE      4096 /* default comp. window size */
+
+#endif /* _DEV_AR5212REG_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5311reg.h b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5311reg.h
new file mode 100644
index 0000000..efb8568
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5311reg.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5311reg.h,v 1.3 2008/10/06 18:32:50 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5311REG_H_
+#define _DEV_ATH_AR5311REG_H_
+
+/*
+ * Definitions for the Atheros 5311 chipset.
+ */
+#define	AR5311_QDCLKGATE	0x005c	/* MAC QCU/DCU clock gating control */
+#define	AR5311_QDCLKGATE_QCU_M	0x0000FFFF /* QCU clock disable */
+#define	AR5311_QDCLKGATE_DCU_M	0x07FF0000 /* DCU clock disable */
+
+#define	AR5311_RXCFG_DEF_RX_ANTENNA	0x00000008 /* Default Receive Antenna */
+
+/*
+ * NOTE: MAC_5211/MAC_5311 difference
+ * On Oahu the TX latency field has increased from 6 bits to 9 bits.
+ * The RX latency field is unchanged but is shifted over 3 bits.
+ */
+#define	AR5311_USEC_TX_LAT_M	0x000FC000 /* tx latency (usec) */
+#define	AR5311_USEC_TX_LAT_S	14
+#define	AR5311_USEC_RX_LAT_M	0x03F00000 /* rx latency (usec) */
+#define	AR5311_USEC_RX_LAT_S	20
+
+/*
+ * NOTE: MAC_5211/MAC_5311 difference
+ * On Maui2/Spirit the frame sequence number is controlled per DCU.
+ * On Oahu the frame sequence number is global across all DCUs and
+ * is controlled
+ */
+#define	AR5311_D_MISC_SEQ_NUM_CONTROL	0x01000000 /* seq num local or global */
+#define	AR5311_DIAG_USE_ECO	0x00000400	/* "super secret" enable ECO */
+
+#endif /* _DEV_ATH_AR5311REG_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5413.c b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5413.c
new file mode 100644
index 0000000..ecf8538
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5212/ar5413.c
@@ -0,0 +1,797 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5413.c,v 1.8 2008/11/15 22:15:46 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ah_eeprom_v3.h"
+
+#include "ar5212/ar5212.h"
+#include "ar5212/ar5212reg.h"
+#include "ar5212/ar5212phy.h"
+
+#define AH_5212_5413
+#include "ar5212/ar5212.ini"
+
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+
+struct ar5413State {
+	RF_HAL_FUNCS	base;		/* public state, must be first */
+	uint16_t	pcdacTable[PWR_TABLE_SIZE_2413];
+
+	uint32_t	Bank1Data[N(ar5212Bank1_5413)];
+	uint32_t	Bank2Data[N(ar5212Bank2_5413)];
+	uint32_t	Bank3Data[N(ar5212Bank3_5413)];
+	uint32_t	Bank6Data[N(ar5212Bank6_5413)];
+	uint32_t	Bank7Data[N(ar5212Bank7_5413)];
+
+	/*
+	 * Private state for reduced stack usage.
+	 */
+	/* filled out Vpd table for all pdGains (chanL) */
+	uint16_t vpdTable_L[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (chanR) */
+	uint16_t vpdTable_R[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+	/* filled out Vpd table for all pdGains (interpolated) */
+	uint16_t vpdTable_I[MAX_NUM_PDGAINS_PER_CHANNEL]
+			    [MAX_PWR_RANGE_IN_HALF_DB];
+};
+#define	AR5413(ah)	((struct ar5413State *) AH5212(ah)->ah_rfHal)
+
+extern	void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+		uint32_t numBits, uint32_t firstBit, uint32_t column);
+
+static void
+ar5413WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+	int writes)
+{
+	HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5413, modesIndex, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212Common_5413, 1, writes);
+	HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5413, freqIndex, writes);
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ */
+static HAL_BOOL
+ar5413SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t channelSel  = 0;
+	uint32_t bModeSynth  = 0;
+	uint32_t aModeRefSel = 0;
+	uint32_t reg32       = 0;
+	uint16_t freq;
+
+	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+
+	if (chan->channel < 4800) {
+		uint32_t txctl;
+
+		if (((chan->channel - 2192) % 5) == 0) {
+			channelSel = ((chan->channel - 672) * 2 - 3040)/10;
+			bModeSynth = 0;
+		} else if (((chan->channel - 2224) % 5) == 0) {
+			channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
+			bModeSynth = 1;
+		} else {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: invalid channel %u MHz\n",
+			    __func__, chan->channel);
+			return AH_FALSE;
+		}
+
+		channelSel = (channelSel << 2) & 0xff;
+		channelSel = ath_hal_reverseBits(channelSel, 8);
+
+		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+		if (chan->channel == 2484) {
+			/* Enable channel spreading for channel 14 */
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+		}
+	} else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
+		freq = chan->channel - 2; /* Align to even 5MHz raster */
+		channelSel = ath_hal_reverseBits(
+			(uint32_t)(((freq - 4800)*10)/25 + 1), 8);
+            	aModeRefSel = ath_hal_reverseBits(0, 2);
+	} else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 20 << 2), 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else if ((chan->channel % 10) == 0) {
+		channelSel = ath_hal_reverseBits(
+			((chan->channel - 4800) / 10 << 1), 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else if ((chan->channel % 5) == 0) {
+		channelSel = ath_hal_reverseBits(
+			(chan->channel - 4800) / 5, 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
+		    __func__, chan->channel);
+		return AH_FALSE;
+	}
+
+	reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
+			(1 << 12) | 0x1;
+	OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
+
+	reg32 >>= 8;
+	OS_REG_WRITE(ah, AR_PHY(0x36), reg32 & 0x7f);
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ *
+ * REQUIRES: Access to the analog rf device
+ */
+static HAL_BOOL
+ar5413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+#define	RF_BANK_SETUP(_priv, _ix, _col) do {				    \
+	int i;								    \
+	for (i = 0; i < N(ar5212Bank##_ix##_5413); i++)			    \
+		(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_5413[i][_col];\
+} while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	uint16_t ob5GHz = 0, db5GHz = 0;	
+	uint16_t ob2GHz = 0, db2GHz = 0;
+	struct ar5413State *priv = AR5413(ah);
+	int regWrites = 0;
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM,
+	    "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
+	    __func__, chan->channel, chan->channelFlags, modesIndex);
+
+	HALASSERT(priv != AH_NULL);
+
+	/* Setup rf parameters */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+	case CHANNEL_T:
+		if (chan->channel > 4000 && chan->channel < 5260) {
+			ob5GHz = ee->ee_ob1;
+			db5GHz = ee->ee_db1;
+		} else if (chan->channel >= 5260 && chan->channel < 5500) {
+			ob5GHz = ee->ee_ob2;
+			db5GHz = ee->ee_db2;
+		} else if (chan->channel >= 5500 && chan->channel < 5725) {
+			ob5GHz = ee->ee_ob3;
+			db5GHz = ee->ee_db3;
+		} else if (chan->channel >= 5725) {
+			ob5GHz = ee->ee_ob4;
+			db5GHz = ee->ee_db4;
+		} else {
+			/* XXX else */
+		}
+		break;
+	case CHANNEL_B:
+		ob2GHz = ee->ee_obFor24;
+		db2GHz = ee->ee_dbFor24;
+		break;
+	case CHANNEL_G:
+	case CHANNEL_108G:
+		ob2GHz = ee->ee_obFor24g;
+		db2GHz = ee->ee_dbFor24g;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/* Bank 1 Write */
+	RF_BANK_SETUP(priv, 1, 1);
+
+	/* Bank 2 Write */
+	RF_BANK_SETUP(priv, 2, modesIndex);
+
+	/* Bank 3 Write */
+	RF_BANK_SETUP(priv, 3, modesIndex);
+
+	/* Bank 6 Write */
+	RF_BANK_SETUP(priv, 6, modesIndex);
+
+    	/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
+	if (IS_CHAN_2GHZ(chan)) {
+        	ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 241, 0);
+        	ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 238, 0);
+
+			/* TODO - only for Eagle 1.0 2GHz - remove for production */
+			/* XXX: but without this bit G doesn't work. */
+			ar5212ModifyRfBuffer(priv->Bank6Data, 1 , 1, 291, 2);
+
+			/* Optimum value for rf_pwd_iclobuf2G for PCIe chips only */
+			if (IS_PCIE(ah)) {
+				ar5212ModifyRfBuffer(priv->Bank6Data, ath_hal_reverseBits(6, 3),
+						 3, 131, 3);
+			}
+	} else {
+        	ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 247, 0);
+        	ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 244, 0);
+
+	}
+
+	/* Bank 7 Setup */
+	RF_BANK_SETUP(priv, 7, modesIndex);
+
+	/* Write Analog registers */
+	HAL_INI_WRITE_BANK(ah, ar5212Bank1_5413, priv->Bank1Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank2_5413, priv->Bank2Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank3_5413, priv->Bank3Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank6_5413, priv->Bank6Data, regWrites);
+	HAL_INI_WRITE_BANK(ah, ar5212Bank7_5413, priv->Bank7Data, regWrites);
+
+	/* Now that we have reprogrammed rfgain value, clear the flag. */
+	ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
+
+	return AH_TRUE;
+#undef	RF_BANK_SETUP
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar5413GetRfBank(struct ath_hal *ah, int bank)
+{
+	struct ar5413State *priv = AR5413(ah);
+
+	HALASSERT(priv != AH_NULL);
+	switch (bank) {
+	case 1: return priv->Bank1Data;
+	case 2: return priv->Bank2Data;
+	case 3: return priv->Bank3Data;
+	case 6: return priv->Bank6Data;
+	case 7: return priv->Bank7Data;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+	    __func__, bank);
+	return AH_NULL;
+}
+
+/*
+ * Return indices surrounding the value in sorted integer lists.
+ *
+ * NB: the input list is assumed to be sorted in ascending order
+ */
+static void
+GetLowerUpperIndex(int16_t v, const uint16_t *lp, uint16_t listSize,
+                          uint32_t *vlo, uint32_t *vhi)
+{
+	int16_t target = v;
+	const uint16_t *ep = lp+listSize;
+	const uint16_t *tp;
+
+	/*
+	 * Check first and last elements for out-of-bounds conditions.
+	 */
+	if (target < lp[0]) {
+		*vlo = *vhi = 0;
+		return;
+	}
+	if (target >= ep[-1]) {
+		*vlo = *vhi = listSize - 1;
+		return;
+	}
+
+	/* look for value being near or between 2 values in list */
+	for (tp = lp; tp < ep; tp++) {
+		/*
+		 * If value is close to the current value of the list
+		 * then target is not between values, it is one of the values
+		 */
+		if (*tp == target) {
+			*vlo = *vhi = tp - (const uint16_t *) lp;
+			return;
+		}
+		/*
+		 * Look for value being between current value and next value
+		 * if so return these 2 values
+		 */
+		if (target < tp[1]) {
+			*vlo = tp - (const uint16_t *) lp;
+			*vhi = *vlo + 1;
+			return;
+		}
+	}
+}
+
+/*
+ * Fill the Vpdlist for indices Pmax-Pmin
+ */
+static HAL_BOOL
+ar5413FillVpdTable(uint32_t pdGainIdx, int16_t Pmin, int16_t  Pmax,
+		   const int16_t *pwrList, const uint16_t *VpdList,
+		   uint16_t numIntercepts,
+		   uint16_t retVpdList[][64])
+{
+	uint16_t ii, jj, kk;
+	int16_t currPwr = (int16_t)(2*Pmin);
+	/* since Pmin is pwr*2 and pwrList is 4*pwr */
+	uint32_t  idxL, idxR;
+
+	ii = 0;
+	jj = 0;
+
+	if (numIntercepts < 2)
+		return AH_FALSE;
+
+	while (ii <= (uint16_t)(Pmax - Pmin)) {
+		GetLowerUpperIndex(currPwr, (const uint16_t *) pwrList,
+				   numIntercepts, &(idxL), &(idxR));
+		if (idxR < 1)
+			idxR = 1;			/* extrapolate below */
+		if (idxL == (uint32_t)(numIntercepts - 1))
+			idxL = numIntercepts - 2;	/* extrapolate above */
+		if (pwrList[idxL] == pwrList[idxR])
+			kk = VpdList[idxL];
+		else
+			kk = (uint16_t)
+				(((currPwr - pwrList[idxL])*VpdList[idxR]+ 
+				  (pwrList[idxR] - currPwr)*VpdList[idxL])/
+				 (pwrList[idxR] - pwrList[idxL]));
+		retVpdList[pdGainIdx][ii] = kk;
+		ii++;
+		currPwr += 2;				/* half dB steps */
+	}
+
+	return AH_TRUE;
+}
+
+/*
+ * Returns interpolated or the scaled up interpolated value
+ */
+static int16_t
+interpolate_signed(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+	int16_t targetLeft, int16_t targetRight)
+{
+	int16_t rv;
+
+	if (srcRight != srcLeft) {
+		rv = ((target - srcLeft)*targetRight +
+		      (srcRight - target)*targetLeft) / (srcRight - srcLeft);
+	} else {
+		rv = targetLeft;
+	}
+	return rv;
+}
+
+/*
+ * Uses the data points read from EEPROM to reconstruct the pdadc power table
+ * Called by ar5413SetPowerTable()
+ */
+static int 
+ar5413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
+		const RAW_DATA_STRUCT_2413 *pRawDataset,
+		uint16_t pdGainOverlap_t2, 
+		int16_t  *pMinCalPower, uint16_t pPdGainBoundaries[], 
+		uint16_t pPdGainValues[], uint16_t pPDADCValues[]) 
+{
+	struct ar5413State *priv = AR5413(ah);
+#define	VpdTable_L	priv->vpdTable_L
+#define	VpdTable_R	priv->vpdTable_R
+#define	VpdTable_I	priv->vpdTable_I
+	uint32_t ii, jj, kk;
+	int32_t ss;/* potentially -ve index for taking care of pdGainOverlap */
+	uint32_t idxL, idxR;
+	uint32_t numPdGainsUsed = 0;
+	/* 
+	 * If desired to support -ve power levels in future, just
+	 * change pwr_I_0 to signed 5-bits.
+	 */
+	int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on. */
+	int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
+	/* to accomodate -ve power levels later on */
+	uint16_t numVpd = 0;
+	uint16_t Vpd_step;
+	int16_t tmpVal ; 
+	uint32_t sizeCurrVpdTable, maxIndex, tgtIndex;
+    
+	/* Get upper lower index */
+	GetLowerUpperIndex(channel, pRawDataset->pChannels,
+				 pRawDataset->numChannels, &(idxL), &(idxR));
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			pPdGainValues[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pd_gain;
+			Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0];
+			if (Pmin_t2[numPdGainsUsed] >pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]) {
+				Pmin_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0];
+			}
+			Pmin_t2[numPdGainsUsed] = (int16_t)
+				(Pmin_t2[numPdGainsUsed] / 2);
+			Pmax_t2[numPdGainsUsed] = pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			if (Pmax_t2[numPdGainsUsed] > pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1])
+				Pmax_t2[numPdGainsUsed] = 
+					pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[numVpd-1];
+			Pmax_t2[numPdGainsUsed] = (int16_t)(Pmax_t2[numPdGainsUsed] / 2);
+			ar5413FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].pwr_t4[0]), 
+					   &(pRawDataset->pDataPerChannel[idxL].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_L
+					   );
+			ar5413FillVpdTable(
+					   numPdGainsUsed, Pmin_t2[numPdGainsUsed], Pmax_t2[numPdGainsUsed], 
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].pwr_t4[0]),
+					   &(pRawDataset->pDataPerChannel[idxR].pDataPerPDGain[jj].Vpd[0]), numVpd, VpdTable_R
+					   );
+			for (kk = 0; kk < (uint16_t)(Pmax_t2[numPdGainsUsed] - Pmin_t2[numPdGainsUsed]); kk++) {
+				VpdTable_I[numPdGainsUsed][kk] = 
+					interpolate_signed(
+							   channel, pRawDataset->pChannels[idxL], pRawDataset->pChannels[idxR],
+							   (int16_t)VpdTable_L[numPdGainsUsed][kk], (int16_t)VpdTable_R[numPdGainsUsed][kk]);
+			}
+			/* fill VpdTable_I for this pdGain */
+			numPdGainsUsed++;
+		}
+		/* if this pdGain is used */
+	}
+
+	*pMinCalPower = Pmin_t2[0];
+	kk = 0; /* index for the final table */
+	for (ii = 0; ii < numPdGainsUsed; ii++) {
+		if (ii == (numPdGainsUsed - 1))
+			pPdGainBoundaries[ii] = Pmax_t2[ii] +
+				PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB;
+		else 
+			pPdGainBoundaries[ii] = (uint16_t)
+				((Pmax_t2[ii] + Pmin_t2[ii+1]) / 2 );
+		if (pPdGainBoundaries[ii] > 63) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: clamp pPdGainBoundaries[%d] %d\n",
+			    __func__, ii, pPdGainBoundaries[ii]);/*XXX*/
+			pPdGainBoundaries[ii] = 63;
+		}
+
+		/* Find starting index for this pdGain */
+		if (ii == 0) 
+			ss = 0; /* for the first pdGain, start from index 0 */
+		else 
+			ss = (pPdGainBoundaries[ii-1] - Pmin_t2[ii]) - 
+				pdGainOverlap_t2;
+		Vpd_step = (uint16_t)(VpdTable_I[ii][1] - VpdTable_I[ii][0]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);
+		/*
+		 *-ve ss indicates need to extrapolate data below for this pdGain
+		 */
+		while (ss < 0) {
+			tmpVal = (int16_t)(VpdTable_I[ii][0] + ss*Vpd_step);
+			pPDADCValues[kk++] = (uint16_t)((tmpVal < 0) ? 0 : tmpVal);
+			ss++;
+		}
+
+		sizeCurrVpdTable = Pmax_t2[ii] - Pmin_t2[ii];
+		tgtIndex = pPdGainBoundaries[ii] + pdGainOverlap_t2 - Pmin_t2[ii];
+		maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
+
+		while (ss < (int16_t)maxIndex)
+			pPDADCValues[kk++] = VpdTable_I[ii][ss++];
+
+		Vpd_step = (uint16_t)(VpdTable_I[ii][sizeCurrVpdTable-1] -
+				       VpdTable_I[ii][sizeCurrVpdTable-2]);
+		Vpd_step = (uint16_t)((Vpd_step < 1) ? 1 : Vpd_step);           
+		/*
+		 * for last gain, pdGainBoundary == Pmax_t2, so will 
+		 * have to extrapolate
+		 */
+		if (tgtIndex > maxIndex) {	/* need to extrapolate above */
+			while(ss < (int16_t)tgtIndex) {
+				tmpVal = (uint16_t)
+					(VpdTable_I[ii][sizeCurrVpdTable-1] + 
+					 (ss-maxIndex)*Vpd_step);
+				pPDADCValues[kk++] = (tmpVal > 127) ? 
+					127 : tmpVal;
+				ss++;
+			}
+		}				/* extrapolated above */
+	}					/* for all pdGainUsed */
+
+	while (ii < MAX_NUM_PDGAINS_PER_CHANNEL) {
+		pPdGainBoundaries[ii] = pPdGainBoundaries[ii-1];
+		ii++;
+	}
+	while (kk < 128) {
+		pPDADCValues[kk] = pPDADCValues[kk-1];
+		kk++;
+	}
+
+	return numPdGainsUsed;
+#undef VpdTable_L
+#undef VpdTable_R
+#undef VpdTable_I
+}
+
+static HAL_BOOL
+ar5413SetPowerTable(struct ath_hal *ah,
+	int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan, 
+	uint16_t *rfXpdGain)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
+	uint16_t pdGainOverlap_t2;
+	int16_t minCalPower5413_t2;
+	uint16_t *pdadcValues = ahp->ah_pcdacTable;
+	uint16_t gainBoundaries[4];
+	uint32_t reg32, regoffset;
+	int i, numPdGainsUsed;
+#ifndef AH_USE_INIPDGAIN
+	uint32_t tpcrg1;
+#endif
+
+	HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
+	    __func__, chan->channel,chan->channelFlags);
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else {
+		HALASSERT(IS_CHAN_5GHZ(chan));
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11A];
+	}
+
+	pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
+					  AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
+    
+	numPdGainsUsed = ar5413getGainBoundariesAndPdadcsForPowers(ah,
+		chan->channel, pRawDataset, pdGainOverlap_t2,
+		&minCalPower5413_t2,gainBoundaries, rfXpdGain, pdadcValues);
+	HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
+
+#ifdef AH_USE_INIPDGAIN
+	/*
+	 * Use pd_gains curve from eeprom; Atheros always uses
+	 * the default curve from the ini file but some vendors
+	 * (e.g. Zcomax) want to override this curve and not
+	 * honoring their settings results in tx power 5dBm low.
+	 */
+	OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 
+			 (pRawDataset->pDataPerChannel[0].numPdGains - 1));
+#else
+	tpcrg1 = OS_REG_READ(ah, AR_PHY_TPCRG1);
+	tpcrg1 = (tpcrg1 &~ AR_PHY_TPCRG1_NUM_PD_GAIN)
+		  | SM(numPdGainsUsed-1, AR_PHY_TPCRG1_NUM_PD_GAIN);
+	switch (numPdGainsUsed) {
+	case 3:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING3;
+		tpcrg1 |= SM(rfXpdGain[2], AR_PHY_TPCRG1_PDGAIN_SETTING3);
+		/* fall thru... */
+	case 2:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING2;
+		tpcrg1 |= SM(rfXpdGain[1], AR_PHY_TPCRG1_PDGAIN_SETTING2);
+		/* fall thru... */
+	case 1:
+		tpcrg1 &= ~AR_PHY_TPCRG1_PDGAIN_SETTING1;
+		tpcrg1 |= SM(rfXpdGain[0], AR_PHY_TPCRG1_PDGAIN_SETTING1);
+		break;
+	}
+#ifdef AH_DEBUG
+	if (tpcrg1 != OS_REG_READ(ah, AR_PHY_TPCRG1))
+		HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: using non-default "
+		    "pd_gains (default 0x%x, calculated 0x%x)\n",
+		    __func__, OS_REG_READ(ah, AR_PHY_TPCRG1), tpcrg1);
+#endif
+	OS_REG_WRITE(ah, AR_PHY_TPCRG1, tpcrg1);
+#endif
+
+	/*
+	 * Note the pdadc table may not start at 0 dBm power, could be
+	 * negative or greater than 0.  Need to offset the power
+	 * values by the amount of minPower for griffin
+	 */
+	if (minCalPower5413_t2 != 0)
+		ahp->ah_txPowerIndexOffset = (int16_t)(0 - minCalPower5413_t2);
+	else
+		ahp->ah_txPowerIndexOffset = 0;
+
+	/* Finally, write the power values into the baseband power table */
+	regoffset = 0x9800 + (672 <<2); /* beginning of pdadc table in griffin */
+	for (i = 0; i < 32; i++) {
+		reg32 = ((pdadcValues[4*i + 0] & 0xFF) << 0)  | 
+			((pdadcValues[4*i + 1] & 0xFF) << 8)  |
+			((pdadcValues[4*i + 2] & 0xFF) << 16) |
+			((pdadcValues[4*i + 3] & 0xFF) << 24) ;        
+		OS_REG_WRITE(ah, regoffset, reg32);
+		regoffset += 4;
+	}
+
+	OS_REG_WRITE(ah, AR_PHY_TPCRG5, 
+		     SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 
+		     SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
+		     SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
+		     SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
+		     SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
+
+	return AH_TRUE;
+}
+
+static int16_t
+ar5413GetMinPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)
+{
+	uint32_t ii,jj;
+	uint16_t Pmin=0,numVpd;
+
+	for (ii = 0; ii < MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		jj = MAX_NUM_PDGAINS_PER_CHANNEL - ii - 1;
+		/* work backwards 'cause highest pdGain for lowest power */
+		numVpd = data->pDataPerPDGain[jj].numVpd;
+		if (numVpd > 0) {
+			Pmin = data->pDataPerPDGain[jj].pwr_t4[0];
+			return(Pmin);
+		}
+	}
+	return(Pmin);
+}
+
+static int16_t
+ar5413GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data)
+{
+	uint32_t ii;
+	uint16_t Pmax=0,numVpd;
+	
+	for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) {
+		/* work forwards cuase lowest pdGain for highest power */
+		numVpd = data->pDataPerPDGain[ii].numVpd;
+		if (numVpd > 0) {
+			Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
+			return(Pmax);
+		}
+	}
+	return(Pmax);
+}
+
+static HAL_BOOL
+ar5413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
+	int16_t *maxPow, int16_t *minPow)
+{
+	const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
+	const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
+	const RAW_DATA_PER_CHANNEL_2413 *data=AH_NULL;
+	uint16_t numChannels;
+	int totalD,totalF, totalMin,last, i;
+
+	*maxPow = 0;
+
+	if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
+	else if (IS_CHAN_B(chan))
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
+	else {
+		HALASSERT(IS_CHAN_5GHZ(chan));
+		pRawDataset = &ee->ee_rawDataset2413[headerInfo11A];
+	}
+
+	numChannels = pRawDataset->numChannels;
+	data = pRawDataset->pDataPerChannel;
+	
+	/* Make sure the channel is in the range of the TP values 
+	 *  (freq piers)
+	 */
+	if (numChannels < 1)
+		return(AH_FALSE);
+
+	if ((chan->channel < data[0].channelValue) ||
+	    (chan->channel > data[numChannels-1].channelValue)) {
+		if (chan->channel < data[0].channelValue) {
+			*maxPow = ar5413GetMaxPower(ah, &data[0]);
+			*minPow = ar5413GetMinPower(ah, &data[0]);
+			return(AH_TRUE);
+		} else {
+			*maxPow = ar5413GetMaxPower(ah, &data[numChannels - 1]);
+			*minPow = ar5413GetMinPower(ah, &data[numChannels - 1]);
+			return(AH_TRUE);
+		}
+	}
+
+	/* Linearly interpolate the power value now */
+	for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
+	     last = i++);
+	totalD = data[i].channelValue - data[last].channelValue;
+	if (totalD > 0) {
+		totalF = ar5413GetMaxPower(ah, &data[i]) - ar5413GetMaxPower(ah, &data[last]);
+		*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + 
+				     ar5413GetMaxPower(ah, &data[last])*totalD)/totalD);
+		totalMin = ar5413GetMinPower(ah, &data[i]) - ar5413GetMinPower(ah, &data[last]);
+		*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
+				     ar5413GetMinPower(ah, &data[last])*totalD)/totalD);
+		return(AH_TRUE);
+	} else {
+		if (chan->channel == data[i].channelValue) {
+			*maxPow = ar5413GetMaxPower(ah, &data[i]);
+			*minPow = ar5413GetMinPower(ah, &data[i]);
+			return(AH_TRUE);
+		} else
+			return(AH_FALSE);
+	}
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar5413RfDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(ahp->ah_rfHal != AH_NULL);
+	ath_hal_free(ahp->ah_rfHal);
+	ahp->ah_rfHal = AH_NULL;
+}
+
+/*
+ * Allocate memory for analog bank scratch buffers
+ * Scratch Buffer will be reinitialized every reset so no need to zero now
+ */
+static HAL_BOOL
+ar5413RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5413State *priv;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+
+	HALASSERT(ahp->ah_rfHal == AH_NULL);
+	priv = ath_hal_malloc(sizeof(struct ar5413State));
+	if (priv == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot allocate private state\n", __func__);
+		*status = HAL_ENOMEM;		/* XXX */
+		return AH_FALSE;
+	}
+	priv->base.rfDetach		= ar5413RfDetach;
+	priv->base.writeRegs		= ar5413WriteRegs;
+	priv->base.getRfBank		= ar5413GetRfBank;
+	priv->base.setChannel		= ar5413SetChannel;
+	priv->base.setRfRegs		= ar5413SetRfRegs;
+	priv->base.setPowerTable	= ar5413SetPowerTable;
+	priv->base.getChannelMaxMinPower = ar5413GetChannelMaxMinPower;
+	priv->base.getNfAdjust		= ar5212GetNfAdjust;
+
+	ahp->ah_pcdacTable = priv->pcdacTable;
+	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+	ahp->ah_rfHal = &priv->base;
+
+	return AH_TRUE;
+}
+
+static HAL_BOOL
+ar5413Probe(struct ath_hal *ah)
+{
+	return IS_5413(ah);
+}
+AH_RF(RF5413, ar5413Probe, ar5413RfAttach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312.h b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312.h
new file mode 100644
index 0000000..3eb1a16
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ar5312/ar5312.h,v 1.2.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#ifndef _ATH_AR5312_H_
+#define _ATH_AR5312_H_
+
+#include "ah_soc.h"
+#include "ar5212/ar5212.h"
+
+#define AR5312_UNIT(_ah) \
+	(((const struct ar531x_config *)((_ah)->ah_st))->unit)
+#define AR5312_BOARDCONFIG(_ah) \
+	(((const struct ar531x_config *)((_ah)->ah_st))->board)
+#define AR5312_RADIOCONFIG(_ah) \
+	(((const struct ar531x_config *)((_ah)->ah_st))->radio)
+
+#define	IS_5312_2_X(ah) \
+	(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && \
+	 (AH_PRIVATE(ah)->ah_macRev == 2 || AH_PRIVATE(ah)->ah_macRev == 7))
+#define IS_5315(ah) \
+	(AH_PRIVATE(ah)->ah_devid == AR5212_AR2315_REV6 || \
+	 AH_PRIVATE(ah)->ah_devid == AR5212_AR2315_REV7 || \
+	 AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1 || \
+	 AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)
+
+extern  HAL_BOOL ar5312IsInterruptPending(struct ath_hal *ah);
+
+/* AR5312 */
+extern	HAL_BOOL ar5312GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5312GpioCfgInput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5312GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
+extern	uint32_t ar5312GpioGet(struct ath_hal *ah, uint32_t gpio);
+extern	void ar5312GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
+
+/* AR2315+ */
+extern	HAL_BOOL ar5315GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5315GpioCfgInput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5315GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
+extern	uint32_t ar5315GpioGet(struct ath_hal *ah, uint32_t gpio);
+extern	void ar5315GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
+
+extern  void ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
+extern  HAL_BOOL ar5312DetectCardPresent(struct ath_hal *ah);
+extern  void ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
+extern  void ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
+extern  void ar5312DumpState(struct ath_hal *ah);
+extern  HAL_BOOL ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
+              HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status);
+extern  HAL_BOOL ar5312ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan);
+extern  HAL_BOOL ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
+                                    int setChip);
+extern  HAL_BOOL ar5312PhyDisable(struct ath_hal *ah);
+extern  HAL_BOOL ar5312Disable(struct ath_hal *ah);
+extern  HAL_BOOL ar5312MacReset(struct ath_hal *ah, unsigned int RCMask);
+extern  uint32_t ar5312GetPowerMode(struct ath_hal *ah);
+extern  HAL_BOOL ar5312GetPowerStatus(struct ath_hal *ah);
+
+/* BSP functions */
+extern	HAL_BOOL ar5312EepromRead(struct ath_hal *, u_int off, uint16_t *data);
+extern	HAL_BOOL ar5312EepromWrite(struct ath_hal *, u_int off, uint16_t data);
+
+#endif	/* _ATH_AR3212_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_attach.c b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_attach.c
new file mode 100644
index 0000000..60d3a0f
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_attach.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $FreeBSD: src/sys/dev/ath/ath_hal/ar5312/ar5312_attach.c,v 1.3.2.1.2.1 2009/04/15 03:14:26 kensmith Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5312/ar5312.h"
+#include "ar5312/ar5312reg.h"
+#include "ar5312/ar5312phy.h"
+
+/* Add static register initialization vectors */
+#define AH_5212_COMMON
+#include "ar5212/ar5212.ini"
+
+static  HAL_BOOL ar5312GetMacAddr(struct ath_hal *ah);
+
+static void
+ar5312AniSetup(struct ath_hal *ah)
+{
+	static const struct ar5212AniParams aniparams = {
+		.maxNoiseImmunityLevel	= 4,	/* levels 0..4 */
+		.totalSizeDesired	= { -41, -41, -48, -48, -48 },
+		.coarseHigh		= { -18, -18, -16, -14, -12 },
+		.coarseLow		= { -56, -56, -60, -60, -60 },
+		.firpwr			= { -72, -72, -75, -78, -80 },
+		.maxSpurImmunityLevel	= 2,
+		.cycPwrThr1		= { 2, 4, 6 },
+		.maxFirstepLevel	= 2,	/* levels 0..2 */
+		.firstep		= { 0, 4, 8 },
+		.ofdmTrigHigh		= 500,
+		.ofdmTrigLow		= 200,
+		.cckTrigHigh		= 200,
+		.cckTrigLow		= 100,
+		.rssiThrHigh		= 40,
+		.rssiThrLow		= 7,
+		.period			= 100,
+	};
+	ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
+}
+
+/*
+ * Attach for an AR5312 part.
+ */
+static struct ath_hal *
+ar5312Attach(uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH_NULL;
+	struct ath_hal *ah;
+	struct ath_hal_rf *rf;
+	uint32_t val;
+	uint16_t eeval;
+	HAL_STATUS ecode;
+
+	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
+		 __func__, sc, st, (void*) sh);
+
+	/* NB: memory is returned zero'd */
+	ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
+	if (ahp == AH_NULL) {
+		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+		    "%s: cannot allocate memory for state block\n", __func__);
+		*status = HAL_ENOMEM;
+		return AH_NULL;
+	}
+	ar5212InitState(ahp, devid, sc, st, sh, status);
+	ah = &ahp->ah_priv.h;
+
+	/* override 5212 methods for our needs */
+	ah->ah_reset			= ar5312Reset;
+	ah->ah_phyDisable		= ar5312PhyDisable;
+	ah->ah_setLedState		= ar5312SetLedState;
+	ah->ah_detectCardPresent	= ar5312DetectCardPresent;
+	ah->ah_setPowerMode		= ar5312SetPowerMode;
+	ah->ah_getPowerMode		= ar5312GetPowerMode;
+	ah->ah_isInterruptPending	= ar5312IsInterruptPending;
+
+	ahp->ah_priv.ah_eepromRead	= ar5312EepromRead;
+#ifdef AH_SUPPORT_WRITE_EEPROM
+	ahp->ah_priv.ah_eepromWrite	= ar5312EepromWrite;
+#endif
+#if ( AH_SUPPORT_2316 || AH_SUPPORT_2317)
+	if (IS_5315(ah)) {
+		ahp->ah_priv.ah_gpioCfgOutput	= ar5315GpioCfgOutput;
+		ahp->ah_priv.ah_gpioCfgInput	= ar5315GpioCfgInput;
+		ahp->ah_priv.ah_gpioGet		= ar5315GpioGet;
+		ahp->ah_priv.ah_gpioSet		= ar5315GpioSet;
+		ahp->ah_priv.ah_gpioSetIntr	= ar5315GpioSetIntr;
+	} else
+#endif
+	{
+		ahp->ah_priv.ah_gpioCfgOutput	= ar5312GpioCfgOutput;
+		ahp->ah_priv.ah_gpioCfgInput	= ar5312GpioCfgInput;
+		ahp->ah_priv.ah_gpioGet		= ar5312GpioGet;
+		ahp->ah_priv.ah_gpioSet		= ar5312GpioSet;
+		ahp->ah_priv.ah_gpioSetIntr	= ar5312GpioSetIntr;
+	}
+
+	ah->ah_gpioCfgInput		= ahp->ah_priv.ah_gpioCfgInput;
+	ah->ah_gpioCfgOutput		= ahp->ah_priv.ah_gpioCfgOutput;
+	ah->ah_gpioGet			= ahp->ah_priv.ah_gpioGet;
+	ah->ah_gpioSet			= ahp->ah_priv.ah_gpioSet;
+	ah->ah_gpioSetIntr		= ahp->ah_priv.ah_gpioSetIntr;
+
+	/* setup common ini data; rf backends handle remainder */
+	HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6);
+	HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2);
+
+	if (!ar5312ChipReset(ah, AH_NULL)) {	/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+#if ( AH_SUPPORT_2316 || AH_SUPPORT_2317)
+	if ((devid == AR5212_AR2315_REV6) ||
+	    (devid == AR5212_AR2315_REV7) ||
+	    (devid == AR5212_AR2317_REV1) ||
+	    (devid == AR5212_AR2317_REV2) ) {
+		val = ((OS_REG_READ(ah, (AR5315_RSTIMER_BASE -((uint32_t) sh)) + AR5315_WREV)) >> AR5315_WREV_S)
+			& AR5315_WREV_ID;
+		AH_PRIVATE(ah)->ah_macVersion = val >> AR5315_WREV_ID_S;
+		AH_PRIVATE(ah)->ah_macRev = val & AR5315_WREV_REVISION;
+		HALDEBUG(ah, HAL_DEBUG_ATTACH,
+		    "%s: Mac Chip Rev 0x%02x.%x\n" , __func__,
+		    AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev);
+	} else
+#endif
+	{
+		val = OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + 0x0020);
+		val = OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + 0x0080);
+		/* Read Revisions from Chips */
+		val = ((OS_REG_READ(ah, (AR5312_RSTIMER_BASE - ((uint32_t) sh)) + AR5312_WREV)) >> AR5312_WREV_S) & AR5312_WREV_ID;
+		AH_PRIVATE(ah)->ah_macVersion = val >> AR5312_WREV_ID_S;
+		AH_PRIVATE(ah)->ah_macRev = val & AR5312_WREV_REVISION;
+	}
+	/* XXX - THIS IS WRONG. NEEDS TO BE FIXED */
+	if (((AH_PRIVATE(ah)->ah_macVersion != AR_SREV_VERSION_VENICE &&
+              AH_PRIVATE(ah)->ah_macVersion != AR_SREV_VERSION_VENICE) ||
+             AH_PRIVATE(ah)->ah_macRev < AR_SREV_D2PLUS) &&
+              AH_PRIVATE(ah)->ah_macVersion != AR_SREV_VERSION_COBRA) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s: Mac Chip Rev 0x%02x.%x is not supported by "
+                         "this driver\n", __func__,
+                         AH_PRIVATE(ah)->ah_macVersion,
+                         AH_PRIVATE(ah)->ah_macRev);
+#endif
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+	}
+        
+	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
+        
+	if (!ar5212ChipTest(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
+		    __func__);
+		ecode = HAL_ESELFTEST;
+		goto bad;
+	}
+
+	/*
+	 * Set correct Baseband to analog shift
+	 * setting to access analog chips.
+	 */
+	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+        
+	/* Read Radio Chip Rev Extract */
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
+
+	rf = ath_hal_rfprobe(ah, &ecode);
+	if (rf == AH_NULL)
+		goto bad;
+	if (IS_RAD5112(ah) && !IS_RADX112_REV2(ah)) {
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "%s: 5112 Rev 1 is not supported by this "
+                         "driver (analog5GhzRev 0x%x)\n", __func__,
+                         AH_PRIVATE(ah)->ah_analog5GhzRev);
+#endif
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+	}
+
+	ecode = ath_hal_legacyEepromAttach(ah);
+	if (ecode != HAL_OK) {
+		goto bad;
+	}
+
+	/*
+	 * If Bmode and AR5212, verify 2.4 analog exists
+	 */
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) &&
+	    (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) {
+		/*
+		 * Set correct Baseband to analog shift
+		 * setting to access analog chips.
+		 */
+		OS_REG_WRITE(ah, AR_PHY(0), 0x00004007);
+		OS_DELAY(2000);
+		AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah);
+
+		/* Set baseband for 5GHz chip */
+		OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+		OS_DELAY(2000);
+		if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) {
+#ifdef AH_DEBUG
+			ath_hal_printf(ah, "%s: 2G Radio Chip Rev 0x%02X is not "
+				"supported by this driver\n", __func__,
+				AH_PRIVATE(ah)->ah_analog2GhzRev);
+#endif
+			ecode = HAL_ENOTSUPP;
+			goto bad;
+		}
+	}
+
+	ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot read regulatory domain from EEPROM\n",
+		    __func__);
+		goto bad;
+        }
+	AH_PRIVATE(ah)->ah_currentRD = eeval;
+	/* XXX record serial number */
+
+	/* XXX other capabilities */
+	/*
+	 * Got everything we need now to setup the capabilities.
+	 */
+	if (!ar5212FillCapabilityInfo(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: failed ar5212FillCapabilityInfo\n", __func__);
+		ecode = HAL_EEREAD;
+		goto bad;
+	}
+
+	if (!rf->attach(ah, &ecode)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
+		    __func__, ecode);
+		goto bad;
+	}
+	/* arrange a direct call instead of thunking */
+	AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust;
+
+	/* Initialize gain ladder thermal calibration structure */
+	ar5212InitializeGainValues(ah);
+
+        /* BSP specific call for MAC address of this WMAC device */
+        if (!ar5312GetMacAddr(ah)) {
+                ecode = HAL_EEBADMAC;
+                goto bad;
+        }
+
+	ar5312AniSetup(ah);
+	ar5212InitNfCalHistBuffer(ah);
+
+	/* XXX EAR stuff goes here */
+	return ah;
+
+bad:
+	if (ahp)
+		ar5212Detach((struct ath_hal *) ahp);
+	if (status)
+		*status = ecode;
+	return AH_NULL;
+}
+
+static HAL_BOOL
+ar5312GetMacAddr(struct ath_hal *ah)
+{
+	const struct ar531x_boarddata *board = AR5312_BOARDCONFIG(ah); 
+        int wlanNum = AR5312_UNIT(ah);
+        const uint8_t *macAddr;
+
+	switch (wlanNum) {
+	case 0:
+		macAddr = board->wlan0Mac;
+		break;
+	case 1:
+		macAddr = board->wlan1Mac;
+		break;
+	default:
+#ifdef AH_DEBUG
+		ath_hal_printf(ah, "Invalid WLAN wmac index (%d)\n",
+			       wlanNum);
+#endif
+		return AH_FALSE;
+	}
+	OS_MEMCPY(AH5212(ah)->ah_macaddr, macAddr, 6);
+	return AH_TRUE;
+}
+
+static const char*
+ar5312Probe(uint16_t vendorid, uint16_t devid)
+{
+	if (vendorid == ATHEROS_VENDOR_ID) {
+		switch (devid) {
+		case AR5212_AR5312_REV2:
+		case AR5212_AR5312_REV7:
+			return "Atheros 5312 WiSoC";
+		case AR5212_AR2313_REV8:
+			return "Atheros 2313 WiSoC";
+		case AR5212_AR2315_REV6:
+		case AR5212_AR2315_REV7:
+			return "Atheros 2315 WiSoC";
+		case AR5212_AR2317_REV1:
+			return "Atheros 2317 WiSoC";
+		case AR5212_AR2413:
+			return "Atheros 2413";
+		case AR5212_AR2417:
+			return "Atheros 2417";
+		}
+	}
+	return AH_NULL;
+}
+AH_CHIP(AR5312, ar5312Probe, ar5312Attach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_eeprom.c b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_eeprom.c
new file mode 100644
index 0000000..c14b8b2
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_eeprom.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5312_eeprom.c,v 1.4 2008/11/10 04:08:04 sam Exp $
+ */
+#include "opt_ah.h"
+
+
+#ifdef AH_SUPPORT_AR5312
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5312/ar5312.h"
+#include "ar5312/ar5312reg.h"
+#include "ar5212/ar5212desc.h"
+
+/*
+ * Read 16 bits of data from offset into *data
+ */
+HAL_BOOL
+ar5312EepromRead(struct ath_hal *ah, u_int off, uint16_t *dataIn)
+{
+        int i,offset;
+	const char *eepromAddr = AR5312_RADIOCONFIG(ah);
+	uint8_t *data;
+	
+	data = (uint8_t *) dataIn;
+	for (i=0,offset=2*off; i<2; i++,offset++) {
+		data[i] = eepromAddr[offset];
+	}
+        return AH_TRUE;
+}
+#endif /* AH_SUPPORT_AR5312 */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_gpio.c b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_gpio.c
new file mode 100644
index 0000000..02ed565
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_gpio.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5312_gpio.c,v 1.3 2008/11/10 04:08:04 sam Exp $
+ */
+#include "opt_ah.h"
+
+#ifdef AH_SUPPORT_AR5312
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5312/ar5312.h"
+#include "ar5312/ar5312reg.h"
+#include "ar5312/ar5312phy.h"
+
+#define	AR_NUM_GPIO	6		/* 6 GPIO pins */
+#define	AR5312_GPIOD_MASK	0x0000002F	/* GPIO data reg r/w mask */
+
+/*
+ * Configure GPIO Output lines
+ */
+HAL_BOOL
+ar5312GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+{
+	uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR,
+		  (OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
+		| AR_GPIOCR_CR_A(gpio));
+
+	return AH_TRUE;
+}
+
+/*
+ * Configure GPIO Input lines
+ */
+HAL_BOOL
+ar5312GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
+{
+	uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR,
+		  (OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
+		| AR_GPIOCR_CR_N(gpio));
+
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - set output lines
+ */
+HAL_BOOL
+ar5312GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
+{
+	uint32_t reg;
+        uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	reg =  OS_REG_READ(ah, gpioOffset+AR5312_GPIODO);
+	reg &= ~(1 << gpio);
+	reg |= (val&1) << gpio;
+
+	OS_REG_WRITE(ah, gpioOffset+AR5312_GPIODO, reg);
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - get input lines
+ */
+uint32_t
+ar5312GpioGet(struct ath_hal *ah, uint32_t gpio)
+{
+	uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	if (gpio < AR_NUM_GPIO) {
+		uint32_t val = OS_REG_READ(ah, gpioOffset+AR5312_GPIODI);
+		val = ((val & AR5312_GPIOD_MASK) >> gpio) & 0x1;
+		return val;
+	} else {
+		return 0xffffffff;
+	}
+}
+
+/*
+ * Set the GPIO Interrupt
+ */
+void
+ar5312GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
+{
+	uint32_t val;
+        uint32_t gpioOffset = (AR5312_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	/* XXX bounds check gpio */
+	val = OS_REG_READ(ah, gpioOffset+AR5312_GPIOCR);
+	val &= ~(AR_GPIOCR_CR_A(gpio) |
+		 AR_GPIOCR_INT_MASK | AR_GPIOCR_INT_ENA | AR_GPIOCR_INT_SEL);
+	val |= AR_GPIOCR_CR_N(gpio) | AR_GPIOCR_INT(gpio) | AR_GPIOCR_INT_ENA;
+	if (ilevel)
+		val |= AR_GPIOCR_INT_SELH;	/* interrupt on pin high */
+	else
+		val |= AR_GPIOCR_INT_SELL;	/* interrupt on pin low */
+
+	/* Don't need to change anything for low level interrupt. */
+	OS_REG_WRITE(ah, gpioOffset+AR5312_GPIOCR, val);
+
+	/* Change the interrupt mask. */
+	(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);
+}
+
+
+#endif /* AH_SUPPORT_AR5312 */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_interrupts.c b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_interrupts.c
new file mode 100644
index 0000000..c40191e
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_interrupts.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5312_interrupts.c,v 1.2 2008/11/10 01:19:39 sam Exp $
+ */
+#include "opt_ah.h"
+
+#ifdef AH_SUPPORT_AR5312
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5312/ar5312.h"
+#include "ar5312/ar5312reg.h"
+#include "ar5312/ar5312phy.h"
+
+
+/*
+ * Checks to see if an interrupt is pending on our NIC
+ *
+ * Returns: TRUE    if an interrupt is pending
+ *          FALSE   if not
+ */
+HAL_BOOL
+ar5312IsInterruptPending(struct ath_hal *ah)
+{
+        /* 
+         * Some platforms trigger our ISR before applying power to
+         * the card.  For the 5312, this is always true.
+         */
+
+	return(AH_TRUE);
+}
+#endif /* AH_SUPPORT_AR5312 */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_misc.c b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_misc.c
new file mode 100644
index 0000000..7928318
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_misc.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5312_misc.c,v 1.4 2008/11/22 07:40:15 sam Exp $
+ */
+#include "opt_ah.h"
+
+#ifdef AH_SUPPORT_AR5312
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5312/ar5312.h"
+#include "ar5312/ar5312reg.h"
+#include "ar5312/ar5312phy.h"
+
+#define	AR_NUM_GPIO	6		/* 6 GPIO pins */
+#define	AR_GPIOD_MASK	0x0000002F	/* GPIO data reg r/w mask */
+
+/*
+ * Change the LED blinking pattern to correspond to the connectivity
+ */
+void
+ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
+{
+	uint32_t val;
+	uint32_t resOffset = (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh));
+    if(IS_2316(ah)) return; /* not yet */
+	val = SM(AR5312_PCICFG_LEDSEL0, AR5312_PCICFG_LEDSEL) |
+		SM(AR5312_PCICFG_LEDMOD0, AR5312_PCICFG_LEDMODE) |
+		2;
+	OS_REG_WRITE(ah, resOffset+AR5312_PCICFG,
+		(OS_REG_READ(ah, AR5312_PCICFG) &~
+		 (AR5312_PCICFG_LEDSEL | AR5312_PCICFG_LEDMODE |
+		  AR5312_PCICFG_LEDSBR))
+		     | val);
+}
+
+/*
+ * Detect if our wireless mac is present. 
+ */
+HAL_BOOL
+ar5312DetectCardPresent(struct ath_hal *ah)
+{
+	uint16_t macVersion, macRev;
+	uint32_t v;
+
+	/*
+	 * Read the Silicon Revision register and compare that
+	 * to what we read at attach time.  If the same, we say
+	 * a card/device is present.
+	 */
+#if (AH_SUPPORT_2316 || AH_SUPPORT_2317)
+    if(IS_5315(ah))
+    {
+		v = (OS_REG_READ(ah,
+                         (AR5315_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5315_WREV))
+			& AR_SREV_ID;
+		macVersion = v >> AR_SREV_ID_S;
+		macRev = v & AR_SREV_REVISION;
+		return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
+				AH_PRIVATE(ah)->ah_macRev == macRev);
+    }
+    else
+#endif
+    {
+		v = (OS_REG_READ(ah,
+                         (AR5312_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5312_WREV))
+			& AR_SREV_ID;
+		macVersion = v >> AR_SREV_ID_S;
+		macRev = v & AR_SREV_REVISION;
+		return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
+				AH_PRIVATE(ah)->ah_macRev == macRev);
+    }
+}
+
+/*
+ * If 32KHz clock exists, use it to lower power consumption during sleep
+ *
+ * Note: If clock is set to 32 KHz, delays on accessing certain
+ *       baseband registers (27-31, 124-127) are required.
+ */
+void
+ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
+{
+	if (ar5212Use32KHzclock(ah, opmode)) {
+		/*
+		 * Enable clocks to be turned OFF in BB during sleep
+		 * and also enable turning OFF 32MHz/40MHz Refclk
+		 * from A2.
+		 */
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x0d);
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0c);
+		OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x03);
+		OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0x05);
+		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
+		    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
+
+		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
+		OS_REG_WRITE(ah, AR_TSF_PARM, 61);	/* 32 KHz TSF incr */
+
+	} else {
+		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32 MHz TSF incr */
+		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
+		    IS_RAD5112_ANY(ah) ? 39 : 31);
+
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
+
+		if (IS_5312_2_X(ah)) {
+			/* Set ADC/DAC select values */
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x04);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0e);
+			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
+			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
+			OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
+			    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
+		}
+	}
+}
+
+/*
+ * If 32KHz clock exists, turn it off and turn back on the 32Mhz
+ */
+void
+ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
+{
+	if (ar5212Use32KHzclock(ah, opmode)) {
+		/* # Set sleep clock rate back to 32 MHz. */
+		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32 MHz TSF incr */
+		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
+		    IS_RAD5112_ANY(ah) ? 39 : 31);
+
+		/*
+		 * Restore BB registers to power-on defaults
+		 */
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
+		if (IS_5312_2_X(ah)) {
+			/* Set ADC/DAC select values */
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x04);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0e);
+			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
+			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
+			OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
+			    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
+		}
+	}
+}
+
+#endif /* AH_SUPPORT_AR5312 */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_power.c b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_power.c
new file mode 100644
index 0000000..1cc4ed6
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_power.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5312_power.c,v 1.4 2008/11/10 04:08:04 sam Exp $
+ */
+#include "opt_ah.h"
+
+#ifdef AH_SUPPORT_AR5312
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5312/ar5312.h"
+#include "ar5312/ar5312reg.h"
+#include "ar5212/ar5212desc.h"
+
+/*
+ * Notify Power Mgt is enabled in self-generated frames.
+ * If requested, force chip awake.
+ *
+ * Returns A_OK if chip is awake or successfully forced awake.
+ *
+ * WARNING WARNING WARNING
+ * There is a problem with the chip where sometimes it will not wake up.
+ */
+static HAL_BOOL
+ar5312SetPowerModeAwake(struct ath_hal *ah, int setChip)
+{
+        /* No need for this at the moment for APs */
+	return AH_TRUE;
+}
+
+/*
+ * Notify Power Mgt is disabled in self-generated frames.
+ * If requested, force chip to sleep.
+ */
+static void
+ar5312SetPowerModeSleep(struct ath_hal *ah, int setChip)
+{
+        /* No need for this at the moment for APs */
+}
+
+/*
+ * Notify Power Management is enabled in self-generating
+ * fames.  If request, set power mode of chip to
+ * auto/normal.  Duration in units of 128us (1/8 TU).
+ */
+static void
+ar5312SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)
+{
+        /* No need for this at the moment for APs */
+}
+
+/*
+ * Set power mgt to the requested mode, and conditionally set
+ * the chip as well
+ */
+HAL_BOOL
+ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+#ifdef AH_DEBUG
+	static const char* modes[] = {
+		"AWAKE",
+		"FULL-SLEEP",
+		"NETWORK SLEEP",
+		"UNDEFINED"
+	};
+#endif
+	int status = AH_TRUE;
+
+	HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
+		modes[ahp->ah_powerMode], modes[mode],
+		setChip ? "set chip " : "");
+	switch (mode) {
+	case HAL_PM_AWAKE:
+		status = ar5312SetPowerModeAwake(ah, setChip);
+		break;
+	case HAL_PM_FULL_SLEEP:
+		ar5312SetPowerModeSleep(ah, setChip);
+		break;
+	case HAL_PM_NETWORK_SLEEP:
+		ar5312SetPowerModeNetworkSleep(ah, setChip);
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_POWER, "%s: unknown power mode %u\n",
+		    __func__, mode);
+		return AH_FALSE;
+	}
+	ahp->ah_powerMode = mode;
+	return status; 
+}
+
+/*
+ * Return the current sleep mode of the chip
+ */
+uint32_t
+ar5312GetPowerMode(struct ath_hal *ah)
+{
+	return HAL_PM_AWAKE;
+}
+
+/*
+ * Return the current sleep state of the chip
+ * TRUE = sleeping
+ */
+HAL_BOOL
+ar5312GetPowerStatus(struct ath_hal *ah)
+{
+        return 0;		/* Currently, 5312 is never in sleep mode. */
+}
+#endif /* AH_SUPPORT_AR5312 */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_reset.c b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_reset.c
new file mode 100644
index 0000000..6c0bb0a
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312_reset.c
@@ -0,0 +1,919 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5312_reset.c,v 1.10 2008/11/22 07:41:37 sam Exp $
+ */
+#include "opt_ah.h"
+
+#ifdef AH_SUPPORT_AR5312
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5312/ar5312.h"
+#include "ar5312/ar5312reg.h"
+#include "ar5312/ar5312phy.h"
+
+#include "ah_eeprom_v3.h"
+
+/* Additional Time delay to wait after activiting the Base band */
+#define BASE_ACTIVATE_DELAY	100	/* 100 usec */
+#define PLL_SETTLE_DELAY	300	/* 300 usec */
+
+extern int16_t ar5212GetNf(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+extern void ar5212SetRateDurationTable(struct ath_hal *, HAL_CHANNEL *);
+extern HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,
+                      HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain);
+extern void ar5212SetDeltaSlope(struct ath_hal *, HAL_CHANNEL *);
+extern HAL_BOOL ar5212SetBoardValues(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+extern void ar5212SetIFSTiming(struct ath_hal *, HAL_CHANNEL *);
+extern HAL_BOOL	ar5212IsSpurChannel(struct ath_hal *, HAL_CHANNEL *);
+extern HAL_BOOL	ar5212ChannelChange(struct ath_hal *, HAL_CHANNEL *);
+
+static HAL_BOOL ar5312SetResetReg(struct ath_hal *, uint32_t resetMask);
+
+static int
+write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+	HAL_BOOL bChannelChange, int writes)
+{
+#define IS_NO_RESET_TIMER_ADDR(x)                      \
+    ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \
+      (((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3)))
+#define	V(r, c)	(ia)->data[((r)*(ia)->cols) + (c)]
+	int i;
+
+	/* Write Common Array Parameters */
+	for (i = 0; i < ia->rows; i++) {
+		uint32_t reg = V(i, 0);
+		/* XXX timer/beacon setup registers? */
+		/* On channel change, don't reset the PCU registers */
+		if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) {
+			OS_REG_WRITE(ah, reg, V(i, 1));
+			DMA_YIELD(writes);
+		}
+	}
+	return writes;
+#undef IS_NO_RESET_TIMER_ADDR
+#undef V
+}
+
+/*
+ * Places the device in and out of reset and then places sane
+ * values in the registers based on EEPROM config, initialization
+ * vectors (as determined by the mode), and station configuration
+ *
+ * bChannelChange is used to preserve DMA/PCU registers across
+ * a HW Reset during channel change.
+ */
+HAL_BOOL
+ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
+	HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+{
+#define	N(a)	(sizeof (a) / sizeof (a[0]))
+#define	FAIL(_code)	do { ecode = _code; goto bad; } while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *ichan;
+	const HAL_EEPROM *ee;
+	uint32_t saveFrameSeqCount, saveDefAntenna;
+	uint32_t macStaId1, synthDelay, txFrm2TxDStart;
+	uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL];
+	int16_t cckOfdmPwrDelta = 0;
+	u_int modesIndex, freqIndex;
+	HAL_STATUS ecode;
+	int i, regWrites = 0;
+	uint32_t testReg;
+	uint32_t saveLedState = 0;
+
+	HALASSERT(ah->ah_magic == AR5212_MAGIC);
+	ee = AH_PRIVATE(ah)->ah_eeprom;
+
+	OS_MARK(ah, AH_MARK_RESET, bChannelChange);
+#define	IS(_c,_f)	(((_c)->channelFlags & _f) || 0)
+	if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+	if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+#undef IS
+	/*
+	 * Map public channel to private.
+	 */
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+	switch (opmode) {
+	case HAL_M_STA:
+	case HAL_M_IBSS:
+	case HAL_M_HOSTAP:
+	case HAL_M_MONITOR:
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
+		    __func__, opmode);
+		FAIL(HAL_EINVAL);
+		break;
+	}
+	HALASSERT(ahp->ah_eeversion >= AR_EEPROM_VER3);
+
+	/* Preserve certain DMA hardware registers on a channel change */
+	if (bChannelChange) {
+		/*
+		 * On Venice, the TSF is almost preserved across a reset;
+		 * it requires the doubling writes to the RESET_TSF
+		 * bit in the AR_BEACON register; it also has the quirk
+		 * of the TSF going back in time on the station (station
+		 * latches onto the last beacon's tsf during a reset 50%
+		 * of the times); the latter is not a problem for adhoc
+		 * stations since as long as the TSF is behind, it will
+		 * get resynchronized on receiving the next beacon; the
+		 * TSF going backwards in time could be a problem for the
+		 * sleep operation (supported on infrastructure stations
+		 * only) - the best and most general fix for this situation
+		 * is to resynchronize the various sleep/beacon timers on
+		 * the receipt of the next beacon i.e. when the TSF itself
+		 * gets resynchronized to the AP's TSF - power save is
+		 * needed to be temporarily disabled until that time
+		 *
+		 * Need to save the sequence number to restore it after
+		 * the reset!
+		 */
+		saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);
+	} else
+		saveFrameSeqCount = 0;		/* NB: silence compiler */
+
+	/* If the channel change is across the same mode - perform a fast channel change */
+	if ((IS_2413(ah) || IS_5413(ah))) {
+		/*
+		 * Channel change can only be used when:
+		 *  -channel change requested - so it's not the initial reset.
+		 *  -it's not a change to the current channel - often called when switching modes
+		 *   on a channel
+		 *  -the modes of the previous and requested channel are the same - some ugly code for XR
+		 */
+		if (bChannelChange &&
+		    (AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
+		    (chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) &&
+		    ((chan->channelFlags & CHANNEL_ALL) ==
+		     (AH_PRIVATE(ah)->ah_curchan->channelFlags & CHANNEL_ALL))) {
+			if (ar5212ChannelChange(ah, chan))
+				/* If ChannelChange completed - skip the rest of reset */
+				return AH_TRUE;
+		}
+	}
+
+	/*
+	 * Preserve the antenna on a channel change
+	 */
+	saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
+	if (saveDefAntenna == 0)		/* XXX magic constants */
+		saveDefAntenna = 1;
+
+	/* Save hardware flag before chip reset clears the register */
+	macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 
+		(AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT);
+
+	/* Save led state from pci config register */
+	if (!IS_5315(ah))
+		saveLedState = OS_REG_READ(ah, AR5312_PCICFG) &
+			(AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK |
+			 AR_PCICFG_LEDSLOW);
+
+	ar5312RestoreClock(ah, opmode);		/* move to refclk operation */
+
+	/*
+	 * Adjust gain parameters before reset if
+	 * there's an outstanding gain updated.
+	 */
+	(void) ar5212GetRfgain(ah);
+
+	if (!ar5312ChipReset(ah, chan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Setup the indices for the next set of register array writes */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+		modesIndex = 1;
+		freqIndex  = 1;
+		break;
+	case CHANNEL_T:
+		modesIndex = 2;
+		freqIndex  = 1;
+		break;
+	case CHANNEL_B:
+		modesIndex = 3;
+		freqIndex  = 2;
+		break;
+	case CHANNEL_PUREG:
+		modesIndex = 4;
+		freqIndex  = 2;
+		break;
+	case CHANNEL_108G:
+		modesIndex = 5;
+		freqIndex  = 2;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	/* Set correct Baseband to analog shift setting to access analog chips. */
+	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
+	regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
+		regWrites);
+	ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) {
+		ar5212SetIFSTiming(ah, chan);
+	}
+
+	/* Overwrite INI values for revised chipsets */
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
+		/* ADC_CTL */
+		OS_REG_WRITE(ah, AR_PHY_ADC_CTL,
+			     SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) |
+			     SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) |
+			     AR_PHY_ADC_CTL_OFF_PWDDAC |
+			     AR_PHY_ADC_CTL_OFF_PWDADC);
+		
+		/* TX_PWR_ADJ */
+		if (chan->channel == 2484) {
+			cckOfdmPwrDelta = SCALE_OC_DELTA(ee->ee_cckOfdmPwrDelta - ee->ee_scaledCh14FilterCckDelta);
+		} else {
+			cckOfdmPwrDelta = SCALE_OC_DELTA(ee->ee_cckOfdmPwrDelta);
+		}
+		
+		if (IS_CHAN_G(chan)) {
+			OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
+				     SM((ee->ee_cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) |
+				     SM((cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX));
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);
+		}
+		
+		/* Add barker RSSI thresh enable as disabled */
+		OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK,
+			       AR_PHY_DAG_CTRLCCK_EN_RSSI_THR);
+		OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
+				 AR_PHY_DAG_CTRLCCK_RSSI_THR, 2);
+		
+		/* Set the mute mask to the correct default */
+		OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
+	}
+	
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
+		/* Clear reg to alllow RX_CLEAR line debug */
+		OS_REG_WRITE(ah, AR_PHY_BLUETOOTH,  0);
+	}
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
+#ifdef notyet
+		/* Enable burst prefetch for the data queues */
+		OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
+		/* Enable double-buffering */
+		OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
+#endif
+	}
+
+	if (IS_5312_2_X(ah)) {
+		/* ADC_CTRL */
+		OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA,
+			     SM(2, AR_PHY_SIGMA_DELTA_ADC_SEL) |
+			     SM(4, AR_PHY_SIGMA_DELTA_FILT2) |
+			     SM(0x16, AR_PHY_SIGMA_DELTA_FILT1) |
+			     SM(0, AR_PHY_SIGMA_DELTA_ADC_CLIP));
+
+		if (IS_CHAN_2GHZ(chan))
+			OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);
+
+		/* CCK Short parameter adjustment in 11B mode */
+		if (IS_CHAN_B(chan))
+			OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);
+
+		/* Set ADC/DAC select values */
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
+
+		/* Increase 11A AGC Settling */
+		if ((chan->channelFlags & CHANNEL_ALL) == CHANNEL_A)
+			OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);
+	} else {
+		/* Set ADC/DAC select values */
+		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
+	}
+
+	/* Setup the transmit power values. */
+	if (!ar5212SetTransmitPower(ah, ichan, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error init'ing transmit power\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Write the analog registers */
+	if (!ahp->ah_rfHal->setRfRegs(ah, ichan, modesIndex, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",
+		    __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
+	if (IS_CHAN_OFDM(chan)) {
+		if ((IS_5413(ah) || (AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)) &&
+		    (!IS_CHAN_B(chan)))
+			ar5212SetSpurMitigation(ah, ichan);
+		ar5212SetDeltaSlope(ah, chan);
+	}
+
+	/* Setup board specific options for EEPROM version 3 */
+	if (!ar5212SetBoardValues(ah, ichan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error setting board options\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Restore certain DMA hardware registers on a channel change */
+	if (bChannelChange)
+		OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount);
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
+	OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
+		| macStaId1
+		| AR_STA_ID1_RTS_USE_DEF
+		| ahp->ah_staId1Defaults
+	);
+	ar5212SetOperatingMode(ah, opmode);
+
+	/* Set Venice BSSID mask according to current state */
+	OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
+	OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
+
+	/* Restore previous led state */
+	if (!IS_5315(ah))
+		OS_REG_WRITE(ah, AR5312_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);
+
+	/* Restore previous antenna */
+	OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
+
+	/* then our BSSID */
+	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
+	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
+
+	/* Restore bmiss rssi & count thresholds */
+	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
+
+	OS_REG_WRITE(ah, AR_ISR, ~0);		/* cleared on write */
+
+	if (!ar5212SetChannel(ah, ichan))
+		FAIL(HAL_EIO);
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
+
+	ar5212SetRateDurationTable(ah, chan);
+
+	/* Set Tx frame start to tx data start delay */
+	if (IS_RAD5112_ANY(ah) &&
+	    (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan) ||
+	     IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan))) {
+		txFrm2TxDStart = 
+			(IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) ?
+					TX_FRAME_D_START_HALF_RATE:
+					TX_FRAME_D_START_QUARTER_RATE;
+		OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, 
+			AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart);
+	}
+
+	/*
+	 * Setup fast diversity.
+	 * Fast diversity can be enabled or disabled via regadd.txt.
+	 * Default is enabled.
+	 * For reference,
+	 *    Disable: reg        val
+	 *             0x00009860 0x00009d18 (if 11a / 11g, else no change)
+	 *             0x00009970 0x192bb514
+	 *             0x0000a208 0xd03e4648
+	 *
+	 *    Enable:  0x00009860 0x00009d10 (if 11a / 11g, else no change)
+	 *             0x00009970 0x192fb514
+	 *             0x0000a208 0xd03e6788
+	 */
+
+	/* XXX Setup pre PHY ENABLE EAR additions */
+
+	/* flush SCAL reg */
+	if (IS_5312_2_X(ah)) {
+		(void) OS_REG_READ(ah, AR_PHY_SLEEP_SCAL);
+	}
+
+	/*
+	 * Wait for the frequency synth to settle (synth goes on
+	 * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
+	 * Value is in 100ns increments.
+	 */
+	synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
+	if (IS_CHAN_CCK(chan)) {
+		synthDelay = (4 * synthDelay) / 22;
+	} else {
+		synthDelay /= 10;
+	}
+
+	/* Activate the PHY (includes baseband activate and synthesizer on) */
+	OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+
+	/* 
+	 * There is an issue if the AP starts the calibration before
+	 * the base band timeout completes.  This could result in the
+	 * rx_clear false triggering.  As a workaround we add delay an
+	 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
+	 * does not happen.
+	 */
+	if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+		OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
+	} else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+		OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
+	} else {
+		OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
+	}
+
+	/*
+	 * The udelay method is not reliable with notebooks.
+	 * Need to check to see if the baseband is ready
+	 */
+	testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL);
+	/* Selects the Tx hold */
+	OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD);
+	i = 0;
+	while ((i++ < 20) &&
+	       (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */		OS_DELAY(200);
+	OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg);
+
+	/* Calibrate the AGC and start a NF calculation */
+	OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
+		  OS_REG_READ(ah, AR_PHY_AGC_CONTROL)
+		| AR_PHY_AGC_CONTROL_CAL
+		| AR_PHY_AGC_CONTROL_NF);
+
+	if (!IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) {
+		/* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
+		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 
+			AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
+			INIT_IQCAL_LOG_COUNT_MAX);
+		OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
+			AR_PHY_TIMING_CTRL4_DO_IQCAL);
+		ahp->ah_bIQCalibration = IQ_CAL_RUNNING;
+	} else
+		ahp->ah_bIQCalibration = IQ_CAL_INACTIVE;
+
+	/* Setup compression registers */
+	ar5212SetCompRegs(ah);
+
+	/* Set 1:1 QCU to DCU mapping for all queues */
+	for (i = 0; i < AR_NUM_DCU; i++)
+		OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
+
+	ahp->ah_intrTxqs = 0;
+	for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
+		ar5212ResetTxQueue(ah, i);
+
+	/*
+	 * Setup interrupt handling.  Note that ar5212ResetTxQueue
+	 * manipulates the secondary IMR's as queues are enabled
+	 * and disabled.  This is done with RMW ops to insure the
+	 * settings we make here are preserved.
+	 */
+	ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN
+			| AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN
+			| AR_IMR_HIUERR
+			;
+	if (opmode == HAL_M_HOSTAP)
+		ahp->ah_maskReg |= AR_IMR_MIB;
+	OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
+	/* Enable bus errors that are OR'd to set the HIUERR bit */
+	OS_REG_WRITE(ah, AR_IMR_S2,
+		OS_REG_READ(ah, AR_IMR_S2)
+		| AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR);
+
+	if (AH_PRIVATE(ah)->ah_rfkillEnabled)
+		ar5212EnableRfKill(ah);
+
+	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: offset calibration failed to complete in 1ms;"
+		    " noisy environment?\n", __func__);
+	}
+
+	/*
+	 * Set clocks back to 32kHz if they had been using refClk, then
+	 * use an external 32kHz crystal when sleeping, if one exists.
+	 */
+	ar5312SetupClock(ah, opmode);
+
+	/*
+	 * Writing to AR_BEACON will start timers. Hence it should
+	 * be the last register to be written. Do not reset tsf, do
+	 * not enable beacons at this point, but preserve other values
+	 * like beaconInterval.
+	 */
+	OS_REG_WRITE(ah, AR_BEACON,
+		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
+
+	/* XXX Setup post reset EAR additions */
+
+	/*  QoS support */
+	if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE ||
+	    (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
+	     AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) {
+		OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa);	/* XXX magic */
+		OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210);	/* XXX magic */
+	}
+
+	/* Turn on NOACK Support for QoS packets */
+	OS_REG_WRITE(ah, AR_NOACK,
+		     SM(2, AR_NOACK_2BIT_VALUE) |
+		     SM(5, AR_NOACK_BIT_OFFSET) |
+		     SM(0, AR_NOACK_BYTE_OFFSET));
+
+	/* Restore user-specified settings */
+	if (ahp->ah_miscMode != 0)
+		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+	if (ahp->ah_slottime != (u_int) -1)
+		ar5212SetSlotTime(ah, ahp->ah_slottime);
+	if (ahp->ah_acktimeout != (u_int) -1)
+		ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
+	if (ahp->ah_ctstimeout != (u_int) -1)
+		ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
+	if (ahp->ah_sifstime != (u_int) -1)
+		ar5212SetSifsTime(ah, ahp->ah_sifstime);
+	if (AH_PRIVATE(ah)->ah_diagreg != 0)
+		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
+
+	AH_PRIVATE(ah)->ah_opmode = opmode;	/* record operating mode */
+
+	if (bChannelChange) {
+		if (!(ichan->privFlags & CHANNEL_DFS)) 
+			ichan->privFlags &= ~CHANNEL_INTERFERENCE;
+		chan->channelFlags = ichan->channelFlags;
+		chan->privFlags = ichan->privFlags;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
+
+	OS_MARK(ah, AH_MARK_RESET_DONE, 0);
+
+	return AH_TRUE;
+bad:
+	OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
+	if (*status)
+		*status = ecode;
+	return AH_FALSE;
+#undef FAIL
+#undef N
+}
+
+/*
+ * Places the PHY and Radio chips into reset.  A full reset
+ * must be called to leave this state.  The PCI/MAC/PCU are
+ * not placed into reset as we must receive interrupt to
+ * re-enable the hardware.
+ */
+HAL_BOOL
+ar5312PhyDisable(struct ath_hal *ah)
+{
+    return ar5312SetResetReg(ah, AR_RC_BB);
+}
+
+/*
+ * Places all of hardware into reset
+ */
+HAL_BOOL
+ar5312Disable(struct ath_hal *ah)
+{
+	if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+	/*
+	 * Reset the HW - PCI must be reset after the rest of the
+	 * device has been reset.
+	 */
+	return ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB);
+}
+
+/*
+ * Places the hardware into reset and then pulls it out of reset
+ *
+ * TODO: Only write the PLL if we're changing to or from CCK mode
+ * 
+ * WARNING: The order of the PLL and mode registers must be correct.
+ */
+HAL_BOOL
+ar5312ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+
+	OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0);
+
+	/*
+	 * Reset the HW 
+	 */
+	if (!ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
+		    __func__);
+		return AH_FALSE;
+	}
+
+	/* Bring out of sleep mode (AGAIN) */
+	if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetPowerMode failed\n",
+		    __func__);
+		return AH_FALSE;
+	}
+
+	/* Clear warm reset register */
+	if (!ar5312SetResetReg(ah, 0)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
+		    __func__);
+		return AH_FALSE;
+	}
+
+	/*
+	 * Perform warm reset before the mode/PLL/turbo registers
+	 * are changed in order to deactivate the radio.  Mode changes
+	 * with an active radio can result in corrupted shifts to the
+	 * radio device.
+	 */
+
+	/*
+	 * Set CCK and Turbo modes correctly.
+	 */
+	if (chan != AH_NULL) {		/* NB: can be null during attach */
+		uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo;
+
+		if (IS_RAD5112_ANY(ah)) {
+			rfMode = AR_PHY_MODE_AR5112;
+			if (!IS_5315(ah)) {
+				if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan)) {
+					phyPLL = AR_PHY_PLL_CTL_44_5312;
+				} else {
+					if (IS_CHAN_HALF_RATE(chan)) {
+						phyPLL = AR_PHY_PLL_CTL_40_5312_HALF;
+					} else if (IS_CHAN_QUARTER_RATE(chan)) {
+						phyPLL = AR_PHY_PLL_CTL_40_5312_QUARTER;
+					} else {
+						phyPLL = AR_PHY_PLL_CTL_40_5312;
+					}
+				}
+			} else {
+				if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+					phyPLL = AR_PHY_PLL_CTL_44_5112;
+				else
+					phyPLL = AR_PHY_PLL_CTL_40_5112;
+				if (IS_CHAN_HALF_RATE(chan))
+					phyPLL |= AR_PHY_PLL_CTL_HALF;
+				else if (IS_CHAN_QUARTER_RATE(chan))
+					phyPLL |= AR_PHY_PLL_CTL_QUARTER;
+			}
+		} else {
+			rfMode = AR_PHY_MODE_AR5111;
+			if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan))
+				phyPLL = AR_PHY_PLL_CTL_44;
+			else
+				phyPLL = AR_PHY_PLL_CTL_40;
+			if (IS_CHAN_HALF_RATE(chan))
+				phyPLL = AR_PHY_PLL_CTL_HALF;
+			else if (IS_CHAN_QUARTER_RATE(chan))
+				phyPLL = AR_PHY_PLL_CTL_QUARTER;
+		}
+		if (IS_CHAN_OFDM(chan) && (IS_CHAN_CCK(chan) || 
+					   IS_CHAN_G(chan)))
+			rfMode |= AR_PHY_MODE_DYNAMIC;
+		else if (IS_CHAN_OFDM(chan))
+			rfMode |= AR_PHY_MODE_OFDM;
+		else
+			rfMode |= AR_PHY_MODE_CCK;
+		if (IS_CHAN_5GHZ(chan))
+			rfMode |= AR_PHY_MODE_RF5GHZ;
+		else
+			rfMode |= AR_PHY_MODE_RF2GHZ;
+		turbo = IS_CHAN_TURBO(chan) ?
+			(AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0;
+		curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);
+		/*
+		 * PLL, Mode, and Turbo values must be written in the correct
+		 * order to ensure:
+		 * - The PLL cannot be set to 44 unless the CCK or DYNAMIC
+		 *   mode bit is set
+		 * - Turbo cannot be set at the same time as CCK or DYNAMIC
+		 */
+		if (IS_CHAN_CCK(chan) || IS_CHAN_G(chan)) {
+			OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
+			OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
+			if (curPhyPLL != phyPLL) {
+				OS_REG_WRITE(ah,  AR_PHY_PLL_CTL,  phyPLL);
+				/* Wait for the PLL to settle */
+				OS_DELAY(PLL_SETTLE_DELAY);
+			}
+		} else {
+			if (curPhyPLL != phyPLL) {
+				OS_REG_WRITE(ah,  AR_PHY_PLL_CTL,  phyPLL);
+				/* Wait for the PLL to settle */
+				OS_DELAY(PLL_SETTLE_DELAY);
+			}
+			OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
+			OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
+		}
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Write the given reset bit mask into the reset register
+ */
+static HAL_BOOL
+ar5312SetResetReg(struct ath_hal *ah, uint32_t resetMask)
+{
+	uint32_t mask = resetMask ? resetMask : ~0;
+	HAL_BOOL rt;
+
+        if ((rt = ar5312MacReset(ah, mask)) == AH_FALSE) {
+		return rt;
+	}
+        if ((resetMask & AR_RC_MAC) == 0) {
+		if (isBigEndian()) {
+			/*
+			 * Set CFG, little-endian for register
+			 * and descriptor accesses.
+			 */
+#ifdef AH_NEED_DESC_SWAP
+			mask = INIT_CONFIG_STATUS | AR_CFG_SWRD;
+#else
+			mask = INIT_CONFIG_STATUS |
+                                AR_CFG_SWTD | AR_CFG_SWRD;
+#endif
+			OS_REG_WRITE(ah, AR_CFG, mask);
+		} else
+			OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
+	}
+	return rt;
+}
+
+/*
+ * ar5312MacReset resets (and then un-resets) the specified
+ * wireless components.
+ * Note: The RCMask cannot be zero on entering from ar5312SetResetReg.
+ */
+
+HAL_BOOL
+ar5312MacReset(struct ath_hal *ah, unsigned int RCMask)
+{
+	int wlanNum = AR5312_UNIT(ah);
+	uint32_t resetBB, resetBits, regMask;
+	uint32_t reg;
+
+	if (RCMask == 0)
+		return(AH_FALSE);
+#if ( AH_SUPPORT_2316 || AH_SUPPORT_2317 )
+	    if (IS_5315(ah)) {
+			switch(wlanNum) {
+			case 0:
+				resetBB = AR5315_RC_BB0_CRES | AR5315_RC_WBB0_RES; 
+				/* Warm and cold reset bits for wbb */
+				resetBits = AR5315_RC_WMAC0_RES;
+				break;
+			case 1:
+				resetBB = AR5315_RC_BB1_CRES | AR5315_RC_WBB1_RES; 
+				/* Warm and cold reset bits for wbb */
+				resetBits = AR5315_RC_WMAC1_RES;
+				break;
+			default:
+				return(AH_FALSE);
+			}		
+			regMask = ~(resetBB | resetBits);
+
+			/* read before */
+			reg = OS_REG_READ(ah, 
+							  (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5315_RESET));
+
+			if (RCMask == AR_RC_BB) {
+				/* Put baseband in reset */
+				reg |= resetBB;    /* Cold and warm reset the baseband bits */
+			} else {
+				/*
+				 * Reset the MAC and baseband.  This is a bit different than
+				 * the PCI version, but holding in reset causes problems.
+				 */
+				reg &= regMask;
+				reg |= (resetBits | resetBB) ;
+			}
+			OS_REG_WRITE(ah, 
+						 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),
+						 reg);
+			/* read after */
+			OS_REG_READ(ah, 
+						(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5315_RESET));
+			OS_DELAY(100);
+
+			/* Bring MAC and baseband out of reset */
+			reg &= regMask;
+			/* read before */
+			OS_REG_READ(ah, 
+						(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
+			OS_REG_WRITE(ah, 
+						 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),
+						 reg);
+			/* read after */
+			OS_REG_READ(ah,
+						(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
+
+
+		} 
+        else 
+#endif
+		{
+
+			switch(wlanNum) {
+			case 0:
+				resetBB = AR5312_RC_BB0_CRES | AR5312_RC_WBB0_RES;
+				/* Warm and cold reset bits for wbb */
+				resetBits = AR5312_RC_WMAC0_RES;
+				break;
+			case 1:
+				resetBB = AR5312_RC_BB1_CRES | AR5312_RC_WBB1_RES;
+				/* Warm and cold reset bits for wbb */
+				resetBits = AR5312_RC_WMAC1_RES;
+				break;
+			default:
+				return(AH_FALSE);
+			}
+			regMask = ~(resetBB | resetBits);
+
+			/* read before */
+			reg = OS_REG_READ(ah,
+							  (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5312_RESET));
+
+			if (RCMask == AR_RC_BB) {
+				/* Put baseband in reset */
+				reg |= resetBB;    /* Cold and warm reset the baseband bits */
+			} else {
+				/*
+				 * Reset the MAC and baseband.  This is a bit different than
+				 * the PCI version, but holding in reset causes problems.
+				 */
+				reg &= regMask;
+				reg |= (resetBits | resetBB) ;
+			}
+			OS_REG_WRITE(ah,
+						 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),
+						 reg);
+			/* read after */
+			OS_REG_READ(ah,
+						(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5312_RESET));
+			OS_DELAY(100);
+
+			/* Bring MAC and baseband out of reset */
+			reg &= regMask;
+			/* read before */
+			OS_REG_READ(ah,
+						(AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));
+			OS_REG_WRITE(ah,
+						 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),
+						 reg);
+			/* read after */
+			OS_REG_READ(ah,
+						(AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));
+		}
+	return(AH_TRUE);
+}
+
+#endif /* AH_SUPPORT_AR5312 */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312phy.h b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312phy.h
new file mode 100644
index 0000000..9f867c7
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312phy.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5312phy.h,v 1.3 2008/10/06 18:32:50 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5312PHY_H_
+#define _DEV_ATH_AR5312PHY_H_
+
+#include "ar5212/ar5212phy.h"
+
+/* PHY registers */
+
+#define AR_PHY_PLL_CTL_44_5312  0x14d6          /* 44 MHz for 11b, 11g */
+#define AR_PHY_PLL_CTL_40_5312  0x14d4          /* 40 MHz for 11a, turbos */
+#define AR_PHY_PLL_CTL_40_5312_HALF  0x15d4	/* 40 MHz for 11a, turbos (Half)*/
+#define AR_PHY_PLL_CTL_40_5312_QUARTER  0x16d4	/* 40 MHz for 11a, turbos (Quarter)*/
+
+#endif	/* _DEV_ATH_AR5312PHY_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312reg.h b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312reg.h
new file mode 100644
index 0000000..ff79cd3
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5312reg.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5312reg.h,v 1.4 2008/11/10 04:08:04 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5312REG_H_
+#define _DEV_ATH_AR5312REG_H_
+
+#include "ar5212/ar5212reg.h"
+/*
+ * Definitions for the Atheros 5312 chipset.
+ */
+
+/* Register base addresses for modules which are not wmac modules */
+/* 531X has a fixed memory map */
+
+
+#define REG_WRITE(_reg,_val)		*((volatile uint32_t *)(_reg)) = (_val);
+#define REG_READ(_reg)		*((volatile uint32_t *)(_reg))
+/* 
+ * PCI-MAC Configuration registers (AR2315+)
+ */
+#define AR5315_RSTIMER_BASE 0xb1000000  /* Address for reset/timer registers */
+#define AR5315_GPIO_BASE    0xb1000000  /* Address for GPIO registers */
+#define AR5315_WLAN0            0xb0000000
+
+#define AR5315_RESET   0x0004      /* Offset of reset control register */
+#define AR5315_SREV    0x0014      /* Offset of reset control register */
+#define AR5315_ENDIAN_CTL  0x000c  /* offset of the endian control register */
+#define AR5315_CONFIG_WLAN     0x00000002      /* WLAN byteswap */
+
+#define AR5315_REV_MAJ                     0x00f0
+#define AR5315_REV_MIN                     0x000f
+
+#define AR5315_GPIODIR      0x0098      /* GPIO direction register */
+#define AR5315_GPIODO       0x0090      /* GPIO data output access reg */
+#define AR5315_GPIODI       0x0088      /* GPIO data input access reg*/
+#define AR5315_GPIOINT      0x00a0      /* GPIO interrupt control */
+
+#define AR5315_GPIODIR_M(x) (1 << (x))  /* mask for i/o */
+#define AR5315_GPIODIR_O(x) (1 << (x))  /* output */
+#define AR5315_GPIODIR_I(x) 0           /* input */
+
+#define AR5315_GPIOINT_S    0
+#define AR5315_GPIOINT_M    0x3F
+#define AR5315_GPIOINTLVL_S 6
+#define AR5315_GPIOINTLVL_M (3 << AR5315_GPIOINTLVL_S)
+
+#define AR5315_WREV         (-0xefbfe0)      /* Revision ID register offset */
+#define AR5315_WREV_S       0           /* Shift for WMAC revision info */
+#define AR5315_WREV_ID      0x000000FF  /* Mask for WMAC revision info */
+#define AR5315_WREV_ID_S    4           /* Shift for WMAC Rev ID */
+#define AR5315_WREV_REVISION 0x0000000F /* Mask for WMAN Revsion version */
+
+#define AR5315_RC_BB0_CRES   0x00000002  /* Cold reset to WMAC0 & WBB0 */
+#define AR5315_RC_BB1_CRES   0x00000200  /* Cold reset to WMAC1 & WBB1n */
+#define AR5315_RC_WMAC0_RES  0x00000001  /* Warm reset to WMAC 0 */
+#define AR5315_RC_WBB0_RES  0x00000002  /* Warm reset to WBB0 */
+#define AR5315_RC_WMAC1_RES  0x00020000  /* Warm reset to WMAC1 */
+#define AR5315_RC_WBB1_RES   0x00040000  /* Warm reset to WBB */
+
+/*
+ * PCI-MAC Configuration registers (AR5312)
+ */
+#define AR5312_RSTIMER_BASE 0xbc003000  /* Address for reset/timer registers */
+#define AR5312_GPIO_BASE    0xbc002000  /* Address for GPIO registers */
+#define AR5312_WLAN0            0xb8000000
+#define AR5312_WLAN1            0xb8500000
+
+#define AR5312_RESET	0x0020      /* Offset of reset control register */
+#define	AR5312_PCICFG	0x00B0	    /* MAC/PCI configuration reg (LEDs) */
+
+#define AR5312_PCICFG_LEDMODE  0x0000001c	/* LED Mode mask */
+#define AR5312_PCICFG_LEDMODE_S  2	/* LED Mode shift */
+#define AR5312_PCICFG_LEDMOD0  0	/* Blnk prop to Tx and filtered Rx */
+#define AR5312_PCICFG_LEDMOD1  1	/* Blnk prop to all Tx and Rx */
+#define AR5312_PCICFG_LEDMOD2  2	/* DEBG flash */
+#define AR5312_PCICFG_LEDMOD3  3	/* BLNK Randomly */
+
+#define	AR5312_PCICFG_LEDSEL   0x000000e0 /* LED Throughput select */
+#define AR5312_PCICFG_LEDSEL_S 5
+#define AR5312_PCICFG_LEDSEL0  0	/* See blink rate table on p. 143 */
+#define AR5312_PCICFG_LEDSEL1  1	/* of AR5212 data sheet */
+#define AR5312_PCICFG_LEDSEL2  2
+#define AR5312_PCICFG_LEDSEL3  3
+#define AR5312_PCICFG_LEDSEL4  4
+#define AR5312_PCICFG_LEDSEL5  5
+#define AR5312_PCICFG_LEDSEL6  6
+#define AR5312_PCICFG_LEDSEL7  7
+
+#define AR5312_PCICFG_LEDSBR   0x00000100 /* Slow blink rate if no
+			   		     activity. 0 = blink @ lowest
+					     rate */
+
+#undef AR_GPIOCR
+#undef AR_GPIODO                    /* Undefine the 5212 defs */
+#undef AR_GPIODI
+
+#define AR5312_GPIOCR       0x0008      /* GPIO Control register */
+#define AR5312_GPIODO       0x0000      /* GPIO data output access reg */
+#define AR5312_GPIODI       0x0004      /* GPIO data input access reg*/
+/* NB: AR5312 uses AR5212 defines for GPIOCR definitions */
+
+#define AR5312_WREV         0x0090      /* Revision ID register offset */
+#define AR5312_WREV_S       8           /* Shift for WMAC revision info */
+#define AR5312_WREV_ID      0x000000FF  /* Mask for WMAC revision info */
+#define AR5312_WREV_ID_S    4           /* Shift for WMAC Rev ID */
+#define AR5312_WREV_REVISION 0x0000000F /* Mask for WMAN Revsion version */
+
+#define AR5312_RC_BB0_CRES   0x00000004  /* Cold reset to WMAC0 & WBB0 */
+#define AR5312_RC_BB1_CRES   0x00000200  /* Cold reset to WMAC1 & WBB1n */
+#define AR5312_RC_WMAC0_RES  0x00002000  /* Warm reset to WMAC 0 */
+#define AR5312_RC_WBB0_RES  0x00004000  /* Warm reset to WBB0 */
+#define AR5312_RC_WMAC1_RES  0x00020000  /* Warm reset to WMAC1 */
+#define AR5312_RC_WBB1_RES   0x00040000  /* Warm reset to WBB */
+
+
+#define AR_RAD2112_SREV_MAJOR   0x40    /* 2112 Major Rev */
+
+enum AR5312PowerMode {
+    AR5312_POWER_MODE_FORCE_SLEEP  = 0,
+    AR5312_POWER_MODE_FORCE_WAKE   = 1,
+    AR5312_POWER_MODE_NORMAL       = 2,
+};
+
+#endif /* _DEV_AR5312REG_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5315_gpio.c b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5315_gpio.c
new file mode 100644
index 0000000..2aca97a
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5312/ar5315_gpio.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5315_gpio.c,v 1.3 2008/11/10 04:08:04 sam Exp $
+ */
+#include "opt_ah.h"
+
+#if (AH_SUPPORT_2316 || AH_SUPPORT_2317)
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5312/ar5312.h"
+#include "ar5312/ar5312reg.h"
+#include "ar5312/ar5312phy.h"
+
+#define	AR_NUM_GPIO	7		/* 6 GPIO pins */
+#define	AR5315_GPIOD_MASK	0x0000007F	/* GPIO data reg r/w mask */
+
+/*
+ * Configure GPIO Output lines
+ */
+HAL_BOOL
+ar5315GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+{
+	uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODIR,
+		  (OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio))
+		| AR5315_GPIODIR_O(gpio));
+
+	return AH_TRUE;
+}
+
+/*
+ * Configure GPIO Input lines
+ */
+HAL_BOOL
+ar5315GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
+{
+	uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODIR,
+		  (OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio))
+		| AR5315_GPIODIR_I(gpio));
+
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - set output lines
+ */
+HAL_BOOL
+ar5315GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
+{
+	uint32_t reg;
+        uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+
+	reg =  OS_REG_READ(ah, gpioOffset+AR5315_GPIODO);
+	reg &= ~(1 << gpio);
+	reg |= (val&1) << gpio;
+
+	OS_REG_WRITE(ah, gpioOffset+AR5315_GPIODO, reg);
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - get input lines
+ */
+uint32_t
+ar5315GpioGet(struct ath_hal *ah, uint32_t gpio)
+{
+	uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	if (gpio < AR_NUM_GPIO) {
+		uint32_t val = OS_REG_READ(ah, gpioOffset+AR5315_GPIODI);
+		val = ((val & AR5315_GPIOD_MASK) >> gpio) & 0x1;
+		return val;
+	} else  {
+		return 0xffffffff;
+	}
+}
+
+/*
+ * Set the GPIO Interrupt
+ */
+void
+ar5315GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
+{
+	uint32_t val;
+	uint32_t gpioOffset = (AR5315_GPIO_BASE - ((uint32_t) ah->ah_sh));
+
+	/* XXX bounds check gpio */
+	val = OS_REG_READ(ah, gpioOffset+AR5315_GPIOINT);
+	val &= ~(AR5315_GPIOINT_M | AR5315_GPIOINTLVL_M);
+	val |= gpio << AR5315_GPIOINT_S;
+	if (ilevel)
+		val |= 2 << AR5315_GPIOINTLVL_S;	/* interrupt on pin high */
+	else
+		val |= 1 << AR5315_GPIOINTLVL_S;	/* interrupt on pin low */
+
+	/* Don't need to change anything for low level interrupt. */
+	OS_REG_WRITE(ah, gpioOffset+AR5315_GPIOINT, val);
+
+	/* Change the interrupt mask. */
+	(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);
+}
+
+
+#endif /* AH_SUPPORT_2316 || AH_SUPPORT_2317 */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar2133.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar2133.c
new file mode 100644
index 0000000..5d90b6e
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar2133.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar2133.c,v 1.13 2008/11/11 00:11:30 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ah_eeprom_v14.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+#define N(a)    (sizeof(a)/sizeof(a[0]))
+
+struct ar2133State {
+	RF_HAL_FUNCS	base;		/* public state, must be first */
+	uint16_t	pcdacTable[1];
+
+	uint32_t	*Bank0Data;
+	uint32_t	*Bank1Data;
+	uint32_t	*Bank2Data;
+	uint32_t	*Bank3Data;
+	uint32_t	*Bank6Data;
+	uint32_t	*Bank7Data;
+
+	/* NB: Bank*Data storage follows */
+};
+#define	AR2133(ah)	((struct ar2133State *) AH5212(ah)->ah_rfHal)
+
+#define	ar5416ModifyRfBuffer	ar5212ModifyRfBuffer	/*XXX*/
+
+extern  void ar5416ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
+	uint32_t numBits, uint32_t firstBit, uint32_t column);
+HAL_BOOL ar2133GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL 
+	*chans, uint32_t nchans);
+	
+static HAL_BOOL ar2133GetChannelMaxMinPower(struct ath_hal *, HAL_CHANNEL *, 
+		int16_t *maxPow,int16_t *minPow);
+int16_t ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);
+
+static void
+ar2133WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
+	int writes)
+{
+	(void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
+		freqIndex, writes);
+}
+
+/*
+ * Take the MHz channel value and set the Channel value
+ *
+ * ASSUMES: Writes enabled to analog bus
+ */
+static HAL_BOOL
+ar2133SetChannel(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan)
+{
+	uint32_t channelSel  = 0;
+	uint32_t bModeSynth  = 0;
+	uint32_t aModeRefSel = 0;
+	uint32_t reg32       = 0;
+	uint16_t freq;
+	CHAN_CENTERS centers;
+    
+	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
+    
+	ar5416GetChannelCenters(ah,  chan, &centers);
+	freq = centers.synth_center;
+
+	if (freq < 4800) {
+		uint32_t txctl;
+
+		if (((freq - 2192) % 5) == 0) {
+			channelSel = ((freq - 672) * 2 - 3040)/10;
+			bModeSynth = 0;
+		} else if (((freq - 2224) % 5) == 0) {
+			channelSel = ((freq - 704) * 2 - 3040) / 10;
+			bModeSynth = 1;
+		} else {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: invalid channel %u MHz\n", __func__, freq);
+			return AH_FALSE;
+		}
+
+		channelSel = (channelSel << 2) & 0xff;
+		channelSel = ath_hal_reverseBits(channelSel, 8);
+
+		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
+		if (freq == 2484) {
+			/* Enable channel spreading for channel 14 */
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
+		} else {
+			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
+ 			txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
+		}
+	} else if ((freq % 20) == 0 && freq >= 5120) {
+		channelSel = ath_hal_reverseBits(((freq - 4800) / 20 << 2), 8);
+		if (AR_SREV_SOWL_10_OR_LATER(ah))
+			aModeRefSel = ath_hal_reverseBits(3, 2);
+		else
+			aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else if ((freq % 10) == 0) {
+		channelSel = ath_hal_reverseBits(((freq - 4800) / 10 << 1), 8);
+		if (AR_SREV_SOWL_10_OR_LATER(ah))
+			aModeRefSel = ath_hal_reverseBits(2, 2);
+		else
+			aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else if ((freq % 5) == 0) {
+		channelSel = ath_hal_reverseBits((freq - 4800) / 5, 8);
+		aModeRefSel = ath_hal_reverseBits(1, 2);
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
+		    __func__, freq);
+		return AH_FALSE;
+	}
+
+	reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
+		(1 << 5) | 0x1;
+
+	OS_REG_WRITE(ah, AR_PHY(0x37), reg32);
+
+	AH_PRIVATE(ah)->ah_curchan = chan;
+	return AH_TRUE;
+
+}
+
+/*
+ * Return a reference to the requested RF Bank.
+ */
+static uint32_t *
+ar2133GetRfBank(struct ath_hal *ah, int bank)
+{
+	struct ar2133State *priv = AR2133(ah);
+
+	HALASSERT(priv != AH_NULL);
+	switch (bank) {
+	case 1: return priv->Bank1Data;
+	case 2: return priv->Bank2Data;
+	case 3: return priv->Bank3Data;
+	case 6: return priv->Bank6Data;
+	case 7: return priv->Bank7Data;
+	}
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
+	    __func__, bank);
+	return AH_NULL;
+}
+
+/*
+ * Reads EEPROM header info from device structure and programs
+ * all rf registers
+ *
+ * REQUIRES: Access to the analog rf device
+ */
+static HAL_BOOL
+ar2133SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+                uint16_t modesIndex, uint16_t *rfXpdGain)
+{
+	struct ar2133State *priv = AR2133(ah);
+	int writes;
+
+	HALASSERT(priv);
+
+	/* Setup Bank 0 Write */
+	ath_hal_ini_bank_setup(priv->Bank0Data, &AH5416(ah)->ah_ini_bank0, 1);
+
+	/* Setup Bank 1 Write */
+	ath_hal_ini_bank_setup(priv->Bank1Data, &AH5416(ah)->ah_ini_bank1, 1);
+
+	/* Setup Bank 2 Write */
+	ath_hal_ini_bank_setup(priv->Bank2Data, &AH5416(ah)->ah_ini_bank2, 1);
+
+	/* Setup Bank 3 Write */
+	ath_hal_ini_bank_setup(priv->Bank3Data, &AH5416(ah)->ah_ini_bank3, modesIndex);
+
+	/* Setup Bank 6 Write */
+	ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex);
+	
+	/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
+	if (IS_CHAN_2GHZ(chan)) {
+		ar5416ModifyRfBuffer(priv->Bank6Data,
+		    ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL), 3, 197, 0);
+		ar5416ModifyRfBuffer(priv->Bank6Data,
+		    ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL), 3, 194, 0);
+	} else {
+		ar5416ModifyRfBuffer(priv->Bank6Data,
+		    ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL), 3, 203, 0);
+		ar5416ModifyRfBuffer(priv->Bank6Data,
+		    ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL), 3, 200, 0);
+	}
+	/* Setup Bank 7 Setup */
+	ath_hal_ini_bank_setup(priv->Bank7Data, &AH5416(ah)->ah_ini_bank7, 1);
+
+	/* Write Analog registers */
+	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank0,
+	    priv->Bank0Data, 0);
+	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank1,
+	    priv->Bank1Data, writes);
+	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank2,
+	    priv->Bank2Data, writes);
+	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank3,
+	    priv->Bank3Data, writes);
+	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6,
+	    priv->Bank6Data, writes);
+	(void) ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank7,
+	    priv->Bank7Data, writes);
+
+	return AH_TRUE;
+#undef  RF_BANK_SETUP
+}
+
+/*
+ * Read the transmit power levels from the structures taken from EEPROM
+ * Interpolate read transmit power values for this channel
+ * Organize the transmit power values into a table for writing into the hardware
+ */
+
+static HAL_BOOL
+ar2133SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax, 
+	HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain)
+{
+	return AH_TRUE;
+}
+
+#if 0
+static int16_t
+ar2133GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
+{
+    int i, minIndex;
+    int16_t minGain,minPwr,minPcdac,retVal;
+
+    /* Assume NUM_POINTS_XPD0 > 0 */
+    minGain = data->pDataPerXPD[0].xpd_gain;
+    for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
+        if (data->pDataPerXPD[i].xpd_gain < minGain) {
+            minIndex = i;
+            minGain = data->pDataPerXPD[i].xpd_gain;
+        }
+    }
+    minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
+    minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
+    for (i=1; i<NUM_POINTS_XPD0; i++) {
+        if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
+            minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
+            minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
+        }
+    }
+    retVal = minPwr - (minPcdac*2);
+    return(retVal);
+}
+#endif
+
+static HAL_BOOL
+ar2133GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan, int16_t *maxPow,
+                int16_t *minPow)
+{
+#if 0
+    struct ath_hal_5212 *ahp = AH5212(ah);
+    int numChannels=0,i,last;
+    int totalD, totalF,totalMin;
+    EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
+    EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
+
+    *maxPow = 0;
+    if (IS_CHAN_A(chan)) {
+        powerArray = ahp->ah_modePowerArray5112;
+        data = powerArray[headerInfo11A].pDataPerChannel;
+        numChannels = powerArray[headerInfo11A].numChannels;
+    } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
+        /* XXX - is this correct? Should we also use the same power for turbo G? */
+        powerArray = ahp->ah_modePowerArray5112;
+        data = powerArray[headerInfo11G].pDataPerChannel;
+        numChannels = powerArray[headerInfo11G].numChannels;
+    } else if (IS_CHAN_B(chan)) {
+        powerArray = ahp->ah_modePowerArray5112;
+        data = powerArray[headerInfo11B].pDataPerChannel;
+        numChannels = powerArray[headerInfo11B].numChannels;
+    } else {
+        return (AH_TRUE);
+    }
+    /* Make sure the channel is in the range of the TP values
+     *  (freq piers)
+     */
+    if ((numChannels < 1) ||
+        (chan->channel < data[0].channelValue) ||
+        (chan->channel > data[numChannels-1].channelValue))
+        return(AH_FALSE);
+
+    /* Linearly interpolate the power value now */
+    for (last=0,i=0;
+         (i<numChannels) && (chan->channel > data[i].channelValue);
+         last=i++);
+    totalD = data[i].channelValue - data[last].channelValue;
+    if (totalD > 0) {
+        totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
+        *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
+
+        totalMin = ar2133GetMinPower(ah,&data[i]) - ar2133GetMinPower(ah, &data[last]);
+        *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar2133GetMinPower(ah, &data[last])*totalD)/totalD);
+        return (AH_TRUE);
+    } else {
+        if (chan->channel == data[i].channelValue) {
+            *maxPow = data[i].maxPower_t4;
+            *minPow = ar2133GetMinPower(ah, &data[i]);
+            return(AH_TRUE);
+        } else
+            return(AH_FALSE);
+    }
+#else
+    *maxPow = *minPow = 0;
+	return AH_FALSE;
+#endif
+}
+
+static void 
+ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
+{
+	struct ath_hal_5416 *ahp = AH5416(ah);
+	int16_t nf;
+
+	switch (ahp->ah_rx_chainmask) {
+        case 0x7:
+		nf = MS(OS_REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
+		if (nf & 0x100)
+			nf = 0 - ((nf ^ 0x1ff) + 1);
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "NF calibrated [ctl] [chain 2] is %d\n", nf);
+		nfarray[4] = nf;
+
+		nf = MS(OS_REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
+		if (nf & 0x100)
+			nf = 0 - ((nf ^ 0x1ff) + 1);
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "NF calibrated [ext] [chain 2] is %d\n", nf);
+		nfarray[5] = nf;
+		/* fall thru... */
+        case 0x3:
+        case 0x5:
+		nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
+		if (nf & 0x100)
+			nf = 0 - ((nf ^ 0x1ff) + 1);
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "NF calibrated [ctl] [chain 1] is %d\n", nf);
+		nfarray[2] = nf;
+
+
+		nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
+		if (nf & 0x100)
+			nf = 0 - ((nf ^ 0x1ff) + 1);
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "NF calibrated [ext] [chain 1] is %d\n", nf);
+		nfarray[3] = nf;
+		/* fall thru... */
+        case 0x1:
+		nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
+		if (nf & 0x100)
+			nf = 0 - ((nf ^ 0x1ff) + 1);
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "NF calibrated [ctl] [chain 0] is %d\n", nf);
+		nfarray[0] = nf;
+
+		nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
+		if (nf & 0x100)
+			nf = 0 - ((nf ^ 0x1ff) + 1);
+		HALDEBUG(ah, HAL_DEBUG_NFCAL,
+		    "NF calibrated [ext] [chain 0] is %d\n", nf);
+		nfarray[1] = nf;
+
+		break;
+	}
+}
+
+/*
+ * Adjust NF based on statistical values for 5GHz frequencies.
+ * Stubbed:Not used by Fowl
+ */
+int16_t
+ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
+{
+	return 0;
+}
+
+/*
+ * Free memory for analog bank scratch buffers
+ */
+static void
+ar2133RfDetach(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(ahp->ah_rfHal != AH_NULL);
+	ath_hal_free(ahp->ah_rfHal);
+	ahp->ah_rfHal = AH_NULL;
+}
+	
+/*
+ * Allocate memory for analog bank scratch buffers
+ * Scratch Buffer will be reinitialized every reset so no need to zero now
+ */
+HAL_BOOL
+ar2133RfAttach(struct ath_hal *ah, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar2133State *priv;
+	uint32_t *bankData;
+
+	HALASSERT(ahp->ah_rfHal == AH_NULL);
+	priv = ath_hal_malloc(sizeof(struct ar2133State)
+	    + AH5416(ah)->ah_ini_bank0.rows * sizeof(uint32_t)
+	    + AH5416(ah)->ah_ini_bank1.rows * sizeof(uint32_t)
+	    + AH5416(ah)->ah_ini_bank2.rows * sizeof(uint32_t)
+	    + AH5416(ah)->ah_ini_bank3.rows * sizeof(uint32_t)
+	    + AH5416(ah)->ah_ini_bank6.rows * sizeof(uint32_t)
+	    + AH5416(ah)->ah_ini_bank7.rows * sizeof(uint32_t)
+	);
+	if (priv == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: cannot allocate private state\n", __func__);
+		*status = HAL_ENOMEM;		/* XXX */
+		return AH_FALSE;
+	}
+	priv->base.rfDetach		= ar2133RfDetach;
+	priv->base.writeRegs		= ar2133WriteRegs;
+	priv->base.getRfBank		= ar2133GetRfBank;
+	priv->base.setChannel		= ar2133SetChannel;
+	priv->base.setRfRegs		= ar2133SetRfRegs;
+	priv->base.setPowerTable	= ar2133SetPowerTable;
+	priv->base.getChannelMaxMinPower = ar2133GetChannelMaxMinPower;
+	priv->base.getNfAdjust		= ar2133GetNfAdjust;
+
+	bankData = (uint32_t *) &priv[1];
+	priv->Bank0Data = bankData, bankData += AH5416(ah)->ah_ini_bank0.rows;
+	priv->Bank1Data = bankData, bankData += AH5416(ah)->ah_ini_bank1.rows;
+	priv->Bank2Data = bankData, bankData += AH5416(ah)->ah_ini_bank2.rows;
+	priv->Bank3Data = bankData, bankData += AH5416(ah)->ah_ini_bank3.rows;
+	priv->Bank6Data = bankData, bankData += AH5416(ah)->ah_ini_bank6.rows;
+	priv->Bank7Data = bankData, bankData += AH5416(ah)->ah_ini_bank7.rows;
+
+	ahp->ah_pcdacTable = priv->pcdacTable;
+	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
+	ahp->ah_rfHal = &priv->base;
+	/*
+	 * Set noise floor adjust method; we arrange a
+	 * direct call instead of thunking.
+	 */
+	AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
+	AH_PRIVATE(ah)->ah_getNoiseFloor = ar2133GetNoiseFloor;
+
+	return AH_TRUE;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416.h b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416.h
new file mode 100644
index 0000000..34e76b9
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416.h,v 1.19 2008/11/11 21:38:13 sam Exp $
+ */
+#ifndef _ATH_AR5416_H_
+#define _ATH_AR5416_H_
+
+#include "ar5212/ar5212.h"
+#include "ar5416_cal.h"
+
+#define	AR5416_MAGIC	0x20065416
+
+enum {
+	HAL_RESET_POWER_ON,
+	HAL_RESET_WARM,
+	HAL_RESET_COLD,
+};
+
+typedef struct {
+	uint16_t	synth_center;
+	uint16_t	ctl_center;
+	uint16_t	ext_center;
+} CHAN_CENTERS;
+
+#define	AR5416_DEFAULT_RXCHAINMASK	7
+#define	AR5416_DEFAULT_TXCHAINMASK	1
+#define	AR5416_MAX_RATE_POWER		63
+#define	AR5416_KEYTABLE_SIZE		128
+
+#define	AR5416_CCA_MAX_GOOD_VALUE	-85
+#define	AR5416_CCA_MAX_HIGH_VALUE	-62
+#define	AR5416_CCA_MIN_BAD_VALUE	-140
+
+struct ath_hal_5416 {
+	struct ath_hal_5212 ah_5212;
+
+	/* NB: RF data setup at attach */
+	HAL_INI_ARRAY	ah_ini_bb_rfgain;
+	HAL_INI_ARRAY	ah_ini_bank0;
+	HAL_INI_ARRAY	ah_ini_bank1;
+	HAL_INI_ARRAY	ah_ini_bank2;
+	HAL_INI_ARRAY	ah_ini_bank3;
+	HAL_INI_ARRAY	ah_ini_bank6;
+	HAL_INI_ARRAY	ah_ini_bank7;
+	HAL_INI_ARRAY	ah_ini_addac;
+
+	u_int       	ah_globaltxtimeout;	/* global tx timeout */
+	int		ah_hangs;		/* h/w hangs state */
+	uint8_t		ah_keytype[AR5416_KEYTABLE_SIZE];
+	/*
+	 * Extension Channel Rx Clear State
+	 */
+	uint32_t	ah_cycleCount;
+	uint32_t	ah_ctlBusy;
+	uint32_t	ah_extBusy;
+	uint32_t	ah_rx_chainmask;
+	uint32_t	ah_tx_chainmask;
+
+	struct ar5416PerCal ah_cal;		/* periodic calibration state */
+};
+#define	AH5416(_ah)	((struct ath_hal_5416 *)(_ah))
+
+#define IS_5416_PCI(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_OWL_PCI)
+#define IS_5416_PCIE(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_OWL_PCIE)
+#undef IS_PCIE
+#define IS_PCIE(ah) (IS_5416_PCIE(ah))
+
+extern	HAL_BOOL ar2133RfAttach(struct ath_hal *, HAL_STATUS *);
+
+struct ath_hal;
+
+extern	struct ath_hal * ar5416Attach(uint16_t devid, HAL_SOFTC sc,
+		HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
+extern	void ar5416InitState(struct ath_hal_5416 *, uint16_t devid,
+		HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh,
+		HAL_STATUS *status);
+extern	void ar5416Detach(struct ath_hal *ah);
+extern	HAL_BOOL ar5416FillCapabilityInfo(struct ath_hal *ah);
+
+#define	IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
+	(IS_CHAN_5GHZ(_c) && ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G))
+
+extern	void ar5416AniAttach(struct ath_hal *, const struct ar5212AniParams *,
+		const struct ar5212AniParams *, HAL_BOOL ena);
+extern	void ar5416AniDetach(struct ath_hal *);
+extern	HAL_BOOL ar5416AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param);
+extern	HAL_BOOL ar5416AniSetParams(struct ath_hal *,
+		const struct ar5212AniParams *, const struct ar5212AniParams *);
+extern	void ar5416ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
+extern	void ar5416AniPoll(struct ath_hal *, const HAL_NODE_STATS *,
+			     HAL_CHANNEL *);
+extern	void ar5416AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *,
+		HAL_OPMODE, int);
+
+extern	void ar5416SetBeaconTimers(struct ath_hal *, const HAL_BEACON_TIMERS *);
+extern	void ar5416BeaconInit(struct ath_hal *ah,
+		uint32_t next_beacon, uint32_t beacon_period);
+extern	void ar5416ResetStaBeaconTimers(struct ath_hal *ah);
+extern	void ar5416SetStaBeaconTimers(struct ath_hal *ah,
+		const HAL_BEACON_STATE *);
+
+extern	HAL_BOOL ar5416EepromRead(struct ath_hal *, u_int off, uint16_t *data);
+extern	HAL_BOOL ar5416EepromWrite(struct ath_hal *, u_int off, uint16_t data);
+
+extern	HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah);
+extern	HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *, HAL_INT *masked);
+extern	HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints);
+
+extern	HAL_BOOL ar5416GpioCfgOutput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5416GpioCfgInput(struct ath_hal *, uint32_t gpio);
+extern	HAL_BOOL ar5416GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
+extern	uint32_t ar5416GpioGet(struct ath_hal *ah, uint32_t gpio);
+extern	void ar5416GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
+
+extern	u_int ar5416GetWirelessModes(struct ath_hal *ah);
+extern	void ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
+extern	void ar5416ResetTsf(struct ath_hal *ah);
+extern	HAL_BOOL ar5416SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
+extern	HAL_BOOL ar5416SetDecompMask(struct ath_hal *, uint16_t, int);
+extern	void ar5416SetCoverageClass(struct ath_hal *, uint8_t, int);
+extern	uint32_t ar5416Get11nExtBusy(struct ath_hal *ah);
+extern	void ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode);
+extern	HAL_HT_RXCLEAR ar5416Get11nRxClear(struct ath_hal *ah);
+extern	void ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear);
+extern	HAL_STATUS ar5416GetCapability(struct ath_hal *ah,
+	    HAL_CAPABILITY_TYPE type, uint32_t capability, uint32_t *result);
+extern	HAL_BOOL ar5416GetDiagState(struct ath_hal *ah, int request,
+	    const void *args, uint32_t argsize,
+	    void **result, uint32_t *resultsize);
+
+extern	HAL_BOOL ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
+		int setChip);
+extern	HAL_POWER_MODE ar5416GetPowerMode(struct ath_hal *ah);
+extern	HAL_BOOL ar5416GetPowerStatus(struct ath_hal *ah);
+
+extern	HAL_BOOL ar5416ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
+extern	HAL_BOOL ar5416SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
+	       const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
+
+extern	void ar5416StartPcuReceive(struct ath_hal *ah);
+extern	void ar5416StopPcuReceive(struct ath_hal *ah);
+extern	HAL_BOOL ar5416SetupRxDesc(struct ath_hal *,
+		struct ath_desc *, uint32_t size, u_int flags);
+extern	HAL_STATUS ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
+		uint32_t, struct ath_desc *, uint64_t,
+		struct ath_rx_status *);
+
+extern	HAL_BOOL ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
+		HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status);
+extern	HAL_BOOL ar5416PhyDisable(struct ath_hal *ah);
+extern	HAL_RFGAIN ar5416GetRfgain(struct ath_hal *ah);
+extern	HAL_BOOL ar5416Disable(struct ath_hal *ah);
+extern	HAL_BOOL ar5416ChipReset(struct ath_hal *ah, HAL_CHANNEL *);
+extern	HAL_BOOL ar5416SetResetReg(struct ath_hal *, uint32_t type);
+extern	HAL_BOOL ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
+extern	HAL_BOOL ar5416GetChipPowerLimits(struct ath_hal *ah,
+		HAL_CHANNEL *chans, uint32_t nchans);
+extern	void ar5416GetChannelCenters(struct ath_hal *,
+		HAL_CHANNEL_INTERNAL *chan, CHAN_CENTERS *centers);
+
+extern	HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, u_int q);
+extern	HAL_BOOL ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+		u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
+		u_int txRate0, u_int txTries0,
+		u_int keyIx, u_int antMode, u_int flags,
+		u_int rtsctsRate, u_int rtsctsDuration,
+		u_int compicvLen, u_int compivLen, u_int comp);
+extern	HAL_BOOL ar5416SetupXTxDesc(struct ath_hal *, struct ath_desc *,
+		u_int txRate1, u_int txRetries1,
+		u_int txRate2, u_int txRetries2,
+		u_int txRate3, u_int txRetries3);
+extern	HAL_BOOL ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+		u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
+		const struct ath_desc *ds0);
+extern	HAL_STATUS ar5416ProcTxDesc(struct ath_hal *ah,
+		struct ath_desc *, struct ath_tx_status *);
+
+extern	const HAL_RATE_TABLE *ar5416GetRateTable(struct ath_hal *, u_int mode);
+#endif	/* _ATH_AR5416_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416.ini b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416.ini
new file mode 100644
index 0000000..6e96f68
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416.ini
@@ -0,0 +1,688 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416.ini,v 1.3 2008/11/10 04:08:04 sam Exp $
+ */
+/* Auto Generated PCI Register Writes.  Created: 09/20/06 */
+
+static const uint32_t ar5416Modes[][6] = {
+   /* Register    A           A-20/40     G-20/40     G           G-Turbo    */
+    { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
+    { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
+    { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
+    { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
+    { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
+    { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
+    { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
+    { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
+    { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
+    { 0x00009844, 0x1372161e, 0x13721c1e, 0x13721c30, 0x137216a4, 0x13721c25 },
+    { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x00009850, 0x6c28b4e0, 0x6c28b4e0, 0x6d68b0de, 0x6d68b0de, 0x6c28b0de },
+    { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
+    { 0x0000985c, 0x313a5d5e, 0x313a5d5e, 0x313a605e, 0x313a605e, 0x313a5d5e },
+    { 0x00009860, 0x00049d10, 0x00049d10, 0x00049d20, 0x00049d20, 0x00049d10 },
+    { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+    { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
+    { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000370 },
+    { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a19, 0xd0058a13, 0xd0058a0b },
+    { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
+#ifdef TB243
+    { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
+    { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
+    { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
+    { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
+#else
+    { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
+    { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
+    { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
+#ifdef __LINUX_ARM_ARCH__
+    { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
+#else
+    { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
+#endif
+#endif
+    { 0x0000c9bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
+    { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
+    { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
+    { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },
+    { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
+    { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
+    { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a204, 0x00000440, 0x00000440, 0x00000440, 0x00000440, 0x00000440 },
+    { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
+    { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
+    { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
+    { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
+    { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
+    { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
+    { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
+    { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
+    { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
+    { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
+    { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
+    { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
+    { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
+    { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
+    { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
+static const uint32_t ar5416Common[][2] = {
+    { 0x0000000c, 0x00000000 },
+    { 0x00000030, 0x00020015 },
+    { 0x00000034, 0x00000005 },
+    { 0x00000040, 0x00000000 },
+    { 0x00000044, 0x00000008 },
+    { 0x00000048, 0x00000008 },
+    { 0x0000004c, 0x00000010 },
+    { 0x00000050, 0x00000000 },
+    { 0x00000054, 0x0000001f },
+    { 0x00000800, 0x00000000 },
+    { 0x00000804, 0x00000000 },
+    { 0x00000808, 0x00000000 },
+    { 0x0000080c, 0x00000000 },
+    { 0x00000810, 0x00000000 },
+    { 0x00000814, 0x00000000 },
+    { 0x00000818, 0x00000000 },
+    { 0x0000081c, 0x00000000 },
+    { 0x00000820, 0x00000000 },
+    { 0x00000824, 0x00000000 },
+    { 0x00001040, 0x002ffc0f },
+    { 0x00001044, 0x002ffc0f },
+    { 0x00001048, 0x002ffc0f },
+    { 0x0000104c, 0x002ffc0f },
+    { 0x00001050, 0x002ffc0f },
+    { 0x00001054, 0x002ffc0f },
+    { 0x00001058, 0x002ffc0f },
+    { 0x0000105c, 0x002ffc0f },
+    { 0x00001060, 0x002ffc0f },
+    { 0x00001064, 0x002ffc0f },
+    { 0x00001230, 0x00000000 },
+    { 0x00001270, 0x00000000 },
+    { 0x00001038, 0x00000000 },
+    { 0x00001078, 0x00000000 },
+    { 0x000010b8, 0x00000000 },
+    { 0x000010f8, 0x00000000 },
+    { 0x00001138, 0x00000000 },
+    { 0x00001178, 0x00000000 },
+    { 0x000011b8, 0x00000000 },
+    { 0x000011f8, 0x00000000 },
+    { 0x00001238, 0x00000000 },
+    { 0x00001278, 0x00000000 },
+    { 0x000012b8, 0x00000000 },
+    { 0x000012f8, 0x00000000 },
+    { 0x00001338, 0x00000000 },
+    { 0x00001378, 0x00000000 },
+    { 0x000013b8, 0x00000000 },
+    { 0x000013f8, 0x00000000 },
+    { 0x00001438, 0x00000000 },
+    { 0x00001478, 0x00000000 },
+    { 0x000014b8, 0x00000000 },
+    { 0x000014f8, 0x00000000 },
+    { 0x00001538, 0x00000000 },
+    { 0x00001578, 0x00000000 },
+    { 0x000015b8, 0x00000000 },
+    { 0x000015f8, 0x00000000 },
+    { 0x00001638, 0x00000000 },
+    { 0x00001678, 0x00000000 },
+    { 0x000016b8, 0x00000000 },
+    { 0x000016f8, 0x00000000 },
+    { 0x00001738, 0x00000000 },
+    { 0x00001778, 0x00000000 },
+    { 0x000017b8, 0x00000000 },
+    { 0x000017f8, 0x00000000 },
+    { 0x0000103c, 0x00000000 },
+    { 0x0000107c, 0x00000000 },
+    { 0x000010bc, 0x00000000 },
+    { 0x000010fc, 0x00000000 },
+    { 0x0000113c, 0x00000000 },
+    { 0x0000117c, 0x00000000 },
+    { 0x000011bc, 0x00000000 },
+    { 0x000011fc, 0x00000000 },
+    { 0x0000123c, 0x00000000 },
+    { 0x0000127c, 0x00000000 },
+    { 0x000012bc, 0x00000000 },
+    { 0x000012fc, 0x00000000 },
+    { 0x0000133c, 0x00000000 },
+    { 0x0000137c, 0x00000000 },
+    { 0x000013bc, 0x00000000 },
+    { 0x000013fc, 0x00000000 },
+    { 0x0000143c, 0x00000000 },
+    { 0x0000147c, 0x00000000 },
+    { 0x00004030, 0x00000002 },
+    { 0x0000403c, 0x00000002 },
+#ifdef AR9100
+    { 0x00020010, 0x00000000 },
+#else
+    { 0x00007010, 0x00000000 },
+#endif
+    { 0x00007038, 0x000004c2 },
+    { 0x00008004, 0x00000000 },
+    { 0x00008008, 0x00000000 },
+    { 0x0000800c, 0x00000000 },
+    { 0x00008018, 0x00000700 },
+    { 0x00008020, 0x00000000 },
+    { 0x00008038, 0x00000000 },
+    { 0x0000803c, 0x00000000 },
+    { 0x00008048, 0x40000000 },
+    { 0x00008054, 0x00000000 },
+    { 0x00008058, 0x00000000 },
+    { 0x0000805c, 0x000fc78f },
+    { 0x00008060, 0x0000000f },
+    { 0x00008064, 0x00000000 },
+    { 0x000080c0, 0x2a82301a },
+    { 0x000080c4, 0x05dc01e0 },
+    { 0x000080c8, 0x1f402710 },
+    { 0x000080cc, 0x01f40000 },
+    { 0x000080d0, 0x00001e00 },
+    { 0x000080d4, 0x00000000 },
+    { 0x000080d8, 0x00400000 },
+    { 0x000080e0, 0xffffffff },
+    { 0x000080e4, 0x0000ffff },
+    { 0x000080e8, 0x003f3f3f },
+    { 0x000080ec, 0x00000000 },
+    { 0x000080f0, 0x00000000 },
+    { 0x000080f4, 0x00000000 },
+    { 0x000080f8, 0x00000000 },
+    { 0x000080fc, 0x00020000 },
+    { 0x00008100, 0x00020000 },
+    { 0x00008104, 0x00000001 },
+    { 0x00008108, 0x00000052 },
+    { 0x0000810c, 0x00000000 },
+    { 0x00008110, 0x00000168 },
+    { 0x00008118, 0x000100aa },
+    { 0x0000811c, 0x00003210 },
+    { 0x00008120, 0x08f04800 },
+    { 0x00008124, 0x00000000 },
+    { 0x00008128, 0x00000000 },
+    { 0x0000812c, 0x00000000 },
+    { 0x00008130, 0x00000000 },
+    { 0x00008134, 0x00000000 },
+    { 0x00008138, 0x00000000 },
+    { 0x0000813c, 0x00000000 },
+    { 0x00008144, 0x00000000 },
+    { 0x00008168, 0x00000000 },
+    { 0x0000816c, 0x00000000 },
+    { 0x00008170, 0x32143320 },
+    { 0x00008174, 0xfaa4fa50 },
+    { 0x00008178, 0x00000100 },
+    { 0x0000817c, 0x00000000 },
+    { 0x000081c4, 0x00000000 },
+    { 0x000081d0, 0x00003210 },
+    { 0x000081ec, 0x00000000 },
+    { 0x000081f0, 0x00000000 },
+    { 0x000081f4, 0x00000000 },
+    { 0x000081f8, 0x00000000 },
+    { 0x000081fc, 0x00000000 },
+    { 0x00008200, 0x00000000 },
+    { 0x00008204, 0x00000000 },
+    { 0x00008208, 0x00000000 },
+    { 0x0000820c, 0x00000000 },
+    { 0x00008210, 0x00000000 },
+    { 0x00008214, 0x00000000 },
+    { 0x00008218, 0x00000000 },
+    { 0x0000821c, 0x00000000 },
+    { 0x00008220, 0x00000000 },
+    { 0x00008224, 0x00000000 },
+    { 0x00008228, 0x00000000 },
+    { 0x0000822c, 0x00000000 },
+    { 0x00008230, 0x00000000 },
+    { 0x00008234, 0x00000000 },
+    { 0x00008238, 0x00000000 },
+    { 0x0000823c, 0x00000000 },
+    { 0x00008240, 0x00100000 },
+    { 0x00008244, 0x0010f400 },
+    { 0x00008248, 0x00000100 },
+    { 0x0000824c, 0x0001e800 },
+    { 0x00008250, 0x00000000 },
+    { 0x00008254, 0x00000000 },
+    { 0x00008258, 0x00000000 },
+    { 0x0000825c, 0x400000ff },
+    { 0x00008260, 0x00080922 },
+    { 0x00008270, 0x00000000 },
+    { 0x00008274, 0x40000000 },
+    { 0x00008278, 0x003e4180 },
+    { 0x0000827c, 0x00000000 },
+    { 0x00008284, 0x0000002c },
+    { 0x00008288, 0x0000002c },
+    { 0x0000828c, 0x00000000 },
+    { 0x00008294, 0x00000000 },
+    { 0x00008298, 0x00000000 },
+    { 0x00008300, 0x00000000 },
+    { 0x00008304, 0x00000000 },
+    { 0x00008308, 0x00000000 },
+    { 0x0000830c, 0x00000000 },
+    { 0x00008310, 0x00000000 },
+    { 0x00008314, 0x00000000 },
+    { 0x00008318, 0x00000000 },
+    { 0x00008328, 0x00000000 },
+    { 0x0000832c, 0x00000007 },
+    { 0x00008330, 0x00000302 },
+    { 0x00008334, 0x00000e00 },
+    { 0x00008338, 0x00000000 },
+    { 0x0000833c, 0x00000000 },
+    { 0x00008340, 0x000107ff },
+    { 0x00009808, 0x00000000 },
+    { 0x0000980c, 0xad848e19 },
+    { 0x00009810, 0x7d14e000 },
+    { 0x00009814, 0x9c0a9f6b },
+    { 0x0000981c, 0x00000000 },
+    { 0x0000982c, 0x0000a000 },
+    { 0x00009830, 0x00000000 },
+    { 0x0000983c, 0x00200400 },
+    { 0x00009840, 0x206a016e },
+    { 0x0000984c, 0x1284233c },
+    { 0x00009854, 0x00000859 },
+    { 0x00009900, 0x00000000 },
+    { 0x00009904, 0x00000000 },
+    { 0x00009908, 0x00000000 },
+    { 0x0000990c, 0x00000000 },
+    { 0x0000991c, 0x10000fff },
+    { 0x00009920, 0x05100000 },
+    { 0x0000a920, 0x05100000 },
+    { 0x0000b920, 0x05100000 },
+    { 0x00009928, 0x00000001 },
+    { 0x0000992c, 0x00000004 },
+    { 0x00009934, 0x1e1f2022 },
+    { 0x00009938, 0x0a0b0c0d },
+    { 0x0000993c, 0x00000000 },
+    { 0x00009948, 0x9280b212 },
+    { 0x0000994c, 0x00020028 },
+    { 0x00009954, 0x5d50e188 },
+    { 0x00009958, 0x00081fff },
+    { 0x0000c95c, 0x004b6a8e },
+    { 0x0000c968, 0x000003ce },
+    { 0x00009970, 0x190c0514 },
+    { 0x00009974, 0x00000000 },
+    { 0x00009978, 0x00000001 },
+    { 0x0000997c, 0x00000000 },
+    { 0x00009980, 0x00000000 },
+    { 0x00009984, 0x00000000 },
+    { 0x00009988, 0x00000000 },
+    { 0x0000998c, 0x00000000 },
+    { 0x00009990, 0x00000000 },
+    { 0x00009994, 0x00000000 },
+    { 0x00009998, 0x00000000 },
+    { 0x0000999c, 0x00000000 },
+    { 0x000099a0, 0x00000000 },
+    { 0x000099a4, 0x00000001 },
+    { 0x000099a8, 0x001fff00 },
+    { 0x000099ac, 0x000000c4 },
+    { 0x000099b0, 0x03051000 },
+    { 0x000099dc, 0x00000000 },
+    { 0x000099e0, 0x00000200 },
+    { 0x000099e4, 0xaaaaaaaa },
+    { 0x000099e8, 0x3c466478 },
+    { 0x000099ec, 0x000000aa },
+    { 0x000099fc, 0x00001042 },
+    { 0x00009b00, 0x00000000 },
+    { 0x00009b04, 0x00000001 },
+    { 0x00009b08, 0x00000002 },
+    { 0x00009b0c, 0x00000003 },
+    { 0x00009b10, 0x00000004 },
+    { 0x00009b14, 0x00000005 },
+    { 0x00009b18, 0x00000008 },
+    { 0x00009b1c, 0x00000009 },
+    { 0x00009b20, 0x0000000a },
+    { 0x00009b24, 0x0000000b },
+    { 0x00009b28, 0x0000000c },
+    { 0x00009b2c, 0x0000000d },
+    { 0x00009b30, 0x00000010 },
+    { 0x00009b34, 0x00000011 },
+    { 0x00009b38, 0x00000012 },
+    { 0x00009b3c, 0x00000013 },
+    { 0x00009b40, 0x00000014 },
+    { 0x00009b44, 0x00000015 },
+    { 0x00009b48, 0x00000018 },
+    { 0x00009b4c, 0x00000019 },
+    { 0x00009b50, 0x0000001a },
+    { 0x00009b54, 0x0000001b },
+    { 0x00009b58, 0x0000001c },
+    { 0x00009b5c, 0x0000001d },
+    { 0x00009b60, 0x00000020 },
+    { 0x00009b64, 0x00000021 },
+    { 0x00009b68, 0x00000022 },
+    { 0x00009b6c, 0x00000023 },
+    { 0x00009b70, 0x00000024 },
+    { 0x00009b74, 0x00000025 },
+    { 0x00009b78, 0x00000028 },
+    { 0x00009b7c, 0x00000029 },
+    { 0x00009b80, 0x0000002a },
+    { 0x00009b84, 0x0000002b },
+    { 0x00009b88, 0x0000002c },
+    { 0x00009b8c, 0x0000002d },
+    { 0x00009b90, 0x00000030 },
+    { 0x00009b94, 0x00000031 },
+    { 0x00009b98, 0x00000032 },
+    { 0x00009b9c, 0x00000033 },
+    { 0x00009ba0, 0x00000034 },
+    { 0x00009ba4, 0x00000035 },
+    { 0x00009ba8, 0x00000035 },
+    { 0x00009bac, 0x00000035 },
+    { 0x00009bb0, 0x00000035 },
+    { 0x00009bb4, 0x00000035 },
+    { 0x00009bb8, 0x00000035 },
+    { 0x00009bbc, 0x00000035 },
+    { 0x00009bc0, 0x00000035 },
+    { 0x00009bc4, 0x00000035 },
+    { 0x00009bc8, 0x00000035 },
+    { 0x00009bcc, 0x00000035 },
+    { 0x00009bd0, 0x00000035 },
+    { 0x00009bd4, 0x00000035 },
+    { 0x00009bd8, 0x00000035 },
+    { 0x00009bdc, 0x00000035 },
+    { 0x00009be0, 0x00000035 },
+    { 0x00009be4, 0x00000035 },
+    { 0x00009be8, 0x00000035 },
+    { 0x00009bec, 0x00000035 },
+    { 0x00009bf0, 0x00000035 },
+    { 0x00009bf4, 0x00000035 },
+    { 0x00009bf8, 0x00000010 },
+    { 0x00009bfc, 0x0000001a },
+    { 0x0000a210, 0x40806333 },
+    { 0x0000a214, 0x00106c10 },
+    { 0x0000a218, 0x009c4060 },
+    { 0x0000a220, 0x018830c6 },
+    { 0x0000a224, 0x00000400 },
+    { 0x0000a228, 0x00000bb5 },
+    { 0x0000a22c, 0x00000011 },
+    { 0x0000a234, 0x20202020 },
+    { 0x0000a238, 0x20202020 },
+    { 0x0000a23c, 0x13c889af },
+    { 0x0000a240, 0x38490a20 },
+    { 0x0000a244, 0x00007bb6 },
+    { 0x0000a248, 0x0fff3ffc },
+    { 0x0000a24c, 0x00000001 },
+    { 0x0000a250, 0x0000a000 },
+    { 0x0000a254, 0x00000000 },
+    { 0x0000a258, 0x0cc75380 },
+    { 0x0000a25c, 0x0f0f0f01 },
+    { 0x0000a260, 0xdfa91f01 },
+    { 0x0000a268, 0x00000000 },
+    { 0x0000a26c, 0x0ebae9c6 },
+    { 0x0000b26c, 0x0ebae9c6 },
+    { 0x0000c26c, 0x0ebae9c6 },
+    { 0x0000d270, 0x00820820 },
+    { 0x0000a278, 0x1ce739ce },
+    { 0x0000a27c, 0x051701ce },
+    { 0x0000a338, 0x00000000 },
+    { 0x0000a33c, 0x00000000 },
+    { 0x0000a340, 0x00000000 },
+    { 0x0000a344, 0x00000000 },
+    { 0x0000a348, 0x3fffffff },
+    { 0x0000a34c, 0x3fffffff },
+    { 0x0000a350, 0x3fffffff },
+    { 0x0000a354, 0x0003ffff },
+    { 0x0000a358, 0x79a8aa1f },
+    { 0x0000d35c, 0x066c420f },
+    { 0x0000d360, 0x0f282207 },
+    { 0x0000d364, 0x17601685 },
+    { 0x0000d368, 0x1f801104 },
+    { 0x0000d36c, 0x37a00c03 },
+    { 0x0000d370, 0x3fc40883 },
+    { 0x0000d374, 0x57c00803 },
+    { 0x0000d378, 0x5fd80682 },
+    { 0x0000d37c, 0x7fe00482 },
+    { 0x0000d380, 0x7f3c7bba },
+    { 0x0000d384, 0xf3307ff0 },
+    { 0x0000a388, 0x08000000 },
+    { 0x0000a38c, 0x20202020 },
+    { 0x0000a390, 0x20202020 },
+    { 0x0000a394, 0x1ce739ce },
+    { 0x0000a398, 0x000001ce },
+    { 0x0000a39c, 0x00000001 },
+    { 0x0000a3a0, 0x00000000 },
+    { 0x0000a3a4, 0x00000000 },
+    { 0x0000a3a8, 0x00000000 },
+    { 0x0000a3ac, 0x00000000 },
+    { 0x0000a3b0, 0x00000000 },
+    { 0x0000a3b4, 0x00000000 },
+    { 0x0000a3b8, 0x00000000 },
+    { 0x0000a3bc, 0x00000000 },
+    { 0x0000a3c0, 0x00000000 },
+    { 0x0000a3c4, 0x00000000 },
+    { 0x0000a3c8, 0x00000246 },
+    { 0x0000a3cc, 0x20202020 },
+    { 0x0000a3d0, 0x20202020 },
+    { 0x0000a3d4, 0x20202020 },
+    { 0x0000a3dc, 0x1ce739ce },
+    { 0x0000a3e0, 0x000001ce },
+};
+
+static const uint32_t ar5416Bank0[][2] = {
+    { 0x000098b0, 0x1e5795e5 },
+    { 0x000098e0, 0x02008020 },
+};
+
+static const uint32_t ar5416BB_RfGain[][3] = {
+    { 0x00009a00, 0x00000000, 0x00000000 },
+    { 0x00009a04, 0x00000040, 0x00000040 },
+    { 0x00009a08, 0x00000080, 0x00000080 },
+    { 0x00009a0c, 0x000001a1, 0x00000141 },
+    { 0x00009a10, 0x000001e1, 0x00000181 },
+    { 0x00009a14, 0x00000021, 0x000001c1 },
+    { 0x00009a18, 0x00000061, 0x00000001 },
+    { 0x00009a1c, 0x00000168, 0x00000041 },
+    { 0x00009a20, 0x000001a8, 0x000001a8 },
+    { 0x00009a24, 0x000001e8, 0x000001e8 },
+    { 0x00009a28, 0x00000028, 0x00000028 },
+    { 0x00009a2c, 0x00000068, 0x00000068 },
+    { 0x00009a30, 0x00000189, 0x000000a8 },
+    { 0x00009a34, 0x000001c9, 0x00000169 },
+    { 0x00009a38, 0x00000009, 0x000001a9 },
+    { 0x00009a3c, 0x00000049, 0x000001e9 },
+    { 0x00009a40, 0x00000089, 0x00000029 },
+    { 0x00009a44, 0x00000170, 0x00000069 },
+    { 0x00009a48, 0x000001b0, 0x00000190 },
+    { 0x00009a4c, 0x000001f0, 0x000001d0 },
+    { 0x00009a50, 0x00000030, 0x00000010 },
+    { 0x00009a54, 0x00000070, 0x00000050 },
+    { 0x00009a58, 0x00000191, 0x00000090 },
+    { 0x00009a5c, 0x000001d1, 0x00000151 },
+    { 0x00009a60, 0x00000011, 0x00000191 },
+    { 0x00009a64, 0x00000051, 0x000001d1 },
+    { 0x00009a68, 0x00000091, 0x00000011 },
+    { 0x00009a6c, 0x000001b8, 0x00000051 },
+    { 0x00009a70, 0x000001f8, 0x00000198 },
+    { 0x00009a74, 0x00000038, 0x000001d8 },
+    { 0x00009a78, 0x00000078, 0x00000018 },
+    { 0x00009a7c, 0x00000199, 0x00000058 },
+    { 0x00009a80, 0x000001d9, 0x00000098 },
+    { 0x00009a84, 0x00000019, 0x00000159 },
+    { 0x00009a88, 0x00000059, 0x00000199 },
+    { 0x00009a8c, 0x00000099, 0x000001d9 },
+    { 0x00009a90, 0x000000d9, 0x00000019 },
+    { 0x00009a94, 0x000000f9, 0x00000059 },
+    { 0x00009a98, 0x000000f9, 0x00000099 },
+    { 0x00009a9c, 0x000000f9, 0x000000d9 },
+    { 0x00009aa0, 0x000000f9, 0x000000f9 },
+    { 0x00009aa4, 0x000000f9, 0x000000f9 },
+    { 0x00009aa8, 0x000000f9, 0x000000f9 },
+    { 0x00009aac, 0x000000f9, 0x000000f9 },
+    { 0x00009ab0, 0x000000f9, 0x000000f9 },
+    { 0x00009ab4, 0x000000f9, 0x000000f9 },
+    { 0x00009ab8, 0x000000f9, 0x000000f9 },
+    { 0x00009abc, 0x000000f9, 0x000000f9 },
+    { 0x00009ac0, 0x000000f9, 0x000000f9 },
+    { 0x00009ac4, 0x000000f9, 0x000000f9 },
+    { 0x00009ac8, 0x000000f9, 0x000000f9 },
+    { 0x00009acc, 0x000000f9, 0x000000f9 },
+    { 0x00009ad0, 0x000000f9, 0x000000f9 },
+    { 0x00009ad4, 0x000000f9, 0x000000f9 },
+    { 0x00009ad8, 0x000000f9, 0x000000f9 },
+    { 0x00009adc, 0x000000f9, 0x000000f9 },
+    { 0x00009ae0, 0x000000f9, 0x000000f9 },
+    { 0x00009ae4, 0x000000f9, 0x000000f9 },
+    { 0x00009ae8, 0x000000f9, 0x000000f9 },
+    { 0x00009aec, 0x000000f9, 0x000000f9 },
+    { 0x00009af0, 0x000000f9, 0x000000f9 },
+    { 0x00009af4, 0x000000f9, 0x000000f9 },
+    { 0x00009af8, 0x000000f9, 0x000000f9 },
+    { 0x00009afc, 0x000000f9, 0x000000f9 },
+};
+
+static const uint32_t ar5416Bank1[][2] = {
+    { 0x000098b0, 0x02108421 },
+    { 0x000098ec, 0x00000008 },
+};
+
+static const uint32_t ar5416Bank2[][2] = {
+    { 0x000098b0, 0x0e73ff17 },
+    { 0x000098e0, 0x00000420 },
+};
+
+static const uint32_t ar5416Bank3[][3] = {
+    { 0x000098f0, 0x01400018, 0x01c00018 },
+};
+
+#ifdef USE_NONTPC_BANK
+static const uint32_t ar5416Bank6[][3] = {
+/*    Reg      A            G            */
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00e00000, 0x00e00000 },
+    { 0x0000989c, 0x005e0000, 0x005e0000 },
+    { 0x0000989c, 0x00120000, 0x00120000 },
+    { 0x0000989c, 0x00620000, 0x00620000 },
+    { 0x0000989c, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x40ff0000, 0x40ff0000 },
+    { 0x0000989c, 0x005f0000, 0x005f0000 },
+    { 0x0000989c, 0x00870000, 0x00870000 },
+    { 0x0000989c, 0x00f90000, 0x00f90000 },
+    { 0x0000989c, 0x007b0000, 0x007b0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00f50000, 0x00f50000 },
+    { 0x0000989c, 0x00dc0000, 0x00dc0000 },
+    { 0x0000989c, 0x00110000, 0x00110000 },
+    { 0x0000989c, 0x006100a8, 0x006100a8 },
+    { 0x0000989c, 0x004210a2, 0x004210a2 },
+    { 0x0000989c, 0x0014008f, 0x0014008f },
+    { 0x0000989c, 0x00c40003, 0x00c40003 },
+    { 0x0000989c, 0x003000f2, 0x003000f2 },
+    { 0x0000989c, 0x00440016, 0x00440016 },
+    { 0x0000989c, 0x00410040, 0x00410040 },
+    { 0x0000989c, 0x0001805e, 0x0001805e },
+    { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
+    { 0x0000989c, 0x000000f1, 0x000000f1 },
+    { 0x0000989c, 0x00002081, 0x00002081 },
+    { 0x0000989c, 0x000000d4, 0x000000d4 },
+    { 0x000098d0, 0x0000000f, 0x0010000f },
+};
+
+#else
+/* TPC bank */
+static const uint32_t ar5416Bank6[][3] = {
+/*    Reg      A            G            */
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00e00000, 0x00e00000 },
+    { 0x0000989c, 0x005e0000, 0x005e0000 },
+    { 0x0000989c, 0x00120000, 0x00120000 },
+    { 0x0000989c, 0x00620000, 0x00620000 },
+    { 0x0000989c, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x40ff0000, 0x40ff0000 },
+    { 0x0000989c, 0x005f0000, 0x005f0000 },
+    { 0x0000989c, 0x00870000, 0x00870000 },
+    { 0x0000989c, 0x00f90000, 0x00f90000 },
+    { 0x0000989c, 0x007b0000, 0x007b0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00f50000, 0x00f50000 },
+    { 0x0000989c, 0x00dc0000, 0x00dc0000 },
+    { 0x0000989c, 0x00110000, 0x00110000 },
+    { 0x0000989c, 0x006100a8, 0x006100a8 },
+    { 0x0000989c, 0x00421022, 0x00421022 },
+    { 0x0000989c, 0x001400df, 0x001400df },
+    { 0x0000989c, 0x00c40002, 0x00c40002 },
+    { 0x0000989c, 0x003000f2, 0x003000f2 },
+    { 0x0000989c, 0x00440016, 0x00440016 },
+    { 0x0000989c, 0x00410040, 0x00410040 },
+    { 0x0000989c, 0x0001805e, 0x0001805e },
+    { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
+    { 0x0000989c, 0x000000e1, 0x000000e1 },
+    { 0x0000989c, 0x00002081, 0x00002081 },
+    { 0x0000989c, 0x000000d4, 0x000000d4 },
+    { 0x000098d0, 0x0000000f, 0x0010000f },
+};
+
+#endif
+
+static const uint32_t ar5416Bank7[][2] = {
+    { 0x0000989c, 0x00000500 },
+    { 0x0000989c, 0x00000800 },
+    { 0x000098cc, 0x0000000e },
+};
+
+static const uint32_t ar5416Addac[][2] = {
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000003 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x0000000c },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000030 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000060 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000058 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x0989c,  0x00000000 },
+    {0x098c4,  0x00000000 },
+};
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_ani.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_ani.c
new file mode 100644
index 0000000..59bfb20
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_ani.c
@@ -0,0 +1,886 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_ani.c,v 1.1 2008/11/11 20:46:06 sam Exp $
+ */
+#include "opt_ah.h"
+
+/*
+ * XXX this is virtually the same code as for 5212; we reuse
+ * storage in the 5212 state block; need to refactor.
+ */
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_desc.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/*
+ * Anti noise immunity support.  We track phy errors and react
+ * to excessive errors by adjusting the noise immunity parameters.
+ */
+
+#define HAL_EP_RND(x, mul) \
+	((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
+#define	BEACON_RSSI(ahp) \
+	HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
+		HAL_RSSI_EP_MULTIPLIER)
+
+/*
+ * ANI processing tunes radio parameters according to PHY errors
+ * and related information.  This is done for for noise and spur
+ * immunity in all operating modes if the device indicates it's
+ * capable at attach time.  In addition, when there is a reference
+ * rssi value (e.g. beacon frames from an ap in station mode)
+ * further tuning is done.
+ *
+ * ANI_ENA indicates whether any ANI processing should be done;
+ * this is specified at attach time.
+ *
+ * ANI_ENA_RSSI indicates whether rssi-based processing should
+ * done, this is enabled based on operating mode and is meaningful
+ * only if ANI_ENA is true.
+ *
+ * ANI parameters are typically controlled only by the hal.  The
+ * AniControl interface however permits manual tuning through the
+ * diagnostic api.
+ */
+#define ANI_ENA(ah) \
+	(AH5212(ah)->ah_procPhyErr & HAL_ANI_ENA)
+#define ANI_ENA_RSSI(ah) \
+	(AH5212(ah)->ah_procPhyErr & HAL_RSSI_ANI_ENA)
+
+#define	ah_mibStats	ah_stats.ast_mibstats
+
+static void
+enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "
+	    "OfdmPhyErrBase 0x%x cckPhyErrBase 0x%x\n",
+	    __func__, params->ofdmPhyErrBase, params->cckPhyErrBase);
+
+	OS_REG_WRITE(ah, AR_FILTOFDM, 0);
+	OS_REG_WRITE(ah, AR_FILTCCK, 0);
+
+	OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
+	OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
+	OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
+	OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
+
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);	/* save+clear counters*/
+	ar5212EnableMibCounters(ah);			/* enable everything */
+}
+
+static void 
+disableAniMIBCounters(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_ANI, "Disable MIB counters\n");
+
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);	/* save stats */
+	ar5212DisableMibCounters(ah);			/* disable everything */
+
+	OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, 0);
+	OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, 0);
+}
+
+/*
+ * This routine returns the index into the aniState array that
+ * corresponds to the channel in *chan.  If no match is found and the
+ * array is still not fully utilized, a new entry is created for the
+ * channel.  We assume the attach function has already initialized the
+ * ah_ani values and only the channel field needs to be set.
+ */
+static int
+ar5416GetAniChannelIndex(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+#define N(a)     (sizeof(a) / sizeof(a[0]))
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	int i;
+
+	for (i = 0; i < N(ahp->ah_ani); i++) {
+		struct ar5212AniState *asp = &ahp->ah_ani[i];
+		if (asp->c.channel == chan->channel)
+			return i;
+		if (asp->c.channel == 0) {
+			asp->c.channel = chan->channel;
+			asp->c.channelFlags = chan->channelFlags;
+			asp->c.privFlags = chan->privFlags;
+			asp->isSetup = AH_FALSE;
+			if (IS_CHAN_2GHZ(chan))
+				asp->params = &ahp->ah_aniParams24;
+			else
+				asp->params = &ahp->ah_aniParams5;
+			return i;
+		}
+	}
+	/* XXX statistic */
+	HALDEBUG(ah, HAL_DEBUG_ANY,
+	    "No more channel states left. Using channel 0\n");
+	return 0;		/* XXX gotta return something valid */
+#undef N
+}
+
+static void
+setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)
+{
+	if (params->ofdmTrigHigh >= AR_PHY_COUNTMAX) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "OFDM Trigger %d is too high for hw counters, using max\n",
+		    params->ofdmTrigHigh);
+		params->ofdmPhyErrBase = 0;
+	} else
+		params->ofdmPhyErrBase = AR_PHY_COUNTMAX - params->ofdmTrigHigh;
+	if (params->cckTrigHigh >= AR_PHY_COUNTMAX) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "CCK Trigger %d is too high for hw counters, using max\n",
+		    params->cckTrigHigh);
+		params->cckPhyErrBase = 0;
+	} else
+		params->cckPhyErrBase = AR_PHY_COUNTMAX - params->cckTrigHigh;
+}
+
+/*
+ * Setup ANI handling.  Sets all thresholds and reset the
+ * channel statistics.  Note that ar5416AniReset should be
+ * called by ar5416Reset before anything else happens and
+ * that's where we force initial settings.
+ */
+void
+ar5416AniAttach(struct ath_hal *ah, const struct ar5212AniParams *params24,
+	const struct ar5212AniParams *params5, HAL_BOOL enable)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	if (params24 != AH_NULL) {
+		OS_MEMCPY(&ahp->ah_aniParams24, params24, sizeof(*params24));
+		setPhyErrBase(ah, &ahp->ah_aniParams24);
+	}
+	if (params5 != AH_NULL) {
+		OS_MEMCPY(&ahp->ah_aniParams5, params5, sizeof(*params5));
+		setPhyErrBase(ah, &ahp->ah_aniParams5);
+	}
+
+	OS_MEMZERO(ahp->ah_ani, sizeof(ahp->ah_ani));
+	/* Enable MIB Counters */
+	enableAniMIBCounters(ah, &ahp->ah_aniParams24 /*XXX*/);
+
+	if (enable) {		/* Enable ani now */
+		HALASSERT(params24 != AH_NULL && params5 != AH_NULL);
+		ahp->ah_procPhyErr |= HAL_ANI_ENA;
+	} else {
+		ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
+	}
+}
+
+/*
+ * Cleanup any ANI state setup.
+ */
+void
+ar5416AniDetach(struct ath_hal *ah)
+{
+	HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");
+	disableAniMIBCounters(ah);
+}
+
+/*
+ * Control Adaptive Noise Immunity Parameters
+ */
+HAL_BOOL
+ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
+{
+	typedef int TABLE[];
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState = ahp->ah_curani;
+	const struct ar5212AniParams *params = aniState->params;
+
+	OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);
+
+	switch (cmd) {
+	case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
+		u_int level = param;
+
+		if (level >= params->maxNoiseImmunityLevel) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: level out of range (%u > %u)\n",
+			    __func__, level, params->maxNoiseImmunityLevel);
+			return AH_FALSE;
+		}
+
+		OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+		    AR_PHY_DESIRED_SZ_TOT_DES, params->totalSizeDesired[level]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
+		    AR_PHY_AGC_CTL1_COARSE_LOW, params->coarseLow[level]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
+		    AR_PHY_AGC_CTL1_COARSE_HIGH, params->coarseHigh[level]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+		    AR_PHY_FIND_SIG_FIRPWR, params->firpwr[level]);
+
+		if (level > aniState->noiseImmunityLevel)
+			ahp->ah_stats.ast_ani_niup++;
+		else if (level < aniState->noiseImmunityLevel)
+			ahp->ah_stats.ast_ani_nidown++;
+		aniState->noiseImmunityLevel = level;
+		break;
+	}
+	case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: {
+		static const TABLE m1ThreshLow   = { 127,   50 };
+		static const TABLE m2ThreshLow   = { 127,   40 };
+		static const TABLE m1Thresh      = { 127, 0x4d };
+		static const TABLE m2Thresh      = { 127, 0x40 };
+		static const TABLE m2CountThr    = {  31,   16 };
+		static const TABLE m2CountThrLow = {  63,   48 };
+		u_int on = param ? 1 : 0;
+
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+			AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+			AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
+
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+			AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+			AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+			AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
+		OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+			AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
+
+		if (on) {
+			OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
+				AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+		} else {
+			OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
+				AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+		}
+		if (on)
+			ahp->ah_stats.ast_ani_ofdmon++;
+		else
+			ahp->ah_stats.ast_ani_ofdmoff++;
+		aniState->ofdmWeakSigDetectOff = !on;
+		break;
+	}
+	case HAL_ANI_CCK_WEAK_SIGNAL_THR: {
+		static const TABLE weakSigThrCck = { 8, 6 };
+		u_int high = param ? 1 : 0;
+
+		OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
+		    AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]);
+		if (high)
+			ahp->ah_stats.ast_ani_cckhigh++;
+		else
+			ahp->ah_stats.ast_ani_ccklow++;
+		aniState->cckWeakSigThreshold = high;
+		break;
+	}
+	case HAL_ANI_FIRSTEP_LEVEL: {
+		u_int level = param;
+
+		if (level >= params->maxFirstepLevel) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: level out of range (%u > %u)\n",
+			    __func__, level, params->maxFirstepLevel);
+			return AH_FALSE;
+		}
+		OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+		    AR_PHY_FIND_SIG_FIRSTEP, params->firstep[level]);
+		if (level > aniState->firstepLevel)
+			ahp->ah_stats.ast_ani_stepup++;
+		else if (level < aniState->firstepLevel)
+			ahp->ah_stats.ast_ani_stepdown++;
+		aniState->firstepLevel = level;
+		break;
+	}
+	case HAL_ANI_SPUR_IMMUNITY_LEVEL: {
+		u_int level = param;
+
+		if (level >= params->maxSpurImmunityLevel) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: level out of range (%u > %u)\n",
+			    __func__, level, params->maxSpurImmunityLevel);
+			return AH_FALSE;
+		}
+		OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
+		    AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]);
+		if (level > aniState->spurImmunityLevel)
+			ahp->ah_stats.ast_ani_spurup++;
+		else if (level < aniState->spurImmunityLevel)
+			ahp->ah_stats.ast_ani_spurdown++;
+		aniState->spurImmunityLevel = level;
+		break;
+	}
+	case HAL_ANI_PRESENT:
+		break;
+	case HAL_ANI_MODE:
+		if (param == 0) {
+			ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
+			/* Turn off HW counters if we have them */
+			ar5416AniDetach(ah);
+			ar5212SetRxFilter(ah,
+				ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
+		} else {			/* normal/auto mode */
+			/* don't mess with state if already enabled */
+			if (ahp->ah_procPhyErr & HAL_ANI_ENA)
+				break;
+			ar5212SetRxFilter(ah,
+				ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
+			/* Enable MIB Counters */
+			enableAniMIBCounters(ah, ahp->ah_curani != AH_NULL ?
+			    ahp->ah_curani->params: &ahp->ah_aniParams24 /*XXX*/);
+			ahp->ah_procPhyErr |= HAL_ANI_ENA;
+		}
+		break;
+#ifdef AH_PRIVATE_DIAG
+	case HAL_ANI_PHYERR_RESET:
+		ahp->ah_stats.ast_ani_ofdmerrs = 0;
+		ahp->ah_stats.ast_ani_cckerrs = 0;
+		break;
+#endif /* AH_PRIVATE_DIAG */
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid cmd %u\n",
+		    __func__, cmd);
+		return AH_FALSE;
+	}
+	return AH_TRUE;
+}
+
+static void
+ar5416AniOfdmErrTrigger(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	struct ar5212AniState *aniState;
+	const struct ar5212AniParams *params;
+
+	HALASSERT(chan != AH_NULL);
+
+	if (!ANI_ENA(ah))
+		return;
+
+	aniState = ahp->ah_curani;
+	params = aniState->params;
+	/* First, raise noise immunity level, up to max */
+	if (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel) {
+		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 
+				 aniState->noiseImmunityLevel + 1);
+		return;
+	}
+	/* then, raise spur immunity level, up to max */
+	if (aniState->spurImmunityLevel+1 < params->maxSpurImmunityLevel) {
+		ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+				 aniState->spurImmunityLevel + 1);
+		return;
+	}
+
+	if (ANI_ENA_RSSI(ah)) {
+		int32_t rssi = BEACON_RSSI(ahp);
+		if (rssi > params->rssiThrHigh) {
+			/*
+			 * Beacon rssi is high, can turn off ofdm
+			 * weak sig detect.
+			 */
+			if (!aniState->ofdmWeakSigDetectOff) {
+				ar5416AniControl(ah,
+				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				    AH_FALSE);
+				ar5416AniControl(ah,
+				    HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
+				return;
+			}
+			/* 
+			 * If weak sig detect is already off, as last resort,
+			 * raise firstep level 
+			 */
+			if (aniState->firstepLevel+1 < params->maxFirstepLevel) {
+				ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+						 aniState->firstepLevel + 1);
+				return;
+			}
+		} else if (rssi > params->rssiThrLow) {
+			/* 
+			 * Beacon rssi in mid range, need ofdm weak signal
+			 * detect, but we can raise firststepLevel.
+			 */
+			if (aniState->ofdmWeakSigDetectOff)
+				ar5416AniControl(ah,
+				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				    AH_TRUE);
+			if (aniState->firstepLevel+1 < params->maxFirstepLevel)
+				ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+				     aniState->firstepLevel + 1);
+			return;
+		} else {
+			/* 
+			 * Beacon rssi is low, if in 11b/g mode, turn off ofdm
+			 * weak signal detection and zero firstepLevel to
+			 * maximize CCK sensitivity 
+			 */
+			/* XXX can optimize */
+			if (IS_CHAN_B(chan) || IS_CHAN_G(chan)) {
+				if (!aniState->ofdmWeakSigDetectOff)
+					ar5416AniControl(ah,
+					    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+					    AH_FALSE);
+				if (aniState->firstepLevel > 0)
+					ar5416AniControl(ah,
+					     HAL_ANI_FIRSTEP_LEVEL, 0);
+				return;
+			}
+		}
+	}
+}
+
+static void
+ar5416AniCckErrTrigger(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan;
+	struct ar5212AniState *aniState;
+	const struct ar5212AniParams *params;
+
+	HALASSERT(chan != AH_NULL);
+
+	if (!ANI_ENA(ah))
+		return;
+
+	/* first, raise noise immunity level, up to max */
+	aniState = ahp->ah_curani;
+	params = aniState->params;
+	if (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel) {
+		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+				 aniState->noiseImmunityLevel + 1);
+		return;
+	}
+
+	if (ANI_ENA_RSSI(ah)) {
+		int32_t rssi = BEACON_RSSI(ahp);
+		if (rssi >  params->rssiThrLow) {
+			/*
+			 * Beacon signal in mid and high range,
+			 * raise firstep level.
+			 */
+			if (aniState->firstepLevel+1 < params->maxFirstepLevel)
+				ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+						 aniState->firstepLevel + 1);
+		} else {
+			/*
+			 * Beacon rssi is low, zero firstep level to maximize
+			 * CCK sensitivity in 11b/g mode.
+			 */
+			/* XXX can optimize */
+			if (IS_CHAN_B(chan) || IS_CHAN_G(chan)) {
+				if (aniState->firstepLevel > 0)
+					ar5416AniControl(ah,
+					    HAL_ANI_FIRSTEP_LEVEL, 0);
+			}
+		}
+	}
+}
+
+static void
+ar5416AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const struct ar5212AniParams *params = aniState->params;
+
+	aniState->listenTime = 0;
+	/*
+	 * NB: these are written on reset based on the
+	 *     ini so we must re-write them!
+	 */
+	HALDEBUG(ah, HAL_DEBUG_ANI,
+	    "%s: Writing ofdmbase=%u   cckbase=%u\n", __func__,
+	    params->ofdmPhyErrBase, params->cckPhyErrBase);
+	OS_REG_WRITE(ah, AR_PHY_ERR_1, params->ofdmPhyErrBase);
+	OS_REG_WRITE(ah, AR_PHY_ERR_2, params->cckPhyErrBase);
+	OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
+	OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_CCK_TIMING);
+
+	/* Clear the mib counters and save them in the stats */
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
+	aniState->ofdmPhyErrCount = 0;
+	aniState->cckPhyErrCount = 0;
+}
+
+/*
+ * Restore/reset the ANI parameters and reset the statistics.
+ * This routine must be called for every channel change.
+ *
+ * NOTE: This is where ah_curani is set; other ani code assumes
+ *       it is setup to reflect the current channel.
+ */
+void
+ar5416AniReset(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
+	HAL_OPMODE opmode, int restore)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState;
+	uint32_t rxfilter;
+	int index;
+
+	index = ar5416GetAniChannelIndex(ah, chan);
+	aniState = &ahp->ah_ani[index];
+	ahp->ah_curani = aniState;
+#if 0
+	ath_hal_printf(ah,"%s: chan %u/0x%x restore %d setup %d opmode %u\n",
+	    __func__, chan->channel, chan->channelFlags, restore,
+	    aniState->isSetup, opmode);
+#else
+	HALDEBUG(ah, HAL_DEBUG_ANI,
+	    "%s: chan %u/0x%x restore %d setup %d opmode %u\n",
+	    __func__, chan->channel, chan->channelFlags, restore,
+	    aniState->isSetup, opmode);
+#endif
+	OS_MARK(ah, AH_MARK_ANI_RESET, opmode);
+
+	/*
+	 * Turn off PHY error frame delivery while we futz with settings.
+	 */
+	rxfilter = ar5212GetRxFilter(ah);
+	ar5212SetRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);
+	/*
+	 * Automatic processing is done only in station mode right now.
+	 */
+	if (opmode == HAL_M_STA)
+		ahp->ah_procPhyErr |= HAL_RSSI_ANI_ENA;
+	else
+		ahp->ah_procPhyErr &= ~HAL_RSSI_ANI_ENA;
+	/*
+	 * Set all ani parameters.  We either set them to initial
+	 * values or restore the previous ones for the channel.
+	 * XXX if ANI follows hardware, we don't care what mode we're
+	 * XXX in, we should keep the ani parameters
+	 */
+	if (restore && aniState->isSetup) {
+		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+				 aniState->noiseImmunityLevel);
+		ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+				 aniState->spurImmunityLevel);
+		ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				 !aniState->ofdmWeakSigDetectOff);
+		ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
+				 aniState->cckWeakSigThreshold);
+		ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+				 aniState->firstepLevel);
+	} else {
+		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
+		ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
+		ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+			AH_TRUE);
+		ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
+		ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
+		aniState->isSetup = AH_TRUE;
+	}
+	ar5416AniRestart(ah, aniState);
+
+	/* restore RX filter mask */
+	ar5212SetRxFilter(ah, rxfilter);
+}
+
+/*
+ * Process a MIB interrupt.  We may potentially be invoked because
+ * any of the MIB counters overflow/trigger so don't assume we're
+ * here because a PHY error counter triggered.
+ */
+void
+ar5416ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	uint32_t phyCnt1, phyCnt2;
+
+	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "
+	    "filtofdm 0x%x filtcck 0x%x\n",
+	    __func__, OS_REG_READ(ah, AR_MIBC),
+	    OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
+	    OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
+
+	/*
+	 * First order of business is to clear whatever caused
+	 * the interrupt so we don't keep getting interrupted.
+	 * We have the usual mib counters that are reset-on-read
+	 * and the additional counters that appeared starting in
+	 * Hainan.  We collect the mib counters and explicitly
+	 * zero additional counters we are not using.  Anything
+	 * else is reset only if it caused the interrupt.
+	 */
+	/* NB: these are not reset-on-read */
+	phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
+	phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
+	/* not used, always reset them in case they are the cause */
+	OS_REG_WRITE(ah, AR_FILTOFDM, 0);
+	OS_REG_WRITE(ah, AR_FILTCCK, 0);
+	if ((OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING) == 0)
+		OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
+
+	/* Clear the mib counters and save them in the stats */
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
+	ahp->ah_stats.ast_nodestats = *stats;
+
+	/*
+	 * Check for an ani stat hitting the trigger threshold.
+	 * When this happens we get a MIB interrupt and the top
+	 * 2 bits of the counter register will be 0b11, hence
+	 * the mask check of phyCnt?.
+	 */
+	if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 
+	    ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
+		struct ar5212AniState *aniState = ahp->ah_curani;
+		const struct ar5212AniParams *params = aniState->params;
+		uint32_t ofdmPhyErrCnt, cckPhyErrCnt;
+
+		ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
+		ahp->ah_stats.ast_ani_ofdmerrs +=
+			ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
+		aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
+
+		cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
+		ahp->ah_stats.ast_ani_cckerrs +=
+			cckPhyErrCnt - aniState->cckPhyErrCount;
+		aniState->cckPhyErrCount = cckPhyErrCnt;
+
+		/*
+		 * NB: figure out which counter triggered.  If both
+		 * trigger we'll only deal with one as the processing
+		 * clobbers the error counter so the trigger threshold
+		 * check will never be true.
+		 */
+		if (aniState->ofdmPhyErrCount > params->ofdmTrigHigh)
+			ar5416AniOfdmErrTrigger(ah);
+		if (aniState->cckPhyErrCount > params->cckTrigHigh)
+			ar5416AniCckErrTrigger(ah);
+		/* NB: always restart to insure the h/w counters are reset */
+		ar5416AniRestart(ah, aniState);
+	}
+}
+
+static void
+ar5416AniLowerImmunity(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState;
+	const struct ar5212AniParams *params;
+	
+	HALASSERT(ANI_ENA(ah));
+
+	aniState = ahp->ah_curani;
+	params = aniState->params;
+	if (ANI_ENA_RSSI(ah)) {
+		int32_t rssi = BEACON_RSSI(ahp);
+		if (rssi > params->rssiThrHigh) {
+			/* 
+			 * Beacon signal is high, leave ofdm weak signal
+			 * detection off or it may oscillate.  Let it fall
+			 * through.
+			 */
+		} else if (rssi > params->rssiThrLow) {
+			/*
+			 * Beacon rssi in mid range, turn on ofdm weak signal
+			 * detection or lower firstep level.
+			 */
+			if (aniState->ofdmWeakSigDetectOff) {
+				ar5416AniControl(ah,
+				    HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
+				    AH_TRUE);
+				return;
+			}
+			if (aniState->firstepLevel > 0) {
+				ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+						 aniState->firstepLevel - 1);
+				return;
+			}
+		} else {
+			/*
+			 * Beacon rssi is low, reduce firstep level.
+			 */
+			if (aniState->firstepLevel > 0) {
+				ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
+						 aniState->firstepLevel - 1);
+				return;
+			}
+		}
+	}
+	/* then lower spur immunity level, down to zero */
+	if (aniState->spurImmunityLevel > 0) {
+		ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
+				 aniState->spurImmunityLevel - 1);
+		return;
+	}
+	/* 
+	 * if all else fails, lower noise immunity level down to a min value
+	 * zero for now
+	 */
+	if (aniState->noiseImmunityLevel > 0) {
+		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
+				 aniState->noiseImmunityLevel - 1);
+		return;
+	}
+}
+
+#define CLOCK_RATE 44000	/* XXX use mac_usec or similar */
+/* convert HW counter values to ms using 11g clock rate, goo9d enough
+   for 11a and Turbo */
+
+/* 
+ * Return an approximation of the time spent ``listening'' by
+ * deducting the cycles spent tx'ing and rx'ing from the total
+ * cycle count since our last call.  A return value <0 indicates
+ * an invalid/inconsistent time.
+ */
+static int32_t
+ar5416AniGetListenTime(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState;
+	uint32_t txFrameCount, rxFrameCount, cycleCount;
+	int32_t listenTime;
+
+	txFrameCount = OS_REG_READ(ah, AR_TFCNT);
+	rxFrameCount = OS_REG_READ(ah, AR_RFCNT);
+	cycleCount = OS_REG_READ(ah, AR_CCCNT);
+
+	aniState = ahp->ah_curani;
+	if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
+		/*
+		 * Cycle counter wrap (or initial call); it's not possible
+		 * to accurately calculate a value because the registers
+		 * right shift rather than wrap--so punt and return 0.
+		 */
+		listenTime = 0;
+		ahp->ah_stats.ast_ani_lzero++;
+	} else {
+		int32_t ccdelta = cycleCount - aniState->cycleCount;
+		int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
+		int32_t tfdelta = txFrameCount - aniState->txFrameCount;
+		listenTime = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE;
+	}
+	aniState->cycleCount = cycleCount;
+	aniState->txFrameCount = txFrameCount;
+	aniState->rxFrameCount = rxFrameCount;
+	return listenTime;
+}
+
+/*
+ * Update ani stats in preparation for listen time processing.
+ */
+static void
+updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	const struct ar5212AniParams *params = aniState->params;
+	uint32_t phyCnt1, phyCnt2;
+	int32_t ofdmPhyErrCnt, cckPhyErrCnt;
+
+	/* Clear the mib counters and save them in the stats */
+	ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
+
+	/* NB: these are not reset-on-read */
+	phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
+	phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
+
+	/* NB: these are spec'd to never roll-over */
+	ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
+	if (ofdmPhyErrCnt < 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "OFDM phyErrCnt %d phyCnt1 0x%x\n",
+		    ofdmPhyErrCnt, phyCnt1);
+		ofdmPhyErrCnt = AR_PHY_COUNTMAX;
+	}
+	ahp->ah_stats.ast_ani_ofdmerrs +=
+	     ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
+	aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
+
+	cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
+	if (cckPhyErrCnt < 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANI, "CCK phyErrCnt %d phyCnt2 0x%x\n",
+		    cckPhyErrCnt, phyCnt2);
+		cckPhyErrCnt = AR_PHY_COUNTMAX;
+	}
+	ahp->ah_stats.ast_ani_cckerrs +=
+		cckPhyErrCnt - aniState->cckPhyErrCount;
+	aniState->cckPhyErrCount = cckPhyErrCnt;
+}
+
+/*
+ * Do periodic processing.  This routine is called from the
+ * driver's rx interrupt handler after processing frames.
+ */
+void
+ar5416AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
+		HAL_CHANNEL *chan)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	struct ar5212AniState *aniState = ahp->ah_curani;
+	const struct ar5212AniParams *params;
+	int32_t listenTime;
+
+	ahp->ah_stats.ast_nodestats.ns_avgbrssi = stats->ns_avgbrssi;
+
+	/* XXX can aniState be null? */
+	if (aniState == AH_NULL)
+		return;
+	if (!ANI_ENA(ah))
+		return;
+
+	listenTime = ar5416AniGetListenTime(ah);
+	if (listenTime < 0) {
+		ahp->ah_stats.ast_ani_lneg++;
+		/* restart ANI period if listenTime is invalid */
+		ar5416AniRestart(ah, aniState);
+	}
+	/* XXX beware of overflow? */
+	aniState->listenTime += listenTime;
+
+	OS_MARK(ah, AH_MARK_ANI_POLL, aniState->listenTime);
+
+	params = aniState->params;
+	if (aniState->listenTime > 5*params->period) {
+		/* 
+		 * Check to see if need to lower immunity if
+		 * 5 aniPeriods have passed
+		 */
+		updateMIBStats(ah, aniState);
+		if (aniState->ofdmPhyErrCount <= aniState->listenTime *
+		    params->ofdmTrigLow/1000 &&
+		    aniState->cckPhyErrCount <= aniState->listenTime *
+		    params->cckTrigLow/1000)
+			ar5416AniLowerImmunity(ah);
+		ar5416AniRestart(ah, aniState);
+	} else if (aniState->listenTime > params->period) {
+		updateMIBStats(ah, aniState);
+		/* check to see if need to raise immunity */
+		if (aniState->ofdmPhyErrCount > aniState->listenTime *
+		    params->ofdmTrigHigh / 1000) {
+			ar5416AniOfdmErrTrigger(ah);
+			ar5416AniRestart(ah, aniState);
+		} else if (aniState->cckPhyErrCount > aniState->listenTime *
+			   params->cckTrigHigh / 1000) {
+			ar5416AniCckErrTrigger(ah);
+			ar5416AniRestart(ah, aniState);
+		}
+	}
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_attach.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_attach.c
new file mode 100644
index 0000000..d5ffdae
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_attach.c
@@ -0,0 +1,486 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_attach.c,v 1.27 2008/11/27 22:30:07 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+#include "ar5416/ar5416.ini"
+
+static void
+ar5416AniSetup(struct ath_hal *ah)
+{
+	static const struct ar5212AniParams aniparams = {
+		.maxNoiseImmunityLevel	= 4,	/* levels 0..4 */
+		.totalSizeDesired	= { -55, -55, -55, -55, -62 },
+		.coarseHigh		= { -14, -14, -14, -14, -12 },
+		.coarseLow		= { -64, -64, -64, -64, -70 },
+		.firpwr			= { -78, -78, -78, -78, -80 },
+		.maxSpurImmunityLevel	= 2,
+		.cycPwrThr1		= { 2, 4, 6 },
+		.maxFirstepLevel	= 2,	/* levels 0..2 */
+		.firstep		= { 0, 4, 8 },
+		.ofdmTrigHigh		= 500,
+		.ofdmTrigLow		= 200,
+		.cckTrigHigh		= 200,
+		.cckTrigLow		= 100,
+		.rssiThrHigh		= 40,
+		.rssiThrLow		= 7,
+		.period			= 100,
+	};
+	/* NB: ANI is not enabled yet */
+	ar5212AniAttach(ah, &aniparams, &aniparams, AH_FALSE);
+}
+
+/*
+ * Attach for an AR5416 part.
+ */
+void
+ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+	struct ath_hal_5212 *ahp;
+	struct ath_hal *ah;
+
+	ahp = &ahp5416->ah_5212;
+	ar5212InitState(ahp, devid, sc, st, sh, status);
+	ah = &ahp->ah_priv.h;
+
+	/* override 5212 methods for our needs */
+	ah->ah_magic			= AR5416_MAGIC;
+	ah->ah_getRateTable		= ar5416GetRateTable;
+	ah->ah_detach			= ar5416Detach;
+
+	/* Reset functions */
+	ah->ah_reset			= ar5416Reset;
+	ah->ah_phyDisable		= ar5416PhyDisable;
+	ah->ah_disable			= ar5416Disable;
+	ah->ah_perCalibration		= ar5416PerCalibration;
+	ah->ah_perCalibrationN		= ar5416PerCalibrationN,
+	ah->ah_resetCalValid		= ar5416ResetCalValid,
+	ah->ah_setTxPowerLimit		= ar5416SetTxPowerLimit;
+
+	/* Transmit functions */
+	ah->ah_stopTxDma		= ar5416StopTxDma;
+	ah->ah_setupTxDesc		= ar5416SetupTxDesc;
+	ah->ah_setupXTxDesc		= ar5416SetupXTxDesc;
+	ah->ah_fillTxDesc		= ar5416FillTxDesc;
+	ah->ah_procTxDesc		= ar5416ProcTxDesc;
+
+	/* Receive Functions */
+	ah->ah_startPcuReceive		= ar5416StartPcuReceive;
+	ah->ah_stopPcuReceive		= ar5416StopPcuReceive;
+	ah->ah_setupRxDesc		= ar5416SetupRxDesc;
+	ah->ah_procRxDesc		= ar5416ProcRxDesc;
+	ah->ah_rxMonitor		= ar5416AniPoll,
+	ah->ah_procMibEvent		= ar5416ProcessMibIntr,
+
+	/* Misc Functions */
+	ah->ah_getDiagState		= ar5416GetDiagState;
+	ah->ah_setLedState		= ar5416SetLedState;
+	ah->ah_gpioCfgOutput		= ar5416GpioCfgOutput;
+	ah->ah_gpioCfgInput		= ar5416GpioCfgInput;
+	ah->ah_gpioGet			= ar5416GpioGet;
+	ah->ah_gpioSet			= ar5416GpioSet;
+	ah->ah_gpioSetIntr		= ar5416GpioSetIntr;
+	ah->ah_resetTsf			= ar5416ResetTsf;
+	ah->ah_getRfGain		= ar5416GetRfgain;
+	ah->ah_setAntennaSwitch		= ar5416SetAntennaSwitch;
+	ah->ah_setDecompMask		= ar5416SetDecompMask;
+	ah->ah_setCoverageClass		= ar5416SetCoverageClass;
+
+	ah->ah_resetKeyCacheEntry	= ar5416ResetKeyCacheEntry;
+	ah->ah_setKeyCacheEntry		= ar5416SetKeyCacheEntry;
+
+	/* Power Management Functions */
+	ah->ah_setPowerMode		= ar5416SetPowerMode;
+
+	/* Beacon Management Functions */
+	ah->ah_setBeaconTimers		= ar5416SetBeaconTimers;
+	ah->ah_beaconInit		= ar5416BeaconInit;
+	ah->ah_setStationBeaconTimers	= ar5416SetStaBeaconTimers;
+	ah->ah_resetStationBeaconTimers	= ar5416ResetStaBeaconTimers;
+
+	/* XXX 802.11n Functions */
+#if 0
+	ah->ah_chainTxDesc		= ar5416ChainTxDesc;
+	ah->ah_setupFirstTxDesc		= ar5416SetupFirstTxDesc;
+	ah->ah_setupLastTxDesc		= ar5416SetupLastTxDesc;
+	ah->ah_set11nRateScenario	= ar5416Set11nRateScenario;
+	ah->ah_set11nAggrMiddle		= ar5416Set11nAggrMiddle;
+	ah->ah_clr11nAggr		= ar5416Clr11nAggr;
+	ah->ah_set11nBurstDuration	= ar5416Set11nBurstDuration;
+	ah->ah_get11nExtBusy		= ar5416Get11nExtBusy;
+	ah->ah_set11nMac2040		= ar5416Set11nMac2040;
+	ah->ah_get11nRxClear		= ar5416Get11nRxClear;
+	ah->ah_set11nRxClear		= ar5416Set11nRxClear;
+#endif
+
+	/* Interrupt functions */
+	ah->ah_isInterruptPending	= ar5416IsInterruptPending;
+	ah->ah_getPendingInterrupts	= ar5416GetPendingInterrupts;
+	ah->ah_setInterrupts		= ar5416SetInterrupts;
+
+	ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes;
+	ahp->ah_priv.ah_eepromRead	= ar5416EepromRead;
+#ifdef AH_SUPPORT_WRITE_EEPROM
+	ahp->ah_priv.ah_eepromWrite	= ar5416EepromWrite;
+#endif
+	ahp->ah_priv.ah_gpioCfgOutput	= ar5416GpioCfgOutput;
+	ahp->ah_priv.ah_gpioCfgInput	= ar5416GpioCfgInput;
+	ahp->ah_priv.ah_gpioGet		= ar5416GpioGet;
+	ahp->ah_priv.ah_gpioSet		= ar5416GpioSet;
+	ahp->ah_priv.ah_gpioSetIntr	= ar5416GpioSetIntr;
+	ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
+
+	/*
+	 * Start by setting all Owl devices to 2x2
+	 */
+	AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
+	AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
+}
+
+/*
+ * Attach for an AR5416 part.
+ */
+struct ath_hal *
+ar5416Attach(uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+	struct ath_hal_5416 *ahp5416;
+	struct ath_hal_5212 *ahp;
+	struct ath_hal *ah;
+	uint32_t val;
+	HAL_STATUS ecode;
+	HAL_BOOL rfStatus;
+
+	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
+	    __func__, sc, (void*) st, (void*) sh);
+
+	/* NB: memory is returned zero'd */
+	ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) +
+		/* extra space for Owl 2.1/2.2 WAR */
+		sizeof(ar5416Addac)
+	);
+	if (ahp5416 == AH_NULL) {
+		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+		    "%s: cannot allocate memory for state block\n", __func__);
+		*status = HAL_ENOMEM;
+		return AH_NULL;
+	}
+	ar5416InitState(ahp5416, devid, sc, st, sh, status);
+	ahp = &ahp5416->ah_5212;
+	ah = &ahp->ah_priv.h;
+
+	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
+		/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+	/* Read Revisions from Chips before taking out of reset */
+	val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
+	AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
+	AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
+
+	/* setup common ini data; rf backends handle remainder */
+	HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
+	HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2);
+
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
+
+	if (!IS_5416V2_2(ah)) {		/* Owl 2.1/2.0 */
+		struct ini {
+			uint32_t	*data;		/* NB: !const */
+			int		rows, cols;
+		};
+		/* override CLKDRV value */
+		OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
+		AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
+		HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
+	}
+
+	if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
+		    __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
+
+	if (!ar5212ChipTest(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
+		    __func__);
+		ecode = HAL_ESELFTEST;
+		goto bad;
+	}
+
+	/*
+	 * Set correct Baseband to analog shift
+	 * setting to access analog chips.
+	 */
+	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+	/* Read Radio Chip Rev Extract */
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
+	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
+        case AR_RAD5122_SREV_MAJOR:	/* Fowl: 5G/2x2 */
+        case AR_RAD2122_SREV_MAJOR:	/* Fowl: 2+5G/2x2 */
+        case AR_RAD2133_SREV_MAJOR:	/* Fowl: 2G/3x3 */
+	case AR_RAD5133_SREV_MAJOR:	/* Fowl: 2+5G/3x3 */
+		break;
+	default:
+		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
+			/*
+			 * When RF_Silen is used the analog chip is reset.
+			 * So when the system boots with radio switch off
+			 * the RF chip rev reads back as zero and we need
+			 * to use the mac+phy revs to set the radio rev.
+			 */
+			AH_PRIVATE(ah)->ah_analog5GhzRev =
+				AR_RAD5133_SREV_MAJOR;
+			break;
+		}
+		/* NB: silently accept anything in release code per Atheros */
+#ifdef AH_DEBUG
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
+		    "this driver\n", __func__,
+		    AH_PRIVATE(ah)->ah_analog5GhzRev);
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+#endif
+	}
+
+	ecode = ath_hal_v14EepromAttach(ah);
+	if (ecode != HAL_OK)
+		goto bad;
+
+	/*
+	 * Got everything we need now to setup the capabilities.
+	 */
+	if (!ar5416FillCapabilityInfo(ah)) {
+		ecode = HAL_EEREAD;
+		goto bad;
+	}
+
+	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error getting mac address from EEPROM\n", __func__);
+		goto bad;
+        }
+	/* XXX How about the serial number ? */
+	/* Read Reg Domain */
+	AH_PRIVATE(ah)->ah_currentRD =
+	    ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
+
+	/*
+	 * ah_miscMode is populated by ar5416FillCapabilityInfo()
+	 * starting from griffin. Set here to make sure that
+	 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
+	 * placed into hardware.
+	 */
+	if (ahp->ah_miscMode != 0)
+		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: Attaching AR2133 radio\n",
+	    __func__);
+	rfStatus = ar2133RfAttach(ah, &ecode);
+	if (!rfStatus) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
+		    __func__, ecode);
+		goto bad;
+	}
+
+	ar5416AniSetup(ah);			/* Anti Noise Immunity */
+	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
+
+	return ah;
+bad:
+	if (ahp)
+		ar5416Detach((struct ath_hal *) ahp);
+	if (status)
+		*status = ecode;
+	return AH_NULL;
+}
+
+void
+ar5416Detach(struct ath_hal *ah)
+{
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
+
+	HALASSERT(ah != AH_NULL);
+	HALASSERT(ah->ah_magic == AR5416_MAGIC);
+
+	ar5416AniDetach(ah);
+	ar5212RfDetach(ah);
+	ah->ah_disable(ah);
+	ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
+	ath_hal_eepromDetach(ah);
+	ath_hal_free(ah);
+}
+
+/*
+ * Fill all software cached or static hardware state information.
+ * Return failure if capabilities are to come from EEPROM and
+ * cannot be read.
+ */
+HAL_BOOL
+ar5416FillCapabilityInfo(struct ath_hal *ah)
+{
+	struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
+	HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
+	uint16_t val;
+	
+	/* Construct wireless mode from EEPROM */
+	pCap->halWirelessModes = 0;
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
+		pCap->halWirelessModes |= HAL_MODE_11A
+				       |  HAL_MODE_11NA_HT20
+				       |  HAL_MODE_11NA_HT40PLUS
+				       |  HAL_MODE_11NA_HT40MINUS
+				       ;
+	}
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
+		pCap->halWirelessModes |= HAL_MODE_11G
+				       |  HAL_MODE_11NG_HT20
+				       |  HAL_MODE_11NG_HT40PLUS
+				       |  HAL_MODE_11NG_HT40MINUS
+				       ;
+		pCap->halWirelessModes |= HAL_MODE_11A
+				       |  HAL_MODE_11NA_HT20
+				       |  HAL_MODE_11NA_HT40PLUS
+				       |  HAL_MODE_11NA_HT40MINUS
+				       ;
+	}
+
+	pCap->halLow2GhzChan = 2312;
+	pCap->halHigh2GhzChan = 2732;
+
+	pCap->halLow5GhzChan = 4915;
+	pCap->halHigh5GhzChan = 6100;
+
+	pCap->halCipherCkipSupport = AH_FALSE;
+	pCap->halCipherTkipSupport = AH_TRUE;
+	pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
+
+	pCap->halMicCkipSupport    = AH_FALSE;
+	pCap->halMicTkipSupport    = AH_TRUE;
+	pCap->halMicAesCcmSupport  = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
+	/*
+	 * Starting with Griffin TX+RX mic keys can be combined
+	 * in one key cache slot.
+	 */
+	pCap->halTkipMicTxRxKeySupport = AH_TRUE;
+	pCap->halChanSpreadSupport = AH_TRUE;
+	pCap->halSleepAfterBeaconBroken = AH_TRUE;
+
+	pCap->halCompressSupport = AH_FALSE;
+	pCap->halBurstSupport = AH_TRUE;
+	pCap->halFastFramesSupport = AH_FALSE;	/* XXX? */
+	pCap->halChapTuningSupport = AH_TRUE;
+	pCap->halTurboPrimeSupport = AH_TRUE;
+
+	pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
+
+	pCap->halPSPollBroken = AH_TRUE;	/* XXX fixed in later revs? */
+	pCap->halVEOLSupport = AH_TRUE;
+	pCap->halBssIdMaskSupport = AH_TRUE;
+	pCap->halMcastKeySrchSupport = AH_FALSE;
+	pCap->halTsfAddSupport = AH_TRUE;
+
+	if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
+		pCap->halTotalQueues = val;
+	else
+		pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
+
+	if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
+		pCap->halKeyCacheSize = val;
+	else
+		pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE;
+
+	/* XXX not needed */
+	pCap->halChanHalfRate = AH_FALSE;	/* XXX ? */
+	pCap->halChanQuarterRate = AH_FALSE;	/* XXX ? */
+
+	pCap->halTstampPrecision = 32;
+	pCap->halHwPhyCounterSupport = AH_TRUE;
+
+	pCap->halFastCCSupport = AH_TRUE;
+	pCap->halNumGpioPins = 6;
+	pCap->halWowSupport = AH_FALSE;
+	pCap->halWowMatchPatternExact = AH_FALSE;
+	pCap->halBtCoexSupport = AH_FALSE;	/* XXX need support */
+	pCap->halAutoSleepSupport = AH_FALSE;
+#if 0	/* XXX not yet */
+	pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ);
+	pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ);
+#endif
+	pCap->halHTSupport = AH_TRUE;
+	pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
+	/* XXX CB71 uses GPIO 0 to indicate 3 rx chains */
+	pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
+	pCap->halRtsAggrLimit = 8*1024;		/* Owl 2.0 limit */
+	pCap->halMbssidAggrSupport = AH_TRUE;
+	pCap->halForcePpmSupport = AH_TRUE;
+	pCap->halEnhancedPmSupport = AH_TRUE;
+
+	if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
+	    ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
+		/* NB: enabled by default */
+		ahpriv->ah_rfkillEnabled = AH_TRUE;
+		pCap->halRfSilentSupport = AH_TRUE;
+	}
+
+	ahpriv->ah_rxornIsFatal = AH_FALSE;
+
+	return AH_TRUE;
+}
+
+static const char*
+ar5416Probe(uint16_t vendorid, uint16_t devid)
+{
+	if (vendorid == ATHEROS_VENDOR_ID &&
+	    (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE))
+		return "Atheros 5416";
+	return AH_NULL;
+}
+AH_CHIP(AR5416, ar5416Probe, ar5416Attach);
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_beacon.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_beacon.c
new file mode 100644
index 0000000..1d68c68
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_beacon.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_beacon.c,v 1.8 2008/11/11 01:03:12 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+#define TU_TO_USEC(_tu)		((_tu) << 10)
+
+/*
+ * Initialize all of the hardware registers used to
+ * send beacons.  Note that for station operation the
+ * driver calls ar5416SetStaBeaconTimers instead.
+ */
+void
+ar5416SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
+{
+	uint32_t bperiod;
+
+	OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bt->bt_nexttbtt));
+	OS_REG_WRITE(ah, AR_NEXT_DBA, TU_TO_USEC(bt->bt_nextdba) >> 3);
+	OS_REG_WRITE(ah, AR_NEXT_SWBA, TU_TO_USEC(bt->bt_nextswba) >> 3);
+	OS_REG_WRITE(ah, AR_NEXT_NDP, TU_TO_USEC(bt->bt_nextatim));
+
+	bperiod = TU_TO_USEC(bt->bt_intval & HAL_BEACON_PERIOD);
+	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, bperiod);
+	OS_REG_WRITE(ah, AR_DBA_PERIOD, bperiod);
+	OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod);
+	OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod);
+
+	/*
+	 * Reset TSF if required.
+	 */
+	if (bt->bt_intval & AR_BEACON_RESET_TSF)
+		ar5416ResetTsf(ah);
+
+	/* enable timers */
+	/* NB: flags == 0 handled specially for backwards compatibility */
+	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
+	    bt->bt_flags != 0 ? bt->bt_flags :
+		AR_TIMER_MODE_TBTT | AR_TIMER_MODE_DBA | AR_TIMER_MODE_SWBA);
+}
+
+/*
+ * Initializes all of the hardware registers used to
+ * send beacons.  Note that for station operation the
+ * driver calls ar5212SetStaBeaconTimers instead.
+ */
+void
+ar5416BeaconInit(struct ath_hal *ah,
+	uint32_t next_beacon, uint32_t beacon_period)
+{
+	HAL_BEACON_TIMERS bt;
+
+	bt.bt_nexttbtt = next_beacon;
+	/* 
+	 * TIMER1: in AP/adhoc mode this controls the DMA beacon
+	 * alert timer; otherwise it controls the next wakeup time.
+	 * TIMER2: in AP mode, it controls the SBA beacon alert
+	 * interrupt; otherwise it sets the start of the next CFP.
+	 */
+	bt.bt_flags = 0;
+	switch (AH_PRIVATE(ah)->ah_opmode) {
+	case HAL_M_STA:
+	case HAL_M_MONITOR:
+		bt.bt_nextdba = 0xffff;
+		bt.bt_nextswba = 0x7ffff;
+		bt.bt_flags |= AR_TIMER_MODE_TBTT;
+		break;
+	case HAL_M_IBSS:
+		OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ATIM_TXPOLICY);
+		bt.bt_flags |= AR_TIMER_MODE_NDP;
+		/* fall thru... */
+	case HAL_M_HOSTAP:
+		bt.bt_nextdba = (next_beacon -
+			ath_hal_dma_beacon_response_time) << 3;	/* 1/8 TU */
+		bt.bt_nextswba = (next_beacon -
+			ath_hal_sw_beacon_response_time) << 3;	/* 1/8 TU */
+		bt.bt_flags |= AR_TIMER_MODE_TBTT
+			    |  AR_TIMER_MODE_DBA
+			    |  AR_TIMER_MODE_SWBA;
+		break;
+	}
+	/*
+	 * Set the ATIM window 
+	 * Our hardware does not support an ATIM window of 0
+	 * (beacons will not work).  If the ATIM windows is 0,
+	 * force it to 1.
+	 */
+	bt.bt_nextatim = next_beacon + 1;
+	bt.bt_intval = beacon_period &
+		(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
+	ar5416SetBeaconTimers(ah, &bt);
+}
+
+#define AR_BEACON_PERIOD_MAX	0xffff
+
+void
+ar5416ResetStaBeaconTimers(struct ath_hal *ah)
+{
+	uint32_t val;
+
+	OS_REG_WRITE(ah, AR_NEXT_TBTT, 0);		/* no beacons */
+	val = OS_REG_READ(ah, AR_STA_ID1);
+	val |= AR_STA_ID1_PWR_SAV;		/* XXX */
+	/* tell the h/w that the associated AP is not PCF capable */
+	OS_REG_WRITE(ah, AR_STA_ID1,
+		val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
+	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, AR_BEACON_PERIOD_MAX);
+	OS_REG_WRITE(ah, AR_DBA_PERIOD, AR_BEACON_PERIOD_MAX);
+}
+
+/*
+ * Set all the beacon related bits on the h/w for stations
+ * i.e. initializes the corresponding h/w timers;
+ * also tells the h/w whether to anticipate PCF beacons
+ */
+void
+ar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
+{
+	uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
+
+	HALASSERT(bs->bs_intval != 0);
+	
+	/* NB: no cfp setting since h/w automatically takes care */
+
+	OS_REG_WRITE(ah, AR_NEXT_TBTT, bs->bs_nexttbtt);
+
+	/*
+	 * Start the beacon timers by setting the BEACON register
+	 * to the beacon interval; no need to write tim offset since
+	 * h/w parses IEs.
+	 */
+	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD,
+			 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
+	OS_REG_WRITE(ah, AR_DBA_PERIOD,
+			 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
+
+	/*
+	 * Configure the BMISS interrupt.  Note that we
+	 * assume the caller blocks interrupts while enabling
+	 * the threshold.
+	 */
+	HALASSERT(bs->bs_bmissthreshold <=
+		(AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S));
+	OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
+		AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
+
+	/*
+	 * Program the sleep registers to correlate with the beacon setup.
+	 */
+
+	/*
+	 * Oahu beacons timers on the station were used for power
+	 * save operation (waking up in anticipation of a beacon)
+	 * and any CFP function; Venice does sleep/power-save timers
+	 * differently - so this is the right place to set them up;
+	 * don't think the beacon timers are used by venice sta hw
+	 * for any useful purpose anymore
+	 * Setup venice's sleep related timers
+	 * Current implementation assumes sw processing of beacons -
+	 *   assuming an interrupt is generated every beacon which
+	 *   causes the hardware to become awake until the sw tells
+	 *   it to go to sleep again; beacon timeout is to allow for
+	 *   beacon jitter; cab timeout is max time to wait for cab
+	 *   after seeing the last DTIM or MORE CAB bit
+	 */
+#define CAB_TIMEOUT_VAL     10 /* in TU */
+#define BEACON_TIMEOUT_VAL  10 /* in TU */
+#define SLEEP_SLOP          3  /* in TU */
+
+	/*
+	 * For max powersave mode we may want to sleep for longer than a
+	 * beacon period and not want to receive all beacons; modify the
+	 * timers accordingly; make sure to align the next TIM to the
+	 * next DTIM if we decide to wake for DTIMs only
+	 */
+	beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
+	HALASSERT(beaconintval != 0);
+	if (bs->bs_sleepduration > beaconintval) {
+		HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
+				bs->bs_sleepduration);
+		beaconintval = bs->bs_sleepduration;
+	}
+	dtimperiod = bs->bs_dtimperiod;
+	if (bs->bs_sleepduration > dtimperiod) {
+		HALASSERT(dtimperiod == 0 ||
+			roundup(bs->bs_sleepduration, dtimperiod) ==
+				bs->bs_sleepduration);
+		dtimperiod = bs->bs_sleepduration;
+	}
+	HALASSERT(beaconintval <= dtimperiod);
+	if (beaconintval == dtimperiod)
+		nextTbtt = bs->bs_nextdtim;
+	else
+		nextTbtt = bs->bs_nexttbtt;
+	nextdtim = bs->bs_nextdtim;
+
+	OS_REG_WRITE(ah, AR_NEXT_DTIM,
+		TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
+	OS_REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
+
+	/* cab timeout is now in 1/8 TU */
+	OS_REG_WRITE(ah, AR_SLEEP1,
+		SM((CAB_TIMEOUT_VAL << 3), AR5416_SLEEP1_CAB_TIMEOUT)
+		| AR_SLEEP1_ASSUME_DTIM);
+	/* beacon timeout is now in 1/8 TU */
+	OS_REG_WRITE(ah, AR_SLEEP2,
+		SM((BEACON_TIMEOUT_VAL << 3), AR5416_SLEEP2_BEACON_TIMEOUT));
+
+	OS_REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
+	OS_REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
+	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
+	     AR_TIMER_MODE_TBTT | AR_TIMER_MODE_TIM | AR_TIMER_MODE_DTIM);
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
+	    __func__, bs->bs_nextdtim);
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
+	    __func__, nextTbtt);
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
+	    __func__, beaconintval);
+	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
+	    __func__, dtimperiod);
+#undef CAB_TIMEOUT_VAL
+#undef BEACON_TIMEOUT_VAL
+#undef SLEEP_SLOP
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal.c
new file mode 100644
index 0000000..49db049
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal.c
@@ -0,0 +1,663 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_cal.c,v 1.7 2008/11/11 17:43:23 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ah_eeprom_v14.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/* Owl specific stuff */
+#define NUM_NOISEFLOOR_READINGS 6       /* 3 chains * (ctl + ext) */
+
+static void ar5416StartNFCal(struct ath_hal *ah);
+static void ar5416LoadNF(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *);
+static int16_t ar5416GetNf(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+
+/*
+ * Determine if calibration is supported by device and channel flags
+ */
+static OS_INLINE HAL_BOOL
+ar5416IsCalSupp(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_CAL_TYPE calType) 
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+
+	switch (calType & cal->suppCals) {
+	case IQ_MISMATCH_CAL:
+		/* Run IQ Mismatch for non-CCK only */
+		return !IS_CHAN_B(chan);
+	case ADC_GAIN_CAL:
+	case ADC_DC_CAL:
+		/* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
+		return !IS_CHAN_B(chan) &&
+		    !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan));
+	}
+	return AH_FALSE;
+}
+
+/*
+ * Setup HW to collect samples used for current cal
+ */
+static void
+ar5416SetupMeasurement(struct ath_hal *ah, HAL_CAL_LIST *currCal)
+{
+	/* Start calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
+	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
+	    AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
+	    currCal->calData->calCountMax);
+
+	/* Select calibration to run */
+	switch (currCal->calData->calType) {
+	case IQ_MISMATCH_CAL:
+		OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%s: start IQ Mismatch calibration\n", __func__);
+		break;
+	case ADC_GAIN_CAL:
+		OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%s: start ADC Gain calibration\n", __func__);
+		break;
+	case ADC_DC_CAL:
+		OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%s: start ADC DC calibration\n", __func__);
+		break;
+	case ADC_DC_INIT_CAL:
+		OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%s: start Init ADC DC calibration\n", __func__);
+		break;
+	}
+	/* Kick-off cal */
+	OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL);
+}
+
+/*
+ * Initialize shared data structures and prepare a cal to be run.
+ */
+static void
+ar5416ResetMeasurement(struct ath_hal *ah, HAL_CAL_LIST *currCal)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+
+	/* Reset data structures shared between different calibrations */
+	OS_MEMZERO(cal->caldata, sizeof(cal->caldata));
+	cal->calSamples = 0;
+
+	/* Setup HW for new calibration */
+	ar5416SetupMeasurement(ah, currCal);
+
+	/* Change SW state to RUNNING for this calibration */
+	currCal->calState = CAL_RUNNING;
+}
+
+#if 0
+/*
+ * Run non-periodic calibrations.
+ */
+static HAL_BOOL
+ar5416RunInitCals(struct ath_hal *ah, int init_cal_count)
+{
+	struct ath_hal_5416 *ahp = AH5416(ah);
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	HAL_CHANNEL_INTERNAL ichan;	/* XXX bogus */
+	HAL_CAL_LIST *curCal = ahp->ah_cal_curr;
+	HAL_BOOL isCalDone;
+	int i;
+
+	if (curCal == AH_NULL)
+		return AH_FALSE;
+
+	ichan.calValid = 0;
+	for (i = 0; i < init_cal_count; i++) {
+		/* Reset this Cal */
+		ar5416ResetMeasurement(ah, curCal);
+		/* Poll for offset calibration complete */
+		if (!ath_hal_wait(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: Cal %d failed to finish in 100ms.\n",
+			    __func__, curCal->calData->calType);
+			/* Re-initialize list pointers for periodic cals */
+			cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;
+			return AH_FALSE;
+		}
+		/* Run this cal */
+		ar5416DoCalibration(ah, &ichan, ahp->ah_rxchainmask,
+		    curCal, &isCalDone);
+		if (!isCalDone)
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: init cal %d did not complete.\n",
+			    __func__, curCal->calData->calType);
+		if (curCal->calNext != AH_NULL)
+			curCal = curCal->calNext;
+	}
+
+	/* Re-initialize list pointers for periodic cals */
+	cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;
+	return AH_TRUE;
+}
+#endif
+
+/*
+ * Initialize Calibration infrastructure.
+ */
+HAL_BOOL
+ar5416InitCal(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	HAL_CHANNEL_INTERNAL *ichan;
+
+	ichan = ath_hal_checkchannel(ah, chan);
+	HALASSERT(ichan != AH_NULL);
+
+	if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
+		/* Enable Rx Filter Cal */
+		OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
+		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
+		    AR_PHY_AGC_CONTROL_FLTR_CAL);
+
+		/* Clear the carrier leak cal bit */
+		OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
+
+		/* kick off the cal */
+		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+
+		/* Poll for offset calibration complete */
+		if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: offset calibration failed to complete in 1ms; "
+			    "noisy environment?\n", __func__);
+			return AH_FALSE;
+		}
+
+		/* Set the cl cal bit and rerun the cal a 2nd time */
+		/* Enable Rx Filter Cal */
+		OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
+		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
+		    AR_PHY_AGC_CONTROL_FLTR_CAL);
+
+		OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
+	} 	
+
+	/* Calibrate the AGC */
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+
+	/* Poll for offset calibration complete */
+	if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: offset calibration did not complete in 1ms; "
+		    "noisy environment?\n", __func__);
+		return AH_FALSE;
+	}
+
+	/* 
+	 * Do NF calibration after DC offset and other CALs.
+	 * Per system engineers, noise floor value can sometimes be 20 dB
+	 * higher than normal value if DC offset and noise floor cal are
+	 * triggered at the same time.
+	 */
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+
+	/* Initialize list pointers */
+	cal->cal_list = cal->cal_last = cal->cal_curr = AH_NULL;
+
+	/*
+	 * Enable IQ, ADC Gain, ADC DC Offset Cals
+	 */
+	if (AR_SREV_SOWL_10_OR_LATER(ah)) {
+		/* Setup all non-periodic, init time only calibrations */
+		/* XXX: Init DC Offset not working yet */
+#if 0
+		if (ar5416IsCalSupp(ah, chan, ADC_DC_INIT_CAL)) {
+			INIT_CAL(&cal->adcDcCalInitData);
+			INSERT_CAL(cal, &cal->adcDcCalInitData);
+		}
+		/* Initialize current pointer to first element in list */
+		cal->cal_curr = cal->cal_list;
+
+		if (cal->ah_cal_curr != AH_NULL && !ar5416RunInitCals(ah, 0))
+			return AH_FALSE;
+#endif
+	}
+
+	/* If Cals are supported, add them to list via INIT/INSERT_CAL */
+	if (ar5416IsCalSupp(ah, chan, ADC_GAIN_CAL)) {
+		INIT_CAL(&cal->adcGainCalData);
+		INSERT_CAL(cal, &cal->adcGainCalData);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%s: enable ADC Gain Calibration.\n", __func__);
+	}
+	if (ar5416IsCalSupp(ah, chan, ADC_DC_CAL)) {
+		INIT_CAL(&cal->adcDcCalData);
+		INSERT_CAL(cal, &cal->adcDcCalData);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%s: enable ADC DC Calibration.\n", __func__);
+	}
+	if (ar5416IsCalSupp(ah, chan, IQ_MISMATCH_CAL)) {
+		INIT_CAL(&cal->iqCalData);
+		INSERT_CAL(cal, &cal->iqCalData);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%s: enable IQ Calibration.\n", __func__);
+	}
+	/* Initialize current pointer to first element in list */
+	cal->cal_curr = cal->cal_list;
+
+	/* Kick off measurements for the first cal */
+	if (cal->cal_curr != AH_NULL)
+		ar5416ResetMeasurement(ah, cal->cal_curr);
+
+	/* Mark all calibrations on this channel as being invalid */
+	ichan->calValid = 0;
+
+	return AH_TRUE;
+}
+
+/*
+ * Entry point for upper layers to restart current cal.
+ * Reset the calibration valid bit in channel.
+ */
+HAL_BOOL
+ar5416ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
+	HAL_CAL_LIST *currCal = cal->cal_curr;
+
+	if (!AR_SREV_SOWL_10_OR_LATER(ah))
+		return AH_FALSE;
+	if (currCal == AH_NULL)
+		return AH_FALSE;
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		return AH_FALSE;
+	}
+	/*
+	 * Expected that this calibration has run before, post-reset.
+	 * Current state should be done
+	 */
+	if (currCal->calState != CAL_DONE) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: Calibration state incorrect, %d\n",
+		    __func__, currCal->calState);
+		return AH_FALSE;
+	}
+
+	/* Verify Cal is supported on this channel */
+	if (!ar5416IsCalSupp(ah, chan, currCal->calData->calType))
+		return AH_FALSE;
+
+	HALDEBUG(ah, HAL_DEBUG_PERCAL,
+	    "%s: Resetting Cal %d state for channel %u/0x%x\n",
+	    __func__, currCal->calData->calType, chan->channel,
+	    chan->channelFlags);
+
+	/* Disable cal validity in channel */
+	ichan->calValid &= ~currCal->calData->calType;
+	currCal->calState = CAL_WAITING;
+
+	return AH_TRUE;
+}
+
+/*
+ * Recalibrate the lower PHY chips to account for temperature/environment
+ * changes.
+ */
+static void
+ar5416DoCalibration(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *ichan,
+	uint8_t rxchainmask, HAL_CAL_LIST *currCal, HAL_BOOL *isCalDone)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+
+	/* Cal is assumed not done until explicitly set below */
+	*isCalDone = AH_FALSE;
+
+	HALDEBUG(ah, HAL_DEBUG_PERCAL,
+	    "%s: %s Calibration, state %d, calValid 0x%x\n",
+	    __func__, currCal->calData->calName, currCal->calState,
+	    ichan->calValid);
+
+	/* Calibration in progress. */
+	if (currCal->calState == CAL_RUNNING) {
+		/* Check to see if it has finished. */
+		if (!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_CAL)) {
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "%s: sample %d of %d finished\n",
+			    __func__, cal->calSamples,
+			    currCal->calData->calNumSamples);
+			/* 
+			 * Collect measurements for active chains.
+			 */
+			currCal->calData->calCollect(ah);
+			if (++cal->calSamples >= currCal->calData->calNumSamples) {
+				int i, numChains = 0;
+				for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+					if (rxchainmask & (1 << i))
+						numChains++;
+				}
+				/* 
+				 * Process accumulated data
+				 */
+				currCal->calData->calPostProc(ah, numChains);
+
+				/* Calibration has finished. */
+				ichan->calValid |= currCal->calData->calType;
+				currCal->calState = CAL_DONE;
+				*isCalDone = AH_TRUE;
+			} else {
+				/*
+				 * Set-up to collect of another sub-sample.
+				 */
+				ar5416SetupMeasurement(ah, currCal);
+			}
+		}
+	} else if (!(ichan->calValid & currCal->calData->calType)) {
+		/* If current cal is marked invalid in channel, kick it off */
+		ar5416ResetMeasurement(ah, currCal);
+	}
+}
+
+/*
+ * Internal interface to schedule periodic calibration work.
+ */
+HAL_BOOL
+ar5416PerCalibrationN(struct ath_hal *ah,  HAL_CHANNEL *chan,
+	u_int rxchainmask, HAL_BOOL longcal, HAL_BOOL *isCalDone)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	HAL_CAL_LIST *currCal = cal->cal_curr;
+	HAL_CHANNEL_INTERNAL *ichan;
+
+	OS_MARK(ah, AH_MARK_PERCAL, chan->channel);
+
+	*isCalDone = AH_TRUE;
+
+	/* Invalid channel check */
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		return AH_FALSE;
+	}
+
+	/*
+	 * For given calibration:
+	 * 1. Call generic cal routine
+	 * 2. When this cal is done (isCalDone) if we have more cals waiting
+	 *    (eg after reset), mask this to upper layers by not propagating
+	 *    isCalDone if it is set to TRUE.
+	 *    Instead, change isCalDone to FALSE and setup the waiting cal(s)
+	 *    to be run.
+	 */
+	if (currCal != AH_NULL &&
+	    (currCal->calState == CAL_RUNNING ||
+	     currCal->calState == CAL_WAITING)) {
+		ar5416DoCalibration(ah, ichan, rxchainmask, currCal, isCalDone);
+		if (*isCalDone == AH_TRUE) {
+			cal->cal_curr = currCal = currCal->calNext;
+			if (currCal->calState == CAL_WAITING) {
+				*isCalDone = AH_FALSE;
+				ar5416ResetMeasurement(ah, currCal);
+			}
+		}
+	}
+
+	/* Do NF cal only at longer intervals */
+	if (longcal) {
+		/*
+		 * Get the value from the previous NF cal
+		 * and update the history buffer.
+		 */
+		ar5416GetNf(ah, ichan);
+
+		/* 
+		 * Load the NF from history buffer of the current channel.
+		 * NF is slow time-variant, so it is OK to use a
+		 * historical value.
+		 */
+		ar5416LoadNF(ah, AH_PRIVATE(ah)->ah_curchan);
+
+		/* start NF calibration, without updating BB NF register*/
+		ar5416StartNFCal(ah);
+
+		if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
+			/* report up and clear internal state */
+			chan->channelFlags |= CHANNEL_CW_INT;
+			ichan->channelFlags &= ~CHANNEL_CW_INT;
+		}
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Recalibrate the lower PHY chips to account for temperature/environment
+ * changes.
+ */
+HAL_BOOL
+ar5416PerCalibration(struct ath_hal *ah,  HAL_CHANNEL *chan, HAL_BOOL *isIQdone)
+{
+	struct ath_hal_5416 *ahp = AH5416(ah);
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	HAL_CAL_LIST *curCal = cal->cal_curr;
+
+	if (curCal != AH_NULL && curCal->calData->calType == IQ_MISMATCH_CAL) {
+		return ar5416PerCalibrationN(ah, chan, ahp->ah_rx_chainmask,
+		    AH_TRUE, isIQdone);
+	} else {
+		HAL_BOOL isCalDone;
+
+		*isIQdone = AH_FALSE;
+		return ar5416PerCalibrationN(ah, chan, ahp->ah_rx_chainmask,
+		    AH_TRUE, &isCalDone);
+	}
+}
+
+static HAL_BOOL
+ar5416GetEepromNoiseFloorThresh(struct ath_hal *ah,
+	const HAL_CHANNEL_INTERNAL *chan, int16_t *nft)
+{
+	switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) {
+	case CHANNEL_A:
+	case CHANNEL_A_HT20:
+	case CHANNEL_A_HT40PLUS:
+	case CHANNEL_A_HT40MINUS:
+		ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_5, nft);
+		break;
+	case CHANNEL_B:
+	case CHANNEL_G:
+	case CHANNEL_G_HT20:
+	case CHANNEL_G_HT40PLUS:
+	case CHANNEL_G_HT40MINUS:
+		ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_2, nft);
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		return AH_FALSE;
+	}
+	return AH_TRUE;
+}
+
+static void
+ar5416StartNFCal(struct ath_hal *ah)
+{
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+}
+
+static void
+ar5416LoadNF(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+	static const uint32_t ar5416_cca_regs[] = {
+		AR_PHY_CCA,
+		AR_PHY_CH1_CCA,
+		AR_PHY_CH2_CCA,
+		AR_PHY_EXT_CCA,
+		AR_PHY_CH1_EXT_CCA,
+		AR_PHY_CH2_EXT_CCA
+	};
+	struct ar5212NfCalHist *h;
+	int i, j;
+	int32_t val;
+	uint8_t chainmask;
+
+	/*
+	 * Force NF calibration for all chains.
+	 */
+	if (AR_SREV_KITE(ah)) {
+		/* Kite has only one chain */
+		chainmask = 0x9;
+	} else if (AR_SREV_MERLIN(ah)) {
+		/* Merlin has only two chains */
+		chainmask = 0x1B;
+	} else {
+		chainmask = 0x3F;
+	}
+
+	/*
+	 * Write filtered NF values into maxCCApwr register parameter
+	 * so we can load below.
+	 */
+	h = AH5416(ah)->ah_cal.nfCalHist;
+	for (i = 0; i < AR5416_NUM_NF_READINGS; i ++)
+		if (chainmask & (1 << i)) { 
+			val = OS_REG_READ(ah, ar5416_cca_regs[i]);
+			val &= 0xFFFFFE00;
+			val |= (((uint32_t)(h[i].privNF) << 1) & 0x1ff);
+			OS_REG_WRITE(ah, ar5416_cca_regs[i], val);
+		}
+
+	/* Load software filtered NF value into baseband internal minCCApwr variable. */
+	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+	OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+
+	/* Wait for load to complete, should be fast, a few 10s of us. */
+	for (j = 0; j < 1000; j++) {
+		if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0)
+			break;
+		OS_DELAY(10);
+	}
+
+	/*
+	 * Restore maxCCAPower register parameter again so that we're not capped
+	 * by the median we just loaded.  This will be initial (and max) value
+	 * of next noise floor calibration the baseband does.  
+	 */
+	for (i = 0; i < AR5416_NUM_NF_READINGS; i ++)
+		if (chainmask & (1 << i)) {	
+			val = OS_REG_READ(ah, ar5416_cca_regs[i]);
+			val &= 0xFFFFFE00;
+			val |= (((uint32_t)(-50) << 1) & 0x1ff);
+			OS_REG_WRITE(ah, ar5416_cca_regs[i], val);
+		}
+}
+
+void
+ar5416InitNfHistBuff(struct ar5212NfCalHist *h)
+{
+	int i, j;
+
+	for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
+		h[i].currIndex = 0;
+		h[i].privNF = AR5416_CCA_MAX_GOOD_VALUE;
+		h[i].invalidNFcount = AR512_NF_CAL_HIST_MAX;
+		for (j = 0; j < AR512_NF_CAL_HIST_MAX; j ++)
+			h[i].nfCalBuffer[j] = AR5416_CCA_MAX_GOOD_VALUE;
+	}
+}
+
+/*
+ * Update the noise floor buffer as a ring buffer
+ */
+static void
+ar5416UpdateNFHistBuff(struct ar5212NfCalHist *h, int16_t *nfarray)
+{
+	int i;
+
+	for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
+		h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
+
+		if (++h[i].currIndex >= AR512_NF_CAL_HIST_MAX)
+			h[i].currIndex = 0;
+		if (h[i].invalidNFcount > 0) {
+			if (nfarray[i] < AR5416_CCA_MIN_BAD_VALUE ||
+			    nfarray[i] > AR5416_CCA_MAX_HIGH_VALUE) {
+				h[i].invalidNFcount = AR512_NF_CAL_HIST_MAX;
+			} else {
+				h[i].invalidNFcount--;
+				h[i].privNF = nfarray[i];
+			}
+		} else {
+			h[i].privNF = ar5212GetNfHistMid(h[i].nfCalBuffer);
+		}
+	}
+}   
+
+/*
+ * Read the NF and check it against the noise floor threshhold
+ */
+static int16_t
+ar5416GetNf(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+	int16_t nf, nfThresh;
+
+	if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: NF didn't complete in calibration window\n", __func__);
+		nf = 0;
+	} else {
+		/* Finished NF cal, check against threshold */
+		int16_t nfarray[NUM_NOISEFLOOR_READINGS] = { 0 };
+			
+		/* TODO - enhance for multiple chains and ext ch */
+		ath_hal_getNoiseFloor(ah, nfarray);
+		nf = nfarray[0];
+		if (ar5416GetEepromNoiseFloorThresh(ah, chan, &nfThresh)) {
+			if (nf > nfThresh) {
+				HALDEBUG(ah, HAL_DEBUG_ANY,
+				    "%s: noise floor failed detected; "
+				    "detected %d, threshold %d\n", __func__,
+				    nf, nfThresh);
+				/*
+				 * NB: Don't discriminate 2.4 vs 5Ghz, if this
+				 *     happens it indicates a problem regardless
+				 *     of the band.
+				 */
+				chan->channelFlags |= CHANNEL_CW_INT;
+				nf = 0;
+			}
+		} else {
+			nf = 0;
+		}
+		ar5416UpdateNFHistBuff(AH5416(ah)->ah_cal.nfCalHist, nfarray);
+		chan->rawNoiseFloor = nf;
+	}
+	return nf;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal.h b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal.h
new file mode 100644
index 0000000..1240029
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_cal.h,v 1.3 2008/11/11 17:43:23 sam Exp $
+ */
+#ifndef _ATH_AR5416_CAL_H_
+#define _ATH_AR5416_CAL_H_
+ 
+typedef enum {
+	ADC_DC_INIT_CAL	= 0x1,
+	ADC_GAIN_CAL	= 0x2,
+	ADC_DC_CAL	= 0x4,
+	IQ_MISMATCH_CAL	= 0x8
+} HAL_CAL_TYPE;
+
+/* Calibrate state */
+typedef enum {
+	CAL_INACTIVE,
+	CAL_WAITING,
+	CAL_RUNNING,
+	CAL_DONE
+} HAL_CAL_STATE;
+
+typedef union {
+	uint32_t	u;
+	int32_t		s;
+} HAL_CAL_SAMPLE;
+
+#define	MIN_CAL_SAMPLES     1
+#define	MAX_CAL_SAMPLES    64
+#define	INIT_LOG_COUNT      5
+#define	PER_MIN_LOG_COUNT   2
+#define	PER_MAX_LOG_COUNT  10
+
+/* Per Calibration data structure */
+typedef struct per_cal_data {
+	const char	*calName;		/* for diagnostics */
+	HAL_CAL_TYPE	calType;		/* Type of calibration */
+	uint32_t	calNumSamples;		/* # SW samples to collect */
+	uint32_t	calCountMax;		/* # HW samples to collect */
+	void (*calCollect)(struct ath_hal *);	/* Accumulator function */
+						/* Post-processing function */
+	void (*calPostProc)(struct ath_hal *, uint8_t);
+} HAL_PERCAL_DATA;
+
+/* List structure for calibration data */
+typedef struct cal_list {
+	struct cal_list		*calNext;
+	HAL_CAL_STATE		calState;
+	const HAL_PERCAL_DATA	*calData;
+} HAL_CAL_LIST;
+
+struct ar5416PerCal {
+	/*
+	 * Periodic calibration state.
+	 */
+	HAL_CAL_TYPE	suppCals;
+	HAL_CAL_LIST	iqCalData;
+	HAL_CAL_LIST	adcGainCalData;
+	HAL_CAL_LIST	adcDcCalInitData;
+	HAL_CAL_LIST	adcDcCalData;
+	HAL_CAL_LIST	*cal_list;
+	HAL_CAL_LIST	*cal_last;
+	HAL_CAL_LIST	*cal_curr;
+#define AR5416_MAX_CHAINS            	3	/* XXX dup's eeprom def */
+	HAL_CAL_SAMPLE	caldata[4][AR5416_MAX_CHAINS];
+	int		calSamples;
+	/*
+	 * Noise floor cal histogram support.
+	 * XXX be nice to re-use space in ar5212
+	 */
+#define	AR5416_NUM_NF_READINGS		6	/* (3 chains * (ctl + ext) */
+	struct ar5212NfCalHist nfCalHist[AR5416_NUM_NF_READINGS];
+};
+
+#define INIT_CAL(_perCal) do {						\
+	(_perCal)->calState = CAL_WAITING;				\
+	(_perCal)->calNext = AH_NULL;					\
+} while (0)
+
+#define INSERT_CAL(_cal, _perCal) do {					\
+	if ((_cal)->cal_last == AH_NULL) {				\
+		(_cal)->cal_list = (_cal)->cal_last = (_perCal);	\
+		((_cal)->cal_last)->calNext = (_perCal);		\
+	} else {							\
+		((_cal)->cal_last)->calNext = (_perCal);		\
+		(_cal)->cal_last = (_perCal);				\
+		(_perCal)->calNext = (_cal)->cal_list;			\
+	}								\
+} while (0)
+
+HAL_BOOL ar5416InitCal(struct ath_hal *ah, HAL_CHANNEL *chan);
+HAL_BOOL ar5416PerCalibration(struct ath_hal *,  HAL_CHANNEL *,
+	    HAL_BOOL *isIQdone);
+HAL_BOOL ar5416PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
+	    u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
+HAL_BOOL ar5416ResetCalValid(struct ath_hal *ah,  HAL_CHANNEL *chan);
+
+void	ar5416IQCalCollect(struct ath_hal *ah);
+void	ar5416IQCalibration(struct ath_hal *ah, uint8_t numChains);
+void	ar5416AdcGainCalCollect(struct ath_hal *ah);
+void	ar5416AdcGainCalibration(struct ath_hal *ah, uint8_t numChains);
+void	ar5416AdcDcCalCollect(struct ath_hal *ah);
+void	ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains);
+void	ar5416InitNfHistBuff(struct ar5212NfCalHist *h);
+#endif /* _ATH_AR5416_CAL_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_adcdc.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_adcdc.c
new file mode 100644
index 0000000..2e580bd
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_adcdc.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_cal_adcdc.c,v 1.2 2008/11/11 17:43:23 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/* Adc DC Offset Cal aliases */
+#define	totalAdcDcOffsetIOddPhase(i)	caldata[0][i].s
+#define	totalAdcDcOffsetIEvenPhase(i)	caldata[1][i].s
+#define	totalAdcDcOffsetQOddPhase(i)	caldata[2][i].s
+#define	totalAdcDcOffsetQEvenPhase(i)	caldata[3][i].s
+
+void
+ar5416AdcDcCalCollect(struct ath_hal *ah)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	int i;
+
+	for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+		cal->totalAdcDcOffsetIOddPhase(i) += (int32_t)
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
+		cal->totalAdcDcOffsetIEvenPhase(i) += (int32_t)
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
+		cal->totalAdcDcOffsetQOddPhase(i) += (int32_t)
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
+		cal->totalAdcDcOffsetQEvenPhase(i) += (int32_t)
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
+
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
+		   cal->calSamples, i,
+		   cal->totalAdcDcOffsetIOddPhase(i),
+		   cal->totalAdcDcOffsetIEvenPhase(i),
+		   cal->totalAdcDcOffsetQOddPhase(i),
+		   cal->totalAdcDcOffsetQEvenPhase(i));
+	}
+}
+
+void
+ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	const HAL_PERCAL_DATA *calData = cal->cal_curr->calData;
+	uint32_t numSamples;
+	int i;
+
+	numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
+	for (i = 0; i < numChains; i++) {
+		uint32_t iOddMeasOffset = cal->totalAdcDcOffsetIOddPhase(i);
+		uint32_t iEvenMeasOffset = cal->totalAdcDcOffsetIEvenPhase(i);
+		int32_t qOddMeasOffset = cal->totalAdcDcOffsetQOddPhase(i);
+		int32_t qEvenMeasOffset = cal->totalAdcDcOffsetQEvenPhase(i);
+		int32_t qDcMismatch, iDcMismatch;
+		uint32_t val;
+
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "Starting ADC DC Offset Cal for Chain %d\n", i);
+
+		HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_i = %d\n",
+		    iOddMeasOffset);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_i = %d\n",
+		    iEvenMeasOffset);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_q = %d\n",
+		    qOddMeasOffset);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_q = %d\n",
+		    qEvenMeasOffset);
+
+		HALASSERT(numSamples);
+
+		iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
+		    numSamples) & 0x1ff;
+		qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
+		    numSamples) & 0x1ff;
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    " dc_offset_mismatch_i = 0x%08x\n", iDcMismatch);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    " dc_offset_mismatch_q = 0x%08x\n", qDcMismatch);
+
+		val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
+		val &= 0xc0000fff;
+		val |= (qDcMismatch << 12) | (iDcMismatch << 21);
+		OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 
+
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "ADC DC Offset Cal done for Chain %d\n", i);
+	}
+	OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
+	    AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_adcgain.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_adcgain.c
new file mode 100644
index 0000000..ce38b03
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_adcgain.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_cal_adcgain.c,v 1.2 2008/11/11 17:43:23 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/* Adc Gain Cal aliases */
+#define	totalAdcIOddPhase(i)	caldata[0][i].u
+#define	totalAdcIEvenPhase(i)	caldata[1][i].u
+#define	totalAdcQOddPhase(i)	caldata[2][i].u
+#define	totalAdcQEvenPhase(i)	caldata[3][i].u
+
+/*
+ * Collect data from HW to later perform ADC Gain Calibration
+ */
+void
+ar5416AdcGainCalCollect(struct ath_hal *ah)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	int i;
+
+	/*
+	* Accumulate ADC Gain cal measures for active chains
+	*/
+	for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+		cal->totalAdcIOddPhase(i) +=
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
+		cal->totalAdcIEvenPhase(i) +=
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
+		cal->totalAdcQOddPhase(i) +=
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
+		cal->totalAdcQEvenPhase(i) +=
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
+
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
+		    cal->calSamples, i, cal->totalAdcIOddPhase(i),
+		    cal->totalAdcIEvenPhase(i), cal->totalAdcQOddPhase(i),
+		    cal->totalAdcQEvenPhase(i));
+	}
+}
+
+/*
+ * Use HW data to do ADC Gain Calibration
+ */
+void
+ar5416AdcGainCalibration(struct ath_hal *ah, uint8_t numChains)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	uint32_t i;
+
+	for (i = 0; i < numChains; i++) {
+		uint32_t iOddMeasOffset  = cal->totalAdcIOddPhase(i);
+		uint32_t iEvenMeasOffset = cal->totalAdcIEvenPhase(i);
+		uint32_t qOddMeasOffset  = cal->totalAdcQOddPhase(i);
+		uint32_t qEvenMeasOffset = cal->totalAdcQEvenPhase(i);
+
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "Start ADC Gain Cal for Chain %d\n", i);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "  pwr_meas_odd_i = 0x%08x\n", iOddMeasOffset);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "  pwr_meas_even_i = 0x%08x\n", iEvenMeasOffset);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "  pwr_meas_odd_q = 0x%08x\n", qOddMeasOffset);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "  pwr_meas_even_q = 0x%08x\n", qEvenMeasOffset);
+
+		if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
+			uint32_t iGainMismatch =
+			    ((iEvenMeasOffset*32)/iOddMeasOffset) & 0x3f;
+			uint32_t qGainMismatch =
+			    ((qOddMeasOffset*32)/qEvenMeasOffset) & 0x3f;
+			uint32_t val;
+
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    " gain_mismatch_i = 0x%08x\n",
+			    iGainMismatch);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    " gain_mismatch_q = 0x%08x\n",
+			    qGainMismatch);
+
+			val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
+			val &= 0xfffff000;
+			val |= (qGainMismatch) | (iGainMismatch << 6);
+			OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 
+
+			HALDEBUG(ah,  HAL_DEBUG_PERCAL,
+			    "ADC Gain Cal done for Chain %d\n", i);
+		}
+	}
+	OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
+	    AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_iq.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_iq.c
new file mode 100644
index 0000000..931249e
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_cal_iq.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_cal_iq.c,v 1.2 2008/11/11 17:43:23 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/* IQ Cal aliases */
+#define	totalPowerMeasI(i)	caldata[0][i].u
+#define	totalPowerMeasQ(i)	caldata[1][i].u
+#define	totalIqCorrMeas(i)	caldata[2][i].s
+
+/*
+ * Collect data from HW to later perform IQ Mismatch Calibration
+ */
+void
+ar5416IQCalCollect(struct ath_hal *ah)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	int i;
+
+	/* 
+	 * Accumulate IQ cal measures for active chains
+	 */
+	for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+		cal->totalPowerMeasI(i) +=
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
+		cal->totalPowerMeasQ(i) +=
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
+		cal->totalIqCorrMeas(i) += (int32_t)
+		    OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
+		    cal->calSamples, i, cal->totalPowerMeasI(i),
+		    cal->totalPowerMeasQ(i), cal->totalIqCorrMeas(i));
+	}
+}
+
+/*
+ * Use HW data to do IQ Mismatch Calibration
+ */
+void
+ar5416IQCalibration(struct ath_hal *ah, uint8_t numChains)
+{
+	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
+	int i;
+
+	for (i = 0; i < numChains; i++) {
+		uint32_t powerMeasI = cal->totalPowerMeasI(i);
+		uint32_t powerMeasQ = cal->totalPowerMeasQ(i);
+		uint32_t iqCorrMeas = cal->totalIqCorrMeas(i);
+		uint32_t qCoffDenom, iCoffDenom;
+		int iqCorrNeg;
+
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "Start IQ Cal and Correction for Chain %d\n", i);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL,
+		    "Orignal: iq_corr_meas = 0x%08x\n", iqCorrMeas);
+
+		iqCorrNeg = 0;
+		/* iqCorrMeas is always negative. */ 
+		if (iqCorrMeas > 0x80000000)  {
+			iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
+			iqCorrNeg = 1;
+		}
+
+		HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_i = 0x%08x\n",
+		    powerMeasI);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_q = 0x%08x\n",
+		    powerMeasQ);
+		HALDEBUG(ah, HAL_DEBUG_PERCAL, " iqCorrNeg is 0x%08x\n",
+		    iqCorrNeg);
+
+		iCoffDenom = (powerMeasI/2 + powerMeasQ/2)/ 128;
+		qCoffDenom = powerMeasQ / 64;
+		/* Protect against divide-by-0 */
+		if (powerMeasQ != 0) {
+			/* IQ corr_meas is already negated if iqcorr_neg == 1 */
+			int32_t iCoff = iqCorrMeas/iCoffDenom;
+			int32_t qCoff = powerMeasI/qCoffDenom - 64;
+
+			HALDEBUG(ah, HAL_DEBUG_PERCAL, " iCoff = 0x%08x\n",
+			    iCoff);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL, " qCoff = 0x%08x\n",
+			    qCoff);
+	 
+			/* Negate iCoff if iqCorrNeg == 0 */
+			iCoff = iCoff & 0x3f;
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "New:  iCoff = 0x%08x\n", iCoff);
+
+			if (iqCorrNeg == 0x0)
+				iCoff = 0x40 - iCoff;
+			if (qCoff > 15)
+				qCoff = 15;
+			else if (qCoff <= -16)
+				qCoff = 16;
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    " : iCoff = 0x%x  qCoff = 0x%x\n", iCoff, qCoff);
+
+			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),
+			    AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff);
+			OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),
+			    AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff);
+			HALDEBUG(ah, HAL_DEBUG_PERCAL,
+			    "IQ Cal and Correction done for Chain %d\n", i);
+		}
+	}
+	OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
+	    AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_eeprom.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_eeprom.c
new file mode 100644
index 0000000..812159f
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_eeprom.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_eeprom.c,v 1.6 2008/11/10 04:08:04 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ah_eeprom_v14.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/*
+ * Read 16 bits of data from offset into *data
+ */
+HAL_BOOL
+ar5416EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
+{
+        OS_REG_READ(ah,  AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
+       	if (!ath_hal_wait(ah, AR_EEPROM_STATUS_DATA,
+	    AR_EEPROM_STATUS_DATA_BUSY | AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0))
+		return AH_FALSE;
+       	*data = MS(OS_REG_READ(ah, AR_EEPROM_STATUS_DATA),
+		   AR_EEPROM_STATUS_DATA_VAL);
+	return AH_TRUE;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_gpio.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_gpio.c
new file mode 100644
index 0000000..0aa2843
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_gpio.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_gpio.c,v 1.3 2008/11/10 04:08:04 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+#ifdef AH_DEBUG
+#include "ah_desc.h"			/* NB: for HAL_PHYERR* */
+#endif
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+#define	AR_NUM_GPIO	6		/* 6 GPIO pins */
+#define AR_GPIO_BIT(_gpio)	(1 << _gpio)
+
+/*
+ * Configure GPIO Output lines
+ */
+HAL_BOOL
+ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio)
+{
+	HALASSERT(gpio < AR_NUM_GPIO);
+	OS_REG_CLR_BIT(ah, AR_GPIO_INTR_OUT, AR_GPIO_BIT(gpio));
+	return AH_TRUE;
+}
+
+/*
+ * Configure GPIO Input lines
+ */
+HAL_BOOL
+ar5416GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
+{
+	HALASSERT(gpio < AR_NUM_GPIO);
+	OS_REG_SET_BIT(ah, AR_GPIO_INTR_OUT, AR_GPIO_BIT(gpio));
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - set output lines
+ */
+HAL_BOOL
+ar5416GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
+{
+	uint32_t reg;
+
+	HALASSERT(gpio < AR_NUM_GPIO);
+	reg = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_OUT_VAL);
+	if (val & 1)
+		reg |= AR_GPIO_BIT(gpio);
+	else 
+		reg &= ~AR_GPIO_BIT(gpio);
+		
+	OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_OUT_VAL, reg);	
+	return AH_TRUE;
+}
+
+/*
+ * Once configured for I/O - get input lines
+ */
+uint32_t
+ar5416GpioGet(struct ath_hal *ah, uint32_t gpio)
+{
+	if (gpio >= AR_NUM_GPIO)
+		return 0xffffffff;
+	return ((OS_REG_READ(ah, AR_GPIO_IN) & AR_GPIO_BIT(gpio)) >> gpio);
+}
+
+/*
+ * Set the GPIO Interrupt
+ */
+void
+ar5416GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
+{
+	uint32_t val;
+	
+	HALASSERT(gpio < AR_NUM_GPIO);
+	/* XXX bounds check gpio */
+	val = MS(OS_REG_READ(ah, AR_GPIO_INTR_OUT), AR_GPIO_INTR_CTRL);
+	if (ilevel)		/* 0 == interrupt on pin high */
+		val &= ~AR_GPIO_BIT(gpio);
+	else			/* 1 == interrupt on pin low */
+		val |= AR_GPIO_BIT(gpio);
+	OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_OUT, AR_GPIO_INTR_CTRL, val);
+
+	/* Change the interrupt mask. */
+	val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE), AR_INTR_GPIO);
+	val |= AR_GPIO_BIT(gpio);
+	OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_GPIO, val);
+
+	val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_MASK), AR_INTR_GPIO);
+	val |= AR_GPIO_BIT(gpio);
+	OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK, AR_INTR_GPIO, val);	
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_interrupts.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_interrupts.c
new file mode 100644
index 0000000..bef7522
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_interrupts.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_interrupts.c,v 1.6 2008/11/10 04:08:04 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+
+/*
+ * Checks to see if an interrupt is pending on our NIC
+ *
+ * Returns: TRUE    if an interrupt is pending
+ *          FALSE   if not
+ */
+HAL_BOOL
+ar5416IsInterruptPending(struct ath_hal *ah)
+{
+	uint32_t isr;
+	/* 
+	 * Some platforms trigger our ISR before applying power to
+	 * the card, so make sure the INTPEND is really 1, not 0xffffffff.
+	 */
+	isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+	if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0)
+		return AH_TRUE;
+
+	isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+	if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT))
+		return AH_TRUE;
+
+	return AH_FALSE;
+}
+
+/*
+ * Reads the Interrupt Status Register value from the NIC, thus deasserting
+ * the interrupt line, and returns both the masked and unmasked mapped ISR
+ * values.  The value returned is mapped to abstract the hw-specific bit
+ * locations in the Interrupt Status Register.
+ *
+ * Returns: A hardware-abstracted bitmap of all non-masked-out
+ *          interrupts pending, as well as an unmasked value
+ */
+HAL_BOOL
+ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
+{
+	uint32_t isr, isr0, isr1, sync_cause;
+
+	/*
+	 * Verify there's a mac interrupt and the RTC is on.
+	 */
+	if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+	    (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
+		isr = OS_REG_READ(ah, AR_ISR);
+	else
+		isr = 0;
+	sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+	sync_cause &= AR_INTR_SYNC_DEFAULT;
+	if (isr == 0 && sync_cause == 0) {
+		*masked = 0;
+		return AH_FALSE;
+	}
+
+	if (isr != 0) {
+		struct ath_hal_5212 *ahp = AH5212(ah);
+		uint32_t mask2;
+
+		mask2 = 0;
+		if (isr & AR_ISR_BCNMISC) {
+			uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
+			if (isr2 & AR_ISR_S2_TIM)
+				mask2 |= HAL_INT_TIM;
+			if (isr2 & AR_ISR_S2_DTIM)
+				mask2 |= HAL_INT_DTIM;
+			if (isr2 & AR_ISR_S2_DTIMSYNC)
+				mask2 |= HAL_INT_DTIMSYNC;
+			if (isr2 & (AR_ISR_S2_CABEND ))
+				mask2 |= HAL_INT_CABEND;
+			if (isr2 & AR_ISR_S2_GTT)
+				mask2 |= HAL_INT_GTT;
+			if (isr2 & AR_ISR_S2_CST)
+				mask2 |= HAL_INT_CST;	
+			if (isr2 & AR_ISR_S2_TSFOOR)
+				mask2 |= HAL_INT_TSFOOR;
+		}
+
+		isr = OS_REG_READ(ah, AR_ISR_RAC);
+		if (isr == 0xffffffff) {
+			*masked = 0;
+			return AH_FALSE;;
+		}
+
+		*masked = isr & HAL_INT_COMMON;
+		if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
+			*masked |= HAL_INT_RX;
+		if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
+			*masked |= HAL_INT_TX;
+			isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
+			ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK);
+			ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC);
+			isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
+			ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
+			ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
+		}
+
+		/* Interrupt Mitigation on AR5416 */
+#ifdef AR5416_INT_MITIGATION
+		if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
+			*masked |= HAL_INT_RX;
+		if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
+			*masked |= HAL_INT_TX;
+#endif
+		*masked |= mask2;
+	}
+	if (sync_cause != 0) {
+		if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) {
+			*masked |= HAL_INT_FATAL;
+		}
+		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
+			HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n",
+			    __func__);
+			OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
+			OS_REG_WRITE(ah, AR_RC, 0);
+			*masked |= HAL_INT_FATAL;
+		}
+		/*
+		 * On fatal errors collect ISR state for debugging.
+		 */
+		if (*masked & HAL_INT_FATAL) {
+			AH_PRIVATE(ah)->ah_fatalState[0] = isr;
+			AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause;
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n",
+			    __func__, isr, sync_cause);
+		}
+
+		OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
+		/* NB: flush write */
+		(void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
+	}
+	return AH_TRUE;
+}
+
+/*
+ * Atomically enables NIC interrupts.  Interrupts are passed in
+ * via the enumerated bitmask in ints.
+ */
+HAL_INT
+ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	uint32_t omask = ahp->ah_maskReg;
+	uint32_t mask,mask2;
+
+	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
+	    __func__, omask, ints);
+
+	if (omask & HAL_INT_GLOBAL) {
+		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
+		OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+		(void) OS_REG_READ(ah, AR_IER);
+
+		OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
+		(void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+
+		OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+		(void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE);
+	}
+
+	mask = ints & HAL_INT_COMMON;
+	mask2 = 0;
+
+	if (ints & HAL_INT_TX) {
+		if (ahp->ah_txOkInterruptMask)
+			mask |= AR_IMR_TXOK;
+		if (ahp->ah_txErrInterruptMask)
+			mask |= AR_IMR_TXERR;
+		if (ahp->ah_txDescInterruptMask)
+			mask |= AR_IMR_TXDESC;
+		if (ahp->ah_txEolInterruptMask)
+			mask |= AR_IMR_TXEOL;
+	}
+	if (ints & HAL_INT_RX)
+		mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
+#ifdef AR5416_INT_MITIGATION
+	/*
+	 * Overwrite default mask if Interrupt mitigation
+	 * is specified for AR5416
+	 */
+	mask = ints & HAL_INT_COMMON;
+	if (ints & HAL_INT_TX)
+		mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
+	if (ints & HAL_INT_RX)
+		mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM;
+#endif
+	if (ints & (HAL_INT_BMISC)) {
+		mask |= AR_IMR_BCNMISC;
+		if (ints & HAL_INT_TIM)
+			mask2 |= AR_IMR_S2_TIM;
+		if (ints & HAL_INT_DTIM)
+			mask2 |= AR_IMR_S2_DTIM;
+		if (ints & HAL_INT_DTIMSYNC)
+			mask2 |= AR_IMR_S2_DTIMSYNC;
+		if (ints & HAL_INT_CABEND)
+			mask2 |= (AR_IMR_S2_CABEND );
+		if (ints & HAL_INT_GTT)
+			mask2 |= AR_IMR_S2_GTT;			
+		if (ints & HAL_INT_CST)
+			mask2 |= AR_IMR_S2_CST;
+		if (ints & HAL_INT_TSFOOR)
+			mask2 |= AR_IMR_S2_TSFOOR;
+	}
+
+	/* Write the new IMR and store off our SW copy. */
+	HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
+	OS_REG_WRITE(ah, AR_IMR, mask);
+	mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
+					AR_IMR_S2_DTIM |
+					AR_IMR_S2_DTIMSYNC |
+					AR_IMR_S2_CABEND |
+					AR_IMR_S2_CABTO  |
+					AR_IMR_S2_TSFOOR |
+					AR_IMR_S2_GTT |
+					AR_IMR_S2_CST);
+	OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2);
+
+	ahp->ah_maskReg = ints;
+
+	/* Re-enable interrupts if they were enabled before. */
+	if (ints & HAL_INT_GLOBAL) {
+		HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
+		OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+
+		OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
+		OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+
+		OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
+		OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, AR_INTR_SYNC_DEFAULT);
+	}
+
+	return omask;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_keycache.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_keycache.c
new file mode 100644
index 0000000..cb8ad71
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_keycache.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_keycache.c,v 1.3 2008/11/10 04:08:04 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5416/ar5416.h"
+
+static const int keyType[] = {
+	1,	/* HAL_CIPHER_WEP */
+	0,	/* HAL_CIPHER_AES_OCB */
+	2,	/* HAL_CIPHER_AES_CCM */
+	0,	/* HAL_CIPHER_CKIP */
+	3,	/* HAL_CIPHER_TKIP */
+	0,	/* HAL_CIPHER_CLR */
+};
+
+/*
+ * Clear the specified key cache entry and any associated MIC entry.
+ */
+HAL_BOOL
+ar5416ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry)
+{
+	struct ath_hal_5416 *ahp = AH5416(ah);
+
+	if (ar5212ResetKeyCacheEntry(ah, entry)) {
+		ahp->ah_keytype[entry] = keyType[HAL_CIPHER_CLR];
+		return AH_TRUE;
+	} else
+		return AH_FALSE;
+}
+
+/*
+ * Sets the contents of the specified key cache entry
+ * and any associated MIC entry.
+ */
+HAL_BOOL
+ar5416SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
+                       const HAL_KEYVAL *k, const uint8_t *mac,
+                       int xorKey)
+{
+	struct ath_hal_5416 *ahp = AH5416(ah);
+
+	if (ar5212SetKeyCacheEntry(ah, entry, k, mac, xorKey)) {
+		ahp->ah_keytype[entry] = keyType[k->kv_type];
+		return AH_TRUE;
+	} else
+		return AH_FALSE;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_misc.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_misc.c
new file mode 100644
index 0000000..0ed704f
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_misc.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_misc.c,v 1.12 2008/11/27 22:30:07 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+#ifdef AH_DEBUG
+#include "ah_desc.h"                    /* NB: for HAL_PHYERR* */
+#endif
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+/*
+ * Return the wireless modes (a,b,g,t) supported by hardware.
+ *
+ * This value is what is actually supported by the hardware
+ * and is unaffected by regulatory/country code settings.
+ *
+ */
+u_int
+ar5416GetWirelessModes(struct ath_hal *ah)
+{
+	u_int mode;
+
+	mode = ar5212GetWirelessModes(ah);
+	if (mode & HAL_MODE_11A)
+		mode |= HAL_MODE_11NA_HT20
+		     |  HAL_MODE_11NA_HT40PLUS
+		     |  HAL_MODE_11NA_HT40MINUS
+		     ;
+	if (mode & HAL_MODE_11G)
+		mode |= HAL_MODE_11NG_HT20
+		     |  HAL_MODE_11NG_HT40PLUS
+		     |  HAL_MODE_11NG_HT40MINUS
+		     ;
+	return mode;
+}
+
+/*
+ * Change the LED blinking pattern to correspond to the connectivity
+ */
+void
+ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
+{
+	static const uint32_t ledbits[8] = {
+		AR_MAC_LED_ASSOC_NONE,		/* HAL_LED_INIT */
+		AR_MAC_LED_ASSOC_PEND,		/* HAL_LED_SCAN */
+		AR_MAC_LED_ASSOC_PEND,		/* HAL_LED_AUTH */
+		AR_MAC_LED_ASSOC_ACTIVE,	/* HAL_LED_ASSOC*/
+		AR_MAC_LED_ASSOC_ACTIVE,	/* HAL_LED_RUN */
+		AR_MAC_LED_ASSOC_NONE,
+		AR_MAC_LED_ASSOC_NONE,
+		AR_MAC_LED_ASSOC_NONE,
+	};
+	uint32_t bits;
+
+	bits = OS_REG_READ(ah, AR_MAC_LED);
+	bits = (bits &~ AR_MAC_LED_MODE)
+	     | SM(AR_MAC_LED_MODE_POWON, AR_MAC_LED_MODE)
+#if 1
+	     | SM(AR_MAC_LED_MODE_NETON, AR_MAC_LED_MODE)
+#endif
+	     ;
+	bits = (bits &~ AR_MAC_LED_ASSOC)
+	     | SM(ledbits[state & 0x7], AR_MAC_LED_ASSOC);
+	OS_REG_WRITE(ah, AR_MAC_LED, bits);
+}
+
+/*
+ * Reset the current hardware tsf for stamlme.
+ */
+void
+ar5416ResetTsf(struct ath_hal *ah)
+{
+	uint32_t v;
+	int i;
+
+	for (i = 0; i < 10; i++) {
+		v = OS_REG_READ(ah, AR_SLP32_MODE);
+		if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0)
+			break;
+		OS_DELAY(10);
+	}
+	OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);	
+}
+
+HAL_BOOL
+ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
+{
+	return AH_TRUE;
+}
+
+/* Setup decompression for given key index */
+HAL_BOOL
+ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
+{
+	return HAL_OK;
+}
+
+/* Setup coverage class */
+void
+ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
+{
+}
+
+/*
+ * Return approximation of extension channel busy over an time interval
+ * 0% (clear) -> 100% (busy)
+ *
+ */
+uint32_t
+ar5416Get11nExtBusy(struct ath_hal *ah)
+{
+    struct ath_hal_5416 *ahp = AH5416(ah);
+    uint32_t busy; /* percentage */
+    uint32_t cycleCount, ctlBusy, extBusy;
+
+    ctlBusy = OS_REG_READ(ah, AR_RCCNT);
+    extBusy = OS_REG_READ(ah, AR_EXTRCCNT);
+    cycleCount = OS_REG_READ(ah, AR_CCCNT);
+
+    if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) {
+        /*
+         * Cycle counter wrap (or initial call); it's not possible
+         * to accurately calculate a value because the registers
+         * right shift rather than wrap--so punt and return 0.
+         */
+        busy = 0;
+        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n",
+	    __func__);
+
+    } else {
+        uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount;
+        uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy;
+        uint32_t extBusyDelta = extBusy - ahp->ah_extBusy;
+        uint32_t ctlClearDelta = 0;
+
+        /* Compute control channel rxclear.
+         * The cycle delta may be less than the control channel delta.
+         * This could be solved by freezing the timers (or an atomic read,
+         * if one was available). Checking for the condition should be
+         * sufficient.
+         */
+        if (cycleDelta > ctlBusyDelta) {
+            ctlClearDelta = cycleDelta - ctlBusyDelta;
+        }
+
+        /* Compute ratio of extension channel busy to control channel clear
+         * as an approximation to extension channel cleanliness.
+         *
+         * According to the hardware folks, ext rxclear is undefined
+         * if the ctrl rxclear is de-asserted (i.e. busy)
+         */
+        if (ctlClearDelta) {
+            busy = (extBusyDelta * 100) / ctlClearDelta;
+        } else {
+            busy = 100;
+        }
+        if (busy > 100) {
+            busy = 100;
+        }
+#if 0
+        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, "
+             "extBusyDelta 0x%x, ctlClearDelta 0x%x, "
+             "busy %d\n",
+              __func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy);
+#endif
+    }
+
+    ahp->ah_cycleCount = cycleCount;
+    ahp->ah_ctlBusy = ctlBusy;
+    ahp->ah_extBusy = extBusy;
+
+    return busy;
+}
+
+/*
+ * Configure 20/40 operation
+ *
+ * 20/40 = joint rx clear (control and extension)
+ * 20    = rx clear (control)
+ *
+ * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing
+ *         from 20/40 => 20 only
+ */
+void
+ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
+{
+    uint32_t macmode;
+
+    /* Configure MAC for 20/40 operation */
+    if (mode == HAL_HT_MACMODE_2040) {
+        macmode = AR_2040_JOINED_RX_CLEAR;
+    } else {
+        macmode = 0;
+    }
+    OS_REG_WRITE(ah, AR_2040_MODE, macmode);
+}
+
+/*
+ * Get Rx clear (control/extension channel)
+ *
+ * Returns active low (busy) for ctrl/ext channel
+ * Owl 2.0
+ */
+HAL_HT_RXCLEAR
+ar5416Get11nRxClear(struct ath_hal *ah)
+{
+    HAL_HT_RXCLEAR rxclear = 0;
+    uint32_t val;
+
+    val = OS_REG_READ(ah, AR_DIAG_SW);
+
+    /* control channel */
+    if (val & AR_DIAG_RXCLEAR_CTL_LOW) {
+        rxclear |= HAL_RX_CLEAR_CTL_LOW;
+    }
+    /* extension channel */
+    if (val & AR_DIAG_RXCLEAR_CTL_LOW) {
+        rxclear |= HAL_RX_CLEAR_EXT_LOW;
+    }
+    return rxclear;
+}
+
+/*
+ * Set Rx clear (control/extension channel)
+ *
+ * Useful for forcing the channel to appear busy for
+ * debugging/diagnostics
+ * Owl 2.0
+ */
+void
+ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
+{
+    /* control channel */
+    if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
+        OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);
+    } else {
+        OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);
+    }
+    /* extension channel */
+    if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
+        OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);
+    } else {
+        OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);
+    }
+}
+
+HAL_STATUS
+ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+        uint32_t capability, uint32_t *result)
+{
+	switch (type) {
+	case HAL_CAP_BB_HANG:
+		switch (capability) {
+		case HAL_BB_HANG_RIFS:
+			return AR_SREV_SOWL(ah) ? HAL_OK : HAL_ENOTSUPP;
+		case HAL_BB_HANG_DFS:
+			return AR_SREV_SOWL(ah) ? HAL_OK : HAL_ENOTSUPP;
+		case HAL_BB_HANG_RX_CLEAR:
+			return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP;
+		}
+		break;
+	case HAL_CAP_MAC_HANG:
+		return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) ||
+		    (ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) ||
+		    AR_SREV_SOWL(ah)) ?
+			HAL_OK : HAL_ENOTSUPP;
+	default:
+		break;
+	}
+	return ar5212GetCapability(ah, type, capability, result);
+}
+
+static int ar5416DetectMacHang(struct ath_hal *ah);
+static int ar5416DetectBBHang(struct ath_hal *ah);
+
+HAL_BOOL
+ar5416GetDiagState(struct ath_hal *ah, int request,
+	const void *args, uint32_t argsize,
+	void **result, uint32_t *resultsize)
+{
+	struct ath_hal_5416 *ahp = AH5416(ah);
+	int hangs;
+
+	if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
+		return AH_TRUE;
+	switch (request) {
+	case HAL_DIAG_EEPROM:
+		return ath_hal_eepromDiag(ah, request,
+		    args, argsize, result, resultsize);
+	case HAL_DIAG_CHECK_HANGS:
+		if (argsize != sizeof(int))
+			return AH_FALSE;
+		hangs = *(const int *) args;
+		ahp->ah_hangs = 0;
+		if (hangs & HAL_BB_HANGS)
+			ahp->ah_hangs |= ar5416DetectBBHang(ah);
+		/* NB: if BB is hung MAC will be hung too so skip check */
+		if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS))
+			ahp->ah_hangs |= ar5416DetectMacHang(ah);
+		*result = &ahp->ah_hangs;
+		*resultsize = sizeof(ahp->ah_hangs);
+		return AH_TRUE;
+	}
+	return ar5212GetDiagState(ah, request,
+	    args, argsize, result, resultsize);
+}
+
+typedef struct {
+	uint32_t dma_dbg_3;
+	uint32_t dma_dbg_4;
+	uint32_t dma_dbg_5;
+	uint32_t dma_dbg_6;
+} mac_dbg_regs_t;
+
+typedef enum {
+	dcu_chain_state		= 0x1,
+	dcu_complete_state	= 0x2,
+	qcu_state		= 0x4,
+	qcu_fsp_ok		= 0x8,
+	qcu_fsp_state		= 0x10,
+	qcu_stitch_state	= 0x20,
+	qcu_fetch_state		= 0x40,
+	qcu_complete_state	= 0x80
+} hal_mac_hangs_t;
+
+typedef struct {
+	int states;
+	uint8_t dcu_chain_state;
+	uint8_t dcu_complete_state;
+	uint8_t qcu_state;
+	uint8_t qcu_fsp_ok;
+	uint8_t qcu_fsp_state;
+	uint8_t qcu_stitch_state;
+	uint8_t qcu_fetch_state;
+	uint8_t qcu_complete_state;
+} hal_mac_hang_check_t;
+
+static HAL_BOOL
+ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs,
+    const hal_mac_hang_check_t *check)
+{
+	int found_states;
+
+	found_states = 0;
+	if (check->states & dcu_chain_state) {
+		int i;
+
+		for (i = 0; i < 6; i++) {
+			if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) ==
+			    check->dcu_chain_state)
+				found_states |= dcu_chain_state;
+		}
+		for (i = 0; i < 4; i++) {
+			if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) ==
+			    check->dcu_chain_state)
+				found_states |= dcu_chain_state;
+		}
+	}
+	if (check->states & dcu_complete_state) { 
+		if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state)
+			found_states |= dcu_complete_state;
+	}
+	if (check->states & qcu_stitch_state) { 
+		if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state)
+			found_states |= qcu_stitch_state;
+	}
+	if (check->states & qcu_fetch_state) { 
+		if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state)
+			found_states |= qcu_fetch_state;
+	}
+	if (check->states & qcu_complete_state) { 
+		if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state)
+			found_states |= qcu_complete_state;
+	}
+	return (found_states == check->states);
+}
+
+#define NUM_STATUS_READS 50
+
+static int
+ar5416DetectMacHang(struct ath_hal *ah)
+{
+	static const hal_mac_hang_check_t hang_sig1 = {
+		.dcu_chain_state	= 0x6,
+		.dcu_complete_state	= 0x1,
+		.states			= dcu_chain_state
+					| dcu_complete_state,
+	};
+	static const hal_mac_hang_check_t hang_sig2 = {
+		.qcu_stitch_state	= 0x9,
+		.qcu_fetch_state	= 0x8,
+		.qcu_complete_state	= 0x4,
+		.states			= qcu_stitch_state
+					| qcu_fetch_state
+					| qcu_complete_state,
+        };
+	mac_dbg_regs_t mac_dbg;
+	int i;
+
+	mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3);
+	mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
+	mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
+	mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
+	for (i = 1; i <= NUM_STATUS_READS; i++) {
+		if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) ||
+		    mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) ||
+		    mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) ||
+		    mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6))
+			return 0;
+	}
+
+	if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1))
+		return HAL_MAC_HANG_SIG1;
+	if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2))
+		return HAL_MAC_HANG_SIG2;
+
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s Found an unknown MAC hang signature "
+	    "DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n",
+	    __func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
+	    mac_dbg.dma_dbg_6);
+
+	return HAL_MAC_HANG_UNKNOWN;
+}
+
+/*
+ * Determine if the baseband using the Observation Bus Register
+ */
+static int
+ar5416DetectBBHang(struct ath_hal *ah)
+{
+#define N(a) (sizeof(a)/sizeof(a[0]))
+	/*
+	 * Check the PCU Observation Bus 1 register (0x806c)
+	 * NUM_STATUS_READS times
+	 *
+	 * 4 known BB hang signatures -
+	 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
+	 * [2] bits 8,9 are 1, bit 11 is 0. State machine state
+	 *     (bits 25-31) is 0x52
+	 * [3] bits 8,9 are 1, bit 11 is 0. State machine state
+	 *     (bits 25-31) is 0x18
+	 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
+	 *     Rx State (bits 20-24) is 0x7.
+	 */
+	static const struct {
+		uint32_t val;
+		uint32_t mask;
+		int code;
+	} hang_list[] = {
+		/* Reg Value   Reg Mask    Hang Code XXX */
+		{ 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS },
+		{ 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS },
+		{ 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR },
+		{ 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR }
+	};
+	uint32_t hang_sig;
+	int i;
+
+	hang_sig = OS_REG_READ(ah, AR_OBSERV_1);
+	for (i = 1; i <= NUM_STATUS_READS; i++) {
+		if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1))
+			return 0;
+	}
+	for (i = 0; i < N(hang_list); i++)
+		if ((hang_sig & hang_list[i].mask) == hang_list[i].val) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s BB hang, signature 0x%x, code 0x%x\n",
+			    __func__, hang_sig, hang_list[i].code);
+			return hang_list[i].code;
+		}
+
+	HALDEBUG(ah, HAL_DEBUG_ANY, "%s Found an unknown BB hang signature! "
+	    "<0x806c>=0x%x\n", __func__, hang_sig);
+
+	return HAL_BB_HANG_UNKNOWN;
+#undef N
+}
+#undef NUM_STATUS_READS
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_phy.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_phy.c
new file mode 100644
index 0000000..f8f5b2a
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_phy.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_phy.c,v 1.4 2008/11/27 22:30:08 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5416/ar5416.h"
+
+/* shorthands to compact tables for readability */
+#define	OFDM	IEEE80211_T_OFDM
+#define	CCK	IEEE80211_T_CCK
+#define HT      IEEE80211_T_HT
+
+HAL_RATE_TABLE ar5416_11ng_table = {
+    28,  /* number of rates */
+    { 0 },
+    {
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   1 Mb */ {  AH_TRUE, CCK,     1000,    0x1b,    0x00, (0x80| 2),   0 },
+/*   2 Mb */ {  AH_TRUE, CCK,     2000,    0x1a,    0x04, (0x80| 4),   1 },
+/* 5.5 Mb */ {  AH_TRUE, CCK,     5500,    0x19,    0x04, (0x80|11),   2 },
+/*  11 Mb */ {  AH_TRUE, CCK,    11000,    0x18,    0x04, (0x80|22),   3 },
+/* Remove rates 6, 9 from rate ctrl */
+/*   6 Mb */ { AH_FALSE, OFDM,    6000,    0x0b,    0x00,        12,   4 },
+/*   9 Mb */ { AH_FALSE, OFDM,    9000,    0x0f,    0x00,        18,   4 },
+/*  12 Mb */ {  AH_TRUE, OFDM,   12000,    0x0a,    0x00,        24,   6 },
+/*  18 Mb */ {  AH_TRUE, OFDM,   18000,    0x0e,    0x00,        36,   6 },
+/*  24 Mb */ {  AH_TRUE, OFDM,   24000,    0x09,    0x00,        48,   8 },
+/*  36 Mb */ {  AH_TRUE, OFDM,   36000,    0x0d,    0x00,        72,   8 },
+/*  48 Mb */ {  AH_TRUE, OFDM,   48000,    0x08,    0x00,        96,   8 },
+/*  54 Mb */ {  AH_TRUE, OFDM,   54000,    0x0c,    0x00,       108,   8 },
+/* 6.5 Mb */ {  AH_TRUE, HT,      6500,    0x80,    0x00,      	  0,   8 },
+/*  13 Mb */ {  AH_TRUE, HT,  	 13000,    0x81,    0x00,      	  1,   8 },
+/*19.5 Mb */ {  AH_TRUE, HT,     19500,    0x82,    0x00,         2,   8 },
+/*  26 Mb */ {  AH_TRUE, HT,  	 26000,    0x83,    0x00,         3,   8 },
+/*  39 Mb */ {  AH_TRUE, HT,  	 39000,    0x84,    0x00,         4,   8 },
+/*  52 Mb */ {  AH_TRUE, HT,   	 52000,    0x85,    0x00,         5,   8 },
+/*58.5 Mb */ {  AH_TRUE, HT,  	 58500,    0x86,    0x00,         6,   8 },
+/*  65 Mb */ {  AH_TRUE, HT,  	 65000,    0x87,    0x00,         7,   8 },
+/*  13 Mb */ {  AH_TRUE, HT,  	 13000,    0x88,    0x00,         8,   8 },
+/*  26 Mb */ {  AH_TRUE, HT,  	 26000,    0x89,    0x00,         9,   8 },
+/*  39 Mb */ {  AH_TRUE, HT,  	 39000,    0x8a,    0x00,        10,   8 },
+/*  52 Mb */ {  AH_TRUE, HT,  	 52000,    0x8b,    0x00,        11,   8 },
+/*  78 Mb */ {  AH_TRUE, HT,  	 78000,    0x8c,    0x00,        12,   8 },
+/* 104 Mb */ {  AH_TRUE, HT, 	104000,    0x8d,    0x00,        13,   8 },
+/* 117 Mb */ {  AH_TRUE, HT, 	117000,    0x8e,    0x00,        14,   8 },
+/* 130 Mb */ {  AH_TRUE, HT, 	130000,    0x8f,    0x00,        15,   8 },
+	},
+};
+
+static HAL_RATE_TABLE ar5416_11na_table = {
+    24,  /* number of rates */
+    { 0 },
+    {
+/*                                                 short            ctrl  */
+/*                valid                rateCode Preamble  dot11Rate Rate */
+/*   6 Mb */ {  AH_TRUE, OFDM,    6000,    0x0b,    0x00, (0x80|12),   0 },
+/*   9 Mb */ {  AH_TRUE, OFDM,    9000,    0x0f,    0x00,        18,   0 },
+/*  12 Mb */ {  AH_TRUE, OFDM,   12000,    0x0a,    0x00, (0x80|24),   2 },
+/*  18 Mb */ {  AH_TRUE, OFDM,   18000,    0x0e,    0x00,        36,   2 },
+/*  24 Mb */ {  AH_TRUE, OFDM,   24000,    0x09,    0x00, (0x80|48),   4 },
+/*  36 Mb */ {  AH_TRUE, OFDM,   36000,    0x0d,    0x00,        72,   8 },
+/*  48 Mb */ {  AH_TRUE, OFDM,   48000,    0x08,    0x00,        96,   8 },
+/*  54 Mb */ {  AH_TRUE, OFDM,   54000,    0x0c,    0x00,       108,   8 },
+/* 6.5 Mb */ {  AH_TRUE, HT,      6500,    0x80,    0x00,         0,   8 },
+/*  13 Mb */ {  AH_TRUE, HT,  	 13000,    0x81,    0x00,         1,   8 },
+/*19.5 Mb */ {  AH_TRUE, HT,     19500,    0x82,    0x00,         2,   8 },
+/*  26 Mb */ {  AH_TRUE, HT,  	 26000,    0x83,    0x00,         3,   8 },
+/*  39 Mb */ {  AH_TRUE, HT,  	 39000,    0x84,    0x00,         4,   8 },
+/*  52 Mb */ {  AH_TRUE, HT,   	 52000,    0x85,    0x00,         5,   8 },
+/*58.5 Mb */ {  AH_TRUE, HT,  	 58500,    0x86,    0x00,         6,   8 },
+/*  65 Mb */ {  AH_TRUE, HT,  	 65000,    0x87,    0x00,         7,   8 },
+/*  13 Mb */ {  AH_TRUE, HT,  	 13000,    0x88,    0x00,         8,   8 },
+/*  26 Mb */ {  AH_TRUE, HT,  	 26000,    0x89,    0x00,         9,   8 },
+/*  39 Mb */ {  AH_TRUE, HT,  	 39000,    0x8a,    0x00,        10,   8 },
+/*  52 Mb */ {  AH_TRUE, HT,  	 52000,    0x8b,    0x00,        11,   8 },
+/*  78 Mb */ {  AH_TRUE, HT,  	 78000,    0x8c,    0x00,        12,   8 },
+/* 104 Mb */ {  AH_TRUE, HT, 	104000,    0x8d,    0x00,        13,   8 },
+/* 117 Mb */ {  AH_TRUE, HT, 	117000,    0x8e,    0x00,        14,   8 },
+/* 130 Mb */ {  AH_TRUE, HT, 	130000,    0x8f,    0x00,        15,   8 },
+	},
+};
+
+#undef	OFDM
+#undef	CCK
+#undef	HT
+
+const HAL_RATE_TABLE *
+ar5416GetRateTable(struct ath_hal *ah, u_int mode)
+{
+	HAL_RATE_TABLE *rt;
+	switch (mode) {
+	case HAL_MODE_11NG_HT20:
+	case HAL_MODE_11NG_HT40PLUS:
+	case HAL_MODE_11NG_HT40MINUS:
+		rt = &ar5416_11ng_table;
+		break;
+	case HAL_MODE_11NA_HT20:
+	case HAL_MODE_11NA_HT40PLUS:
+	case HAL_MODE_11NA_HT40MINUS:
+		rt = &ar5416_11na_table;
+		break;
+	default:
+		return ar5212GetRateTable(ah, mode);
+	}
+	ath_hal_setupratetable(ah, rt);
+	return rt;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_power.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_power.c
new file mode 100644
index 0000000..b83b0f8
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_power.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_power.c,v 1.6 2008/11/11 00:11:30 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+
+/*
+ * Notify Power Mgt is enabled in self-generated frames.
+ * If requested, force chip awake.
+ *
+ * Returns A_OK if chip is awake or successfully forced awake.
+ *
+ * WARNING WARNING WARNING
+ * There is a problem with the chip where sometimes it will not wake up.
+ */
+static HAL_BOOL
+ar5416SetPowerModeAwake(struct ath_hal *ah, int setChip)
+{
+#define	POWER_UP_TIME	200000
+	uint32_t val;
+	int i = 0;
+
+	if (setChip) {
+		/*
+		 * Do a Power-On-Reset if OWL is shutdown
+		 * the NetBSD driver  power-cycles the Cardbus slot
+		 * as part of the reset procedure.
+		 */
+		if ((OS_REG_READ(ah, AR_RTC_STATUS) 
+			& AR_RTC_PM_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
+			if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))
+				goto bad;			
+		}
+
+		OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
+		OS_DELAY(50);   /* Give chip the chance to awake */
+
+		for (i = POWER_UP_TIME / 50; i != 0; i--) {
+			val = OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
+			if (val == AR_RTC_STATUS_ON)
+				break;
+			OS_DELAY(50);
+			OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
+		}		
+	bad:
+		if (i == 0) {
+#ifdef AH_DEBUG
+			ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",
+				__func__, POWER_UP_TIME/1000);
+#endif
+			return AH_FALSE;
+		}
+	} 
+
+	OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	return AH_TRUE;
+#undef POWER_UP_TIME
+}
+
+/*
+ * Notify Power Mgt is disabled in self-generated frames.
+ * If requested, force chip to sleep.
+ */
+static void
+ar5416SetPowerModeSleep(struct ath_hal *ah, int setChip)
+{
+	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	if (setChip) {
+		/* Clear the RTC force wake bit to allow the mac to sleep */
+		OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
+		OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
+		/* Shutdown chip. Active low */
+		OS_REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
+	}
+}
+
+/*
+ * Notify Power Management is enabled in self-generating
+ * fames.  If request, set power mode of chip to
+ * auto/normal.  Duration in units of 128us (1/8 TU).
+ */
+static void
+ar5416SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)
+{
+	OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	
+	if (setChip)
+		OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
+}
+
+/*
+ * Set power mgt to the requested mode, and conditionally set
+ * the chip as well
+ */
+HAL_BOOL
+ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+#ifdef AH_DEBUG
+	static const char* modes[] = {
+		"AWAKE",
+		"FULL-SLEEP",
+		"NETWORK SLEEP",
+		"UNDEFINED"
+	};
+#endif
+	int status = AH_TRUE;
+	if (!setChip)
+		return AH_TRUE;
+
+	HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
+	    modes[ahp->ah_powerMode], modes[mode], setChip ? "set chip " : "");
+	switch (mode) {
+	case HAL_PM_AWAKE:
+		status = ar5416SetPowerModeAwake(ah, setChip);
+		break;
+	case HAL_PM_FULL_SLEEP:
+		ar5416SetPowerModeSleep(ah, setChip);
+		break;
+	case HAL_PM_NETWORK_SLEEP:
+		ar5416SetPowerModeNetworkSleep(ah, setChip);
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode 0x%x\n",
+		    __func__, mode);
+		return AH_FALSE;
+	}
+	ahp->ah_powerMode = mode;
+	return status;
+}
+
+/*
+ * Return the current sleep mode of the chip
+ */
+HAL_POWER_MODE
+ar5416GetPowerMode(struct ath_hal *ah)
+{
+	int mode = OS_REG_READ(ah, AR_RTC_STATUS);
+	switch (mode & AR_RTC_PM_STATUS_M) {
+	case AR_RTC_STATUS_ON:
+	case AR_RTC_STATUS_WAKEUP:
+		return HAL_PM_AWAKE;
+	case AR_RTC_STATUS_SLEEP:
+		return HAL_PM_NETWORK_SLEEP;
+	case AR_RTC_STATUS_SHUTDOWN:
+		return HAL_PM_FULL_SLEEP;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: unknown power mode, RTC_STATUS 0x%x\n",
+		    __func__, mode);
+		return HAL_PM_UNDEFINED;	
+	}
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_recv.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_recv.c
new file mode 100644
index 0000000..e888373
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_recv.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_recv.c,v 1.7 2008/11/11 20:46:06 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_desc.h"
+#include "ah_internal.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416desc.h"
+
+/*
+ * Start receive at the PCU engine
+ */
+void
+ar5416StartPcuReceive(struct ath_hal *ah)
+{
+	struct ath_hal_private *ahp = AH_PRIVATE(ah);
+
+	HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__);
+	ar5212EnableMibCounters(ah);
+	/* NB: restore current settings */
+	ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
+	/*
+	 * NB: must do after enabling phy errors to avoid rx
+	 *     frames w/ corrupted descriptor status.
+	 */
+	OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+}
+
+/*
+ * Stop receive at the PCU engine
+ * and abort current frame in PCU
+ */
+void
+ar5416StopPcuReceive(struct ath_hal *ah)
+{
+	OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+    
+	HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__);
+	ar5212DisableMibCounters(ah);
+}
+
+/*
+ * Initialize RX descriptor, by clearing the status and setting
+ * the size (and any other flags).
+ */
+HAL_BOOL
+ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
+    uint32_t size, u_int flags)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+
+	HALASSERT((size &~ AR_BufLen) == 0);
+
+	ads->ds_ctl1 = size & AR_BufLen;
+	if (flags & HAL_RXDESC_INTREQ)
+		ads->ds_ctl1 |= AR_RxIntrReq;
+
+	/* this should be enough */
+	ads->ds_rxstatus8 &= ~AR_RxDone;
+
+	return AH_TRUE;
+}
+
+/*
+ * Process an RX descriptor, and return the status to the caller.
+ * Copy some hardware specific items into the software portion
+ * of the descriptor.
+ *
+ * NB: the caller is responsible for validating the memory contents
+ *     of the descriptor (e.g. flushing any cached copy).
+ */
+HAL_STATUS
+ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
+    uint32_t pa, struct ath_desc *nds, uint64_t tsf,
+    struct ath_rx_status *rs)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+	struct ar5416_desc *ands = AR5416DESC(nds);
+
+	if ((ads->ds_rxstatus8 & AR_RxDone) == 0)
+		return HAL_EINPROGRESS;
+	/*
+	 * Given the use of a self-linked tail be very sure that the hw is
+	 * done with this descriptor; the hw may have done this descriptor
+	 * once and picked it up again...make sure the hw has moved on.
+	 */
+	if ((ands->ds_rxstatus8 & AR_RxDone) == 0
+	    && OS_REG_READ(ah, AR_RXDP) == pa)
+		return HAL_EINPROGRESS;
+
+	rs->rs_status = 0;
+	rs->rs_flags = 0;
+
+	rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen;
+	rs->rs_tstamp =  ads->AR_RcvTimestamp;
+
+	/* XXX what about KeyCacheMiss? */
+
+	rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined);
+	rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00);
+	rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01);
+	rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02);
+	rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10);
+	rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11);
+	rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12);
+
+	if (ads->ds_rxstatus8 & AR_RxKeyIdxValid)
+		rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx);
+	else
+		rs->rs_keyix = HAL_RXKEYIX_INVALID;
+
+	/* NB: caller expected to do rate table mapping */
+	rs->rs_rate = RXSTATUS_RATE(ah, ads);
+	rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0;
+
+	rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
+	rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
+	rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna);
+
+	if (ads->ds_rxstatus3 & AR_GI)
+		rs->rs_flags |= HAL_RX_GI;
+	if (ads->ds_rxstatus3 & AR_2040)
+		rs->rs_flags |= HAL_RX_2040;
+
+	if (ads->ds_rxstatus8 & AR_PreDelimCRCErr)
+		rs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
+	if (ads->ds_rxstatus8 & AR_PostDelimCRCErr)
+		rs->rs_flags |= HAL_RX_DELIM_CRC_POST;
+	if (ads->ds_rxstatus8 & AR_DecryptBusyErr)
+		rs->rs_flags |= HAL_RX_DECRYPT_BUSY;
+	if (ads->ds_rxstatus8 & AR_HiRxChain)
+		rs->rs_flags |= HAL_RX_HI_RX_CHAIN;
+
+	if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) {
+		/*
+		 * These four bits should not be set together.  The
+		 * 5416 spec states a Michael error can only occur if
+		 * DecryptCRCErr not set (and TKIP is used).  Experience
+		 * indicates however that you can also get Michael errors
+		 * when a CRC error is detected, but these are specious.
+		 * Consequently we filter them out here so we don't
+		 * confuse and/or complicate drivers.
+		 */
+		if (ads->ds_rxstatus8 & AR_CRCErr)
+			rs->rs_status |= HAL_RXERR_CRC;
+		else if (ads->ds_rxstatus8 & AR_PHYErr) {
+			u_int phyerr;
+
+			rs->rs_status |= HAL_RXERR_PHY;
+			phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode);
+			rs->rs_phyerr = phyerr;
+		} else if (ads->ds_rxstatus8 & AR_DecryptCRCErr)
+			rs->rs_status |= HAL_RXERR_DECRYPT;
+		else if (ads->ds_rxstatus8 & AR_MichaelErr)
+			rs->rs_status |= HAL_RXERR_MIC;
+	}
+
+	return HAL_OK;
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_reset.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_reset.c
new file mode 100644
index 0000000..74ba497
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_reset.c
@@ -0,0 +1,2895 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_reset.c,v 1.27 2008/11/27 22:30:08 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ah_eeprom_v14.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+#ifdef AH_SUPPORT_AR9280
+#include "ar5416/ar9280.h"
+#endif
+
+/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 
+#define	EEP_MINOR(_ah) \
+	(AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
+#define IS_EEP_MINOR_V2(_ah)	(EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
+#define IS_EEP_MINOR_V3(_ah)	(EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
+
+/* Additional Time delay to wait after activiting the Base band */
+#define BASE_ACTIVATE_DELAY	100	/* 100 usec */
+#define PLL_SETTLE_DELAY	300	/* 300 usec */
+#define RTC_PLL_SETTLE_DELAY    1000    /* 1 ms     */
+
+static void ar5416InitDMA(struct ath_hal *ah);
+static void ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan);
+static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode);
+static void ar5416InitQoS(struct ath_hal *ah);
+static void ar5416InitUserSettings(struct ath_hal *ah);
+
+static HAL_BOOL ar5416SetTransmitPower(struct ath_hal *ah, 
+	HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain);
+
+#if 0
+static HAL_BOOL	ar5416ChannelChange(struct ath_hal *, HAL_CHANNEL *);
+#endif
+static void ar5416SetDeltaSlope(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+static void ar5416SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan);
+#ifdef AH_SUPPORT_AR9280
+static void ar9280SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan);
+#endif
+
+static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
+static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
+static void ar5416InitPLL(struct ath_hal *ah, HAL_CHANNEL *chan);
+static HAL_BOOL ar5416SetBoardValues(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
+static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
+	struct ar5416eeprom *pEepData, 
+	HAL_CHANNEL_INTERNAL *chan, int16_t *ratesArray,
+	uint16_t cfgCtl, uint16_t AntennaReduction,
+	uint16_t twiceMaxRegulatoryPower, 
+	uint16_t powerLimit);
+static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
+	struct ar5416eeprom *pEepData,
+	HAL_CHANNEL_INTERNAL *chan,
+	int16_t *pTxPowerIndexOffset);
+static uint16_t ar5416GetMaxEdgePower(uint16_t freq,
+	CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
+static void ar5416GetTargetPowers(struct ath_hal *ah, 
+	HAL_CHANNEL_INTERNAL *chan, CAL_TARGET_POWER_HT *powInfo,
+	uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower,
+	uint16_t numRates, HAL_BOOL isHt40Target);
+static void ar5416GetTargetPowersLeg(struct ath_hal *ah, 
+	HAL_CHANNEL_INTERNAL *chan, CAL_TARGET_POWER_LEG *powInfo,
+	uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower,
+	uint16_t numRates, HAL_BOOL isExtTarget);
+
+static int16_t interpolate(uint16_t target, uint16_t srcLeft,
+	uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
+static void ar5416Set11nRegs(struct ath_hal *ah, HAL_CHANNEL *chan);
+static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 
+	HAL_CHANNEL_INTERNAL *chan, CAL_DATA_PER_FREQ *pRawDataSet,
+	uint8_t * bChans, uint16_t availPiers,
+	uint16_t tPdGainOverlap, int16_t *pMinCalPower,
+	uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
+	uint16_t numXpdGains);
+static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList,
+	uint16_t listSize,  uint16_t *indexL, uint16_t *indexR);
+static HAL_BOOL ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
+	uint8_t *pPwrList, uint8_t *pVpdList,
+	uint16_t numIntercepts, uint8_t *pRetVpdList);
+
+/*
+ * Places the device in and out of reset and then places sane
+ * values in the registers based on EEPROM config, initialization
+ * vectors (as determined by the mode), and station configuration
+ *
+ * bChannelChange is used to preserve DMA/PCU registers across
+ * a HW Reset during channel change.
+ */
+HAL_BOOL
+ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
+	HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status)
+{
+#define	N(a)	(sizeof (a) / sizeof (a[0]))
+#define	FAIL(_code)	do { ecode = _code; goto bad; } while (0)
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *ichan;
+	uint32_t softLedCfg;
+	uint32_t saveDefAntenna, saveLedState;
+	uint32_t macStaId1;
+	uint16_t rfXpdGain[2];
+	u_int modesIndex, freqIndex;
+	HAL_STATUS ecode;
+	int i, regWrites = 0;
+	uint32_t powerVal, rssiThrReg;
+	uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow;
+
+	OS_MARK(ah, AH_MARK_RESET, bChannelChange);
+#define	IS(_c,_f)	(((_c)->channelFlags & _f) || 0)
+	if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+	if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+#undef IS
+
+	/* Bring out of sleep mode */
+	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n",
+		    __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/*
+	 * Map public channel to private.
+	 */
+	ichan = ath_hal_checkchannel(ah, chan);
+	if (ichan == AH_NULL) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: invalid channel %u/0x%x; no mapping\n",
+		    __func__, chan->channel, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	} else {
+		HALDEBUG(ah, HAL_DEBUG_RESET,
+		    "%s: Ch=%u Max=%d Min=%d\n",__func__,
+		    ichan->channel, ichan->maxTxPower, ichan->minTxPower);
+	}
+	switch (opmode) {
+	case HAL_M_STA:
+	case HAL_M_IBSS:
+	case HAL_M_HOSTAP:
+	case HAL_M_MONITOR:
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
+		    __func__, opmode);
+		FAIL(HAL_EINVAL);
+		break;
+	}
+	HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
+
+	/* XXX Turn on fast channel change for 5416 */
+	/*
+	 * Preserve the bmiss rssi threshold and count threshold
+	 * across resets
+	 */
+	rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR);
+	/* If reg is zero, first time thru set to default val */
+	if (rssiThrReg == 0)
+		rssiThrReg = INIT_RSSI_THR;
+
+	/*
+	 * Preserve the antenna on a channel change
+	 */
+	saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
+	if (saveDefAntenna == 0)		/* XXX magic constants */
+		saveDefAntenna = 1;
+
+	/* Save hardware flag before chip reset clears the register */
+	macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 
+		(AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT);
+
+	/* Save led state from pci config register */
+	saveLedState = OS_REG_READ(ah, AR_MAC_LED) &
+		(AR_MAC_LED_ASSOC | AR_MAC_LED_MODE |
+		 AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW);
+	softLedCfg = OS_REG_READ(ah, AR_GPIO_INTR_OUT);	
+
+	/*
+	 * Adjust gain parameters before reset if
+	 * there's an outstanding gain updated.
+	 */
+	(void) ar5416GetRfgain(ah);
+
+	if (!ar5416ChipReset(ah, chan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Restore bmiss rssi & count thresholds */
+	OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg);
+
+	/* Setup the indices for the next set of register array writes */
+	/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
+	switch (chan->channelFlags & CHANNEL_ALL) {
+	case CHANNEL_A:
+    	case CHANNEL_A_HT20:
+                modesIndex = 1;
+                freqIndex  = 1;
+		break;
+    	case CHANNEL_T:
+    	case CHANNEL_A_HT40PLUS:
+    	case CHANNEL_A_HT40MINUS:
+                modesIndex = 2;
+                freqIndex  = 1;
+	    	break;
+	case CHANNEL_PUREG:
+	case CHANNEL_G_HT20:
+	case CHANNEL_B:	/* treat as channel G , no  B mode suport in owl */
+		modesIndex = 4;
+		freqIndex  = 2;
+		break;
+    	case CHANNEL_G_HT40PLUS:
+    	case CHANNEL_G_HT40MINUS:
+		modesIndex = 3;
+		freqIndex  = 2;
+		break;
+	case CHANNEL_108G:
+		modesIndex = 5;
+		freqIndex  = 2;
+		break;
+	default:
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
+		    __func__, chan->channelFlags);
+		FAIL(HAL_EINVAL);
+	}
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	/* Set correct Baseband to analog shift setting to access analog chips. */
+	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+	 /*
+	 * Write addac shifts
+	 */
+	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
+#if 0
+	/* NB: only required for Sowl */
+	ar5416EepromSetAddac(ah, ichan);
+#endif
+	regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
+	    regWrites);
+	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
+
+	/* XXX Merlin ini fixups */
+	/* XXX Merlin 100us delay for shift registers */
+	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex,
+	    regWrites);
+#ifdef AH_SUPPORT_AR9280
+	if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
+		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
+		    modesIndex, regWrites);
+		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
+		    modesIndex, regWrites);
+	}
+#endif
+	/* XXX Merlin 100us delay for shift registers */
+	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_common, 1, regWrites);
+	/* Setup 11n MAC/Phy mode registers */
+	ar5416Set11nRegs(ah,chan);	
+	/* XXX updated regWrites? */
+	ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
+#ifdef AH_SUPPORT_AR9280
+	if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
+		/* 5GHz channels w/ Fast Clock use different modal values */
+		regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
+		    modesIndex, regWrites);
+	}
+#endif
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n",
+		__func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK));
+	HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n",
+		__func__, OS_REG_READ(ah,AR_PHY_ADC_CTL));	
+
+	/* Set the mute mask to the correct default */
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2)
+		OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
+
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
+		/* Clear reg to alllow RX_CLEAR line debug */
+		OS_REG_WRITE(ah, AR_PHY_BLUETOOTH,  0);
+	}
+	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
+#ifdef notyet
+		/* Enable burst prefetch for the data queues */
+		OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
+		/* Enable double-buffering */
+		OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
+#endif
+	}
+
+	/* Set ADC/DAC select values */
+	OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
+
+	if (AH5416(ah)->ah_rx_chainmask == 0x5 ||
+	    AH5416(ah)->ah_tx_chainmask == 0x5)
+		OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
+	/* Setup Chain Masks */
+	OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask);
+	OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask);
+	OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask);
+
+	/* Setup the transmit power values. */
+	if (!ar5416SetTransmitPower(ah, ichan, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error init'ing transmit power\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Write the analog registers */
+	if (!ahp->ah_rfHal->setRfRegs(ah, ichan, freqIndex, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: ar5212SetRfRegs failed\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
+	if (IS_CHAN_OFDM(chan)|| IS_CHAN_HT(chan))
+		ar5416SetDeltaSlope(ah, ichan);
+
+#ifdef AH_SUPPORT_AR9280
+	if (AR_SREV_MERLIN_10_OR_LATER(ah))
+		ar9280SpurMitigate(ah, ichan);
+	else
+#endif
+		ar5416SpurMitigate(ah, ichan);
+
+	/* Setup board specific options for EEPROM version 3 */
+	if (!ar5416SetBoardValues(ah, ichan)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error setting board options\n", __func__);
+		FAIL(HAL_EIO);
+	}
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
+	OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
+		| macStaId1
+		| AR_STA_ID1_RTS_USE_DEF
+		| ahp->ah_staId1Defaults
+	);
+	ar5212SetOperatingMode(ah, opmode);
+
+	/* Set Venice BSSID mask according to current state */
+	OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
+	OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
+
+	/* Restore previous led state */
+	OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState);
+	/* Restore soft Led state to GPIO */
+	OS_REG_WRITE(ah, AR_GPIO_INTR_OUT, softLedCfg);
+
+	/* Restore previous antenna */
+	OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
+
+	/* then our BSSID */
+	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
+	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
+
+	/* Restore bmiss rssi & count thresholds */
+	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
+
+	OS_REG_WRITE(ah, AR_ISR, ~0);		/* cleared on write */
+
+	if (!ar5212SetChannel(ah, ichan))
+		FAIL(HAL_EIO);
+
+	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
+
+	/* Set 1:1 QCU to DCU mapping for all queues */
+	for (i = 0; i < AR_NUM_DCU; i++)
+		OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
+
+	ahp->ah_intrTxqs = 0;
+	for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
+		ar5212ResetTxQueue(ah, i);
+
+	ar5416InitIMR(ah, opmode);
+	ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
+	ar5416InitQoS(ah);
+	ar5416InitUserSettings(ah);
+
+	/*
+	 * disable seq number generation in hw
+	 */
+	 OS_REG_WRITE(ah, AR_STA_ID1,
+	     OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
+	 
+	ar5416InitDMA(ah);
+
+	/*
+	 * program OBS bus to see MAC interrupts
+	 */
+	OS_REG_WRITE(ah, AR_OBS, 8);
+
+#ifdef AR5416_INT_MITIGATION
+	OS_REG_WRITE(ah, AR_MIRT, 0);
+	OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
+	OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
+#endif	    
+	
+	ar5416InitBB(ah, chan);
+
+	/* Setup compression registers */
+	ar5212SetCompRegs(ah);		/* XXX not needed? */
+
+	/*
+	 * 5416 baseband will check the per rate power table
+	 * and select the lower of the two
+	 */
+	ackTpcPow = 63;
+	ctsTpcPow = 63;
+	chirpTpcPow = 63;
+	powerVal = SM(ackTpcPow, AR_TPC_ACK) |
+		SM(ctsTpcPow, AR_TPC_CTS) |
+		SM(chirpTpcPow, AR_TPC_CHIRP);
+	OS_REG_WRITE(ah, AR_TPC, powerVal);
+
+	if (!ar5416InitCal(ah, chan))
+		FAIL(HAL_ESELFTEST);
+
+	AH_PRIVATE(ah)->ah_opmode = opmode;	/* record operating mode */
+
+	if (bChannelChange) {
+		if (!(ichan->privFlags & CHANNEL_DFS)) 
+			ichan->privFlags &= ~CHANNEL_INTERFERENCE;
+		chan->channelFlags = ichan->channelFlags;
+		chan->privFlags = ichan->privFlags;
+		chan->maxRegTxPower = ichan->maxRegTxPower;
+		chan->maxTxPower = ichan->maxTxPower;
+		chan->minTxPower = ichan->minTxPower;
+	}
+
+	HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
+
+	OS_MARK(ah, AH_MARK_RESET_DONE, 0);
+
+	return AH_TRUE;
+bad:
+	OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
+	if (*status)
+		*status = ecode;
+	return AH_FALSE;
+#undef FAIL
+#undef N
+}
+
+#if 0
+/*
+ * This channel change evaluates whether the selected hardware can
+ * perform a synthesizer-only channel change (no reset).  If the
+ * TX is not stopped, or the RFBus cannot be granted in the given
+ * time, the function returns false as a reset is necessary
+ */
+HAL_BOOL
+ar5416ChannelChange(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	uint32_t       ulCount;
+	uint32_t   data, synthDelay, qnum;
+	uint16_t   rfXpdGain[4];
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	HAL_CHANNEL_INTERNAL *ichan;
+
+	/*
+	 * Map public channel to private.
+	 */
+	ichan = ath_hal_checkchannel(ah, chan);
+
+	/* TX must be stopped or RF Bus grant will not work */
+	for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {
+		if (ar5212NumTxPending(ah, qnum)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: frames pending on queue %d\n", __func__, qnum);
+			return AH_FALSE;
+		}
+	}
+
+	/*
+	 * Kill last Baseband Rx Frame - Request analog bus grant
+	 */
+	OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST);
+	if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n",
+		    __func__);
+		return AH_FALSE;
+	}
+
+	ar5416Set11nRegs(ah, chan);	/* NB: setup 5416-specific regs */
+
+	/* Change the synth */
+	if (!ar5212SetChannel(ah, ichan))
+		return AH_FALSE;
+
+	/* Setup the transmit power values. */
+	if (!ar5416SetTransmitPower(ah, ichan, rfXpdGain)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error init'ing transmit power\n", __func__);
+		return AH_FALSE;
+	}
+
+	/*
+	 * Wait for the frequency synth to settle (synth goes on
+	 * via PHY_ACTIVE_EN).  Read the phy active delay register.
+	 * Value is in 100ns increments.
+	 */
+	data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
+	if (IS_CHAN_CCK(ichan)) {
+		synthDelay = (4 * data) / 22;
+	} else {
+		synthDelay = data / 10;
+	}
+
+	OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
+
+	/* Release the RFBus Grant */
+	OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
+
+	/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
+	if (IS_CHAN_OFDM(ichan)|| IS_CHAN_HT(chan)) {
+		if (ahp->ah_eeprom.ee_version >= AR_EEPROM_VER5_3 &&
+		    !IS_CHAN_B(chan))
+			ar5212SetSpurMitigation(ah, ichan);
+		ar5416SetDeltaSlope(ah, ichan);
+	}
+
+	/* XXX spur mitigation for Melin */
+
+	/* Copy over internal channel flags to public hal channel */
+
+	if (!(ichan->privFlags & CHANNEL_DFS)) 
+		ichan->privFlags &= ~CHANNEL_INTERFERENCE;
+	chan->channelFlags = ichan->channelFlags;
+	chan->privFlags = ichan->privFlags;
+	chan->maxRegTxPower = ichan->maxRegTxPower;
+	chan->maxTxPower = ichan->maxTxPower;
+	chan->minTxPower = ichan->minTxPower;
+	AH_PRIVATE(ah)->ah_curchan->ah_channel_time=0;
+	AH_PRIVATE(ah)->ah_curchan->ah_tsf_last = ar5212GetTsf64(ah);
+	ar5212TxEnable(ah,AH_TRUE);
+	return AH_TRUE;
+}
+#endif
+
+static void
+ar5416InitDMA(struct ath_hal *ah)
+{
+
+	/*
+	 * set AHB_MODE not to do cacheline prefetches
+	 */
+	OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
+
+	/*
+	 * let mac dma reads be in 128 byte chunks
+	 */
+	OS_REG_WRITE(ah, AR_TXCFG, 
+		(OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B);
+
+	/*
+	 * let mac dma writes be in 128 byte chunks
+	 */
+	OS_REG_WRITE(ah, AR_RXCFG, 
+		(OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B);
+
+	/* XXX restore TX trigger level */
+
+	/*
+	 * Setup receive FIFO threshold to hold off TX activities
+	 */
+	OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
+	
+	/*
+	 * reduce the number of usable entries in PCU TXBUF to avoid
+	 * wrap around.
+	 */
+	OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE);
+}
+
+static void
+ar5416InitBB(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	uint32_t synthDelay;
+
+	/*
+	 * Wait for the frequency synth to settle (synth goes on
+	 * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
+	 * Value is in 100ns increments.
+	  */
+	synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
+	if (IS_CHAN_CCK(chan)) {
+		synthDelay = (4 * synthDelay) / 22;
+	} else {
+		synthDelay /= 10;
+	}
+
+	/* Turn on PLL on 5416 */
+	HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n",
+	    __func__, IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz");
+	ar5416InitPLL(ah, chan);
+
+	/* Activate the PHY (includes baseband activate and synthesizer on) */
+	OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+	
+	/* 
+	 * If the AP starts the calibration before the base band timeout
+	 * completes  we could get rx_clear false triggering.  Add an
+	 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
+	 * does not happen.
+	 */
+	if (IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+		OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
+	} else if (IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+		OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
+	} else {
+		OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
+	}
+}
+
+static void
+ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	/*
+	 * Setup interrupt handling.  Note that ar5212ResetTxQueue
+	 * manipulates the secondary IMR's as queues are enabled
+	 * and disabled.  This is done with RMW ops to insure the
+	 * settings we make here are preserved.
+	 */
+        ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN
+			| AR_IMR_RXERR | AR_IMR_RXORN
+                        | AR_IMR_BCNMISC;
+
+#ifdef AR5416_INT_MITIGATION
+       	ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM
+			|  AR_IMR_TXMINTR | AR_IMR_RXMINTR;
+#else
+        ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK;
+#endif	
+	if (opmode == HAL_M_HOSTAP)
+		ahp->ah_maskReg |= AR_IMR_MIB;
+	OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
+	/* Enable bus errors that are OR'd to set the HIUERR bit */
+	
+#if 0
+	OS_REG_WRITE(ah, AR_IMR_S2, 
+	    	OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST);      
+#endif
+}
+
+static void
+ar5416InitQoS(struct ath_hal *ah)
+{
+	/* QoS support */
+	OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa);	/* XXX magic */
+	OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210);	/* XXX magic */
+
+	/* Turn on NOACK Support for QoS packets */
+	OS_REG_WRITE(ah, AR_NOACK,
+		SM(2, AR_NOACK_2BIT_VALUE) |
+		SM(5, AR_NOACK_BIT_OFFSET) |
+		SM(0, AR_NOACK_BYTE_OFFSET));
+		
+    	/*
+    	 * initialize TXOP for all TIDs
+    	 */
+	OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
+	OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
+	OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
+	OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
+	OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
+}
+
+static void
+ar5416InitUserSettings(struct ath_hal *ah)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	/* Restore user-specified settings */
+	if (ahp->ah_miscMode != 0)
+		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+	if (ahp->ah_sifstime != (u_int) -1)
+		ar5212SetSifsTime(ah, ahp->ah_sifstime);
+	if (ahp->ah_slottime != (u_int) -1)
+		ar5212SetSlotTime(ah, ahp->ah_slottime);
+	if (ahp->ah_acktimeout != (u_int) -1)
+		ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
+	if (ahp->ah_ctstimeout != (u_int) -1)
+		ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
+	if (AH_PRIVATE(ah)->ah_diagreg != 0)
+		OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
+#if 0 /* XXX Todo */
+	if (ahp->ah_globaltxtimeout != (u_int) -1)
+        	ar5416SetGlobalTxTimeout(ah, ahp->ah_globaltxtimeout);
+#endif
+}
+
+/*
+ * Places the hardware into reset and then pulls it out of reset
+ */
+HAL_BOOL
+ar5416ChipReset(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	uint32_t rfMode = 0;
+
+	OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->channel : 0);
+	/*
+	 * Warm reset is optimistic.
+	 */
+	if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
+	    ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
+		if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))
+			return AH_FALSE;
+	} else {
+		if (!ar5416SetResetReg(ah, HAL_RESET_WARM))
+			return AH_FALSE;
+	}
+
+	/* Bring out of sleep mode (AGAIN) */
+	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+	       return AH_FALSE;
+
+	ar5416InitPLL(ah, chan);
+
+	/*
+	 * Perform warm reset before the mode/PLL/turbo registers
+	 * are changed in order to deactivate the radio.  Mode changes
+	 * with an active radio can result in corrupted shifts to the
+	 * radio device.
+	 */
+	if (chan != AH_NULL) { 
+		/* treat channel B as channel G , no  B mode suport in owl */
+		rfMode |= (IS_CHAN_G(chan) || IS_CHAN_B(chan)) ?
+			AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
+		if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
+			/* phy mode bits for 5GHz channels require Fast Clock */
+			rfMode |= AR_PHY_MODE_DYNAMIC
+			       |  AR_PHY_MODE_DYN_CCK_DISABLE;
+		} else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) {
+			rfMode |= (IS_CHAN_5GHZ(chan)) ?
+				AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
+		}
+		OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
+	}
+	return AH_TRUE;	
+}
+
+/*
+ * Delta slope coefficient computation.
+ * Required for OFDM operation.
+ */
+static void
+ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled,
+                          uint32_t *coef_mantissa, uint32_t *coef_exponent)
+{
+#define COEF_SCALE_S 24
+    uint32_t coef_exp, coef_man;
+    /*
+     * ALGO -> coef_exp = 14-floor(log2(coef));
+     * floor(log2(x)) is the highest set bit position
+     */
+    for (coef_exp = 31; coef_exp > 0; coef_exp--)
+            if ((coef_scaled >> coef_exp) & 0x1)
+                    break;
+    /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */
+    HALASSERT(coef_exp);
+    coef_exp = 14 - (coef_exp - COEF_SCALE_S);
+
+    /*
+     * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5);
+     * The coefficient is already shifted up for scaling
+     */
+    coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
+
+    *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
+    *coef_exponent = coef_exp - 16;
+
+#undef COEF_SCALE_S    
+}
+
+void
+ar5416SetDeltaSlope(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+#define INIT_CLOCKMHZSCALED	0x64000000
+	uint32_t coef_scaled, ds_coef_exp, ds_coef_man;
+	uint32_t clockMhzScaled = INIT_CLOCKMHZSCALED;
+
+	CHAN_CENTERS centers;
+
+	if (IS_CHAN_TURBO(chan))
+		clockMhzScaled *= 2;
+	/* half and quarter rate can divide the scaled clock by 2 or 4 respectively */
+	/* scale for selected channel bandwidth */ 
+	if (IS_CHAN_HALF_RATE(chan)) {
+		clockMhzScaled = clockMhzScaled >> 1;
+	} else if (IS_CHAN_QUARTER_RATE(chan)) {
+		clockMhzScaled = clockMhzScaled >> 2;
+	} 
+
+	/*
+	 * ALGO -> coef = 1e8/fcarrier*fclock/40;
+	 * scaled coef to provide precision for this floating calculation 
+	 */
+	ar5416GetChannelCenters(ah, chan, &centers);
+	coef_scaled = clockMhzScaled / centers.synth_center;		
+	
+ 	ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
+
+	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
+		AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
+	OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
+		AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
+		
+        /*
+         * For Short GI,
+         * scaled coeff is 9/10 that of normal coeff
+         */ 
+        coef_scaled = (9 * coef_scaled)/10;
+
+        ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
+
+        /* for short gi */
+        OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
+                AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
+        OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
+                AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);	
+#undef INIT_CLOCKMHZSCALED
+}
+
+/*
+ * Convert to baseband spur frequency given input channel frequency 
+ * and compute register settings below.
+ */
+#define SPUR_RSSI_THRESH 40
+
+static void
+ar5416SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+    static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
+                AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
+    static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
+                AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
+    static const int inc[4] = { 0, 100, 0, 0 };
+
+    int bb_spur = AR_NO_SPUR;
+    int bin, cur_bin;
+    int spur_freq_sd;
+    int spur_delta_phase;
+    int denominator;
+    int upper, lower, cur_vit_mask;
+    int tmp, new;
+    int i;
+
+    int8_t mask_m[123];
+    int8_t mask_p[123];
+    int8_t mask_amt;
+    int tmp_mask;
+    int cur_bb_spur;
+    HAL_BOOL is2GHz = IS_CHAN_2GHZ(chan);
+
+    OS_MEMZERO(mask_m, sizeof(mask_m));
+    OS_MEMZERO(mask_p, sizeof(mask_p));
+
+    /*
+     * Need to verify range +/- 9.5 for static ht20, otherwise spur
+     * is out-of-band and can be ignored.
+     */
+    for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+        cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
+        if (AR_NO_SPUR == cur_bb_spur)
+            break;
+        cur_bb_spur = cur_bb_spur - (chan->channel * 10);
+        if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
+            bb_spur = cur_bb_spur;
+            break;
+        }
+    }
+    if (AR_NO_SPUR == bb_spur)
+        return;
+
+    bin = bb_spur * 32;
+
+    tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
+    new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
+        AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+        AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
+        AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+
+    OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
+
+    new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
+        AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
+        AR_PHY_SPUR_REG_MASK_RATE_SELECT |
+        AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
+        SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
+    OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
+    /*
+     * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
+     * config, no offset for HT20.
+     * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
+     * /80 for dyn2040.
+     */
+    spur_delta_phase = ((bb_spur * 524288) / 100) &
+        AR_PHY_TIMING11_SPUR_DELTA_PHASE;
+    /*
+     * in 11A mode the denominator of spur_freq_sd should be 40 and
+     * it should be 44 in 11G
+     */
+    denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
+    spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
+
+    new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
+        SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
+        SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
+    OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
+
+
+    /*
+     * ============================================
+     * pilot mask 1 [31:0] = +6..-26, no 0 bin
+     * pilot mask 2 [19:0] = +26..+7
+     *
+     * channel mask 1 [31:0] = +6..-26, no 0 bin
+     * channel mask 2 [19:0] = +26..+7
+     */
+    //cur_bin = -26;
+    cur_bin = -6000;
+    upper = bin + 100;
+    lower = bin - 100;
+
+    for (i = 0; i < 4; i++) {
+        int pilot_mask = 0;
+        int chan_mask  = 0;
+        int bp         = 0;
+        for (bp = 0; bp < 30; bp++) {
+            if ((cur_bin > lower) && (cur_bin < upper)) {
+                pilot_mask = pilot_mask | 0x1 << bp;
+                chan_mask  = chan_mask | 0x1 << bp;
+            }
+            cur_bin += 100;
+        }
+        cur_bin += inc[i];
+        OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
+        OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
+    }
+
+    /* =================================================
+     * viterbi mask 1 based on channel magnitude
+     * four levels 0-3
+     *  - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
+     *      [1 2 2 1] for -9.6 or [1 2 1] for +16
+     *  - enable_mask_ppm, all bins move with freq
+     *
+     *  - mask_select,    8 bits for rates (reg 67,0x990c)
+     *  - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
+     *      choose which mask to use mask or mask2
+     */
+
+    /*
+     * viterbi mask 2  2nd set for per data rate puncturing
+     * four levels 0-3
+     *  - mask_select, 8 bits for rates (reg 67)
+     *  - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
+     *      [1 2 2 1] for -9.6 or [1 2 1] for +16
+     */
+    cur_vit_mask = 6100;
+    upper        = bin + 120;
+    lower        = bin - 120;
+
+    for (i = 0; i < 123; i++) {
+        if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
+            if ((abs(cur_vit_mask - bin)) < 75) {
+                mask_amt = 1;
+            } else {
+                mask_amt = 0;
+            }
+            if (cur_vit_mask < 0) {
+                mask_m[abs(cur_vit_mask / 100)] = mask_amt;
+            } else {
+                mask_p[cur_vit_mask / 100] = mask_amt;
+            }
+        }
+        cur_vit_mask -= 100;
+    }
+
+    tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
+          | (mask_m[48] << 26) | (mask_m[49] << 24)
+          | (mask_m[50] << 22) | (mask_m[51] << 20)
+          | (mask_m[52] << 18) | (mask_m[53] << 16)
+          | (mask_m[54] << 14) | (mask_m[55] << 12)
+          | (mask_m[56] << 10) | (mask_m[57] <<  8)
+          | (mask_m[58] <<  6) | (mask_m[59] <<  4)
+          | (mask_m[60] <<  2) | (mask_m[61] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
+
+    tmp_mask =             (mask_m[31] << 28)
+          | (mask_m[32] << 26) | (mask_m[33] << 24)
+          | (mask_m[34] << 22) | (mask_m[35] << 20)
+          | (mask_m[36] << 18) | (mask_m[37] << 16)
+          | (mask_m[48] << 14) | (mask_m[39] << 12)
+          | (mask_m[40] << 10) | (mask_m[41] <<  8)
+          | (mask_m[42] <<  6) | (mask_m[43] <<  4)
+          | (mask_m[44] <<  2) | (mask_m[45] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
+
+    tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
+          | (mask_m[18] << 26) | (mask_m[18] << 24)
+          | (mask_m[20] << 22) | (mask_m[20] << 20)
+          | (mask_m[22] << 18) | (mask_m[22] << 16)
+          | (mask_m[24] << 14) | (mask_m[24] << 12)
+          | (mask_m[25] << 10) | (mask_m[26] <<  8)
+          | (mask_m[27] <<  6) | (mask_m[28] <<  4)
+          | (mask_m[29] <<  2) | (mask_m[30] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
+
+    tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
+          | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
+          | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
+          | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
+          | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
+          | (mask_m[10] << 10) | (mask_m[11] <<  8)
+          | (mask_m[12] <<  6) | (mask_m[13] <<  4)
+          | (mask_m[14] <<  2) | (mask_m[15] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
+
+    tmp_mask =             (mask_p[15] << 28)
+          | (mask_p[14] << 26) | (mask_p[13] << 24)
+          | (mask_p[12] << 22) | (mask_p[11] << 20)
+          | (mask_p[10] << 18) | (mask_p[ 9] << 16)
+          | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
+          | (mask_p[ 6] << 10) | (mask_p[ 5] <<  8)
+          | (mask_p[ 4] <<  6) | (mask_p[ 3] <<  4)
+          | (mask_p[ 2] <<  2) | (mask_p[ 1] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
+
+    tmp_mask =             (mask_p[30] << 28)
+          | (mask_p[29] << 26) | (mask_p[28] << 24)
+          | (mask_p[27] << 22) | (mask_p[26] << 20)
+          | (mask_p[25] << 18) | (mask_p[24] << 16)
+          | (mask_p[23] << 14) | (mask_p[22] << 12)
+          | (mask_p[21] << 10) | (mask_p[20] <<  8)
+          | (mask_p[19] <<  6) | (mask_p[18] <<  4)
+          | (mask_p[17] <<  2) | (mask_p[16] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
+
+    tmp_mask =             (mask_p[45] << 28)
+          | (mask_p[44] << 26) | (mask_p[43] << 24)
+          | (mask_p[42] << 22) | (mask_p[41] << 20)
+          | (mask_p[40] << 18) | (mask_p[39] << 16)
+          | (mask_p[38] << 14) | (mask_p[37] << 12)
+          | (mask_p[36] << 10) | (mask_p[35] <<  8)
+          | (mask_p[34] <<  6) | (mask_p[33] <<  4)
+          | (mask_p[32] <<  2) | (mask_p[31] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
+
+    tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
+          | (mask_p[59] << 26) | (mask_p[58] << 24)
+          | (mask_p[57] << 22) | (mask_p[56] << 20)
+          | (mask_p[55] << 18) | (mask_p[54] << 16)
+          | (mask_p[53] << 14) | (mask_p[52] << 12)
+          | (mask_p[51] << 10) | (mask_p[50] <<  8)
+          | (mask_p[49] <<  6) | (mask_p[48] <<  4)
+          | (mask_p[47] <<  2) | (mask_p[46] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
+}
+
+#ifdef AH_SUPPORT_AR9280
+#define	AR_BASE_FREQ_2GHZ	2300
+#define	AR_BASE_FREQ_5GHZ	4900
+#define	AR_SPUR_FEEQ_BOUND_HT40	19
+#define	AR_SPUR_FEEQ_BOUND_HT20	10
+
+static void
+ar9280SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
+{
+    static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
+                AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
+    static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
+                AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
+    static int inc[4] = { 0, 100, 0, 0 };
+
+    int bb_spur = AR_NO_SPUR;
+    int freq;
+    int bin, cur_bin;
+    int bb_spur_off, spur_subchannel_sd;
+    int spur_freq_sd;
+    int spur_delta_phase;
+    int denominator;
+    int upper, lower, cur_vit_mask;
+    int tmp, newVal;
+    int i;
+    CHAN_CENTERS centers;
+
+    int8_t mask_m[123];
+    int8_t mask_p[123];
+    int8_t mask_amt;
+    int tmp_mask;
+    int cur_bb_spur;
+    HAL_BOOL is2GHz = IS_CHAN_2GHZ(ichan);
+
+    OS_MEMZERO(&mask_m, sizeof(int8_t) * 123);
+    OS_MEMZERO(&mask_p, sizeof(int8_t) * 123);
+
+    ar5416GetChannelCenters(ah, ichan, &centers);
+    freq = centers.synth_center;
+
+    /*
+     * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40,
+     * otherwise spur is out-of-band and can be ignored.
+     */
+    for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+        cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
+        /* Get actual spur freq in MHz from EEPROM read value */ 
+        if (is2GHz) {
+            cur_bb_spur =  (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
+        } else {
+            cur_bb_spur =  (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
+        }
+
+        if (AR_NO_SPUR == cur_bb_spur)
+            break;
+        cur_bb_spur = cur_bb_spur - freq;
+
+        if (IS_CHAN_HT40(ichan)) {
+            if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 
+                (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
+                bb_spur = cur_bb_spur;
+                break;
+            }
+        } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
+                   (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
+            bb_spur = cur_bb_spur;
+            break;
+        }
+    }
+
+    if (AR_NO_SPUR == bb_spur) {
+#if 1
+        /*
+         * MRC CCK can interfere with beacon detection and cause deaf/mute.
+         * Disable MRC CCK for now.
+         */
+        OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+#else
+        /* Enable MRC CCK if no spur is found in this channel. */
+        OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+#endif
+        return;
+    } else {
+        /* 
+         * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur
+         * is found in this channel.
+         */
+        OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+    }
+
+    bin = bb_spur * 320;
+
+    tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
+
+    newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
+        AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
+        AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
+        AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
+    OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);
+
+    newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
+        AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
+        AR_PHY_SPUR_REG_MASK_RATE_SELECT |
+        AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
+        SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
+    OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
+
+    /* Pick control or extn channel to cancel the spur */
+    if (IS_CHAN_HT40(ichan)) {
+        if (bb_spur < 0) {
+            spur_subchannel_sd = 1;
+            bb_spur_off = bb_spur + 10;
+        } else {
+            spur_subchannel_sd = 0;
+            bb_spur_off = bb_spur - 10;
+        }
+    } else {
+        spur_subchannel_sd = 0;
+        bb_spur_off = bb_spur;
+    }
+
+    /*
+     * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
+     * /80 for dyn2040.
+     */
+    if (IS_CHAN_HT40(ichan))
+        spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;    
+    else
+        spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
+
+    /*
+     * in 11A mode the denominator of spur_freq_sd should be 40 and
+     * it should be 44 in 11G
+     */
+    denominator = IS_CHAN_2GHZ(ichan) ? 44 : 40;
+    spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
+
+    newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
+        SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
+        SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
+    OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);
+
+    /* Choose to cancel between control and extension channels */
+    newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
+    OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
+
+    /*
+     * ============================================
+     * Set Pilot and Channel Masks
+     *
+     * pilot mask 1 [31:0] = +6..-26, no 0 bin
+     * pilot mask 2 [19:0] = +26..+7
+     *
+     * channel mask 1 [31:0] = +6..-26, no 0 bin
+     * channel mask 2 [19:0] = +26..+7
+     */
+    cur_bin = -6000;
+    upper = bin + 100;
+    lower = bin - 100;
+
+    for (i = 0; i < 4; i++) {
+        int pilot_mask = 0;
+        int chan_mask  = 0;
+        int bp         = 0;
+        for (bp = 0; bp < 30; bp++) {
+            if ((cur_bin > lower) && (cur_bin < upper)) {
+                pilot_mask = pilot_mask | 0x1 << bp;
+                chan_mask  = chan_mask | 0x1 << bp;
+            }
+            cur_bin += 100;
+        }
+        cur_bin += inc[i];
+        OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
+        OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
+    }
+
+    /* =================================================
+     * viterbi mask 1 based on channel magnitude
+     * four levels 0-3
+     *  - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
+     *      [1 2 2 1] for -9.6 or [1 2 1] for +16
+     *  - enable_mask_ppm, all bins move with freq
+     *
+     *  - mask_select,    8 bits for rates (reg 67,0x990c)
+     *  - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
+     *      choose which mask to use mask or mask2
+     */
+
+    /*
+     * viterbi mask 2  2nd set for per data rate puncturing
+     * four levels 0-3
+     *  - mask_select, 8 bits for rates (reg 67)
+     *  - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
+     *      [1 2 2 1] for -9.6 or [1 2 1] for +16
+     */
+    cur_vit_mask = 6100;
+    upper        = bin + 120;
+    lower        = bin - 120;
+
+    for (i = 0; i < 123; i++) {
+        if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
+            if ((abs(cur_vit_mask - bin)) < 75) {
+                mask_amt = 1;
+            } else {
+                mask_amt = 0;
+            }
+            if (cur_vit_mask < 0) {
+                mask_m[abs(cur_vit_mask / 100)] = mask_amt;
+            } else {
+                mask_p[cur_vit_mask / 100] = mask_amt;
+            }
+        }
+        cur_vit_mask -= 100;
+    }
+
+    tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
+          | (mask_m[48] << 26) | (mask_m[49] << 24)
+          | (mask_m[50] << 22) | (mask_m[51] << 20)
+          | (mask_m[52] << 18) | (mask_m[53] << 16)
+          | (mask_m[54] << 14) | (mask_m[55] << 12)
+          | (mask_m[56] << 10) | (mask_m[57] <<  8)
+          | (mask_m[58] <<  6) | (mask_m[59] <<  4)
+          | (mask_m[60] <<  2) | (mask_m[61] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
+
+    tmp_mask =             (mask_m[31] << 28)
+          | (mask_m[32] << 26) | (mask_m[33] << 24)
+          | (mask_m[34] << 22) | (mask_m[35] << 20)
+          | (mask_m[36] << 18) | (mask_m[37] << 16)
+          | (mask_m[48] << 14) | (mask_m[39] << 12)
+          | (mask_m[40] << 10) | (mask_m[41] <<  8)
+          | (mask_m[42] <<  6) | (mask_m[43] <<  4)
+          | (mask_m[44] <<  2) | (mask_m[45] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
+
+    tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
+          | (mask_m[18] << 26) | (mask_m[18] << 24)
+          | (mask_m[20] << 22) | (mask_m[20] << 20)
+          | (mask_m[22] << 18) | (mask_m[22] << 16)
+          | (mask_m[24] << 14) | (mask_m[24] << 12)
+          | (mask_m[25] << 10) | (mask_m[26] <<  8)
+          | (mask_m[27] <<  6) | (mask_m[28] <<  4)
+          | (mask_m[29] <<  2) | (mask_m[30] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
+
+    tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
+          | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
+          | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
+          | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
+          | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
+          | (mask_m[10] << 10) | (mask_m[11] <<  8)
+          | (mask_m[12] <<  6) | (mask_m[13] <<  4)
+          | (mask_m[14] <<  2) | (mask_m[15] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
+
+    tmp_mask =             (mask_p[15] << 28)
+          | (mask_p[14] << 26) | (mask_p[13] << 24)
+          | (mask_p[12] << 22) | (mask_p[11] << 20)
+          | (mask_p[10] << 18) | (mask_p[ 9] << 16)
+          | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
+          | (mask_p[ 6] << 10) | (mask_p[ 5] <<  8)
+          | (mask_p[ 4] <<  6) | (mask_p[ 3] <<  4)
+          | (mask_p[ 2] <<  2) | (mask_p[ 1] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
+
+    tmp_mask =             (mask_p[30] << 28)
+          | (mask_p[29] << 26) | (mask_p[28] << 24)
+          | (mask_p[27] << 22) | (mask_p[26] << 20)
+          | (mask_p[25] << 18) | (mask_p[24] << 16)
+          | (mask_p[23] << 14) | (mask_p[22] << 12)
+          | (mask_p[21] << 10) | (mask_p[20] <<  8)
+          | (mask_p[19] <<  6) | (mask_p[18] <<  4)
+          | (mask_p[17] <<  2) | (mask_p[16] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
+
+    tmp_mask =             (mask_p[45] << 28)
+          | (mask_p[44] << 26) | (mask_p[43] << 24)
+          | (mask_p[42] << 22) | (mask_p[41] << 20)
+          | (mask_p[40] << 18) | (mask_p[39] << 16)
+          | (mask_p[38] << 14) | (mask_p[37] << 12)
+          | (mask_p[36] << 10) | (mask_p[35] <<  8)
+          | (mask_p[34] <<  6) | (mask_p[33] <<  4)
+          | (mask_p[32] <<  2) | (mask_p[31] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
+
+    tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
+          | (mask_p[59] << 26) | (mask_p[58] << 24)
+          | (mask_p[57] << 22) | (mask_p[56] << 20)
+          | (mask_p[55] << 18) | (mask_p[54] << 16)
+          | (mask_p[53] << 14) | (mask_p[52] << 12)
+          | (mask_p[51] << 10) | (mask_p[50] <<  8)
+          | (mask_p[49] <<  6) | (mask_p[48] <<  4)
+          | (mask_p[47] <<  2) | (mask_p[46] <<  0);
+    OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
+    OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
+}
+#endif /* AH_SUPPORT_AR9280 */
+
+/*
+ * Set a limit on the overall output power.  Used for dynamic
+ * transmit power control and the like.
+ *
+ * NB: limit is in units of 0.5 dbM.
+ */
+HAL_BOOL
+ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
+{
+	uint16_t dummyXpdGains[2];
+
+	AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
+	return ar5416SetTransmitPower(ah, AH_PRIVATE(ah)->ah_curchan,
+			dummyXpdGains);
+}
+
+HAL_BOOL
+ar5416GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL *chans, uint32_t nchans)
+{
+	struct ath_hal_5212 *ahp = AH5212(ah);
+	int16_t minPower, maxPower;
+	HAL_CHANNEL *chan;
+	int i;
+
+	/*
+	 * Get Pier table max and min powers.
+	 */
+	for (i = 0; i < nchans; i++) {
+		chan = &chans[i];
+		if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {
+			/* NB: rf code returns 1/4 dBm units, convert */
+			chan->maxTxPower = maxPower / 2;
+			chan->minTxPower = minPower / 2;
+		} else {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: no min/max power for %u/0x%x\n",
+			    __func__, chan->channel, chan->channelFlags);
+			chan->maxTxPower = AR5416_MAX_RATE_POWER;
+			chan->minTxPower = 0;
+		}
+	}
+#ifdef AH_DEBUG
+	for (i=0; i<nchans; i++) {
+		HALDEBUG(ah, HAL_DEBUG_RESET,
+		    "Chan %d: MaxPow = %d MinPow = %d\n",
+		    chans[i].channel,chans[i].maxTxPower, chans[i].minTxPower);
+	}
+#endif
+	return AH_TRUE;
+}
+
+/* XXX gag, this is sick */
+typedef enum Ar5416_Rates {
+	rate6mb,  rate9mb,  rate12mb, rate18mb,
+	rate24mb, rate36mb, rate48mb, rate54mb,
+	rate1l,   rate2l,   rate2s,   rate5_5l,
+	rate5_5s, rate11l,  rate11s,  rateXr,
+	rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
+	rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
+	rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
+	rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
+	rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
+	Ar5416RateSize
+} AR5416_RATES;
+
+/**************************************************************
+ * ar5416SetTransmitPower
+ *
+ * Set the transmit power in the baseband for the given
+ * operating channel and mode.
+ */
+static HAL_BOOL
+ar5416SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain)
+{
+#define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
+#define N(a)            (sizeof (a) / sizeof (a[0]))
+
+    MODAL_EEP_HEADER	*pModal;
+    struct ath_hal_5212 *ahp = AH5212(ah);
+    int16_t		ratesArray[Ar5416RateSize];
+    int16_t		txPowerIndexOffset = 0;
+    uint8_t		ht40PowerIncForPdadc = 2;	
+    int			i;
+    
+    uint16_t		cfgCtl;
+    uint16_t		powerLimit;
+    uint16_t		twiceAntennaReduction;
+    uint16_t		twiceMaxRegulatoryPower;
+    int16_t		maxPower;
+    HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+    struct ar5416eeprom	*pEepData = &ee->ee_base;
+
+    HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
+
+    /* Setup info for the actual eeprom */
+    ath_hal_memzero(ratesArray, sizeof(ratesArray));
+    cfgCtl = ath_hal_getctl(ah, (HAL_CHANNEL *)chan);
+    powerLimit = chan->maxRegTxPower * 2;
+    twiceAntennaReduction = chan->antennaMax;
+    twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 
+    pModal = &pEepData->modalHeader[IS_CHAN_2GHZ(chan)];
+    HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
+	__func__,chan->channel, cfgCtl );      
+  
+    if (IS_EEP_MINOR_V2(ah)) {
+        ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
+    }
+ 
+    if (!ar5416SetPowerPerRateTable(ah, pEepData,  chan,
+                                    &ratesArray[0],cfgCtl,
+                                    twiceAntennaReduction,
+				    twiceMaxRegulatoryPower, powerLimit)) {
+        HALDEBUG(ah, HAL_DEBUG_ANY,
+	    "%s: unable to set tx power per rate table\n", __func__);
+        return AH_FALSE;
+    }
+
+    if (!ar5416SetPowerCalTable(ah,  pEepData, chan, &txPowerIndexOffset)) {
+        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
+	    __func__);
+        return AH_FALSE;
+    }
+  
+    maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
+
+    if (IS_CHAN_2GHZ(chan)) {
+        maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
+    }
+
+    if (IS_CHAN_HT40(chan)) {
+        maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
+    }
+
+    ahp->ah_tx6PowerInHalfDbm = maxPower;   
+    AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
+    ahp->ah_txPowerIndexOffset = txPowerIndexOffset;
+
+    /*
+     * txPowerIndexOffset is set by the SetPowerTable() call -
+     *  adjust the rate table (0 offset if rates EEPROM not loaded)
+     */
+    for (i = 0; i < N(ratesArray); i++) {
+        ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
+        if (ratesArray[i] > AR5416_MAX_RATE_POWER)
+            ratesArray[i] = AR5416_MAX_RATE_POWER;
+    }
+
+#ifdef AH_EEPROM_DUMP
+    ar5416PrintPowerPerRate(ah, ratesArray);
+#endif
+
+    /* Write the OFDM power per rate set */
+    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
+        POW_SM(ratesArray[rate18mb], 24)
+          | POW_SM(ratesArray[rate12mb], 16)
+          | POW_SM(ratesArray[rate9mb], 8)
+          | POW_SM(ratesArray[rate6mb], 0)
+    );
+    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
+        POW_SM(ratesArray[rate54mb], 24)
+          | POW_SM(ratesArray[rate48mb], 16)
+          | POW_SM(ratesArray[rate36mb], 8)
+          | POW_SM(ratesArray[rate24mb], 0)
+    );
+
+    if (IS_CHAN_2GHZ(chan)) {
+        /* Write the CCK power per rate set */
+        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
+            POW_SM(ratesArray[rate2s], 24)
+              | POW_SM(ratesArray[rate2l],  16)
+              | POW_SM(ratesArray[rateXr],  8) /* XR target power */
+              | POW_SM(ratesArray[rate1l],   0)
+        );
+        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
+            POW_SM(ratesArray[rate11s], 24)
+              | POW_SM(ratesArray[rate11l], 16)
+              | POW_SM(ratesArray[rate5_5s], 8)
+              | POW_SM(ratesArray[rate5_5l], 0)
+        );
+    HALDEBUG(ah, HAL_DEBUG_RESET,
+	"%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
+	    __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
+	    OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 
+    }
+
+    /* Write the HT20 power per rate set */
+    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
+        POW_SM(ratesArray[rateHt20_3], 24)
+          | POW_SM(ratesArray[rateHt20_2], 16)
+          | POW_SM(ratesArray[rateHt20_1], 8)
+          | POW_SM(ratesArray[rateHt20_0], 0)
+    );
+    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
+        POW_SM(ratesArray[rateHt20_7], 24)
+          | POW_SM(ratesArray[rateHt20_6], 16)
+          | POW_SM(ratesArray[rateHt20_5], 8)
+          | POW_SM(ratesArray[rateHt20_4], 0)
+    );
+
+    if (IS_CHAN_HT40(chan)) {
+        /* Write the HT40 power per rate set */
+	/* Correct PAR difference between HT40 and HT20/LEGACY */
+        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
+            POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
+              | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
+              | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
+              | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
+        );
+        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
+            POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
+              | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
+              | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
+              | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
+        );
+        /* Write the Dup/Ext 40 power per rate set */
+        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
+            POW_SM(ratesArray[rateExtOfdm], 24)
+              | POW_SM(ratesArray[rateExtCck], 16)
+              | POW_SM(ratesArray[rateDupOfdm], 8)
+              | POW_SM(ratesArray[rateDupCck], 0)
+        );
+    }
+
+    /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */
+    OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
+        POW_SM(pModal->pwrDecreaseFor3Chain, 6)
+          | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
+    );
+    return AH_TRUE;
+#undef POW_SM
+#undef N
+}
+
+/*
+ * Exported call to check for a recent gain reading and return
+ * the current state of the thermal calibration gain engine.
+ */
+HAL_RFGAIN
+ar5416GetRfgain(struct ath_hal *ah)
+{
+	return HAL_RFGAIN_INACTIVE;
+}
+
+/*
+ * Places all of hardware into reset
+ */
+HAL_BOOL
+ar5416Disable(struct ath_hal *ah)
+{
+	if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
+		return AH_FALSE;
+	return ar5416SetResetReg(ah, HAL_RESET_COLD);
+}
+
+/*
+ * Places the PHY and Radio chips into reset.  A full reset
+ * must be called to leave this state.  The PCI/MAC/PCU are
+ * not placed into reset as we must receive interrupt to
+ * re-enable the hardware.
+ */
+HAL_BOOL
+ar5416PhyDisable(struct ath_hal *ah)
+{
+	return ar5416SetResetReg(ah, HAL_RESET_WARM);
+}
+
+/*
+ * Write the given reset bit mask into the reset register
+ */
+HAL_BOOL
+ar5416SetResetReg(struct ath_hal *ah, uint32_t type)
+{
+	/*
+	 * Set force wake
+	 */
+	OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
+	     AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
+
+	switch (type) {
+	case HAL_RESET_POWER_ON:
+		return ar5416SetResetPowerOn(ah);
+		break;
+	case HAL_RESET_WARM:
+	case HAL_RESET_COLD:
+		return ar5416SetReset(ah, type);
+		break;
+	default:
+		return AH_FALSE;
+	}
+}
+
+static HAL_BOOL
+ar5416SetResetPowerOn(struct ath_hal *ah)
+{
+    /* Power On Reset (Hard Reset) */
+
+    /*
+     * Set force wake
+     *	
+     * If the MAC was running, previously calling
+     * reset will wake up the MAC but it may go back to sleep
+     * before we can start polling. 
+     * Set force wake  stops that 
+     * This must be called before initiating a hard reset.
+     */
+    OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
+            AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);    
+
+    /*
+     * RTC reset and clear
+     */
+    OS_REG_WRITE(ah, AR_RTC_RESET, 0);
+    OS_DELAY(20);
+    OS_REG_WRITE(ah, AR_RTC_RESET, 1);
+
+    /*
+     * Poll till RTC is ON
+     */
+    if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) {
+        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__);
+        return AH_FALSE;
+    }
+
+    return ar5416SetReset(ah, HAL_RESET_COLD);
+}
+
+static HAL_BOOL
+ar5416SetReset(struct ath_hal *ah, int type)
+{
+    uint32_t tmpReg;
+
+    /*
+     * Force wake
+     */
+    OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
+	AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
+
+    /*
+     * Reset AHB
+     */
+    tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+    if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
+	OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+	OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
+    } else {
+	OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
+    }
+
+    /*
+     * Set Mac(BB,Phy) Warm Reset
+     */
+    switch (type) {
+    case HAL_RESET_WARM:
+            OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM);
+            break;
+        case HAL_RESET_COLD:
+            OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM|AR_RTC_RC_MAC_COLD);
+            break;
+        default:
+            HALASSERT(0);
+            break;
+    }
+
+    /*
+     * Clear resets and force wakeup
+     */
+    OS_REG_WRITE(ah, AR_RTC_RC, 0);
+    if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
+        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__);
+        return AH_FALSE;
+    }
+
+    /* Clear AHB reset */
+    OS_REG_WRITE(ah, AR_RC, 0);
+
+   /* Set register and descriptor swapping on 
+    * Bigendian platforms on cold reset 
+    */
+#ifdef __BIG_ENDIAN__
+    if (type == HAL_RESET_COLD) {
+    		uint32_t	mask;
+		
+		HALDEBUG(ah, HAL_DEBUG_RESET,
+		    "%s Applying descriptor swap\n", __func__);
+
+		mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG;
+#ifndef AH_NEED_DESC_SWAP
+		mask |= AR_CFG_SWTD;
+#endif
+		OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
+	}
+#endif
+
+    ar5416InitPLL(ah, AH_NULL);
+
+    return AH_TRUE;
+}
+
+#ifndef IS_5GHZ_FAST_CLOCK_EN
+#define	IS_5GHZ_FAST_CLOCK_EN(ah, chan)	AH_FALSE
+#endif
+
+static void
+ar5416InitPLL(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	uint32_t pll;
+
+	if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
+		pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
+
+		if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) {
+			pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
+		} else if (chan && IS_CHAN_QUARTER_RATE(chan)) {
+			pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
+		}
+		if (chan != AH_NULL && IS_CHAN_5GHZ(chan)) {
+			pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
+
+			/*
+			 * PLL WAR for Merlin 2.0/2.1
+			 * When doing fast clock, set PLL to 0x142c
+			 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 
+			 */
+			if (AR_SREV_MERLIN_20(ah)) {
+				if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
+					pll = 0x142c;
+				} else {
+					pll = 0x2850;
+				}
+			}
+		} else {
+			pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
+		}
+	} else if (AR_SREV_SOWL_10_OR_LATER(ah)) {
+		pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
+
+		if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) {
+			pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
+		} else if (chan && IS_CHAN_QUARTER_RATE(chan)) {
+			pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
+		}
+		if (chan != AH_NULL && IS_CHAN_5GHZ(chan)) {
+			pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
+		} else {
+			pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
+		}
+	} else {
+		pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
+
+		if (chan != AH_NULL && IS_CHAN_HALF_RATE(chan)) {
+			pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
+		} else if (chan != AH_NULL && IS_CHAN_QUARTER_RATE(chan)) {
+			pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
+		}
+		if (chan != AH_NULL && IS_CHAN_5GHZ(chan)) {
+			pll |= SM(0xa, AR_RTC_PLL_DIV);
+		} else {
+			pll |= SM(0xb, AR_RTC_PLL_DIV);
+		}
+	}
+	OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+
+	/* TODO:
+	* For multi-band owl, switch between bands by reiniting the PLL.
+	*/
+
+	OS_DELAY(RTC_PLL_SETTLE_DELAY);
+
+	OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
+}
+
+/*
+ * Read EEPROM header info and program the device for correct operation
+ * given the channel value.
+ */
+static HAL_BOOL
+ar5416SetBoardValues(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
+{
+    const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
+    const struct ar5416eeprom *eep = &ee->ee_base;
+    const MODAL_EEP_HEADER *pModal;
+    int			i, regChainOffset;
+    uint8_t		txRxAttenLocal;    /* workaround for eeprom versions <= 14.2 */
+
+    HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
+    pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
+
+    txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;    /* workaround for eeprom versions <= 14.2 */
+
+    OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
+    for (i = 0; i < AR5416_MAX_CHAINS; i++) { 
+	   if (AR_SREV_MERLIN(ah)) {
+		if (i >= 2) break;
+	   }
+       	   if (AR_SREV_OWL_20_OR_LATER(ah) &&
+            (AH5416(ah)->ah_rx_chainmask == 0x5 ||
+	     AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
+            /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 
+             * only chains 0 and 2 populated 
+             */
+            regChainOffset = (i == 1) ? 0x2000 : 0x1000;
+        } else {
+            regChainOffset = i * 0x1000;
+        }
+
+        OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
+        OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 
+        	(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
+        	~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
+        	SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
+        	SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
+
+        /*
+         * Large signal upgrade.
+	 * XXX update
+         */
+
+        if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
+            OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, 
+		(OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
+			SM(IS_EEP_MINOR_V3(ah)  ? pModal->txRxAttenCh[i] : txRxAttenLocal,
+				AR_PHY_RXGAIN_TXRX_ATTEN));
+
+            OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 
+	    	(OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
+			SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
+        }
+    }
+
+    OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
+    OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
+    OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
+    OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
+        SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
+        | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
+        | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
+        | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
+
+    OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
+
+    if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
+	OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
+	    pModal->thresh62);
+	OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
+	    pModal->thresh62);
+    } else {
+	OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
+	    pModal->thresh62);
+	OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62,
+	    pModal->thresh62);
+    }
+    
+    /* Minor Version Specific application */
+    if (IS_EEP_MINOR_V2(ah)) {
+        OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,  AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
+        OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,  AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);    
+    }	
+    
+    if (IS_EEP_MINOR_V3(ah)) {
+	if (IS_CHAN_HT40(chan)) {
+		/* Overwrite switch settling with HT40 value */
+		OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
+	}
+	
+        if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
+            (  AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
+            /* Reg Offsets are swapped for logical mapping */
+		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
+			SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
+			SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
+			SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
+			SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+        } else {
+		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
+			SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
+			SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
+			SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+		OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
+			SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+        }
+        OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
+        OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
+    }
+    return AH_TRUE;
+}
+
+/*
+ * Helper functions common for AP/CB/XB
+ */
+
+/*
+ * ar5416SetPowerPerRateTable
+ *
+ * Sets the transmit power in the baseband for the given
+ * operating channel and mode.
+ */
+static HAL_BOOL
+ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
+                           HAL_CHANNEL_INTERNAL *chan,
+                           int16_t *ratesArray, uint16_t cfgCtl,
+                           uint16_t AntennaReduction, 
+                           uint16_t twiceMaxRegulatoryPower,
+                           uint16_t powerLimit)
+{
+#define	N(a)	(sizeof(a)/sizeof(a[0]))
+/* Local defines to distinguish between extension and control CTL's */
+#define EXT_ADDITIVE (0x8000)
+#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
+#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
+#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
+
+	uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+	int i;
+	int16_t  twiceLargestAntenna;
+	CAL_CTL_DATA *rep;
+	CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
+	CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
+	CAL_TARGET_POWER_HT  targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
+	int16_t scaledPower, minCtlPower;
+
+#define SUB_NUM_CTL_MODES_AT_5G_40 2   /* excluding HT40, EXT-OFDM */
+#define SUB_NUM_CTL_MODES_AT_2G_40 3   /* excluding HT40, EXT-OFDM, EXT-CCK */
+	static const uint16_t ctlModesFor11a[] = {
+	   CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
+	};
+	static const uint16_t ctlModesFor11g[] = {
+	   CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+	};
+	const uint16_t *pCtlMode;
+	uint16_t numCtlModes, ctlMode, freq;
+	CHAN_CENTERS centers;
+
+	ar5416GetChannelCenters(ah,  chan, &centers);
+
+	/* Compute TxPower reduction due to Antenna Gain */
+
+	twiceLargestAntenna = AH_MAX(AH_MAX(pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[0],
+					pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
+					pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
+#if 0
+	/* Turn it back on if we need to calculate per chain antenna gain reduction */
+	/* Use only if the expected gain > 6dbi */
+	/* Chain 0 is always used */
+	twiceLargestAntenna = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[0];
+
+	/* Look at antenna gains of Chains 1 and 2 if the TX mask is set */
+	if (ahp->ah_tx_chainmask & 0x2)
+		twiceLargestAntenna = AH_MAX(twiceLargestAntenna,
+			pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
+
+	if (ahp->ah_tx_chainmask & 0x4)
+		twiceLargestAntenna = AH_MAX(twiceLargestAntenna,
+			pEepData->modalHeader[IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
+#endif
+	twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);
+
+	/* XXX setup for 5212 use (really used?) */
+	ath_hal_eepromSet(ah,
+	    IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5,
+	    twiceLargestAntenna);
+
+	/* 
+	 * scaledPower is the minimum of the user input power level and
+	 * the regulatory allowed power level
+	 */
+	scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
+
+	/* Reduce scaled Power by number of chains active to get to per chain tx power level */
+	/* TODO: better value than these? */
+	switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) {
+	case 1:
+		break;
+	case 2:
+		scaledPower -= pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
+		break;
+	case 3:
+		scaledPower -= pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
+		break;
+	default:
+		return AH_FALSE; /* Unsupported number of chains */
+	}
+
+	scaledPower = AH_MAX(0, scaledPower);
+
+	/* Get target powers from EEPROM - our baseline for TX Power */
+	if (IS_CHAN_2GHZ(chan)) {
+		/* Setup for CTL modes */
+		numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
+		pCtlMode = ctlModesFor11g;
+
+		ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPowerCck,
+				AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
+		ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower2G,
+				AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
+		ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower2GHT20,
+				AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
+
+		if (IS_CHAN_HT40(chan)) {
+			numCtlModes = N(ctlModesFor11g);    /* All 2G CTL's */
+
+			ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower2GHT40,
+				AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
+			/* Get target powers for extension channels */
+			ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPowerCck,
+				AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
+			ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower2G,
+				AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
+		}
+	} else {
+		/* Setup for CTL modes */
+		numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */
+		pCtlMode = ctlModesFor11a;
+
+		ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower5G,
+				AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
+		ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower5GHT20,
+				AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
+
+		if (IS_CHAN_HT40(chan)) {
+			numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */
+
+			ar5416GetTargetPowers(ah,  chan, pEepData->calTargetPower5GHT40,
+				AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
+			ar5416GetTargetPowersLeg(ah,  chan, pEepData->calTargetPower5G,
+				AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
+		}
+	}
+
+	/*
+	 * For MIMO, need to apply regulatory caps individually across dynamically
+	 * running modes: CCK, OFDM, HT20, HT40
+	 *
+	 * The outer loop walks through each possible applicable runtime mode.
+	 * The inner loop walks through each ctlIndex entry in EEPROM.
+	 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
+	 *
+	 */
+	for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
+
+		HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
+								 (pCtlMode[ctlMode] == CTL_2GHT40);
+		if (isHt40CtlMode) {
+			freq = centers.ctl_center;
+		} else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
+			freq = centers.ext_center;
+		} else {
+			freq = centers.ctl_center;
+		}
+
+		/* walk through each CTL index stored in EEPROM */
+		for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
+			uint16_t twiceMinEdgePower;
+
+			/* compare test group from regulatory channel list with test mode from pCtlMode list */
+			if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
+				(((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 
+				 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
+				rep = &(pEepData->ctlData[i]);
+				twiceMinEdgePower = ar5416GetMaxEdgePower(freq,
+							rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],
+							IS_CHAN_2GHZ(chan));
+				if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
+					/* Find the minimum of all CTL edge powers that apply to this channel */
+					twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
+				} else {
+					/* specific */
+					twiceMaxEdgePower = twiceMinEdgePower;
+					break;
+				}
+			}
+		}
+		minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower);
+		/* Apply ctl mode to correct target power set */
+		switch(pCtlMode[ctlMode]) {
+		case CTL_11B:
+			for (i = 0; i < N(targetPowerCck.tPow2x); i++) {
+				targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower);
+			}
+			break;
+		case CTL_11A:
+		case CTL_11G:
+			for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) {
+				targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower);
+			}
+			break;
+		case CTL_5GHT20:
+		case CTL_2GHT20:
+			for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
+				targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower);
+			}
+			break;
+		case CTL_11B_EXT:
+			targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower);
+			break;
+		case CTL_11A_EXT:
+		case CTL_11G_EXT:
+			targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower);
+			break;
+		case CTL_5GHT40:
+		case CTL_2GHT40:
+			for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
+				targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower);
+			}
+			break;
+		default:
+			return AH_FALSE;
+			break;
+		}
+	} /* end ctl mode checking */
+
+	/* Set rates Array from collected data */
+	ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
+	ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
+	ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
+	ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
+	ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
+
+	for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
+		ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
+	}
+
+	if (IS_CHAN_2GHZ(chan)) {
+		ratesArray[rate1l]  = targetPowerCck.tPow2x[0];
+		ratesArray[rate2s] = ratesArray[rate2l]  = targetPowerCck.tPow2x[1];
+		ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
+		ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
+	}
+	if (IS_CHAN_HT40(chan)) {
+		for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
+			ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
+		}
+		ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
+		ratesArray[rateDupCck]  = targetPowerHt40.tPow2x[0];
+		ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
+		if (IS_CHAN_2GHZ(chan)) {
+			ratesArray[rateExtCck]  = targetPowerCckExt.tPow2x[0];
+		}
+	}
+	return AH_TRUE;
+#undef EXT_ADDITIVE
+#undef CTL_11A_EXT
+#undef CTL_11G_EXT
+#undef CTL_11B_EXT
+#undef SUB_NUM_CTL_MODES_AT_5G_40
+#undef SUB_NUM_CTL_MODES_AT_2G_40
+#undef N
+}
+
+/**************************************************************************
+ * fbin2freq
+ *
+ * Get channel value from binary representation held in eeprom
+ * RETURNS: the frequency in MHz
+ */
+static uint16_t
+fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
+{
+    /*
+     * Reserved value 0xFF provides an empty definition both as
+     * an fbin and as a frequency - do not convert
+     */
+    if (fbin == AR5416_BCHAN_UNUSED) {
+        return fbin;
+    }
+
+    return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
+}
+
+/*
+ * ar5416GetMaxEdgePower
+ *
+ * Find the maximum conformance test limit for the given channel and CTL info
+ */
+static uint16_t
+ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
+{
+    uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+    int      i;
+
+    /* Get the edge power */
+    for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
+        /*
+         * If there's an exact channel match or an inband flag set
+         * on the lower channel use the given rdEdgePower
+         */
+        if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
+            twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
+            break;
+        } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) {
+            if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) {
+                twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER);
+            }
+            /* Leave loop - no more affecting edges possible in this monotonic increasing list */
+            break;
+        }
+    }
+    HALASSERT(twiceMaxEdgePower > 0);
+    return twiceMaxEdgePower;
+}
+
+/**************************************************************
+ * ar5416GetTargetPowers
+ *
+ * Return the rates of target power for the given target power table
+ * channel, and number of channels
+ */
+static void
+ar5416GetTargetPowers(struct ath_hal *ah,  HAL_CHANNEL_INTERNAL *chan,
+                      CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels,
+                      CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates,
+                      HAL_BOOL isHt40Target)
+{
+    uint16_t clo, chi;
+    int i;
+    int matchIndex = -1, lowIndex = -1;
+    uint16_t freq;
+    CHAN_CENTERS centers;
+
+    ar5416GetChannelCenters(ah,  chan, &centers);
+    freq = isHt40Target ? centers.synth_center : centers.ctl_center;
+
+    /* Copy the target powers into the temp channel list */
+    if (freq <= fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
+        matchIndex = 0;
+    } else {
+        for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
+            if (freq == fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) {
+                matchIndex = i;
+                break;
+            } else if ((freq < fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) &&
+                       (freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan))))
+            {
+                lowIndex = i - 1;
+                break;
+            }
+        }
+        if ((matchIndex == -1) && (lowIndex == -1)) {
+            HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan)));
+            matchIndex = i - 1;
+        }
+    }
+
+    if (matchIndex != -1) {
+        OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower));
+    } else {
+        HALASSERT(lowIndex != -1);
+        /*
+         * Get the lower and upper channels, target powers,
+         * and interpolate between them.
+         */
+        clo = fbin2freq(powInfo[lowIndex].bChannel, IS_CHAN_2GHZ(chan));
+        chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IS_CHAN_2GHZ(chan));
+
+        for (i = 0; i < numRates; i++) {
+            pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi,
+                                   powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]);
+        }
+    }
+}
+/**************************************************************
+ * ar5416GetTargetPowersLeg
+ *
+ * Return the four rates of target power for the given target power table
+ * channel, and number of channels
+ */
+static void
+ar5416GetTargetPowersLeg(struct ath_hal *ah, 
+                         HAL_CHANNEL_INTERNAL *chan,
+                         CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels,
+                         CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates,
+			 HAL_BOOL isExtTarget)
+{
+    uint16_t clo, chi;
+    int i;
+    int matchIndex = -1, lowIndex = -1;
+    uint16_t freq;
+    CHAN_CENTERS centers;
+
+    ar5416GetChannelCenters(ah,  chan, &centers);
+    freq = (isExtTarget) ? centers.ext_center :centers.ctl_center;
+
+    /* Copy the target powers into the temp channel list */
+    if (freq <= fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
+        matchIndex = 0;
+    } else {
+        for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
+            if (freq == fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) {
+                matchIndex = i;
+                break;
+            } else if ((freq < fbin2freq(powInfo[i].bChannel, IS_CHAN_2GHZ(chan))) &&
+                       (freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan))))
+            {
+                lowIndex = i - 1;
+                break;
+            }
+        }
+        if ((matchIndex == -1) && (lowIndex == -1)) {
+            HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IS_CHAN_2GHZ(chan)));
+            matchIndex = i - 1;
+        }
+    }
+
+    if (matchIndex != -1) {
+        OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower));
+    } else {
+        HALASSERT(lowIndex != -1);
+        /*
+         * Get the lower and upper channels, target powers,
+         * and interpolate between them.
+         */
+        clo = fbin2freq(powInfo[lowIndex].bChannel, IS_CHAN_2GHZ(chan));
+        chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IS_CHAN_2GHZ(chan));
+
+        for (i = 0; i < numRates; i++) {
+            pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi,
+                                   powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]);
+        }
+    }
+}
+
+/**************************************************************
+ * ar5416SetPowerCalTable
+ *
+ * Pull the PDADC piers from cal data and interpolate them across the given
+ * points as well as from the nearest pier(s) to get a power detector
+ * linear voltage to power level table.
+ */
+static HAL_BOOL
+ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, HAL_CHANNEL_INTERNAL *chan, int16_t *pTxPowerIndexOffset)
+{
+    CAL_DATA_PER_FREQ *pRawDataset;
+    uint8_t  *pCalBChans = AH_NULL;
+    uint16_t pdGainOverlap_t2;
+    static uint8_t  pdadcValues[AR5416_NUM_PDADC_VALUES];
+    uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
+    uint16_t numPiers, i, j;
+    int16_t  tMinCalPower;
+    uint16_t numXpdGain, xpdMask;
+    uint16_t xpdGainValues[AR5416_NUM_PD_GAINS];
+    uint32_t reg32, regOffset, regChainOffset;
+
+    ath_hal_memzero(xpdGainValues, sizeof(xpdGainValues));
+    
+    xpdMask = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].xpdGain;
+
+    if (IS_EEP_MINOR_V2(ah)) {
+        pdGainOverlap_t2 = pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pdGainOverlap;
+    } else { 
+    	pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
+    }
+
+    if (IS_CHAN_2GHZ(chan)) {
+        pCalBChans = pEepData->calFreqPier2G;
+        numPiers = AR5416_NUM_2G_CAL_PIERS;
+    } else {
+        pCalBChans = pEepData->calFreqPier5G;
+        numPiers = AR5416_NUM_5G_CAL_PIERS;
+    }
+
+    numXpdGain = 0;
+    /* Calculate the value of xpdgains from the xpdGain Mask */
+    for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+        if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
+            if (numXpdGain >= AR5416_NUM_PD_GAINS) {
+                HALASSERT(0);
+                break;
+            }
+            xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i);
+            numXpdGain++;
+        }
+    }
+    
+    /* Write the detector gain biases and their number */
+    OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & 
+    	~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | 
+	SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
+	SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2],  AR_PHY_TPCRG1_PD_GAIN_3));
+
+    for (i = 0; i < AR5416_MAX_CHAINS; i++) {
+
+            if (AR_SREV_OWL_20_OR_LATER(ah) && 
+            ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
+            /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 
+             * only chains 0 and 2 populated 
+             */
+            regChainOffset = (i == 1) ? 0x2000 : 0x1000;
+        } else {
+            regChainOffset = i * 0x1000;
+        }
+
+        if (pEepData->baseEepHeader.txMask & (1 << i)) {
+            if (IS_CHAN_2GHZ(chan)) {
+                pRawDataset = pEepData->calPierData2G[i];
+            } else {
+                pRawDataset = pEepData->calPierData5G[i];
+            }
+
+            ar5416GetGainBoundariesAndPdadcs(ah,  chan, pRawDataset,
+                                             pCalBChans, numPiers,
+                                             pdGainOverlap_t2,
+                                             &tMinCalPower, gainBoundaries,
+                                             pdadcValues, numXpdGain);
+
+            if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
+                /*
+                 * Note the pdadc table may not start at 0 dBm power, could be
+                 * negative or greater than 0.  Need to offset the power
+                 * values by the amount of minPower for griffin
+                 */
+
+                OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
+                     SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
+                     SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)  |
+                     SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)  |
+                     SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)  |
+                     SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
+            }
+
+            /* Write the power values into the baseband power table */
+            regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
+
+            for (j = 0; j < 32; j++) {
+                reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0)  |
+                    ((pdadcValues[4*j + 1] & 0xFF) << 8)  |
+                    ((pdadcValues[4*j + 2] & 0xFF) << 16) |
+                    ((pdadcValues[4*j + 3] & 0xFF) << 24) ;
+                OS_REG_WRITE(ah, regOffset, reg32);
+
+#ifdef PDADC_DUMP
+		ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n",
+			       i,
+			       4*j, pdadcValues[4*j],
+			       4*j+1, pdadcValues[4*j + 1],
+			       4*j+2, pdadcValues[4*j + 2],
+			       4*j+3, pdadcValues[4*j + 3]);
+#endif
+                regOffset += 4;
+            }
+        }
+    }
+    *pTxPowerIndexOffset = 0;
+
+    return AH_TRUE;
+}
+
+/**************************************************************
+ * ar5416GetGainBoundariesAndPdadcs
+ *
+ * Uses the data points read from EEPROM to reconstruct the pdadc power table
+ * Called by ar5416SetPowerCalTable only.
+ */
+static void
+ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 
+                                 HAL_CHANNEL_INTERNAL *chan, CAL_DATA_PER_FREQ *pRawDataSet,
+                                 uint8_t * bChans,  uint16_t availPiers,
+                                 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
+                                 uint8_t * pPDADCValues, uint16_t numXpdGains)
+{
+
+    int       i, j, k;
+    int16_t   ss;         /* potentially -ve index for taking care of pdGainOverlap */
+    uint16_t  idxL, idxR, numPiers; /* Pier indexes */
+
+    /* filled out Vpd table for all pdGains (chanL) */
+    static uint8_t   vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+    /* filled out Vpd table for all pdGains (chanR) */
+    static uint8_t   vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+    /* filled out Vpd table for all pdGains (interpolated) */
+    static uint8_t   vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+    uint8_t   *pVpdL, *pVpdR, *pPwrL, *pPwrR;
+    uint8_t   minPwrT4[AR5416_NUM_PD_GAINS];
+    uint8_t   maxPwrT4[AR5416_NUM_PD_GAINS];
+    int16_t   vpdStep;
+    int16_t   tmpVal;
+    uint16_t  sizeCurrVpdTable, maxIndex, tgtIndex;
+    HAL_BOOL    match;
+    int16_t  minDelta = 0;
+    CHAN_CENTERS centers;
+
+    ar5416GetChannelCenters(ah, chan, &centers);
+
+    /* Trim numPiers for the number of populated channel Piers */
+    for (numPiers = 0; numPiers < availPiers; numPiers++) {
+        if (bChans[numPiers] == AR5416_BCHAN_UNUSED) {
+            break;
+        }
+    }
+
+    /* Find pier indexes around the current channel */
+    match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
+			bChans, numPiers, &idxL, &idxR);
+
+    if (match) {
+        /* Directly fill both vpd tables from the matching index */
+        for (i = 0; i < numXpdGains; i++) {
+            minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
+            maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
+            ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i],
+                               pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
+        }
+    } else {
+        for (i = 0; i < numXpdGains; i++) {
+            pVpdL = pRawDataSet[idxL].vpdPdg[i];
+            pPwrL = pRawDataSet[idxL].pwrPdg[i];
+            pVpdR = pRawDataSet[idxR].vpdPdg[i];
+            pPwrR = pRawDataSet[idxR].pwrPdg[i];
+
+            /* Start Vpd interpolation from the max of the minimum powers */
+            minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
+
+            /* End Vpd interpolation from the min of the max powers */
+            maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
+            HALASSERT(maxPwrT4[i] > minPwrT4[i]);
+
+            /* Fill pier Vpds */
+            ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]);
+            ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]);
+
+            /* Interpolate the final vpd */
+            for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
+                vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
+                    bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
+            }
+        }
+    }
+    *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
+
+    k = 0; /* index for the final table */
+    for (i = 0; i < numXpdGains; i++) {
+        if (i == (numXpdGains - 1)) {
+            pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2);
+        } else {
+            pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
+        }
+
+        pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
+
+	/* NB: only applies to owl 1.0 */
+        if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) {
+	    /*
+             * fix the gain delta, but get a delta that can be applied to min to
+             * keep the upper power values accurate, don't think max needs to
+             * be adjusted because should not be at that area of the table?
+	     */
+            minDelta = pPdGainBoundaries[0] - 23;
+            pPdGainBoundaries[0] = 23;
+        }
+        else {
+            minDelta = 0;
+        }
+
+        /* Find starting index for this pdGain */
+        if (i == 0) {
+            ss = 0; /* for the first pdGain, start from index 0 */
+        } else {
+	    /* need overlap entries extrapolated below. */
+            ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
+        }
+        vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
+        vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+        /*
+         *-ve ss indicates need to extrapolate data below for this pdGain
+         */
+        while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+            tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
+            pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
+            ss++;
+        }
+
+        sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
+        tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
+        maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
+
+        while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+            pPDADCValues[k++] = vpdTableI[i][ss++];
+        }
+
+        vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);
+        vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+        /*
+         * for last gain, pdGainBoundary == Pmax_t2, so will
+         * have to extrapolate
+         */
+        if (tgtIndex > maxIndex) {  /* need to extrapolate above */
+            while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
+                          (ss - maxIndex +1) * vpdStep));
+                pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal);
+                ss++;
+            }
+        }               /* extrapolated above */
+    }                   /* for all pdGainUsed */
+
+    /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */
+    while (i < AR5416_PD_GAINS_IN_MASK) {
+        pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
+        i++;
+    }
+
+    while (k < AR5416_NUM_PDADC_VALUES) {
+        pPDADCValues[k] = pPDADCValues[k-1];
+        k++;
+    }
+    return;
+}
+
+/**************************************************************
+ * getLowerUppderIndex
+ *
+ * Return indices surrounding the value in sorted integer lists.
+ * Requirement: the input list must be monotonically increasing
+ *     and populated up to the list size
+ * Returns: match is set if an index in the array matches exactly
+ *     or a the target is before or after the range of the array.
+ */
+HAL_BOOL
+getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize,
+                   uint16_t *indexL, uint16_t *indexR)
+{
+    uint16_t i;
+
+    /*
+     * Check first and last elements for beyond ordered array cases.
+     */
+    if (target <= pList[0]) {
+        *indexL = *indexR = 0;
+        return AH_TRUE;
+    }
+    if (target >= pList[listSize-1]) {
+        *indexL = *indexR = (uint16_t)(listSize - 1);
+        return AH_TRUE;
+    }
+
+    /* look for value being near or between 2 values in list */
+    for (i = 0; i < listSize - 1; i++) {
+        /*
+         * If value is close to the current value of the list
+         * then target is not between values, it is one of the values
+         */
+        if (pList[i] == target) {
+            *indexL = *indexR = i;
+            return AH_TRUE;
+        }
+        /*
+         * Look for value being between current value and next value
+         * if so return these 2 values
+         */
+        if (target < pList[i + 1]) {
+            *indexL = i;
+            *indexR = (uint16_t)(i + 1);
+            return AH_FALSE;
+        }
+    }
+    HALASSERT(0);
+    return AH_FALSE;
+}
+
+/**************************************************************
+ * ar5416FillVpdTable
+ *
+ * Fill the Vpdlist for indices Pmax-Pmin
+ * Note: pwrMin, pwrMax and Vpdlist are all in dBm * 4
+ */
+static HAL_BOOL
+ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList,
+                   uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
+{
+    uint16_t  i, k;
+    uint8_t   currPwr = pwrMin;
+    uint16_t  idxL, idxR;
+
+    HALASSERT(pwrMax > pwrMin);
+    for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
+        getLowerUpperIndex(currPwr, pPwrList, numIntercepts,
+                           &(idxL), &(idxR));
+        if (idxR < 1)
+            idxR = 1;           /* extrapolate below */
+        if (idxL == numIntercepts - 1)
+            idxL = (uint16_t)(numIntercepts - 2);   /* extrapolate above */
+        if (pPwrList[idxL] == pPwrList[idxR])
+            k = pVpdList[idxL];
+        else
+            k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
+                  (pPwrList[idxR] - pPwrList[idxL]) );
+        HALASSERT(k < 256);
+        pRetVpdList[i] = (uint8_t)k;
+        currPwr += 2;               /* half dB steps */
+    }
+
+    return AH_TRUE;
+}
+
+/**************************************************************************
+ * interpolate
+ *
+ * Returns signed interpolated or the scaled up interpolated value
+ */
+static int16_t
+interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
+            int16_t targetLeft, int16_t targetRight)
+{
+    int16_t rv;
+
+    if (srcRight == srcLeft) {
+        rv = targetLeft;
+    } else {
+        rv = (int16_t)( ((target - srcLeft) * targetRight +
+              (srcRight - target) * targetLeft) / (srcRight - srcLeft) );
+    }
+    return rv;
+}
+
+static void
+ar5416Set11nRegs(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+	uint32_t phymode;
+	HAL_HT_MACMODE macmode;		/* MAC - 20/40 mode */
+
+	if (!IS_CHAN_HT(chan))
+		return;
+
+	/* Enable 11n HT, 20 MHz */
+	phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
+		| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
+
+	/* Configure baseband for dynamic 20/40 operation */
+	if (IS_CHAN_HT40(chan)) {
+		phymode |= AR_PHY_FC_DYN2040_EN | AR_PHY_FC_SHORT_GI_40;
+
+		/* Configure control (primary) channel at +-10MHz */
+		if ((chan->channelFlags & CHANNEL_HT40PLUS))
+			phymode |= AR_PHY_FC_DYN2040_PRI_CH;
+#if 0
+		/* Configure 20/25 spacing */
+		if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25)
+			phymode |= AR_PHY_FC_DYN2040_EXT_CH;
+#endif
+		macmode = HAL_HT_MACMODE_2040;
+	} else
+		macmode = HAL_HT_MACMODE_20;
+	OS_REG_WRITE(ah, AR_PHY_TURBO, phymode);
+
+	/* Configure MAC for 20/40 operation */
+	ar5416Set11nMac2040(ah, macmode);
+
+	/* global transmit timeout (25 TUs default)*/
+	/* XXX - put this elsewhere??? */
+	OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ;
+
+	/* carrier sense timeout */
+	OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC);
+	OS_REG_WRITE(ah, AR_CST, 1 << AR_CST_TIMEOUT_LIMIT_S);
+}
+
+void
+ar5416GetChannelCenters(struct ath_hal *ah,
+	HAL_CHANNEL_INTERNAL *chan, CHAN_CENTERS *centers)
+{
+	centers->ctl_center = chan->channel;
+	centers->synth_center = chan->channel;
+	/*
+	 * In 20/40 phy mode, the center frequency is
+	 * "between" the control and extension channels.
+	 */
+	if (chan->channelFlags & CHANNEL_HT40PLUS) {
+		centers->synth_center += HT40_CHANNEL_CENTER_SHIFT;
+		centers->ext_center =
+		    centers->synth_center + HT40_CHANNEL_CENTER_SHIFT;
+	} else if (chan->channelFlags & CHANNEL_HT40MINUS) {
+		centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT;
+		centers->ext_center =
+		    centers->synth_center - HT40_CHANNEL_CENTER_SHIFT;
+	} else {
+		centers->ext_center = chan->channel;
+	}
+}
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_xmit.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_xmit.c
new file mode 100644
index 0000000..a0e2f14
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_xmit.c
@@ -0,0 +1,698 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416_xmit.c,v 1.9 2008/11/27 22:30:08 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_desc.h"
+#include "ah_internal.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+#include "ar5416/ar5416desc.h"
+
+/*
+ * Stop transmit on the specified queue
+ */
+HAL_BOOL
+ar5416StopTxDma(struct ath_hal *ah, u_int q)
+{
+#define	STOP_DMA_TIMEOUT	4000	/* us */
+#define	STOP_DMA_ITER		100	/* us */
+	u_int i;
+
+	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
+
+	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
+
+	OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
+	for (i = STOP_DMA_TIMEOUT/STOP_DMA_ITER; i != 0; i--) {
+		if (ar5212NumTxPending(ah, q) == 0)
+			break;
+		OS_DELAY(STOP_DMA_ITER);
+	}
+#ifdef AH_DEBUG
+	if (i == 0) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: queue %u DMA did not stop in 400 msec\n", __func__, q);
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", __func__,
+		    OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),
+		    OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q)));
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
+		    __func__, OS_REG_READ(ah, AR_QMISC(q)),
+		    OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
+		    OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
+	}
+#endif /* AH_DEBUG */
+
+	/* ar5416 and up can kill packets at the PCU level */
+	if (ar5212NumTxPending(ah, q)) {
+		uint32_t j;
+
+		HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
+		    "%s: Num of pending TX Frames %d on Q %d\n",
+		    __func__, ar5212NumTxPending(ah, q), q);
+
+		/* Kill last PCU Tx Frame */
+		/* TODO - save off and restore current values of Q1/Q2? */
+		for (j = 0; j < 2; j++) {
+			uint32_t tsfLow = OS_REG_READ(ah, AR_TSF_L32);
+			OS_REG_WRITE(ah, AR_QUIET2,
+			    SM(10, AR_QUIET2_QUIET_DUR));
+			OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
+			OS_REG_WRITE(ah, AR_NEXT_QUIET, tsfLow >> 10);
+			OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
+
+			if ((OS_REG_READ(ah, AR_TSF_L32)>>10) == (tsfLow>>10))
+				break;
+
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: TSF moved while trying to set quiet time "
+			    "TSF: 0x%08x\n", __func__, tsfLow);
+			HALASSERT(j < 1); /* TSF shouldn't count twice or reg access is taking forever */
+		}
+		
+		OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
+		
+		/* Allow the quiet mechanism to do its work */
+		OS_DELAY(200);
+		OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
+
+		/* Verify the transmit q is empty */
+		for (i = STOP_DMA_TIMEOUT/STOP_DMA_ITER; i != 0; i--) {
+			if (ar5212NumTxPending(ah, q) == 0)
+				break;
+			OS_DELAY(STOP_DMA_ITER);
+		}
+		if (i == 0) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: Failed to stop Tx DMA in %d msec after killing"
+			    " last frame\n", __func__, STOP_DMA_TIMEOUT / 1000);
+		}
+		OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
+	}
+
+	OS_REG_WRITE(ah, AR_Q_TXD, 0);
+	return (i != 0);
+#undef STOP_DMA_ITER
+#undef STOP_DMA_TIMEOUT
+}
+
+#define VALID_KEY_TYPES \
+        ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\
+         (1 << HAL_KEY_TYPE_AES)   | (1 << HAL_KEY_TYPE_TKIP))
+#define isValidKeyType(_t)      ((1 << (_t)) & VALID_KEY_TYPES)
+
+#define set11nTries(_series, _index) \
+        (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
+
+#define set11nRate(_series, _index) \
+        (SM((_series)[_index].Rate, AR_XmitRate##_index))
+
+#define set11nPktDurRTSCTS(_series, _index) \
+        (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\
+         ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS   ?\
+         AR_RTSCTSQual##_index : 0))
+
+#define set11nRateFlags(_series, _index) \
+        ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
+        |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \
+        |SM((_series)[_index].ChSel, AR_ChainSel##_index)
+
+/*
+ * Descriptor Access Functions
+ */
+
+#define VALID_PKT_TYPES \
+        ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
+         (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
+         (1<<HAL_PKT_TYPE_BEACON)|(1<<HAL_PKT_TYPE_AMPDU))
+#define isValidPktType(_t)      ((1<<(_t)) & VALID_PKT_TYPES)
+#define VALID_TX_RATES \
+        ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
+         (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
+         (1<<0x1d)|(1<<0x18)|(1<<0x1c))
+#define isValidTxRate(_r)       ((1<<(_r)) & VALID_TX_RATES)
+
+HAL_BOOL
+ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int pktLen,
+	u_int hdrLen,
+	HAL_PKT_TYPE type,
+	u_int txPower,
+	u_int txRate0, u_int txTries0,
+	u_int keyIx,
+	u_int antMode,
+	u_int flags,
+	u_int rtsctsRate,
+	u_int rtsctsDuration,
+	u_int compicvLen,
+	u_int compivLen,
+	u_int comp)
+{
+#define	RTSCTS	(HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
+	struct ar5416_desc *ads = AR5416DESC(ds);
+	struct ath_hal_5416 *ahp = AH5416(ah);
+
+	(void) hdrLen;
+
+	HALASSERT(txTries0 != 0);
+	HALASSERT(isValidPktType(type));
+	HALASSERT(isValidTxRate(txRate0));
+	HALASSERT((flags & RTSCTS) != RTSCTS);
+	/* XXX validate antMode */
+
+        txPower = (txPower + AH5212(ah)->ah_txPowerIndexOffset);
+        if (txPower > 63)
+		txPower = 63;
+
+	ads->ds_ctl0 = (pktLen & AR_FrameLen)
+		     | (txPower << AR_XmitPower_S)
+		     | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
+		     | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
+		     | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
+		     ;
+	ads->ds_ctl1 = (type << AR_FrameType_S)
+		     | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
+                     ;
+	ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0)
+		     | (flags & HAL_TXDESC_DURENA ? AR_DurUpdateEn : 0)
+		     ;
+	ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S)
+		     ;
+	ads->ds_ctl4 = 0;
+	ads->ds_ctl5 = 0;
+	ads->ds_ctl6 = 0;
+	ads->ds_ctl7 = SM(ahp->ah_tx_chainmask, AR_ChainSel0) 
+		     | SM(ahp->ah_tx_chainmask, AR_ChainSel1)
+		     | SM(ahp->ah_tx_chainmask, AR_ChainSel2) 
+		     | SM(ahp->ah_tx_chainmask, AR_ChainSel3)
+		     ;
+	ads->ds_ctl8 = 0;
+	ads->ds_ctl9 = (txPower << 24);		/* XXX? */
+	ads->ds_ctl10 = (txPower << 24);	/* XXX? */
+	ads->ds_ctl11 = (txPower << 24);	/* XXX? */
+	if (keyIx != HAL_TXKEYIX_INVALID) {
+		/* XXX validate key index */
+		ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
+		ads->ds_ctl0 |= AR_DestIdxValid;
+		ads->ds_ctl6 |= SM(ahp->ah_keytype[keyIx], AR_EncrType);
+	}
+	if (flags & RTSCTS) {
+		if (!isValidTxRate(rtsctsRate)) {
+			HALDEBUG(ah, HAL_DEBUG_ANY,
+			    "%s: invalid rts/cts rate 0x%x\n",
+			    __func__, rtsctsRate);
+			return AH_FALSE;
+		}
+		/* XXX validate rtsctsDuration */
+		ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
+			     | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
+			     ;
+		ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
+		ads->ds_ctl7 |= (rtsctsRate << AR_RTSCTSRate_S);
+	}
+	return AH_TRUE;
+#undef RTSCTS
+}
+
+HAL_BOOL
+ar5416SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int txRate1, u_int txTries1,
+	u_int txRate2, u_int txTries2,
+	u_int txRate3, u_int txTries3)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+
+	if (txTries1) {
+		HALASSERT(isValidTxRate(txRate1));
+		ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1);
+		ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
+	}
+	if (txTries2) {
+		HALASSERT(isValidTxRate(txRate2));
+		ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2);
+		ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
+	}
+	if (txTries3) {
+		HALASSERT(isValidTxRate(txRate3));
+		ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3);
+		ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
+	}
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
+	const struct ath_desc *ds0)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+
+	HALASSERT((segLen &~ AR_BufLen) == 0);
+
+	if (firstSeg) {
+		/*
+		 * First descriptor, don't clobber xmit control data
+		 * setup by ar5212SetupTxDesc.
+		 */
+		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
+	} else if (lastSeg) {		/* !firstSeg && lastSeg */
+		/*
+		 * Last descriptor in a multi-descriptor frame,
+		 * copy the multi-rate transmit parameters from
+		 * the first frame for processing on completion. 
+		 */
+		ads->ds_ctl0 = 0;
+		ads->ds_ctl1 = segLen;
+#ifdef AH_NEED_DESC_SWAP
+		ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
+		ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
+#else
+		ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
+		ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
+#endif
+	} else {			/* !firstSeg && !lastSeg */
+		/*
+		 * Intermediate descriptor in a multi-descriptor frame.
+		 */
+		ads->ds_ctl0 = 0;
+		ads->ds_ctl1 = segLen | AR_TxMore;
+		ads->ds_ctl2 = 0;
+		ads->ds_ctl3 = 0;
+	}
+	/* XXX only on last descriptor? */
+	OS_MEMZERO(ads->u.tx.status, sizeof(ads->u.tx.status));
+	return AH_TRUE;
+}
+
+#if 0
+
+HAL_BOOL
+ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int pktLen,
+	u_int hdrLen,
+	HAL_PKT_TYPE type,
+	u_int keyIx,
+	HAL_CIPHER cipher,
+	uint8_t delims,
+	u_int segLen,
+	HAL_BOOL firstSeg,
+	HAL_BOOL lastSeg)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+	uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
+
+	int isaggr = 0;
+	
+	(void) hdrLen;
+	(void) ah;
+
+	HALASSERT((segLen &~ AR_BufLen) == 0);
+
+	HALASSERT(isValidPktType(type));
+	if (type == HAL_PKT_TYPE_AMPDU) {
+		type = HAL_PKT_TYPE_NORMAL;
+		isaggr = 1;
+	}
+
+	if (!firstSeg) {
+		ath_hal_memzero(ds->ds_hw, AR5416_DESC_TX_CTL_SZ);
+	}
+
+	ads->ds_ctl0 = (pktLen & AR_FrameLen);
+	ads->ds_ctl1 = (type << AR_FrameType_S)
+			| (isaggr ? (AR_IsAggr | AR_MoreAggr) : 0);
+	ads->ds_ctl2 = 0;
+	ads->ds_ctl3 = 0;
+	if (keyIx != HAL_TXKEYIX_INVALID) {
+		/* XXX validate key index */
+		ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
+		ads->ds_ctl0 |= AR_DestIdxValid;
+	}
+
+	ads->ds_ctl6 = SM(keyType[cipher], AR_EncrType);
+	if (isaggr) {
+		ads->ds_ctl6 |= SM(delims, AR_PadDelim);
+	}
+
+	if (firstSeg) {
+		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
+	} else if (lastSeg) {           /* !firstSeg && lastSeg */
+		ads->ds_ctl0 = 0;
+		ads->ds_ctl1 |= segLen;
+	} else {                        /* !firstSeg && !lastSeg */
+		/*
+		 * Intermediate descriptor in a multi-descriptor frame.
+		 */
+		ads->ds_ctl0 = 0;
+		ads->ds_ctl1 |= segLen | AR_TxMore;
+	}
+	ds_txstatus[0] = ds_txstatus[1] = 0;
+	ds_txstatus[9] &= ~AR_TxDone;
+	
+	return AH_TRUE;
+}
+
+HAL_BOOL
+ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+	u_int aggrLen, u_int flags, u_int txPower,
+	u_int txRate0, u_int txTries0, u_int antMode,
+	u_int rtsctsRate, u_int rtsctsDuration)
+{
+#define RTSCTS  (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
+	struct ar5416_desc *ads = AR5416DESC(ds);
+	struct ath_hal_5212 *ahp = AH5212(ah);
+
+	HALASSERT(txTries0 != 0);
+	HALASSERT(isValidTxRate(txRate0));
+	HALASSERT((flags & RTSCTS) != RTSCTS);
+	/* XXX validate antMode */
+	
+	txPower = (txPower + ahp->ah_txPowerIndexOffset );
+	if(txPower > 63)  txPower=63;
+
+	ads->ds_ctl0 |= (txPower << AR_XmitPower_S)
+		| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
+		| (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
+		| (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
+	ads->ds_ctl1 |= (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
+	ads->ds_ctl2 |= SM(txTries0, AR_XmitDataTries0);
+	ads->ds_ctl3 |= (txRate0 << AR_XmitRate0_S);
+	ads->ds_ctl7 = SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel0) 
+		| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel1)
+		| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel2) 
+		| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel3);
+	
+	/* NB: no V1 WAR */
+	ads->ds_ctl8 = 0;
+	ads->ds_ctl9 = (txPower << 24);
+	ads->ds_ctl10 = (txPower << 24);
+	ads->ds_ctl11 = (txPower << 24);
+
+	ads->ds_ctl6 &= ~(0xffff);
+	ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
+
+	if (flags & RTSCTS) {
+		/* XXX validate rtsctsDuration */
+		ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
+			| (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
+		ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
+	}
+	
+	return AH_TRUE;
+#undef RTSCTS
+}
+
+HAL_BOOL
+ar5416SetupLastTxDesc(struct ath_hal *ah, struct ath_desc *ds,
+		const struct ath_desc *ds0)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+
+	ads->ds_ctl1 &= ~AR_MoreAggr;
+	ads->ds_ctl6 &= ~AR_PadDelim;
+
+	/* hack to copy rate info to last desc for later processing */
+#ifdef AH_NEED_DESC_SWAP
+	ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
+	ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
+#else
+	ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
+	ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
+#endif
+	
+	return AH_TRUE;
+}
+#endif /* 0 */
+
+#ifdef AH_NEED_DESC_SWAP
+/* Swap transmit descriptor */
+static __inline void
+ar5416SwapTxDesc(struct ath_desc *ds)
+{
+	ds->ds_data = __bswap32(ds->ds_data);
+	ds->ds_ctl0 = __bswap32(ds->ds_ctl0);
+	ds->ds_ctl1 = __bswap32(ds->ds_ctl1);
+	ds->ds_hw[0] = __bswap32(ds->ds_hw[0]);
+	ds->ds_hw[1] = __bswap32(ds->ds_hw[1]);
+	ds->ds_hw[2] = __bswap32(ds->ds_hw[2]);
+	ds->ds_hw[3] = __bswap32(ds->ds_hw[3]);
+}
+#endif
+
+/*
+ * Processing of HW TX descriptor.
+ */
+HAL_STATUS
+ar5416ProcTxDesc(struct ath_hal *ah,
+	struct ath_desc *ds, struct ath_tx_status *ts)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+	uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
+
+#ifdef AH_NEED_DESC_SWAP
+	if ((ds_txstatus[9] & __bswap32(AR_TxDone)) == 0)
+		return HAL_EINPROGRESS;
+	ar5416SwapTxDesc(ds);
+#else
+	if ((ds_txstatus[9] & AR_TxDone) == 0)
+		return HAL_EINPROGRESS;
+#endif
+
+	/* Update software copies of the HW status */
+	ts->ts_seqnum = MS(ds_txstatus[9], AR_SeqNum);
+	ts->ts_tstamp = AR_SendTimestamp(ds_txstatus);
+
+	ts->ts_status = 0;
+	if (ds_txstatus[1] & AR_ExcessiveRetries)
+		ts->ts_status |= HAL_TXERR_XRETRY;
+	if (ds_txstatus[1] & AR_Filtered)
+		ts->ts_status |= HAL_TXERR_FILT;
+	if (ds_txstatus[1] & AR_FIFOUnderrun)
+		ts->ts_status |= HAL_TXERR_FIFO;
+	if (ds_txstatus[9] & AR_TxOpExceeded)
+		ts->ts_status |= HAL_TXERR_XTXOP;
+	if (ds_txstatus[1] & AR_TxTimerExpired)
+		ts->ts_status |= HAL_TXERR_TIMER_EXPIRED;
+
+	ts->ts_flags  = 0;
+	if (ds_txstatus[0] & AR_TxBaStatus) {
+		ts->ts_flags |= HAL_TX_BA;
+		ts->ts_ba_low = AR_BaBitmapLow(ds_txstatus);
+		ts->ts_ba_high = AR_BaBitmapHigh(ds_txstatus);
+	}
+	if (ds->ds_ctl1 & AR_IsAggr)
+		ts->ts_flags |= HAL_TX_AGGR;
+	if (ds_txstatus[1] & AR_DescCfgErr)
+		ts->ts_flags |= HAL_TX_DESC_CFG_ERR;
+	if (ds_txstatus[1] & AR_TxDataUnderrun)
+		ts->ts_flags |= HAL_TX_DATA_UNDERRUN;
+	if (ds_txstatus[1] & AR_TxDelimUnderrun)
+		ts->ts_flags |= HAL_TX_DELIM_UNDERRUN;
+
+	/*
+	 * Extract the transmit rate used and mark the rate as
+	 * ``alternate'' if it wasn't the series 0 rate.
+	 */
+	ts->ts_finaltsi =  MS(ds_txstatus[9], AR_FinalTxIdx);
+	switch (ts->ts_finaltsi) {
+	case 0:
+		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
+		break;
+	case 1:
+		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1) |
+			HAL_TXSTAT_ALTRATE;
+		break;
+	case 2:
+		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2) |
+			HAL_TXSTAT_ALTRATE;
+		break;
+	case 3:
+		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3) |
+			HAL_TXSTAT_ALTRATE;
+		break;
+	}
+
+	ts->ts_rssi = MS(ds_txstatus[5], AR_TxRSSICombined);
+	ts->ts_rssi_ctl[0] = MS(ds_txstatus[0], AR_TxRSSIAnt00);
+	ts->ts_rssi_ctl[1] = MS(ds_txstatus[0], AR_TxRSSIAnt01);
+	ts->ts_rssi_ctl[2] = MS(ds_txstatus[0], AR_TxRSSIAnt02);
+	ts->ts_rssi_ext[0] = MS(ds_txstatus[5], AR_TxRSSIAnt10);
+	ts->ts_rssi_ext[1] = MS(ds_txstatus[5], AR_TxRSSIAnt11);
+	ts->ts_rssi_ext[2] = MS(ds_txstatus[5], AR_TxRSSIAnt12);
+	ts->ts_evm0 = AR_TxEVM0(ds_txstatus);
+	ts->ts_evm1 = AR_TxEVM1(ds_txstatus);
+	ts->ts_evm2 = AR_TxEVM2(ds_txstatus);
+
+	ts->ts_shortretry = MS(ds_txstatus[1], AR_RTSFailCnt);
+	ts->ts_longretry = MS(ds_txstatus[1], AR_DataFailCnt);
+	/*
+	 * The retry count has the number of un-acked tries for the
+	 * final series used.  When doing multi-rate retry we must
+	 * fixup the retry count by adding in the try counts for
+	 * each series that was fully-processed.  Beware that this
+	 * takes values from the try counts in the final descriptor.
+	 * These are not required by the hardware.  We assume they
+	 * are placed there by the driver as otherwise we have no
+	 * access and the driver can't do the calculation because it
+	 * doesn't know the descriptor format.
+	 */
+	switch (ts->ts_finaltsi) {
+	case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2);
+	case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1);
+	case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0);
+	}
+
+	/*
+	 * These fields are not used. Zero these to preserve compatability
+	 * with existing drivers.
+	 */
+	ts->ts_virtcol = MS(ads->ds_ctl1, AR_VirtRetryCnt);
+	ts->ts_antenna = 0; /* We don't switch antennas on Owl*/
+
+	/* handle tx trigger level changes internally */
+	if ((ts->ts_status & HAL_TXERR_FIFO) ||
+	    (ts->ts_flags & (HAL_TX_DATA_UNDERRUN | HAL_TX_DELIM_UNDERRUN)))
+		ar5212UpdateTxTrigLevel(ah, AH_TRUE);
+
+	return HAL_OK;
+}
+
+#if 0
+HAL_BOOL
+ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu)
+{
+	struct ath_hal_5416 *ahp = AH5416(ah);
+
+	if (tu > 0xFFFF) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad global tx timeout %u\n",
+		    __func__, tu);
+		/* restore default handling */
+		ahp->ah_globaltxtimeout = (u_int) -1;
+		return AH_FALSE;
+	}
+	OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
+	ahp->ah_globaltxtimeout = tu;
+	return AH_TRUE;
+}
+
+u_int
+ar5416GetGlobalTxTimeout(struct ath_hal *ah)
+{
+	return MS(OS_REG_READ(ah, AR_GTXTO), AR_GTXTO_TIMEOUT_LIMIT);
+}
+
+void
+ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds,
+        u_int durUpdateEn, u_int rtsctsRate,
+	HAL_11N_RATE_SERIES series[], u_int nseries)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+
+	HALASSERT(nseries == 4);
+	(void)nseries;
+
+
+	ads->ds_ctl2 = set11nTries(series, 0)
+		     | set11nTries(series, 1)
+		     | set11nTries(series, 2)
+		     | set11nTries(series, 3)
+		     | (durUpdateEn ? AR_DurUpdateEn : 0);
+
+	ads->ds_ctl3 = set11nRate(series, 0)
+		     | set11nRate(series, 1)
+		     | set11nRate(series, 2)
+		     | set11nRate(series, 3);
+
+	ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
+		     | set11nPktDurRTSCTS(series, 1);
+
+	ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
+		     | set11nPktDurRTSCTS(series, 3);
+
+	ads->ds_ctl7 = set11nRateFlags(series, 0)
+		     | set11nRateFlags(series, 1)
+		     | set11nRateFlags(series, 2)
+		     | set11nRateFlags(series, 3)
+		     | SM(rtsctsRate, AR_RTSCTSRate);
+
+	/*
+	 * Enable RTSCTS if any of the series is flagged for RTSCTS,
+	 * but only if CTS is not enabled.
+	 */
+	/*
+	 * FIXME : the entire RTS/CTS handling should be moved to this
+	 * function (by passing the global RTS/CTS flags to this function).
+	 * currently it is split between this function and the
+	 * setupFiirstDescriptor. with this current implementation there
+	 * is an implicit assumption that setupFirstDescriptor is called
+	 * before this function. 
+	 */
+	if (((series[0].RateFlags & HAL_RATESERIES_RTS_CTS) ||
+	     (series[1].RateFlags & HAL_RATESERIES_RTS_CTS) ||
+	     (series[2].RateFlags & HAL_RATESERIES_RTS_CTS) ||
+	     (series[3].RateFlags & HAL_RATESERIES_RTS_CTS) )  &&
+	    (ads->ds_ctl0 & AR_CTSEnable) == 0) {
+		ads->ds_ctl0 |= AR_RTSEnable;
+		ads->ds_ctl0 &= ~AR_CTSEnable;
+	}
+}
+
+void
+ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+	uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
+
+	ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
+
+	ads->ds_ctl6 &= ~AR_PadDelim;
+	ads->ds_ctl6 |= SM(numDelims, AR_PadDelim);
+	ads->ds_ctl6 &= ~AR_AggrLen;
+
+	/*
+	 * Clear the TxDone status here, may need to change
+	 * func name to reflect this
+	 */
+	ds_txstatus[9] &= ~AR_TxDone;
+}
+
+void
+ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+
+	ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
+	ads->ds_ctl6 &= ~AR_PadDelim;
+	ads->ds_ctl6 &= ~AR_AggrLen;
+}
+
+void
+ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds,
+                                                  u_int burstDuration)
+{
+	struct ar5416_desc *ads = AR5416DESC(ds);
+
+	ads->ds_ctl2 &= ~AR_BurstDur;
+	ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
+}
+#endif
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416desc.h b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416desc.h
new file mode 100644
index 0000000..7c60b24
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416desc.h
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416desc.h,v 1.7 2008/11/11 00:11:30 sam Exp $
+ */
+#ifndef _ATH_AR5416_DESC_H_
+#define _ATH_AR5416_DESC_H
+
+/*
+ * Hardware-specific descriptor structures.
+ */
+#include "ah_desc.h"
+
+/* XXX Need to replace this with a dynamic 
+ * method of determining Owl2 if possible 
+ */
+#define _get_index(_ah) ( IS_5416V1(_ah)  ? -4 : 0 )
+#define AR5416_DS_TXSTATUS(_ah, _ads) \
+	((uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))
+#define AR5416_DS_TXSTATUS_CONST(_ah, _ads) \
+	((const uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))
+
+#define AR5416_NUM_TX_STATUS	10 /* Number of TX status words */
+/* Clear the whole descriptor */
+#define AR5416_DESC_TX_CTL_SZ	sizeof(struct ar5416_tx_desc)
+
+struct ar5416_tx_desc { /* tx desc has 12 control words + 10 status words */
+	uint32_t	ctl2;
+	uint32_t	ctl3;
+	uint32_t	ctl4;
+	uint32_t	ctl5;
+	uint32_t	ctl6;
+	uint32_t	ctl7;
+	uint32_t	ctl8;
+	uint32_t	ctl9;
+	uint32_t	ctl10;
+	uint32_t	ctl11;
+	uint32_t	status[AR5416_NUM_TX_STATUS];
+};
+
+struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */
+	uint32_t	status0;
+	uint32_t	status1;
+	uint32_t	status2;
+	uint32_t	status3;
+	uint32_t	status4;
+	uint32_t	status5;
+	uint32_t	status6;
+ 	uint32_t	status7;
+	uint32_t	status8;
+};
+
+
+struct ar5416_desc {
+	uint32_t   ds_link;    /* link pointer */
+	uint32_t   ds_data;    /* data buffer pointer */
+	uint32_t   ds_ctl0;    /* DMA control 0 */
+	uint32_t   ds_ctl1;    /* DMA control 1 */
+	union {
+		struct ar5416_tx_desc tx;
+		struct ar5416_rx_desc rx;
+	} u;
+} __packed;
+#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
+#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
+
+#define ds_ctl2     u.tx.ctl2
+#define ds_ctl3     u.tx.ctl3
+#define ds_ctl4     u.tx.ctl4
+#define ds_ctl5     u.tx.ctl5
+#define ds_ctl6     u.tx.ctl6
+#define ds_ctl7     u.tx.ctl7
+#define ds_ctl8     u.tx.ctl8
+#define ds_ctl9     u.tx.ctl9
+#define ds_ctl10    u.tx.ctl10
+#define ds_ctl11    u.tx.ctl11
+
+#define ds_rxstatus0    u.rx.status0
+#define ds_rxstatus1    u.rx.status1
+#define ds_rxstatus2    u.rx.status2
+#define ds_rxstatus3    u.rx.status3
+#define ds_rxstatus4    u.rx.status4
+#define ds_rxstatus5    u.rx.status5
+#define ds_rxstatus6    u.rx.status6
+#define ds_rxstatus7    u.rx.status7
+#define ds_rxstatus8    u.rx.status8
+
+/***********
+ * TX Desc *
+ ***********/
+
+/* ds_ctl0 */
+#define AR_FrameLen         0x00000fff
+#define AR_VirtMoreFrag     0x00001000
+#define AR_TxCtlRsvd00      0x0000e000
+#define AR_XmitPower        0x003f0000
+#define AR_XmitPower_S      16
+#define AR_RTSEnable        0x00400000
+#define AR_VEOL             0x00800000
+#define AR_ClrDestMask      0x01000000
+#define AR_TxCtlRsvd01      0x1e000000
+#define AR_TxIntrReq        0x20000000
+#define AR_DestIdxValid     0x40000000
+#define AR_CTSEnable        0x80000000
+
+/* ds_ctl1 */
+#define AR_BufLen           0x00000fff
+#define AR_TxMore           0x00001000
+#define AR_DestIdx          0x000fe000
+#define AR_DestIdx_S        13
+#define AR_FrameType        0x00f00000
+#define AR_FrameType_S      20
+#define AR_NoAck            0x01000000
+#define AR_InsertTS         0x02000000
+#define AR_CorruptFCS       0x04000000
+#define AR_ExtOnly          0x08000000
+#define AR_ExtAndCtl        0x10000000
+#define AR_MoreAggr         0x20000000
+#define AR_IsAggr           0x40000000
+#define AR_MoreRifs	    0x80000000
+
+/* ds_ctl2 */
+#define AR_BurstDur         0x00007fff
+#define AR_BurstDur_S       0
+#define AR_DurUpdateEn      0x00008000
+#define AR_XmitDataTries0   0x000f0000
+#define AR_XmitDataTries0_S 16
+#define AR_XmitDataTries1   0x00f00000
+#define AR_XmitDataTries1_S 20
+#define AR_XmitDataTries2   0x0f000000
+#define AR_XmitDataTries2_S 24
+#define AR_XmitDataTries3   0xf0000000
+#define AR_XmitDataTries3_S 28
+
+/* ds_ctl3 */
+#define AR_XmitRate0        0x000000ff
+#define AR_XmitRate0_S      0
+#define AR_XmitRate1        0x0000ff00
+#define AR_XmitRate1_S      8
+#define AR_XmitRate2        0x00ff0000
+#define AR_XmitRate2_S      16
+#define AR_XmitRate3        0xff000000
+#define AR_XmitRate3_S      24
+
+/* ds_ctl4 */
+#define AR_PacketDur0       0x00007fff
+#define AR_PacketDur0_S     0
+#define AR_RTSCTSQual0      0x00008000
+#define AR_PacketDur1       0x7fff0000
+#define AR_PacketDur1_S     16
+#define AR_RTSCTSQual1      0x80000000
+
+/* ds_ctl5 */
+#define AR_PacketDur2       0x00007fff
+#define AR_PacketDur2_S     0
+#define AR_RTSCTSQual2      0x00008000
+#define AR_PacketDur3       0x7fff0000
+#define AR_PacketDur3_S     16
+#define AR_RTSCTSQual3      0x80000000
+
+/* ds_ctl6 */
+#define AR_AggrLen          0x0000ffff
+#define AR_AggrLen_S        0
+#define AR_TxCtlRsvd60      0x00030000
+#define AR_PadDelim         0x03fc0000
+#define AR_PadDelim_S       18
+#define AR_EncrType         0x0c000000
+#define AR_EncrType_S       26
+#define AR_TxCtlRsvd61      0xf0000000
+
+/* ds_ctl7 */
+#define AR_2040_0           0x00000001
+#define AR_GI0              0x00000002
+#define AR_ChainSel0        0x0000001c
+#define AR_ChainSel0_S      2
+#define AR_2040_1           0x00000020
+#define AR_GI1              0x00000040
+#define AR_ChainSel1        0x00000380
+#define AR_ChainSel1_S      7
+#define AR_2040_2           0x00000400
+#define AR_GI2              0x00000800
+#define AR_ChainSel2        0x00007000
+#define AR_ChainSel2_S      12
+#define AR_2040_3           0x00008000
+#define AR_GI3              0x00010000
+#define AR_ChainSel3        0x000e0000
+#define AR_ChainSel3_S      17
+#define AR_RTSCTSRate       0x0ff00000
+#define AR_RTSCTSRate_S     20
+#define	AR_STBC0	    0x10000000
+#define	AR_STBC1	    0x20000000
+#define	AR_STBC2	    0x40000000
+#define	AR_STBC3	    0x80000000
+
+/*************
+ * TX Status *
+ *************/
+
+/* ds_status0 */
+#define AR_TxRSSIAnt00      0x000000ff
+#define AR_TxRSSIAnt00_S    0
+#define AR_TxRSSIAnt01      0x0000ff00
+#define AR_TxRSSIAnt01_S    8
+#define AR_TxRSSIAnt02      0x00ff0000
+#define AR_TxRSSIAnt02_S    16
+#define AR_TxStatusRsvd00   0x3f000000
+#define AR_TxBaStatus       0x40000000
+#define AR_TxStatusRsvd01   0x80000000
+
+/* ds_status1 */
+#define AR_FrmXmitOK            0x00000001
+#define AR_ExcessiveRetries     0x00000002
+#define AR_FIFOUnderrun         0x00000004
+#define AR_Filtered             0x00000008
+#define AR_RTSFailCnt           0x000000f0
+#define AR_RTSFailCnt_S         4
+#define AR_DataFailCnt          0x00000f00
+#define AR_DataFailCnt_S        8
+#define AR_VirtRetryCnt         0x0000f000
+#define AR_VirtRetryCnt_S       12
+#define AR_TxDelimUnderrun      0x00010000
+#define AR_TxDelimUnderrun_S    13
+#define AR_TxDataUnderrun       0x00020000
+#define AR_TxDataUnderrun_S     14
+#define AR_DescCfgErr           0x00040000
+#define AR_DescCfgErr_S         15
+#define	AR_TxTimerExpired	0x00080000
+#define AR_TxStatusRsvd10       0xfff00000
+
+/* ds_status2 */
+#define AR_SendTimestamp(_ptr)   (_ptr)[2]
+
+/* ds_status3 */
+#define AR_BaBitmapLow(_ptr)     (_ptr)[3]
+
+/* ds_status4 */
+#define AR_BaBitmapHigh(_ptr)    (_ptr)[4]
+
+/* ds_status5 */
+#define AR_TxRSSIAnt10      0x000000ff
+#define AR_TxRSSIAnt10_S    0
+#define AR_TxRSSIAnt11      0x0000ff00
+#define AR_TxRSSIAnt11_S    8
+#define AR_TxRSSIAnt12      0x00ff0000
+#define AR_TxRSSIAnt12_S    16
+#define AR_TxRSSICombined   0xff000000
+#define AR_TxRSSICombined_S 24
+
+/* ds_status6 */
+#define AR_TxEVM0(_ptr)     (_ptr)[6]
+
+/* ds_status7 */
+#define AR_TxEVM1(_ptr)    (_ptr)[7]
+
+/* ds_status8 */
+#define AR_TxEVM2(_ptr)   (_ptr)[8]
+
+/* ds_status9 */
+#define AR_TxDone           0x00000001
+#define AR_SeqNum           0x00001ffe
+#define AR_SeqNum_S         1
+#define AR_TxStatusRsvd80   0x0001e000
+#define AR_TxOpExceeded     0x00020000
+#define AR_TxStatusRsvd81   0x001c0000
+#define AR_FinalTxIdx       0x00600000
+#define AR_FinalTxIdx_S     21
+#define AR_TxStatusRsvd82   0x01800000
+#define AR_PowerMgmt        0x02000000
+#define AR_TxStatusRsvd83   0xfc000000
+
+/***********
+ * RX Desc *
+ ***********/
+
+/* ds_ctl0 */
+#define AR_RxCTLRsvd00  0xffffffff
+
+/* ds_ctl1 */
+#define AR_BufLen       0x00000fff
+#define AR_RxCtlRsvd00  0x00001000
+#define AR_RxIntrReq    0x00002000
+#define AR_RxCtlRsvd01  0xffffc000
+
+/*************
+ * Rx Status *
+ *************/
+
+/* ds_status0 */
+#define AR_RxRSSIAnt00      0x000000ff
+#define AR_RxRSSIAnt00_S    0
+#define AR_RxRSSIAnt01      0x0000ff00
+#define AR_RxRSSIAnt01_S    8
+#define AR_RxRSSIAnt02      0x00ff0000
+#define AR_RxRSSIAnt02_S    16
+/* Rev specific */
+/* Owl 1.x only */
+#define AR_RxStatusRsvd00   0xff000000
+/* Owl 2.x only */
+#define AR_RxRate           0xff000000
+#define AR_RxRate_S         24
+
+/* ds_status1 */
+#define AR_DataLen          0x00000fff
+#define AR_RxMore           0x00001000
+#define AR_NumDelim         0x003fc000
+#define AR_NumDelim_S       14
+#define AR_RxStatusRsvd10   0xff800000
+
+/* ds_status2 */
+#define AR_RcvTimestamp     ds_rxstatus2
+
+/* ds_status3 */
+#define AR_GI               0x00000001
+#define AR_2040             0x00000002
+/* Rev specific */
+/* Owl 1.x only */
+#define AR_RxRateV1         0x000003fc
+#define AR_RxRateV1_S       2
+#define AR_Parallel40       0x00000400
+#define AR_RxStatusRsvd30   0xfffff800
+/* Owl 2.x only */
+#define AR_DupFrame	    0x00000004
+#define AR_RxAntenna        0xffffff00
+#define AR_RxAntenna_S      8
+
+/* ds_status4 */
+#define AR_RxRSSIAnt10            0x000000ff
+#define AR_RxRSSIAnt10_S          0
+#define AR_RxRSSIAnt11            0x0000ff00
+#define AR_RxRSSIAnt11_S          8
+#define AR_RxRSSIAnt12            0x00ff0000
+#define AR_RxRSSIAnt12_S          16
+#define AR_RxRSSICombined         0xff000000
+#define AR_RxRSSICombined_S       24
+
+/* ds_status5 */
+#define AR_RxEVM0           ds_rxstatus5
+
+/* ds_status6 */
+#define AR_RxEVM1           ds_rxstatus6
+
+/* ds_status7 */
+#define AR_RxEVM2           ds_rxstatus7
+
+/* ds_status8 */
+#define AR_RxDone           0x00000001
+#define AR_RxFrameOK        0x00000002
+#define AR_CRCErr           0x00000004
+#define AR_DecryptCRCErr    0x00000008
+#define AR_PHYErr           0x00000010
+#define AR_MichaelErr       0x00000020
+#define AR_PreDelimCRCErr   0x00000040
+#define AR_RxStatusRsvd70   0x00000080
+#define AR_RxKeyIdxValid    0x00000100
+#define AR_KeyIdx           0x0000fe00
+#define AR_KeyIdx_S         9
+#define AR_PHYErrCode       0x0000ff00
+#define AR_PHYErrCode_S     8
+#define AR_RxMoreAggr       0x00010000
+#define AR_RxAggr           0x00020000
+#define AR_PostDelimCRCErr  0x00040000
+#define AR_RxStatusRsvd71   0x2ff80000
+#define	AR_HiRxChain	    0x10000000
+#define AR_DecryptBusyErr   0x40000000
+#define AR_KeyMiss          0x80000000
+
+#define TXCTL_OFFSET(ah)	2
+#define TXCTL_NUMWORDS(ah)	(AR_SREV_5416_V20_OR_LATER(ah) ? 12 : 8)
+#define TXSTATUS_OFFSET(ah)	(AR_SREV_5416_V20_OR_LATER(ah) ? 14 : 10)
+#define TXSTATUS_NUMWORDS(ah)	10
+
+#define RXCTL_OFFSET(ah)	3
+#define RXCTL_NUMWORDS(ah)	1
+#define RXSTATUS_OFFSET(ah)	4
+#define RXSTATUS_NUMWORDS(ah)	9
+#define RXSTATUS_RATE(ah, ads) \
+	(AR_SREV_OWL_20_OR_LATER(ah) ? \
+	 MS((ads)->ds_rxstatus0, AR_RxRate) : \
+	 ((ads)->ds_rxstatus3 >> 2) & 0xFF)
+#define RXSTATUS_DUPLICATE(ah, ads) \
+	(AR_SREV_OWL_20_OR_LATER(ah) ?	\
+	 MS((ads)->ds_rxstatus3, AR_Parallel40) : \
+	 ((ads)->ds_rxstatus3 >> 10) & 0x1)
+#endif /* _ATH_AR5416_DESC_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416phy.h b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416phy.h
new file mode 100644
index 0000000..416aae6
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416phy.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416phy.h,v 1.10 2008/11/11 20:46:06 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5416PHY_H_
+#define _DEV_ATH_AR5416PHY_H_
+
+#include "ar5212/ar5212phy.h"
+
+#define AR_PHY_CHIP_ID_REV_0    0x80        /* 5416 Rev 0 (owl 1.0) BB */
+#define AR_PHY_CHIP_ID_REV_1    0x81        /* 5416 Rev 1 (owl 2.0) BB */
+
+#define RFSILENT_BB             0x00002000      /* shush bb */
+#define AR_PHY_RESTART      	0x9970      /* restart */
+#define AR_PHY_RESTART_DIV_GC   0x001C0000  /* bb_ant_fast_div_gc_limit */
+#define AR_PHY_RESTART_DIV_GC_S 18
+
+/* PLL settling times */
+#define RTC_PLL_SETTLE_DELAY		1000    /* 1 ms     */
+#define HT40_CHANNEL_CENTER_SHIFT   	10	/* MHz      */
+
+#define AR_PHY_RFBUS_REQ        0x997C
+#define AR_PHY_RFBUS_REQ_EN     0x00000001
+
+#define AR_2040_MODE                0x8318
+#define AR_2040_JOINED_RX_CLEAR     0x00000001   // use ctl + ext rx_clear for cca
+
+#define AR_PHY_FC_TURBO_SHORT       0x00000002  /* Set short symbols to turbo mode setting */
+#define AR_PHY_FC_DYN2040_EN        0x00000004      /* Enable dyn 20/40 mode */
+#define AR_PHY_FC_DYN2040_PRI_ONLY  0x00000008      /* dyn 20/40 - primary only */
+#define AR_PHY_FC_DYN2040_PRI_CH    0x00000010      /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
+#define AR_PHY_FC_DYN2040_EXT_CH    0x00000020      /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
+#define AR_PHY_FC_HT_EN             0x00000040      /* ht enable */
+#define AR_PHY_FC_SHORT_GI_40       0x00000080      /* allow short GI for HT 40 */
+#define AR_PHY_FC_WALSH             0x00000100      /* walsh spatial spreading for 2 chains,2 streams TX */
+#define AR_PHY_FC_SINGLE_HT_LTF1    0x00000200      /* single length (4us) 1st HT long training symbol */
+
+#define AR_PHY_TIMING2      0x9810      /* Timing Control 2 */
+#define AR_PHY_TIMING2_USE_FORCE    0x00001000
+#define AR_PHY_TIMING2_FORCE_VAL    0x00000fff
+
+#define	AR_PHY_TIMING_CTRL4_CHAIN(_i) \
+	(AR_PHY_TIMING_CTRL4 + ((_i) << 12))
+#define	AR_PHY_TIMING_CTRL4_DO_CAL  0x10000	    /* perform calibration */
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F   /* Mask for kcos_theta-1 for q correction */
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S   0   /* shift for Q_COFF */
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0   /* Mask for sin_theta for i correction */
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S   5   /* Shift for sin_theta for i correction */
+#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE   0x800   /* enable IQ correction */
+#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000  /* Mask for max number of samples (logarithmic) */
+#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S   12  /* Shift for max number of samples */
+
+#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI	0x80000000
+#define	AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER	0x40000000	/* Enable spur filter */
+#define	AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK	0x20000000
+#define	AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK	0x10000000
+
+#define AR_PHY_ADC_SERIAL_CTL       0x9830
+#define AR_PHY_SEL_INTERNAL_ADDAC   0x00000000
+#define AR_PHY_SEL_EXTERNAL_RADIO   0x00000001
+
+#define AR_PHY_GAIN_2GHZ_BSW_MARGIN	0x00003C00
+#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S	10
+#define AR_PHY_GAIN_2GHZ_BSW_ATTEN	0x0000001F
+#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S	0
+
+#define AR_PHY_EXT_CCA          0x99bc
+#define AR_PHY_EXT_CCA_CYCPWR_THR1      0x0000FE00
+#define AR_PHY_EXT_CCA_CYCPWR_THR1_S    9
+#define AR_PHY_EXT_MINCCA_PWR   0xFF800000
+#define AR_PHY_EXT_MINCCA_PWR_S 23
+#define AR_PHY_EXT_CCA_THRESH62	0x007F0000
+#define AR_PHY_EXT_CCA_THRESH62_S	16
+#define AR9280_PHY_EXT_MINCCA_PWR       0x01FF0000
+#define AR9280_PHY_EXT_MINCCA_PWR_S     16
+
+#define AR_PHY_HALFGI           0x99D0      /* Timing control 3 */
+#define AR_PHY_HALFGI_DSC_MAN   0x0007FFF0
+#define AR_PHY_HALFGI_DSC_MAN_S 4
+#define AR_PHY_HALFGI_DSC_EXP   0x0000000F
+#define AR_PHY_HALFGI_DSC_EXP_S 0
+
+#define AR_PHY_HEAVY_CLIP_ENABLE    0x99E0
+
+#define AR_PHY_M_SLEEP      0x99f0      /* sleep control registers */
+#define AR_PHY_REFCLKDLY    0x99f4
+#define AR_PHY_REFCLKPD     0x99f8
+
+#define	AR_PHY_CALMODE		0x99f0
+/* Calibration Types */
+#define	AR_PHY_CALMODE_IQ		0x00000000
+#define	AR_PHY_CALMODE_ADC_GAIN		0x00000001
+#define	AR_PHY_CALMODE_ADC_DC_PER	0x00000002
+#define	AR_PHY_CALMODE_ADC_DC_INIT	0x00000003
+/* Calibration results */
+#define	AR_PHY_CAL_MEAS_0(_i)	(0x9c10 + ((_i) << 12))
+#define	AR_PHY_CAL_MEAS_1(_i)	(0x9c14 + ((_i) << 12))
+#define	AR_PHY_CAL_MEAS_2(_i)	(0x9c18 + ((_i) << 12))
+#define	AR_PHY_CAL_MEAS_3(_i)	(0x9c1c + ((_i) << 12))
+
+
+#define AR_PHY_CCA          0x9864
+#define AR_PHY_MINCCA_PWR   0x0FF80000
+#define AR_PHY_MINCCA_PWR_S 19
+#define AR9280_PHY_MINCCA_PWR       0x1FF00000
+#define AR9280_PHY_MINCCA_PWR_S     20
+#define AR9280_PHY_CCA_THRESH62     0x000FF000
+#define AR9280_PHY_CCA_THRESH62_S   12
+
+#define AR_PHY_CH1_CCA          0xa864
+#define AR_PHY_CH1_MINCCA_PWR   0x0FF80000
+#define AR_PHY_CH1_MINCCA_PWR_S 19
+#define AR_PHY_CCA_THRESH62     0x0007F000
+#define AR_PHY_CCA_THRESH62_S   12
+#define AR9280_PHY_CH1_MINCCA_PWR   0x1FF00000
+#define AR9280_PHY_CH1_MINCCA_PWR_S 20
+
+#define AR_PHY_CH2_CCA          0xb864
+#define AR_PHY_CH2_MINCCA_PWR   0x0FF80000
+#define AR_PHY_CH2_MINCCA_PWR_S 19
+
+#define AR_PHY_CH1_EXT_CCA          0xa9bc
+#define AR_PHY_CH1_EXT_MINCCA_PWR   0xFF800000
+#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
+#define AR9280_PHY_CH1_EXT_MINCCA_PWR   0x01FF0000
+#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
+
+#define AR_PHY_CH2_EXT_CCA          0xb9bc
+#define AR_PHY_CH2_EXT_MINCCA_PWR   0xFF800000
+#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
+
+#define AR_PHY_RX_CHAINMASK     0x99a4
+
+#define	AR_PHY_NEW_ADC_DC_GAIN_CORR(_i)	(0x99b4 + ((_i) << 12))
+#define	AR_PHY_NEW_ADC_GAIN_CORR_ENABLE	0x40000000
+#define	AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE	0x80000000
+#define	AR_PHY_MULTICHAIN_GAIN_CTL	0x99ac
+
+#define	AR_PHY_EXT_CCA0			0x99b8
+#define	AR_PHY_EXT_CCA0_THRESH62	0x000000FF
+#define	AR_PHY_EXT_CCA0_THRESH62_S	0
+
+#define AR_PHY_CH1_EXT_CCA          0xa9bc
+#define AR_PHY_CH1_EXT_MINCCA_PWR   0xFF800000
+#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
+
+#define AR_PHY_CH2_EXT_CCA          0xb9bc
+#define AR_PHY_CH2_EXT_MINCCA_PWR   0xFF800000
+#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
+#define AR_PHY_ANALOG_SWAP      0xa268
+#define AR_PHY_SWAP_ALT_CHAIN   0x00000040
+#define AR_PHY_CAL_CHAINMASK	0xa39c
+
+#define AR_PHY_SWITCH_CHAIN_0     0x9960
+#define AR_PHY_SWITCH_COM         0x9964
+
+#define AR_PHY_RF_CTL2                  0x9824
+#define AR_PHY_TX_FRAME_TO_DATA_START	0x000000FF
+#define AR_PHY_TX_FRAME_TO_DATA_START_S	0
+#define AR_PHY_TX_FRAME_TO_PA_ON	0x0000FF00
+#define AR_PHY_TX_FRAME_TO_PA_ON_S	8
+
+#define AR_PHY_RF_CTL3                  0x9828
+#define AR_PHY_TX_END_TO_A2_RX_ON       0x00FF0000
+#define AR_PHY_TX_END_TO_A2_RX_ON_S     16
+
+#define AR_PHY_RF_CTL4                    0x9834
+#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF    0xFF000000
+#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S  24
+#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF    0x00FF0000
+#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S  16
+#define AR_PHY_RF_CTL4_FRAME_XPAB_ON      0x0000FF00
+#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S    8
+#define AR_PHY_RF_CTL4_FRAME_XPAA_ON      0x000000FF
+#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S    0
+
+#define	AR_PHY_SYNTH_CONTROL	0x9874
+
+#define	AR_PHY_FORCE_CLKEN_CCK	0xA22C
+#define	AR_PHY_FORCE_CLKEN_CCK_MRC_MUX	0x00000040
+
+#define AR_PHY_POWER_TX_SUB     0xA3C8
+#define AR_PHY_POWER_TX_RATE5   0xA38C
+#define AR_PHY_POWER_TX_RATE6   0xA390
+#define AR_PHY_POWER_TX_RATE7   0xA3CC
+#define AR_PHY_POWER_TX_RATE8   0xA3D0
+#define AR_PHY_POWER_TX_RATE9   0xA3D4
+
+#define	AR_PHY_TPCRG1_PD_GAIN_1 	0x00030000
+#define	AR_PHY_TPCRG1_PD_GAIN_1_S	16
+#define	AR_PHY_TPCRG1_PD_GAIN_2		0x000C0000
+#define	AR_PHY_TPCRG1_PD_GAIN_2_S	18
+#define	AR_PHY_TPCRG1_PD_GAIN_3		0x00300000
+#define	AR_PHY_TPCRG1_PD_GAIN_3_S	20
+
+#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
+#define AR_PHY_MASK2_M_31_45     0xa3a4
+#define AR_PHY_MASK2_M_16_30     0xa3a8
+#define AR_PHY_MASK2_M_00_15     0xa3ac
+#define AR_PHY_MASK2_P_15_01     0xa3b8
+#define AR_PHY_MASK2_P_30_16     0xa3bc
+#define AR_PHY_MASK2_P_45_31     0xa3c0
+#define AR_PHY_MASK2_P_61_45     0xa3c4
+
+#define	AR_PHY_SPUR_REG         0x994c
+#define	AR_PHY_SFCORR_EXT	0x99c0
+#define	AR_PHY_SFCORR_EXT_M1_THRESH	0x0000007F
+#define	AR_PHY_SFCORR_EXT_M1_THRESH_S	0
+#define	AR_PHY_SFCORR_EXT_M2_THRESH	0x00003F80
+#define	AR_PHY_SFCORR_EXT_M2_THRESH_S	7
+#define	AR_PHY_SFCORR_EXT_M1_THRESH_LOW	0x001FC000
+#define	AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S	14
+#define	AR_PHY_SFCORR_EXT_M2_THRESH_LOW	0x0FE00000
+#define	AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S	21
+#define	AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S	28
+
+/* enable vit puncture per rate, 8 bits, lsb is low rate */
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL       (0xFF << 18)
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S     18
+
+#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM      0x20000     /* bins move with freq offset */
+#define AR_PHY_SPUR_REG_MASK_RATE_SELECT     (0xFF << 9) /* use mask1 or mask2, one per rate */
+#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S   9
+#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH     0x7F
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S   0
+
+#define AR_PHY_PILOT_MASK_01_30   0xa3b0
+#define AR_PHY_PILOT_MASK_31_60   0xa3b4
+
+#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
+#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
+
+#define	AR_PHY_CL_CAL_CTL	0xA358		/* carrier leak cal control */
+#define	AR_PHY_CL_CAL_ENABLE	0x00000002
+#endif /* _DEV_ATH_AR5416PHY_H_ */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416reg.h b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416reg.h
new file mode 100644
index 0000000..770ec22
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416reg.h
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar5416reg.h,v 1.10 2008/11/11 00:11:30 sam Exp $
+ */
+#ifndef _DEV_ATH_AR5416REG_H
+#define	_DEV_ATH_AR5416REG_H
+
+#include "ar5212/ar5212reg.h"
+
+/*
+ * Register added starting with the AR5416
+ */
+#define	AR_MIRT			0x0020	/* interrupt rate threshold */
+#define	AR_TIMT			0x0028	/* Tx Interrupt mitigation threshold */
+#define	AR_RIMT			0x002C	/* Rx Interrupt mitigation threshold */
+#define	AR_GTXTO		0x0064	/* global transmit timeout */
+#define	AR_GTTM			0x0068	/* global transmit timeout mode */
+#define	AR_CST			0x006C	/* carrier sense timeout */
+#define	AR_MAC_LED		0x1f04	/* LED control */
+#define	AR5416_PCIE_PM_CTRL	0x4014
+#define	AR_AHB_MODE		0x4024	/* AHB mode for dma */
+#define	AR_INTR_SYNC_CAUSE_CLR	0x4028	/* clear interrupt */
+#define	AR_INTR_SYNC_CAUSE	0x4028	/* check pending interrupts */
+#define	AR_INTR_SYNC_ENABLE	0x402c	/* enable interrupts */
+#define	AR_INTR_ASYNC_MASK	0x4030	/* asynchronous interrupt mask */
+#define	AR_INTR_SYNC_MASK	0x4034	/* synchronous interrupt mask */
+#define	AR_INTR_ASYNC_CAUSE	0x4038	/* check pending interrupts */
+#define	AR_INTR_ASYNC_ENABLE	0x403c	/* enable interrupts */
+#define	AR5416_PCIE_SERDES	0x4040
+#define	AR5416_PCIE_SERDES2	0x4044
+#define	AR_GPIO_IN		0x4048	/* GPIO input register */
+#define	AR_GPIO_INTR_OUT	0x404c	/* GPIO output register */
+#define	AR_EEPROM_STATUS_DATA	0x407c
+#define	AR_OBS			0x4080
+#define	AR_RTC_RC		0x7000	/* reset control */
+#define	AR_RTC_PLL_CONTROL	0x7014
+#define	AR_RTC_RESET		0x7040	/* RTC reset register */
+#define	AR_RTC_STATUS		0x7044	/* system sleep status */
+#define	AR_RTC_SLEEP_CLK	0x7048
+#define	AR_RTC_FORCE_WAKE	0x704c	/* control MAC force wake */
+#define	AR_RTC_INTR_CAUSE	0x7050	/* RTC interrupt cause/clear */
+#define	AR_RTC_INTR_ENABLE	0x7054	/* RTC interrupt enable */
+#define	AR_RTC_INTR_MASK	0x7058	/* RTC interrupt mask */
+/* AR9280: rf long shift registers */
+#define	AR_AN_RF2G1_CH0         0x7810
+#define	AR_AN_RF5G1_CH0         0x7818
+#define	AR_AN_RF2G1_CH1         0x7834
+#define	AR_AN_RF5G1_CH1         0x783C
+#define	AR_AN_TOP2		0x7894
+#define	AR_AN_SYNTH9            0x7868
+#define	AR9285_AN_RF2G3         0x7828
+#define	AR9285_AN_TOP3		0x786c
+#define	AR_RESET_TSF		0x8020
+#define	AR_RXFIFO_CFG		0x8114
+#define	AR_PHY_ERR_1		0x812c
+#define	AR_PHY_ERR_MASK_1	0x8130	/* mask for AR_PHY_ERR_1 */
+#define	AR_PHY_ERR_2		0x8134
+#define	AR_PHY_ERR_MASK_2	0x8138	/* mask for AR_PHY_ERR_2 */
+#define	AR_TSFOOR_THRESHOLD	0x813c
+#define	AR_PHY_ERR_3		0x8168
+#define	AR_PHY_ERR_MASK_3	0x816c	/* mask for AR_PHY_ERR_3 */
+#define	AR_TXOP_X		0x81ec	/* txop for legacy non-qos */
+#define	AR_TXOP_0_3		0x81f0	/* txop for various tid's */
+#define	AR_TXOP_4_7		0x81f4
+#define	AR_TXOP_8_11		0x81f8
+#define	AR_TXOP_12_15		0x81fc
+/* generic timers based on tsf - all uS */
+#define	AR_NEXT_TBTT		0x8200
+#define	AR_NEXT_DBA		0x8204
+#define	AR_NEXT_SWBA		0x8208
+#define	AR_NEXT_CFP		0x8208
+#define	AR_NEXT_HCF		0x820C
+#define	AR_NEXT_TIM		0x8210
+#define	AR_NEXT_DTIM		0x8214
+#define	AR_NEXT_QUIET		0x8218
+#define	AR_NEXT_NDP		0x821C
+#define	AR5416_BEACON_PERIOD	0x8220
+#define	AR_DBA_PERIOD		0x8224
+#define	AR_SWBA_PERIOD		0x8228
+#define	AR_HCF_PERIOD		0x822C
+#define	AR_TIM_PERIOD		0x8230
+#define	AR_DTIM_PERIOD		0x8234
+#define	AR_QUIET_PERIOD		0x8238
+#define	AR_NDP_PERIOD		0x823C
+#define	AR_TIMER_MODE		0x8240
+#define	AR_SLP32_MODE		0x8244
+#define	AR_SLP32_WAKE		0x8248
+#define	AR_SLP32_INC		0x824c
+#define	AR_SLP_CNT		0x8250	/* 32kHz cycles with mac asleep */
+#define	AR_SLP_CYCLE_CNT	0x8254	/* absolute number of 32kHz cycles */
+#define	AR_SLP_MIB_CTRL		0x8258
+#define	AR_2040_MODE		0x8318
+#define	AR_EXTRCCNT		0x8328	/* extension channel rx clear count */
+#define	AR_SELFGEN_MASK		0x832c	/* rx and cal chain masks */
+#define	AR_PCU_TXBUF_CTRL	0x8340
+
+/* DMA & PCI Registers in PCI space (usable during sleep)*/
+#define	AR_RC_AHB		0x00000001	/* AHB reset */
+#define	AR_RC_APB		0x00000002	/* APB reset */
+#define	AR_RC_HOSTIF		0x00000100	/* host interface reset */
+
+#define	AR_MIRT_VAL		0x0000ffff	/* in uS */
+#define	AR_MIRT_VAL_S		16
+
+#define	AR_TIMT_LAST		0x0000ffff	/* Last packet threshold */
+#define	AR_TIMT_LAST_S		0
+#define	AR_TIMT_FIRST		0xffff0000	/* First packet threshold */
+#define	AR_TIMT_FIRST_S		16
+
+#define	AR_RIMT_LAST		0x0000ffff	/* Last packet threshold */
+#define	AR_RIMT_LAST_S		0
+#define	AR_RIMT_FIRST		0xffff0000	/* First packet threshold */
+#define	AR_RIMT_FIRST_S		16
+
+#define	AR_GTXTO_TIMEOUT_COUNTER    0x0000FFFF  // Mask for timeout counter (in TUs)
+#define	AR_GTXTO_TIMEOUT_LIMIT      0xFFFF0000  // Mask for timeout limit (in  TUs)
+#define	AR_GTXTO_TIMEOUT_LIMIT_S    16      // Shift for timeout limit
+
+#define	AR_GTTM_USEC          0x00000001 // usec strobe
+#define	AR_GTTM_IGNORE_IDLE   0x00000002 // ignore channel idle
+#define	AR_GTTM_RESET_IDLE    0x00000004 // reset counter on channel idle low
+#define	AR_GTTM_CST_USEC      0x00000008 // CST usec strobe
+
+#define	AR_CST_TIMEOUT_COUNTER    0x0000FFFF  // Mask for timeout counter (in TUs)
+#define	AR_CST_TIMEOUT_LIMIT      0xFFFF0000  // Mask for timeout limit (in  TUs)
+#define	AR_CST_TIMEOUT_LIMIT_S    16      // Shift for timeout limit
+
+/* MAC tx DMA size config  */
+#define	AR_TXCFG_DMASZ_MASK	0x00000003
+#define	AR_TXCFG_DMASZ_4B	0
+#define	AR_TXCFG_DMASZ_8B	1
+#define	AR_TXCFG_DMASZ_16B	2
+#define	AR_TXCFG_DMASZ_32B	3
+#define	AR_TXCFG_DMASZ_64B	4
+#define	AR_TXCFG_DMASZ_128B	5
+#define	AR_TXCFG_DMASZ_256B	6
+#define	AR_TXCFG_DMASZ_512B	7
+#define	AR_TXCFG_ATIM_TXPOLICY	0x00000800
+
+/* MAC rx DMA size config  */
+#define	AR_RXCFG_DMASZ_MASK	0x00000007
+#define	AR_RXCFG_DMASZ_4B	0
+#define	AR_RXCFG_DMASZ_8B	1
+#define	AR_RXCFG_DMASZ_16B	2
+#define	AR_RXCFG_DMASZ_32B	3
+#define	AR_RXCFG_DMASZ_64B	4
+#define	AR_RXCFG_DMASZ_128B	5
+#define	AR_RXCFG_DMASZ_256B	6
+#define	AR_RXCFG_DMASZ_512B	7
+
+/* MAC Led registers */
+#define	AR_MAC_LED_BLINK_SLOW	0x00000008	/* LED slowest blink rate mode */
+#define	AR_MAC_LED_BLINK_THRESH_SEL 0x00000070	/* LED blink threshold select */
+#define	AR_MAC_LED_MODE		0x00000380	/* LED mode select */
+#define	AR_MAC_LED_MODE_S	7
+#define	AR_MAC_LED_MODE_PROP	0	/* Blink prop to filtered tx/rx */
+#define	AR_MAC_LED_MODE_RPROP	1	/* Blink prop to unfiltered tx/rx */
+#define	AR_MAC_LED_MODE_SPLIT	2	/* Blink power for tx/net for rx */
+#define	AR_MAC_LED_MODE_RAND	3	/* Blink randomly */
+#define	AR_MAC_LED_MODE_POWON	5	/* Power LED on (s/w control) */
+#define	AR_MAC_LED_MODE_NETON	6	/* Network LED on (s/w control) */
+#define	AR_MAC_LED_ASSOC	0x00000c00
+#define	AR_MAC_LED_ASSOC_NONE	0x00000000 /* STA is not associated or trying */
+#define	AR_MAC_LED_ASSOC_ACTIVE	0x00000400 /* STA is associated */
+#define	AR_MAC_LED_ASSOC_PEND	0x00000800 /* STA is trying to associate */
+#define	AR_MAC_LED_ASSOC_S	10
+
+#define	AR_AHB_EXACT_WR_EN	0x00000000	/* write exact bytes */
+#define	AR_AHB_BUF_WR_EN	0x00000001	/* buffer write upto cacheline*/
+#define	AR_AHB_EXACT_RD_EN	0x00000000	/* read exact bytes */
+#define	AR_AHB_CACHELINE_RD_EN	0x00000002	/* read upto end of cacheline */
+#define	AR_AHB_PREFETCH_RD_EN	0x00000004	/* prefetch upto page boundary*/
+#define	AR_AHB_PAGE_SIZE_1K	0x00000000	/* set page-size as 1k */
+#define	AR_AHB_PAGE_SIZE_2K	0x00000008	/* set page-size as 2k */
+#define	AR_AHB_PAGE_SIZE_4K	0x00000010	/* set page-size as 4k */
+
+/* MAC PCU Registers */
+#define	AR_STA_ID1_PRESERVE_SEQNUM	0x20000000 /* Don't replace seq num */
+
+/* Extended PCU DIAG_SW control fields */
+#define	AR_DIAG_DUAL_CHAIN_INFO	0x01000000	/* dual chain channel info */
+#define	AR_DIAG_RX_ABORT	0x02000000	/* abort rx */
+#define	AR_DIAG_SATURATE_CCNT	0x04000000	/* sat. cycle cnts (no shift) */
+#define	AR_DIAG_OBS_PT_SEL2	0x08000000	/* observation point sel */
+#define	AR_DIAG_RXCLEAR_CTL_LOW	0x10000000	/* force rx_clear(ctl) low/busy */
+#define	AR_DIAG_RXCLEAR_EXT_LOW	0x20000000	/* force rx_clear(ext) low/busy */
+
+#define	AR_TXOP_X_VAL	0x000000FF
+
+#define	AR_RESET_TSF_ONCE	0x01000000	/* reset tsf once; self-clears*/
+
+/* Interrupts */
+#define	AR_ISR_TXMINTR		0x00080000	/* Maximum interrupt tx rate */
+#define	AR_ISR_RXMINTR		0x01000000	/* Maximum interrupt rx rate */
+#define	AR_ISR_TXINTM		0x40000000	/* Tx int after mitigation */
+#define	AR_ISR_RXINTM		0x80000000	/* Rx int after mitigation */
+
+#define	AR_ISR_S2_CST		0x00400000	/* Carrier sense timeout */
+#define	AR_ISR_S2_GTT		0x00800000	/* Global transmit timeout */
+#define	AR_ISR_S2_TSFOOR	0x40000000	/* RX TSF out of range */
+
+#define	AR_INTR_SPURIOUS	0xffffffff
+#define	AR_INTR_RTC_IRQ		0x00000001	/* rtc in shutdown state */
+#define	AR_INTR_MAC_IRQ		0x00000002	/* pending mac interrupt */
+#define	AR_INTR_EEP_PROT_ACCESS	0x00000004	/* eeprom protected access */
+#define	AR_INTR_MAC_AWAKE	0x00020000	/* mac is awake */
+#define	AR_INTR_MAC_ASLEEP	0x00040000	/* mac is asleep */
+
+/* Interrupt Mask Registers */
+#define	AR_IMR_TXMINTR		0x00080000	/* Maximum interrupt tx rate */
+#define	AR_IMR_RXMINTR		0x01000000	/* Maximum interrupt rx rate */
+#define	AR_IMR_TXINTM		0x40000000	/* Tx int after mitigation */
+#define	AR_IMR_RXINTM		0x80000000	/* Rx int after mitigation */
+
+#define	AR_IMR_S2_CST		0x00400000	/* Carrier sense timeout */
+#define	AR_IMR_S2_GTT		0x00800000	/* Global transmit timeout */
+
+/* synchronous interrupt signals */
+#define	AR_INTR_SYNC_RTC_IRQ		0x00000001
+#define	AR_INTR_SYNC_MAC_IRQ		0x00000002
+#define	AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS	0x00000004
+#define	AR_INTR_SYNC_APB_TIMEOUT	0x00000008
+#define	AR_INTR_SYNC_PCI_MODE_CONFLICT	0x00000010
+#define	AR_INTR_SYNC_HOST1_FATAL	0x00000020
+#define	AR_INTR_SYNC_HOST1_PERR		0x00000040
+#define	AR_INTR_SYNC_TRCV_FIFO_PERR	0x00000080
+#define	AR_INTR_SYNC_RADM_CPL_EP	0x00000100
+#define	AR_INTR_SYNC_RADM_CPL_DLLP_ABORT	0x00000200
+#define	AR_INTR_SYNC_RADM_CPL_TLP_ABORT	0x00000400
+#define	AR_INTR_SYNC_RADM_CPL_ECRC_ERR	0x00000800
+#define	AR_INTR_SYNC_RADM_CPL_TIMEOUT	0x00001000
+#define	AR_INTR_SYNC_LOCAL_TIMEOUT	0x00002000
+#define	AR_INTR_SYNC_PM_ACCESS		0x00004000
+#define	AR_INTR_SYNC_MAC_AWAKE		0x00008000
+#define	AR_INTR_SYNC_MAC_ASLEEP		0x00010000
+#define	AR_INTR_SYNC_MAC_SLEEP_ACCESS	0x00020000
+#define	AR_INTR_SYNC_ALL		0x0003FFFF
+
+/* default synchronous interrupt signals enabled */
+#define	AR_INTR_SYNC_DEFAULT \
+	(AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \
+	 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \
+	 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \
+	 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \
+	 AR_INTR_SYNC_MAC_SLEEP_ACCESS)
+
+/* RTC registers */
+#define	AR_RTC_RC_M		0x00000003
+#define	AR_RTC_RC_MAC_WARM	0x00000001
+#define	AR_RTC_RC_MAC_COLD	0x00000002
+#define	AR_RTC_PLL_DIV		0x0000001f
+#define	AR_RTC_PLL_DIV_S	0
+#define	AR_RTC_PLL_DIV2		0x00000020
+#define	AR_RTC_PLL_REFDIV_5	0x000000c0
+
+#define	AR_RTC_SOWL_PLL_DIV		0x000003ff
+#define	AR_RTC_SOWL_PLL_DIV_S		0
+#define	AR_RTC_SOWL_PLL_REFDIV		0x00003C00
+#define	AR_RTC_SOWL_PLL_REFDIV_S	10
+#define	AR_RTC_SOWL_PLL_CLKSEL		0x0000C000
+#define	AR_RTC_SOWL_PLL_CLKSEL_S	14
+
+#define	AR_RTC_RESET_EN		0x00000001	/* Reset RTC bit */
+
+#define	AR_RTC_PM_STATUS_M	0x0000000f	/* Pwr Mgmt Status */
+#define	AR_RTC_STATUS_M		0x0000003f	/* RTC Status */
+#define	AR_RTC_STATUS_SHUTDOWN	0x00000001
+#define	AR_RTC_STATUS_ON	0x00000002
+#define	AR_RTC_STATUS_SLEEP	0x00000004
+#define	AR_RTC_STATUS_WAKEUP	0x00000008
+#define	AR_RTC_STATUS_COLDRESET	0x00000010	/* Not currently used */
+#define	AR_RTC_STATUS_PLLCHANGE	0x00000020	/* Not currently used */
+
+#define	AR_RTC_SLEEP_DERIVED_CLK	0x2
+
+#define	AR_RTC_FORCE_WAKE_EN	0x00000001	/* enable force wake */
+#define	AR_RTC_FORCE_WAKE_ON_INT 0x00000002	/* auto-wake on MAC interrupt */
+
+#define	AR_RTC_PLL_CLKSEL	0x00000300
+#define	AR_RTC_PLL_CLKSEL_S	8
+
+/* AR9280: rf long shift registers */
+#define	AR_AN_RF2G1_CH0_OB      0x03800000
+#define	AR_AN_RF2G1_CH0_OB_S    23
+#define	AR_AN_RF2G1_CH0_DB      0x1C000000
+#define	AR_AN_RF2G1_CH0_DB_S    26
+
+#define	AR_AN_RF5G1_CH0_OB5     0x00070000
+#define	AR_AN_RF5G1_CH0_OB5_S   16
+#define	AR_AN_RF5G1_CH0_DB5     0x00380000
+#define	AR_AN_RF5G1_CH0_DB5_S   19
+
+#define	AR_AN_RF2G1_CH1_OB      0x03800000
+#define	AR_AN_RF2G1_CH1_OB_S    23
+#define	AR_AN_RF2G1_CH1_DB      0x1C000000
+#define	AR_AN_RF2G1_CH1_DB_S    26
+
+#define	AR_AN_RF5G1_CH1_OB5     0x00070000
+#define	AR_AN_RF5G1_CH1_OB5_S   16
+#define	AR_AN_RF5G1_CH1_DB5     0x00380000
+#define	AR_AN_RF5G1_CH1_DB5_S   19
+
+#define	AR_AN_TOP2_XPABIAS_LVL      0xC0000000
+#define	AR_AN_TOP2_XPABIAS_LVL_S    30
+#define	AR_AN_TOP2_LOCALBIAS        0x00200000
+#define	AR_AN_TOP2_LOCALBIAS_S      21
+#define	AR_AN_TOP2_PWDCLKIND        0x00400000
+#define	AR_AN_TOP2_PWDCLKIND_S      22
+
+#define	AR_AN_SYNTH9_REFDIVA    0xf8000000
+#define	AR_AN_SYNTH9_REFDIVA_S  27
+
+/* AR9285 Analog registers */
+#define	AR9285_AN_RF2G3_OB_0    0x00E00000
+#define	AR9285_AN_RF2G3_OB_0_S    21
+#define	AR9285_AN_RF2G3_OB_1    0x001C0000
+#define	AR9285_AN_RF2G3_OB_1_S    18
+#define	AR9285_AN_RF2G3_OB_2    0x00038000
+#define	AR9285_AN_RF2G3_OB_2_S    15
+#define	AR9285_AN_RF2G3_OB_3    0x00007000
+#define	AR9285_AN_RF2G3_OB_3_S    12
+#define	AR9285_AN_RF2G3_OB_4    0x00000E00
+#define	AR9285_AN_RF2G3_OB_4_S    9
+
+#define	AR9285_AN_RF2G3_DB1_0    0x000001C0
+#define	AR9285_AN_RF2G3_DB1_0_S    6
+#define	AR9285_AN_RF2G3_DB1_1    0x00000038
+#define	AR9285_AN_RF2G3_DB1_1_S    3
+#define	AR9285_AN_RF2G3_DB1_2    0x00000007
+#define	AR9285_AN_RF2G3_DB1_2_S    0
+#define	AR9285_AN_RF2G4         0x782C
+#define	AR9285_AN_RF2G4_DB1_3    0xE0000000
+#define	AR9285_AN_RF2G4_DB1_3_S    29
+#define	AR9285_AN_RF2G4_DB1_4    0x1C000000
+#define	AR9285_AN_RF2G4_DB1_4_S    26
+
+#define	AR9285_AN_RF2G4_DB2_0    0x03800000
+#define	AR9285_AN_RF2G4_DB2_0_S    23
+#define	AR9285_AN_RF2G4_DB2_1    0x00700000
+#define	AR9285_AN_RF2G4_DB2_1_S    20
+#define	AR9285_AN_RF2G4_DB2_2    0x000E0000
+#define	AR9285_AN_RF2G4_DB2_2_S    17
+#define	AR9285_AN_RF2G4_DB2_3    0x0001C000
+#define	AR9285_AN_RF2G4_DB2_3_S    14
+#define	AR9285_AN_RF2G4_DB2_4    0x00003800
+#define	AR9285_AN_RF2G4_DB2_4_S    11
+
+#define	AR9285_AN_TOP3_XPABIAS_LVL      0x0000000C
+#define	AR9285_AN_TOP3_XPABIAS_LVL_S    2
+
+/* Sleep control */
+#define	AR5416_SLEEP1_CAB_TIMEOUT	0xFFE00000	/* Cab timeout (TU) */
+#define	AR5416_SLEEP1_CAB_TIMEOUT_S	22
+
+#define	AR5416_SLEEP2_BEACON_TIMEOUT	0xFFE00000	/* Beacon timeout (TU)*/
+#define	AR5416_SLEEP2_BEACON_TIMEOUT_S	22
+
+/* Sleep Registers */
+#define	AR_SLP32_HALFCLK_LATENCY      0x000FFFFF	/* rising <-> falling edge */
+#define	AR_SLP32_ENA		0x00100000
+#define	AR_SLP32_TSF_WRITE_STATUS      0x00200000	/* tsf update in progress */
+
+#define	AR_SLP32_WAKE_XTL_TIME	0x0000FFFF	/* time to wake crystal */
+
+#define	AR_SLP32_TST_INC	0x000FFFFF
+
+#define	AR_SLP_MIB_CLEAR	0x00000001	/* clear pending */
+#define	AR_SLP_MIB_PENDING	0x00000002	/* clear counters */
+
+#define	AR_TIMER_MODE_TBTT		0x00000001
+#define	AR_TIMER_MODE_DBA		0x00000002
+#define	AR_TIMER_MODE_SWBA		0x00000004
+#define	AR_TIMER_MODE_HCF		0x00000008
+#define	AR_TIMER_MODE_TIM		0x00000010
+#define	AR_TIMER_MODE_DTIM		0x00000020
+#define	AR_TIMER_MODE_QUIET		0x00000040
+#define	AR_TIMER_MODE_NDP		0x00000080
+#define	AR_TIMER_MODE_OVERFLOW_INDEX	0x00000700
+#define	AR_TIMER_MODE_OVERFLOW_INDEX_S	8
+#define	AR_TIMER_MODE_THRESH		0xFFFFF000
+#define	AR_TIMER_MODE_THRESH_S		12
+
+/* PCU Misc modes */
+#define	AR_PCU_FORCE_BSSID_MATCH	0x00000001 /* force bssid to match */
+#define	AR_PCU_MIC_NEW_LOC_ENA		0x00000004 /* tx/rx mic keys together */
+#define	AR_PCU_TX_ADD_TSF		0x00000008 /* add tx_tsf + int_tsf */
+#define	AR_PCU_CCK_SIFS_MODE		0x00000010 /* assume 11b sifs */
+#define	AR_PCU_RX_ANT_UPDT		0x00000800 /* KC_RX_ANT_UPDATE */
+#define	AR_PCU_TXOP_TBTT_LIMIT_ENA	0x00001000 /* enforce txop / tbtt */
+#define	AR_PCU_MISS_BCN_IN_SLEEP	0x00004000 /* count bmiss's when sleeping */
+#define	AR_PCU_BUG_12306_FIX_ENA	0x00020000 /* use rx_clear to count sifs */
+#define	AR_PCU_FORCE_QUIET_COLL		0x00040000 /* kill xmit for channel change */
+#define	AR_PCU_TBTT_PROTECT		0x00200000 /* no xmit upto tbtt+20 uS */
+#define	AR_PCU_CLEAR_VMF		0x01000000 /* clear vmf mode (fast cc)*/
+#define	AR_PCU_CLEAR_BA_VALID		0x04000000 /* clear ba state */
+
+/* GPIO Interrupt */
+#define	AR_INTR_GPIO		0x3FF00000	/* gpio interrupted */
+#define	AR_INTR_GPIO_S		20
+
+#define	AR_GPIO_OUT_CTRL	0x000003FF	/* 0 = out, 1 = in */
+#define	AR_GPIO_OUT_VAL		0x000FFC00
+#define	AR_GPIO_OUT_VAL_S	10
+#define	AR_GPIO_INTR_CTRL	0x3FF00000
+#define	AR_GPIO_INTR_CTRL_S	20
+
+#define	AR_2040_JOINED_RX_CLEAR	0x00000001	/* use ctl + ext rx_clear for cca */
+
+#define	AR_PCU_TXBUF_CTRL_SIZE_MASK	0x7FF
+#define	AR_PCU_TXBUF_CTRL_USABLE_SIZE	0x700
+
+/* Eeprom defines */
+#define	AR_EEPROM_STATUS_DATA_VAL           0x0000ffff
+#define	AR_EEPROM_STATUS_DATA_VAL_S         0
+#define	AR_EEPROM_STATUS_DATA_BUSY          0x00010000
+#define	AR_EEPROM_STATUS_DATA_BUSY_ACCESS   0x00020000
+#define	AR_EEPROM_STATUS_DATA_PROT_ACCESS   0x00040000
+#define	AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
+
+#define	AR_SREV_REVISION_OWL_10		0x08
+#define	AR_SREV_REVISION_OWL_20		0x09
+#define	AR_SREV_REVISION_OWL_22		0x0a
+
+#define	AR_RAD5133_SREV_MAJOR		0xc0	/* Fowl: 2+5G/3x3 */
+#define	AR_RAD2133_SREV_MAJOR		0xd0	/* Fowl: 2G/3x3   */
+#define	AR_RAD5122_SREV_MAJOR		0xe0	/* Fowl: 5G/2x2   */
+#define	AR_RAD2122_SREV_MAJOR		0xf0	/* Fowl: 2+5G/2x2 */
+
+/* Test macro for owl 1.0 */
+#define	IS_5416V1(_ah)	((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10)  
+#define	IS_5416V2(_ah)	((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20)
+#define	IS_5416V2_2(_ah)	((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22) 
+
+/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */
+#define	AR_XSREV_ID		0xFFFFFFFF	/* Chip ID */
+#define	AR_XSREV_ID_S		0
+#define	AR_XSREV_VERSION	0xFFFC0000	/* Chip version */
+#define	AR_XSREV_VERSION_S	18
+#define	AR_XSREV_TYPE		0x0003F000	/* Chip type */
+#define	AR_XSREV_TYPE_S		12
+#define	AR_XSREV_TYPE_CHAIN	0x00001000	/* Chain Mode (1:3 chains,
+						 * 0:2 chains) */
+#define	AR_XSREV_TYPE_HOST_MODE 0x00002000	/* Host Mode (1:PCI, 0:PCIe) */
+#define	AR_XSREV_REVISION	0x00000F00
+#define	AR_XSREV_REVISION_S	8
+
+#define	AR_XSREV_VERSION_OWL_PCI	0x0D
+#define	AR_XSREV_VERSION_OWL_PCIE	0x0C
+#define	AR_XSREV_REVISION_OWL_10	0	/* Owl 1.0 */
+#define	AR_XSREV_REVISION_OWL_20	1	/* Owl 2.0/2.1 */
+#define	AR_XSREV_REVISION_OWL_22	2	/* Owl 2.2 */
+#define	AR_XSREV_VERSION_SOWL		0x40
+#define	AR_XSREV_REVISION_SOWL_10	0	/* Sowl 1.0 */
+#define	AR_XSREV_REVISION_SOWL_11	1	/* Sowl 1.1 */
+#define	AR_XSREV_VERSION_MERLIN		0x80	/* Merlin Version */
+#define	AR_XSREV_REVISION_MERLIN_10	0	/* Merlin 1.0 */
+#define	AR_XSREV_REVISION_MERLIN_20	1	/* Merlin 2.0 */
+#define	AR_XSREV_REVISION_MERLIN_21	2	/* Merlin 2.1 */
+#define	AR_XSREV_VERSION_KITE		0xC0	/* Kite Version */
+#define	AR_XSREV_REVISION_KITE_10	0	/* Kite 1.0 */
+
+#define	AR_SREV_OWL_20_OR_LATER(_ah) \
+	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
+	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20)
+#define	AR_SREV_OWL_22_OR_LATER(_ah) \
+	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
+	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22)
+
+#define	AR_SREV_SOWL(_ah) \
+	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL)
+#define	AR_SREV_SOWL_10_OR_LATER(_ah) \
+	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL)
+#define	AR_SREV_SOWL_11(_ah) \
+	(AR_SREV_SOWL(_ah) && \
+	 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11)
+
+#define	AR_SREV_MERLIN(_ah) \
+	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN)
+#define	AR_SREV_MERLIN_10_OR_LATER(_ah)	\
+	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN)
+#define	AR_SREV_MERLIN_20(_ah) \
+	(AR_SREV_MERLIN(_ah) && \
+	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)
+#define	AR_SREV_MERLIN_20_OR_LATER(_ah) \
+	(AR_SREV_MERLIN_20(_ah) || \
+	 AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN)
+
+#define	AR_SREV_KITE(_ah) \
+	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE)
+#define	AR_SREV_KITE_10_OR_LATER(_ah) \
+	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE)
+#endif /* _DEV_ATH_AR5416REG_H */
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar9160.ini b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar9160.ini
new file mode 100644
index 0000000..85f09a3
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar9160.ini
@@ -0,0 +1,699 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar9160.ini,v 1.5 2008/11/10 04:08:05 sam Exp $
+ */
+/* Auto Generated PCI Register Writes.  Created: 05/22/08 */
+
+static const uint32_t ar9160Modes[][6] = {
+    { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
+    { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
+    { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
+    { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
+    { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
+    { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
+    { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
+    { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
+    { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
+    { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
+    { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
+    { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
+    { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
+    { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
+    { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
+    { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
+    { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
+    { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
+    { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
+    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
+    { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
+    { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
+    { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
+    { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
+    { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
+    { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
+    { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
+    { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
+    { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
+    { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
+    { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
+    { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
+    { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
+    { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
+    { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
+    { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
+    { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
+    { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
+    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
+    { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
+    { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
+    { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
+    { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
+    { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
+    { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
+    { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
+    { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
+    { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
+    { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
+    { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
+    { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
+    { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+    { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
+static const uint32_t ar9160Common[][2] = {
+    { 0x0000000c, 0x00000000 },
+    { 0x00000030, 0x00020015 },
+    { 0x00000034, 0x00000005 },
+    { 0x00000040, 0x00000000 },
+    { 0x00000044, 0x00000008 },
+    { 0x00000048, 0x00000008 },
+    { 0x0000004c, 0x00000010 },
+    { 0x00000050, 0x00000000 },
+    { 0x00000054, 0x0000001f },
+    { 0x00000800, 0x00000000 },
+    { 0x00000804, 0x00000000 },
+    { 0x00000808, 0x00000000 },
+    { 0x0000080c, 0x00000000 },
+    { 0x00000810, 0x00000000 },
+    { 0x00000814, 0x00000000 },
+    { 0x00000818, 0x00000000 },
+    { 0x0000081c, 0x00000000 },
+    { 0x00000820, 0x00000000 },
+    { 0x00000824, 0x00000000 },
+    { 0x00001040, 0x002ffc0f },
+    { 0x00001044, 0x002ffc0f },
+    { 0x00001048, 0x002ffc0f },
+    { 0x0000104c, 0x002ffc0f },
+    { 0x00001050, 0x002ffc0f },
+    { 0x00001054, 0x002ffc0f },
+    { 0x00001058, 0x002ffc0f },
+    { 0x0000105c, 0x002ffc0f },
+    { 0x00001060, 0x002ffc0f },
+    { 0x00001064, 0x002ffc0f },
+    { 0x00001230, 0x00000000 },
+    { 0x00001270, 0x00000000 },
+    { 0x00001038, 0x00000000 },
+    { 0x00001078, 0x00000000 },
+    { 0x000010b8, 0x00000000 },
+    { 0x000010f8, 0x00000000 },
+    { 0x00001138, 0x00000000 },
+    { 0x00001178, 0x00000000 },
+    { 0x000011b8, 0x00000000 },
+    { 0x000011f8, 0x00000000 },
+    { 0x00001238, 0x00000000 },
+    { 0x00001278, 0x00000000 },
+    { 0x000012b8, 0x00000000 },
+    { 0x000012f8, 0x00000000 },
+    { 0x00001338, 0x00000000 },
+    { 0x00001378, 0x00000000 },
+    { 0x000013b8, 0x00000000 },
+    { 0x000013f8, 0x00000000 },
+    { 0x00001438, 0x00000000 },
+    { 0x00001478, 0x00000000 },
+    { 0x000014b8, 0x00000000 },
+    { 0x000014f8, 0x00000000 },
+    { 0x00001538, 0x00000000 },
+    { 0x00001578, 0x00000000 },
+    { 0x000015b8, 0x00000000 },
+    { 0x000015f8, 0x00000000 },
+    { 0x00001638, 0x00000000 },
+    { 0x00001678, 0x00000000 },
+    { 0x000016b8, 0x00000000 },
+    { 0x000016f8, 0x00000000 },
+    { 0x00001738, 0x00000000 },
+    { 0x00001778, 0x00000000 },
+    { 0x000017b8, 0x00000000 },
+    { 0x000017f8, 0x00000000 },
+    { 0x0000103c, 0x00000000 },
+    { 0x0000107c, 0x00000000 },
+    { 0x000010bc, 0x00000000 },
+    { 0x000010fc, 0x00000000 },
+    { 0x0000113c, 0x00000000 },
+    { 0x0000117c, 0x00000000 },
+    { 0x000011bc, 0x00000000 },
+    { 0x000011fc, 0x00000000 },
+    { 0x0000123c, 0x00000000 },
+    { 0x0000127c, 0x00000000 },
+    { 0x000012bc, 0x00000000 },
+    { 0x000012fc, 0x00000000 },
+    { 0x0000133c, 0x00000000 },
+    { 0x0000137c, 0x00000000 },
+    { 0x000013bc, 0x00000000 },
+    { 0x000013fc, 0x00000000 },
+    { 0x0000143c, 0x00000000 },
+    { 0x0000147c, 0x00000000 },
+    { 0x00004030, 0x00000002 },
+    { 0x0000403c, 0x00000002 },
+    { 0x00007010, 0x00000020 },
+    { 0x00007038, 0x000004c2 },
+    { 0x00008004, 0x00000000 },
+    { 0x00008008, 0x00000000 },
+    { 0x0000800c, 0x00000000 },
+    { 0x00008018, 0x00000700 },
+    { 0x00008020, 0x00000000 },
+    { 0x00008038, 0x00000000 },
+    { 0x0000803c, 0x00000000 },
+    { 0x00008048, 0x40000000 },
+    { 0x00008054, 0x00000000 },
+    { 0x00008058, 0x00000000 },
+    { 0x0000805c, 0x000fc78f },
+    { 0x00008060, 0x0000000f },
+    { 0x00008064, 0x00000000 },
+    { 0x000080c0, 0x2a82301a },
+    { 0x000080c4, 0x05dc01e0 },
+    { 0x000080c8, 0x1f402710 },
+    { 0x000080cc, 0x01f40000 },
+    { 0x000080d0, 0x00001e00 },
+    { 0x000080d4, 0x00000000 },
+    { 0x000080d8, 0x00400000 },
+    { 0x000080e0, 0xffffffff },
+    { 0x000080e4, 0x0000ffff },
+    { 0x000080e8, 0x003f3f3f },
+    { 0x000080ec, 0x00000000 },
+    { 0x000080f0, 0x00000000 },
+    { 0x000080f4, 0x00000000 },
+    { 0x000080f8, 0x00000000 },
+    { 0x000080fc, 0x00020000 },
+    { 0x00008100, 0x00020000 },
+    { 0x00008104, 0x00000001 },
+    { 0x00008108, 0x00000052 },
+    { 0x0000810c, 0x00000000 },
+    { 0x00008110, 0x00000168 },
+    { 0x00008118, 0x000100aa },
+    { 0x0000811c, 0x00003210 },
+    { 0x00008120, 0x08f04800 },
+    { 0x00008124, 0x00000000 },
+    { 0x00008128, 0x00000000 },
+    { 0x0000812c, 0x00000000 },
+    { 0x00008130, 0x00000000 },
+    { 0x00008134, 0x00000000 },
+    { 0x00008138, 0x00000000 },
+    { 0x0000813c, 0x00000000 },
+    { 0x00008144, 0x00000000 },
+    { 0x00008168, 0x00000000 },
+    { 0x0000816c, 0x00000000 },
+    { 0x00008170, 0x32143320 },
+    { 0x00008174, 0xfaa4fa50 },
+    { 0x00008178, 0x00000100 },
+    { 0x0000817c, 0x00000000 },
+    { 0x000081c4, 0x00000000 },
+    { 0x000081d0, 0x00003210 },
+    { 0x000081ec, 0x00000000 },
+    { 0x000081f0, 0x00000000 },
+    { 0x000081f4, 0x00000000 },
+    { 0x000081f8, 0x00000000 },
+    { 0x000081fc, 0x00000000 },
+    { 0x00008200, 0x00000000 },
+    { 0x00008204, 0x00000000 },
+    { 0x00008208, 0x00000000 },
+    { 0x0000820c, 0x00000000 },
+    { 0x00008210, 0x00000000 },
+    { 0x00008214, 0x00000000 },
+    { 0x00008218, 0x00000000 },
+    { 0x0000821c, 0x00000000 },
+    { 0x00008220, 0x00000000 },
+    { 0x00008224, 0x00000000 },
+    { 0x00008228, 0x00000000 },
+    { 0x0000822c, 0x00000000 },
+    { 0x00008230, 0x00000000 },
+    { 0x00008234, 0x00000000 },
+    { 0x00008238, 0x00000000 },
+    { 0x0000823c, 0x00000000 },
+    { 0x00008240, 0x00100000 },
+    { 0x00008244, 0x0010f400 },
+    { 0x00008248, 0x00000100 },
+    { 0x0000824c, 0x0001e800 },
+    { 0x00008250, 0x00000000 },
+    { 0x00008254, 0x00000000 },
+    { 0x00008258, 0x00000000 },
+    { 0x0000825c, 0x400000ff },
+    { 0x00008260, 0x00080922 },
+    { 0x00008270, 0x00000000 },
+    { 0x00008274, 0x40000000 },
+    { 0x00008278, 0x003e4180 },
+    { 0x0000827c, 0x00000000 },
+    { 0x00008284, 0x0000002c },
+    { 0x00008288, 0x0000002c },
+    { 0x0000828c, 0x00000000 },
+    { 0x00008294, 0x00000000 },
+    { 0x00008298, 0x00000000 },
+    { 0x00008300, 0x00000000 },
+    { 0x00008304, 0x00000000 },
+    { 0x00008308, 0x00000000 },
+    { 0x0000830c, 0x00000000 },
+    { 0x00008310, 0x00000000 },
+    { 0x00008314, 0x00000000 },
+    { 0x00008318, 0x00000000 },
+    { 0x00008328, 0x00000000 },
+    { 0x0000832c, 0x00000007 },
+    { 0x00008330, 0x00000302 },
+    { 0x00008334, 0x00000e00 },
+    { 0x00008338, 0x00000000 },
+    { 0x0000833c, 0x00000000 },
+    { 0x00008340, 0x000107ff },
+    { 0x00009808, 0x00000000 },
+    { 0x0000980c, 0xad848e19 },
+    { 0x00009810, 0x7d14e000 },
+    { 0x00009814, 0x9c0a9f6b },
+    { 0x0000981c, 0x00000000 },
+    { 0x0000982c, 0x0000a000 },
+    { 0x00009830, 0x00000000 },
+    { 0x0000983c, 0x00200400 },
+    { 0x00009840, 0x206a01ae },
+    { 0x0000984c, 0x1284233c },
+    { 0x00009854, 0x00000859 },
+    { 0x00009900, 0x00000000 },
+    { 0x00009904, 0x00000000 },
+    { 0x00009908, 0x00000000 },
+    { 0x0000990c, 0x00000000 },
+    { 0x0000991c, 0x10000fff },
+    { 0x00009920, 0x05100000 },
+    { 0x0000a920, 0x05100000 },
+    { 0x0000b920, 0x05100000 },
+    { 0x00009928, 0x00000001 },
+    { 0x0000992c, 0x00000004 },
+    { 0x00009934, 0x1e1f2022 },
+    { 0x00009938, 0x0a0b0c0d },
+    { 0x0000993c, 0x00000000 },
+    { 0x00009948, 0x9280b212 },
+    { 0x0000994c, 0x00020028 },
+    { 0x00009954, 0x5f3ca3de },
+    { 0x00009958, 0x2108ecff },
+    { 0x00009940, 0x00750604 },
+    { 0x0000c95c, 0x004b6a8e },
+    { 0x00009970, 0x190fb515 },
+    { 0x00009974, 0x00000000 },
+    { 0x00009978, 0x00000001 },
+    { 0x0000997c, 0x00000000 },
+    { 0x00009980, 0x00000000 },
+    { 0x00009984, 0x00000000 },
+    { 0x00009988, 0x00000000 },
+    { 0x0000998c, 0x00000000 },
+    { 0x00009990, 0x00000000 },
+    { 0x00009994, 0x00000000 },
+    { 0x00009998, 0x00000000 },
+    { 0x0000999c, 0x00000000 },
+    { 0x000099a0, 0x00000000 },
+    { 0x000099a4, 0x00000001 },
+    { 0x000099a8, 0x201fff00 },
+    { 0x000099ac, 0x006f0000 },
+    { 0x000099b0, 0x03051000 },
+    { 0x000099dc, 0x00000000 },
+    { 0x000099e0, 0x00000200 },
+    { 0x000099e4, 0xaaaaaaaa },
+    { 0x000099e8, 0x3c466478 },
+    { 0x000099ec, 0x0cc80caa },
+    { 0x000099fc, 0x00001042 },
+    { 0x00009b00, 0x00000000 },
+    { 0x00009b04, 0x00000001 },
+    { 0x00009b08, 0x00000002 },
+    { 0x00009b0c, 0x00000003 },
+    { 0x00009b10, 0x00000004 },
+    { 0x00009b14, 0x00000005 },
+    { 0x00009b18, 0x00000008 },
+    { 0x00009b1c, 0x00000009 },
+    { 0x00009b20, 0x0000000a },
+    { 0x00009b24, 0x0000000b },
+    { 0x00009b28, 0x0000000c },
+    { 0x00009b2c, 0x0000000d },
+    { 0x00009b30, 0x00000010 },
+    { 0x00009b34, 0x00000011 },
+    { 0x00009b38, 0x00000012 },
+    { 0x00009b3c, 0x00000013 },
+    { 0x00009b40, 0x00000014 },
+    { 0x00009b44, 0x00000015 },
+    { 0x00009b48, 0x00000018 },
+    { 0x00009b4c, 0x00000019 },
+    { 0x00009b50, 0x0000001a },
+    { 0x00009b54, 0x0000001b },
+    { 0x00009b58, 0x0000001c },
+    { 0x00009b5c, 0x0000001d },
+    { 0x00009b60, 0x00000020 },
+    { 0x00009b64, 0x00000021 },
+    { 0x00009b68, 0x00000022 },
+    { 0x00009b6c, 0x00000023 },
+    { 0x00009b70, 0x00000024 },
+    { 0x00009b74, 0x00000025 },
+    { 0x00009b78, 0x00000028 },
+    { 0x00009b7c, 0x00000029 },
+    { 0x00009b80, 0x0000002a },
+    { 0x00009b84, 0x0000002b },
+    { 0x00009b88, 0x0000002c },
+    { 0x00009b8c, 0x0000002d },
+    { 0x00009b90, 0x00000030 },
+    { 0x00009b94, 0x00000031 },
+    { 0x00009b98, 0x00000032 },
+    { 0x00009b9c, 0x00000033 },
+    { 0x00009ba0, 0x00000034 },
+    { 0x00009ba4, 0x00000035 },
+    { 0x00009ba8, 0x00000035 },
+    { 0x00009bac, 0x00000035 },
+    { 0x00009bb0, 0x00000035 },
+    { 0x00009bb4, 0x00000035 },
+    { 0x00009bb8, 0x00000035 },
+    { 0x00009bbc, 0x00000035 },
+    { 0x00009bc0, 0x00000035 },
+    { 0x00009bc4, 0x00000035 },
+    { 0x00009bc8, 0x00000035 },
+    { 0x00009bcc, 0x00000035 },
+    { 0x00009bd0, 0x00000035 },
+    { 0x00009bd4, 0x00000035 },
+    { 0x00009bd8, 0x00000035 },
+    { 0x00009bdc, 0x00000035 },
+    { 0x00009be0, 0x00000035 },
+    { 0x00009be4, 0x00000035 },
+    { 0x00009be8, 0x00000035 },
+    { 0x00009bec, 0x00000035 },
+    { 0x00009bf0, 0x00000035 },
+    { 0x00009bf4, 0x00000035 },
+    { 0x00009bf8, 0x00000010 },
+    { 0x00009bfc, 0x0000001a },
+    { 0x0000a210, 0x40806333 },
+    { 0x0000a214, 0x00106c10 },
+    { 0x0000a218, 0x009c4060 },
+    { 0x0000a220, 0x018830c6 },
+    { 0x0000a224, 0x00000400 },
+    { 0x0000a228, 0x001a0bb5 },
+    { 0x0000a22c, 0x00000000 },
+    { 0x0000a234, 0x20202020 },
+    { 0x0000a238, 0x20202020 },
+    { 0x0000a23c, 0x13c889af },
+    { 0x0000a240, 0x38490a20 },
+    { 0x0000a244, 0x00007bb6 },
+    { 0x0000a248, 0x0fff3ffc },
+    { 0x0000a24c, 0x00000001 },
+    { 0x0000a250, 0x0000a000 },
+    { 0x0000a254, 0x00000000 },
+    { 0x0000a258, 0x0cc75380 },
+    { 0x0000a25c, 0x0f0f0f01 },
+    { 0x0000a260, 0xdfa91f01 },
+    { 0x0000a268, 0x00000001 },
+    { 0x0000a26c, 0x0ebae9c6 },
+    { 0x0000b26c, 0x0ebae9c6 },
+    { 0x0000c26c, 0x0ebae9c6 },
+    { 0x0000d270, 0x00820820 },
+    { 0x0000a278, 0x1ce739ce },
+    { 0x0000a27c, 0x050701ce },
+    { 0x0000a338, 0x00000000 },
+    { 0x0000a33c, 0x00000000 },
+    { 0x0000a340, 0x00000000 },
+    { 0x0000a344, 0x00000000 },
+    { 0x0000a348, 0x3fffffff },
+    { 0x0000a34c, 0x3fffffff },
+    { 0x0000a350, 0x3fffffff },
+    { 0x0000a354, 0x0003ffff },
+    { 0x0000a358, 0x79a8aa33 },
+    { 0x0000d35c, 0x07ffffef },
+    { 0x0000d360, 0x0fffffe7 },
+    { 0x0000d364, 0x17ffffe5 },
+    { 0x0000d368, 0x1fffffe4 },
+    { 0x0000d36c, 0x37ffffe3 },
+    { 0x0000d370, 0x3fffffe3 },
+    { 0x0000d374, 0x57ffffe3 },
+    { 0x0000d378, 0x5fffffe2 },
+    { 0x0000d37c, 0x7fffffe2 },
+    { 0x0000d380, 0x7f3c7bba },
+    { 0x0000d384, 0xf3307ff0 },
+    { 0x0000a388, 0x0c000000 },
+    { 0x0000a38c, 0x20202020 },
+    { 0x0000a390, 0x20202020 },
+    { 0x0000a394, 0x1ce739ce },
+    { 0x0000a398, 0x000001ce },
+    { 0x0000a39c, 0x00000001 },
+    { 0x0000a3a0, 0x00000000 },
+    { 0x0000a3a4, 0x00000000 },
+    { 0x0000a3a8, 0x00000000 },
+    { 0x0000a3ac, 0x00000000 },
+    { 0x0000a3b0, 0x00000000 },
+    { 0x0000a3b4, 0x00000000 },
+    { 0x0000a3b8, 0x00000000 },
+    { 0x0000a3bc, 0x00000000 },
+    { 0x0000a3c0, 0x00000000 },
+    { 0x0000a3c4, 0x00000000 },
+    { 0x0000a3c8, 0x00000246 },
+    { 0x0000a3cc, 0x20202020 },
+    { 0x0000a3d0, 0x20202020 },
+    { 0x0000a3d4, 0x20202020 },
+    { 0x0000a3dc, 0x1ce739ce },
+    { 0x0000a3e0, 0x000001ce },
+};
+
+static const uint32_t ar9160Bank0[][2] = {
+    { 0x000098b0, 0x1e5795e5 },
+    { 0x000098e0, 0x02008020 },
+};
+
+static const uint32_t ar9160BB_RfGain[][3] = {
+    { 0x00009a00, 0x00000000, 0x00000000 },
+    { 0x00009a04, 0x00000040, 0x00000040 },
+    { 0x00009a08, 0x00000080, 0x00000080 },
+    { 0x00009a0c, 0x000001a1, 0x00000141 },
+    { 0x00009a10, 0x000001e1, 0x00000181 },
+    { 0x00009a14, 0x00000021, 0x000001c1 },
+    { 0x00009a18, 0x00000061, 0x00000001 },
+    { 0x00009a1c, 0x00000168, 0x00000041 },
+    { 0x00009a20, 0x000001a8, 0x000001a8 },
+    { 0x00009a24, 0x000001e8, 0x000001e8 },
+    { 0x00009a28, 0x00000028, 0x00000028 },
+    { 0x00009a2c, 0x00000068, 0x00000068 },
+    { 0x00009a30, 0x00000189, 0x000000a8 },
+    { 0x00009a34, 0x000001c9, 0x00000169 },
+    { 0x00009a38, 0x00000009, 0x000001a9 },
+    { 0x00009a3c, 0x00000049, 0x000001e9 },
+    { 0x00009a40, 0x00000089, 0x00000029 },
+    { 0x00009a44, 0x00000170, 0x00000069 },
+    { 0x00009a48, 0x000001b0, 0x00000190 },
+    { 0x00009a4c, 0x000001f0, 0x000001d0 },
+    { 0x00009a50, 0x00000030, 0x00000010 },
+    { 0x00009a54, 0x00000070, 0x00000050 },
+    { 0x00009a58, 0x00000191, 0x00000090 },
+    { 0x00009a5c, 0x000001d1, 0x00000151 },
+    { 0x00009a60, 0x00000011, 0x00000191 },
+    { 0x00009a64, 0x00000051, 0x000001d1 },
+    { 0x00009a68, 0x00000091, 0x00000011 },
+    { 0x00009a6c, 0x000001b8, 0x00000051 },
+    { 0x00009a70, 0x000001f8, 0x00000198 },
+    { 0x00009a74, 0x00000038, 0x000001d8 },
+    { 0x00009a78, 0x00000078, 0x00000018 },
+    { 0x00009a7c, 0x00000199, 0x00000058 },
+    { 0x00009a80, 0x000001d9, 0x00000098 },
+    { 0x00009a84, 0x00000019, 0x00000159 },
+    { 0x00009a88, 0x00000059, 0x00000199 },
+    { 0x00009a8c, 0x00000099, 0x000001d9 },
+    { 0x00009a90, 0x000000d9, 0x00000019 },
+    { 0x00009a94, 0x000000f9, 0x00000059 },
+    { 0x00009a98, 0x000000f9, 0x00000099 },
+    { 0x00009a9c, 0x000000f9, 0x000000d9 },
+    { 0x00009aa0, 0x000000f9, 0x000000f9 },
+    { 0x00009aa4, 0x000000f9, 0x000000f9 },
+    { 0x00009aa8, 0x000000f9, 0x000000f9 },
+    { 0x00009aac, 0x000000f9, 0x000000f9 },
+    { 0x00009ab0, 0x000000f9, 0x000000f9 },
+    { 0x00009ab4, 0x000000f9, 0x000000f9 },
+    { 0x00009ab8, 0x000000f9, 0x000000f9 },
+    { 0x00009abc, 0x000000f9, 0x000000f9 },
+    { 0x00009ac0, 0x000000f9, 0x000000f9 },
+    { 0x00009ac4, 0x000000f9, 0x000000f9 },
+    { 0x00009ac8, 0x000000f9, 0x000000f9 },
+    { 0x00009acc, 0x000000f9, 0x000000f9 },
+    { 0x00009ad0, 0x000000f9, 0x000000f9 },
+    { 0x00009ad4, 0x000000f9, 0x000000f9 },
+    { 0x00009ad8, 0x000000f9, 0x000000f9 },
+    { 0x00009adc, 0x000000f9, 0x000000f9 },
+    { 0x00009ae0, 0x000000f9, 0x000000f9 },
+    { 0x00009ae4, 0x000000f9, 0x000000f9 },
+    { 0x00009ae8, 0x000000f9, 0x000000f9 },
+    { 0x00009aec, 0x000000f9, 0x000000f9 },
+    { 0x00009af0, 0x000000f9, 0x000000f9 },
+    { 0x00009af4, 0x000000f9, 0x000000f9 },
+    { 0x00009af8, 0x000000f9, 0x000000f9 },
+    { 0x00009afc, 0x000000f9, 0x000000f9 },
+};
+
+static const uint32_t ar9160Bank1[][2] = {
+    { 0x000098b0, 0x02108421 },
+    { 0x000098ec, 0x00000008 },
+};
+
+static const uint32_t ar9160Bank2[][2] = {
+    { 0x000098b0, 0x0e73ff17 },
+    { 0x000098e0, 0x00000420 },
+};
+
+static const uint32_t ar9160Bank3[][3] = {
+    { 0x000098f0, 0x01400018, 0x01c00018 },
+};
+
+static const uint32_t ar9160Bank6[][3] = {
+/*    Reg      A            G            */
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00e00000, 0x00e00000 },
+    { 0x0000989c, 0x005e0000, 0x005e0000 },
+    { 0x0000989c, 0x00120000, 0x00120000 },
+    { 0x0000989c, 0x00620000, 0x00620000 },
+    { 0x0000989c, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x40ff0000, 0x40ff0000 },
+    { 0x0000989c, 0x005f0000, 0x005f0000 },
+    { 0x0000989c, 0x00870000, 0x00870000 },
+    { 0x0000989c, 0x00f90000, 0x00f90000 },
+    { 0x0000989c, 0x007b0000, 0x007b0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00f50000, 0x00f50000 },
+    { 0x0000989c, 0x00dc0000, 0x00dc0000 },
+    { 0x0000989c, 0x00110000, 0x00110000 },
+    { 0x0000989c, 0x006100a8, 0x006100a8 },
+    { 0x0000989c, 0x004210a2, 0x004210a2 },
+    { 0x0000989c, 0x0014008f, 0x0014008f },
+    { 0x0000989c, 0x00c40003, 0x00c40003 },
+    { 0x0000989c, 0x003000f2, 0x003000f2 },
+    { 0x0000989c, 0x00440016, 0x00440016 },
+    { 0x0000989c, 0x00410040, 0x00410040 },
+    { 0x0000989c, 0x0001805e, 0x0001805e },
+    { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
+    { 0x0000989c, 0x000000f1, 0x000000f1 },
+    { 0x0000989c, 0x00002081, 0x00002081 },
+    { 0x0000989c, 0x000000d4, 0x000000d4 },
+    { 0x000098d0, 0x0000000f, 0x0010000f },
+};
+
+static const uint32_t ar9160Bank6TPC[][3] = {
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00000000, 0x00000000 },
+    { 0x0000989c, 0x00e00000, 0x00e00000 },
+    { 0x0000989c, 0x005e0000, 0x005e0000 },
+    { 0x0000989c, 0x00120000, 0x00120000 },
+    { 0x0000989c, 0x00620000, 0x00620000 },
+    { 0x0000989c, 0x00020000, 0x00020000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x40ff0000, 0x40ff0000 },
+    { 0x0000989c, 0x005f0000, 0x005f0000 },
+    { 0x0000989c, 0x00870000, 0x00870000 },
+    { 0x0000989c, 0x00f90000, 0x00f90000 },
+    { 0x0000989c, 0x007b0000, 0x007b0000 },
+    { 0x0000989c, 0x00ff0000, 0x00ff0000 },
+    { 0x0000989c, 0x00f50000, 0x00f50000 },
+    { 0x0000989c, 0x00dc0000, 0x00dc0000 },
+    { 0x0000989c, 0x00110000, 0x00110000 },
+    { 0x0000989c, 0x006100a8, 0x006100a8 },
+    { 0x0000989c, 0x00423022, 0x00423022 },
+    { 0x0000989c, 0x2014008f, 0x2014008f },
+    { 0x0000989c, 0x00c40002, 0x00c40002 },
+    { 0x0000989c, 0x003000f2, 0x003000f2 },
+    { 0x0000989c, 0x00440016, 0x00440016 },
+    { 0x0000989c, 0x00410040, 0x00410040 },
+    { 0x0000989c, 0x0001805e, 0x0001805e },
+    { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
+    { 0x0000989c, 0x000000e1, 0x000000e1 },
+    { 0x0000989c, 0x00007080, 0x00007080 },
+    { 0x0000989c, 0x000000d4, 0x000000d4 },
+    { 0x000098d0, 0x0000000f, 0x0010000f },
+};
+
+static const uint32_t ar9160Bank7[][2] = {
+    { 0x0000989c, 0x00000500 },
+    { 0x0000989c, 0x00000800 },
+    { 0x000098cc, 0x0000000e },
+};
+
+/* Auto generated PCI Register Writes for SOWL1.0 ADDAC Shift Chain */
+static const uint32_t ar9160Addac[][2] = {
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x000000c0 },
+    {0x0000989c,  0x00000018 },
+    {0x0000989c,  0x00000004 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x000000c0 },
+    {0x0000989c,  0x00000019 },
+    {0x0000989c,  0x00000004 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000004 },
+    {0x0000989c,  0x00000003 },
+    {0x0000989c,  0x00000008 },
+    {0x0000989c,  0x00000000 },
+    {0x000098cc,  0x00000000 },
+};
+
+/* Auto generated PCI Register Writes for SOWL1.1 ADDAC Shift Chain */
+static const uint32_t ar9160Addac_1_1[][2] = {
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x000000c0 },
+    {0x0000989c,  0x00000018 },
+    {0x0000989c,  0x00000004 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x000000c0 },
+    {0x0000989c,  0x00000019 },
+    {0x0000989c,  0x00000004 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x0000989c,  0x00000000 },
+    {0x000098cc,  0x00000000 },
+};
diff --git a/sys/dev/netif/ath/hal/ath_hal/ar5416/ar9160_attach.c b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar9160_attach.c
new file mode 100644
index 0000000..f92c3a6
--- /dev/null
+++ b/sys/dev/netif/ath/hal/ath_hal/ar5416/ar9160_attach.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ar9160_attach.c,v 1.14 2008/11/27 22:30:08 sam Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+#include "ar5416/ar5416.h"
+#include "ar5416/ar5416reg.h"
+#include "ar5416/ar5416phy.h"
+
+#include "ar5416/ar9160.ini"
+
+static const HAL_PERCAL_DATA ar9160_iq_cal = {		/* multi sample */
+	.calName = "IQ", .calType = IQ_MISMATCH_CAL,
+	.calNumSamples	= MAX_CAL_SAMPLES,
+	.calCountMax	= PER_MIN_LOG_COUNT,
+	.calCollect	= ar5416IQCalCollect,
+	.calPostProc	= ar5416IQCalibration
+};
+static const HAL_PERCAL_DATA ar9160_adc_gain_cal = {	/* multi sample */
+	.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
+	.calNumSamples	= MAX_CAL_SAMPLES,
+	.calCountMax	= PER_MIN_LOG_COUNT,
+	.calCollect	= ar5416AdcGainCalCollect,
+	.calPostProc	= ar5416AdcGainCalibration
+};
+static const HAL_PERCAL_DATA ar9160_adc_dc_cal = {	/* multi sample */
+	.calName = "ADC DC", .calType = ADC_DC_CAL,
+	.calNumSamples	= MAX_CAL_SAMPLES,
+	.calCountMax	= PER_MIN_LOG_COUNT,
+	.calCollect	= ar5416AdcDcCalCollect,
+	.calPostProc	= ar5416AdcDcCalibration
+};
+static const HAL_PERCAL_DATA ar9160_adc_init_dc_cal = {
+	.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
+	.calNumSamples	= MIN_CAL_SAMPLES,
+	.calCountMax	= INIT_LOG_COUNT,
+	.calCollect	= ar5416AdcDcCalCollect,
+	.calPostProc	= ar5416AdcDcCalibration
+};
+
+struct ath_hal *ar9160Attach(uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
+static void ar9160Detach(struct ath_hal *);
+static HAL_BOOL ar9160FillCapabilityInfo(struct ath_hal *ah);
+
+static void
+ar9160AniSetup(struct ath_hal *ah)
+{
+	static const struct ar5212AniParams aniparams = {
+		.maxNoiseImmunityLevel	= 4,	/* levels 0..4 */
+		.totalSizeDesired	= { -55, -55, -55, -55, -62 },
+		.coarseHigh		= { -14, -14, -14, -14, -12 },
+		.coarseLow		= { -64, -64, -64, -64, -70 },
+		.firpwr			= { -78, -78, -78, -78, -80 },
+		.maxSpurImmunityLevel	= 2,
+		.cycPwrThr1		= { 2, 4, 6 },
+		.maxFirstepLevel	= 2,	/* levels 0..2 */
+		.firstep		= { 0, 4, 8 },
+		.ofdmTrigHigh		= 500,
+		.ofdmTrigLow		= 200,
+		.cckTrigHigh		= 200,
+		.cckTrigLow		= 100,
+		.rssiThrHigh		= 40,
+		.rssiThrLow		= 7,
+		.period			= 100,
+	};
+	/* NB: ANI is not enabled yet */
+	ar5212AniAttach(ah, &aniparams, &aniparams, AH_FALSE);
+}
+
+/*
+ * Attach for an AR9160 part.
+ */
+struct ath_hal *
+ar9160Attach(uint16_t devid, HAL_SOFTC sc,
+	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
+{
+	struct ath_hal_5416 *ahp5416;
+	struct ath_hal_5212 *ahp;
+	struct ath_hal *ah;
+	uint32_t val;
+	HAL_STATUS ecode;
+	HAL_BOOL rfStatus;
+
+	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
+	    __func__, sc, (void*) st, (void*) sh);
+
+	/* NB: memory is returned zero'd */
+	ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416));
+	if (ahp5416 == AH_NULL) {
+		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
+		    "%s: cannot allocate memory for state block\n", __func__);
+		*status = HAL_ENOMEM;
+		return AH_NULL;
+	}
+	ar5416InitState(ahp5416, devid, sc, st, sh, status);
+	ahp = &ahp5416->ah_5212;
+	ah = &ahp->ah_priv.h;
+
+	/* XXX override with 9160 specific state */
+	/* override 5416 methods for our needs */
+	ah->ah_detach			= ar9160Detach;
+
+	AH5416(ah)->ah_cal.iqCalData.calData = &ar9160_iq_cal;
+	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9160_adc_gain_cal;
+	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9160_adc_dc_cal;
+	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9160_adc_init_dc_cal;
+	AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
+
+	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
+		/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
+		    __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
+		    __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+	/* Read Revisions from Chips before taking out of reset */
+	val = OS_REG_READ(ah, AR_SREV);
+	HALDEBUG(ah, HAL_DEBUG_ATTACH,
+	    "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
+	    __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
+	    MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
+	/* NB: include chip type to differentiate from pre-Sowl versions */
+	AH_PRIVATE(ah)->ah_macVersion =
+	    (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
+	AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
+	/* XXX extract pcie info */
+
+	/* setup common ini data; rf backends handle remainder */
+	HAL_INI_INIT(&ahp->ah_ini_modes, ar9160Modes, 6);
+	HAL_INI_INIT(&ahp->ah_ini_common, ar9160Common, 2);
+
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar9160BB_RfGain, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar9160Bank0, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar9160Bank1, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar9160Bank2, 2);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar9160Bank3, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar9160Bank6, 3);
+	HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar9160Bank7, 2);
+	if (AR_SREV_SOWL_11(ah))
+		HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar9160Addac_1_1, 2);
+	else
+		HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar9160Addac, 2);
+
+	if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
+		ecode = HAL_EIO;
+		goto bad;
+	}
+
+	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
+
+	if (!ar5212ChipTest(ah)) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
+		    __func__);
+		ecode = HAL_ESELFTEST;
+		goto bad;
+	}
+
+	/*
+	 * Set correct Baseband to analog shift
+	 * setting to access analog chips.
+	 */
+	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
+
+	/* Read Radio Chip Rev Extract */
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
+	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
+        case AR_RAD2133_SREV_MAJOR:	/* Sowl: 2G/3x3 */
+	case AR_RAD5133_SREV_MAJOR:	/* Sowl: 2+5G/3x3 */
+		break;
+	default:
+		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
+			AH_PRIVATE(ah)->ah_analog5GhzRev =
+				AR_RAD5133_SREV_MAJOR;
+			break;
+		}
+#ifdef AH_DEBUG
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
+		    "this driver\n", __func__,
+		    AH_PRIVATE(ah)->ah_analog5GhzRev);
+		ecode = HAL_ENOTSUPP;
+		goto bad;
+#endif
+	}
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: Attaching AR2133 radio\n",
+	    __func__);
+	rfStatus = ar2133RfAttach(ah, &ecode);
+	if (!rfStatus) {
+		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
+		    __func__, ecode);
+		goto bad;
+	}
+
+	ecode = ath_hal_v14EepromAttach(ah);
+	if (ecode != HAL_OK)
+		goto bad;
+
+	/*
+	 * Got everything we need now to setup the capabilities.
+	 */
+	if (!ar9160FillCapabilityInfo(ah)) {
+		ecode = HAL_EEREAD;
+		goto bad;
+	}
+
+	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
+	if (ecode != HAL_OK) {
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: error getting mac address from EEPROM\n", __func__);
+		goto bad;
+        }
+	/* XXX How about the serial number ? */
+	/* Read Reg Domain */
+	AH_PRIVATE(ah)->ah_currentRD =
+	    ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
+
+	/*
+	 * ah_miscMode is populated by ar5416FillCapabilityInfo()
+	 * starting from griffin. Set here to make sure that
+	 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
+	 * placed into hardware.
+	 */
+	if (ahp->ah_miscMode != 0)
+		OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
+
+	ar9160AniSetup(ah);			/* Anti Noise Immunity */
+	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
+
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
+
+	return ah;
+bad:
+	if (ahp)
+		ar9160Detach((struct ath_hal *) ahp);
+	if (status)
+		*status = ecode;
+	return AH_NULL;
+}
+
+void
+ar9160Detach(struct ath_hal *ah)
+{
+	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
+
+	HALASSERT(ah != AH_NULL);
+	HALASSERT(ah->ah_magic == AR5416_MAGIC);
+
+	ar5416Detach(ah);
+}
+
+/*
+ * Fill all software cached or static hardware state information.
+ * Return failure if capabilities are to come from EEPROM and
+ * cannot be read.
+ */
+static HAL_BOOL
+ar9160FillCapabilityInfo(struct ath_hal *ah)
+{
+	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+
+	if (!ar5416FillCapabilityInfo(ah))
+		return AH_FALSE;
+	pCap->halCSTSupport = AH_TRUE;
+	pCap->halRifsRxSupport = AH_TRUE;
+	pCap->halRifsTxSupport = AH_TRUE;
+	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
+	pCap->halExtChanDfsSupport = AH_TRUE;
+	pCap->halAutoSleepSupport = AH_FALSE;	/* XXX? */
+	return AH_TRUE;
+}
+
+static const char*
+ar9160Probe(uint16_t vendorid, uint16_t devid)
+{
+	if (vendorid == ATHEROS_VENDOR_ID && devid == AR9160_DEVID_PCI)
+		return "Atheros 9160";
+	return AH_NULL;
+}
+AH_CHIP(AR9160, ar9160Probe, ar9160Attach);
diff --git a/sys/dev/netif/ath/hal/opt_ah.h b/sys/dev/netif/ath/hal/opt_ah.h
new file mode 100644
index 0000000..41bc951
--- /dev/null
+++ b/sys/dev/netif/ath/hal/opt_ah.h
@@ -0,0 +1 @@
+#define AH_SUPPORT_AR5416 1
diff --git a/sys/dev/netif/ath/rate_amrr/amrr.c b/sys/dev/netif/ath/rate_amrr/amrr.c
index 73f1748..3dff3ec 100644
--- a/sys/dev/netif/ath/rate_amrr/amrr.c
+++ b/sys/dev/netif/ath/rate_amrr/amrr.c
@@ -67,7 +67,7 @@
 
 #include <dev/netif/ath/ath/if_athvar.h>
 #include <dev/netif/ath/rate_amrr/amrr.h>
-#include <contrib/dev/ath/ah_desc.h>
+#include <dev/netif/ath/hal/ath_hal/ah_desc.h>
 
 #define	AMRR_DEBUG
 #ifdef AMRR_DEBUG
diff --git a/sys/dev/netif/ath/rate_onoe/onoe.c b/sys/dev/netif/ath/rate_onoe/onoe.c
index d011e46..9e1dedc 100644
--- a/sys/dev/netif/ath/rate_onoe/onoe.c
+++ b/sys/dev/netif/ath/rate_onoe/onoe.c
@@ -64,7 +64,7 @@
 
 #include <dev/netif/ath/ath/if_athvar.h>
 #include <dev/netif/ath/rate_onoe/onoe.h>
-#include <contrib/dev/ath/ah_desc.h>
+#include <dev/netif/ath/hal/ath_hal/ah_desc.h>
 
 #define	ONOE_DEBUG
 #ifdef ONOE_DEBUG
diff --git a/sys/dev/netif/ath/rate_sample/sample.c b/sys/dev/netif/ath/rate_sample/sample.c
index 16ad29f..920a004 100644
--- a/sys/dev/netif/ath/rate_sample/sample.c
+++ b/sys/dev/netif/ath/rate_sample/sample.c
@@ -62,7 +62,7 @@
 
 #include <dev/netif/ath/ath/if_athvar.h>
 #include <dev/netif/ath/rate_sample/sample.h>
-#include <contrib/dev/ath/ah_desc.h>
+#include <dev/netif/ath/hal/ath_hal/ah_desc.h>
 
 #define	SAMPLE_DEBUG
 #ifdef SAMPLE_DEBUG
