DragonFly users List (threaded) for 2005-02
Re: Dragonfly and Hyperthreading....
:> viable up till now because Intel's cpu architecture sucks rocks compared
:> with AMD's, but Intel can no longer compete by boosting clock rate so
:> now they are stuck... they have to slow their cpus down and make them
:> more efficient, and that will kill HT's effectiveness even if you
:> ignore the heat issue.
:Maybe HT will be the only way to gain more effectiveness with lower
:clock frequency on netburst (P4).
:My point of interested is what's AMD making better?
No, HT definitely has nothing to do with reducing clock frequency on
the P4. You can't reduce the clock basis for, e.g. the pipeline and
still run the execution units at full speed and hope to have something
that still works well. Ht has everything to do with utiliziing
otherwise idle resources. Nobody is going to purposefully idle
resources just to make HT work more efficiently because that would
destroy UP performance.
Here's a starter on the AMD Opteron's cpu architecture. It's long but
it's colorful and very easy reading, and it will give you an idea of
what it takes to design a fast cpu:
The simple fact of the matter is that there are so many good reasons
to go multi-core rather then HT that for anyone in the know, it's
obvious multi-core will be *THE* next up-and-coming technology. Besides,
IBM has been doing multi-core for years on their power-pc line and
they can pretty much blow away the competition. It hasn't been evident
because they've used it internally for the most part and not for
consumer machines. The technology starts to show itself in the most
recent Mac's I think, but it's technology that IBM has had for years.
* more cpu power per watt.
* far easier to scale. For AMD, *trivial* to scale because their
hypertransport technology already works with it, whereas Intel
has to basically hack up something to do multi-core because they
currently depend on external resources to manage MP configurations.
* far easier to manage (symmetric, possible to power down whole cores).
* chip feature sizes are going down and it's far easier and far more
efficient to use all that extra room to plop down more cores rather
then adding more cache or making the existing cpu designs more
On the otherhand, HT is:
* complex (fully integrated into the cpu design).
* not scaleable (you can't plop down four HT's).
* difficult to manage (assymetric, not possible to reduce power
consumption anywhere near as much due to the integration).
* does not work well as cpu designs get more efficient.
* cannot take avantage of the extra die area now available.