DragonFly commits List (threaded) for 2009-05
Re: DragonFly-184.108.40.2064.gc5b83 master sys/platform/pc32/apic mpapic.c sys/platform/pc32/isa clock.c sys/platform/pc64/isa clock.c sys/platform/vkernel/platform systimer.c sys/sys systimer.h
On Tue, May 5, 2009 at 2:07 AM, Hasso Tepper <firstname.lastname@example.org> wrote:
> Matthew Dillon wrote:
>> 450 interrupts/sec sounds ok for an idle system. I'd expect a
>> higher number, actually.
> Yes, but ...
>> I wonder if the load calculations are being messed up by the C3
>> state. The code path for the per-cpu hardclock interrupt has
>> always been fairly sensitive. With the 8254 it was being driven by
>> IPIs. Now it is being driven by an actual interrupt so there might be
>> an issue with how it distinguishes the system state when accounting for
>> the clock tick.
> It seems to be a real load though - applications lag etc.
> And one more thing. With sephe's change it's even worse _without_ lapic.
> The interrupt load is still there and the rate of clock interrupts
> doubles to ~800.
I think it's probably because we always reload one shot timer after
the C3. When using i8254, if the timer interrupt is fired but not
serviced yet, we are going to trigger an immediate interrupt. For
lapic timer, this is necessary, since it stops ticking in C3 mode, for
i8254 this is not necessary. So add another cputimer sleep interface,
like sleep exit?
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